Series comparison

-[Qemu-devel] [PULL 0/9] target-arm queue
+[PULL 00/11] target-arm queue
-ARM bugfixes for rc1...
+target-arm queue: two bug fixes, plus the KVM/SVE patchset,
 which is a new feature but one which was in my pre-softfreeze
 pullreq (it just had to be dropped due to an unexpected test failure.)
+thanks
+-- PMM
-The following changes since commit f291910db61b5812e68f1e76afb3ade41d567bea:
+The following changes since commit b7c9a7f353c0e260519bf735ff0d4aa01e72784b:
-  Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-11-09' into staging (2017-11-13 13:13:12 +0000)
+  Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2019-10-31 15:57:30 +0000)
-are available in the git repository at:
+are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171113
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191101-1
-for you to fetch changes up to d25f2a72272b9ffe0d06710d6217d1169bc2cc7d:
+for you to fetch changes up to d9ae7624b659362cb2bb2b04fee53bf50829ca56:
-  accel/tcg/translate-all: expand cpu_restore_state addr check (2017-11-13 13:55:27 +0000)
+  target/arm: Allow reading flags from FPSCR for M-profile (2019-11-01 08:49:10 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * translate-a64.c: silence gcc5 warning
+ * Support SVE in KVM guests
- * highbank: validate register offset before access
+ * Don't UNDEF on M-profile 'vmrs apsr_nzcv, fpscr'
- * MAINTAINERS: Add entries for Smartfusion2
+ * Update hflags after boot.c modifies CPU state
  * accel/tcg/translate-all: expand cpu_restore_state addr check
    (so usermode insn aborts don't crash with an assertion failure)
  * fix TCG initialization of some Arm boards by allowing them
    to specify min/default number of CPUs to create
 ----------------------------------------------------------------
-Alex Bennée (1):
+Andrew Jones (9):
-      accel/tcg/translate-all: expand cpu_restore_state addr check
+      target/arm/monitor: Introduce qmp_query_cpu_model_expansion
       tests: arm: Introduce cpu feature tests
       target/arm: Allow SVE to be disabled via a CPU property
       target/arm/cpu64: max cpu: Introduce sve<N> properties
       target/arm/kvm64: Add kvm_arch_get/put_sve
       target/arm/kvm64: max cpu: Enable SVE when available
       target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features
       target/arm/cpu64: max cpu: Support sve properties with KVM
       target/arm/kvm: host cpu: Add support for sve<N> properties
-Alistair Francis (2):
+Christophe Lyon (1):
-      xlnx-zynqmp: Properly support the smp command line option
+      target/arm: Allow reading flags from FPSCR for M-profile
       xlnx-zcu102: Add an info message deprecating the EP108
-Emilio G. Cota (4):
+Edgar E. Iglesias (1):
-      arm/translate-a64: mark path as unreachable to eliminate warning
+      hw/arm/boot: Rebuild hflags when modifying CPUState at boot
       qom: move CPUClass.tcg_initialize to a global
       xlnx-zcu102: Specify the max number of CPUs for the EP108
       hw: add .min_cpus and .default_cpus fields to machine_class
-Prasad J Pandit (1):
+ tests/Makefile.include         |   5 +-
-      highbank: validate register offset before access
+ qapi/machine-target.json       |   6 +-
  include/qemu/bitops.h          |   1 +
  target/arm/cpu.h               |  21 ++
  target/arm/kvm_arm.h           |  39 +++
  hw/arm/boot.c                  |   1 +
  target/arm/cpu.c               |  25 +-
  target/arm/cpu64.c             | 364 +++++++++++++++++++++++++--
  target/arm/helper.c            |  10 +-
  target/arm/kvm.c               |  25 +-
  target/arm/kvm32.c             |   6 +-
  target/arm/kvm64.c             | 325 +++++++++++++++++++++---
  target/arm/monitor.c           | 158 ++++++++++++
  target/arm/translate-vfp.inc.c |   5 +-
  tests/arm-cpu-features.c       | 551 +++++++++++++++++++++++++++++++++++++++++
  docs/arm-cpu-features.rst      | 317 ++++++++++++++++++++++++
 files changed, 1795 insertions(+), 64 deletions(-)
  create mode 100644 tests/arm-cpu-features.c
  create mode 100644 docs/arm-cpu-features.rst
-Subbaraya Sundeep (1):
-      MAINTAINERS: Add entries for Smartfusion2
- include/exec/exec-all.h    | 11 ++++++++++
- include/hw/boards.h        |  5 +++++
- include/qom/cpu.h          |  1 -
- accel/tcg/translate-all.c  | 52 ++++++++++++++++++++++++++--------------------
- exec.c                     |  5 +++--
- hw/arm/exynos4_boards.c    | 12 ++++-------
- hw/arm/highbank.c          | 17 +++++++++++++--
- hw/arm/raspi.c             |  2 ++
- hw/arm/xlnx-zcu102.c       |  9 +++++++-
- hw/arm/xlnx-zynqmp.c       | 26 ++++++++++++++---------
- target/arm/translate-a64.c |  2 ++
- vl.c                       | 21 ++++++++++++++++---
- MAINTAINERS                | 17 +++++++++++++++
- qemu-doc.texi              |  7 +++++++
-files changed, 137 insertions(+), 50 deletions(-)

-[Qemu-devel] [PULL 3/9] MAINTAINERS: Add entries for Smartfusion2
+[PULL 01/11] target/arm/monitor: Introduce qmp_query_cpu_model_expansion
-From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+From: Andrew Jones <drjones@redhat.com>
-Voluntarily add myself as maintainer for Smartfusion2
+Add support for the query-cpu-model-expansion QMP command to Arm. We
+do this selectively, only exposing CPU properties which represent
-Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+optional CPU features which the user may want to enable/disable.
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Additionally we restrict the list of queryable cpu models to 'max',
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+'host', or the current type when KVM is in use. And, finally, we only
-Message-id: 1510552520-3566-1-git-send-email-sundeep.lkml@gmail.com
+implement expansion type 'full', as Arm does not yet have a "base"
 CPU type. More details and example queries are described in a new
 document (docs/arm-cpu-features.rst).
 Note, certainly more features may be added to the list of advertised
 features, e.g. 'vfp' and 'neon'. The only requirement is that we can
 detect invalid configurations and emit failures at QMP query time.
 For 'vfp' and 'neon' this will require some refactoring to share a
 validation function between the QMP query and the CPU realize
 functions.
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
 Message-id: 20191031142734.8590-2-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- MAINTAINERS | 17 +++++++++++++++++
+ qapi/machine-target.json  |   6 +-
-file changed, 17 insertions(+)
+ target/arm/monitor.c      | 146 ++++++++++++++++++++++++++++++++++++++
+ docs/arm-cpu-features.rst | 137 +++++++++++++++++++++++++++++++++++
-diff --git a/MAINTAINERS b/MAINTAINERS
+files changed, 286 insertions(+), 3 deletions(-)
  create mode 100644 docs/arm-cpu-features.rst
 diff --git a/qapi/machine-target.json b/qapi/machine-target.json
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/qapi/machine-target.json
-+++ b/MAINTAINERS
++++ b/qapi/machine-target.json
-@@ -XXX,XX +XXX,XX @@ M: Alistair Francis <alistair@alistair23.me>
+@@ -XXX,XX +XXX,XX @@
- S: Maintained
+ ##
- F: hw/arm/netduino2.c
+ { 'struct': 'CpuModelExpansionInfo',
+   'data': { 'model': 'CpuModelInfo' },
-+SmartFusion2
+-  'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
-+M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
++  'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
-+S: Maintained
-+F: hw/arm/msf2-soc.c
+ ##
-+F: hw/misc/msf2-sysreg.c
+ # @query-cpu-model-expansion:
-+F: hw/timer/mss-timer.c
+@@ -XXX,XX +XXX,XX @@
-+F: hw/ssi/mss-spi.c
+ #   query-cpu-model-expansion while using these is not advised.
-+F: include/hw/arm/msf2-soc.h
+ #
-+F: include/hw/misc/msf2-sysreg.h
+ # Some architectures may not support all expansion types. s390x supports
-+F: include/hw/timer/mss-timer.h
+-# "full" and "static".
-+F: include/hw/ssi/mss-spi.h
++# "full" and "static". Arm only supports "full".
-+
+ #
-+Emcraft M2S-FG484
+ # Returns: a CpuModelExpansionInfo. Returns an error if expanding CPU models is
-+M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ #          not supported, if the model cannot be expanded, if the model contains
-+S: Maintained
+@@ -XXX,XX +XXX,XX @@
-+F: hw/arm/msf2-som.c
+   'data': { 'type': 'CpuModelExpansionType',
-+
+             'model': 'CpuModelInfo' },
- CRIS Machines
+   'returns': 'CpuModelExpansionInfo',
- -------------
+-  'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
- Axis Dev88
++  'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
  ##
  # @CpuDefinitionInfo:
 diff --git a/target/arm/monitor.c b/target/arm/monitor.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/monitor.c
 +++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
 +#include "hw/boards.h"
  #include "kvm_arm.h"
 +#include "qapi/error.h"
 +#include "qapi/visitor.h"
 +#include "qapi/qobject-input-visitor.h"
 +#include "qapi/qapi-commands-machine-target.h"
  #include "qapi/qapi-commands-misc-target.h"
 +#include "qapi/qmp/qerror.h"
 +#include "qapi/qmp/qdict.h"
 +#include "qom/qom-qobject.h"
  static GICCapability *gic_cap_new(int version)
  {
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
      return head;
  }
 +
 +/*
 + * These are cpu model features we want to advertise. The order here
 + * matters as this is the order in which qmp_query_cpu_model_expansion
 + * will attempt to set them. If there are dependencies between features,
 + * then the order that considers those dependencies must be used.
 + */
 +static const char *cpu_model_advertised_features[] = {
 +    "aarch64", "pmu",
 +    NULL
 +};
 +
 +CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
 +                                                     CpuModelInfo *model,
 +                                                     Error **errp)
 +{
 +    CpuModelExpansionInfo *expansion_info;
 +    const QDict *qdict_in = NULL;
 +    QDict *qdict_out;
 +    ObjectClass *oc;
 +    Object *obj;
 +    const char *name;
 +    int i;
 +
 +    if (type != CPU_MODEL_EXPANSION_TYPE_FULL) {
 +        error_setg(errp, "The requested expansion type is not supported");
 +        return NULL;
 +    }
 +
 +    if (!kvm_enabled() && !strcmp(model->name, "host")) {
 +        error_setg(errp, "The CPU type '%s' requires KVM", model->name);
 +        return NULL;
 +    }
 +
 +    oc = cpu_class_by_name(TYPE_ARM_CPU, model->name);
 +    if (!oc) {
 +        error_setg(errp, "The CPU type '%s' is not a recognized ARM CPU type",
 +                   model->name);
 +        return NULL;
 +    }
 +
 +    if (kvm_enabled()) {
 +        const char *cpu_type = current_machine->cpu_type;
 +        int len = strlen(cpu_type) - strlen(ARM_CPU_TYPE_SUFFIX);
 +        bool supported = false;
 +
 +        if (!strcmp(model->name, "host") || !strcmp(model->name, "max")) {
 +            /* These are kvmarm's recommended cpu types */
 +            supported = true;
 +        } else if (strlen(model->name) == len &&
 +                   !strncmp(model->name, cpu_type, len)) {
 +            /* KVM is enabled and we're using this type, so it works. */
 +            supported = true;
 +        }
 +        if (!supported) {
 +            error_setg(errp, "We cannot guarantee the CPU type '%s' works "
 +                             "with KVM on this host", model->name);
 +            return NULL;
 +        }
 +    }
 +
 +    if (model->props) {
 +        qdict_in = qobject_to(QDict, model->props);
 +        if (!qdict_in) {
 +            error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");
 +            return NULL;
 +        }
 +    }
 +
 +    obj = object_new(object_class_get_name(oc));
 +
 +    if (qdict_in) {
 +        Visitor *visitor;
 +        Error *err = NULL;
 +
 +        visitor = qobject_input_visitor_new(model->props);
 +        visit_start_struct(visitor, NULL, NULL, 0, &err);
 +        if (err) {
 +            visit_free(visitor);
 +            object_unref(obj);
 +            error_propagate(errp, err);
 +            return NULL;
 +        }
 +
 +        i = 0;
 +        while ((name = cpu_model_advertised_features[i++]) != NULL) {
 +            if (qdict_get(qdict_in, name)) {
 +                object_property_set(obj, visitor, name, &err);
 +                if (err) {
 +                    break;
 +                }
 +            }
 +        }
 +
 +        if (!err) {
 +            visit_check_struct(visitor, &err);
 +        }
 +        visit_end_struct(visitor, NULL);
 +        visit_free(visitor);
 +        if (err) {
 +            object_unref(obj);
 +            error_propagate(errp, err);
 +            return NULL;
 +        }
 +    }
 +
 +    expansion_info = g_new0(CpuModelExpansionInfo, 1);
 +    expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
 +    expansion_info->model->name = g_strdup(model->name);
 +
 +    qdict_out = qdict_new();
 +
 +    i = 0;
 +    while ((name = cpu_model_advertised_features[i++]) != NULL) {
 +        ObjectProperty *prop = object_property_find(obj, name, NULL);
 +        if (prop) {
 +            Error *err = NULL;
 +            QObject *value;
 +
 +            assert(prop->get);
 +            value = object_property_get_qobject(obj, name, &err);
 +            assert(!err);
 +
 +            qdict_put_obj(qdict_out, name, value);
 +        }
 +    }
 +
 +    if (!qdict_size(qdict_out)) {
 +        qobject_unref(qdict_out);
 +    } else {
 +        expansion_info->model->props = QOBJECT(qdict_out);
 +        expansion_info->model->has_props = true;
 +    }
 +
 +    object_unref(obj);
 +
 +    return expansion_info;
 +}
 diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@
 +================
 +ARM CPU Features
 +================
 +
 +Examples of probing and using ARM CPU features
 +
 +Introduction
 +============
 +
 +CPU features are optional features that a CPU of supporting type may
 +choose to implement or not.  In QEMU, optional CPU features have
 +corresponding boolean CPU proprieties that, when enabled, indicate
 +that the feature is implemented, and, conversely, when disabled,
 +indicate that it is not implemented. An example of an ARM CPU feature
 +is the Performance Monitoring Unit (PMU).  CPU types such as the
 +Cortex-A15 and the Cortex-A57, which respectively implement ARM
 +architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
 +implement PMUs.  For example, if a user wants to use a Cortex-A15 without
 +a PMU, then the `-cpu` parameter should contain `pmu=off` on the QEMU
 +command line, i.e. `-cpu cortex-a15,pmu=off`.
 +
 +As not all CPU types support all optional CPU features, then whether or
 +not a CPU property exists depends on the CPU type.  For example, CPUs
 +that implement the ARMv8-A architecture reference manual may optionally
 +support the AArch32 CPU feature, which may be enabled by disabling the
 +`aarch64` CPU property.  A CPU type such as the Cortex-A15, which does
 +not implement ARMv8-A, will not have the `aarch64` CPU property.
 +
 +QEMU's support may be limited for some CPU features, only partially
 +supporting the feature or only supporting the feature under certain
 +configurations.  For example, the `aarch64` CPU feature, which, when
 +disabled, enables the optional AArch32 CPU feature, is only supported
 +when using the KVM accelerator and when running on a host CPU type that
 +supports the feature.
 +
 +CPU Feature Probing
 +===================
 +
 +Determining which CPU features are available and functional for a given
 +CPU type is possible with the `query-cpu-model-expansion` QMP command.
 +Below are some examples where `scripts/qmp/qmp-shell` (see the top comment
 +block in the script for usage) is used to issue the QMP commands.
 +
 +(1) Determine which CPU features are available for the `max` CPU type
 +    (Note, we started QEMU with qemu-system-aarch64, so `max` is
 +     implementing the ARMv8-A reference manual in this case)::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
 +      { "return": {
 +        "model": { "name": "max", "props": {
 +        "pmu": true, "aarch64": true
 +      }}}}
 +
 +We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
 +We also see that the CPU features are enabled, as they are all `true`.
 +
 +(2) Let's try to disable the PMU::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
 +      { "return": {
 +        "model": { "name": "max", "props": {
 +        "pmu": false, "aarch64": true
 +      }}}}
 +
 +We see it worked, as `pmu` is now `false`.
 +
 +(3) Let's try to disable `aarch64`, which enables the AArch32 CPU feature::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"aarch64":false}}
 +      {"error": {
 +       "class": "GenericError", "desc":
 +       "'aarch64' feature cannot be disabled unless KVM is enabled and 32-bit EL1 is supported"
 +      }}
 +
 +It looks like this feature is limited to a configuration we do not
 +currently have.
 +
 +(4) Let's try probing CPU features for the Cortex-A15 CPU type::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
 +      {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
 +
 +Only the `pmu` CPU feature is available.
 +
 +A note about CPU feature dependencies
 +-------------------------------------
 +
 +It's possible for features to have dependencies on other features. I.e.
 +it may be possible to change one feature at a time without error, but
 +when attempting to change all features at once an error could occur
 +depending on the order they are processed.  It's also possible changing
 +all at once doesn't generate an error, because a feature's dependencies
 +are satisfied with other features, but the same feature cannot be changed
 +independently without error.  For these reasons callers should always
 +attempt to make their desired changes all at once in order to ensure the
 +collection is valid.
 +
 +A note about CPU models and KVM
 +-------------------------------
 +
 +Named CPU models generally do not work with KVM.  There are a few cases
 +that do work, e.g. using the named CPU model `cortex-a57` with KVM on a
 +seattle host, but mostly if KVM is enabled the `host` CPU type must be
 +used.  This means the guest is provided all the same CPU features as the
 +host CPU type has.  And, for this reason, the `host` CPU type should
 +enable all CPU features that the host has by default.  Indeed it's even
 +a bit strange to allow disabling CPU features that the host has when using
 +the `host` CPU type, but in the absence of CPU models it's the best we can
 +do if we want to launch guests without all the host's CPU features enabled.
 +
 +Enabling KVM also affects the `query-cpu-model-expansion` QMP command.  The
 +affect is not only limited to specific features, as pointed out in example
 +(3) of "CPU Feature Probing", but also to which CPU types may be expanded.
 +When KVM is enabled, only the `max`, `host`, and current CPU type may be
 +expanded.  This restriction is necessary as it's not possible to know all
 +CPU types that may work with KVM, but it does impose a small risk of users
 +experiencing unexpected errors.  For example on a seattle, as mentioned
 +above, the `cortex-a57` CPU type is also valid when KVM is enabled.
 +Therefore a user could use the `host` CPU type for the current type, but
 +then attempt to query `cortex-a57`, however that query will fail with our
 +restrictions.  This shouldn't be an issue though as management layers and
 +users have been preferring the `host` CPU type for use with KVM for quite
 +some time.  Additionally, if the KVM-enabled QEMU instance running on a
 +seattle host is using the `cortex-a57` CPU type, then querying `cortex-a57`
 +will work.
 +
 +Using CPU Features
 +==================
 +
 +After determining which CPU features are available and supported for a
 +given CPU type, then they may be selectively enabled or disabled on the
 +QEMU command line with that CPU type::
 +
 +  $ qemu-system-aarch64 -M virt -cpu max,pmu=off
 +
 +The example above disables the PMU for the `max` CPU type.
 +
 --
-.7.4
+.20.1

-New patch
+[PULL 02/11] tests: arm: Introduce cpu feature tests
+From: Andrew Jones <drjones@redhat.com>
 Now that Arm CPUs have advertised features lets add tests to ensure
 we maintain their expected availability with and without KVM.
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20191031142734.8590-3-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/Makefile.include   |   5 +-
  tests/arm-cpu-features.c | 253 +++++++++++++++++++++++++++++++++++++++
 files changed, 257 insertions(+), 1 deletion(-)
  create mode 100644 tests/arm-cpu-features.c
 diff --git a/tests/Makefile.include b/tests/Makefile.include
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/Makefile.include
 +++ b/tests/Makefile.include
@@ -XXX,XX +XXX,XX @@ check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
  check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
  check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
 +check-qtest-arm-y += tests/arm-cpu-features$(EXESUF)
  check-qtest-arm-y += tests/microbit-test$(EXESUF)
  check-qtest-arm-y += tests/m25p80-test$(EXESUF)
  check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
@@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
  check-qtest-arm-y += tests/hexloader-test$(EXESUF)
  check-qtest-arm-$(CONFIG_PFLASH_CFI02) += tests/pflash-cfi02-test$(EXESUF)
 -check-qtest-aarch64-y = tests/numa-test$(EXESUF)
 +check-qtest-aarch64-y += tests/arm-cpu-features$(EXESUF)
 +check-qtest-aarch64-y += tests/numa-test$(EXESUF)
  check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF)
  check-qtest-aarch64-y += tests/migration-test$(EXESUF)
  # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional
@@ -XXX,XX +XXX,XX @@ tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y)
  tests/numa-test$(EXESUF): tests/numa-test.o
  tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o
  tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y)
 +tests/arm-cpu-features$(EXESUF): tests/arm-cpu-features.o
  tests/migration/stress$(EXESUF): tests/migration/stress.o
      $(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@")
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Arm CPU feature test cases
 + *
 + * Copyright (c) 2019 Red Hat Inc.
 + * Authors:
 + *  Andrew Jones <drjones@redhat.com>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +#include "qemu/osdep.h"
 +#include "libqtest.h"
 +#include "qapi/qmp/qdict.h"
 +#include "qapi/qmp/qjson.h"
 +
 +#define MACHINE     "-machine virt,gic-version=max,accel=tcg "
 +#define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
 +#define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
 +                    "  'arguments': { 'type': 'full', "
 +#define QUERY_TAIL  "}}"
 +
 +static bool kvm_enabled(QTestState *qts)
 +{
 +    QDict *resp, *qdict;
 +    bool enabled;
 +
 +    resp = qtest_qmp(qts, "{ 'execute': 'query-kvm' }");
 +    g_assert(qdict_haskey(resp, "return"));
 +    qdict = qdict_get_qdict(resp, "return");
 +    g_assert(qdict_haskey(qdict, "enabled"));
 +    enabled = qdict_get_bool(qdict, "enabled");
 +    qobject_unref(resp);
 +
 +    return enabled;
 +}
 +
 +static QDict *do_query_no_props(QTestState *qts, const char *cpu_type)
 +{
 +    return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }"
 +                          QUERY_TAIL, cpu_type);
 +}
 +
 +static QDict *do_query(QTestState *qts, const char *cpu_type,
 +                       const char *fmt, ...)
 +{
 +    QDict *resp;
 +
 +    if (fmt) {
 +        QDict *args;
 +        va_list ap;
 +
 +        va_start(ap, fmt);
 +        args = qdict_from_vjsonf_nofail(fmt, ap);
 +        va_end(ap);
 +
 +        resp = qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s, "
 +                                                    "'props': %p }"
 +                              QUERY_TAIL, cpu_type, args);
 +    } else {
 +        resp = do_query_no_props(qts, cpu_type);
 +    }
 +
 +    return resp;
 +}
 +
 +static const char *resp_get_error(QDict *resp)
 +{
 +    QDict *qdict;
 +
 +    g_assert(resp);
 +
 +    qdict = qdict_get_qdict(resp, "error");
 +    if (qdict) {
 +        return qdict_get_str(qdict, "desc");
 +    }
 +
 +    return NULL;
 +}
 +
 +#define assert_error(qts, cpu_type, expected_error, fmt, ...)          \
 +({                                                                     \
 +    QDict *_resp;                                                      \
 +    const char *_error;                                                \
 +                                                                       \
 +    _resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__);               \
 +    g_assert(_resp);                                                   \
 +    _error = resp_get_error(_resp);                                    \
 +    g_assert(_error);                                                  \
 +    g_assert(g_str_equal(_error, expected_error));                     \
 +    qobject_unref(_resp);                                              \
 +})
 +
 +static bool resp_has_props(QDict *resp)
 +{
 +    QDict *qdict;
 +
 +    g_assert(resp);
 +
 +    if (!qdict_haskey(resp, "return")) {
 +        return false;
 +    }
 +    qdict = qdict_get_qdict(resp, "return");
 +
 +    if (!qdict_haskey(qdict, "model")) {
 +        return false;
 +    }
 +    qdict = qdict_get_qdict(qdict, "model");
 +
 +    return qdict_haskey(qdict, "props");
 +}
 +
 +static QDict *resp_get_props(QDict *resp)
 +{
 +    QDict *qdict;
 +
 +    g_assert(resp);
 +    g_assert(resp_has_props(resp));
 +
 +    qdict = qdict_get_qdict(resp, "return");
 +    qdict = qdict_get_qdict(qdict, "model");
 +    qdict = qdict_get_qdict(qdict, "props");
 +
 +    return qdict;
 +}
 +
 +#define assert_has_feature(qts, cpu_type, feature)                     \
 +({                                                                     \
 +    QDict *_resp = do_query_no_props(qts, cpu_type);                   \
 +    g_assert(_resp);                                                   \
 +    g_assert(resp_has_props(_resp));                                   \
 +    g_assert(qdict_get(resp_get_props(_resp), feature));               \
 +    qobject_unref(_resp);                                              \
 +})
 +
 +#define assert_has_not_feature(qts, cpu_type, feature)                 \
 +({                                                                     \
 +    QDict *_resp = do_query_no_props(qts, cpu_type);                   \
 +    g_assert(_resp);                                                   \
 +    g_assert(!resp_has_props(_resp) ||                                 \
 +             !qdict_get(resp_get_props(_resp), feature));              \
 +    qobject_unref(_resp);                                              \
 +})
 +
 +static void assert_type_full(QTestState *qts)
 +{
 +    const char *error;
 +    QDict *resp;
 +
 +    resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
 +                            "'arguments': { 'type': 'static', "
 +                                           "'model': { 'name': 'foo' }}}");
 +    g_assert(resp);
 +    error = resp_get_error(resp);
 +    g_assert(error);
 +    g_assert(g_str_equal(error,
 +                         "The requested expansion type is not supported"));
 +    qobject_unref(resp);
 +}
 +
 +static void assert_bad_props(QTestState *qts, const char *cpu_type)
 +{
 +    const char *error;
 +    QDict *resp;
 +
 +    resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
 +                            "'arguments': { 'type': 'full', "
 +                                           "'model': { 'name': %s, "
 +                                                      "'props': false }}}",
 +                     cpu_type);
 +    g_assert(resp);
 +    error = resp_get_error(resp);
 +    g_assert(error);
 +    g_assert(g_str_equal(error,
 +                         "Invalid parameter type for 'props', expected: dict"));
 +    qobject_unref(resp);
 +}
 +
 +static void test_query_cpu_model_expansion(const void *data)
 +{
 +    QTestState *qts;
 +
 +    qts = qtest_init(MACHINE "-cpu max");
 +
 +    /* Test common query-cpu-model-expansion input validation */
 +    assert_type_full(qts);
 +    assert_bad_props(qts, "max");
 +    assert_error(qts, "foo", "The CPU type 'foo' is not a recognized "
 +                 "ARM CPU type", NULL);
 +    assert_error(qts, "max", "Parameter 'not-a-prop' is unexpected",
 +                 "{ 'not-a-prop': false }");
 +    assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
 +
 +    /* Test expected feature presence/absence for some cpu types */
 +    assert_has_feature(qts, "max", "pmu");
 +    assert_has_feature(qts, "cortex-a15", "pmu");
 +    assert_has_not_feature(qts, "cortex-a15", "aarch64");
 +
 +    if (g_str_equal(qtest_get_arch(), "aarch64")) {
 +        assert_has_feature(qts, "max", "aarch64");
 +        assert_has_feature(qts, "cortex-a57", "pmu");
 +        assert_has_feature(qts, "cortex-a57", "aarch64");
 +
 +        /* Test that features that depend on KVM generate errors without. */
 +        assert_error(qts, "max",
 +                     "'aarch64' feature cannot be disabled "
 +                     "unless KVM is enabled and 32-bit EL1 "
 +                     "is supported",
 +                     "{ 'aarch64': false }");
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +static void test_query_cpu_model_expansion_kvm(const void *data)
 +{
 +    QTestState *qts;
 +
 +    qts = qtest_init(MACHINE_KVM "-cpu max");
 +
 +    /*
 +     * These tests target the 'host' CPU type, so KVM must be enabled.
 +     */
 +    if (!kvm_enabled(qts)) {
 +        qtest_quit(qts);
 +        return;
 +    }
 +
 +    if (g_str_equal(qtest_get_arch(), "aarch64")) {
 +        assert_has_feature(qts, "host", "aarch64");
 +        assert_has_feature(qts, "host", "pmu");
 +
 +        assert_error(qts, "cortex-a15",
 +            "We cannot guarantee the CPU type 'cortex-a15' works "
 +            "with KVM on this host", NULL);
 +    } else {
 +        assert_has_not_feature(qts, "host", "aarch64");
 +        assert_has_not_feature(qts, "host", "pmu");
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +int main(int argc, char **argv)
 +{
 +    g_test_init(&argc, &argv, NULL);
 +
 +    qtest_add_data_func("/arm/query-cpu-model-expansion",
 +                        NULL, test_query_cpu_model_expansion);
 +    qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
 +                        NULL, test_query_cpu_model_expansion_kvm);
 +
 +    return g_test_run();
 +}
 --
 .20.1

-[Qemu-devel] [PULL 5/9] xlnx-zynqmp: Properly support the smp command line option
+[PULL 03/11] target/arm: Allow SVE to be disabled via a CPU property
-From: Alistair Francis <alistair.francis@xilinx.com>
+From: Andrew Jones <drjones@redhat.com>
-Allow the -smp command line option to control the number of CPUs we
+Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via
-create.
+a CPU property") we can disable the 'max' cpu model's VFP and neon
 features, but there's no way to disable SVE. Add the 'sve=on|off'
 property to give it that flexibility. We also rename
 cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them
 to follow the typical *_get/set_<property-name> pattern.
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Emilio G. Cota <cota@braap.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Tested-by: Emilio G. Cota <cota@braap.org>
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
-Message-id: 1510343626-25861-3-git-send-email-cota@braap.org
+Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
 Message-id: 20191031142734.8590-4-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-zcu102.c |  3 ++-
+ target/arm/cpu.c         |  3 ++-
- hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++----------
+ target/arm/cpu64.c       | 52 ++++++++++++++++++++++++++++++++++------
-files changed, 18 insertions(+), 11 deletions(-)
+ target/arm/monitor.c     |  2 +-
  tests/arm-cpu-features.c |  1 +
 files changed, 49 insertions(+), 9 deletions(-)
-diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-zcu102.c
+--- a/target/arm/cpu.c
-+++ b/hw/arm/xlnx-zcu102.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
          env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
          env->cp15.cptr_el[3] |= CPTR_EZ;
          /* with maximum vector length */
 -        env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
 +        env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
 +                             cpu->sve_max_vq - 1 : 0;
          env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
          env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
          /*
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
  }
 -static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
 -                               void *opaque, Error **errp)
 +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
 +                                   void *opaque, Error **errp)
  {
-     MachineClass *mc = MACHINE_CLASS(oc);
+     ARMCPU *cpu = ARM_CPU(obj);
+-    visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
--    mc->desc = "Xilinx ZynqMP ZCU102 board";
++    uint32_t value;
-+    mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5s based on " \
++
-+               "the value of smp";
++    /* All vector lengths are disabled when SVE is off. */
-     mc->init = xlnx_zcu102_init;
++    if (!cpu_isar_feature(aa64_sve, cpu)) {
-     mc->block_default_type = IF_IDE;
++        value = 0;
-     mc->units_per_default_bus = 1;
++    } else {
-diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
++        value = cpu->sve_max_vq;
-index XXXXXXX..XXXXXXX 100644
++    }
---- a/hw/arm/xlnx-zynqmp.c
++    visit_type_uint32(v, name, &value, errp);
-+++ b/hw/arm/xlnx-zynqmp.c
+ }
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
 -static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
 -                               void *opaque, Error **errp)
 +static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
 +                                   void *opaque, Error **errp)
  {
+     ARMCPU *cpu = ARM_CPU(obj);
      Error *err = NULL;
-     int i;
+@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
-+    int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
+     error_propagate(errp, err);
+ }
--    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
-+    for (i = 0; i < num_rpus; i++) {
++static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
-         char *name;
++                            void *opaque, Error **errp)
++{
-         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
++    ARMCPU *cpu = ARM_CPU(obj);
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
++    bool value = cpu_isar_feature(aa64_sve, cpu);
  {
      XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
      int i;
 +    int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 -    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 +    for (i = 0; i < num_apus; i++) {
          object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
                            "cortex-a53-" TYPE_ARM_CPU);
          object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
      MemoryRegion *system_memory = get_system_memory();
      uint8_t i;
      uint64_t ram_size;
 +    int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
      const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
      ram_addr_t ddr_low_size, ddr_high_size;
      qemu_irq gic_spi[GIC_NUM_SPI_INTR];
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
      qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
      qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 -    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
 +    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
      /* Realize APUs before realizing the GIC. KVM requires this.  */
 -    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 +    for (i = 0; i < num_apus; i++) {
          char *name;
          object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
          }
      }
 -    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
 +    for (i = 0; i < num_apus; i++) {
          qemu_irq irq;
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
      }
      if (s->has_rpu) {
 -        xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
 -        if (err) {
 -            error_propagate(errp, err);
 -            return;
 -        }
 +        info_report("The 'has_rpu' property is no longer required, to use the "
 +                    "RPUs just use -smp 6.");
 +    }
 +
-+    xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
++    visit_type_bool(v, name, &value, errp);
 +}
 +
 +static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
 +                            void *opaque, Error **errp)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +    Error *err = NULL;
 +    bool value;
 +    uint64_t t;
 +
 +    visit_type_bool(v, name, &value, &err);
 +    if (err) {
 +        error_propagate(errp, err);
 +        return;
++    }
++
++    t = cpu->isar.id_aa64pfr0;
++    t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
++    cpu->isar.id_aa64pfr0 = t;
++}
++
+ /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
+  * otherwise, a CPU with as many features enabled as our emulation supports.
+  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+ #endif
+         cpu->sve_max_vq = ARM_MAX_VQ;
+-        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
+-                            cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
++        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
++                            cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
++        object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
++                            cpu_arm_set_sve, NULL, NULL, &error_fatal);
      }
+ }
-     if (!s->boot_cpu_ptr) {
 diff --git a/target/arm/monitor.c b/target/arm/monitor.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/monitor.c
 +++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
   * then the order that considers those dependencies must be used.
   */
  static const char *cpu_model_advertised_features[] = {
 -    "aarch64", "pmu",
 +    "aarch64", "pmu", "sve",
      NULL
  };
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/arm-cpu-features.c
 +++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
      if (g_str_equal(qtest_get_arch(), "aarch64")) {
          assert_has_feature(qts, "max", "aarch64");
 +        assert_has_feature(qts, "max", "sve");
          assert_has_feature(qts, "cortex-a57", "pmu");
          assert_has_feature(qts, "cortex-a57", "aarch64");
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 4/9] qom: move CPUClass.tcg_initialize to a global
+[PULL 04/11] target/arm/cpu64: max cpu: Introduce sve<N> properties
-From: "Emilio G. Cota" <cota@braap.org>
+From: Andrew Jones <drjones@redhat.com>
-c3cee ("qom: Introduce CPUClass.tcg_initialize", 2017-10-24)
+Introduce cpu properties to give fine control over SVE vector lengths.
-introduces a per-CPUClass bool that we check so that the target CPU
+We introduce a property for each valid length up to the current
-is initialized for TCG only once. This works well except when
+maximum supported, which is 2048-bits. The properties are named, e.g.
-we end up creating more than one CPUClass, in which case we end
+sve128, sve256, sve384, sve512, ..., where the number is the number of
-up incorrectly initializing TCG more than once, i.e. once for
+bits. See the updates to docs/arm-cpu-features.rst for a description
-each CPUClass.
+of the semantics and for example uses.
-This can be replicated with:
+Note, as sve-max-vq is still present and we'd like to be able to
-  $ aarch64-softmmu/qemu-system-aarch64 -machine xlnx-zcu102 -smp 6 \
+support qmp_query_cpu_model_expansion with guests launched with e.g.
-      -global driver=xlnx,,zynqmp,property=has_rpu,value=on
+-cpu max,sve-max-vq=8 on their command lines, then we do allow
-In this case the class name of the "RPUs" is prefixed by "cortex-r5-",
+sve-max-vq and sve<N> properties to be provided at the same time, but
-whereas the "regular" CPUs are prefixed by "cortex-a53-". This
+this is not recommended, and is why sve-max-vq is not mentioned in the
-results in two CPUClass instances being created.
+document.  If sve-max-vq is provided then it enables all lengths smaller
 than and including the max and disables all lengths larger. It also has
 the side-effect that no larger lengths may be enabled and that the max
 itself cannot be disabled. Smaller non-power-of-two lengths may,
 however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
 guest the vector lengths 128, 256, and 512 bits.
-Fix it by introducing a static variable, so that only the first
+This patch has been co-authored with Richard Henderson, who reworked
-target CPU being initialized will initialize the target-dependent
+the target/arm/cpu64.c changes in order to push all the validation and
-part of TCG, regardless of CPUClass instances.
+auto-enabling/disabling steps into the finalizer, resulting in a nice
 LOC reduction.
-Fixes: 55c3ceef61fcf06fc98ddc752b7cce788ce7680b
+Signed-off-by: Andrew Jones <drjones@redhat.com>
 Signed-off-by: Emilio G. Cota <cota@braap.org>
 Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Alistair Francis <alistair.francis@xilinx.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 1510343626-25861-2-git-send-email-cota@braap.org
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
 Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
 Message-id: 20191031142734.8590-5-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/qom/cpu.h | 1 -
+ include/qemu/bitops.h     |   1 +
- exec.c            | 5 +++--
+ target/arm/cpu.h          |  19 ++++
-files changed, 3 insertions(+), 3 deletions(-)
+ target/arm/cpu.c          |  19 ++++
  target/arm/cpu64.c        | 192 ++++++++++++++++++++++++++++++++++++-
  target/arm/helper.c       |  10 +-
  target/arm/monitor.c      |  12 +++
  tests/arm-cpu-features.c  | 194 ++++++++++++++++++++++++++++++++++++++
  docs/arm-cpu-features.rst | 168 +++++++++++++++++++++++++++++++--
 files changed, 606 insertions(+), 9 deletions(-)
-diff --git a/include/qom/cpu.h b/include/qom/cpu.h
+diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/qom/cpu.h
+--- a/include/qemu/bitops.h
-+++ b/include/qom/cpu.h
++++ b/include/qemu/bitops.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
+@@ -XXX,XX +XXX,XX @@
-     /* Keep non-pointer data at the end to minimize holes.  */
+ #define BITS_PER_LONG           (sizeof (unsigned long) * BITS_PER_BYTE)
-     int gdb_num_core_regs;
-     bool gdb_stop_before_watchpoint;
+ #define BIT(nr)                 (1UL << (nr))
--    bool tcg_initialized;
++#define BIT_ULL(nr)             (1ULL << (nr))
- } CPUClass;
+ #define BIT_MASK(nr)            (1UL << ((nr) % BITS_PER_LONG))
+ #define BIT_WORD(nr)            ((nr) / BITS_PER_LONG)
- #ifdef HOST_WORDS_BIGENDIAN
+ #define BITS_TO_LONGS(nr)       DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
-diff --git a/exec.c b/exec.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/exec.c
+--- a/target/arm/cpu.h
-+++ b/exec.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ void cpu_exec_initfn(CPUState *cpu)
+@@ -XXX,XX +XXX,XX @@ typedef struct {
- void cpu_exec_realizefn(CPUState *cpu, Error **errp)
  #ifdef TARGET_AARCH64
  # define ARM_MAX_VQ    16
 +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 +uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
  #else
  # define ARM_MAX_VQ    1
 +static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
 +static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
 +{ return 0; }
  #endif
  typedef struct ARMVectorReg {
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
      /* Used to set the maximum vector length the cpu will support.  */
      uint32_t sve_max_vq;
 +
 +    /*
 +     * In sve_vq_map each set bit is a supported vector length of
 +     * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
 +     * length in quadwords.
 +     *
 +     * While processing properties during initialization, corresponding
 +     * sve_vq_init bits are set for bits in sve_vq_map that have been
 +     * set by properties.
 +     */
 +    DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
 +    DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
  };
  void arm_cpu_post_init(Object *obj);
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
      return (env->features & (1ULL << feature)) != 0;
  }
 +void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
 +
  #if !defined(CONFIG_USER_ONLY)
  /* Return true if exception levels below EL3 are in secure state,
   * or would be following an exception return to that level.
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
  #endif
  }
 +void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
 +{
 +    Error *local_err = NULL;
 +
 +    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +        arm_cpu_sve_finalize(cpu, &local_err);
 +        if (local_err != NULL) {
 +            error_propagate(errp, local_err);
 +            return;
 +        }
 +    }
 +}
 +
  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
  {
-     CPUClass *cc = CPU_GET_CLASS(cpu);
+     CPUState *cs = CPU(dev);
-+    static bool tcg_target_initialized;
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+         return;
      cpu_list_add(cpu);
 -    if (tcg_enabled() && !cc->tcg_initialized) {
 -        cc->tcg_initialized = true;
 +    if (tcg_enabled() && !tcg_target_initialized) {
 +        tcg_target_initialized = true;
          cc->tcg_initialize();
      }
++    arm_cpu_finalize_features(cpu, &local_err);
++    if (local_err != NULL) {
++        error_propagate(errp, local_err);
++        return;
++    }
++
+     if (arm_feature(env, ARM_FEATURE_AARCH64) &&
+         cpu->has_vfp != cpu->has_neon) {
+         /*
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu64.c
++++ b/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
+     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+ }
++void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
++{
++    /*
++     * If any vector lengths are explicitly enabled with sve<N> properties,
++     * then all other lengths are implicitly disabled.  If sve-max-vq is
++     * specified then it is the same as explicitly enabling all lengths
++     * up to and including the specified maximum, which means all larger
++     * lengths will be implicitly disabled.  If no sve<N> properties
++     * are enabled and sve-max-vq is not specified, then all lengths not
++     * explicitly disabled will be enabled.  Additionally, all power-of-two
++     * vector lengths less than the maximum enabled length will be
++     * automatically enabled and all vector lengths larger than the largest
++     * disabled power-of-two vector length will be automatically disabled.
++     * Errors are generated if the user provided input that interferes with
++     * any of the above.  Finally, if SVE is not disabled, then at least one
++     * vector length must be enabled.
++     */
++    DECLARE_BITMAP(tmp, ARM_MAX_VQ);
++    uint32_t vq, max_vq = 0;
++
++    /*
++     * Process explicit sve<N> properties.
++     * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
++     * Check first for any sve<N> enabled.
++     */
++    if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) {
++        max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1;
++
++        if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
++            error_setg(errp, "cannot enable sve%d", max_vq * 128);
++            error_append_hint(errp, "sve%d is larger than the maximum vector "
++                              "length, sve-max-vq=%d (%d bits)\n",
++                              max_vq * 128, cpu->sve_max_vq,
++                              cpu->sve_max_vq * 128);
++            return;
++        }
++
++        /* Propagate enabled bits down through required powers-of-two. */
++        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
++            if (!test_bit(vq - 1, cpu->sve_vq_init)) {
++                set_bit(vq - 1, cpu->sve_vq_map);
++            }
++        }
++    } else if (cpu->sve_max_vq == 0) {
++        /*
++         * No explicit bits enabled, and no implicit bits from sve-max-vq.
++         */
++        if (!cpu_isar_feature(aa64_sve, cpu)) {
++            /* SVE is disabled and so are all vector lengths.  Good. */
++            return;
++        }
++
++        /* Disabling a power-of-two disables all larger lengths. */
++        if (test_bit(0, cpu->sve_vq_init)) {
++            error_setg(errp, "cannot disable sve128");
++            error_append_hint(errp, "Disabling sve128 results in all vector "
++                              "lengths being disabled.\n");
++            error_append_hint(errp, "With SVE enabled, at least one vector "
++                              "length must be enabled.\n");
++            return;
++        }
++        for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
++            if (test_bit(vq - 1, cpu->sve_vq_init)) {
++                break;
++            }
++        }
++        max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
++
++        bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
++        max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
++    }
++
++    /*
++     * Process the sve-max-vq property.
++     * Note that we know from the above that no bit above
++     * sve-max-vq is currently set.
++     */
++    if (cpu->sve_max_vq != 0) {
++        max_vq = cpu->sve_max_vq;
++
++        if (!test_bit(max_vq - 1, cpu->sve_vq_map) &&
++            test_bit(max_vq - 1, cpu->sve_vq_init)) {
++            error_setg(errp, "cannot disable sve%d", max_vq * 128);
++            error_append_hint(errp, "The maximum vector length must be "
++                              "enabled, sve-max-vq=%d (%d bits)\n",
++                              max_vq, max_vq * 128);
++            return;
++        }
++
++        /* Set all bits not explicitly set within sve-max-vq. */
++        bitmap_complement(tmp, cpu->sve_vq_init, max_vq);
++        bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
++    }
++
++    /*
++     * We should know what max-vq is now.  Also, as we're done
++     * manipulating sve-vq-map, we ensure any bits above max-vq
++     * are clear, just in case anybody looks.
++     */
++    assert(max_vq != 0);
++    bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
++
++    /* Ensure all required powers-of-two are enabled. */
++    for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
++        if (!test_bit(vq - 1, cpu->sve_vq_map)) {
++            error_setg(errp, "cannot disable sve%d", vq * 128);
++            error_append_hint(errp, "sve%d is required as it "
++                              "is a power-of-two length smaller than "
++                              "the maximum, sve%d\n",
++                              vq * 128, max_vq * 128);
++            return;
++        }
++    }
++
++    /*
++     * Now that we validated all our vector lengths, the only question
++     * left to answer is if we even want SVE at all.
++     */
++    if (!cpu_isar_feature(aa64_sve, cpu)) {
++        error_setg(errp, "cannot enable sve%d", max_vq * 128);
++        error_append_hint(errp, "SVE must be enabled to enable vector "
++                          "lengths.\n");
++        error_append_hint(errp, "Add sve=on to the CPU property list.\n");
++        return;
++    }
++
++    /* From now on sve_max_vq is the actual maximum supported length. */
++    cpu->sve_max_vq = max_vq;
++}
++
++uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
++{
++    uint32_t bitnum;
++
++    /*
++     * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
++     * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
++     * function always returns the next smaller than the input.
++     */
++    assert(vq && vq <= ARM_MAX_VQ + 1);
++
++    bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
++    return bitnum == vq - 1 ? 0 : bitnum + 1;
++}
++
+ static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
+                                    void *opaque, Error **errp)
+ {
+@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
+     error_propagate(errp, err);
+ }
++static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
++                               void *opaque, Error **errp)
++{
++    ARMCPU *cpu = ARM_CPU(obj);
++    uint32_t vq = atoi(&name[3]) / 128;
++    bool value;
++
++    /* All vector lengths are disabled when SVE is off. */
++    if (!cpu_isar_feature(aa64_sve, cpu)) {
++        value = false;
++    } else {
++        value = test_bit(vq - 1, cpu->sve_vq_map);
++    }
++    visit_type_bool(v, name, &value, errp);
++}
++
++static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
++                               void *opaque, Error **errp)
++{
++    ARMCPU *cpu = ARM_CPU(obj);
++    uint32_t vq = atoi(&name[3]) / 128;
++    Error *err = NULL;
++    bool value;
++
++    visit_type_bool(v, name, &value, &err);
++    if (err) {
++        error_propagate(errp, err);
++        return;
++    }
++
++    if (value) {
++        set_bit(vq - 1, cpu->sve_vq_map);
++    } else {
++        clear_bit(vq - 1, cpu->sve_vq_map);
++    }
++    set_bit(vq - 1, cpu->sve_vq_init);
++}
++
+ static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
+                             void *opaque, Error **errp)
+ {
+@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
+ static void aarch64_max_initfn(Object *obj)
+ {
+     ARMCPU *cpu = ARM_CPU(obj);
++    uint32_t vq;
+     if (kvm_enabled()) {
+         kvm_arm_set_cpu_features_from_host(cpu);
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+         cpu->dcz_blocksize = 7; /*  512 bytes */
+ #endif
+-        cpu->sve_max_vq = ARM_MAX_VQ;
+         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
+                             cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
+         object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
+                             cpu_arm_set_sve, NULL, NULL, &error_fatal);
++
++        for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
++            char name[8];
++            sprintf(name, "sve%d", vq * 128);
++            object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
++                                cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
++        }
+     }
+ }
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
+     return 0;
+ }
++static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
++{
++    uint32_t start_vq = (start_len & 0xf) + 1;
++
++    return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
++}
++
+ /*
+  * Given that SVE is enabled, return the vector length for EL.
+  */
+@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
+     if (arm_feature(env, ARM_FEATURE_EL3)) {
+         zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
+     }
+-    return zcr_len;
++
++    return sve_zcr_get_valid_len(cpu, zcr_len);
+ }
+ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+diff --git a/target/arm/monitor.c b/target/arm/monitor.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/monitor.c
++++ b/target/arm/monitor.c
+@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
+     return head;
+ }
++QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
++
+ /*
+  * These are cpu model features we want to advertise. The order here
+  * matters as this is the order in which qmp_query_cpu_model_expansion
+@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
+  */
+ static const char *cpu_model_advertised_features[] = {
+     "aarch64", "pmu", "sve",
++    "sve128", "sve256", "sve384", "sve512",
++    "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
++    "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
+     NULL
+ };
+@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
+         if (!err) {
+             visit_check_struct(visitor, &err);
+         }
++        if (!err) {
++            arm_cpu_finalize_features(ARM_CPU(obj), &err);
++        }
+         visit_end_struct(visitor, NULL);
+         visit_free(visitor);
+         if (err) {
+@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
+             error_propagate(errp, err);
+             return NULL;
+         }
++    } else {
++        Error *err = NULL;
++        arm_cpu_finalize_features(ARM_CPU(obj), &err);
++        assert(err == NULL);
+     }
+     expansion_info = g_new0(CpuModelExpansionInfo, 1);
+diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/arm-cpu-features.c
++++ b/tests/arm-cpu-features.c
+@@ -XXX,XX +XXX,XX @@
+  * See the COPYING file in the top-level directory.
+  */
+ #include "qemu/osdep.h"
++#include "qemu/bitops.h"
+ #include "libqtest.h"
+ #include "qapi/qmp/qdict.h"
+ #include "qapi/qmp/qjson.h"
++/*
++ * We expect the SVE max-vq to be 16. Also it must be <= 64
++ * for our test code, otherwise 'vls' can't just be a uint64_t.
++ */
++#define SVE_MAX_VQ 16
++
+ #define MACHINE     "-machine virt,gic-version=max,accel=tcg "
+ #define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
+ #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
+@@ -XXX,XX +XXX,XX @@ static void assert_bad_props(QTestState *qts, const char *cpu_type)
+     qobject_unref(resp);
+ }
++static uint64_t resp_get_sve_vls(QDict *resp)
++{
++    QDict *props;
++    const QDictEntry *e;
++    uint64_t vls = 0;
++    int n = 0;
++
++    g_assert(resp);
++    g_assert(resp_has_props(resp));
++
++    props = resp_get_props(resp);
++
++    for (e = qdict_first(props); e; e = qdict_next(props, e)) {
++        if (strlen(e->key) > 3 && !strncmp(e->key, "sve", 3) &&
++            g_ascii_isdigit(e->key[3])) {
++            char *endptr;
++            int bits;
++
++            bits = g_ascii_strtoll(&e->key[3], &endptr, 10);
++            if (!bits || *endptr != '\0') {
++                continue;
++            }
++
++            if (qdict_get_bool(props, e->key)) {
++                vls |= BIT_ULL((bits / 128) - 1);
++            }
++            ++n;
++        }
++    }
++
++    g_assert(n == SVE_MAX_VQ);
++
++    return vls;
++}
++
++#define assert_sve_vls(qts, cpu_type, expected_vls, fmt, ...)          \
++({                                                                     \
++    QDict *_resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__);        \
++    g_assert(_resp);                                                   \
++    g_assert(resp_has_props(_resp));                                   \
++    g_assert(resp_get_sve_vls(_resp) == expected_vls);                 \
++    qobject_unref(_resp);                                              \
++})
++
++static void sve_tests_default(QTestState *qts, const char *cpu_type)
++{
++    /*
++     * With no sve-max-vq or sve<N> properties on the command line
++     * the default is to have all vector lengths enabled. This also
++     * tests that 'sve' is 'on' by default.
++     */
++    assert_sve_vls(qts, cpu_type, BIT_ULL(SVE_MAX_VQ) - 1, NULL);
++
++    /* With SVE off, all vector lengths should also be off. */
++    assert_sve_vls(qts, cpu_type, 0, "{ 'sve': false }");
++
++    /* With SVE on, we must have at least one vector length enabled. */
++    assert_error(qts, cpu_type, "cannot disable sve128", "{ 'sve128': false }");
++
++    /* Basic enable/disable tests. */
++    assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve384': true }");
++    assert_sve_vls(qts, cpu_type, ((BIT_ULL(SVE_MAX_VQ) - 1) & ~BIT_ULL(2)),
++                   "{ 'sve384': false }");
++
++    /*
++     * ---------------------------------------------------------------------
++     *               power-of-two(vq)   all-power-            can      can
++     *                                  of-two(< vq)        enable   disable
++     * ---------------------------------------------------------------------
++     * vq < max_vq      no                MUST*              yes      yes
++     * vq < max_vq      yes               MUST*              yes      no
++     * ---------------------------------------------------------------------
++     * vq == max_vq     n/a               MUST*              yes**    yes**
++     * ---------------------------------------------------------------------
++     * vq > max_vq      n/a               no                 no       yes
++     * vq > max_vq      n/a               yes                yes      yes
++     * ---------------------------------------------------------------------
++     *
++     * [*] "MUST" means this requirement must already be satisfied,
++     *     otherwise 'max_vq' couldn't itself be enabled.
++     *
++     * [**] Not testable with the QMP interface, only with the command line.
++     */
++
++    /* max_vq := 8 */
++    assert_sve_vls(qts, cpu_type, 0x8b, "{ 'sve1024': true }");
++
++    /* max_vq := 8, vq < max_vq, !power-of-two(vq) */
++    assert_sve_vls(qts, cpu_type, 0x8f,
++                   "{ 'sve1024': true, 'sve384': true }");
++    assert_sve_vls(qts, cpu_type, 0x8b,
++                   "{ 'sve1024': true, 'sve384': false }");
++
++    /* max_vq := 8, vq < max_vq, power-of-two(vq) */
++    assert_sve_vls(qts, cpu_type, 0x8b,
++                   "{ 'sve1024': true, 'sve256': true }");
++    assert_error(qts, cpu_type, "cannot disable sve256",
++                 "{ 'sve1024': true, 'sve256': false }");
++
++    /* max_vq := 3, vq > max_vq, !all-power-of-two(< vq) */
++    assert_error(qts, cpu_type, "cannot disable sve512",
++                 "{ 'sve384': true, 'sve512': false, 'sve640': true }");
++
++    /*
++     * We can disable power-of-two vector lengths when all larger lengths
++     * are also disabled. We only need to disable the power-of-two length,
++     * as all non-enabled larger lengths will then be auto-disabled.
++     */
++    assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve512': false }");
++
++    /* max_vq := 3, vq > max_vq, all-power-of-two(< vq) */
++    assert_sve_vls(qts, cpu_type, 0x1f,
++                   "{ 'sve384': true, 'sve512': true, 'sve640': true }");
++    assert_sve_vls(qts, cpu_type, 0xf,
++                   "{ 'sve384': true, 'sve512': true, 'sve640': false }");
++}
++
++static void sve_tests_sve_max_vq_8(const void *data)
++{
++    QTestState *qts;
++
++    qts = qtest_init(MACHINE "-cpu max,sve-max-vq=8");
++
++    assert_sve_vls(qts, "max", BIT_ULL(8) - 1, NULL);
++
++    /*
++     * Disabling the max-vq set by sve-max-vq is not allowed, but
++     * of course enabling it is OK.
++     */
++    assert_error(qts, "max", "cannot disable sve1024", "{ 'sve1024': false }");
++    assert_sve_vls(qts, "max", 0xff, "{ 'sve1024': true }");
++
++    /*
++     * Enabling anything larger than max-vq set by sve-max-vq is not
++     * allowed, but of course disabling everything larger is OK.
++     */
++    assert_error(qts, "max", "cannot enable sve1152", "{ 'sve1152': true }");
++    assert_sve_vls(qts, "max", 0xff, "{ 'sve1152': false }");
++
++    /*
++     * We can enable/disable non power-of-two lengths smaller than the
++     * max-vq set by sve-max-vq, but, while we can enable power-of-two
++     * lengths, we can't disable them.
++     */
++    assert_sve_vls(qts, "max", 0xff, "{ 'sve384': true }");
++    assert_sve_vls(qts, "max", 0xfb, "{ 'sve384': false }");
++    assert_sve_vls(qts, "max", 0xff, "{ 'sve256': true }");
++    assert_error(qts, "max", "cannot disable sve256", "{ 'sve256': false }");
++
++    qtest_quit(qts);
++}
++
++static void sve_tests_sve_off(const void *data)
++{
++    QTestState *qts;
++
++    qts = qtest_init(MACHINE "-cpu max,sve=off");
++
++    /* SVE is off, so the map should be empty. */
++    assert_sve_vls(qts, "max", 0, NULL);
++
++    /* The map stays empty even if we turn lengths off. */
++    assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
++
++    /* It's an error to enable lengths when SVE is off. */
++    assert_error(qts, "max", "cannot enable sve128", "{ 'sve128': true }");
++
++    /* With SVE re-enabled we should get all vector lengths enabled. */
++    assert_sve_vls(qts, "max", BIT_ULL(SVE_MAX_VQ) - 1, "{ 'sve': true }");
++
++    /* Or enable SVE with just specific vector lengths. */
++    assert_sve_vls(qts, "max", 0x3,
++                   "{ 'sve': true, 'sve128': true, 'sve256': true }");
++
++    qtest_quit(qts);
++}
++
+ static void test_query_cpu_model_expansion(const void *data)
+ {
+     QTestState *qts;
+@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
+     if (g_str_equal(qtest_get_arch(), "aarch64")) {
+         assert_has_feature(qts, "max", "aarch64");
+         assert_has_feature(qts, "max", "sve");
++        assert_has_feature(qts, "max", "sve128");
+         assert_has_feature(qts, "cortex-a57", "pmu");
+         assert_has_feature(qts, "cortex-a57", "aarch64");
++        sve_tests_default(qts, "max");
++
+         /* Test that features that depend on KVM generate errors without. */
+         assert_error(qts, "max",
+                      "'aarch64' feature cannot be disabled "
+@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
+     qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
+                         NULL, test_query_cpu_model_expansion_kvm);
++    if (g_str_equal(qtest_get_arch(), "aarch64")) {
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
++                            NULL, sve_tests_sve_max_vq_8);
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
++                            NULL, sve_tests_sve_off);
++    }
++
+     return g_test_run();
+ }
+diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/arm-cpu-features.rst
++++ b/docs/arm-cpu-features.rst
+@@ -XXX,XX +XXX,XX @@ block in the script for usage) is used to issue the QMP commands.
+       (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
+       { "return": {
+         "model": { "name": "max", "props": {
+-        "pmu": true, "aarch64": true
++        "sve1664": true, "pmu": true, "sve1792": true, "sve1920": true,
++        "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
++        "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
++        "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
++        "sve896": true, "sve1280": true, "sve2048": true
+       }}}}
+-We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
+-We also see that the CPU features are enabled, as they are all `true`.
++We see that the `max` CPU type has the `pmu`, `aarch64`, `sve`, and many
++`sve<N>` CPU features.  We also see that all the CPU features are
++enabled, as they are all `true`.  (The `sve<N>` CPU features are all
++optional SVE vector lengths (see "SVE CPU Properties").  While with TCG
++all SVE vector lengths can be supported, when KVM is in use it's more
++likely that only a few lengths will be supported, if SVE is supported at
++all.)
+ (2) Let's try to disable the PMU::
+       (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
+       { "return": {
+         "model": { "name": "max", "props": {
+-        "pmu": false, "aarch64": true
++        "sve1664": true, "pmu": false, "sve1792": true, "sve1920": true,
++        "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
++        "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
++        "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
++        "sve896": true, "sve1280": true, "sve2048": true
+       }}}}
+ We see it worked, as `pmu` is now `false`.
+@@ -XXX,XX +XXX,XX @@ We see it worked, as `pmu` is now `false`.
+ It looks like this feature is limited to a configuration we do not
+ currently have.
+-(4) Let's try probing CPU features for the Cortex-A15 CPU type::
++(4) Let's disable `sve` and see what happens to all the optional SVE
++    vector lengths::
++
++      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"sve":false}}
++      { "return": {
++        "model": { "name": "max", "props": {
++        "sve1664": false, "pmu": true, "sve1792": false, "sve1920": false,
++        "sve128": false, "aarch64": true, "sve1024": false, "sve": false,
++        "sve640": false, "sve768": false, "sve1408": false, "sve256": false,
++        "sve1152": false, "sve512": false, "sve384": false, "sve1536": false,
++        "sve896": false, "sve1280": false, "sve2048": false
++      }}}}
++
++As expected they are now all `false`.
++
++(5) Let's try probing CPU features for the Cortex-A15 CPU type::
+       (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
+       {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
+@@ -XXX,XX +XXX,XX @@ After determining which CPU features are available and supported for a
+ given CPU type, then they may be selectively enabled or disabled on the
+ QEMU command line with that CPU type::
+-  $ qemu-system-aarch64 -M virt -cpu max,pmu=off
++  $ qemu-system-aarch64 -M virt -cpu max,pmu=off,sve=on,sve128=on,sve256=on
+-The example above disables the PMU for the `max` CPU type.
++The example above disables the PMU and enables the first two SVE vector
++lengths for the `max` CPU type.  Note, the `sve=on` isn't actually
++necessary, because, as we observed above with our probe of the `max` CPU
++type, `sve` is already on by default.  Also, based on our probe of
++defaults, it would seem we need to disable many SVE vector lengths, rather
++than only enabling the two we want.  This isn't the case, because, as
++disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU
++properties have special semantics (see "SVE CPU Property Parsing
++Semantics").
++
++SVE CPU Properties
++==================
++
++There are two types of SVE CPU properties: `sve` and `sve<N>`.  The first
++is used to enable or disable the entire SVE feature, just as the `pmu`
++CPU property completely enables or disables the PMU.  The second type
++is used to enable or disable specific vector lengths, where `N` is the
++number of bits of the length.  The `sve<N>` CPU properties have special
++dependencies and constraints, see "SVE CPU Property Dependencies and
++Constraints" below.  Additionally, as we want all supported vector lengths
++to be enabled by default, then, in order to avoid overly verbose command
++lines (command lines full of `sve<N>=off`, for all `N` not wanted), we
++provide the parsing semantics listed in "SVE CPU Property Parsing
++Semantics".
++
++SVE CPU Property Dependencies and Constraints
++---------------------------------------------
++
++  1) At least one vector length must be enabled when `sve` is enabled.
++
++  2) If a vector length `N` is enabled, then all power-of-two vector
++     lengths smaller than `N` must also be enabled.  E.g. if `sve512`
++     is enabled, then the 128-bit and 256-bit vector lengths must also
++     be enabled.
++
++SVE CPU Property Parsing Semantics
++----------------------------------
++
++  1) If SVE is disabled (`sve=off`), then which SVE vector lengths
++     are enabled or disabled is irrelevant to the guest, as the entire
++     SVE feature is disabled and that disables all vector lengths for
++     the guest.  However QEMU will still track any `sve<N>` CPU
++     properties provided by the user.  If later an `sve=on` is provided,
++     then the guest will get only the enabled lengths.  If no `sve=on`
++     is provided and there are explicitly enabled vector lengths, then
++     an error is generated.
++
++  2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
++     provided, then all supported vector lengths are enabled, including
++     the non-power-of-two lengths.
++
++  3) If SVE is enabled, then an error is generated when attempting to
++     disable the last enabled vector length (see constraint (1) of "SVE
++     CPU Property Dependencies and Constraints").
++
++  4) If one or more vector lengths have been explicitly enabled and at
++     at least one of the dependency lengths of the maximum enabled length
++     has been explicitly disabled, then an error is generated (see
++     constraint (2) of "SVE CPU Property Dependencies and Constraints").
++
++  5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
++     CPU properties are set `on`, then the specified vector lengths are
++     disabled but the default for any unspecified lengths remains enabled.
++     Disabling a power-of-two vector length also disables all vector
++     lengths larger than the power-of-two length (see constraint (2) of
++     "SVE CPU Property Dependencies and Constraints").
++
++  6) If one or more `sve<N>` CPU properties are set to `on`, then they
++     are enabled and all unspecified lengths default to disabled, except
++     for the required lengths per constraint (2) of "SVE CPU Property
++     Dependencies and Constraints", which will even be auto-enabled if
++     they were not explicitly enabled.
++
++  7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
++     explicitly disabled (i.e. avoiding the error specified in (3) of
++     "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
++     provided an error will be generated.  To avoid this error, one must
++     enable at least one vector length prior to enabling SVE.
++
++SVE CPU Property Examples
++-------------------------
++
++  1) Disable SVE::
++
++     $ qemu-system-aarch64 -M virt -cpu max,sve=off
++
++  2) Implicitly enable all vector lengths for the `max` CPU type::
++
++     $ qemu-system-aarch64 -M virt -cpu max
++
++  3) Only enable the 128-bit vector length::
++
++     $ qemu-system-aarch64 -M virt -cpu max,sve128=on
++
++  4) Disable the 512-bit vector length and all larger vector lengths,
++     since 512 is a power-of-two.  This results in all the smaller,
++     uninitialized lengths (128, 256, and 384) defaulting to enabled::
++
++     $ qemu-system-aarch64 -M virt -cpu max,sve512=off
++
++  5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
++
++     $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
++
++  6) The same as (5), but since the 128-bit and 256-bit vector
++     lengths are required for the 512-bit vector length to be enabled,
++     then allow them to be auto-enabled::
++
++     $ qemu-system-aarch64 -M virt -cpu max,sve512=on
++
++  7) Do the same as (6), but by first disabling SVE and then re-enabling it::
++
++     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
++
++  8) Force errors regarding the last vector length::
++
++     $ qemu-system-aarch64 -M virt -cpu max,sve128=off
++     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
++
++SVE CPU Property Recommendations
++--------------------------------
++
++The examples in "SVE CPU Property Examples" exhibit many ways to select
++vector lengths which developers may find useful in order to avoid overly
++verbose command lines.  However, the recommended way to select vector
++lengths is to explicitly enable each desired length.  Therefore only
++example's (1), (3), and (5) exhibit recommended uses of the properties.
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 9/9] accel/tcg/translate-all: expand cpu_restore_state addr check
+[PULL 05/11] target/arm/kvm64: Add kvm_arch_get/put_sve
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-We are still seeing signals during translation time when we walk over
+These are the SVE equivalents to kvm_arch_get/put_fpsimd. Note, the
-a page protection boundary. This expands the check to ensure the host
+swabbing is different than it is for fpsmid because the vector format
-PC is inside the code generation buffer. The original suggestion was
+is a little-endian stream of words.
-to check versus tcg_ctx.code_gen_ptr but as we now segment the
-translation buffer we have to settle for just a general check for
+Signed-off-by: Andrew Jones <drjones@redhat.com>
 being inside.
 I've also fixed up the declaration to make it clear it can deal with
 invalid addresses. A later patch will fix up the call sites.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Laurent Vivier <laurent@vivier.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20171108153245.20740-2-alex.bennee@linaro.org
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
-Cc: Richard Henderson <rth@twiddle.net>
+Message-id: 20191031142734.8590-6-drjones@redhat.com
 Tested-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/exec/exec-all.h   | 11 ++++++++++
+ target/arm/kvm64.c | 185 ++++++++++++++++++++++++++++++++++++++-------
- accel/tcg/translate-all.c | 52 ++++++++++++++++++++++++++---------------------
+file changed, 156 insertions(+), 29 deletions(-)
-files changed, 40 insertions(+), 23 deletions(-)
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/exec/exec-all.h
+--- a/target/arm/kvm64.c
-+++ b/include/exec/exec-all.h
++++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_destroy_vcpu(CPUState *cs)
-                           target_ulong *data);
+ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
+ {
- void cpu_gen_init(void);
+     /* Return true if the regidx is a register we should synchronize
-+
+-     * via the cpreg_tuples array (ie is not a core reg we sync by
-+/**
+-     * hand in kvm_arch_get/put_registers())
-+ * cpu_restore_state:
++     * via the cpreg_tuples array (ie is not a core or sve reg that
-+ * @cpu: the vCPU state is to be restore to
++     * we sync by hand in kvm_arch_get/put_registers())
-+ * @searched_pc: the host PC the fault occurred at
+      */
-+ * @return: true if state was restored, false otherwise
+     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
-+ *
+     case KVM_REG_ARM_CORE:
-+ * Attempt to restore the state for a fault occurring in translated
++    case KVM_REG_ARM64_SVE:
-+ * code. If the searched_pc is not in translated code no state is
+         return false;
-+ * restored and the function returns false.
+     default:
          return true;
@@ -XXX,XX +XXX,XX @@ int kvm_arm_cpreg_level(uint64_t regidx)
  static int kvm_arch_put_fpsimd(CPUState *cs)
  {
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    CPUARMState *env = &cpu->env;
 +    CPUARMState *env = &ARM_CPU(cs)->env;
      struct kvm_one_reg reg;
 -    uint32_t fpr;
      int i, ret;
      for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_fpsimd(CPUState *cs)
          }
      }
 -    reg.addr = (uintptr_t)(&fpr);
 -    fpr = vfp_get_fpsr(env);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 -    if (ret) {
 -        return ret;
 +    return 0;
 +}
 +
 +/*
 + * SVE registers are encoded in KVM's memory in an endianness-invariant format.
 + * The byte at offset i from the start of the in-memory representation contains
 + * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
 + * lowest offsets are stored in the lowest memory addresses, then that nearly
 + * matches QEMU's representation, which is to use an array of host-endian
 + * uint64_t's, where the lower offsets are at the lower indices. To complete
 + * the translation we just need to byte swap the uint64_t's on big-endian hosts.
 + */
- bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
++static uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
++{
- void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
++#ifdef HOST_WORDS_BIGENDIAN
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
++    int i;
-index XXXXXXX..XXXXXXX 100644
++
---- a/accel/tcg/translate-all.c
++    for (i = 0; i < nr; ++i) {
-+++ b/accel/tcg/translate-all.c
++        dst[i] = bswap64(src[i]);
-@@ -XXX,XX +XXX,XX @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
+     }
 -    reg.addr = (uintptr_t)(&fpr);
 -    fpr = vfp_get_fpcr(env);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 +    return dst;
 +#else
 +    return src;
 +#endif
 +}
 +
 +/*
 + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
 + * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
 + * code the slice index to zero for now as it's unlikely we'll need more than
 + * one slice for quite some time.
 + */
 +static int kvm_arch_put_sve(CPUState *cs)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +    uint64_t tmp[ARM_MAX_VQ * 2];
 +    uint64_t *r;
 +    struct kvm_one_reg reg;
 +    int n, ret;
 +
 +    for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
 +        r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
 +        reg.addr = (uintptr_t)r;
 +        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
 +        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +        if (ret) {
 +            return ret;
 +        }
 +    }
 +
 +    for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
 +        r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
 +                        DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 +        reg.addr = (uintptr_t)r;
 +        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
 +        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +        if (ret) {
 +            return ret;
 +        }
 +    }
 +
 +    r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
 +                    DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 +    reg.addr = (uintptr_t)r;
 +    reg.id = KVM_REG_ARM64_SVE_FFR(0);
      ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
      if (ret) {
          return ret;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
  {
      struct kvm_one_reg reg;
      uint64_t val;
 +    uint32_t fpr;
      int i, ret;
      unsigned int el;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
          }
      }
 -    ret = kvm_arch_put_fpsimd(cs);
 +    if (cpu_isar_feature(aa64_sve, cpu)) {
 +        ret = kvm_arch_put_sve(cs);
 +    } else {
 +        ret = kvm_arch_put_fpsimd(cs);
 +    }
 +    if (ret) {
 +        return ret;
 +    }
 +
 +    reg.addr = (uintptr_t)(&fpr);
 +    fpr = vfp_get_fpsr(env);
 +    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 +    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    if (ret) {
 +        return ret;
 +    }
 +
 +    reg.addr = (uintptr_t)(&fpr);
 +    fpr = vfp_get_fpcr(env);
 +    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 +    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
  static int kvm_arch_get_fpsimd(CPUState *cs)
  {
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    CPUARMState *env = &cpu->env;
 +    CPUARMState *env = &ARM_CPU(cs)->env;
      struct kvm_one_reg reg;
 -    uint32_t fpr;
      int i, ret;
      for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_fpsimd(CPUState *cs)
          }
      }
 -    reg.addr = (uintptr_t)(&fpr);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 -    if (ret) {
 -        return ret;
 -    }
 -    vfp_set_fpsr(env, fpr);
 +    return 0;
 +}
 -    reg.addr = (uintptr_t)(&fpr);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 +/*
 + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
 + * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
 + * code the slice index to zero for now as it's unlikely we'll need more than
 + * one slice for quite some time.
 + */
 +static int kvm_arch_get_sve(CPUState *cs)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +    struct kvm_one_reg reg;
 +    uint64_t *r;
 +    int n, ret;
 +
 +    for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
 +        r = &env->vfp.zregs[n].d[0];
 +        reg.addr = (uintptr_t)r;
 +        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
 +        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        if (ret) {
 +            return ret;
 +        }
 +        sve_bswap64(r, r, cpu->sve_max_vq * 2);
 +    }
 +
 +    for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
 +        r = &env->vfp.pregs[n].p[0];
 +        reg.addr = (uintptr_t)r;
 +        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
 +        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        if (ret) {
 +            return ret;
 +        }
 +        sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 +    }
 +
 +    r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
 +    reg.addr = (uintptr_t)r;
 +    reg.id = KVM_REG_ARM64_SVE_FFR(0);
      ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
      if (ret) {
          return ret;
      }
 -    vfp_set_fpcr(env, fpr);
 +    sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
      return 0;
  }
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
--bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
+     struct kvm_one_reg reg;
-+bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
+     uint64_t val;
- {
+     unsigned int el;
-     TranslationBlock *tb;
++    uint32_t fpr;
-     bool r = false;
+     int i, ret;
-+    uintptr_t check_offset;
+     ARMCPU *cpu = ARM_CPU(cs);
--    /* A retaddr of zero is invalid so we really shouldn't have ended
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
--     * up here. The target code has likely forgotten to check retaddr
+         env->spsr = env->banked_spsr[i];
--     * != 0 before attempting to restore state. We return early to
+     }
--     * avoid blowing up on a recursive tb_lock(). The target must have
--     * previously survived a failed cpu_restore_state because
+-    ret = kvm_arch_get_fpsimd(cs);
--     * tb_find_pc(0) would have failed anyway. It still should be
++    if (cpu_isar_feature(aa64_sve, cpu)) {
--     * fixed though.
++        ret = kvm_arch_get_sve(cs);
-+    /* The host_pc has to be in the region of current code buffer. If
++    } else {
-+     * it is not we will not be able to resolve it here. The two cases
++        ret = kvm_arch_get_fpsimd(cs);
-+     * where host_pc will not be correct are:
++    }
-+     *
+     if (ret) {
-+     *  - fault during translation (instruction fetch)
+         return ret;
-+     *  - fault from helper (not using GETPC() macro)
+     }
-+     *
-+     * Either way we need return early to avoid blowing up on a
++    reg.addr = (uintptr_t)(&fpr);
-+     * recursive tb_lock() as we can't resolve it here.
++    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
-+     *
++    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
-+     * We are using unsigned arithmetic so if host_pc <
++    if (ret) {
-+     * tcg_init_ctx.code_gen_buffer check_offset will wrap to way
++        return ret;
-+     * above the code_gen_buffer_size
++    }
-      */
++    vfp_set_fpsr(env, fpr);
--
++
--    if (!retaddr) {
++    reg.addr = (uintptr_t)(&fpr);
--        return r;
++    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
--    }
++    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
--
++    if (ret) {
--    tb_lock();
++        return ret;
--    tb = tb_find_pc(retaddr);
++    }
--    if (tb) {
++    vfp_set_fpcr(env, fpr);
--        cpu_restore_state_from_tb(cpu, tb, retaddr);
++
--        if (tb->cflags & CF_NOCACHE) {
+     ret = kvm_get_vcpu_events(cpu);
--            /* one-shot translation, invalidate it immediately */
+     if (ret) {
--            tb_phys_invalidate(tb, -1);
+         return ret;
 -            tb_remove(tb);
 +    check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer;
 +
 +    if (check_offset < tcg_init_ctx.code_gen_buffer_size) {
 +        tb_lock();
 +        tb = tb_find_pc(host_pc);
 +        if (tb) {
 +            cpu_restore_state_from_tb(cpu, tb, host_pc);
 +            if (tb->cflags & CF_NOCACHE) {
 +                /* one-shot translation, invalidate it immediately */
 +                tb_phys_invalidate(tb, -1);
 +                tb_remove(tb);
 +            }
 +            r = true;
          }
 -        r = true;
 +        tb_unlock();
      }
 -    tb_unlock();
      return r;
  }
 --
-.7.4
+.20.1

-New patch
+[PULL 06/11] target/arm/kvm64: max cpu: Enable SVE when available
+From: Andrew Jones <drjones@redhat.com>
 Enable SVE in the KVM guest when the 'max' cpu type is configured
 and KVM supports it. KVM SVE requires use of the new finalize
 vcpu ioctl, so we add that now too. For starters SVE can only be
 turned on or off, getting all vector lengths the host CPU supports
 when on. We'll add the other SVE CPU properties in later patches.
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
 Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
 Message-id: 20191031142734.8590-7-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/kvm_arm.h     | 27 +++++++++++++++++++++++++++
  target/arm/cpu64.c       | 17 ++++++++++++++---
  target/arm/kvm.c         |  5 +++++
  target/arm/kvm64.c       | 20 +++++++++++++++++++-
  tests/arm-cpu-features.c |  4 ++++
 files changed, 69 insertions(+), 4 deletions(-)
 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm_arm.h
 +++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@
   */
  int kvm_arm_vcpu_init(CPUState *cs);
 +/**
 + * kvm_arm_vcpu_finalize
 + * @cs: CPUState
 + * @feature: int
 + *
 + * Finalizes the configuration of the specified VCPU feature by
 + * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring
 + * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of
 + * KVM's API documentation.
 + *
 + * Returns: 0 if success else < 0 error code
 + */
 +int kvm_arm_vcpu_finalize(CPUState *cs, int feature);
 +
  /**
   * kvm_arm_register_device:
   * @mr: memory region for this device
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs);
   */
  bool kvm_arm_pmu_supported(CPUState *cs);
 +/**
 + * bool kvm_arm_sve_supported:
 + * @cs: CPUState
 + *
 + * Returns true if the KVM VCPU can enable SVE and false otherwise.
 + */
 +bool kvm_arm_sve_supported(CPUState *cs);
 +
  /**
   * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
   * IPA address space supported by KVM
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_pmu_supported(CPUState *cs)
      return false;
  }
 +static inline bool kvm_arm_sve_supported(CPUState *cs)
 +{
 +    return false;
 +}
 +
  static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
  {
      return -ENOENT;
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
          return;
      }
 +    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
 +        error_setg(errp, "'sve' feature not supported by KVM on this host");
 +        return;
 +    }
 +
      t = cpu->isar.id_aa64pfr0;
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
      cpu->isar.id_aa64pfr0 = t;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
      uint32_t vq;
 +    uint64_t t;
      if (kvm_enabled()) {
          kvm_arm_set_cpu_features_from_host(cpu);
 +        if (kvm_arm_sve_supported(CPU(cpu))) {
 +            t = cpu->isar.id_aa64pfr0;
 +            t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 +            cpu->isar.id_aa64pfr0 = t;
 +        }
      } else {
 -        uint64_t t;
          uint32_t u;
          aarch64_a57_initfn(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                              cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 -        object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 -                            cpu_arm_set_sve, NULL, NULL, &error_fatal);
          for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
              char name[8];
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
                                  cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
          }
      }
 +
 +    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 +                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
  }
  struct ARMCPUInfo {
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs)
      return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
  }
 +int kvm_arm_vcpu_finalize(CPUState *cs, int feature)
 +{
 +    return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature);
 +}
 +
  void kvm_arm_init_serror_injection(CPUState *cs)
  {
      cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state,
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cpu)
      return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
  }
 +bool kvm_arm_sve_supported(CPUState *cpu)
 +{
 +    KVMState *s = KVM_STATE(current_machine->accelerator);
 +
 +    return kvm_check_extension(s, KVM_CAP_ARM_SVE);
 +}
 +
  #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
  int kvm_arch_init_vcpu(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
          cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
      }
      if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
 -            cpu->has_pmu = false;
 +        cpu->has_pmu = false;
      }
      if (cpu->has_pmu) {
          cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
      } else {
          unset_feature(&env->features, ARM_FEATURE_PMU);
      }
 +    if (cpu_isar_feature(aa64_sve, cpu)) {
 +        assert(kvm_arm_sve_supported(cs));
 +        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
 +    }
      /* Do KVM_ARM_VCPU_INIT ioctl */
      ret = kvm_arm_vcpu_init(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
          return ret;
      }
 +    if (cpu_isar_feature(aa64_sve, cpu)) {
 +        ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
 +        if (ret) {
 +            return ret;
 +        }
 +    }
 +
      /*
       * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
       * Currently KVM has its own idea about MPIDR assignment, so we
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/arm-cpu-features.c
 +++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
          assert_has_feature(qts, "host", "aarch64");
          assert_has_feature(qts, "host", "pmu");
 +        assert_has_feature(qts, "max", "sve");
 +
          assert_error(qts, "cortex-a15",
              "We cannot guarantee the CPU type 'cortex-a15' works "
              "with KVM on this host", NULL);
      } else {
          assert_has_not_feature(qts, "host", "aarch64");
          assert_has_not_feature(qts, "host", "pmu");
 +
 +        assert_has_not_feature(qts, "max", "sve");
      }
      qtest_quit(qts);
 --
 .20.1

-[Qemu-devel] [PULL 1/9] arm/translate-a64: mark path as unreachable to eliminate warning
+[PULL 07/11] target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features
-From: "Emilio G. Cota" <cota@braap.org>
+From: Andrew Jones <drjones@redhat.com>
-Fixes the following warning when compiling with gcc 5.4.0 with -O1
+kvm_arm_create_scratch_host_vcpu() takes a struct kvm_vcpu_init
-optimizations and --enable-debug:
+parameter. Rather than just using it as an output parameter to
 pass back the preferred target, use it also as an input parameter,
 allowing a caller to pass a selected target if they wish and to
 also pass cpu features. If the caller doesn't want to select a
 target they can pass -1 for the target which indicates they want
 to use the preferred target and have it passed back like before.
-target/arm/translate-a64.c: In function ‘aarch64_tr_translate_insn’:
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-target/arm/translate-a64.c:2361:8: error: ‘post_index’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-     if (!post_index) {
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-        ^
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
-target/arm/translate-a64.c:2307:10: note: ‘post_index’ was declared here
+Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
-     bool post_index;
+Message-id: 20191031142734.8590-8-drjones@redhat.com
           ^
 target/arm/translate-a64.c:2386:8: error: ‘writeback’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
      if (writeback) {
         ^
 target/arm/translate-a64.c:2308:10: note: ‘writeback’ was declared here
      bool writeback;
           ^
 Note that idx comes from selecting 2 bits, and therefore its value
 can be at most 3.
 Signed-off-by: Emilio G. Cota <cota@braap.org>
 Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 1510087611-1851-1-git-send-email-cota@braap.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 2 ++
+ target/arm/kvm.c   | 20 +++++++++++++++-----
-file changed, 2 insertions(+)
+ target/arm/kvm32.c |  6 +++++-
  target/arm/kvm64.c |  6 +++++-
 files changed, 25 insertions(+), 7 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/target/arm/kvm.c
-+++ b/target/arm/translate-a64.c
++++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
-         post_index = false;
+                                       int *fdarray,
-         writeback = true;
+                                       struct kvm_vcpu_init *init)
-         break;
+ {
-+    default:
+-    int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
-+        g_assert_not_reached();
++    int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1;
      kvmfd = qemu_open("/dev/kvm", O_RDWR);
      if (kvmfd < 0) {
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
          goto finish;
      }
-     if (rn == 31) {
+-    ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
 +    if (init->target == -1) {
 +        struct kvm_vcpu_init preferred;
 +
 +        ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred);
 +        if (!ret) {
 +            init->target = preferred.target;
 +        }
 +    }
      if (ret >= 0) {
          ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
          if (ret < 0) {
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
           * creating one kind of guest CPU which is its preferred
           * CPU type.
           */
 +        struct kvm_vcpu_init try;
 +
          while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
 -            init->target = *cpus_to_try++;
 -            memset(init->features, 0, sizeof(init->features));
 -            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
 +            try.target = *cpus_to_try++;
 +            memcpy(try.features, init->features, sizeof(init->features));
 +            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try);
              if (ret >= 0) {
                  break;
              }
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
          if (ret < 0) {
              goto err;
          }
 +        init->target = try.target;
      } else {
          /* Treat a NULL cpus_to_try argument the same as an empty
           * list, which means we will fail the call since this must
 diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm32.c
 +++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
          QEMU_KVM_ARM_TARGET_CORTEX_A15,
          QEMU_KVM_ARM_TARGET_NONE
      };
 -    struct kvm_vcpu_init init;
 +    /*
 +     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
 +     * to use the preferred target
 +     */
 +    struct kvm_vcpu_init init = { .target = -1, };
      if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
          return false;
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
          KVM_ARM_TARGET_CORTEX_A57,
          QEMU_KVM_ARM_TARGET_NONE
      };
 -    struct kvm_vcpu_init init;
 +    /*
 +     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
 +     * to use the preferred target
 +     */
 +    struct kvm_vcpu_init init = { .target = -1, };
      if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
          return false;
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 8/9] hw: add .min_cpus and .default_cpus fields to machine_class
+[PULL 08/11] target/arm/cpu64: max cpu: Support sve properties with KVM
-From: "Emilio G. Cota" <cota@braap.org>
+From: Andrew Jones <drjones@redhat.com>
-max_cpus needs to be an upper bound on the number of vCPUs
+Extend the SVE vq map initialization and validation with KVM's
-initialized; otherwise TCG region initialization breaks.
+supported vector lengths when KVM is enabled. In order to determine
 and select supported lengths we add two new KVM functions for getting
 and setting the KVM_REG_ARM64_SVE_VLS pseudo-register.
-Some boards initialize a hard-coded number of vCPUs, which is not
+This patch has been co-authored with Richard Henderson, who reworked
-captured by the global max_cpus and therefore breaks TCG initialization.
+the target/arm/cpu64.c changes in order to push all the validation and
-Fix it by adding the .min_cpus field to machine_class.
+auto-enabling/disabling steps into the finalizer, resulting in a nice
 LOC reduction.
-This commit also changes some user-facing behaviour: we now die if
+Signed-off-by: Andrew Jones <drjones@redhat.com>
--smp is below this hard-coded vCPU minimum instead of silently
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-ignoring the passed -smp value (sometimes announcing this by printing
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-a warning). However, the introduction of .default_cpus lessens the
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
-likelihood that users will notice this: if -smp isn't set, we now
+Message-id: 20191031142734.8590-9-drjones@redhat.com
 assign the value in .default_cpus to both smp_cpus and max_cpus. IOW,
 if a user does not set -smp, they always get a correct number of vCPUs.
 This change fixes 3468b59 ("tcg: enable multiple TCG contexts in
 softmmu", 2017-10-24), which broke TCG initialization for some
 ARM boards.
 Fixes: 3468b59e18b179bc63c7ce934de912dfa9596122
 Reported-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
 Signed-off-by: Emilio G. Cota <cota@braap.org>
 Message-id: 1510343626-25861-6-git-send-email-cota@braap.org
 Suggested-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Emilio G. Cota <cota@braap.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/boards.h     |  5 +++++
+ target/arm/kvm_arm.h      |  12 +++
- hw/arm/exynos4_boards.c | 12 ++++--------
+ target/arm/cpu64.c        | 176 ++++++++++++++++++++++++++++----------
- hw/arm/raspi.c          |  2 ++
+ target/arm/kvm64.c        | 100 +++++++++++++++++++++-
- hw/arm/xlnx-zcu102.c    |  2 ++
+ tests/arm-cpu-features.c  | 104 +++++++++++++++++++++-
- vl.c                    | 21 ++++++++++++++++++---
+ docs/arm-cpu-features.rst |  45 +++++++---
-files changed, 31 insertions(+), 11 deletions(-)
+files changed, 379 insertions(+), 58 deletions(-)
-diff --git a/include/hw/boards.h b/include/hw/boards.h
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/boards.h
+--- a/target/arm/kvm_arm.h
-+++ b/include/hw/boards.h
++++ b/target/arm/kvm_arm.h
-@@ -XXX,XX +XXX,XX @@ typedef struct {
+@@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures {
+  */
  bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
 +/**
 + * kvm_arm_sve_get_vls:
 + * @cs: CPUState
 + * @map: bitmap to fill in
 + *
 + * Get all the SVE vector lengths supported by the KVM host, setting
 + * the bits corresponding to their length in quadwords minus one
 + * (vq - 1) in @map up to ARM_MAX_VQ.
 + */
 +void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map);
 +
  /**
-  * MachineClass:
+  * kvm_arm_set_cpu_features_from_host:
-+ * @max_cpus: maximum number of CPUs supported. Default: 1
+  * @cpu: ARMCPU to set the features for
-+ * @min_cpus: minimum number of CPUs supported. Default: 1
+@@ -XXX,XX +XXX,XX @@ static inline int kvm_arm_vgic_probe(void)
-+ * @default_cpus: number of CPUs instantiated if none are specified. Default: 1
+ static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
-  * @get_hotplug_handler: this function is called during bus-less
+ static inline void kvm_arm_pmu_init(CPUState *cs) {}
-  *    device hotplug. If defined it returns pointer to an instance
-  *    of HotplugHandler object, which handles hotplug operation
++static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
-@@ -XXX,XX +XXX,XX @@ struct MachineClass {
+ #endif
-     BlockInterfaceType block_default_type;
-     int units_per_default_bus;
+ static inline const char *gic_class_name(void)
-     int max_cpus;
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 +    int min_cpus;
 +    int default_cpus;
      unsigned int no_serial:1,
          no_parallel:1,
          use_virtcon:1,
 diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/exynos4_boards.c
+--- a/target/arm/cpu64.c
-+++ b/hw/arm/exynos4_boards.c
++++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
- #include "qemu-common.h"
+      * any of the above.  Finally, if SVE is not disabled, then at least one
- #include "cpu.h"
+      * vector length must be enabled.
- #include "sysemu/sysemu.h"
+      */
--#include "sysemu/qtest.h"
++    DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ);
- #include "hw/sysbus.h"
+     DECLARE_BITMAP(tmp, ARM_MAX_VQ);
- #include "net/net.h"
+     uint32_t vq, max_vq = 0;
- #include "hw/arm/arm.h"
-@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
++    /* Collect the set of vector lengths supported by KVM. */
-                            Exynos4BoardType board_type)
++    bitmap_zero(kvm_supported, ARM_MAX_VQ);
 +    if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
 +        kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
 +    } else if (kvm_enabled()) {
 +        assert(!cpu_isar_feature(aa64_sve, cpu));
 +    }
 +
      /*
       * Process explicit sve<N> properties.
       * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
              return;
          }
 -        /* Propagate enabled bits down through required powers-of-two. */
 -        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 -            if (!test_bit(vq - 1, cpu->sve_vq_init)) {
 -                set_bit(vq - 1, cpu->sve_vq_map);
 +        if (kvm_enabled()) {
 +            /*
 +             * For KVM we have to automatically enable all supported unitialized
 +             * lengths, even when the smaller lengths are not all powers-of-two.
 +             */
 +            bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq);
 +            bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
 +        } else {
 +            /* Propagate enabled bits down through required powers-of-two. */
 +            for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 +                if (!test_bit(vq - 1, cpu->sve_vq_init)) {
 +                    set_bit(vq - 1, cpu->sve_vq_map);
 +                }
              }
          }
      } else if (cpu->sve_max_vq == 0) {
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
              return;
          }
 -        /* Disabling a power-of-two disables all larger lengths. */
 -        if (test_bit(0, cpu->sve_vq_init)) {
 -            error_setg(errp, "cannot disable sve128");
 -            error_append_hint(errp, "Disabling sve128 results in all vector "
 -                              "lengths being disabled.\n");
 -            error_append_hint(errp, "With SVE enabled, at least one vector "
 -                              "length must be enabled.\n");
 -            return;
 -        }
 -        for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
 -            if (test_bit(vq - 1, cpu->sve_vq_init)) {
 -                break;
 +        if (kvm_enabled()) {
 +            /* Disabling a supported length disables all larger lengths. */
 +            for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 +                if (test_bit(vq - 1, cpu->sve_vq_init) &&
 +                    test_bit(vq - 1, kvm_supported)) {
 +                    break;
 +                }
              }
 +            max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 +            bitmap_andnot(cpu->sve_vq_map, kvm_supported,
 +                          cpu->sve_vq_init, max_vq);
 +            if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
 +                error_setg(errp, "cannot disable sve%d", vq * 128);
 +                error_append_hint(errp, "Disabling sve%d results in all "
 +                                  "vector lengths being disabled.\n",
 +                                  vq * 128);
 +                error_append_hint(errp, "With SVE enabled, at least one "
 +                                  "vector length must be enabled.\n");
 +                return;
 +            }
 +        } else {
 +            /* Disabling a power-of-two disables all larger lengths. */
 +            if (test_bit(0, cpu->sve_vq_init)) {
 +                error_setg(errp, "cannot disable sve128");
 +                error_append_hint(errp, "Disabling sve128 results in all "
 +                                  "vector lengths being disabled.\n");
 +                error_append_hint(errp, "With SVE enabled, at least one "
 +                                  "vector length must be enabled.\n");
 +                return;
 +            }
 +            for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
 +                if (test_bit(vq - 1, cpu->sve_vq_init)) {
 +                    break;
 +                }
 +            }
 +            max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 +            bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
          }
 -        max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 -        bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
          max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
      }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
      assert(max_vq != 0);
      bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
 -    /* Ensure all required powers-of-two are enabled. */
 -    for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 -        if (!test_bit(vq - 1, cpu->sve_vq_map)) {
 -            error_setg(errp, "cannot disable sve%d", vq * 128);
 -            error_append_hint(errp, "sve%d is required as it "
 -                              "is a power-of-two length smaller than "
 -                              "the maximum, sve%d\n",
 -                              vq * 128, max_vq * 128);
 +    if (kvm_enabled()) {
 +        /* Ensure the set of lengths matches what KVM supports. */
 +        bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq);
 +        if (!bitmap_empty(tmp, max_vq)) {
 +            vq = find_last_bit(tmp, max_vq) + 1;
 +            if (test_bit(vq - 1, cpu->sve_vq_map)) {
 +                if (cpu->sve_max_vq) {
 +                    error_setg(errp, "cannot set sve-max-vq=%d",
 +                               cpu->sve_max_vq);
 +                    error_append_hint(errp, "This KVM host does not support "
 +                                      "the vector length %d-bits.\n",
 +                                      vq * 128);
 +                    error_append_hint(errp, "It may not be possible to use "
 +                                      "sve-max-vq with this KVM host. Try "
 +                                      "using only sve<N> properties.\n");
 +                } else {
 +                    error_setg(errp, "cannot enable sve%d", vq * 128);
 +                    error_append_hint(errp, "This KVM host does not support "
 +                                      "the vector length %d-bits.\n",
 +                                      vq * 128);
 +                }
 +            } else {
 +                error_setg(errp, "cannot disable sve%d", vq * 128);
 +                error_append_hint(errp, "The KVM host requires all "
 +                                  "supported vector lengths smaller "
 +                                  "than %d bits to also be enabled.\n",
 +                                  max_vq * 128);
 +            }
              return;
          }
 +    } else {
 +        /* Ensure all required powers-of-two are enabled. */
 +        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 +            if (!test_bit(vq - 1, cpu->sve_vq_map)) {
 +                error_setg(errp, "cannot disable sve%d", vq * 128);
 +                error_append_hint(errp, "sve%d is required as it "
 +                                  "is a power-of-two length smaller than "
 +                                  "the maximum, sve%d\n",
 +                                  vq * 128, max_vq * 128);
 +                return;
 +            }
 +        }
      }
      /*
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
  {
-     Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
+     ARMCPU *cpu = ARM_CPU(obj);
--    MachineClass *mc = MACHINE_GET_CLASS(machine);
+     Error *err = NULL;
 +    uint32_t max_vq;
 -    visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
 -
--    if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
+-    if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
--        error_report("%s board supports only %d CPU cores, ignoring smp_cpus"
+-        error_setg(&err, "unsupported SVE vector length");
--                     " value",
+-        error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
--                     mc->name, EXYNOS4210_NCPUS);
+-                          ARM_MAX_VQ);
--    }
++    visit_type_uint32(v, name, &max_vq, &err);
++    if (err) {
-     exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
++        error_propagate(errp, err);
-     exynos4_board_binfo.board_id = exynos4_board_id[board_type];
++        return;
-@@ -XXX,XX +XXX,XX @@ static void nuri_class_init(ObjectClass *oc, void *data)
+     }
-     mc->desc = "Samsung NURI board (Exynos4210)";
+-    error_propagate(errp, err);
-     mc->init = nuri_init;
++
-     mc->max_cpus = EXYNOS4210_NCPUS;
++    if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
-+    mc->min_cpus = EXYNOS4210_NCPUS;
++        error_setg(errp, "cannot set sve-max-vq");
-+    mc->default_cpus = EXYNOS4210_NCPUS;
++        error_append_hint(errp, "SVE not supported by KVM on this host\n");
-     mc->ignore_memory_transaction_failures = true;
++        return;
 +    }
 +
 +    if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
 +        error_setg(errp, "unsupported SVE vector length");
 +        error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
 +                          ARM_MAX_VQ);
 +        return;
 +    }
 +
 +    cpu->sve_max_vq = max_vq;
  }
-@@ -XXX,XX +XXX,XX @@ static void smdkc210_class_init(ObjectClass *oc, void *data)
+ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
-     mc->desc = "Samsung SMDKC210 board (Exynos4210)";
+@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
-     mc->init = smdkc210_init;
+         return;
-     mc->max_cpus = EXYNOS4210_NCPUS;
+     }
-+    mc->min_cpus = EXYNOS4210_NCPUS;
-+    mc->default_cpus = EXYNOS4210_NCPUS;
++    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
-     mc->ignore_memory_transaction_failures = true;
++        error_setg(errp, "cannot enable %s", name);
 +        error_append_hint(errp, "SVE not supported by KVM on this host\n");
 +        return;
 +    }
 +
      if (value) {
          set_bit(vq - 1, cpu->sve_vq_map);
      } else {
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
          cpu->dcz_blocksize = 7; /*  512 bytes */
  #endif
 -
 -        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
 -                            cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 -
 -        for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 -            char name[8];
 -            sprintf(name, "sve%d", vq * 128);
 -            object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 -                                cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 -        }
      }
      object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
                          cpu_arm_set_sve, NULL, NULL, &error_fatal);
 +    object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
 +                        cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 +
 +    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 +        char name[8];
 +        sprintf(name, "sve%d", vq * 128);
 +        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 +                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 +    }
  }
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+ struct ARMCPUInfo {
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
+--- a/target/arm/kvm64.c
-+++ b/hw/arm/raspi.c
++++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(CPUState *cpu)
-     mc->no_floppy = 1;
+     return kvm_check_extension(s, KVM_CAP_ARM_SVE);
-     mc->no_cdrom = 1;
+ }
-     mc->max_cpus = BCM2836_NCPUS;
-+    mc->min_cpus = BCM2836_NCPUS;
++QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
-+    mc->default_cpus = BCM2836_NCPUS;
++
-     mc->default_ram_size = 1024 * 1024 * 1024;
++void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
-     mc->ignore_memory_transaction_failures = true;
++{
- };
++    /* Only call this function if kvm_arm_sve_supported() returns true. */
-diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
++    static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];
 +    static bool probed;
 +    uint32_t vq = 0;
 +    int i, j;
 +
 +    bitmap_clear(map, 0, ARM_MAX_VQ);
 +
 +    /*
 +     * KVM ensures all host CPUs support the same set of vector lengths.
 +     * So we only need to create the scratch VCPUs once and then cache
 +     * the results.
 +     */
 +    if (!probed) {
 +        struct kvm_vcpu_init init = {
 +            .target = -1,
 +            .features[0] = (1 << KVM_ARM_VCPU_SVE),
 +        };
 +        struct kvm_one_reg reg = {
 +            .id = KVM_REG_ARM64_SVE_VLS,
 +            .addr = (uint64_t)&vls[0],
 +        };
 +        int fdarray[3], ret;
 +
 +        probed = true;
 +
 +        if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) {
 +            error_report("failed to create scratch VCPU with SVE enabled");
 +            abort();
 +        }
 +        ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &reg);
 +        kvm_arm_destroy_scratch_host_vcpu(fdarray);
 +        if (ret) {
 +            error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s",
 +                         strerror(errno));
 +            abort();
 +        }
 +
 +        for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {
 +            if (vls[i]) {
 +                vq = 64 - clz64(vls[i]) + i * 64;
 +                break;
 +            }
 +        }
 +        if (vq > ARM_MAX_VQ) {
 +            warn_report("KVM supports vector lengths larger than "
 +                        "QEMU can enable");
 +        }
 +    }
 +
 +    for (i = 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) {
 +        if (!vls[i]) {
 +            continue;
 +        }
 +        for (j = 1; j <= 64; ++j) {
 +            vq = j + i * 64;
 +            if (vq > ARM_MAX_VQ) {
 +                return;
 +            }
 +            if (vls[i] & (1UL << (j - 1))) {
 +                set_bit(vq - 1, map);
 +            }
 +        }
 +    }
 +}
 +
 +static int kvm_arm_sve_set_vls(CPUState *cs)
 +{
 +    uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = {0};
 +    struct kvm_one_reg reg = {
 +        .id = KVM_REG_ARM64_SVE_VLS,
 +        .addr = (uint64_t)&vls[0],
 +    };
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    uint32_t vq;
 +    int i, j;
 +
 +    assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
 +
 +    for (vq = 1; vq <= cpu->sve_max_vq; ++vq) {
 +        if (test_bit(vq - 1, cpu->sve_vq_map)) {
 +            i = (vq - 1) / 64;
 +            j = (vq - 1) % 64;
 +            vls[i] |= 1UL << j;
 +        }
 +    }
 +
 +    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +}
 +
  #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
  int kvm_arch_init_vcpu(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
          !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
 -        fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 +        error_report("KVM is not supported for this guest CPU type");
          return -EINVAL;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      }
      if (cpu_isar_feature(aa64_sve, cpu)) {
 +        ret = kvm_arm_sve_set_vls(cs);
 +        if (ret) {
 +            return ret;
 +        }
          ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
          if (ret) {
              return ret;
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-zcu102.c
+--- a/tests/arm-cpu-features.c
-+++ b/hw/arm/xlnx-zcu102.c
++++ b/tests/arm-cpu-features.c
-@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static QDict *resp_get_props(QDict *resp)
-     mc->units_per_default_bus = 1;
+     return qdict;
      mc->ignore_memory_transaction_failures = true;
      mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
 +    mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
  }
- static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
++static bool resp_get_feature(QDict *resp, const char *feature)
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
++{
-     mc->units_per_default_bus = 1;
++    QDict *props;
-     mc->ignore_memory_transaction_failures = true;
++
-     mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
++    g_assert(resp);
-+    mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
++    g_assert(resp_has_props(resp));
 +    props = resp_get_props(resp);
 +    g_assert(qdict_get(props, feature));
 +    return qdict_get_bool(props, feature);
 +}
 +
  #define assert_has_feature(qts, cpu_type, feature)                     \
  ({                                                                     \
      QDict *_resp = do_query_no_props(qts, cpu_type);                   \
@@ -XXX,XX +XXX,XX @@ static void sve_tests_sve_off(const void *data)
      qtest_quit(qts);
  }
- static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
++static void sve_tests_sve_off_kvm(const void *data)
-diff --git a/vl.c b/vl.c
++{
 +    QTestState *qts;
 +
 +    qts = qtest_init(MACHINE_KVM "-cpu max,sve=off");
 +
 +    /*
 +     * We don't know if this host supports SVE so we don't
 +     * attempt to test enabling anything. We only test that
 +     * everything is disabled (as it should be with sve=off)
 +     * and that using sve<N>=off to explicitly disable vector
 +     * lengths is OK too.
 +     */
 +    assert_sve_vls(qts, "max", 0, NULL);
 +    assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
 +
 +    qtest_quit(qts);
 +}
 +
  static void test_query_cpu_model_expansion(const void *data)
  {
      QTestState *qts;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
      }
      if (g_str_equal(qtest_get_arch(), "aarch64")) {
 +        bool kvm_supports_sve;
 +        char max_name[8], name[8];
 +        uint32_t max_vq, vq;
 +        uint64_t vls;
 +        QDict *resp;
 +        char *error;
 +
          assert_has_feature(qts, "host", "aarch64");
          assert_has_feature(qts, "host", "pmu");
 -        assert_has_feature(qts, "max", "sve");
 -
          assert_error(qts, "cortex-a15",
              "We cannot guarantee the CPU type 'cortex-a15' works "
              "with KVM on this host", NULL);
 +
 +        assert_has_feature(qts, "max", "sve");
 +        resp = do_query_no_props(qts, "max");
 +        kvm_supports_sve = resp_get_feature(resp, "sve");
 +        vls = resp_get_sve_vls(resp);
 +        qobject_unref(resp);
 +
 +        if (kvm_supports_sve) {
 +            g_assert(vls != 0);
 +            max_vq = 64 - __builtin_clzll(vls);
 +            sprintf(max_name, "sve%d", max_vq * 128);
 +
 +            /* Enabling a supported length is of course fine. */
 +            assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
 +
 +            /* Get the next supported length smaller than max-vq. */
 +            vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
 +            if (vq) {
 +                /*
 +                 * We have at least one length smaller than max-vq,
 +                 * so we can disable max-vq.
 +                 */
 +                assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
 +                               "{ %s: false }", max_name);
 +
 +                /*
 +                 * Smaller, supported vector lengths cannot be disabled
 +                 * unless all larger, supported vector lengths are also
 +                 * disabled.
 +                 */
 +                sprintf(name, "sve%d", vq * 128);
 +                error = g_strdup_printf("cannot disable %s", name);
 +                assert_error(qts, "max", error,
 +                             "{ %s: true, %s: false }",
 +                             max_name, name);
 +                g_free(error);
 +            }
 +
 +            /*
 +             * The smallest, supported vector length is required, because
 +             * we need at least one vector length enabled.
 +             */
 +            vq = __builtin_ffsll(vls);
 +            sprintf(name, "sve%d", vq * 128);
 +            error = g_strdup_printf("cannot disable %s", name);
 +            assert_error(qts, "max", error, "{ %s: false }", name);
 +            g_free(error);
 +
 +            /* Get an unsupported length. */
 +            for (vq = 1; vq <= max_vq; ++vq) {
 +                if (!(vls & BIT_ULL(vq - 1))) {
 +                    break;
 +                }
 +            }
 +            if (vq <= SVE_MAX_VQ) {
 +                sprintf(name, "sve%d", vq * 128);
 +                error = g_strdup_printf("cannot enable %s", name);
 +                assert_error(qts, "max", error, "{ %s: true }", name);
 +                g_free(error);
 +            }
 +        } else {
 +            g_assert(vls == 0);
 +        }
      } else {
          assert_has_not_feature(qts, "host", "aarch64");
          assert_has_not_feature(qts, "host", "pmu");
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
                              NULL, sve_tests_sve_max_vq_8);
          qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
                              NULL, sve_tests_sve_off);
 +        qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
 +                            NULL, sve_tests_sve_off_kvm);
      }
      return g_test_run();
 diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
 index XXXXXXX..XXXXXXX 100644
---- a/vl.c
+--- a/docs/arm-cpu-features.rst
-+++ b/vl.c
++++ b/docs/arm-cpu-features.rst
-@@ -XXX,XX +XXX,XX @@ Chardev *virtcon_hds[MAX_VIRTIO_CONSOLES];
+@@ -XXX,XX +XXX,XX @@ SVE CPU Property Dependencies and Constraints
- Chardev *sclp_hds[MAX_SCLP_CONSOLES];
- int win2k_install_hack = 0;
+) At least one vector length must be enabled when `sve` is enabled.
- int singlestep = 0;
--int smp_cpus = 1;
+-  2) If a vector length `N` is enabled, then all power-of-two vector
--unsigned int max_cpus = 1;
+-     lengths smaller than `N` must also be enabled.  E.g. if `sve512`
-+int smp_cpus;
+-     is enabled, then the 128-bit and 256-bit vector lengths must also
-+unsigned int max_cpus;
+-     be enabled.
- int smp_cores = 1;
++  2) If a vector length `N` is enabled, then, when KVM is enabled, all
- int smp_threads = 1;
++     smaller, host supported vector lengths must also be enabled.  If
- int acpi_enabled = 1;
++     KVM is not enabled, then only all the smaller, power-of-two vector
-@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp)
++     lengths must be enabled.  E.g. with KVM if the host supports all
-         exit(0);
++     vector lengths up to 512-bits (128, 256, 384, 512), then if `sve512`
-     }
++     is enabled, the 128-bit vector length, 256-bit vector length, and
++     384-bit vector length must also be enabled. Without KVM, the 384-bit
-+    /* machine_class: default to UP */
++     vector length would not be required.
-+    machine_class->max_cpus = machine_class->max_cpus ?: 1;
++
-+    machine_class->min_cpus = machine_class->min_cpus ?: 1;
++  3) If KVM is enabled then only vector lengths that the host CPU type
-+    machine_class->default_cpus = machine_class->default_cpus ?: 1;
++     support may be enabled.  If SVE is not supported by the host, then
-+
++     no `sve*` properties may be enabled.
-+    /* default to machine_class->default_cpus */
-+    smp_cpus = machine_class->default_cpus;
+ SVE CPU Property Parsing Semantics
-+    max_cpus = machine_class->default_cpus;
+ ----------------------------------
-+
+@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
-     smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
+      an error is generated.
--    machine_class->max_cpus = machine_class->max_cpus ?: 1; /* Default to UP */
+) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
-+    /* sanity-check smp_cpus and max_cpus against machine_class */
+-     provided, then all supported vector lengths are enabled, including
-+    if (smp_cpus < machine_class->min_cpus) {
+-     the non-power-of-two lengths.
-+        error_report("Invalid SMP CPUs %d. The min CPUs "
++     provided, then all supported vector lengths are enabled, which when
-+                     "supported by machine '%s' is %d", smp_cpus,
++     KVM is not in use means including the non-power-of-two lengths, and,
-+                     machine_class->name, machine_class->min_cpus);
++     when KVM is in use, it means all vector lengths supported by the host
-+        exit(1);
++     processor.
-+    }
-     if (max_cpus > machine_class->max_cpus) {
+) If SVE is enabled, then an error is generated when attempting to
-         error_report("Invalid SMP CPUs %d. The max CPUs "
+      disable the last enabled vector length (see constraint (1) of "SVE
-                      "supported by machine '%s' is %d", max_cpus,
+@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
       has been explicitly disabled, then an error is generated (see
       constraint (2) of "SVE CPU Property Dependencies and Constraints").
 -  5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
 +  5) When KVM is enabled, if the host does not support SVE, then an error
 +     is generated when attempting to enable any `sve*` properties (see
 +     constraint (3) of "SVE CPU Property Dependencies and Constraints").
 +
 +  6) When KVM is enabled, if the host does support SVE, then an error is
 +     generated when attempting to enable any vector lengths not supported
 +     by the host (see constraint (3) of "SVE CPU Property Dependencies and
 +     Constraints").
 +
 +  7) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
       CPU properties are set `on`, then the specified vector lengths are
       disabled but the default for any unspecified lengths remains enabled.
 -     Disabling a power-of-two vector length also disables all vector
 -     lengths larger than the power-of-two length (see constraint (2) of
 -     "SVE CPU Property Dependencies and Constraints").
 +     When KVM is not enabled, disabling a power-of-two vector length also
 +     disables all vector lengths larger than the power-of-two length.
 +     When KVM is enabled, then disabling any supported vector length also
 +     disables all larger vector lengths (see constraint (2) of "SVE CPU
 +     Property Dependencies and Constraints").
 -  6) If one or more `sve<N>` CPU properties are set to `on`, then they
 +  8) If one or more `sve<N>` CPU properties are set to `on`, then they
       are enabled and all unspecified lengths default to disabled, except
       for the required lengths per constraint (2) of "SVE CPU Property
       Dependencies and Constraints", which will even be auto-enabled if
       they were not explicitly enabled.
 -  7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
 +  9) If SVE was disabled (`sve=off`), allowing all vector lengths to be
       explicitly disabled (i.e. avoiding the error specified in (3) of
       "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
       provided an error will be generated.  To avoid this error, one must
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 6/9] xlnx-zcu102: Add an info message deprecating the EP108
+[PULL 09/11] target/arm/kvm: host cpu: Add support for sve<N> properties
-From: Alistair Francis <alistair.francis@xilinx.com>
+From: Andrew Jones <drjones@redhat.com>
-The EP108 was an early access development board that is no longer used.
+Allow cpu 'host' to enable SVE when it's available, unless the
-Add an info message to convert any users to the ZCU102 instead. On QEMU
+user chooses to disable it with the added 'sve=off' cpu property.
-they are both identical.
+Also give the user the ability to select vector lengths with the
+sve<N> properties. We don't adopt 'max' cpu's other sve property,
-This patch also updated the qemu-doc.texi file to indicate that the
+sve-max-vq, because that property is difficult to use with KVM.
-EP108 has been deprecated.
+That property assumes all vector lengths in the range from 1 up
+to and including the specified maximum length are supported, but
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
+there may be optional lengths not supported by the host in that
-Reviewed-by: Emilio G. Cota <cota@braap.org>
+range. With KVM one must be more specific when enabling vector
-Message-id: 1510343626-25861-4-git-send-email-cota@braap.org
+lengths.
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
 Message-id: 20191031142734.8590-10-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-zcu102.c | 3 +++
+ target/arm/cpu.h          |  2 ++
- qemu-doc.texi        | 7 +++++++
+ target/arm/cpu.c          |  3 +++
-files changed, 10 insertions(+)
+ target/arm/cpu64.c        | 33 +++++++++++++++++----------------
+ target/arm/kvm64.c        | 14 +++++++++++++-
-diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
+ tests/arm-cpu-features.c  | 17 ++++++++---------
-index XXXXXXX..XXXXXXX 100644
+ docs/arm-cpu-features.rst | 19 ++++++++++++-------
---- a/hw/arm/xlnx-zcu102.c
+files changed, 55 insertions(+), 33 deletions(-)
-+++ b/hw/arm/xlnx-zcu102.c
-@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
  void aarch64_sve_change_el(CPUARMState *env, int old_el,
                             int new_el, bool el0_a64);
 +void aarch64_add_sve_properties(Object *obj);
  #else
  static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
  static inline void aarch64_sve_change_el(CPUARMState *env, int o,
                                           int n, bool a)
  { }
 +static inline void aarch64_add_sve_properties(Object *obj) { }
  #endif
  #if !defined(CONFIG_TCG)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
      ARMCPU *cpu = ARM_CPU(obj);
      kvm_arm_set_cpu_features_from_host(cpu);
 +    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +        aarch64_add_sve_properties(obj);
 +    }
      arm_cpu_post_init(obj);
  }
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
      cpu->isar.id_aa64pfr0 = t;
  }
 +void aarch64_add_sve_properties(Object *obj)
 +{
 +    uint32_t vq;
 +
 +    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 +                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
 +
 +    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 +        char name[8];
 +        sprintf(name, "sve%d", vq * 128);
 +        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 +                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 +    }
 +}
 +
  /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
   * otherwise, a CPU with as many features enabled as our emulation supports.
   * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
  static void aarch64_max_initfn(Object *obj)
  {
-     XlnxZCU102 *s = EP108_MACHINE(machine);
+     ARMCPU *cpu = ARM_CPU(obj);
+-    uint32_t vq;
-+    info_report("The Xilinx EP108 machine is deprecated, please use the "
+-    uint64_t t;
-+                "ZCU102 machine instead. It has the same features supported.");
-+
+     if (kvm_enabled()) {
-     xlnx_zynqmp_init(s, machine);
+         kvm_arm_set_cpu_features_from_host(cpu);
 -        if (kvm_arm_sve_supported(CPU(cpu))) {
 -            t = cpu->isar.id_aa64pfr0;
 -            t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 -            cpu->isar.id_aa64pfr0 = t;
 -        }
      } else {
 +        uint64_t t;
          uint32_t u;
          aarch64_a57_initfn(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
  #endif
      }
 -    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 -                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
 +    aarch64_add_sve_properties(obj);
      object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                          cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 -
 -    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 -        char name[8];
 -        sprintf(name, "sve%d", vq * 128);
 -        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 -                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 -    }
  }
-diff --git a/qemu-doc.texi b/qemu-doc.texi
+ struct ARMCPUInfo {
-index XXXXXXX..XXXXXXX 100644
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
---- a/qemu-doc.texi
+index XXXXXXX..XXXXXXX 100644
-+++ b/qemu-doc.texi
+--- a/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ or ``ivshmem-doorbell`` device types.
++++ b/target/arm/kvm64.c
- The ``spapr-pci-vfio-host-bridge'' device type is replaced by
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
- the ``spapr-pci-host-bridge'' device type.
+      * and then query that CPU for the relevant ID registers.
+      */
-+@section System emulator machines
+     int fdarray[3];
-+
++    bool sve_supported;
-+@subsection Xilinx EP108 (since 2.11.0)
+     uint64_t features = 0;
-+
++    uint64_t t;
-+The ``xlnx-ep108'' machine has been replaced by the ``xlnx-zcu102'' machine.
+     int err;
-+The ``xlnx-zcu102'' machine has the same features and capabilites in QEMU.
-+
+     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
- @node License
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
- @appendix License
+                               ARM64_SYS_REG(3, 0, 0, 3, 2));
      }
 +    sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
 +
      kvm_arm_destroy_scratch_host_vcpu(fdarray);
      if (err < 0) {
          return false;
      }
 -   /* We can assume any KVM supporting CPU is at least a v8
 +    /* Add feature bits that can't appear until after VCPU init. */
 +    if (sve_supported) {
 +        t = ahcf->isar.id_aa64pfr0;
 +        t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 +        ahcf->isar.id_aa64pfr0 = t;
 +    }
 +
 +    /*
 +     * We can assume any KVM supporting CPU is at least a v8
       * with VFPv4+Neon; this in turn implies most of the other
       * feature bits.
       */
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/arm-cpu-features.c
 +++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
              "We cannot guarantee the CPU type 'cortex-a15' works "
              "with KVM on this host", NULL);
 -        assert_has_feature(qts, "max", "sve");
 -        resp = do_query_no_props(qts, "max");
 +        assert_has_feature(qts, "host", "sve");
 +        resp = do_query_no_props(qts, "host");
          kvm_supports_sve = resp_get_feature(resp, "sve");
          vls = resp_get_sve_vls(resp);
          qobject_unref(resp);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
              sprintf(max_name, "sve%d", max_vq * 128);
              /* Enabling a supported length is of course fine. */
 -            assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
 +            assert_sve_vls(qts, "host", vls, "{ %s: true }", max_name);
              /* Get the next supported length smaller than max-vq. */
              vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
                   * We have at least one length smaller than max-vq,
                   * so we can disable max-vq.
                   */
 -                assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
 +                assert_sve_vls(qts, "host", (vls & ~BIT_ULL(max_vq - 1)),
                                 "{ %s: false }", max_name);
                  /*
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
                   */
                  sprintf(name, "sve%d", vq * 128);
                  error = g_strdup_printf("cannot disable %s", name);
 -                assert_error(qts, "max", error,
 +                assert_error(qts, "host", error,
                               "{ %s: true, %s: false }",
                               max_name, name);
                  g_free(error);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
              vq = __builtin_ffsll(vls);
              sprintf(name, "sve%d", vq * 128);
              error = g_strdup_printf("cannot disable %s", name);
 -            assert_error(qts, "max", error, "{ %s: false }", name);
 +            assert_error(qts, "host", error, "{ %s: false }", name);
              g_free(error);
              /* Get an unsupported length. */
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
              if (vq <= SVE_MAX_VQ) {
                  sprintf(name, "sve%d", vq * 128);
                  error = g_strdup_printf("cannot enable %s", name);
 -                assert_error(qts, "max", error, "{ %s: true }", name);
 +                assert_error(qts, "host", error, "{ %s: true }", name);
                  g_free(error);
              }
          } else {
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
      } else {
          assert_has_not_feature(qts, "host", "aarch64");
          assert_has_not_feature(qts, "host", "pmu");
 -
 -        assert_has_not_feature(qts, "max", "sve");
 +        assert_has_not_feature(qts, "host", "sve");
      }
      qtest_quit(qts);
 diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/arm-cpu-features.rst
 +++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Examples
       $ qemu-system-aarch64 -M virt -cpu max
 -  3) Only enable the 128-bit vector length::
 +  3) When KVM is enabled, implicitly enable all host CPU supported vector
 +     lengths with the `host` CPU type::
 +
 +     $ qemu-system-aarch64 -M virt,accel=kvm -cpu host
 +
 +  4) Only enable the 128-bit vector length::
       $ qemu-system-aarch64 -M virt -cpu max,sve128=on
 -  4) Disable the 512-bit vector length and all larger vector lengths,
 +  5) Disable the 512-bit vector length and all larger vector lengths,
       since 512 is a power-of-two.  This results in all the smaller,
       uninitialized lengths (128, 256, and 384) defaulting to enabled::
       $ qemu-system-aarch64 -M virt -cpu max,sve512=off
 -  5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
 +  6) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
       $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
 -  6) The same as (5), but since the 128-bit and 256-bit vector
 +  7) The same as (6), but since the 128-bit and 256-bit vector
       lengths are required for the 512-bit vector length to be enabled,
       then allow them to be auto-enabled::
       $ qemu-system-aarch64 -M virt -cpu max,sve512=on
 -  7) Do the same as (6), but by first disabling SVE and then re-enabling it::
 +  8) Do the same as (7), but by first disabling SVE and then re-enabling it::
       $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
 -  8) Force errors regarding the last vector length::
 +  9) Force errors regarding the last vector length::
       $ qemu-system-aarch64 -M virt -cpu max,sve128=off
       $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
@@ -XXX,XX +XXX,XX @@ The examples in "SVE CPU Property Examples" exhibit many ways to select
  vector lengths which developers may find useful in order to avoid overly
  verbose command lines.  However, the recommended way to select vector
  lengths is to explicitly enable each desired length.  Therefore only
 -example's (1), (3), and (5) exhibit recommended uses of the properties.
 +example's (1), (4), and (6) exhibit recommended uses of the properties.
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 7/9] xlnx-zcu102: Specify the max number of CPUs for the EP108
+[PULL 10/11] hw/arm/boot: Rebuild hflags when modifying CPUState at boot
-From: "Emilio G. Cota" <cota@braap.org>
+From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Just like the zcu102, the ep108 can instantiate several CPUs.
+Rebuild hflags when modifying CPUState at boot.
-Signed-off-by: Emilio G. Cota <cota@braap.org>
+Fixes: e979972a6a
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Message-id: 1510343626-25861-5-git-send-email-cota@braap.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
 Message-id: 20191031040830.18800-2-edgar.iglesias@xilinx.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-zcu102.c | 1 +
+ hw/arm/boot.c | 1 +
 file changed, 1 insertion(+)
-diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-zcu102.c
+--- a/hw/arm/boot.c
-+++ b/hw/arm/xlnx-zcu102.c
++++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
-     mc->block_default_type = IF_IDE;
+                 info->secondary_cpu_reset_hook(cpu, info);
-     mc->units_per_default_bus = 1;
+             }
-     mc->ignore_memory_transaction_failures = true;
+         }
-+    mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
++        arm_rebuild_hflags(env);
      }
  }
- static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 2/9] highbank: validate register offset before access
+[PULL 11/11] target/arm: Allow reading flags from FPSCR for M-profile
-From: Prasad J Pandit <pjp@fedoraproject.org>
+From: Christophe Lyon <christophe.lyon@linaro.org>
-An 'offset' parameter sent to highbank register r/w functions
+rt==15 is a special case when reading the flags: it means the
-could be greater than number(NUM_REGS=0x200) of hb registers,
+destination is APSR. This patch avoids rejecting
-leading to an OOB access issue. Add check to avoid it.
+vmrs apsr_nzcv, fpscr
 as illegal instruction.
-Reported-by: Moguofang (Dennis mo) <moguofang@huawei.com>
+Cc: qemu-stable@nongnu.org
-Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
+Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
-Message-id: 20171113062658.9697-1-ppandit@redhat.com
+Message-id: 20191025095711.10853-1-christophe.lyon@linaro.org
 [PMM: updated the comment]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/highbank.c | 17 +++++++++++++++--
+ target/arm/translate-vfp.inc.c | 5 +++--
-file changed, 15 insertions(+), 2 deletions(-)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
+diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/highbank.c
+--- a/target/arm/translate-vfp.inc.c
-+++ b/hw/arm/highbank.c
++++ b/target/arm/translate-vfp.inc.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
- #include "hw/ide/ahci.h"
+     if (arm_dc_feature(s, ARM_FEATURE_M)) {
- #include "hw/cpu/a9mpcore.h"
+         /*
- #include "hw/cpu/a15mpcore.h"
+          * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
-+#include "qemu/log.h"
+-         * Writes to R15 are UNPREDICTABLE; we choose to undef.
++         * Accesses to R15 are UNPREDICTABLE; we choose to undef.
- #define SMP_BOOT_ADDR           0x100
++         * (FPSCR -> r15 is a special case which writes to the PSR flags.)
- #define SMP_BOOT_REG            0x40
+          */
-@@ -XXX,XX +XXX,XX @@ static void hb_regs_write(void *opaque, hwaddr offset,
+-        if (a->rt == 15 || a->reg != ARM_VFP_FPSCR) {
 +        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
              return false;
          }
      }
--    regs[offset/4] = value;
-+    if (offset / 4 >= NUM_REGS) {
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                  "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
-+        return;
-+    }
-+    regs[offset / 4] = value;
- }
- static uint64_t hb_regs_read(void *opaque, hwaddr offset,
-                              unsigned size)
- {
-+    uint32_t value;
-     uint32_t *regs = opaque;
--    uint32_t value = regs[offset/4];
-+
-+    if (offset / 4 >= NUM_REGS) {
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                  "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
-+        return 0;
-+    }
-+    value = regs[offset / 4];
-     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
-         value |= 0x30000000;
 --
-.7.4
+.20.1

ARM bugfixes for rc1...

The following changes since commit f291910db61b5812e68f1e76afb3ade41d567bea:

Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-11-09' into staging (2017-11-13 13:13:12 +0000)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171113

for you to fetch changes up to d25f2a72272b9ffe0d06710d6217d1169bc2cc7d:

accel/tcg/translate-all: expand cpu_restore_state addr check (2017-11-13 13:55:27 +0000)

----------------------------------------------------------------
target-arm queue:
 * translate-a64.c: silence gcc5 warning
 * highbank: validate register offset before access
 * MAINTAINERS: Add entries for Smartfusion2
 * accel/tcg/translate-all: expand cpu_restore_state addr check
   (so usermode insn aborts don't crash with an assertion failure)
 * fix TCG initialization of some Arm boards by allowing them
   to specify min/default number of CPUs to create

----------------------------------------------------------------
Alex Bennée (1):
      accel/tcg/translate-all: expand cpu_restore_state addr check

Alistair Francis (2):
      xlnx-zynqmp: Properly support the smp command line option
      xlnx-zcu102: Add an info message deprecating the EP108

Emilio G. Cota (4):
      arm/translate-a64: mark path as unreachable to eliminate warning
      qom: move CPUClass.tcg_initialize to a global
      xlnx-zcu102: Specify the max number of CPUs for the EP108
      hw: add .min_cpus and .default_cpus fields to machine_class

Prasad J Pandit (1):
      highbank: validate register offset before access

Subbaraya Sundeep (1):
      MAINTAINERS: Add entries for Smartfusion2

From: "Emilio G. Cota" <cota@braap.org>

Fixes the following warning when compiling with gcc 5.4.0 with -O1
optimizations and --enable-debug:

target/arm/translate-a64.c: In function ‘aarch64_tr_translate_insn’:
target/arm/translate-a64.c:2361:8: error: ‘post_index’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
     if (!post_index) {
        ^
target/arm/translate-a64.c:2307:10: note: ‘post_index’ was declared here
     bool post_index;
          ^
target/arm/translate-a64.c:2386:8: error: ‘writeback’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
     if (writeback) {
        ^
target/arm/translate-a64.c:2308:10: note: ‘writeback’ was declared here
     bool writeback;
          ^

Note that idx comes from selecting 2 bits, and therefore its value
can be at most 3.

Signed-off-by: Emilio G. Cota <cota@braap.org>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1510087611-1851-1-git-send-email-cota@braap.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
         post_index = false;
         writeback = true;
         break;
+    default:
+        g_assert_not_reached();
     }
 
     if (rn == 31) {
-- 
2.7.4

From: Prasad J Pandit <pjp@fedoraproject.org>

An 'offset' parameter sent to highbank register r/w functions
could be greater than number(NUM_REGS=0x200) of hb registers,
leading to an OOB access issue. Add check to avoid it.

Reported-by: Moguofang (Dennis mo) <moguofang@huawei.com>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Message-id: 20171113062658.9697-1-ppandit@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/highbank.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/ide/ahci.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/cpu/a15mpcore.h"
+#include "qemu/log.h"
 
 #define SMP_BOOT_ADDR           0x100
 #define SMP_BOOT_REG            0x40
@@ -XXX,XX +XXX,XX @@ static void hb_regs_write(void *opaque, hwaddr offset,
         }
     }
 
-    regs[offset/4] = value;
+    if (offset / 4 >= NUM_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                  "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
+        return;
+    }
+    regs[offset / 4] = value;
 }
 
 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
                              unsigned size)
 {
+    uint32_t value;
     uint32_t *regs = opaque;
-    uint32_t value = regs[offset/4];
+
+    if (offset / 4 >= NUM_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                  "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
+        return 0;
+    }
+    value = regs[offset / 4];
 
     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
         value |= 0x30000000;
-- 
2.7.4

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Voluntarily add myself as maintainer for Smartfusion2

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1510552520-3566-1-git-send-email-sundeep.lkml@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/arm/netduino2.c
 
+SmartFusion2
+M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+S: Maintained
+F: hw/arm/msf2-soc.c
+F: hw/misc/msf2-sysreg.c
+F: hw/timer/mss-timer.c
+F: hw/ssi/mss-spi.c
+F: include/hw/arm/msf2-soc.h
+F: include/hw/misc/msf2-sysreg.h
+F: include/hw/timer/mss-timer.h
+F: include/hw/ssi/mss-spi.h
+
+Emcraft M2S-FG484
+M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+S: Maintained
+F: hw/arm/msf2-som.c
+
 CRIS Machines
 -------------
 Axis Dev88
-- 
2.7.4

From: "Emilio G. Cota" <cota@braap.org>

55c3cee ("qom: Introduce CPUClass.tcg_initialize", 2017-10-24)
introduces a per-CPUClass bool that we check so that the target CPU
is initialized for TCG only once. This works well except when
we end up creating more than one CPUClass, in which case we end
up incorrectly initializing TCG more than once, i.e. once for
each CPUClass.

This can be replicated with:
  $ aarch64-softmmu/qemu-system-aarch64 -machine xlnx-zcu102 -smp 6 \
      -global driver=xlnx,,zynqmp,property=has_rpu,value=on
In this case the class name of the "RPUs" is prefixed by "cortex-r5-",
whereas the "regular" CPUs are prefixed by "cortex-a53-". This
results in two CPUClass instances being created.

Fix it by introducing a static variable, so that only the first
target CPU being initialized will initialize the target-dependent
part of TCG, regardless of CPUClass instances.

Fixes: 55c3ceef61fcf06fc98ddc752b7cce788ce7680b
Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1510343626-25861-2-git-send-email-cota@braap.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/qom/cpu.h | 1 -
 exec.c            | 5 +++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
     /* Keep non-pointer data at the end to minimize holes.  */
     int gdb_num_core_regs;
     bool gdb_stop_before_watchpoint;
-    bool tcg_initialized;
 } CPUClass;
 
 #ifdef HOST_WORDS_BIGENDIAN
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ void cpu_exec_initfn(CPUState *cpu)
 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
 {
     CPUClass *cc = CPU_GET_CLASS(cpu);
+    static bool tcg_target_initialized;
 
     cpu_list_add(cpu);
 
-    if (tcg_enabled() && !cc->tcg_initialized) {
-        cc->tcg_initialized = true;
+    if (tcg_enabled() && !tcg_target_initialized) {
+        tcg_target_initialized = true;
         cc->tcg_initialize();
     }
 
-- 
2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

Allow the -smp command line option to control the number of CPUs we
create.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Tested-by: Emilio G. Cota <cota@braap.org>
Message-id: 1510343626-25861-3-git-send-email-cota@braap.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-zcu102.c |  3 ++-
 hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++----------
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
 
-    mc->desc = "Xilinx ZynqMP ZCU102 board";
+    mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5s based on " \
+               "the value of smp";
     mc->init = xlnx_zcu102_init;
     mc->block_default_type = IF_IDE;
     mc->units_per_default_bus = 1;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
 {
     Error *err = NULL;
     int i;
+    int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
 
-    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
+    for (i = 0; i < num_rpus; i++) {
         char *name;
 
         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
 {
     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
     int i;
+    int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 
-    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
+    for (i = 0; i < num_apus; i++) {
         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
                           "cortex-a53-" TYPE_ARM_CPU);
         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
     MemoryRegion *system_memory = get_system_memory();
     uint8_t i;
     uint64_t ram_size;
+    int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
     ram_addr_t ddr_low_size, ddr_high_size;
     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 
     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
-    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
+    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
 
     /* Realize APUs before realizing the GIC. KVM requires this.  */
-    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
+    for (i = 0; i < num_apus; i++) {
         char *name;
 
         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
         }
     }
 
-    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
+    for (i = 0; i < num_apus; i++) {
         qemu_irq irq;
 
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
     }
 
     if (s->has_rpu) {
-        xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
-        if (err) {
-            error_propagate(errp, err);
-            return;
-        }
+        info_report("The 'has_rpu' property is no longer required, to use the "
+                    "RPUs just use -smp 6.");
+    }
+
+    xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
     }
 
     if (!s->boot_cpu_ptr) {
-- 
2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

The EP108 was an early access development board that is no longer used.
Add an info message to convert any users to the ZCU102 instead. On QEMU
they are both identical.

This patch also updated the qemu-doc.texi file to indicate that the
EP108 has been deprecated.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Message-id: 1510343626-25861-4-git-send-email-cota@braap.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-zcu102.c | 3 +++
 qemu-doc.texi        | 7 +++++++
 2 files changed, 10 insertions(+)

diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)
 {
     XlnxZCU102 *s = EP108_MACHINE(machine);
 
+    info_report("The Xilinx EP108 machine is deprecated, please use the "
+                "ZCU102 machine instead. It has the same features supported.");
+
     xlnx_zynqmp_init(s, machine);
 }
 
diff --git a/qemu-doc.texi b/qemu-doc.texi
index XXXXXXX..XXXXXXX 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -XXX,XX +XXX,XX @@ or ``ivshmem-doorbell`` device types.
 The ``spapr-pci-vfio-host-bridge'' device type is replaced by
 the ``spapr-pci-host-bridge'' device type.
 
+@section System emulator machines
+
+@subsection Xilinx EP108 (since 2.11.0)
+
+The ``xlnx-ep108'' machine has been replaced by the ``xlnx-zcu102'' machine.
+The ``xlnx-zcu102'' machine has the same features and capabilites in QEMU.
+
 @node License
 @appendix License
 
-- 
2.7.4

From: "Emilio G. Cota" <cota@braap.org>

max_cpus needs to be an upper bound on the number of vCPUs
initialized; otherwise TCG region initialization breaks.

Some boards initialize a hard-coded number of vCPUs, which is not
captured by the global max_cpus and therefore breaks TCG initialization.
Fix it by adding the .min_cpus field to machine_class.

This commit also changes some user-facing behaviour: we now die if
-smp is below this hard-coded vCPU minimum instead of silently
ignoring the passed -smp value (sometimes announcing this by printing
a warning). However, the introduction of .default_cpus lessens the
likelihood that users will notice this: if -smp isn't set, we now
assign the value in .default_cpus to both smp_cpus and max_cpus. IOW,
if a user does not set -smp, they always get a correct number of vCPUs.

This change fixes 3468b59 ("tcg: enable multiple TCG contexts in
softmmu", 2017-10-24), which broke TCG initialization for some
ARM boards.

Fixes: 3468b59e18b179bc63c7ce934de912dfa9596122
Reported-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-id: 1510343626-25861-6-git-send-email-cota@braap.org
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/boards.h     |  5 +++++
 hw/arm/exynos4_boards.c | 12 ++++--------
 hw/arm/raspi.c          |  2 ++
 hw/arm/xlnx-zcu102.c    |  2 ++
 vl.c                    | 21 ++++++++++++++++++---
 5 files changed, 31 insertions(+), 11 deletions(-)

diff --git a/include/hw/boards.h b/include/hw/boards.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 /**
  * MachineClass:
+ * @max_cpus: maximum number of CPUs supported. Default: 1
+ * @min_cpus: minimum number of CPUs supported. Default: 1
+ * @default_cpus: number of CPUs instantiated if none are specified. Default: 1
  * @get_hotplug_handler: this function is called during bus-less
  *    device hotplug. If defined it returns pointer to an instance
  *    of HotplugHandler object, which handles hotplug operation
@@ -XXX,XX +XXX,XX @@ struct MachineClass {
     BlockInterfaceType block_default_type;
     int units_per_default_bus;
     int max_cpus;
+    int min_cpus;
+    int default_cpus;
     unsigned int no_serial:1,
         no_parallel:1,
         use_virtcon:1,
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "sysemu/sysemu.h"
-#include "sysemu/qtest.h"
 #include "hw/sysbus.h"
 #include "net/net.h"
 #include "hw/arm/arm.h"
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
                            Exynos4BoardType board_type)
 {
     Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
-    MachineClass *mc = MACHINE_GET_CLASS(machine);
-
-    if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
-        error_report("%s board supports only %d CPU cores, ignoring smp_cpus"
-                     " value",
-                     mc->name, EXYNOS4210_NCPUS);
-    }
 
     exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
     exynos4_board_binfo.board_id = exynos4_board_id[board_type];
@@ -XXX,XX +XXX,XX @@ static void nuri_class_init(ObjectClass *oc, void *data)
     mc->desc = "Samsung NURI board (Exynos4210)";
     mc->init = nuri_init;
     mc->max_cpus = EXYNOS4210_NCPUS;
+    mc->min_cpus = EXYNOS4210_NCPUS;
+    mc->default_cpus = EXYNOS4210_NCPUS;
     mc->ignore_memory_transaction_failures = true;
 }
 
@@ -XXX,XX +XXX,XX @@ static void smdkc210_class_init(ObjectClass *oc, void *data)
     mc->desc = "Samsung SMDKC210 board (Exynos4210)";
     mc->init = smdkc210_init;
     mc->max_cpus = EXYNOS4210_NCPUS;
+    mc->min_cpus = EXYNOS4210_NCPUS;
+    mc->default_cpus = EXYNOS4210_NCPUS;
     mc->ignore_memory_transaction_failures = true;
 }
 
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->max_cpus = BCM2836_NCPUS;
+    mc->min_cpus = BCM2836_NCPUS;
+    mc->default_cpus = BCM2836_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
     mc->ignore_memory_transaction_failures = true;
 };
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
     mc->units_per_default_bus = 1;
     mc->ignore_memory_transaction_failures = true;
     mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
+    mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
 }
 
 static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
     mc->units_per_default_bus = 1;
     mc->ignore_memory_transaction_failures = true;
     mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
+    mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
 }
 
 static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
diff --git a/vl.c b/vl.c
index XXXXXXX..XXXXXXX 100644
--- a/vl.c
+++ b/vl.c
@@ -XXX,XX +XXX,XX @@ Chardev *virtcon_hds[MAX_VIRTIO_CONSOLES];
 Chardev *sclp_hds[MAX_SCLP_CONSOLES];
 int win2k_install_hack = 0;
 int singlestep = 0;
-int smp_cpus = 1;
-unsigned int max_cpus = 1;
+int smp_cpus;
+unsigned int max_cpus;
 int smp_cores = 1;
 int smp_threads = 1;
 int acpi_enabled = 1;
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp)
         exit(0);
     }
 
+    /* machine_class: default to UP */
+    machine_class->max_cpus = machine_class->max_cpus ?: 1;
+    machine_class->min_cpus = machine_class->min_cpus ?: 1;
+    machine_class->default_cpus = machine_class->default_cpus ?: 1;
+
+    /* default to machine_class->default_cpus */
+    smp_cpus = machine_class->default_cpus;
+    max_cpus = machine_class->default_cpus;
+
     smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
 
-    machine_class->max_cpus = machine_class->max_cpus ?: 1; /* Default to UP */
+    /* sanity-check smp_cpus and max_cpus against machine_class */
+    if (smp_cpus < machine_class->min_cpus) {
+        error_report("Invalid SMP CPUs %d. The min CPUs "
+                     "supported by machine '%s' is %d", smp_cpus,
+                     machine_class->name, machine_class->min_cpus);
+        exit(1);
+    }
     if (max_cpus > machine_class->max_cpus) {
         error_report("Invalid SMP CPUs %d. The max CPUs "
                      "supported by machine '%s' is %d", max_cpus,
-- 
2.7.4

From: Alex Bennée <alex.bennee@linaro.org>

We are still seeing signals during translation time when we walk over
a page protection boundary. This expands the check to ensure the host
PC is inside the code generation buffer. The original suggestion was
to check versus tcg_ctx.code_gen_ptr but as we now segment the
translation buffer we have to settle for just a general check for
being inside.

I've also fixed up the declaration to make it clear it can deal with
invalid addresses. A later patch will fix up the call sites.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20171108153245.20740-2-alex.bennee@linaro.org
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Tested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/exec-all.h   | 11 ++++++++++
 accel/tcg/translate-all.c | 52 ++++++++++++++++++++++++++---------------------
 2 files changed, 40 insertions(+), 23 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
                           target_ulong *data);
 
 void cpu_gen_init(void);
+
+/**
+ * cpu_restore_state:
+ * @cpu: the vCPU state is to be restore to
+ * @searched_pc: the host PC the fault occurred at
+ * @return: true if state was restored, false otherwise
+ *
+ * Attempt to restore the state for a fault occurring in translated
+ * code. If the searched_pc is not in translated code no state is
+ * restored and the function returns false.
+ */
 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
 
 void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
     return 0;
 }
 
-bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
+bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
 {
     TranslationBlock *tb;
     bool r = false;
+    uintptr_t check_offset;
 
-    /* A retaddr of zero is invalid so we really shouldn't have ended
-     * up here. The target code has likely forgotten to check retaddr
-     * != 0 before attempting to restore state. We return early to
-     * avoid blowing up on a recursive tb_lock(). The target must have
-     * previously survived a failed cpu_restore_state because
-     * tb_find_pc(0) would have failed anyway. It still should be
-     * fixed though.
+    /* The host_pc has to be in the region of current code buffer. If
+     * it is not we will not be able to resolve it here. The two cases
+     * where host_pc will not be correct are:
+     *
+     *  - fault during translation (instruction fetch)
+     *  - fault from helper (not using GETPC() macro)
+     *
+     * Either way we need return early to avoid blowing up on a
+     * recursive tb_lock() as we can't resolve it here.
+     *
+     * We are using unsigned arithmetic so if host_pc <
+     * tcg_init_ctx.code_gen_buffer check_offset will wrap to way
+     * above the code_gen_buffer_size
      */
-
-    if (!retaddr) {
-        return r;
-    }
-
-    tb_lock();
-    tb = tb_find_pc(retaddr);
-    if (tb) {
-        cpu_restore_state_from_tb(cpu, tb, retaddr);
-        if (tb->cflags & CF_NOCACHE) {
-            /* one-shot translation, invalidate it immediately */
-            tb_phys_invalidate(tb, -1);
-            tb_remove(tb);
+    check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer;
+
+    if (check_offset < tcg_init_ctx.code_gen_buffer_size) {
+        tb_lock();
+        tb = tb_find_pc(host_pc);
+        if (tb) {
+            cpu_restore_state_from_tb(cpu, tb, host_pc);
+            if (tb->cflags & CF_NOCACHE) {
+                /* one-shot translation, invalidate it immediately */
+                tb_phys_invalidate(tb, -1);
+                tb_remove(tb);
+            }
+            r = true;
         }
-        r = true;
+        tb_unlock();
     }
-    tb_unlock();
 
     return r;
 }
-- 
2.7.4

target-arm queue: two bug fixes, plus the KVM/SVE patchset,
which is a new feature but one which was in my pre-softfreeze
pullreq (it just had to be dropped due to an unexpected test failure.)

thanks
-- PMM

The following changes since commit b7c9a7f353c0e260519bf735ff0d4aa01e72784b:

Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2019-10-31 15:57:30 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191101-1

for you to fetch changes up to d9ae7624b659362cb2bb2b04fee53bf50829ca56:

target/arm: Allow reading flags from FPSCR for M-profile (2019-11-01 08:49:10 +0000)

----------------------------------------------------------------
target-arm queue:
 * Support SVE in KVM guests
 * Don't UNDEF on M-profile 'vmrs apsr_nzcv, fpscr'
 * Update hflags after boot.c modifies CPU state

----------------------------------------------------------------
Andrew Jones (9):
      target/arm/monitor: Introduce qmp_query_cpu_model_expansion
      tests: arm: Introduce cpu feature tests
      target/arm: Allow SVE to be disabled via a CPU property
      target/arm/cpu64: max cpu: Introduce sve<N> properties
      target/arm/kvm64: Add kvm_arch_get/put_sve
      target/arm/kvm64: max cpu: Enable SVE when available
      target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features
      target/arm/cpu64: max cpu: Support sve properties with KVM
      target/arm/kvm: host cpu: Add support for sve<N> properties

Christophe Lyon (1):
      target/arm: Allow reading flags from FPSCR for M-profile

Edgar E. Iglesias (1):
      hw/arm/boot: Rebuild hflags when modifying CPUState at boot

From: Andrew Jones <drjones@redhat.com>

Add support for the query-cpu-model-expansion QMP command to Arm. We
do this selectively, only exposing CPU properties which represent
optional CPU features which the user may want to enable/disable.
Additionally we restrict the list of queryable cpu models to 'max',
'host', or the current type when KVM is in use. And, finally, we only
implement expansion type 'full', as Arm does not yet have a "base"
CPU type. More details and example queries are described in a new
document (docs/arm-cpu-features.rst).

Note, certainly more features may be added to the list of advertised
features, e.g. 'vfp' and 'neon'. The only requirement is that we can
detect invalid configurations and emit failures at QMP query time.
For 'vfp' and 'neon' this will require some refactoring to share a
validation function between the QMP query and the CPU realize
functions.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 qapi/machine-target.json  |   6 +-
 target/arm/monitor.c      | 146 ++++++++++++++++++++++++++++++++++++++
 docs/arm-cpu-features.rst | 137 +++++++++++++++++++++++++++++++++++
 3 files changed, 286 insertions(+), 3 deletions(-)
 create mode 100644 docs/arm-cpu-features.rst

diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index XXXXXXX..XXXXXXX 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -XXX,XX +XXX,XX @@
 ##
 { 'struct': 'CpuModelExpansionInfo',
   'data': { 'model': 'CpuModelInfo' },
-  'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
+  'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
 
 ##
 # @query-cpu-model-expansion:
@@ -XXX,XX +XXX,XX @@
 #   query-cpu-model-expansion while using these is not advised.
 #
 # Some architectures may not support all expansion types. s390x supports
-# "full" and "static".
+# "full" and "static". Arm only supports "full".
 #
 # Returns: a CpuModelExpansionInfo. Returns an error if expanding CPU models is
 #          not supported, if the model cannot be expanded, if the model contains
@@ -XXX,XX +XXX,XX @@
   'data': { 'type': 'CpuModelExpansionType',
             'model': 'CpuModelInfo' },
   'returns': 'CpuModelExpansionInfo',
-  'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
+  'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
 
 ##
 # @CpuDefinitionInfo:
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/boards.h"
 #include "kvm_arm.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "qapi/qobject-input-visitor.h"
+#include "qapi/qapi-commands-machine-target.h"
 #include "qapi/qapi-commands-misc-target.h"
+#include "qapi/qmp/qerror.h"
+#include "qapi/qmp/qdict.h"
+#include "qom/qom-qobject.h"
 
 static GICCapability *gic_cap_new(int version)
 {
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
 
     return head;
 }
+
+/*
+ * These are cpu model features we want to advertise. The order here
+ * matters as this is the order in which qmp_query_cpu_model_expansion
+ * will attempt to set them. If there are dependencies between features,
+ * then the order that considers those dependencies must be used.
+ */
+static const char *cpu_model_advertised_features[] = {
+    "aarch64", "pmu",
+    NULL
+};
+
+CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
+                                                     CpuModelInfo *model,
+                                                     Error **errp)
+{
+    CpuModelExpansionInfo *expansion_info;
+    const QDict *qdict_in = NULL;
+    QDict *qdict_out;
+    ObjectClass *oc;
+    Object *obj;
+    const char *name;
+    int i;
+
+    if (type != CPU_MODEL_EXPANSION_TYPE_FULL) {
+        error_setg(errp, "The requested expansion type is not supported");
+        return NULL;
+    }
+
+    if (!kvm_enabled() && !strcmp(model->name, "host")) {
+        error_setg(errp, "The CPU type '%s' requires KVM", model->name);
+        return NULL;
+    }
+
+    oc = cpu_class_by_name(TYPE_ARM_CPU, model->name);
+    if (!oc) {
+        error_setg(errp, "The CPU type '%s' is not a recognized ARM CPU type",
+                   model->name);
+        return NULL;
+    }
+
+    if (kvm_enabled()) {
+        const char *cpu_type = current_machine->cpu_type;
+        int len = strlen(cpu_type) - strlen(ARM_CPU_TYPE_SUFFIX);
+        bool supported = false;
+
+        if (!strcmp(model->name, "host") || !strcmp(model->name, "max")) {
+            /* These are kvmarm's recommended cpu types */
+            supported = true;
+        } else if (strlen(model->name) == len &&
+                   !strncmp(model->name, cpu_type, len)) {
+            /* KVM is enabled and we're using this type, so it works. */
+            supported = true;
+        }
+        if (!supported) {
+            error_setg(errp, "We cannot guarantee the CPU type '%s' works "
+                             "with KVM on this host", model->name);
+            return NULL;
+        }
+    }
+
+    if (model->props) {
+        qdict_in = qobject_to(QDict, model->props);
+        if (!qdict_in) {
+            error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");
+            return NULL;
+        }
+    }
+
+    obj = object_new(object_class_get_name(oc));
+
+    if (qdict_in) {
+        Visitor *visitor;
+        Error *err = NULL;
+
+        visitor = qobject_input_visitor_new(model->props);
+        visit_start_struct(visitor, NULL, NULL, 0, &err);
+        if (err) {
+            visit_free(visitor);
+            object_unref(obj);
+            error_propagate(errp, err);
+            return NULL;
+        }
+
+        i = 0;
+        while ((name = cpu_model_advertised_features[i++]) != NULL) {
+            if (qdict_get(qdict_in, name)) {
+                object_property_set(obj, visitor, name, &err);
+                if (err) {
+                    break;
+                }
+            }
+        }
+
+        if (!err) {
+            visit_check_struct(visitor, &err);
+        }
+        visit_end_struct(visitor, NULL);
+        visit_free(visitor);
+        if (err) {
+            object_unref(obj);
+            error_propagate(errp, err);
+            return NULL;
+        }
+    }
+
+    expansion_info = g_new0(CpuModelExpansionInfo, 1);
+    expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
+    expansion_info->model->name = g_strdup(model->name);
+
+    qdict_out = qdict_new();
+
+    i = 0;
+    while ((name = cpu_model_advertised_features[i++]) != NULL) {
+        ObjectProperty *prop = object_property_find(obj, name, NULL);
+        if (prop) {
+            Error *err = NULL;
+            QObject *value;
+
+            assert(prop->get);
+            value = object_property_get_qobject(obj, name, &err);
+            assert(!err);
+
+            qdict_put_obj(qdict_out, name, value);
+        }
+    }
+
+    if (!qdict_size(qdict_out)) {
+        qobject_unref(qdict_out);
+    } else {
+        expansion_info->model->props = QOBJECT(qdict_out);
+        expansion_info->model->has_props = true;
+    }
+
+    object_unref(obj);
+
+    return expansion_info;
+}
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@
+================
+ARM CPU Features
+================
+
+Examples of probing and using ARM CPU features
+
+Introduction
+============
+
+CPU features are optional features that a CPU of supporting type may
+choose to implement or not.  In QEMU, optional CPU features have
+corresponding boolean CPU proprieties that, when enabled, indicate
+that the feature is implemented, and, conversely, when disabled,
+indicate that it is not implemented. An example of an ARM CPU feature
+is the Performance Monitoring Unit (PMU).  CPU types such as the
+Cortex-A15 and the Cortex-A57, which respectively implement ARM
+architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
+implement PMUs.  For example, if a user wants to use a Cortex-A15 without
+a PMU, then the `-cpu` parameter should contain `pmu=off` on the QEMU
+command line, i.e. `-cpu cortex-a15,pmu=off`.
+
+As not all CPU types support all optional CPU features, then whether or
+not a CPU property exists depends on the CPU type.  For example, CPUs
+that implement the ARMv8-A architecture reference manual may optionally
+support the AArch32 CPU feature, which may be enabled by disabling the
+`aarch64` CPU property.  A CPU type such as the Cortex-A15, which does
+not implement ARMv8-A, will not have the `aarch64` CPU property.
+
+QEMU's support may be limited for some CPU features, only partially
+supporting the feature or only supporting the feature under certain
+configurations.  For example, the `aarch64` CPU feature, which, when
+disabled, enables the optional AArch32 CPU feature, is only supported
+when using the KVM accelerator and when running on a host CPU type that
+supports the feature.
+
+CPU Feature Probing
+===================
+
+Determining which CPU features are available and functional for a given
+CPU type is possible with the `query-cpu-model-expansion` QMP command.
+Below are some examples where `scripts/qmp/qmp-shell` (see the top comment
+block in the script for usage) is used to issue the QMP commands.
+
+(1) Determine which CPU features are available for the `max` CPU type
+    (Note, we started QEMU with qemu-system-aarch64, so `max` is
+     implementing the ARMv8-A reference manual in this case)::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
+      { "return": {
+        "model": { "name": "max", "props": {
+        "pmu": true, "aarch64": true
+      }}}}
+
+We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
+We also see that the CPU features are enabled, as they are all `true`.
+
+(2) Let's try to disable the PMU::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
+      { "return": {
+        "model": { "name": "max", "props": {
+        "pmu": false, "aarch64": true
+      }}}}
+
+We see it worked, as `pmu` is now `false`.
+
+(3) Let's try to disable `aarch64`, which enables the AArch32 CPU feature::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"aarch64":false}}
+      {"error": {
+       "class": "GenericError", "desc":
+       "'aarch64' feature cannot be disabled unless KVM is enabled and 32-bit EL1 is supported"
+      }}
+
+It looks like this feature is limited to a configuration we do not
+currently have.
+
+(4) Let's try probing CPU features for the Cortex-A15 CPU type::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
+      {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
+
+Only the `pmu` CPU feature is available.
+
+A note about CPU feature dependencies
+-------------------------------------
+
+It's possible for features to have dependencies on other features. I.e.
+it may be possible to change one feature at a time without error, but
+when attempting to change all features at once an error could occur
+depending on the order they are processed.  It's also possible changing
+all at once doesn't generate an error, because a feature's dependencies
+are satisfied with other features, but the same feature cannot be changed
+independently without error.  For these reasons callers should always
+attempt to make their desired changes all at once in order to ensure the
+collection is valid.
+
+A note about CPU models and KVM
+-------------------------------
+
+Named CPU models generally do not work with KVM.  There are a few cases
+that do work, e.g. using the named CPU model `cortex-a57` with KVM on a
+seattle host, but mostly if KVM is enabled the `host` CPU type must be
+used.  This means the guest is provided all the same CPU features as the
+host CPU type has.  And, for this reason, the `host` CPU type should
+enable all CPU features that the host has by default.  Indeed it's even
+a bit strange to allow disabling CPU features that the host has when using
+the `host` CPU type, but in the absence of CPU models it's the best we can
+do if we want to launch guests without all the host's CPU features enabled.
+
+Enabling KVM also affects the `query-cpu-model-expansion` QMP command.  The
+affect is not only limited to specific features, as pointed out in example
+(3) of "CPU Feature Probing", but also to which CPU types may be expanded.
+When KVM is enabled, only the `max`, `host`, and current CPU type may be
+expanded.  This restriction is necessary as it's not possible to know all
+CPU types that may work with KVM, but it does impose a small risk of users
+experiencing unexpected errors.  For example on a seattle, as mentioned
+above, the `cortex-a57` CPU type is also valid when KVM is enabled.
+Therefore a user could use the `host` CPU type for the current type, but
+then attempt to query `cortex-a57`, however that query will fail with our
+restrictions.  This shouldn't be an issue though as management layers and
+users have been preferring the `host` CPU type for use with KVM for quite
+some time.  Additionally, if the KVM-enabled QEMU instance running on a
+seattle host is using the `cortex-a57` CPU type, then querying `cortex-a57`
+will work.
+
+Using CPU Features
+==================
+
+After determining which CPU features are available and supported for a
+given CPU type, then they may be selectively enabled or disabled on the
+QEMU command line with that CPU type::
+
+  $ qemu-system-aarch64 -M virt -cpu max,pmu=off
+
+The example above disables the PMU for the `max` CPU type.
+
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Now that Arm CPUs have advertised features lets add tests to ensure
we maintain their expected availability with and without KVM.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20191031142734.8590-3-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/Makefile.include   |   5 +-
 tests/arm-cpu-features.c | 253 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 257 insertions(+), 1 deletion(-)
 create mode 100644 tests/arm-cpu-features.c

diff --git a/tests/Makefile.include b/tests/Makefile.include
index XXXXXXX..XXXXXXX 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -XXX,XX +XXX,XX @@ check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
 check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
 check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
 
+check-qtest-arm-y += tests/arm-cpu-features$(EXESUF)
 check-qtest-arm-y += tests/microbit-test$(EXESUF)
 check-qtest-arm-y += tests/m25p80-test$(EXESUF)
 check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
@@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
 check-qtest-arm-y += tests/hexloader-test$(EXESUF)
 check-qtest-arm-$(CONFIG_PFLASH_CFI02) += tests/pflash-cfi02-test$(EXESUF)
 
-check-qtest-aarch64-y = tests/numa-test$(EXESUF)
+check-qtest-aarch64-y += tests/arm-cpu-features$(EXESUF)
+check-qtest-aarch64-y += tests/numa-test$(EXESUF)
 check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF)
 check-qtest-aarch64-y += tests/migration-test$(EXESUF)
 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional
@@ -XXX,XX +XXX,XX @@ tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y)
 tests/numa-test$(EXESUF): tests/numa-test.o
 tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o
 tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y)
+tests/arm-cpu-features$(EXESUF): tests/arm-cpu-features.o
 
 tests/migration/stress$(EXESUF): tests/migration/stress.o
 	$(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@")
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Arm CPU feature test cases
+ *
+ * Copyright (c) 2019 Red Hat Inc.
+ * Authors:
+ *  Andrew Jones <drjones@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/qmp/qjson.h"
+
+#define MACHINE     "-machine virt,gic-version=max,accel=tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
+#define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
+                    "  'arguments': { 'type': 'full', "
+#define QUERY_TAIL  "}}"
+
+static bool kvm_enabled(QTestState *qts)
+{
+    QDict *resp, *qdict;
+    bool enabled;
+
+    resp = qtest_qmp(qts, "{ 'execute': 'query-kvm' }");
+    g_assert(qdict_haskey(resp, "return"));
+    qdict = qdict_get_qdict(resp, "return");
+    g_assert(qdict_haskey(qdict, "enabled"));
+    enabled = qdict_get_bool(qdict, "enabled");
+    qobject_unref(resp);
+
+    return enabled;
+}
+
+static QDict *do_query_no_props(QTestState *qts, const char *cpu_type)
+{
+    return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }"
+                          QUERY_TAIL, cpu_type);
+}
+
+static QDict *do_query(QTestState *qts, const char *cpu_type,
+                       const char *fmt, ...)
+{
+    QDict *resp;
+
+    if (fmt) {
+        QDict *args;
+        va_list ap;
+
+        va_start(ap, fmt);
+        args = qdict_from_vjsonf_nofail(fmt, ap);
+        va_end(ap);
+
+        resp = qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s, "
+                                                    "'props': %p }"
+                              QUERY_TAIL, cpu_type, args);
+    } else {
+        resp = do_query_no_props(qts, cpu_type);
+    }
+
+    return resp;
+}
+
+static const char *resp_get_error(QDict *resp)
+{
+    QDict *qdict;
+
+    g_assert(resp);
+
+    qdict = qdict_get_qdict(resp, "error");
+    if (qdict) {
+        return qdict_get_str(qdict, "desc");
+    }
+
+    return NULL;
+}
+
+#define assert_error(qts, cpu_type, expected_error, fmt, ...)          \
+({                                                                     \
+    QDict *_resp;                                                      \
+    const char *_error;                                                \
+                                                                       \
+    _resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__);               \
+    g_assert(_resp);                                                   \
+    _error = resp_get_error(_resp);                                    \
+    g_assert(_error);                                                  \
+    g_assert(g_str_equal(_error, expected_error));                     \
+    qobject_unref(_resp);                                              \
+})
+
+static bool resp_has_props(QDict *resp)
+{
+    QDict *qdict;
+
+    g_assert(resp);
+
+    if (!qdict_haskey(resp, "return")) {
+        return false;
+    }
+    qdict = qdict_get_qdict(resp, "return");
+
+    if (!qdict_haskey(qdict, "model")) {
+        return false;
+    }
+    qdict = qdict_get_qdict(qdict, "model");
+
+    return qdict_haskey(qdict, "props");
+}
+
+static QDict *resp_get_props(QDict *resp)
+{
+    QDict *qdict;
+
+    g_assert(resp);
+    g_assert(resp_has_props(resp));
+
+    qdict = qdict_get_qdict(resp, "return");
+    qdict = qdict_get_qdict(qdict, "model");
+    qdict = qdict_get_qdict(qdict, "props");
+
+    return qdict;
+}
+
+#define assert_has_feature(qts, cpu_type, feature)                     \
+({                                                                     \
+    QDict *_resp = do_query_no_props(qts, cpu_type);                   \
+    g_assert(_resp);                                                   \
+    g_assert(resp_has_props(_resp));                                   \
+    g_assert(qdict_get(resp_get_props(_resp), feature));               \
+    qobject_unref(_resp);                                              \
+})
+
+#define assert_has_not_feature(qts, cpu_type, feature)                 \
+({                                                                     \
+    QDict *_resp = do_query_no_props(qts, cpu_type);                   \
+    g_assert(_resp);                                                   \
+    g_assert(!resp_has_props(_resp) ||                                 \
+             !qdict_get(resp_get_props(_resp), feature));              \
+    qobject_unref(_resp);                                              \
+})
+
+static void assert_type_full(QTestState *qts)
+{
+    const char *error;
+    QDict *resp;
+
+    resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
+                            "'arguments': { 'type': 'static', "
+                                           "'model': { 'name': 'foo' }}}");
+    g_assert(resp);
+    error = resp_get_error(resp);
+    g_assert(error);
+    g_assert(g_str_equal(error,
+                         "The requested expansion type is not supported"));
+    qobject_unref(resp);
+}
+
+static void assert_bad_props(QTestState *qts, const char *cpu_type)
+{
+    const char *error;
+    QDict *resp;
+
+    resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
+                            "'arguments': { 'type': 'full', "
+                                           "'model': { 'name': %s, "
+                                                      "'props': false }}}",
+                     cpu_type);
+    g_assert(resp);
+    error = resp_get_error(resp);
+    g_assert(error);
+    g_assert(g_str_equal(error,
+                         "Invalid parameter type for 'props', expected: dict"));
+    qobject_unref(resp);
+}
+
+static void test_query_cpu_model_expansion(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE "-cpu max");
+
+    /* Test common query-cpu-model-expansion input validation */
+    assert_type_full(qts);
+    assert_bad_props(qts, "max");
+    assert_error(qts, "foo", "The CPU type 'foo' is not a recognized "
+                 "ARM CPU type", NULL);
+    assert_error(qts, "max", "Parameter 'not-a-prop' is unexpected",
+                 "{ 'not-a-prop': false }");
+    assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
+
+    /* Test expected feature presence/absence for some cpu types */
+    assert_has_feature(qts, "max", "pmu");
+    assert_has_feature(qts, "cortex-a15", "pmu");
+    assert_has_not_feature(qts, "cortex-a15", "aarch64");
+
+    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        assert_has_feature(qts, "max", "aarch64");
+        assert_has_feature(qts, "cortex-a57", "pmu");
+        assert_has_feature(qts, "cortex-a57", "aarch64");
+
+        /* Test that features that depend on KVM generate errors without. */
+        assert_error(qts, "max",
+                     "'aarch64' feature cannot be disabled "
+                     "unless KVM is enabled and 32-bit EL1 "
+                     "is supported",
+                     "{ 'aarch64': false }");
+    }
+
+    qtest_quit(qts);
+}
+
+static void test_query_cpu_model_expansion_kvm(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE_KVM "-cpu max");
+
+    /*
+     * These tests target the 'host' CPU type, so KVM must be enabled.
+     */
+    if (!kvm_enabled(qts)) {
+        qtest_quit(qts);
+        return;
+    }
+
+    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        assert_has_feature(qts, "host", "aarch64");
+        assert_has_feature(qts, "host", "pmu");
+
+        assert_error(qts, "cortex-a15",
+            "We cannot guarantee the CPU type 'cortex-a15' works "
+            "with KVM on this host", NULL);
+    } else {
+        assert_has_not_feature(qts, "host", "aarch64");
+        assert_has_not_feature(qts, "host", "pmu");
+    }
+
+    qtest_quit(qts);
+}
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    qtest_add_data_func("/arm/query-cpu-model-expansion",
+                        NULL, test_query_cpu_model_expansion);
+    qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
+                        NULL, test_query_cpu_model_expansion_kvm);
+
+    return g_test_run();
+}
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via
a CPU property") we can disable the 'max' cpu model's VFP and neon
features, but there's no way to disable SVE. Add the 'sve=on|off'
property to give it that flexibility. We also rename
cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them
to follow the typical *_get/set_<property-name> pattern.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c         |  3 ++-
 target/arm/cpu64.c       | 52 ++++++++++++++++++++++++++++++++++------
 target/arm/monitor.c     |  2 +-
 tests/arm-cpu-features.c |  1 +
 4 files changed, 49 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
         env->cp15.cptr_el[3] |= CPTR_EZ;
         /* with maximum vector length */
-        env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
+        env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
+                             cpu->sve_max_vq - 1 : 0;
         env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
         env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
         /*
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 }
 
-static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
-                               void *opaque, Error **errp)
+static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
+    uint32_t value;
+
+    /* All vector lengths are disabled when SVE is off. */
+    if (!cpu_isar_feature(aa64_sve, cpu)) {
+        value = 0;
+    } else {
+        value = cpu->sve_max_vq;
+    }
+    visit_type_uint32(v, name, &value, errp);
 }
 
-static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
-                               void *opaque, Error **errp)
+static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
     error_propagate(errp, err);
 }
 
+static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    bool value = cpu_isar_feature(aa64_sve, cpu);
+
+    visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    Error *err = NULL;
+    bool value;
+    uint64_t t;
+
+    visit_type_bool(v, name, &value, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    t = cpu->isar.id_aa64pfr0;
+    t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
+    cpu->isar.id_aa64pfr0 = t;
+}
+
 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
  * otherwise, a CPU with as many features enabled as our emulation supports.
  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 #endif
 
         cpu->sve_max_vq = ARM_MAX_VQ;
-        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
-                            cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
+        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
+                            cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
+        object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
+                            cpu_arm_set_sve, NULL, NULL, &error_fatal);
     }
 }
 
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
  * then the order that considers those dependencies must be used.
  */
 static const char *cpu_model_advertised_features[] = {
-    "aarch64", "pmu",
+    "aarch64", "pmu", "sve",
     NULL
 };
 
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
         assert_has_feature(qts, "max", "aarch64");
+        assert_has_feature(qts, "max", "sve");
         assert_has_feature(qts, "cortex-a57", "pmu");
         assert_has_feature(qts, "cortex-a57", "aarch64");
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.

Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document.  If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.

This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/qemu/bitops.h     |   1 +
 target/arm/cpu.h          |  19 ++++
 target/arm/cpu.c          |  19 ++++
 target/arm/cpu64.c        | 192 ++++++++++++++++++++++++++++++++++++-
 target/arm/helper.c       |  10 +-
 target/arm/monitor.c      |  12 +++
 tests/arm-cpu-features.c  | 194 ++++++++++++++++++++++++++++++++++++++
 docs/arm-cpu-features.rst | 168 +++++++++++++++++++++++++++++++--
 8 files changed, 606 insertions(+), 9 deletions(-)

diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -XXX,XX +XXX,XX @@
 #define BITS_PER_LONG           (sizeof (unsigned long) * BITS_PER_BYTE)
 
 #define BIT(nr)                 (1UL << (nr))
+#define BIT_ULL(nr)             (1ULL << (nr))
 #define BIT_MASK(nr)            (1UL << ((nr) % BITS_PER_LONG))
 #define BIT_WORD(nr)            ((nr) / BITS_PER_LONG)
 #define BITS_TO_LONGS(nr)       DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 #ifdef TARGET_AARCH64
 # define ARM_MAX_VQ    16
+void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
+uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
 #else
 # define ARM_MAX_VQ    1
+static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
+static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
+{ return 0; }
 #endif
 
 typedef struct ARMVectorReg {
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
 
     /* Used to set the maximum vector length the cpu will support.  */
     uint32_t sve_max_vq;
+
+    /*
+     * In sve_vq_map each set bit is a supported vector length of
+     * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
+     * length in quadwords.
+     *
+     * While processing properties during initialization, corresponding
+     * sve_vq_init bits are set for bits in sve_vq_map that have been
+     * set by properties.
+     */
+    DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
+    DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
 };
 
 void arm_cpu_post_init(Object *obj);
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
     return (env->features & (1ULL << feature)) != 0;
 }
 
+void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
+
 #if !defined(CONFIG_USER_ONLY)
 /* Return true if exception levels below EL3 are in secure state,
  * or would be following an exception return to that level.
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
 #endif
 }
 
+void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
+{
+    Error *local_err = NULL;
+
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        arm_cpu_sve_finalize(cpu, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
+            return;
+        }
+    }
+}
+
 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         return;
     }
 
+    arm_cpu_finalize_features(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
     if (arm_feature(env, ARM_FEATURE_AARCH64) &&
         cpu->has_vfp != cpu->has_neon) {
         /*
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 }
 
+void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+{
+    /*
+     * If any vector lengths are explicitly enabled with sve<N> properties,
+     * then all other lengths are implicitly disabled.  If sve-max-vq is
+     * specified then it is the same as explicitly enabling all lengths
+     * up to and including the specified maximum, which means all larger
+     * lengths will be implicitly disabled.  If no sve<N> properties
+     * are enabled and sve-max-vq is not specified, then all lengths not
+     * explicitly disabled will be enabled.  Additionally, all power-of-two
+     * vector lengths less than the maximum enabled length will be
+     * automatically enabled and all vector lengths larger than the largest
+     * disabled power-of-two vector length will be automatically disabled.
+     * Errors are generated if the user provided input that interferes with
+     * any of the above.  Finally, if SVE is not disabled, then at least one
+     * vector length must be enabled.
+     */
+    DECLARE_BITMAP(tmp, ARM_MAX_VQ);
+    uint32_t vq, max_vq = 0;
+
+    /*
+     * Process explicit sve<N> properties.
+     * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
+     * Check first for any sve<N> enabled.
+     */
+    if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) {
+        max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1;
+
+        if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
+            error_setg(errp, "cannot enable sve%d", max_vq * 128);
+            error_append_hint(errp, "sve%d is larger than the maximum vector "
+                              "length, sve-max-vq=%d (%d bits)\n",
+                              max_vq * 128, cpu->sve_max_vq,
+                              cpu->sve_max_vq * 128);
+            return;
+        }
+
+        /* Propagate enabled bits down through required powers-of-two. */
+        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
+            if (!test_bit(vq - 1, cpu->sve_vq_init)) {
+                set_bit(vq - 1, cpu->sve_vq_map);
+            }
+        }
+    } else if (cpu->sve_max_vq == 0) {
+        /*
+         * No explicit bits enabled, and no implicit bits from sve-max-vq.
+         */
+        if (!cpu_isar_feature(aa64_sve, cpu)) {
+            /* SVE is disabled and so are all vector lengths.  Good. */
+            return;
+        }
+
+        /* Disabling a power-of-two disables all larger lengths. */
+        if (test_bit(0, cpu->sve_vq_init)) {
+            error_setg(errp, "cannot disable sve128");
+            error_append_hint(errp, "Disabling sve128 results in all vector "
+                              "lengths being disabled.\n");
+            error_append_hint(errp, "With SVE enabled, at least one vector "
+                              "length must be enabled.\n");
+            return;
+        }
+        for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
+            if (test_bit(vq - 1, cpu->sve_vq_init)) {
+                break;
+            }
+        }
+        max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
+
+        bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
+        max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
+    }
+
+    /*
+     * Process the sve-max-vq property.
+     * Note that we know from the above that no bit above
+     * sve-max-vq is currently set.
+     */
+    if (cpu->sve_max_vq != 0) {
+        max_vq = cpu->sve_max_vq;
+
+        if (!test_bit(max_vq - 1, cpu->sve_vq_map) &&
+            test_bit(max_vq - 1, cpu->sve_vq_init)) {
+            error_setg(errp, "cannot disable sve%d", max_vq * 128);
+            error_append_hint(errp, "The maximum vector length must be "
+                              "enabled, sve-max-vq=%d (%d bits)\n",
+                              max_vq, max_vq * 128);
+            return;
+        }
+
+        /* Set all bits not explicitly set within sve-max-vq. */
+        bitmap_complement(tmp, cpu->sve_vq_init, max_vq);
+        bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
+    }
+
+    /*
+     * We should know what max-vq is now.  Also, as we're done
+     * manipulating sve-vq-map, we ensure any bits above max-vq
+     * are clear, just in case anybody looks.
+     */
+    assert(max_vq != 0);
+    bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
+
+    /* Ensure all required powers-of-two are enabled. */
+    for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
+        if (!test_bit(vq - 1, cpu->sve_vq_map)) {
+            error_setg(errp, "cannot disable sve%d", vq * 128);
+            error_append_hint(errp, "sve%d is required as it "
+                              "is a power-of-two length smaller than "
+                              "the maximum, sve%d\n",
+                              vq * 128, max_vq * 128);
+            return;
+        }
+    }
+
+    /*
+     * Now that we validated all our vector lengths, the only question
+     * left to answer is if we even want SVE at all.
+     */
+    if (!cpu_isar_feature(aa64_sve, cpu)) {
+        error_setg(errp, "cannot enable sve%d", max_vq * 128);
+        error_append_hint(errp, "SVE must be enabled to enable vector "
+                          "lengths.\n");
+        error_append_hint(errp, "Add sve=on to the CPU property list.\n");
+        return;
+    }
+
+    /* From now on sve_max_vq is the actual maximum supported length. */
+    cpu->sve_max_vq = max_vq;
+}
+
+uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
+{
+    uint32_t bitnum;
+
+    /*
+     * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
+     * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
+     * function always returns the next smaller than the input.
+     */
+    assert(vq && vq <= ARM_MAX_VQ + 1);
+
+    bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
+    return bitnum == vq - 1 ? 0 : bitnum + 1;
+}
+
 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
                                    void *opaque, Error **errp)
 {
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
     error_propagate(errp, err);
 }
 
+static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t vq = atoi(&name[3]) / 128;
+    bool value;
+
+    /* All vector lengths are disabled when SVE is off. */
+    if (!cpu_isar_feature(aa64_sve, cpu)) {
+        value = false;
+    } else {
+        value = test_bit(vq - 1, cpu->sve_vq_map);
+    }
+    visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t vq = atoi(&name[3]) / 128;
+    Error *err = NULL;
+    bool value;
+
+    visit_type_bool(v, name, &value, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    if (value) {
+        set_bit(vq - 1, cpu->sve_vq_map);
+    } else {
+        clear_bit(vq - 1, cpu->sve_vq_map);
+    }
+    set_bit(vq - 1, cpu->sve_vq_init);
+}
+
 static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
                             void *opaque, Error **errp)
 {
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
 static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t vq;
 
     if (kvm_enabled()) {
         kvm_arm_set_cpu_features_from_host(cpu);
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
 
-        cpu->sve_max_vq = ARM_MAX_VQ;
         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                             cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
         object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
                             cpu_arm_set_sve, NULL, NULL, &error_fatal);
+
+        for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
+            char name[8];
+            sprintf(name, "sve%d", vq * 128);
+            object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
+                                cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
+        }
     }
 }
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
     return 0;
 }
 
+static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+{
+    uint32_t start_vq = (start_len & 0xf) + 1;
+
+    return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
+}
+
 /*
  * Given that SVE is enabled, return the vector length for EL.
  */
@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
     }
-    return zcr_len;
+
+    return sve_zcr_get_valid_len(cpu, zcr_len);
 }
 
 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
     return head;
 }
 
+QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
+
 /*
  * These are cpu model features we want to advertise. The order here
  * matters as this is the order in which qmp_query_cpu_model_expansion
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
  */
 static const char *cpu_model_advertised_features[] = {
     "aarch64", "pmu", "sve",
+    "sve128", "sve256", "sve384", "sve512",
+    "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
+    "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
     NULL
 };
 
@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
         if (!err) {
             visit_check_struct(visitor, &err);
         }
+        if (!err) {
+            arm_cpu_finalize_features(ARM_CPU(obj), &err);
+        }
         visit_end_struct(visitor, NULL);
         visit_free(visitor);
         if (err) {
@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
             error_propagate(errp, err);
             return NULL;
         }
+    } else {
+        Error *err = NULL;
+        arm_cpu_finalize_features(ARM_CPU(obj), &err);
+        assert(err == NULL);
     }
 
     expansion_info = g_new0(CpuModelExpansionInfo, 1);
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
  * See the COPYING file in the top-level directory.
  */
 #include "qemu/osdep.h"
+#include "qemu/bitops.h"
 #include "libqtest.h"
 #include "qapi/qmp/qdict.h"
 #include "qapi/qmp/qjson.h"
 
+/*
+ * We expect the SVE max-vq to be 16. Also it must be <= 64
+ * for our test code, otherwise 'vls' can't just be a uint64_t.
+ */
+#define SVE_MAX_VQ 16
+
 #define MACHINE     "-machine virt,gic-version=max,accel=tcg "
 #define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
 #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
@@ -XXX,XX +XXX,XX @@ static void assert_bad_props(QTestState *qts, const char *cpu_type)
     qobject_unref(resp);
 }
 
+static uint64_t resp_get_sve_vls(QDict *resp)
+{
+    QDict *props;
+    const QDictEntry *e;
+    uint64_t vls = 0;
+    int n = 0;
+
+    g_assert(resp);
+    g_assert(resp_has_props(resp));
+
+    props = resp_get_props(resp);
+
+    for (e = qdict_first(props); e; e = qdict_next(props, e)) {
+        if (strlen(e->key) > 3 && !strncmp(e->key, "sve", 3) &&
+            g_ascii_isdigit(e->key[3])) {
+            char *endptr;
+            int bits;
+
+            bits = g_ascii_strtoll(&e->key[3], &endptr, 10);
+            if (!bits || *endptr != '\0') {
+                continue;
+            }
+
+            if (qdict_get_bool(props, e->key)) {
+                vls |= BIT_ULL((bits / 128) - 1);
+            }
+            ++n;
+        }
+    }
+
+    g_assert(n == SVE_MAX_VQ);
+
+    return vls;
+}
+
+#define assert_sve_vls(qts, cpu_type, expected_vls, fmt, ...)          \
+({                                                                     \
+    QDict *_resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__);        \
+    g_assert(_resp);                                                   \
+    g_assert(resp_has_props(_resp));                                   \
+    g_assert(resp_get_sve_vls(_resp) == expected_vls);                 \
+    qobject_unref(_resp);                                              \
+})
+
+static void sve_tests_default(QTestState *qts, const char *cpu_type)
+{
+    /*
+     * With no sve-max-vq or sve<N> properties on the command line
+     * the default is to have all vector lengths enabled. This also
+     * tests that 'sve' is 'on' by default.
+     */
+    assert_sve_vls(qts, cpu_type, BIT_ULL(SVE_MAX_VQ) - 1, NULL);
+
+    /* With SVE off, all vector lengths should also be off. */
+    assert_sve_vls(qts, cpu_type, 0, "{ 'sve': false }");
+
+    /* With SVE on, we must have at least one vector length enabled. */
+    assert_error(qts, cpu_type, "cannot disable sve128", "{ 'sve128': false }");
+
+    /* Basic enable/disable tests. */
+    assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve384': true }");
+    assert_sve_vls(qts, cpu_type, ((BIT_ULL(SVE_MAX_VQ) - 1) & ~BIT_ULL(2)),
+                   "{ 'sve384': false }");
+
+    /*
+     * ---------------------------------------------------------------------
+     *               power-of-two(vq)   all-power-            can      can
+     *                                  of-two(< vq)        enable   disable
+     * ---------------------------------------------------------------------
+     * vq < max_vq      no                MUST*              yes      yes
+     * vq < max_vq      yes               MUST*              yes      no
+     * ---------------------------------------------------------------------
+     * vq == max_vq     n/a               MUST*              yes**    yes**
+     * ---------------------------------------------------------------------
+     * vq > max_vq      n/a               no                 no       yes
+     * vq > max_vq      n/a               yes                yes      yes
+     * ---------------------------------------------------------------------
+     *
+     * [*] "MUST" means this requirement must already be satisfied,
+     *     otherwise 'max_vq' couldn't itself be enabled.
+     *
+     * [**] Not testable with the QMP interface, only with the command line.
+     */
+
+    /* max_vq := 8 */
+    assert_sve_vls(qts, cpu_type, 0x8b, "{ 'sve1024': true }");
+
+    /* max_vq := 8, vq < max_vq, !power-of-two(vq) */
+    assert_sve_vls(qts, cpu_type, 0x8f,
+                   "{ 'sve1024': true, 'sve384': true }");
+    assert_sve_vls(qts, cpu_type, 0x8b,
+                   "{ 'sve1024': true, 'sve384': false }");
+
+    /* max_vq := 8, vq < max_vq, power-of-two(vq) */
+    assert_sve_vls(qts, cpu_type, 0x8b,
+                   "{ 'sve1024': true, 'sve256': true }");
+    assert_error(qts, cpu_type, "cannot disable sve256",
+                 "{ 'sve1024': true, 'sve256': false }");
+
+    /* max_vq := 3, vq > max_vq, !all-power-of-two(< vq) */
+    assert_error(qts, cpu_type, "cannot disable sve512",
+                 "{ 'sve384': true, 'sve512': false, 'sve640': true }");
+
+    /*
+     * We can disable power-of-two vector lengths when all larger lengths
+     * are also disabled. We only need to disable the power-of-two length,
+     * as all non-enabled larger lengths will then be auto-disabled.
+     */
+    assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve512': false }");
+
+    /* max_vq := 3, vq > max_vq, all-power-of-two(< vq) */
+    assert_sve_vls(qts, cpu_type, 0x1f,
+                   "{ 'sve384': true, 'sve512': true, 'sve640': true }");
+    assert_sve_vls(qts, cpu_type, 0xf,
+                   "{ 'sve384': true, 'sve512': true, 'sve640': false }");
+}
+
+static void sve_tests_sve_max_vq_8(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE "-cpu max,sve-max-vq=8");
+
+    assert_sve_vls(qts, "max", BIT_ULL(8) - 1, NULL);
+
+    /*
+     * Disabling the max-vq set by sve-max-vq is not allowed, but
+     * of course enabling it is OK.
+     */
+    assert_error(qts, "max", "cannot disable sve1024", "{ 'sve1024': false }");
+    assert_sve_vls(qts, "max", 0xff, "{ 'sve1024': true }");
+
+    /*
+     * Enabling anything larger than max-vq set by sve-max-vq is not
+     * allowed, but of course disabling everything larger is OK.
+     */
+    assert_error(qts, "max", "cannot enable sve1152", "{ 'sve1152': true }");
+    assert_sve_vls(qts, "max", 0xff, "{ 'sve1152': false }");
+
+    /*
+     * We can enable/disable non power-of-two lengths smaller than the
+     * max-vq set by sve-max-vq, but, while we can enable power-of-two
+     * lengths, we can't disable them.
+     */
+    assert_sve_vls(qts, "max", 0xff, "{ 'sve384': true }");
+    assert_sve_vls(qts, "max", 0xfb, "{ 'sve384': false }");
+    assert_sve_vls(qts, "max", 0xff, "{ 'sve256': true }");
+    assert_error(qts, "max", "cannot disable sve256", "{ 'sve256': false }");
+
+    qtest_quit(qts);
+}
+
+static void sve_tests_sve_off(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE "-cpu max,sve=off");
+
+    /* SVE is off, so the map should be empty. */
+    assert_sve_vls(qts, "max", 0, NULL);
+
+    /* The map stays empty even if we turn lengths off. */
+    assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
+
+    /* It's an error to enable lengths when SVE is off. */
+    assert_error(qts, "max", "cannot enable sve128", "{ 'sve128': true }");
+
+    /* With SVE re-enabled we should get all vector lengths enabled. */
+    assert_sve_vls(qts, "max", BIT_ULL(SVE_MAX_VQ) - 1, "{ 'sve': true }");
+
+    /* Or enable SVE with just specific vector lengths. */
+    assert_sve_vls(qts, "max", 0x3,
+                   "{ 'sve': true, 'sve128': true, 'sve256': true }");
+
+    qtest_quit(qts);
+}
+
 static void test_query_cpu_model_expansion(const void *data)
 {
     QTestState *qts;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
         assert_has_feature(qts, "max", "aarch64");
         assert_has_feature(qts, "max", "sve");
+        assert_has_feature(qts, "max", "sve128");
         assert_has_feature(qts, "cortex-a57", "pmu");
         assert_has_feature(qts, "cortex-a57", "aarch64");
 
+        sve_tests_default(qts, "max");
+
         /* Test that features that depend on KVM generate errors without. */
         assert_error(qts, "max",
                      "'aarch64' feature cannot be disabled "
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
     qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
                         NULL, test_query_cpu_model_expansion_kvm);
 
+    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+                            NULL, sve_tests_sve_max_vq_8);
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+                            NULL, sve_tests_sve_off);
+    }
+
     return g_test_run();
 }
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ block in the script for usage) is used to issue the QMP commands.
       (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
       { "return": {
         "model": { "name": "max", "props": {
-        "pmu": true, "aarch64": true
+        "sve1664": true, "pmu": true, "sve1792": true, "sve1920": true,
+        "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
+        "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
+        "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
+        "sve896": true, "sve1280": true, "sve2048": true
       }}}}
 
-We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
-We also see that the CPU features are enabled, as they are all `true`.
+We see that the `max` CPU type has the `pmu`, `aarch64`, `sve`, and many
+`sve<N>` CPU features.  We also see that all the CPU features are
+enabled, as they are all `true`.  (The `sve<N>` CPU features are all
+optional SVE vector lengths (see "SVE CPU Properties").  While with TCG
+all SVE vector lengths can be supported, when KVM is in use it's more
+likely that only a few lengths will be supported, if SVE is supported at
+all.)
 
 (2) Let's try to disable the PMU::
 
       (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
       { "return": {
         "model": { "name": "max", "props": {
-        "pmu": false, "aarch64": true
+        "sve1664": true, "pmu": false, "sve1792": true, "sve1920": true,
+        "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
+        "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
+        "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
+        "sve896": true, "sve1280": true, "sve2048": true
       }}}}
 
 We see it worked, as `pmu` is now `false`.
@@ -XXX,XX +XXX,XX @@ We see it worked, as `pmu` is now `false`.
 It looks like this feature is limited to a configuration we do not
 currently have.
 
-(4) Let's try probing CPU features for the Cortex-A15 CPU type::
+(4) Let's disable `sve` and see what happens to all the optional SVE
+    vector lengths::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"sve":false}}
+      { "return": {
+        "model": { "name": "max", "props": {
+        "sve1664": false, "pmu": true, "sve1792": false, "sve1920": false,
+        "sve128": false, "aarch64": true, "sve1024": false, "sve": false,
+        "sve640": false, "sve768": false, "sve1408": false, "sve256": false,
+        "sve1152": false, "sve512": false, "sve384": false, "sve1536": false,
+        "sve896": false, "sve1280": false, "sve2048": false
+      }}}}
+
+As expected they are now all `false`.
+
+(5) Let's try probing CPU features for the Cortex-A15 CPU type::
 
       (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
       {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
@@ -XXX,XX +XXX,XX @@ After determining which CPU features are available and supported for a
 given CPU type, then they may be selectively enabled or disabled on the
 QEMU command line with that CPU type::
 
-  $ qemu-system-aarch64 -M virt -cpu max,pmu=off
+  $ qemu-system-aarch64 -M virt -cpu max,pmu=off,sve=on,sve128=on,sve256=on
 
-The example above disables the PMU for the `max` CPU type.
+The example above disables the PMU and enables the first two SVE vector
+lengths for the `max` CPU type.  Note, the `sve=on` isn't actually
+necessary, because, as we observed above with our probe of the `max` CPU
+type, `sve` is already on by default.  Also, based on our probe of
+defaults, it would seem we need to disable many SVE vector lengths, rather
+than only enabling the two we want.  This isn't the case, because, as
+disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU
+properties have special semantics (see "SVE CPU Property Parsing
+Semantics").
+
+SVE CPU Properties
+==================
+
+There are two types of SVE CPU properties: `sve` and `sve<N>`.  The first
+is used to enable or disable the entire SVE feature, just as the `pmu`
+CPU property completely enables or disables the PMU.  The second type
+is used to enable or disable specific vector lengths, where `N` is the
+number of bits of the length.  The `sve<N>` CPU properties have special
+dependencies and constraints, see "SVE CPU Property Dependencies and
+Constraints" below.  Additionally, as we want all supported vector lengths
+to be enabled by default, then, in order to avoid overly verbose command
+lines (command lines full of `sve<N>=off`, for all `N` not wanted), we
+provide the parsing semantics listed in "SVE CPU Property Parsing
+Semantics".
+
+SVE CPU Property Dependencies and Constraints
+---------------------------------------------
+
+  1) At least one vector length must be enabled when `sve` is enabled.
+
+  2) If a vector length `N` is enabled, then all power-of-two vector
+     lengths smaller than `N` must also be enabled.  E.g. if `sve512`
+     is enabled, then the 128-bit and 256-bit vector lengths must also
+     be enabled.
+
+SVE CPU Property Parsing Semantics
+----------------------------------
+
+  1) If SVE is disabled (`sve=off`), then which SVE vector lengths
+     are enabled or disabled is irrelevant to the guest, as the entire
+     SVE feature is disabled and that disables all vector lengths for
+     the guest.  However QEMU will still track any `sve<N>` CPU
+     properties provided by the user.  If later an `sve=on` is provided,
+     then the guest will get only the enabled lengths.  If no `sve=on`
+     is provided and there are explicitly enabled vector lengths, then
+     an error is generated.
+
+  2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
+     provided, then all supported vector lengths are enabled, including
+     the non-power-of-two lengths.
+
+  3) If SVE is enabled, then an error is generated when attempting to
+     disable the last enabled vector length (see constraint (1) of "SVE
+     CPU Property Dependencies and Constraints").
+
+  4) If one or more vector lengths have been explicitly enabled and at
+     at least one of the dependency lengths of the maximum enabled length
+     has been explicitly disabled, then an error is generated (see
+     constraint (2) of "SVE CPU Property Dependencies and Constraints").
+
+  5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
+     CPU properties are set `on`, then the specified vector lengths are
+     disabled but the default for any unspecified lengths remains enabled.
+     Disabling a power-of-two vector length also disables all vector
+     lengths larger than the power-of-two length (see constraint (2) of
+     "SVE CPU Property Dependencies and Constraints").
+
+  6) If one or more `sve<N>` CPU properties are set to `on`, then they
+     are enabled and all unspecified lengths default to disabled, except
+     for the required lengths per constraint (2) of "SVE CPU Property
+     Dependencies and Constraints", which will even be auto-enabled if
+     they were not explicitly enabled.
+
+  7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
+     explicitly disabled (i.e. avoiding the error specified in (3) of
+     "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
+     provided an error will be generated.  To avoid this error, one must
+     enable at least one vector length prior to enabling SVE.
+
+SVE CPU Property Examples
+-------------------------
+
+  1) Disable SVE::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve=off
+
+  2) Implicitly enable all vector lengths for the `max` CPU type::
+
+     $ qemu-system-aarch64 -M virt -cpu max
+
+  3) Only enable the 128-bit vector length::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve128=on
+
+  4) Disable the 512-bit vector length and all larger vector lengths,
+     since 512 is a power-of-two.  This results in all the smaller,
+     uninitialized lengths (128, 256, and 384) defaulting to enabled::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve512=off
+
+  5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
+
+  6) The same as (5), but since the 128-bit and 256-bit vector
+     lengths are required for the 512-bit vector length to be enabled,
+     then allow them to be auto-enabled::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve512=on
+
+  7) Do the same as (6), but by first disabling SVE and then re-enabling it::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
+
+  8) Force errors regarding the last vector length::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve128=off
+     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
+
+SVE CPU Property Recommendations
+--------------------------------
+
+The examples in "SVE CPU Property Examples" exhibit many ways to select
+vector lengths which developers may find useful in order to avoid overly
+verbose command lines.  However, the recommended way to select vector
+lengths is to explicitly enable each desired length.  Therefore only
+example's (1), (3), and (5) exhibit recommended uses of the properties.
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

These are the SVE equivalents to kvm_arch_get/put_fpsimd. Note, the
swabbing is different than it is for fpsmid because the vector format
is a little-endian stream of words.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Message-id: 20191031142734.8590-6-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm64.c | 185 ++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 156 insertions(+), 29 deletions(-)

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_destroy_vcpu(CPUState *cs)
 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 {
     /* Return true if the regidx is a register we should synchronize
-     * via the cpreg_tuples array (ie is not a core reg we sync by
-     * hand in kvm_arch_get/put_registers())
+     * via the cpreg_tuples array (ie is not a core or sve reg that
+     * we sync by hand in kvm_arch_get/put_registers())
      */
     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
     case KVM_REG_ARM_CORE:
+    case KVM_REG_ARM64_SVE:
         return false;
     default:
         return true;
@@ -XXX,XX +XXX,XX @@ int kvm_arm_cpreg_level(uint64_t regidx)
 
 static int kvm_arch_put_fpsimd(CPUState *cs)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
+    CPUARMState *env = &ARM_CPU(cs)->env;
     struct kvm_one_reg reg;
-    uint32_t fpr;
     int i, ret;
 
     for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_fpsimd(CPUState *cs)
         }
     }
 
-    reg.addr = (uintptr_t)(&fpr);
-    fpr = vfp_get_fpsr(env);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
-    if (ret) {
-        return ret;
+    return 0;
+}
+
+/*
+ * SVE registers are encoded in KVM's memory in an endianness-invariant format.
+ * The byte at offset i from the start of the in-memory representation contains
+ * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
+ * lowest offsets are stored in the lowest memory addresses, then that nearly
+ * matches QEMU's representation, which is to use an array of host-endian
+ * uint64_t's, where the lower offsets are at the lower indices. To complete
+ * the translation we just need to byte swap the uint64_t's on big-endian hosts.
+ */
+static uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+    int i;
+
+    for (i = 0; i < nr; ++i) {
+        dst[i] = bswap64(src[i]);
     }
 
-    reg.addr = (uintptr_t)(&fpr);
-    fpr = vfp_get_fpcr(env);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
+    return dst;
+#else
+    return src;
+#endif
+}
+
+/*
+ * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
+ * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
+ * code the slice index to zero for now as it's unlikely we'll need more than
+ * one slice for quite some time.
+ */
+static int kvm_arch_put_sve(CPUState *cs)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    uint64_t tmp[ARM_MAX_VQ * 2];
+    uint64_t *r;
+    struct kvm_one_reg reg;
+    int n, ret;
+
+    for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
+        r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
+        reg.addr = (uintptr_t)r;
+        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
+        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        if (ret) {
+            return ret;
+        }
+    }
+
+    for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
+        r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
+                        DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
+        reg.addr = (uintptr_t)r;
+        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
+        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        if (ret) {
+            return ret;
+        }
+    }
+
+    r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
+                    DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
+    reg.addr = (uintptr_t)r;
+    reg.id = KVM_REG_ARM64_SVE_FFR(0);
     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
     if (ret) {
         return ret;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
 {
     struct kvm_one_reg reg;
     uint64_t val;
+    uint32_t fpr;
     int i, ret;
     unsigned int el;
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         }
     }
 
-    ret = kvm_arch_put_fpsimd(cs);
+    if (cpu_isar_feature(aa64_sve, cpu)) {
+        ret = kvm_arch_put_sve(cs);
+    } else {
+        ret = kvm_arch_put_fpsimd(cs);
+    }
+    if (ret) {
+        return ret;
+    }
+
+    reg.addr = (uintptr_t)(&fpr);
+    fpr = vfp_get_fpsr(env);
+    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
+    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg.addr = (uintptr_t)(&fpr);
+    fpr = vfp_get_fpcr(env);
+    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
+    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
 
 static int kvm_arch_get_fpsimd(CPUState *cs)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
+    CPUARMState *env = &ARM_CPU(cs)->env;
     struct kvm_one_reg reg;
-    uint32_t fpr;
     int i, ret;
 
     for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_fpsimd(CPUState *cs)
         }
     }
 
-    reg.addr = (uintptr_t)(&fpr);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
-    if (ret) {
-        return ret;
-    }
-    vfp_set_fpsr(env, fpr);
+    return 0;
+}
 
-    reg.addr = (uintptr_t)(&fpr);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
+/*
+ * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
+ * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
+ * code the slice index to zero for now as it's unlikely we'll need more than
+ * one slice for quite some time.
+ */
+static int kvm_arch_get_sve(CPUState *cs)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    struct kvm_one_reg reg;
+    uint64_t *r;
+    int n, ret;
+
+    for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
+        r = &env->vfp.zregs[n].d[0];
+        reg.addr = (uintptr_t)r;
+        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
+        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        if (ret) {
+            return ret;
+        }
+        sve_bswap64(r, r, cpu->sve_max_vq * 2);
+    }
+
+    for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
+        r = &env->vfp.pregs[n].p[0];
+        reg.addr = (uintptr_t)r;
+        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
+        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        if (ret) {
+            return ret;
+        }
+        sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
+    }
+
+    r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
+    reg.addr = (uintptr_t)r;
+    reg.id = KVM_REG_ARM64_SVE_FFR(0);
     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
     if (ret) {
         return ret;
     }
-    vfp_set_fpcr(env, fpr);
+    sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
     struct kvm_one_reg reg;
     uint64_t val;
     unsigned int el;
+    uint32_t fpr;
     int i, ret;
 
     ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
         env->spsr = env->banked_spsr[i];
     }
 
-    ret = kvm_arch_get_fpsimd(cs);
+    if (cpu_isar_feature(aa64_sve, cpu)) {
+        ret = kvm_arch_get_sve(cs);
+    } else {
+        ret = kvm_arch_get_fpsimd(cs);
+    }
     if (ret) {
         return ret;
     }
 
+    reg.addr = (uintptr_t)(&fpr);
+    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    if (ret) {
+        return ret;
+    }
+    vfp_set_fpsr(env, fpr);
+
+    reg.addr = (uintptr_t)(&fpr);
+    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    if (ret) {
+        return ret;
+    }
+    vfp_set_fpcr(env, fpr);
+
     ret = kvm_get_vcpu_events(cpu);
     if (ret) {
         return ret;
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Enable SVE in the KVM guest when the 'max' cpu type is configured
and KVM supports it. KVM SVE requires use of the new finalize
vcpu ioctl, so we add that now too. For starters SVE can only be
turned on or off, getting all vector lengths the host CPU supports
when on. We'll add the other SVE CPU properties in later patches.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-7-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h     | 27 +++++++++++++++++++++++++++
 target/arm/cpu64.c       | 17 ++++++++++++++---
 target/arm/kvm.c         |  5 +++++
 target/arm/kvm64.c       | 20 +++++++++++++++++++-
 tests/arm-cpu-features.c |  4 ++++
 5 files changed, 69 insertions(+), 4 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@
  */
 int kvm_arm_vcpu_init(CPUState *cs);
 
+/**
+ * kvm_arm_vcpu_finalize
+ * @cs: CPUState
+ * @feature: int
+ *
+ * Finalizes the configuration of the specified VCPU feature by
+ * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring
+ * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of
+ * KVM's API documentation.
+ *
+ * Returns: 0 if success else < 0 error code
+ */
+int kvm_arm_vcpu_finalize(CPUState *cs, int feature);
+
 /**
  * kvm_arm_register_device:
  * @mr: memory region for this device
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs);
  */
 bool kvm_arm_pmu_supported(CPUState *cs);
 
+/**
+ * bool kvm_arm_sve_supported:
+ * @cs: CPUState
+ *
+ * Returns true if the KVM VCPU can enable SVE and false otherwise.
+ */
+bool kvm_arm_sve_supported(CPUState *cs);
+
 /**
  * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
  * IPA address space supported by KVM
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_pmu_supported(CPUState *cs)
     return false;
 }
 
+static inline bool kvm_arm_sve_supported(CPUState *cs)
+{
+    return false;
+}
+
 static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
 {
     return -ENOENT;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
         return;
     }
 
+    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+        error_setg(errp, "'sve' feature not supported by KVM on this host");
+        return;
+    }
+
     t = cpu->isar.id_aa64pfr0;
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
     cpu->isar.id_aa64pfr0 = t;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     uint32_t vq;
+    uint64_t t;
 
     if (kvm_enabled()) {
         kvm_arm_set_cpu_features_from_host(cpu);
+        if (kvm_arm_sve_supported(CPU(cpu))) {
+            t = cpu->isar.id_aa64pfr0;
+            t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+            cpu->isar.id_aa64pfr0 = t;
+        }
     } else {
-        uint64_t t;
         uint32_t u;
         aarch64_a57_initfn(obj);
 
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 
         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                             cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
-        object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
-                            cpu_arm_set_sve, NULL, NULL, &error_fatal);
 
         for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
             char name[8];
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
                                 cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
         }
     }
+
+    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
+                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
 }
 
 struct ARMCPUInfo {
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs)
     return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
 }
 
+int kvm_arm_vcpu_finalize(CPUState *cs, int feature)
+{
+    return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature);
+}
+
 void kvm_arm_init_serror_injection(CPUState *cs)
 {
     cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state,
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cpu)
     return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
 }
 
+bool kvm_arm_sve_supported(CPUState *cpu)
+{
+    KVMState *s = KVM_STATE(current_machine->accelerator);
+
+    return kvm_check_extension(s, KVM_CAP_ARM_SVE);
+}
+
 #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
 
 int kvm_arch_init_vcpu(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
     }
     if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
-            cpu->has_pmu = false;
+        cpu->has_pmu = false;
     }
     if (cpu->has_pmu) {
         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
     } else {
         unset_feature(&env->features, ARM_FEATURE_PMU);
     }
+    if (cpu_isar_feature(aa64_sve, cpu)) {
+        assert(kvm_arm_sve_supported(cs));
+        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
+    }
 
     /* Do KVM_ARM_VCPU_INIT ioctl */
     ret = kvm_arm_vcpu_init(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         return ret;
     }
 
+    if (cpu_isar_feature(aa64_sve, cpu)) {
+        ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
+        if (ret) {
+            return ret;
+        }
+    }
+
     /*
      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
      * Currently KVM has its own idea about MPIDR assignment, so we
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         assert_has_feature(qts, "host", "aarch64");
         assert_has_feature(qts, "host", "pmu");
 
+        assert_has_feature(qts, "max", "sve");
+
         assert_error(qts, "cortex-a15",
             "We cannot guarantee the CPU type 'cortex-a15' works "
             "with KVM on this host", NULL);
     } else {
         assert_has_not_feature(qts, "host", "aarch64");
         assert_has_not_feature(qts, "host", "pmu");
+
+        assert_has_not_feature(qts, "max", "sve");
     }
 
     qtest_quit(qts);
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

kvm_arm_create_scratch_host_vcpu() takes a struct kvm_vcpu_init
parameter. Rather than just using it as an output parameter to
pass back the preferred target, use it also as an input parameter,
allowing a caller to pass a selected target if they wish and to
also pass cpu features. If the caller doesn't want to select a
target they can pass -1 for the target which indicates they want
to use the preferred target and have it passed back like before.

diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
                                       int *fdarray,
                                       struct kvm_vcpu_init *init)
 {
-    int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
+    int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1;
 
     kvmfd = qemu_open("/dev/kvm", O_RDWR);
     if (kvmfd < 0) {
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
         goto finish;
     }
 
-    ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
+    if (init->target == -1) {
+        struct kvm_vcpu_init preferred;
+
+        ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred);
+        if (!ret) {
+            init->target = preferred.target;
+        }
+    }
     if (ret >= 0) {
         ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
         if (ret < 0) {
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
          * creating one kind of guest CPU which is its preferred
          * CPU type.
          */
+        struct kvm_vcpu_init try;
+
         while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
-            init->target = *cpus_to_try++;
-            memset(init->features, 0, sizeof(init->features));
-            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
+            try.target = *cpus_to_try++;
+            memcpy(try.features, init->features, sizeof(init->features));
+            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try);
             if (ret >= 0) {
                 break;
             }
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
         if (ret < 0) {
             goto err;
         }
+        init->target = try.target;
     } else {
         /* Treat a NULL cpus_to_try argument the same as an empty
          * list, which means we will fail the call since this must
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         QEMU_KVM_ARM_TARGET_CORTEX_A15,
         QEMU_KVM_ARM_TARGET_NONE
     };
-    struct kvm_vcpu_init init;
+    /*
+     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
+     * to use the preferred target
+     */
+    struct kvm_vcpu_init init = { .target = -1, };
 
     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
         return false;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         KVM_ARM_TARGET_CORTEX_A57,
         QEMU_KVM_ARM_TARGET_NONE
     };
-    struct kvm_vcpu_init init;
+    /*
+     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
+     * to use the preferred target
+     */
+    struct kvm_vcpu_init init = { .target = -1, };
 
     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
         return false;
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Extend the SVE vq map initialization and validation with KVM's
supported vector lengths when KVM is enabled. In order to determine
and select supported lengths we add two new KVM functions for getting
and setting the KVM_REG_ARM64_SVE_VLS pseudo-register.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Message-id: 20191031142734.8590-9-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h      |  12 +++
 target/arm/cpu64.c        | 176 ++++++++++++++++++++++++++++----------
 target/arm/kvm64.c        | 100 +++++++++++++++++++++-
 tests/arm-cpu-features.c  | 104 +++++++++++++++++++++-
 docs/arm-cpu-features.rst |  45 +++++++---
 5 files changed, 379 insertions(+), 58 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures {
  */
 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
 
+/**
+ * kvm_arm_sve_get_vls:
+ * @cs: CPUState
+ * @map: bitmap to fill in
+ *
+ * Get all the SVE vector lengths supported by the KVM host, setting
+ * the bits corresponding to their length in quadwords minus one
+ * (vq - 1) in @map up to ARM_MAX_VQ.
+ */
+void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map);
+
 /**
  * kvm_arm_set_cpu_features_from_host:
  * @cpu: ARMCPU to set the features for
@@ -XXX,XX +XXX,XX @@ static inline int kvm_arm_vgic_probe(void)
 static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
 static inline void kvm_arm_pmu_init(CPUState *cs) {}
 
+static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
 #endif
 
 static inline const char *gic_class_name(void)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
      * any of the above.  Finally, if SVE is not disabled, then at least one
      * vector length must be enabled.
      */
+    DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ);
     DECLARE_BITMAP(tmp, ARM_MAX_VQ);
     uint32_t vq, max_vq = 0;
 
+    /* Collect the set of vector lengths supported by KVM. */
+    bitmap_zero(kvm_supported, ARM_MAX_VQ);
+    if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
+        kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
+    } else if (kvm_enabled()) {
+        assert(!cpu_isar_feature(aa64_sve, cpu));
+    }
+
     /*
      * Process explicit sve<N> properties.
      * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
             return;
         }
 
-        /* Propagate enabled bits down through required powers-of-two. */
-        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
-            if (!test_bit(vq - 1, cpu->sve_vq_init)) {
-                set_bit(vq - 1, cpu->sve_vq_map);
+        if (kvm_enabled()) {
+            /*
+             * For KVM we have to automatically enable all supported unitialized
+             * lengths, even when the smaller lengths are not all powers-of-two.
+             */
+            bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq);
+            bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
+        } else {
+            /* Propagate enabled bits down through required powers-of-two. */
+            for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
+                if (!test_bit(vq - 1, cpu->sve_vq_init)) {
+                    set_bit(vq - 1, cpu->sve_vq_map);
+                }
             }
         }
     } else if (cpu->sve_max_vq == 0) {
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
             return;
         }
 
-        /* Disabling a power-of-two disables all larger lengths. */
-        if (test_bit(0, cpu->sve_vq_init)) {
-            error_setg(errp, "cannot disable sve128");
-            error_append_hint(errp, "Disabling sve128 results in all vector "
-                              "lengths being disabled.\n");
-            error_append_hint(errp, "With SVE enabled, at least one vector "
-                              "length must be enabled.\n");
-            return;
-        }
-        for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
-            if (test_bit(vq - 1, cpu->sve_vq_init)) {
-                break;
+        if (kvm_enabled()) {
+            /* Disabling a supported length disables all larger lengths. */
+            for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
+                if (test_bit(vq - 1, cpu->sve_vq_init) &&
+                    test_bit(vq - 1, kvm_supported)) {
+                    break;
+                }
             }
+            max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
+            bitmap_andnot(cpu->sve_vq_map, kvm_supported,
+                          cpu->sve_vq_init, max_vq);
+            if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
+                error_setg(errp, "cannot disable sve%d", vq * 128);
+                error_append_hint(errp, "Disabling sve%d results in all "
+                                  "vector lengths being disabled.\n",
+                                  vq * 128);
+                error_append_hint(errp, "With SVE enabled, at least one "
+                                  "vector length must be enabled.\n");
+                return;
+            }
+        } else {
+            /* Disabling a power-of-two disables all larger lengths. */
+            if (test_bit(0, cpu->sve_vq_init)) {
+                error_setg(errp, "cannot disable sve128");
+                error_append_hint(errp, "Disabling sve128 results in all "
+                                  "vector lengths being disabled.\n");
+                error_append_hint(errp, "With SVE enabled, at least one "
+                                  "vector length must be enabled.\n");
+                return;
+            }
+            for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
+                if (test_bit(vq - 1, cpu->sve_vq_init)) {
+                    break;
+                }
+            }
+            max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
+            bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
         }
-        max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 
-        bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
         max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
     }
 
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
     assert(max_vq != 0);
     bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
 
-    /* Ensure all required powers-of-two are enabled. */
-    for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
-        if (!test_bit(vq - 1, cpu->sve_vq_map)) {
-            error_setg(errp, "cannot disable sve%d", vq * 128);
-            error_append_hint(errp, "sve%d is required as it "
-                              "is a power-of-two length smaller than "
-                              "the maximum, sve%d\n",
-                              vq * 128, max_vq * 128);
+    if (kvm_enabled()) {
+        /* Ensure the set of lengths matches what KVM supports. */
+        bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq);
+        if (!bitmap_empty(tmp, max_vq)) {
+            vq = find_last_bit(tmp, max_vq) + 1;
+            if (test_bit(vq - 1, cpu->sve_vq_map)) {
+                if (cpu->sve_max_vq) {
+                    error_setg(errp, "cannot set sve-max-vq=%d",
+                               cpu->sve_max_vq);
+                    error_append_hint(errp, "This KVM host does not support "
+                                      "the vector length %d-bits.\n",
+                                      vq * 128);
+                    error_append_hint(errp, "It may not be possible to use "
+                                      "sve-max-vq with this KVM host. Try "
+                                      "using only sve<N> properties.\n");
+                } else {
+                    error_setg(errp, "cannot enable sve%d", vq * 128);
+                    error_append_hint(errp, "This KVM host does not support "
+                                      "the vector length %d-bits.\n",
+                                      vq * 128);
+                }
+            } else {
+                error_setg(errp, "cannot disable sve%d", vq * 128);
+                error_append_hint(errp, "The KVM host requires all "
+                                  "supported vector lengths smaller "
+                                  "than %d bits to also be enabled.\n",
+                                  max_vq * 128);
+            }
             return;
         }
+    } else {
+        /* Ensure all required powers-of-two are enabled. */
+        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
+            if (!test_bit(vq - 1, cpu->sve_vq_map)) {
+                error_setg(errp, "cannot disable sve%d", vq * 128);
+                error_append_hint(errp, "sve%d is required as it "
+                                  "is a power-of-two length smaller than "
+                                  "the maximum, sve%d\n",
+                                  vq * 128, max_vq * 128);
+                return;
+            }
+        }
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
 {
     ARMCPU *cpu = ARM_CPU(obj);
     Error *err = NULL;
+    uint32_t max_vq;
 
-    visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
-
-    if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
-        error_setg(&err, "unsupported SVE vector length");
-        error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
-                          ARM_MAX_VQ);
+    visit_type_uint32(v, name, &max_vq, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
     }
-    error_propagate(errp, err);
+
+    if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+        error_setg(errp, "cannot set sve-max-vq");
+        error_append_hint(errp, "SVE not supported by KVM on this host\n");
+        return;
+    }
+
+    if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
+        error_setg(errp, "unsupported SVE vector length");
+        error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
+                          ARM_MAX_VQ);
+        return;
+    }
+
+    cpu->sve_max_vq = max_vq;
 }
 
 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
         return;
     }
 
+    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+        error_setg(errp, "cannot enable %s", name);
+        error_append_hint(errp, "SVE not supported by KVM on this host\n");
+        return;
+    }
+
     if (value) {
         set_bit(vq - 1, cpu->sve_vq_map);
     } else {
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
         cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
-
-        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
-                            cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
-
-        for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
-            char name[8];
-            sprintf(name, "sve%d", vq * 128);
-            object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
-                                cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
-        }
     }
 
     object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
                         cpu_arm_set_sve, NULL, NULL, &error_fatal);
+    object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
+                        cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
+
+    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
+        char name[8];
+        sprintf(name, "sve%d", vq * 128);
+        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
+                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
+    }
 }
 
 struct ARMCPUInfo {
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(CPUState *cpu)
     return kvm_check_extension(s, KVM_CAP_ARM_SVE);
 }
 
+QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
+
+void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
+{
+    /* Only call this function if kvm_arm_sve_supported() returns true. */
+    static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];
+    static bool probed;
+    uint32_t vq = 0;
+    int i, j;
+
+    bitmap_clear(map, 0, ARM_MAX_VQ);
+
+    /*
+     * KVM ensures all host CPUs support the same set of vector lengths.
+     * So we only need to create the scratch VCPUs once and then cache
+     * the results.
+     */
+    if (!probed) {
+        struct kvm_vcpu_init init = {
+            .target = -1,
+            .features[0] = (1 << KVM_ARM_VCPU_SVE),
+        };
+        struct kvm_one_reg reg = {
+            .id = KVM_REG_ARM64_SVE_VLS,
+            .addr = (uint64_t)&vls[0],
+        };
+        int fdarray[3], ret;
+
+        probed = true;
+
+        if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) {
+            error_report("failed to create scratch VCPU with SVE enabled");
+            abort();
+        }
+        ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &reg);
+        kvm_arm_destroy_scratch_host_vcpu(fdarray);
+        if (ret) {
+            error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s",
+                         strerror(errno));
+            abort();
+        }
+
+        for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {
+            if (vls[i]) {
+                vq = 64 - clz64(vls[i]) + i * 64;
+                break;
+            }
+        }
+        if (vq > ARM_MAX_VQ) {
+            warn_report("KVM supports vector lengths larger than "
+                        "QEMU can enable");
+        }
+    }
+
+    for (i = 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) {
+        if (!vls[i]) {
+            continue;
+        }
+        for (j = 1; j <= 64; ++j) {
+            vq = j + i * 64;
+            if (vq > ARM_MAX_VQ) {
+                return;
+            }
+            if (vls[i] & (1UL << (j - 1))) {
+                set_bit(vq - 1, map);
+            }
+        }
+    }
+}
+
+static int kvm_arm_sve_set_vls(CPUState *cs)
+{
+    uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = {0};
+    struct kvm_one_reg reg = {
+        .id = KVM_REG_ARM64_SVE_VLS,
+        .addr = (uint64_t)&vls[0],
+    };
+    ARMCPU *cpu = ARM_CPU(cs);
+    uint32_t vq;
+    int i, j;
+
+    assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
+
+    for (vq = 1; vq <= cpu->sve_max_vq; ++vq) {
+        if (test_bit(vq - 1, cpu->sve_vq_map)) {
+            i = (vq - 1) / 64;
+            j = (vq - 1) % 64;
+            vls[i] |= 1UL << j;
+        }
+    }
+
+    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+}
+
 #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
 
 int kvm_arch_init_vcpu(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
 
     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
         !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
-        fprintf(stderr, "KVM is not supported for this guest CPU type\n");
+        error_report("KVM is not supported for this guest CPU type");
         return -EINVAL;
     }
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     }
 
     if (cpu_isar_feature(aa64_sve, cpu)) {
+        ret = kvm_arm_sve_set_vls(cs);
+        if (ret) {
+            return ret;
+        }
         ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
         if (ret) {
             return ret;
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static QDict *resp_get_props(QDict *resp)
     return qdict;
 }
 
+static bool resp_get_feature(QDict *resp, const char *feature)
+{
+    QDict *props;
+
+    g_assert(resp);
+    g_assert(resp_has_props(resp));
+    props = resp_get_props(resp);
+    g_assert(qdict_get(props, feature));
+    return qdict_get_bool(props, feature);
+}
+
 #define assert_has_feature(qts, cpu_type, feature)                     \
 ({                                                                     \
     QDict *_resp = do_query_no_props(qts, cpu_type);                   \
@@ -XXX,XX +XXX,XX @@ static void sve_tests_sve_off(const void *data)
     qtest_quit(qts);
 }
 
+static void sve_tests_sve_off_kvm(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE_KVM "-cpu max,sve=off");
+
+    /*
+     * We don't know if this host supports SVE so we don't
+     * attempt to test enabling anything. We only test that
+     * everything is disabled (as it should be with sve=off)
+     * and that using sve<N>=off to explicitly disable vector
+     * lengths is OK too.
+     */
+    assert_sve_vls(qts, "max", 0, NULL);
+    assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
+
+    qtest_quit(qts);
+}
+
 static void test_query_cpu_model_expansion(const void *data)
 {
     QTestState *qts;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
     }
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        bool kvm_supports_sve;
+        char max_name[8], name[8];
+        uint32_t max_vq, vq;
+        uint64_t vls;
+        QDict *resp;
+        char *error;
+
         assert_has_feature(qts, "host", "aarch64");
         assert_has_feature(qts, "host", "pmu");
 
-        assert_has_feature(qts, "max", "sve");
-
         assert_error(qts, "cortex-a15",
             "We cannot guarantee the CPU type 'cortex-a15' works "
             "with KVM on this host", NULL);
+
+        assert_has_feature(qts, "max", "sve");
+        resp = do_query_no_props(qts, "max");
+        kvm_supports_sve = resp_get_feature(resp, "sve");
+        vls = resp_get_sve_vls(resp);
+        qobject_unref(resp);
+
+        if (kvm_supports_sve) {
+            g_assert(vls != 0);
+            max_vq = 64 - __builtin_clzll(vls);
+            sprintf(max_name, "sve%d", max_vq * 128);
+
+            /* Enabling a supported length is of course fine. */
+            assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
+
+            /* Get the next supported length smaller than max-vq. */
+            vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
+            if (vq) {
+                /*
+                 * We have at least one length smaller than max-vq,
+                 * so we can disable max-vq.
+                 */
+                assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
+                               "{ %s: false }", max_name);
+
+                /*
+                 * Smaller, supported vector lengths cannot be disabled
+                 * unless all larger, supported vector lengths are also
+                 * disabled.
+                 */
+                sprintf(name, "sve%d", vq * 128);
+                error = g_strdup_printf("cannot disable %s", name);
+                assert_error(qts, "max", error,
+                             "{ %s: true, %s: false }",
+                             max_name, name);
+                g_free(error);
+            }
+
+            /*
+             * The smallest, supported vector length is required, because
+             * we need at least one vector length enabled.
+             */
+            vq = __builtin_ffsll(vls);
+            sprintf(name, "sve%d", vq * 128);
+            error = g_strdup_printf("cannot disable %s", name);
+            assert_error(qts, "max", error, "{ %s: false }", name);
+            g_free(error);
+
+            /* Get an unsupported length. */
+            for (vq = 1; vq <= max_vq; ++vq) {
+                if (!(vls & BIT_ULL(vq - 1))) {
+                    break;
+                }
+            }
+            if (vq <= SVE_MAX_VQ) {
+                sprintf(name, "sve%d", vq * 128);
+                error = g_strdup_printf("cannot enable %s", name);
+                assert_error(qts, "max", error, "{ %s: true }", name);
+                g_free(error);
+            }
+        } else {
+            g_assert(vls == 0);
+        }
     } else {
         assert_has_not_feature(qts, "host", "aarch64");
         assert_has_not_feature(qts, "host", "pmu");
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
                             NULL, sve_tests_sve_max_vq_8);
         qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
                             NULL, sve_tests_sve_off);
+        qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+                            NULL, sve_tests_sve_off_kvm);
     }
 
     return g_test_run();
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Dependencies and Constraints
 
   1) At least one vector length must be enabled when `sve` is enabled.
 
-  2) If a vector length `N` is enabled, then all power-of-two vector
-     lengths smaller than `N` must also be enabled.  E.g. if `sve512`
-     is enabled, then the 128-bit and 256-bit vector lengths must also
-     be enabled.
+  2) If a vector length `N` is enabled, then, when KVM is enabled, all
+     smaller, host supported vector lengths must also be enabled.  If
+     KVM is not enabled, then only all the smaller, power-of-two vector
+     lengths must be enabled.  E.g. with KVM if the host supports all
+     vector lengths up to 512-bits (128, 256, 384, 512), then if `sve512`
+     is enabled, the 128-bit vector length, 256-bit vector length, and
+     384-bit vector length must also be enabled. Without KVM, the 384-bit
+     vector length would not be required.
+
+  3) If KVM is enabled then only vector lengths that the host CPU type
+     support may be enabled.  If SVE is not supported by the host, then
+     no `sve*` properties may be enabled.
 
 SVE CPU Property Parsing Semantics
 ----------------------------------
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
      an error is generated.
 
   2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
-     provided, then all supported vector lengths are enabled, including
-     the non-power-of-two lengths.
+     provided, then all supported vector lengths are enabled, which when
+     KVM is not in use means including the non-power-of-two lengths, and,
+     when KVM is in use, it means all vector lengths supported by the host
+     processor.
 
   3) If SVE is enabled, then an error is generated when attempting to
      disable the last enabled vector length (see constraint (1) of "SVE
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
      has been explicitly disabled, then an error is generated (see
      constraint (2) of "SVE CPU Property Dependencies and Constraints").
 
-  5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
+  5) When KVM is enabled, if the host does not support SVE, then an error
+     is generated when attempting to enable any `sve*` properties (see
+     constraint (3) of "SVE CPU Property Dependencies and Constraints").
+
+  6) When KVM is enabled, if the host does support SVE, then an error is
+     generated when attempting to enable any vector lengths not supported
+     by the host (see constraint (3) of "SVE CPU Property Dependencies and
+     Constraints").
+
+  7) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
      CPU properties are set `on`, then the specified vector lengths are
      disabled but the default for any unspecified lengths remains enabled.
-     Disabling a power-of-two vector length also disables all vector
-     lengths larger than the power-of-two length (see constraint (2) of
-     "SVE CPU Property Dependencies and Constraints").
+     When KVM is not enabled, disabling a power-of-two vector length also
+     disables all vector lengths larger than the power-of-two length.
+     When KVM is enabled, then disabling any supported vector length also
+     disables all larger vector lengths (see constraint (2) of "SVE CPU
+     Property Dependencies and Constraints").
 
-  6) If one or more `sve<N>` CPU properties are set to `on`, then they
+  8) If one or more `sve<N>` CPU properties are set to `on`, then they
      are enabled and all unspecified lengths default to disabled, except
      for the required lengths per constraint (2) of "SVE CPU Property
      Dependencies and Constraints", which will even be auto-enabled if
      they were not explicitly enabled.
 
-  7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
+  9) If SVE was disabled (`sve=off`), allowing all vector lengths to be
      explicitly disabled (i.e. avoiding the error specified in (3) of
      "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
      provided an error will be generated.  To avoid this error, one must
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Allow cpu 'host' to enable SVE when it's available, unless the
user chooses to disable it with the added 'sve=off' cpu property.
Also give the user the ability to select vector lengths with the
sve<N> properties. We don't adopt 'max' cpu's other sve property,
sve-max-vq, because that property is difficult to use with KVM.
That property assumes all vector lengths in the range from 1 up
to and including the specified maximum length are supported, but
there may be optional lengths not supported by the host in that
range. With KVM one must be more specific when enabling vector
lengths.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Message-id: 20191031142734.8590-10-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h          |  2 ++
 target/arm/cpu.c          |  3 +++
 target/arm/cpu64.c        | 33 +++++++++++++++++----------------
 target/arm/kvm64.c        | 14 +++++++++++++-
 tests/arm-cpu-features.c  | 17 ++++++++---------
 docs/arm-cpu-features.rst | 19 ++++++++++++-------
 6 files changed, 55 insertions(+), 33 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
 void aarch64_sve_change_el(CPUARMState *env, int old_el,
                            int new_el, bool el0_a64);
+void aarch64_add_sve_properties(Object *obj);
 #else
 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
                                          int n, bool a)
 { }
+static inline void aarch64_add_sve_properties(Object *obj) { }
 #endif
 
 #if !defined(CONFIG_TCG)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
     ARMCPU *cpu = ARM_CPU(obj);
 
     kvm_arm_set_cpu_features_from_host(cpu);
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        aarch64_add_sve_properties(obj);
+    }
     arm_cpu_post_init(obj);
 }
 
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
     cpu->isar.id_aa64pfr0 = t;
 }
 
+void aarch64_add_sve_properties(Object *obj)
+{
+    uint32_t vq;
+
+    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
+                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
+
+    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
+        char name[8];
+        sprintf(name, "sve%d", vq * 128);
+        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
+                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
+    }
+}
+
 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
  * otherwise, a CPU with as many features enabled as our emulation supports.
  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
 static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    uint32_t vq;
-    uint64_t t;
 
     if (kvm_enabled()) {
         kvm_arm_set_cpu_features_from_host(cpu);
-        if (kvm_arm_sve_supported(CPU(cpu))) {
-            t = cpu->isar.id_aa64pfr0;
-            t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-            cpu->isar.id_aa64pfr0 = t;
-        }
     } else {
+        uint64_t t;
         uint32_t u;
         aarch64_a57_initfn(obj);
 
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 #endif
     }
 
-    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
-                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
+    aarch64_add_sve_properties(obj);
     object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                         cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
-
-    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
-        char name[8];
-        sprintf(name, "sve%d", vq * 128);
-        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
-                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
-    }
 }
 
 struct ARMCPUInfo {
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      * and then query that CPU for the relevant ID registers.
      */
     int fdarray[3];
+    bool sve_supported;
     uint64_t features = 0;
+    uint64_t t;
     int err;
 
     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
                               ARM64_SYS_REG(3, 0, 0, 3, 2));
     }
 
+    sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
+
     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 
     if (err < 0) {
         return false;
     }
 
-   /* We can assume any KVM supporting CPU is at least a v8
+    /* Add feature bits that can't appear until after VCPU init. */
+    if (sve_supported) {
+        t = ahcf->isar.id_aa64pfr0;
+        t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+        ahcf->isar.id_aa64pfr0 = t;
+    }
+
+    /*
+     * We can assume any KVM supporting CPU is at least a v8
      * with VFPv4+Neon; this in turn implies most of the other
      * feature bits.
      */
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
             "We cannot guarantee the CPU type 'cortex-a15' works "
             "with KVM on this host", NULL);
 
-        assert_has_feature(qts, "max", "sve");
-        resp = do_query_no_props(qts, "max");
+        assert_has_feature(qts, "host", "sve");
+        resp = do_query_no_props(qts, "host");
         kvm_supports_sve = resp_get_feature(resp, "sve");
         vls = resp_get_sve_vls(resp);
         qobject_unref(resp);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
             sprintf(max_name, "sve%d", max_vq * 128);
 
             /* Enabling a supported length is of course fine. */
-            assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
+            assert_sve_vls(qts, "host", vls, "{ %s: true }", max_name);
 
             /* Get the next supported length smaller than max-vq. */
             vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
                  * We have at least one length smaller than max-vq,
                  * so we can disable max-vq.
                  */
-                assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
+                assert_sve_vls(qts, "host", (vls & ~BIT_ULL(max_vq - 1)),
                                "{ %s: false }", max_name);
 
                 /*
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
                  */
                 sprintf(name, "sve%d", vq * 128);
                 error = g_strdup_printf("cannot disable %s", name);
-                assert_error(qts, "max", error,
+                assert_error(qts, "host", error,
                              "{ %s: true, %s: false }",
                              max_name, name);
                 g_free(error);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
             vq = __builtin_ffsll(vls);
             sprintf(name, "sve%d", vq * 128);
             error = g_strdup_printf("cannot disable %s", name);
-            assert_error(qts, "max", error, "{ %s: false }", name);
+            assert_error(qts, "host", error, "{ %s: false }", name);
             g_free(error);
 
             /* Get an unsupported length. */
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
             if (vq <= SVE_MAX_VQ) {
                 sprintf(name, "sve%d", vq * 128);
                 error = g_strdup_printf("cannot enable %s", name);
-                assert_error(qts, "max", error, "{ %s: true }", name);
+                assert_error(qts, "host", error, "{ %s: true }", name);
                 g_free(error);
             }
         } else {
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
     } else {
         assert_has_not_feature(qts, "host", "aarch64");
         assert_has_not_feature(qts, "host", "pmu");
-
-        assert_has_not_feature(qts, "max", "sve");
+        assert_has_not_feature(qts, "host", "sve");
     }
 
     qtest_quit(qts);
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Examples
 
      $ qemu-system-aarch64 -M virt -cpu max
 
-  3) Only enable the 128-bit vector length::
+  3) When KVM is enabled, implicitly enable all host CPU supported vector
+     lengths with the `host` CPU type::
+
+     $ qemu-system-aarch64 -M virt,accel=kvm -cpu host
+
+  4) Only enable the 128-bit vector length::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve128=on
 
-  4) Disable the 512-bit vector length and all larger vector lengths,
+  5) Disable the 512-bit vector length and all larger vector lengths,
      since 512 is a power-of-two.  This results in all the smaller,
      uninitialized lengths (128, 256, and 384) defaulting to enabled::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve512=off
 
-  5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
+  6) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
 
-  6) The same as (5), but since the 128-bit and 256-bit vector
+  7) The same as (6), but since the 128-bit and 256-bit vector
      lengths are required for the 512-bit vector length to be enabled,
      then allow them to be auto-enabled::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve512=on
 
-  7) Do the same as (6), but by first disabling SVE and then re-enabling it::
+  8) Do the same as (7), but by first disabling SVE and then re-enabling it::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
 
-  8) Force errors regarding the last vector length::
+  9) Force errors regarding the last vector length::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve128=off
      $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
@@ -XXX,XX +XXX,XX @@ The examples in "SVE CPU Property Examples" exhibit many ways to select
 vector lengths which developers may find useful in order to avoid overly
 verbose command lines.  However, the recommended way to select vector
 lengths is to explicitly enable each desired length.  Therefore only
-example's (1), (3), and (5) exhibit recommended uses of the properties.
+example's (1), (4), and (6) exhibit recommended uses of the properties.
 
-- 
2.20.1

From: Christophe Lyon <christophe.lyon@linaro.org>

rt==15 is a special case when reading the flags: it means the
destination is APSR. This patch avoids rejecting
vmrs apsr_nzcv, fpscr
as illegal instruction.

Cc: qemu-stable@nongnu.org
Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
Message-id: 20191025095711.10853-1-christophe.lyon@linaro.org
[PMM: updated the comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-vfp.inc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
     if (arm_dc_feature(s, ARM_FEATURE_M)) {
         /*
          * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
-         * Writes to R15 are UNPREDICTABLE; we choose to undef.
+         * Accesses to R15 are UNPREDICTABLE; we choose to undef.
+         * (FPSCR -> r15 is a special case which writes to the PSR flags.)
          */
-        if (a->rt == 15 || a->reg != ARM_VFP_FPSCR) {
+        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
             return false;
         }
     }
-- 
2.20.1