[Qemu-devel] [PULL 0/5] target-arm queue
[PULL v2 00/29] target-arm queue
1
Just small stuff. I expect/hope to get the "report attributes
1
v2: drop pvpanic-pci patches.
2
in PAR register" fix from Andrew in, but will either send another
3
pull or just apply it as a single patch once it's been reviewed.
4
(I think we can call it a bugfix anyway, since it fixes booting
5
of Windows on ARM.)
6
2
7
thanks
3
The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
8
-- PMM
9
4
5
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
10
6
11
The following changes since commit abf6e752e55b2f5afb48303429dea2db7c3a62de:
7
are available in the Git repository at:
12
8
13
Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20171030' into staging (2017-10-30 13:02:45 +0000)
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
14
10
15
are available in the git repository at:
11
for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
16
12
17
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171031
13
docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
18
19
for you to fetch changes up to 168df2dea701bbf3118bdfea7794369dfa694d3d:
20
21
hw/pci-host/gpex: Improve INTX to gsi routing error checking (2017-10-31 11:50:52 +0000)
22
14
23
----------------------------------------------------------------
15
----------------------------------------------------------------
24
target-arm queue:
16
target-arm queue:
25
* fix instruction-length bit in syndrome for WFI/WFE traps
17
* Implement IMPDEF pauth algorithm
26
* xlnx-zcu102: Specify the max number of CPUs
18
* Support ARMv8.4-SEL2
27
* msf2: Remove dead code reported by Coverity
19
* Fix bug where we were truncating predicate vector lengths in SVE insns
28
* msf2: Wire up SYSRESETREQ in SoC for system reset
20
* npcm7xx_adc-test: Fix memleak in adc_qom_set
29
* hw/pci-host/gpex: Improve INTX to gsi routing error checking
21
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
22
* docs: Build and install all the docs in a single manual
30
23
31
----------------------------------------------------------------
24
----------------------------------------------------------------
32
Alistair Francis (1):
25
Gan Qixin (1):
33
xlnx-zcu102: Specify the max number of CPUs
26
npcm7xx_adc-test: Fix memleak in adc_qom_set
34
27
35
Eric Auger (1):
28
Peter Maydell (1):
36
hw/pci-host/gpex: Improve INTX to gsi routing error checking
29
docs: Build and install all the docs in a single manual
37
30
38
Stefano Stabellini (1):
31
Philippe Mathieu-Daudé (1):
39
fix WFI/WFE length in syndrome register
32
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
40
33
41
Subbaraya Sundeep (2):
34
Richard Henderson (7):
42
msf2: Remove dead code reported by Coverity
35
target/arm: Implement an IMPDEF pauth algorithm
43
msf2: Wire up SYSRESETREQ in SoC for system reset
36
target/arm: Add cpu properties to control pauth
37
target/arm: Use object_property_add_bool for "sve" property
38
target/arm: Introduce PREDDESC field definitions
39
target/arm: Update PFIRST, PNEXT for pred_desc
40
target/arm: Update ZIP, UZP, TRN for pred_desc
41
target/arm: Update REV, PUNPK for pred_desc
44
42
45
target/arm/helper.h | 2 +-
43
Rémi Denis-Courmont (19):
46
target/arm/internals.h | 3 ++-
44
target/arm: remove redundant tests
47
hw/arm/msf2-soc.c | 11 +++++++++++
45
target/arm: add arm_is_el2_enabled() helper
48
hw/arm/xlnx-zcu102.c | 1 +
46
target/arm: use arm_is_el2_enabled() where applicable
49
hw/pci-host/gpex.c | 10 ++++++++--
47
target/arm: use arm_hcr_el2_eff() where applicable
50
hw/ssi/mss-spi.c | 18 ++++++++++++++----
48
target/arm: factor MDCR_EL2 common handling
51
target/arm/op_helper.c | 7 ++++---
49
target/arm: Define isar_feature function to test for presence of SEL2
52
target/arm/psci.c | 2 +-
50
target/arm: add 64-bit S-EL2 to EL exception table
53
target/arm/translate-a64.c | 7 ++++++-
51
target/arm: add MMU stage 1 for Secure EL2
54
target/arm/translate.c | 10 +++++++++-
52
target/arm: add ARMv8.4-SEL2 system registers
55
10 files changed, 57 insertions(+), 14 deletions(-)
53
target/arm: handle VMID change in secure state
54
target/arm: do S1_ptw_translate() before address space lookup
55
target/arm: translate NS bit in page-walks
56
target/arm: generalize 2-stage page-walk condition
57
target/arm: secure stage 2 translation regime
58
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
59
target/arm: revector to run-time pick target EL
60
target/arm: Implement SCR_EL2.EEL2
61
target/arm: enable Secure EL2 in max CPU
62
target/arm: refactor vae1_tlbmask()
56
63
64
docs/conf.py | 46 ++++-
65
docs/devel/conf.py | 15 --
66
docs/index.html.in | 17 --
67
docs/interop/conf.py | 28 ---
68
docs/meson.build | 64 +++---
69
docs/specs/conf.py | 16 --
70
docs/system/arm/cpu-features.rst | 21 ++
71
docs/system/conf.py | 28 ---
72
docs/tools/conf.py | 37 ----
73
docs/user/conf.py | 15 --
74
include/qemu/xxhash.h | 98 +++++++++
75
target/arm/cpu-param.h | 2 +-
76
target/arm/cpu.h | 107 ++++++++--
77
target/arm/internals.h | 45 +++++
78
target/arm/cpu.c | 23 ++-
79
target/arm/cpu64.c | 65 ++++--
80
target/arm/helper-a64.c | 8 +-
81
target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
82
target/arm/m_helper.c | 2 +-
83
target/arm/monitor.c | 1 +
84
target/arm/op_helper.c | 4 +-
85
target/arm/pauth_helper.c | 27 ++-
86
target/arm/sve_helper.c | 33 ++--
87
target/arm/tlb_helper.c | 3 +
88
target/arm/translate-a64.c | 4 +
89
target/arm/translate-sve.c | 31 ++-
90
target/arm/translate.c | 36 +++-
91
tests/qtest/arm-cpu-features.c | 13 ++
92
tests/qtest/npcm7xx_adc-test.c | 1 +
93
.gitlab-ci.yml | 4 +-
94
30 files changed, 770 insertions(+), 438 deletions(-)
95
delete mode 100644 docs/devel/conf.py
96
delete mode 100644 docs/index.html.in
97
delete mode 100644 docs/interop/conf.py
98
delete mode 100644 docs/specs/conf.py
99
delete mode 100644 docs/system/conf.py
100
delete mode 100644 docs/tools/conf.py
101
delete mode 100644 docs/user/conf.py
102
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register
Deleted patch
1
From: Stefano Stabellini <sstabellini@kernel.org>
2
1
3
WFI/E are often, but not always, 4 bytes long. When they are, we need to
4
set ARM_EL_IL_SHIFT in the syndrome register.
5
6
Pass the instruction length to HELPER(wfi), use it to decrement pc
7
appropriately and to pass an is_16bit flag to syn_wfx, which sets
8
ARM_EL_IL_SHIFT if needed.
9
10
Set dc->insn in both arm_tr_translate_insn and thumb_tr_translate_insn.
11
12
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
13
Message-id: alpine.DEB.2.10.1710241055160.574@sstabellini-ThinkPad-X260
14
[PMM: move setting of dc->insn for Thumb so it is correct for 32 bit insns]
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.h | 2 +-
19
target/arm/internals.h | 3 ++-
20
target/arm/op_helper.c | 7 ++++---
21
target/arm/psci.c | 2 +-
22
target/arm/translate-a64.c | 7 ++++++-
23
target/arm/translate.c | 10 +++++++++-
24
6 files changed, 23 insertions(+), 8 deletions(-)
25
26
diff --git a/target/arm/helper.h b/target/arm/helper.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/helper.h
29
+++ b/target/arm/helper.h
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
31
DEF_HELPER_2(exception_internal, void, env, i32)
32
DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
33
DEF_HELPER_1(setend, void, env)
34
-DEF_HELPER_1(wfi, void, env)
35
+DEF_HELPER_2(wfi, void, env, i32)
36
DEF_HELPER_1(wfe, void, env)
37
DEF_HELPER_1(yield, void, env)
38
DEF_HELPER_1(pre_hvc, void, env)
39
diff --git a/target/arm/internals.h b/target/arm/internals.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/internals.h
42
+++ b/target/arm/internals.h
43
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_breakpoint(int same_el)
44
| ARM_EL_IL | 0x22;
45
}
46
47
-static inline uint32_t syn_wfx(int cv, int cond, int ti)
48
+static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
49
{
50
return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
51
+ (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) |
52
(cv << 24) | (cond << 20) | ti;
53
}
54
55
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/op_helper.c
58
+++ b/target/arm/op_helper.c
59
@@ -XXX,XX +XXX,XX @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
60
return 0;
61
}
62
63
-void HELPER(wfi)(CPUARMState *env)
64
+void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
65
{
66
CPUState *cs = CPU(arm_env_get_cpu(env));
67
int target_el = check_wfx_trap(env, false);
68
@@ -XXX,XX +XXX,XX @@ void HELPER(wfi)(CPUARMState *env)
69
}
70
71
if (target_el) {
72
- env->pc -= 4;
73
- raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0), target_el);
74
+ env->pc -= insn_len;
75
+ raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2),
76
+ target_el);
77
}
78
79
cs->exception_index = EXCP_HLT;
80
diff --git a/target/arm/psci.c b/target/arm/psci.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/psci.c
83
+++ b/target/arm/psci.c
84
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
85
} else {
86
env->regs[0] = 0;
87
}
88
- helper_wfi(env);
89
+ helper_wfi(env, 4);
90
break;
91
case QEMU_PSCI_0_1_FN_MIGRATE:
92
case QEMU_PSCI_0_2_FN_MIGRATE:
93
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/target/arm/translate-a64.c
96
+++ b/target/arm/translate-a64.c
97
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
98
gen_helper_yield(cpu_env);
99
break;
100
case DISAS_WFI:
101
+ {
102
/* This is a special case because we don't want to just halt the CPU
103
* if trying to debug across a WFI.
104
*/
105
+ TCGv_i32 tmp = tcg_const_i32(4);
106
+
107
gen_a64_set_pc_im(dc->pc);
108
- gen_helper_wfi(cpu_env);
109
+ gen_helper_wfi(cpu_env, tmp);
110
+ tcg_temp_free_i32(tmp);
111
/* The helper doesn't necessarily throw an exception, but we
112
* must go back to the main loop to check for interrupts anyway.
113
*/
114
tcg_gen_exit_tb(0);
115
break;
116
}
117
+ }
118
}
119
120
/* Functions above can change dc->pc, so re-align db->pc_next */
121
diff --git a/target/arm/translate.c b/target/arm/translate.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/arm/translate.c
124
+++ b/target/arm/translate.c
125
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
126
}
127
128
insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
129
+ dc->insn = insn;
130
dc->pc += 4;
131
disas_arm_insn(dc, insn);
132
133
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
134
insn = insn << 16 | insn2;
135
dc->pc += 2;
136
}
137
+ dc->insn = insn;
138
139
if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
140
uint32_t cond = dc->condexec_cond;
141
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
142
/* nothing more to generate */
143
break;
144
case DISAS_WFI:
145
- gen_helper_wfi(cpu_env);
146
+ {
147
+ TCGv_i32 tmp = tcg_const_i32((dc->thumb &&
148
+ !(dc->insn & (1U << 31))) ? 2 : 4);
149
+
150
+ gen_helper_wfi(cpu_env, tmp);
151
+ tcg_temp_free_i32(tmp);
152
/* The helper doesn't necessarily throw an exception, but we
153
* must go back to the main loop to check for interrupts anyway.
154
*/
155
tcg_gen_exit_tb(0);
156
break;
157
+ }
158
case DISAS_WFE:
159
gen_helper_wfe(cpu_env);
160
break;
161
--
162
2.7.4
163
164
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
Specify the number of CPUs that can run on ZynqMP.
4
5
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/xlnx-zcu102.c | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xlnx-zcu102.c
17
+++ b/hw/arm/xlnx-zcu102.c
18
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
19
mc->block_default_type = IF_IDE;
20
mc->units_per_default_bus = 1;
21
mc->ignore_memory_transaction_failures = true;
22
+ mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
23
}
24
25
static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
26
--
27
2.7.4
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity
Deleted patch
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
2
1
3
Fixed incorrect frame size mask, validated maximum frame
4
size in spi_write and removed dead code.
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9
Message-id: 1508898544-10307-1-git-send-email-sundeep.lkml@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/ssi/mss-spi.c | 18 ++++++++++++++----
13
1 file changed, 14 insertions(+), 4 deletions(-)
14
15
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/ssi/mss-spi.c
18
+++ b/hw/ssi/mss-spi.c
19
@@ -XXX,XX +XXX,XX @@
20
#define C_BIGFIFO (1 << 29)
21
#define C_RESET (1 << 31)
22
23
-#define FRAMESZ_MASK 0x1F
24
+#define FRAMESZ_MASK 0x3F
25
#define FMCOUNT_MASK 0x00FFFF00
26
#define FMCOUNT_SHIFT 8
27
+#define FRAMESZ_MAX 32
28
29
static void txfifo_reset(MSSSpiState *s)
30
{
31
@@ -XXX,XX +XXX,XX @@ static void set_fifodepth(MSSSpiState *s)
32
s->fifo_depth = 32;
33
} else if (size <= 16) {
34
s->fifo_depth = 16;
35
- } else if (size <= 32) {
36
- s->fifo_depth = 8;
37
} else {
38
- s->fifo_depth = 4;
39
+ s->fifo_depth = 8;
40
}
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void spi_write(void *opaque, hwaddr addr,
44
if (s->enabled) {
45
break;
46
}
47
+ /*
48
+ * [31:6] bits are reserved bits and for future use.
49
+ * [5:0] are for frame size. Only [5:0] bits are validated
50
+ * during write, [31:6] bits are untouched.
51
+ */
52
+ if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) {
53
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided."
54
+ "Maximum frame size is %u\n",
55
+ __func__, value & FRAMESZ_MASK, FRAMESZ_MAX);
56
+ break;
57
+ }
58
s->regs[R_SPI_DFSIZE] = value;
59
break;
60
61
--
62
2.7.4
63
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset
Deleted patch
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
2
1
3
Implemented system reset by creating SYSRESETREQ gpio
4
out from nvic.
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Message-id: 1509253165-7434-1-git-send-email-sundeep.lkml@gmail.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/msf2-soc.c | 11 +++++++++++
12
1 file changed, 11 insertions(+)
13
14
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/msf2-soc.c
17
+++ b/hw/arm/msf2-soc.c
18
@@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
19
static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
20
static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
21
22
+static void do_sys_reset(void *opaque, int n, int level)
23
+{
24
+ if (level) {
25
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
26
+ }
27
+}
28
+
29
static void m2sxxx_soc_initfn(Object *obj)
30
{
31
MSF2State *s = MSF2_SOC(obj);
32
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
33
error_append_hint(errp, "m3clk can not be zero\n");
34
return;
35
}
36
+
37
+ qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
38
+ qemu_allocate_irq(&do_sys_reset, NULL, 0));
39
+
40
system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
41
42
for (i = 0; i < MSF2_NUM_UARTS; i++) {
43
--
44
2.7.4
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking
Deleted patch
1
From: Eric Auger <eric.auger@redhat.com>
2
1
3
We exposed gpex_set_irq_num() for machines to set the INTx to
4
GSI routing. However if the machine forgets to call that
5
function we currently do not check the association was properly
6
done. Let's initialize gsi values to -1 and if this value is
7
found in gpex_route_intx_pin_to_irq, set the routing mode as
8
disabled.
9
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 1508776211-22175-1-git-send-email-eric.auger@redhat.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/pci-host/gpex.c | 10 ++++++++--
16
1 file changed, 8 insertions(+), 2 deletions(-)
17
18
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/pci-host/gpex.c
21
+++ b/hw/pci-host/gpex.c
22
@@ -XXX,XX +XXX,XX @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
23
{
24
PCIINTxRoute route;
25
GPEXHost *s = opaque;
26
+ int gsi = s->irq_num[pin];
27
28
- route.mode = PCI_INTX_ENABLED;
29
- route.irq = s->irq_num[pin];
30
+ route.irq = gsi;
31
+ if (gsi < 0) {
32
+ route.mode = PCI_INTX_DISABLED;
33
+ } else {
34
+ route.mode = PCI_INTX_ENABLED;
35
+ }
36
37
return route;
38
}
39
@@ -XXX,XX +XXX,XX @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
40
sysbus_init_mmio(sbd, &s->io_ioport);
41
for (i = 0; i < GPEX_NUM_IRQS; i++) {
42
sysbus_init_irq(sbd, &s->irq[i]);
43
+ s->irq_num[i] = -1;
44
}
45
46
pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,
47
--
48
2.7.4
49
50
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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