ARM v8M: exception entry, exit and security

[Qemu-devel] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset

Posted by Peter Maydell 8 years, 4 months ago

Reset for devices does not include an automatic clear of the
device state (unlike CPU state, where most of the state
structure is cleared to zero). Add some missing initialization
of NVIC state that meant that the device was left in the wrong
state if the guest did a warm reset.

(In particular, since we were resetting the computed state like
s->exception_prio but not all the state it was computed
from like s->vectors[x].active, the NVIC wound up in an
inconsistent state that could later trigger assertion failures.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/armv7m_nvic.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index d90d8d0..bc7b66d 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1782,6 +1782,11 @@ static void armv7m_nvic_reset(DeviceState *dev)
     int resetprio;
     NVICState *s = NVIC(dev);
 
+    memset(s->vectors, 0, sizeof(s->vectors));
+    memset(s->sec_vectors, 0, sizeof(s->sec_vectors));
+    s->prigroup[M_REG_NS] = 0;
+    s->prigroup[M_REG_S] = 0;
+
     s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
     /* MEM, BUS, and USAGE are enabled through
      * the System Handler Control register
-- 
2.7.4

Re: [Qemu-devel] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset

Posted by Richard Henderson 8 years, 4 months ago

On 09/22/2017 09:59 AM, Peter Maydell wrote:
> Reset for devices does not include an automatic clear of the
> device state (unlike CPU state, where most of the state
> structure is cleared to zero). Add some missing initialization
> of NVIC state that meant that the device was left in the wrong
> state if the guest did a warm reset.
> 
> (In particular, since we were resetting the computed state like
> s->exception_prio but not all the state it was computed
> from like s->vectors[x].active, the NVIC wound up in an
> inconsistent state that could later trigger assertion failures.)
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  hw/intc/armv7m_nvic.c | 5 +++++
>  1 file changed, 5 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [Qemu-devel] [Qemu-arm] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset

Posted by Philippe Mathieu-Daudé 8 years, 4 months ago

On 09/22/2017 11:59 AM, Peter Maydell wrote:
> Reset for devices does not include an automatic clear of the
> device state (unlike CPU state, where most of the state
> structure is cleared to zero). Add some missing initialization
> of NVIC state that meant that the device was left in the wrong
> state if the guest did a warm reset.
> 
> (In particular, since we were resetting the computed state like
> s->exception_prio but not all the state it was computed
> from like s->vectors[x].active, the NVIC wound up in an
> inconsistent state that could later trigger assertion failures.)
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>   hw/intc/armv7m_nvic.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index d90d8d0..bc7b66d 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -1782,6 +1782,11 @@ static void armv7m_nvic_reset(DeviceState *dev)
>       int resetprio;
>       NVICState *s = NVIC(dev);
>   
> +    memset(s->vectors, 0, sizeof(s->vectors));
> +    memset(s->sec_vectors, 0, sizeof(s->sec_vectors));
> +    s->prigroup[M_REG_NS] = 0;
> +    s->prigroup[M_REG_S] = 0;
> +
>       s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
>       /* MEM, BUS, and USAGE are enabled through
>        * the System Handler Control register
>