ARM queue: mostly patches from me, but also the Smartfusion2 board.

thanks

-- PMM

The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:

Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921

for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:

msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)

* more preparatory work for v8M support

* convert some omap devices away from old_mmio

* remove out of date ARM ARM section references in comments

* add the Smartfusion2 board

Peter Maydell (26):

target/arm: Implement MSR/MRS access to NS banked registers

nvic: Add banked exception states

nvic: Add cached vectpending_is_s_banked state

nvic: Add cached vectpending_prio state

nvic: Implement AIRCR changes for v8M

nvic: Make ICSR.RETTOBASE handle banked exceptions

nvic: Implement NVIC_ITNS<n> registers

nvic: Handle banked exceptions in nvic_recompute_state()

nvic: Make set_pending and clear_pending take a secure parameter

nvic: Make SHPR registers banked

nvic: Compare group priority for escalation to HF

nvic: In escalation to HardFault, support HF not being priority -1

nvic: Implement v8M changes to fixed priority exceptions

nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear

nvic: Handle v8M changes in nvic_exec_prio()

target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()

nvic: Make ICSR banked for v8M

nvic: Make SHCSR banked for v8M

nvic: Support banked exceptions in acknowledge and complete

target/arm: Remove out of date ARM ARM section references in A64 decoder

hw/arm/palm.c: Don't use old_mmio for static_ops

hw/gpio/omap_gpio.c: Don't use old_mmio

hw/timer/omap_synctimer.c: Don't use old_mmio

hw/timer/omap_gptimer: Don't use old_mmio

hw/i2c/omap_i2c.c: Don't use old_mmio

hw/arm/omap2.c: Don't use old_mmio

Subbaraya Sundeep (5):

msf2: Add Smartfusion2 System timer

msf2: Microsemi Smartfusion2 System Register block

msf2: Add Smartfusion2 SPI controller

msf2: Add Smartfusion2 SoC

msf2: Add Emcraft's Smartfusion2 SOM kit

hw/arm/Makefile.objs | 1 +

hw/misc/Makefile.objs | 1 +

hw/ssi/Makefile.objs | 1 +

hw/timer/Makefile.objs | 1 +

include/hw/arm/msf2-soc.h | 67 +++

include/hw/intc/armv7m_nvic.h | 33 +-

include/hw/misc/msf2-sysreg.h | 77 ++++

include/hw/ssi/mss-spi.h | 58 +++

include/hw/timer/mss-timer.h | 64 +++

target/arm/cpu.h | 62 ++-

hw/arm/msf2-soc.c | 238 +++++++++++

hw/arm/msf2-som.c | 105 +++++

hw/arm/omap2.c | 49 ++-

hw/arm/palm.c | 30 +-

hw/gpio/omap_gpio.c | 26 +-

hw/i2c/omap_i2c.c | 44 +-

hw/intc/armv7m_nvic.c | 913 ++++++++++++++++++++++++++++++++++------

hw/misc/msf2-sysreg.c | 160 +++++++

hw/ssi/mss-spi.c | 404 ++++++++++++++++++

hw/timer/mss-timer.c | 289 +++++++++++++

hw/timer/omap_gptimer.c | 49 ++-

hw/timer/omap_synctimer.c | 35 +-

target/arm/cpu.c | 7 +

target/arm/helper.c | 142 ++++++-

target/arm/translate-a64.c | 227 +++++-----

default-configs/arm-softmmu.mak | 1 +

hw/intc/trace-events | 13 +-

hw/misc/trace-events | 5 +

28 files changed, 2735 insertions(+), 367 deletions(-)

create mode 100644 include/hw/arm/msf2-soc.h

create mode 100644 include/hw/misc/msf2-sysreg.h

create mode 100644 include/hw/ssi/mss-spi.h

create mode 100644 include/hw/timer/mss-timer.h

create mode 100644 hw/arm/msf2-soc.c

create mode 100644 hw/arm/msf2-som.c

create mode 100644 hw/misc/msf2-sysreg.c

create mode 100644 hw/ssi/mss-spi.c

create mode 100644 hw/timer/mss-timer.c

For the v8M security extension, some exceptions must be banked

between security states. Add the new vecinfo array which holds

the state for the banked exceptions and migrate it if the

CPU the NVIC is attached to implements the security extension.

include/hw/intc/armv7m_nvic.h | 14 ++++++++++++

hw/intc/armv7m_nvic.c | 53 ++++++++++++++++++++++++++++++++++++++++++-

2 files changed, 66 insertions(+), 1 deletion(-)

2.7.4

Make the set_prio() function take a bool indicating

whether to pend the secure or non-secure version of a banked

interrupt, and use this to implement the correct banking

semantics for the SHPR registers.

hw/intc/armv7m_nvic.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-----

hw/intc/trace-events | 2 +-

2 files changed, 88 insertions(+), 10 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_raw_execution_priority(void *opaque)

return s->exception_prio;

-/* caller must call nvic_irq_update() after this */

-static void set_prio(NVICState *s, unsigned irq, uint8_t prio)

+/* caller must call nvic_irq_update() after this.

+ * secure indicates the bank to use for banked exceptions (we assert if

+ * we are passed secure=true for a non-banked exception).

+ */

+static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)

{

assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */

assert(irq < s->num_irq);

- s->vectors[irq].prio = prio;

+ if (secure) {

+ assert(exc_is_banked(irq));

+ s->sec_vectors[irq].prio = prio;

+ } else {

+ s->vectors[irq].prio = prio;

+ }

+

+ trace_nvic_set_prio(irq, secure, prio);

+/* Return the current raw priority register value.

+ * secure indicates the bank to use for banked exceptions (we assert if

+ * we are passed secure=true for a non-banked exception).

+ */

+static int get_prio(NVICState *s, unsigned irq, bool secure)

+{

+ assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */

+ assert(irq < s->num_irq);

- trace_nvic_set_prio(irq, prio);

+ if (secure) {

+ assert(exc_is_banked(irq));

+ return s->sec_vectors[irq].prio;

+ } else {

+ return s->vectors[irq].prio;

+ }

/* Recompute state and assert irq line accordingly.

@@ -XXX,XX +XXX,XX @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)

}

static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,

uint64_t *data, unsigned size,

MemTxAttrs attrs)

@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,

}

}

break;

- case 0xd18 ... 0xd23: /* System Handler Priority. */

+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */

val = 0;

for (i = 0; i < size; i++) {

- val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);

+ unsigned hdlidx = (offset - 0xd14) + i;

+ int sbank = shpr_bank(s, hdlidx, attrs);

+

+ if (sbank < 0) {

+ continue;

+ }

+ val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));

}

break;

case 0xfe0 ... 0xfff: /* ID. */

@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,

for (i = 0; i < size && startvec + i < s->num_irq; i++) {

if (attrs.secure || s->itns[startvec + i]) {

- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);

+ set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);

}

}

nvic_irq_update(s);

return MEMTX_OK;

- case 0xd18 ... 0xd23: /* System Handler Priority. */

+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */

for (i = 0; i < size; i++) {

unsigned hdlidx = (offset - 0xd14) + i;

- set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);

+ int newprio = extract32(value, i * 8, 8);

+ int sbank = shpr_bank(s, hdlidx, attrs);

+

+ if (sbank < 0) {

+ continue;

+ }

+ set_prio(s, hdlidx, sbank, newprio);

}

nvic_irq_update(s);

return MEMTX_OK;

diff --git a/hw/intc/trace-events b/hw/intc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/trace-events

+++ b/hw/intc/trace-events

@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S

# hw/intc/armv7m_nvic.c

nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"

nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"

-nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"

+nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"

nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"

nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"

nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"

2.7.4

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Emulated Emcraft's Smartfusion2 System On Module starter

kit.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20170920201737.25723-6-f4bug@amsat.org

[PMD: drop cpu_model to directly use cpu type]

hw/arm/Makefile.objs | 2 +-

hw/arm/msf2-som.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 106 insertions(+), 1 deletion(-)

create mode 100644 hw/arm/msf2-som.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o

obj-$(CONFIG_MPS2) += mps2.o

-obj-$(CONFIG_MSF2) += msf2-soc.o

+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o

diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/msf2-som.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.

+ *

+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "qemu/error-report.h"

+#include "hw/boards.h"

+#include "hw/arm/arm.h"

+#include "exec/address-spaces.h"

+#include "qemu/cutils.h"

+#include "hw/arm/msf2-soc.h"

+#include "cpu.h"

+

+#define DDR_BASE_ADDRESS 0xA0000000

+#define DDR_SIZE (64 * M_BYTE)

+

+#define M2S010_ENVM_SIZE (256 * K_BYTE)

+#define M2S010_ESRAM_SIZE (64 * K_BYTE)

+

+static void emcraft_sf2_s2s010_init(MachineState *machine)

+{

+ DeviceState *dev;

+ DeviceState *spi_flash;

+ MSF2State *soc;

+ MachineClass *mc = MACHINE_GET_CLASS(machine);

+ DriveInfo *dinfo = drive_get_next(IF_MTD);

+ qemu_irq cs_line;

+ SSIBus *spi_bus;

+ MemoryRegion *sysmem = get_system_memory();

+ MemoryRegion *ddr = g_new(MemoryRegion, 1);

+

+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {

+ error_report("This board can only be used with CPU %s",

+ mc->default_cpu_type);

+ memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,

+ &error_fatal);

+ memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);

+ dev = qdev_create(NULL, TYPE_MSF2_SOC);

+ qdev_prop_set_string(dev, "part-name", "M2S010");

+ qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);

+ qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);

+ qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);

+

+ /*

+ * CPU clock and peripheral clocks(APB0, APB1)are configurable

+ * in Libero. CPU clock is divided by APB0 and APB1 divisors for

+ * peripherals. Emcraft's SoM kit comes with these settings by default.

+ */

+ qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);

+ qdev_prop_set_uint32(dev, "apb0div", 2);

+ qdev_prop_set_uint32(dev, "apb1div", 2);

+

+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);

+

+ soc = MSF2_SOC(dev);

+

+ /* Attach SPI flash to SPI0 controller */

+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");

+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");

+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);

+ if (dinfo) {

+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),

+ &error_fatal);

+ }

+ qdev_init_nofail(spi_flash);

+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);

+

+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+ soc->envm_size);

+static void emcraft_sf2_machine_init(MachineClass *mc)

+ mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";

+ mc->init = emcraft_sf2_s2s010_init;

+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");

+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)

2.7.4

Don't use old_mmio in the memory region ops struct.

hw/arm/omap2.c | 49 +++++++++++++++++++++++++++++++++++++------------

1 file changed, 37 insertions(+), 12 deletions(-)

diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c

--- a/hw/arm/omap2.c

+++ b/hw/arm/omap2.c

@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write(void *opaque, hwaddr addr,

+static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,

+ unsigned size)

+{

+ switch (size) {

+ case 1:

+ return omap_sysctl_read8(opaque, addr);

+ case 2:

+ return omap_badwidth_read32(opaque, addr); /* TODO */

+ case 4:

+ return omap_sysctl_read(opaque, addr);

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static void omap_sysctl_writefn(void *opaque, hwaddr addr,

+ uint64_t value, unsigned size)

+{

+ switch (size) {

+ case 1:

+ omap_sysctl_write8(opaque, addr, value);

+ break;

+ case 2:

+ omap_badwidth_write32(opaque, addr, value); /* TODO */

+ break;

+ case 4:

+ omap_sysctl_write(opaque, addr, value);

+ break;

+ default:

+ g_assert_not_reached();

+ }

+}

+

static const MemoryRegionOps omap_sysctl_ops = {

- .old_mmio = {

- .read = {

- omap_sysctl_read8,

- omap_badwidth_read32,    /* TODO */

- omap_sysctl_read,

- },

- .write = {

- omap_sysctl_write8,

- omap_badwidth_write32,    /* TODO */

- omap_sysctl_write,

- },

- },

+ .read = omap_sysctl_readfn,

+ .write = omap_sysctl_writefn,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 4,

.endianness = DEVICE_NATIVE_ENDIAN,

};

2.7.4

Don't use old_mmio in the memory region ops struct.

hw/i2c/omap_i2c.c | 44 ++++++++++++++++++++++++++++++++------------

1 file changed, 32 insertions(+), 12 deletions(-)

diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c

--- a/hw/i2c/omap_i2c.c

+++ b/hw/i2c/omap_i2c.c

@@ -XXX,XX +XXX,XX @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,

}

+static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,

+ unsigned size)

+{

+ switch (size) {

+ case 2:

+ return omap_i2c_read(opaque, addr);

+ default:

+ return omap_badwidth_read16(opaque, addr);

+ }

+}

+

+static void omap_i2c_writefn(void *opaque, hwaddr addr,

+ uint64_t value, unsigned size)

+{

+ switch (size) {

+ case 1:

+ /* Only the last fifo write can be 8 bit. */

+ omap_i2c_writeb(opaque, addr, value);

+ break;

+ case 2:

+ omap_i2c_write(opaque, addr, value);

+ break;

+ default:

+ omap_badwidth_write16(opaque, addr, value);

+ break;

+ }

+}

+

static const MemoryRegionOps omap_i2c_ops = {

- .old_mmio = {

- .read = {

- omap_badwidth_read16,

- omap_i2c_read,

- omap_badwidth_read16,

- },

- .write = {

- omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */

- omap_i2c_write,

- omap_badwidth_write16,

- },

- },

+ .read = omap_i2c_readfn,

+ .write = omap_i2c_writefn,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 4,

.endianness = DEVICE_NATIVE_ENDIAN,

};

2.7.4

Don't use the old_mmio struct in memory region ops.

hw/timer/omap_gptimer.c | 49 +++++++++++++++++++++++++++++++++++++------------

1 file changed, 37 insertions(+), 12 deletions(-)

diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c

--- a/hw/timer/omap_gptimer.c

+++ b/hw/timer/omap_gptimer.c

@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,

s->writeh = (uint16_t) value;

}

+static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,

+ unsigned size)

+{

+ switch (size) {

+ case 1:

+ return omap_badwidth_read32(opaque, addr);

+ case 2:

+ return omap_gp_timer_readh(opaque, addr);

+ case 4:

+ return omap_gp_timer_readw(opaque, addr);

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static void omap_gp_timer_writefn(void *opaque, hwaddr addr,

+ uint64_t value, unsigned size)

+{

+ switch (size) {

+ case 1:

+ omap_badwidth_write32(opaque, addr, value);

+ break;

+ case 2:

+ omap_gp_timer_writeh(opaque, addr, value);

+ break;

+ case 4:

+ omap_gp_timer_write(opaque, addr, value);

+ break;

+ default:

+ g_assert_not_reached();

+ }

+}

+

static const MemoryRegionOps omap_gp_timer_ops = {

- .old_mmio = {

- .read = {

- omap_badwidth_read32,

- omap_gp_timer_readh,

- omap_gp_timer_readw,

- },

- .write = {

- omap_badwidth_write32,

- omap_gp_timer_writeh,

- omap_gp_timer_write,

- },

- },

+ .read = omap_gp_timer_readfn,

+ .write = omap_gp_timer_writefn,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 4,

.endianness = DEVICE_NATIVE_ENDIAN,

};

2.7.4

Don't use the old_mmio in the memory region ops struct.

hw/timer/omap_synctimer.c | 35 +++++++++++++++++++++--------------

1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c

--- a/hw/timer/omap_synctimer.c

+++ b/hw/timer/omap_synctimer.c

@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)

}

}

-static void omap_synctimer_write(void *opaque, hwaddr addr,

- uint32_t value)

+static uint64_t omap_synctimer_readfn(void *opaque, hwaddr addr,

+ unsigned size)

+{

+ switch (size) {

+ case 1:

+ return omap_badwidth_read32(opaque, addr);

+ case 2:

+ return omap_synctimer_readh(opaque, addr);

+ case 4:

+ return omap_synctimer_readw(opaque, addr);

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static void omap_synctimer_writefn(void *opaque, hwaddr addr,

+ uint64_t value, unsigned size)

{

OMAP_BAD_REG(addr);

}

static const MemoryRegionOps omap_synctimer_ops = {

- .old_mmio = {

- .read = {

- omap_badwidth_read32,

- omap_synctimer_readh,

- omap_synctimer_readw,

- },

- .write = {

- omap_badwidth_write32,

- omap_synctimer_write,

- omap_synctimer_write,

- },

- },

+ .read = omap_synctimer_readfn,

+ .write = omap_synctimer_writefn,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 4,

.endianness = DEVICE_NATIVE_ENDIAN,

};

2.7.4

The Application Interrupt and Reset Control Register has some changes

for v8M:

* new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have

real state if the security extension is implemented and otherwise

are constant

* the PRIGROUP field is banked between security states

* non-secure code can be blocked from using the SYSRESET bit

to reset the system if SYSRESETREQS is set

Implement the new state and the changes to register read and write.

For the moment we ignore the effects of the secure PRIGROUP.

We will implement the effects of PRIS and BFHFNMIS later.

@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {

int exception;

uint32_t primask[M_REG_NUM_BANKS];

uint32_t faultmask[M_REG_NUM_BANKS];

+ uint32_t aircr; /* only holds r/w state if security extn implemented */

uint32_t secure; /* Is CPU in Secure state? (not guest visible) */

} v7m;

@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1)

FIELD(V7M_CCR, DC, 16, 1)

FIELD(V7M_CCR, IC, 17, 1)

+/* V7M AIRCR bits */

+FIELD(V7M_AIRCR, VECTRESET, 0, 1)

+FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)

+FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)

+FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)

+FIELD(V7M_AIRCR, PRIGROUP, 8, 3)

+FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)

+FIELD(V7M_AIRCR, PRIS, 14, 1)

+FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)

+FIELD(V7M_AIRCR, VECTKEY, 16, 16)

+

/* V7M CFSR bits for MMFSR */

FIELD(V7M_CFSR, IACCVIOL, 0, 1)

FIELD(V7M_CFSR, DACCVIOL, 1, 1)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)

*/

static inline uint32_t nvic_gprio_mask(NVICState *s)

{

- return ~0U << (s->prigroup + 1);

+ return ~0U << (s->prigroup[M_REG_NS] + 1);

}

/* Recompute vectpending and exception_prio */

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

return val;

case 0xd08: /* Vector Table Offset. */

return cpu->env.v7m.vecbase[attrs.secure];

- case 0xd0c: /* Application Interrupt/Reset Control. */

- return 0xfa050000 | (s->prigroup << 8);

+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */

+ val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);

+ if (attrs.secure) {

+ /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */

+ val |= cpu->env.v7m.aircr;

+ } else {

+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {

+ /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If

+ * security isn't supported then BFHFNMINS is RAO (and

+ * the bit in env.v7m.aircr is always set).

+ */

+ val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;

+ }

+ }

+ return val;

case 0xd10: /* System Control. */

/* TODO: Implement SLEEPONEXIT. */

return 0;

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

case 0xd08: /* Vector Table Offset. */

cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;

break;

- case 0xd0c: /* Application Interrupt/Reset Control. */

- if ((value >> 16) == 0x05fa) {

- if (value & 4) {

- qemu_irq_pulse(s->sysresetreq);

+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */

+ if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {

+ if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {

+ if (attrs.secure ||

+ !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {

+ qemu_irq_pulse(s->sysresetreq);

+ }

}

- if (value & 2) {

+ if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {

qemu_log_mask(LOG_GUEST_ERROR,

"Setting VECTCLRACTIVE when not in DEBUG mode "

"is UNPREDICTABLE\n");

}

- if (value & 1) {

+ if (value & R_V7M_AIRCR_VECTRESET_MASK) {

+ /* NB: this bit is RES0 in v8M */

qemu_log_mask(LOG_GUEST_ERROR,

"Setting VECTRESET when not in DEBUG mode "

"is UNPREDICTABLE\n");

}

- s->prigroup = extract32(value, 8, 3);

+ s->prigroup[attrs.secure] = extract32(value,

+ R_V7M_AIRCR_PRIGROUP_SHIFT,

+ R_V7M_AIRCR_PRIGROUP_LENGTH);

+ if (attrs.secure) {

+ /* These bits are only writable by secure */

+ cpu->env.v7m.aircr = value &

+ (R_V7M_AIRCR_SYSRESETREQS_MASK |

+ R_V7M_AIRCR_BFHFNMINS_MASK |

+ R_V7M_AIRCR_PRIS_MASK);

+ }

nvic_irq_update(s);

}

break;

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {

.fields = (VMStateField[]) {

VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,

vmstate_VecInfo, VecInfo),

+ VMSTATE_UINT32(prigroup[M_REG_S], NVICState),

VMSTATE_END_OF_LIST()

}

};

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {

.fields = (VMStateField[]) {

VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,

vmstate_VecInfo, VecInfo),

- VMSTATE_UINT32(prigroup, NVICState),

+ VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),

VMSTATE_END_OF_LIST()

},

.subsections = (const VMStateDescription*[]) {

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)

if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {

env->v7m.secure = true;

+ } else {

+ /* This bit resets to 0 if security is supported, but 1 if

+ * it is not. The bit is not present in v7M, but we set it

+ * here so we can avoid having to make checks on it conditional

+ * on ARM_FEATURE_V8 (we don't let the guest see the bit).

+ */

+ env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;

}

/* In v7M the reset value of this bit is IMPDEF, but ARM recommends

2.7.4

Now that we have a banked FAULTMASK register and banked exceptions,

we can implement the correct check in cpu_mmu_index() for whether

the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes

handlers which have requested a negative execution priority to run

with the MPU disabled. In v8M the test has to check this for the

current security state and so takes account of banking.

target/arm/cpu.h | 21 ++++++++++++++++-----

hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++

2 files changed, 45 insertions(+), 5 deletions(-)

@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq);

* (v8M ARM ARM I_PKLD.)

*/

int armv7m_nvic_raw_execution_priority(void *opaque);

+/**

+ * armv7m_nvic_neg_prio_requested: return true if the requested execution

+ * priority is negative for the specified security state.

+ * @opaque: the NVIC

+ * @secure: the security state to test

+ * This corresponds to the pseudocode IsReqExecPriNeg().

+ */

+#ifndef CONFIG_USER_ONLY

+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);

+#else

+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)

+{

+ return false;

+}

+#endif

/* Interface for defining coprocessor registers.

* Registers are defined in tables of arm_cp_reginfo structs

@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)

if (arm_feature(env, ARM_FEATURE_M)) {

ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;