[Qemu-devel] [PULL 00/31] target-arm queue
[PULL 00/22] target-arm queue
1
ARM queue: mostly patches from me, but also the Smartfusion2 board.
1
target-arm queue: mostly patches from me this time round.
2
Nothing too exciting.
2
3
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:
6
The following changes since commit 78ac2eebbab9150edf5d0d00e3648f5ebb599001:
7
7
8
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)
8
Merge tag 'artist-cursor-fix-final-pull-request' of https://github.com/hdeller/qemu-hppa into staging (2022-05-18 09:32:15 -0700)
9
9
10
are available in the git repository at:
10
are available in the Git repository at:
11
11
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220519
13
13
14
for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:
14
for you to fetch changes up to fab8ad39fb75a0d9f097db67b2a334444754e88e:
15
15
16
msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)
16
target/arm: Use FIELD definitions for CPACR, CPTR_ELx (2022-05-19 18:34:10 +0100)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* more preparatory work for v8M support
20
* Implement FEAT_S2FWB
21
* convert some omap devices away from old_mmio
21
* Implement FEAT_IDST
22
* remove out of date ARM ARM section references in comments
22
* Drop unsupported_encoding() macro
23
* add the Smartfusion2 board
23
* hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
24
* Fix aarch64 debug register names
25
* hw/adc/zynq-xadc: Use qemu_irq typedef
26
* target/arm/helper.c: Delete stray obsolete comment
27
* Make number of counters in PMCR follow the CPU
28
* hw/arm/virt: Fix dtb nits
29
* ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
30
* target/arm: Fix PAuth keys access checks for disabled SEL2
31
* Enable FEAT_HCX for -cpu max
32
* Use FIELD definitions for CPACR, CPTR_ELx
24
33
25
----------------------------------------------------------------
34
----------------------------------------------------------------
26
Peter Maydell (26):
35
Chris Howard (1):
27
target/arm: Implement MSR/MRS access to NS banked registers
36
Fix aarch64 debug register names.
28
nvic: Add banked exception states
29
nvic: Add cached vectpending_is_s_banked state
30
nvic: Add cached vectpending_prio state
31
nvic: Implement AIRCR changes for v8M
32
nvic: Make ICSR.RETTOBASE handle banked exceptions
33
nvic: Implement NVIC_ITNS<n> registers
34
nvic: Handle banked exceptions in nvic_recompute_state()
35
nvic: Make set_pending and clear_pending take a secure parameter
36
nvic: Make SHPR registers banked
37
nvic: Compare group priority for escalation to HF
38
nvic: In escalation to HardFault, support HF not being priority -1
39
nvic: Implement v8M changes to fixed priority exceptions
40
nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
41
nvic: Handle v8M changes in nvic_exec_prio()
42
target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
43
nvic: Make ICSR banked for v8M
44
nvic: Make SHCSR banked for v8M
45
nvic: Support banked exceptions in acknowledge and complete
46
target/arm: Remove out of date ARM ARM section references in A64 decoder
47
hw/arm/palm.c: Don't use old_mmio for static_ops
48
hw/gpio/omap_gpio.c: Don't use old_mmio
49
hw/timer/omap_synctimer.c: Don't use old_mmio
50
hw/timer/omap_gptimer: Don't use old_mmio
51
hw/i2c/omap_i2c.c: Don't use old_mmio
52
hw/arm/omap2.c: Don't use old_mmio
53
37
54
Subbaraya Sundeep (5):
38
Florian Lugou (1):
55
msf2: Add Smartfusion2 System timer
39
target/arm: Fix PAuth keys access checks for disabled SEL2
56
msf2: Microsemi Smartfusion2 System Register block
57
msf2: Add Smartfusion2 SPI controller
58
msf2: Add Smartfusion2 SoC
59
msf2: Add Emcraft's Smartfusion2 SOM kit
60
40
61
hw/arm/Makefile.objs | 1 +
41
Peter Maydell (17):
62
hw/misc/Makefile.objs | 1 +
42
target/arm: Postpone interpretation of stage 2 descriptor attribute bits
63
hw/ssi/Makefile.objs | 1 +
43
target/arm: Factor out FWB=0 specific part of combine_cacheattrs()
64
hw/timer/Makefile.objs | 1 +
44
target/arm: Implement FEAT_S2FWB
65
include/hw/arm/msf2-soc.h | 67 +++
45
target/arm: Enable FEAT_S2FWB for -cpu max
66
include/hw/intc/armv7m_nvic.h | 33 +-
46
target/arm: Implement FEAT_IDST
67
include/hw/misc/msf2-sysreg.h | 77 ++++
47
target/arm: Drop unsupported_encoding() macro
68
include/hw/ssi/mss-spi.h | 58 +++
48
hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters
69
include/hw/timer/mss-timer.h | 64 +++
49
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
70
target/arm/cpu.h | 62 ++-
50
hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant
71
hw/arm/msf2-soc.c | 238 +++++++++++
51
hw/intc/arm_gicv3: Support configurable number of physical priority bits
72
hw/arm/msf2-som.c | 105 +++++
52
hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
73
hw/arm/omap2.c | 49 ++-
53
hw/intc/arm_gicv3: Provide ich_num_aprs()
74
hw/arm/palm.c | 30 +-
54
target/arm/helper.c: Delete stray obsolete comment
75
hw/gpio/omap_gpio.c | 26 +-
55
target/arm: Make number of counters in PMCR follow the CPU
76
hw/i2c/omap_i2c.c | 44 +-
56
hw/arm/virt: Fix incorrect non-secure flash dtb node name
77
hw/intc/armv7m_nvic.c | 913 ++++++++++++++++++++++++++++++++++------
57
hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node
78
hw/misc/msf2-sysreg.c | 160 +++++++
58
ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
79
hw/ssi/mss-spi.c | 404 ++++++++++++++++++
80
hw/timer/mss-timer.c | 289 +++++++++++++
81
hw/timer/omap_gptimer.c | 49 ++-
82
hw/timer/omap_synctimer.c | 35 +-
83
target/arm/cpu.c | 7 +
84
target/arm/helper.c | 142 ++++++-
85
target/arm/translate-a64.c | 227 +++++-----
86
default-configs/arm-softmmu.mak | 1 +
87
hw/intc/trace-events | 13 +-
88
hw/misc/trace-events | 5 +
89
28 files changed, 2735 insertions(+), 367 deletions(-)
90
create mode 100644 include/hw/arm/msf2-soc.h
91
create mode 100644 include/hw/misc/msf2-sysreg.h
92
create mode 100644 include/hw/ssi/mss-spi.h
93
create mode 100644 include/hw/timer/mss-timer.h
94
create mode 100644 hw/arm/msf2-soc.c
95
create mode 100644 hw/arm/msf2-som.c
96
create mode 100644 hw/misc/msf2-sysreg.c
97
create mode 100644 hw/ssi/mss-spi.c
98
create mode 100644 hw/timer/mss-timer.c
99
59
60
Philippe Mathieu-Daudé (1):
61
hw/adc/zynq-xadc: Use qemu_irq typedef
62
63
Richard Henderson (2):
64
target/arm: Enable FEAT_HCX for -cpu max
65
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
66
67
docs/system/arm/emulation.rst | 2 +
68
include/hw/adc/zynq-xadc.h | 3 +-
69
include/hw/intc/arm_gicv3_common.h | 8 +-
70
include/hw/ptimer.h | 16 +-
71
target/arm/cpregs.h | 24 +++
72
target/arm/cpu.h | 76 +++++++-
73
target/arm/internals.h | 11 +-
74
target/arm/translate-a64.h | 9 -
75
hw/adc/zynq-xadc.c | 4 +-
76
hw/arm/boot.c | 2 +-
77
hw/arm/musicpal.c | 2 +-
78
hw/arm/virt.c | 4 +-
79
hw/core/machine.c | 4 +-
80
hw/dma/xilinx_axidma.c | 2 +-
81
hw/dma/xlnx_csu_dma.c | 2 +-
82
hw/intc/arm_gicv3_common.c | 5 +
83
hw/intc/arm_gicv3_cpuif.c | 225 +++++++++++++++++-------
84
hw/intc/arm_gicv3_kvm.c | 16 +-
85
hw/m68k/mcf5206.c | 2 +-
86
hw/m68k/mcf5208.c | 2 +-
87
hw/net/can/xlnx-zynqmp-can.c | 2 +-
88
hw/net/fsl_etsec/etsec.c | 2 +-
89
hw/net/lan9118.c | 2 +-
90
hw/rtc/exynos4210_rtc.c | 4 +-
91
hw/timer/allwinner-a10-pit.c | 2 +-
92
hw/timer/altera_timer.c | 2 +-
93
hw/timer/arm_timer.c | 2 +-
94
hw/timer/digic-timer.c | 2 +-
95
hw/timer/etraxfs_timer.c | 6 +-
96
hw/timer/exynos4210_mct.c | 6 +-
97
hw/timer/exynos4210_pwm.c | 2 +-
98
hw/timer/grlib_gptimer.c | 2 +-
99
hw/timer/imx_epit.c | 4 +-
100
hw/timer/imx_gpt.c | 2 +-
101
hw/timer/mss-timer.c | 2 +-
102
hw/timer/sh_timer.c | 2 +-
103
hw/timer/slavio_timer.c | 2 +-
104
hw/timer/xilinx_timer.c | 2 +-
105
target/arm/cpu.c | 11 +-
106
target/arm/cpu64.c | 30 ++++
107
target/arm/cpu_tcg.c | 6 +
108
target/arm/helper.c | 348 ++++++++++++++++++++++++++++---------
109
target/arm/kvm64.c | 12 ++
110
target/arm/op_helper.c | 9 +
111
target/arm/translate-a64.c | 36 +++-
112
tests/unit/ptimer-test.c | 6 +-
113
46 files changed, 697 insertions(+), 228 deletions(-)
114
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/31] hw/i2c/omap_i2c.c: Don't use old_mmio
[PULL 01/22] target/arm: Postpone interpretation of stage 2 descriptor attribute bits
1
Don't use old_mmio in the memory region ops struct.
1
In the original Arm v8 two-stage translation, both stage 1 and stage
2
2 specify memory attributes (memory type, cacheability,
3
shareability); these are then combined to produce the overall memory
4
attributes for the whole stage 1+2 access. In QEMU we implement this
5
by having get_phys_addr() fill in an ARMCacheAttrs struct, and we
6
convert both the stage 1 and stage 2 attribute bit formats to the
7
same encoding (an 8-bit attribute value matching the MAIR_EL1 fields,
8
plus a 2-bit shareability value).
9
10
The new FEAT_S2FWB feature allows the guest to enable a different
11
interpretation of the attribute bits in the stage 2 descriptors.
12
These bits can now be used to control details of how the stage 1 and
13
2 attributes should be combined (for instance they can say "always
14
use the stage 1 attributes" or "ignore the stage 1 attributes and
15
always be Device memory"). This means we need to pass the raw bit
16
information for stage 2 down to the function which combines the stage
17
1 and stage 2 information.
18
19
Add a field to ARMCacheAttrs that indicates whether the attrs field
20
should be interpreted as MAIR format, or as the raw stage 2 attribute
21
bits from the descriptor, and store the appropriate values when
22
filling in cacheattrs.
23
24
We only need to interpret the attrs field in a few places:
25
* in do_ats_write(), where we know to expect a MAIR value
26
(there is no ATS instruction to do a stage-2-only walk)
27
* in S1_ptw_translate(), where we want to know whether the
28
combined S1 + S2 attributes indicate Device memory that
29
should provoke a fault
30
* in combine_cacheattrs(), which does the S1 + S2 combining
31
Update those places accordingly.
2
32
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-6-git-send-email-peter.maydell@linaro.org
35
Message-id: 20220505183950.2781801-2-peter.maydell@linaro.org
6
---
36
---
7
hw/i2c/omap_i2c.c | 44 ++++++++++++++++++++++++++++++++------------
37
target/arm/internals.h | 7 ++++++-
8
1 file changed, 32 insertions(+), 12 deletions(-)
38
target/arm/helper.c | 42 ++++++++++++++++++++++++++++++++++++------
39
2 files changed, 42 insertions(+), 7 deletions(-)
9
40
10
diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
41
diff --git a/target/arm/internals.h b/target/arm/internals.h
11
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/i2c/omap_i2c.c
43
--- a/target/arm/internals.h
13
+++ b/hw/i2c/omap_i2c.c
44
+++ b/target/arm/internals.h
14
@@ -XXX,XX +XXX,XX @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
45
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
15
}
46
47
/* Cacheability and shareability attributes for a memory access */
48
typedef struct ARMCacheAttrs {
49
- unsigned int attrs:8; /* as in the MAIR register encoding */
50
+ /*
51
+ * If is_s2_format is true, attrs is the S2 descriptor bits [5:2]
52
+ * Otherwise, attrs is the same as the MAIR_EL1 8-bit format
53
+ */
54
+ unsigned int attrs:8;
55
unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
56
+ bool is_s2_format:1;
57
} ARMCacheAttrs;
58
59
bool get_phys_addr(CPUARMState *env, target_ulong address,
60
diff --git a/target/arm/helper.c b/target/arm/helper.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/helper.c
63
+++ b/target/arm/helper.c
64
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
65
ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
66
&prot, &page_size, &fi, &cacheattrs);
67
68
+ /*
69
+ * ATS operations only do S1 or S1+S2 translations, so we never
70
+ * have to deal with the ARMCacheAttrs format for S2 only.
71
+ */
72
+ assert(!cacheattrs.is_s2_format);
73
+
74
if (ret) {
75
/*
76
* Some kinds of translation fault must cause exceptions rather
77
@@ -XXX,XX +XXX,XX @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
78
return true;
16
}
79
}
17
80
18
+static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
81
+static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
19
+ unsigned size)
20
+{
82
+{
21
+ switch (size) {
83
+ /*
22
+ case 2:
84
+ * For an S1 page table walk, the stage 1 attributes are always
23
+ return omap_i2c_read(opaque, addr);
85
+ * some form of "this is Normal memory". The combined S1+S2
24
+ default:
86
+ * attributes are therefore only Device if stage 2 specifies Device.
25
+ return omap_badwidth_read16(opaque, addr);
87
+ * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
26
+ }
88
+ * ie when cacheattrs.attrs bits [3:2] are 0b00.
89
+ */
90
+ assert(cacheattrs.is_s2_format);
91
+ return (cacheattrs.attrs & 0xc) == 0;
27
+}
92
+}
28
+
93
+
29
+static void omap_i2c_writefn(void *opaque, hwaddr addr,
94
/* Translate a S1 pagetable walk through S2 if needed. */
30
+ uint64_t value, unsigned size)
95
static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
31
+{
96
hwaddr addr, bool *is_secure,
32
+ switch (size) {
97
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
33
+ case 1:
98
return ~0;
34
+ /* Only the last fifo write can be 8 bit. */
99
}
35
+ omap_i2c_writeb(opaque, addr, value);
100
if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
36
+ break;
101
- (cacheattrs.attrs & 0xf0) == 0) {
37
+ case 2:
102
+ ptw_attrs_are_device(env, cacheattrs)) {
38
+ omap_i2c_write(opaque, addr, value);
103
/*
39
+ break;
104
* PTW set and S1 walk touched S2 Device memory:
40
+ default:
105
* generate Permission fault.
41
+ omap_badwidth_write16(opaque, addr, value);
106
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
42
+ break;
107
}
43
+ }
108
44
+}
109
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
110
- cacheattrs->attrs = convert_stage2_attrs(env, extract32(attrs, 0, 4));
111
+ cacheattrs->is_s2_format = true;
112
+ cacheattrs->attrs = extract32(attrs, 0, 4);
113
} else {
114
/* Index into MAIR registers for cache attributes */
115
uint8_t attrindx = extract32(attrs, 0, 3);
116
uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
117
assert(attrindx <= 7);
118
+ cacheattrs->is_s2_format = false;
119
cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
120
}
121
122
@@ -XXX,XX +XXX,XX @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
123
/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
124
* and CombineS1S2Desc()
125
*
126
+ * @env: CPUARMState
127
* @s1: Attributes from stage 1 walk
128
* @s2: Attributes from stage 2 walk
129
*/
130
-static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
131
+static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
132
+ ARMCacheAttrs s1, ARMCacheAttrs s2)
133
{
134
uint8_t s1lo, s2lo, s1hi, s2hi;
135
ARMCacheAttrs ret;
136
bool tagged = false;
137
+ uint8_t s2_mair_attrs;
45
+
138
+
46
static const MemoryRegionOps omap_i2c_ops = {
139
+ assert(s2.is_s2_format && !s1.is_s2_format);
47
- .old_mmio = {
140
+ ret.is_s2_format = false;
48
- .read = {
141
+
49
- omap_badwidth_read16,
142
+ s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
50
- omap_i2c_read,
143
51
- omap_badwidth_read16,
144
if (s1.attrs == 0xf0) {
52
- },
145
tagged = true;
53
- .write = {
146
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
54
- omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
147
}
55
- omap_i2c_write,
148
56
- omap_badwidth_write16,
149
s1lo = extract32(s1.attrs, 0, 4);
57
- },
150
- s2lo = extract32(s2.attrs, 0, 4);
58
- },
151
+ s2lo = extract32(s2_mair_attrs, 0, 4);
59
+ .read = omap_i2c_readfn,
152
s1hi = extract32(s1.attrs, 4, 4);
60
+ .write = omap_i2c_writefn,
153
- s2hi = extract32(s2.attrs, 4, 4);
61
+ .valid.min_access_size = 1,
154
+ s2hi = extract32(s2_mair_attrs, 4, 4);
62
+ .valid.max_access_size = 4,
155
63
.endianness = DEVICE_NATIVE_ENDIAN,
156
/* Combine shareability attributes (table D4-43) */
64
};
157
if (s1.shareability == 2 || s2.shareability == 2) {
65
158
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
159
}
160
cacheattrs->shareability = 0;
161
}
162
- *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
163
+ *cacheattrs = combine_cacheattrs(env, *cacheattrs, cacheattrs2);
164
165
/* Check if IPA translates to secure or non-secure PA space. */
166
if (arm_is_secure_below_el3(env)) {
167
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
168
/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
169
hcr = arm_hcr_el2_eff(env);
170
cacheattrs->shareability = 0;
171
+ cacheattrs->is_s2_format = false;
172
if (hcr & HCR_DC) {
173
if (hcr & HCR_DCT) {
174
memattr = 0xf0; /* Tagged, Normal, WB, RWA */
66
--
175
--
67
2.7.4
176
2.25.1
68
69
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/31] hw/arm/omap2.c: Don't use old_mmio
[PULL 02/22] target/arm: Factor out FWB=0 specific part of combine_cacheattrs()
1
Don't use old_mmio in the memory region ops struct.
1
Factor out the part of combine_cacheattrs() that is specific to
2
handling HCR_EL2.FWB == 0. This is the part where we combine the
3
memory type and cacheability attributes.
4
5
The "force Outer Shareable for Device or Normal Inner-NC Outer-NC"
6
logic remains in combine_cacheattrs() because it holds regardless
7
(this is the equivalent of the pseudocode EffectiveShareability()
8
function).
2
9
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-7-git-send-email-peter.maydell@linaro.org
12
Message-id: 20220505183950.2781801-3-peter.maydell@linaro.org
6
---
13
---
7
hw/arm/omap2.c | 49 +++++++++++++++++++++++++++++++++++++------------
14
target/arm/helper.c | 88 +++++++++++++++++++++++++--------------------
8
1 file changed, 37 insertions(+), 12 deletions(-)
15
1 file changed, 50 insertions(+), 38 deletions(-)
9
16
10
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
11
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/arm/omap2.c
19
--- a/target/arm/helper.c
13
+++ b/hw/arm/omap2.c
20
+++ b/target/arm/helper.c
14
@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write(void *opaque, hwaddr addr,
21
@@ -XXX,XX +XXX,XX @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
15
}
22
}
16
}
23
}
17
24
18
+static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
25
+/*
19
+ unsigned size)
26
+ * Combine the memory type and cacheability attributes of
27
+ * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
28
+ * combined attributes in MAIR_EL1 format.
29
+ */
30
+static uint8_t combined_attrs_nofwb(CPUARMState *env,
31
+ ARMCacheAttrs s1, ARMCacheAttrs s2)
20
+{
32
+{
21
+ switch (size) {
33
+ uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
22
+ case 1:
34
+
23
+ return omap_sysctl_read8(opaque, addr);
35
+ s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
24
+ case 2:
36
+
25
+ return omap_badwidth_read32(opaque, addr); /* TODO */
37
+ s1lo = extract32(s1.attrs, 0, 4);
26
+ case 4:
38
+ s2lo = extract32(s2_mair_attrs, 0, 4);
27
+ return omap_sysctl_read(opaque, addr);
39
+ s1hi = extract32(s1.attrs, 4, 4);
28
+ default:
40
+ s2hi = extract32(s2_mair_attrs, 4, 4);
29
+ g_assert_not_reached();
41
+
42
+ /* Combine memory type and cacheability attributes */
43
+ if (s1hi == 0 || s2hi == 0) {
44
+ /* Device has precedence over normal */
45
+ if (s1lo == 0 || s2lo == 0) {
46
+ /* nGnRnE has precedence over anything */
47
+ ret_attrs = 0;
48
+ } else if (s1lo == 4 || s2lo == 4) {
49
+ /* non-Reordering has precedence over Reordering */
50
+ ret_attrs = 4; /* nGnRE */
51
+ } else if (s1lo == 8 || s2lo == 8) {
52
+ /* non-Gathering has precedence over Gathering */
53
+ ret_attrs = 8; /* nGRE */
54
+ } else {
55
+ ret_attrs = 0xc; /* GRE */
56
+ }
57
+ } else { /* Normal memory */
58
+ /* Outer/inner cacheability combine independently */
59
+ ret_attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
60
+ | combine_cacheattr_nibble(s1lo, s2lo);
30
+ }
61
+ }
62
+ return ret_attrs;
31
+}
63
+}
32
+
64
+
33
+static void omap_sysctl_writefn(void *opaque, hwaddr addr,
65
/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
34
+ uint64_t value, unsigned size)
66
* and CombineS1S2Desc()
35
+{
67
*
36
+ switch (size) {
68
@@ -XXX,XX +XXX,XX @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
37
+ case 1:
69
static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
38
+ omap_sysctl_write8(opaque, addr, value);
70
ARMCacheAttrs s1, ARMCacheAttrs s2)
39
+ break;
71
{
40
+ case 2:
72
- uint8_t s1lo, s2lo, s1hi, s2hi;
41
+ omap_badwidth_write32(opaque, addr, value); /* TODO */
73
ARMCacheAttrs ret;
42
+ break;
74
bool tagged = false;
43
+ case 4:
75
- uint8_t s2_mair_attrs;
44
+ omap_sysctl_write(opaque, addr, value);
76
45
+ break;
77
assert(s2.is_s2_format && !s1.is_s2_format);
46
+ default:
78
ret.is_s2_format = false;
47
+ g_assert_not_reached();
79
48
+ }
80
- s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
49
+}
81
-
50
+
82
if (s1.attrs == 0xf0) {
51
static const MemoryRegionOps omap_sysctl_ops = {
83
tagged = true;
52
- .old_mmio = {
84
s1.attrs = 0xff;
53
- .read = {
85
}
54
- omap_sysctl_read8,
86
55
- omap_badwidth_read32,    /* TODO */
87
- s1lo = extract32(s1.attrs, 0, 4);
56
- omap_sysctl_read,
88
- s2lo = extract32(s2_mair_attrs, 0, 4);
57
- },
89
- s1hi = extract32(s1.attrs, 4, 4);
58
- .write = {
90
- s2hi = extract32(s2_mair_attrs, 4, 4);
59
- omap_sysctl_write8,
91
-
60
- omap_badwidth_write32,    /* TODO */
92
/* Combine shareability attributes (table D4-43) */
61
- omap_sysctl_write,
93
if (s1.shareability == 2 || s2.shareability == 2) {
62
- },
94
/* if either are outer-shareable, the result is outer-shareable */
63
- },
95
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
64
+ .read = omap_sysctl_readfn,
96
}
65
+ .write = omap_sysctl_writefn,
97
66
+ .valid.min_access_size = 1,
98
/* Combine memory type and cacheability attributes */
67
+ .valid.max_access_size = 4,
99
- if (s1hi == 0 || s2hi == 0) {
68
.endianness = DEVICE_NATIVE_ENDIAN,
100
- /* Device has precedence over normal */
69
};
101
- if (s1lo == 0 || s2lo == 0) {
70
102
- /* nGnRnE has precedence over anything */
103
- ret.attrs = 0;
104
- } else if (s1lo == 4 || s2lo == 4) {
105
- /* non-Reordering has precedence over Reordering */
106
- ret.attrs = 4; /* nGnRE */
107
- } else if (s1lo == 8 || s2lo == 8) {
108
- /* non-Gathering has precedence over Gathering */
109
- ret.attrs = 8; /* nGRE */
110
- } else {
111
- ret.attrs = 0xc; /* GRE */
112
- }
113
+ ret.attrs = combined_attrs_nofwb(env, s1, s2);
114
115
- /* Any location for which the resultant memory type is any
116
- * type of Device memory is always treated as Outer Shareable.
117
- */
118
+ /*
119
+ * Any location for which the resultant memory type is any
120
+ * type of Device memory is always treated as Outer Shareable.
121
+ * Any location for which the resultant memory type is Normal
122
+ * Inner Non-cacheable, Outer Non-cacheable is always treated
123
+ * as Outer Shareable.
124
+ * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
125
+ */
126
+ if ((ret.attrs & 0xf0) == 0 || ret.attrs == 0x44) {
127
ret.shareability = 2;
128
- } else { /* Normal memory */
129
- /* Outer/inner cacheability combine independently */
130
- ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
131
- | combine_cacheattr_nibble(s1lo, s2lo);
132
-
133
- if (ret.attrs == 0x44) {
134
- /* Any location for which the resultant memory type is Normal
135
- * Inner Non-cacheable, Outer Non-cacheable is always treated
136
- * as Outer Shareable.
137
- */
138
- ret.shareability = 2;
139
- }
140
}
141
142
/* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
71
--
143
--
72
2.7.4
144
2.25.1
73
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/31] nvic: Make SHPR registers banked
[PULL 03/22] target/arm: Implement FEAT_S2FWB
1
Make the set_prio() function take a bool indicating
1
Implement the handling of FEAT_S2FWB; the meat of this is in the new
2
whether to pend the secure or non-secure version of a banked
2
combined_attrs_fwb() function which combines S1 and S2 attributes
3
interrupt, and use this to implement the correct banking
3
when HCR_EL2.FWB is set.
4
semantics for the SHPR registers.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
7
Message-id: 20220505183950.2781801-4-peter.maydell@linaro.org
9
---
8
---
10
hw/intc/armv7m_nvic.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-----
9
target/arm/cpu.h | 5 +++
11
hw/intc/trace-events | 2 +-
10
target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++--
12
2 files changed, 88 insertions(+), 10 deletions(-)
11
2 files changed, 86 insertions(+), 3 deletions(-)
13
12
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
15
--- a/target/arm/cpu.h
17
+++ b/hw/intc/armv7m_nvic.c
16
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_raw_execution_priority(void *opaque)
17
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
19
return s->exception_prio;
18
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
20
}
19
}
21
20
22
-/* caller must call nvic_irq_update() after this */
21
+static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
23
-static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
22
+{
24
+/* caller must call nvic_irq_update() after this.
23
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
25
+ * secure indicates the bank to use for banked exceptions (we assert if
26
+ * we are passed secure=true for a non-banked exception).
27
+ */
28
+static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
29
{
30
assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
31
assert(irq < s->num_irq);
32
33
- s->vectors[irq].prio = prio;
34
+ if (secure) {
35
+ assert(exc_is_banked(irq));
36
+ s->sec_vectors[irq].prio = prio;
37
+ } else {
38
+ s->vectors[irq].prio = prio;
39
+ }
40
+
41
+ trace_nvic_set_prio(irq, secure, prio);
42
+}
24
+}
43
+
25
+
44
+/* Return the current raw priority register value.
26
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
45
+ * secure indicates the bank to use for banked exceptions (we assert if
27
{
46
+ * we are passed secure=true for a non-banked exception).
28
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
47
+ */
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
+static int get_prio(NVICState *s, unsigned irq, bool secure)
30
index XXXXXXX..XXXXXXX 100644
49
+{
31
--- a/target/arm/helper.c
50
+ assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
32
+++ b/target/arm/helper.c
51
+ assert(irq < s->num_irq);
33
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
52
34
if (cpu_isar_feature(aa64_scxtnum, cpu)) {
53
- trace_nvic_set_prio(irq, prio);
35
valid_mask |= HCR_ENSCXT;
54
+ if (secure) {
36
}
55
+ assert(exc_is_banked(irq));
37
+ if (cpu_isar_feature(aa64_fwb, cpu)) {
56
+ return s->sec_vectors[irq].prio;
38
+ valid_mask |= HCR_FWB;
39
+ }
40
}
41
42
/* Clear RES0 bits. */
43
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
44
* HCR_PTW forbids certain page-table setups
45
* HCR_DC disables stage1 and enables stage2 translation
46
* HCR_DCT enables tagging on (disabled) stage1 translation
47
+ * HCR_FWB changes the interpretation of stage2 descriptor bits
48
*/
49
- if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) {
50
+ if ((env->cp15.hcr_el2 ^ value) &
51
+ (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) {
52
tlb_flush(CPU(cpu));
53
}
54
env->cp15.hcr_el2 = value;
55
@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
56
* attributes are therefore only Device if stage 2 specifies Device.
57
* With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
58
* ie when cacheattrs.attrs bits [3:2] are 0b00.
59
+ * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
60
+ * when cacheattrs.attrs bit [2] is 0.
61
*/
62
assert(cacheattrs.is_s2_format);
63
- return (cacheattrs.attrs & 0xc) == 0;
64
+ if (arm_hcr_el2_eff(env) & HCR_FWB) {
65
+ return (cacheattrs.attrs & 0x4) == 0;
57
+ } else {
66
+ } else {
58
+ return s->vectors[irq].prio;
67
+ return (cacheattrs.attrs & 0xc) == 0;
59
+ }
68
+ }
60
}
69
}
61
70
62
/* Recompute state and assert irq line accordingly.
71
/* Translate a S1 pagetable walk through S2 if needed. */
63
@@ -XXX,XX +XXX,XX @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
72
@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_nofwb(CPUARMState *env,
64
}
73
return ret_attrs;
65
}
74
}
66
75
67
+static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
76
+static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
68
+{
77
+{
69
+ /* Behaviour for the SHPR register field for this exception:
78
+ /*
70
+ * return M_REG_NS to use the nonsecure vector (including for
79
+ * Given the 4 bits specifying the outer or inner cacheability
71
+ * non-banked exceptions), M_REG_S for the secure version of
80
+ * in MAIR format, return a value specifying Normal Write-Back,
72
+ * a banked exception, and -1 if this field should RAZ/WI.
81
+ * with the allocation and transient hints taken from the input
82
+ * if the input specified some kind of cacheable attribute.
73
+ */
83
+ */
74
+ switch (exc) {
84
+ if (attr == 0 || attr == 4) {
75
+ case ARMV7M_EXCP_MEM:
85
+ /*
76
+ case ARMV7M_EXCP_USAGE:
86
+ * 0 == an UNPREDICTABLE encoding
77
+ case ARMV7M_EXCP_SVC:
87
+ * 4 == Non-cacheable
78
+ case ARMV7M_EXCP_PENDSV:
88
+ * Either way, force Write-Back RW allocate non-transient
79
+ case ARMV7M_EXCP_SYSTICK:
89
+ */
80
+ /* Banked exceptions */
90
+ return 0xf;
81
+ return attrs.secure;
91
+ }
82
+ case ARMV7M_EXCP_BUS:
92
+ /* Change WriteThrough to WriteBack, keep allocation and transient hints */
83
+ /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
93
+ return attr | 4;
84
+ if (!attrs.secure &&
94
+}
85
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
95
+
86
+ return -1;
96
+/*
97
+ * Combine the memory type and cacheability attributes of
98
+ * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
99
+ * combined attributes in MAIR_EL1 format.
100
+ */
101
+static uint8_t combined_attrs_fwb(CPUARMState *env,
102
+ ARMCacheAttrs s1, ARMCacheAttrs s2)
103
+{
104
+ switch (s2.attrs) {
105
+ case 7:
106
+ /* Use stage 1 attributes */
107
+ return s1.attrs;
108
+ case 6:
109
+ /*
110
+ * Force Normal Write-Back. Note that if S1 is Normal cacheable
111
+ * then we take the allocation hints from it; otherwise it is
112
+ * RW allocate, non-transient.
113
+ */
114
+ if ((s1.attrs & 0xf0) == 0) {
115
+ /* S1 is Device */
116
+ return 0xff;
87
+ }
117
+ }
88
+ return M_REG_NS;
118
+ /* Need to check the Inner and Outer nibbles separately */
89
+ case ARMV7M_EXCP_SECURE:
119
+ return force_cacheattr_nibble_wb(s1.attrs & 0xf) |
90
+ /* Not banked, RAZ/WI from nonsecure */
120
+ force_cacheattr_nibble_wb(s1.attrs >> 4) << 4;
91
+ if (!attrs.secure) {
121
+ case 5:
92
+ return -1;
122
+ /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
123
+ if ((s1.attrs & 0xf0) == 0) {
124
+ return s1.attrs;
93
+ }
125
+ }
94
+ return M_REG_NS;
126
+ return 0x44;
95
+ case ARMV7M_EXCP_DEBUG:
127
+ case 0 ... 3:
96
+ /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
128
+ /* Force Device, of subtype specified by S2 */
97
+ return M_REG_NS;
129
+ return s2.attrs << 2;
98
+ case 8 ... 10:
99
+ case 13:
100
+ /* RES0 */
101
+ return -1;
102
+ default:
130
+ default:
103
+ /* Not reachable due to decode of SHPR register addresses */
131
+ /*
104
+ g_assert_not_reached();
132
+ * RESERVED values (including RES0 descriptor bit [5] being nonzero);
133
+ * arbitrarily force Device.
134
+ */
135
+ return 0;
105
+ }
136
+ }
106
+}
137
+}
107
+
138
+
108
static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
139
/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
109
uint64_t *data, unsigned size,
140
* and CombineS1S2Desc()
110
MemTxAttrs attrs)
141
*
111
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
142
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
112
}
143
}
113
}
144
114
break;
145
/* Combine memory type and cacheability attributes */
115
- case 0xd18 ... 0xd23: /* System Handler Priority. */
146
- ret.attrs = combined_attrs_nofwb(env, s1, s2);
116
+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
147
+ if (arm_hcr_el2_eff(env) & HCR_FWB) {
117
val = 0;
148
+ ret.attrs = combined_attrs_fwb(env, s1, s2);
118
for (i = 0; i < size; i++) {
149
+ } else {
119
- val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
150
+ ret.attrs = combined_attrs_nofwb(env, s1, s2);
120
+ unsigned hdlidx = (offset - 0xd14) + i;
151
+ }
121
+ int sbank = shpr_bank(s, hdlidx, attrs);
152
122
+
153
/*
123
+ if (sbank < 0) {
154
* Any location for which the resultant memory type is any
124
+ continue;
125
+ }
126
+ val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
127
}
128
break;
129
case 0xfe0 ... 0xfff: /* ID. */
130
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
131
132
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
133
if (attrs.secure || s->itns[startvec + i]) {
134
- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
135
+ set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
136
}
137
}
138
nvic_irq_update(s);
139
return MEMTX_OK;
140
- case 0xd18 ... 0xd23: /* System Handler Priority. */
141
+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
142
for (i = 0; i < size; i++) {
143
unsigned hdlidx = (offset - 0xd14) + i;
144
- set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
145
+ int newprio = extract32(value, i * 8, 8);
146
+ int sbank = shpr_bank(s, hdlidx, attrs);
147
+
148
+ if (sbank < 0) {
149
+ continue;
150
+ }
151
+ set_prio(s, hdlidx, sbank, newprio);
152
}
153
nvic_irq_update(s);
154
return MEMTX_OK;
155
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
156
index XXXXXXX..XXXXXXX 100644
157
--- a/hw/intc/trace-events
158
+++ b/hw/intc/trace-events
159
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
160
# hw/intc/armv7m_nvic.c
161
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
162
nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
163
-nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
164
+nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
165
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
166
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
167
nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
168
--
155
--
169
2.7.4
156
2.25.1
170
171
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/31] nvic: Handle v8M changes in nvic_exec_prio()
[PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max
1
Update nvic_exec_prio() to support the v8M changes:
1
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that
2
* BASEPRI, FAULTMASK and PRIMASK are all banked
2
CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the
3
* AIRCR.PRIS can affect NS priorities
3
inherited CLIDR_EL1 value from the Cortex-A57 has them as 1).
4
* AIRCR.BFHFNMINS affects FAULTMASK behaviour
5
6
These changes mean that it's no longer possible to
7
definitely say that if FAULTMASK is set it overrides
8
PRIMASK, and if PRIMASK is set it overrides BASEPRI
9
(since if PRIMASK_NS is set and AIRCR.PRIS is set then
10
whether that 0x80 priority should take effect or the
11
priority in BASEPRI_S depends on the value of BASEPRI_S,
12
for instance). So we switch to the same approach used
13
by the pseudocode of working through BASEPRI, PRIMASK
14
and FAULTMASK and overriding the previous values if
15
needed.
16
4
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 1505240046-11454-16-git-send-email-peter.maydell@linaro.org
7
Message-id: 20220505183950.2781801-5-peter.maydell@linaro.org
20
---
8
---
21
hw/intc/armv7m_nvic.c | 51 ++++++++++++++++++++++++++++++++++++++++++---------
9
docs/system/arm/emulation.rst | 1 +
22
1 file changed, 42 insertions(+), 9 deletions(-)
10
target/arm/cpu64.c | 11 +++++++++++
11
2 files changed, 12 insertions(+)
23
12
24
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
13
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/intc/armv7m_nvic.c
15
--- a/docs/system/arm/emulation.rst
27
+++ b/hw/intc/armv7m_nvic.c
16
+++ b/docs/system/arm/emulation.rst
28
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
17
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
29
static inline int nvic_exec_prio(NVICState *s)
18
- FEAT_RAS (Reliability, availability, and serviceability)
19
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
20
- FEAT_RNG (Random number generator)
21
+- FEAT_S2FWB (Stage 2 forced Write-Back)
22
- FEAT_SB (Speculation Barrier)
23
- FEAT_SEL2 (Secure EL2)
24
- FEAT_SHA1 (SHA1 instructions)
25
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/cpu64.c
28
+++ b/target/arm/cpu64.c
29
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
30
{
30
{
31
CPUARMState *env = &s->cpu->env;
31
ARMCPU *cpu = ARM_CPU(obj);
32
- int running;
32
uint64_t t;
33
+ int running = NVIC_NOEXC_PRIO;
33
+ uint32_t u;
34
34
35
- if (env->v7m.faultmask[env->v7m.secure]) {
35
if (kvm_enabled() || hvf_enabled()) {
36
- running = -1;
36
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
37
- } else if (env->v7m.primask[env->v7m.secure]) {
37
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
38
+ if (env->v7m.basepri[M_REG_NS] > 0) {
38
t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
39
+ running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
39
cpu->midr = t;
40
+ }
40
41
+ /*
42
+ * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
43
+ * are zero.
44
+ */
45
+ u = cpu->clidr;
46
+ u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
47
+ u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
48
+ cpu->clidr = u;
41
+
49
+
42
+ if (env->v7m.basepri[M_REG_S] > 0) {
50
t = cpu->isar.id_aa64isar0;
43
+ int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
51
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
44
+ if (running > basepri) {
52
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
45
+ running = basepri;
53
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
46
+ }
54
t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
47
+ }
55
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
48
+
56
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
49
+ if (env->v7m.primask[M_REG_NS]) {
57
+ t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
50
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
58
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
51
+ if (running > NVIC_NS_PRIO_LIMIT) {
59
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
52
+ running = NVIC_NS_PRIO_LIMIT;
60
cpu->isar.id_aa64mmfr2 = t;
53
+ }
54
+ } else {
55
+ running = 0;
56
+ }
57
+ }
58
+
59
+ if (env->v7m.primask[M_REG_S]) {
60
running = 0;
61
- } else if (env->v7m.basepri[env->v7m.secure] > 0) {
62
- running = env->v7m.basepri[env->v7m.secure] &
63
- nvic_gprio_mask(s, env->v7m.secure);
64
- } else {
65
- running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
66
}
67
+
68
+ if (env->v7m.faultmask[M_REG_NS]) {
69
+ if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
70
+ running = -1;
71
+ } else {
72
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
73
+ if (running > NVIC_NS_PRIO_LIMIT) {
74
+ running = NVIC_NS_PRIO_LIMIT;
75
+ }
76
+ } else {
77
+ running = 0;
78
+ }
79
+ }
80
+ }
81
+
82
+ if (env->v7m.faultmask[M_REG_S]) {
83
+ running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
84
+ }
85
+
86
/* consider priority of active handler */
87
return MIN(running, s->exception_prio);
88
}
89
--
61
--
90
2.7.4
62
2.25.1
91
92
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/31] nvic: Handle banked exceptions in nvic_recompute_state()
[PULL 05/22] target/arm: Implement FEAT_IDST
1
Update the nvic_recompute_state() code to handle the security
1
The Armv8.4 feature FEAT_IDST specifies that exceptions generated by
2
extension and its associated banked registers.
2
read accesses to the feature ID space should report a syndrome code
3
of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED).
4
The feature ID space is defined to be:
5
op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7}, op2 == {0-7}
3
6
4
Code that uses the resulting cached state (ie the irq
7
In our implementation we might return the EC_UNCATEGORIZED syndrome
5
acknowledge and complete code) will be updated in a later
8
value for a system register access in four cases:
6
commit.
9
* no reginfo struct in the hashtable
10
* cp_access_ok() fails (ie ri->access doesn't permit the access)
11
* ri->accessfn returns CP_ACCESS_TRAP_UNCATEGORIZED at runtime
12
* ri->type includes ARM_CP_RAISES_EXC, and the readfn raises
13
an UNDEF exception at runtime
14
15
We have very few regdefs that set ARM_CP_RAISES_EXC, and none of
16
them are in the feature ID space. (In the unlikely event that any
17
are added in future they would need to take care of setting the
18
correct syndrome themselves.) This patch deals with the other
19
three cases, and enables FEAT_IDST for AArch64 -cpu max.
7
20
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
23
Message-id: 20220509155457.3560724-1-peter.maydell@linaro.org
11
---
24
---
12
hw/intc/armv7m_nvic.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++--
25
docs/system/arm/emulation.rst | 1 +
13
hw/intc/trace-events | 1 +
26
target/arm/cpregs.h | 24 ++++++++++++++++++++++++
14
2 files changed, 147 insertions(+), 5 deletions(-)
27
target/arm/cpu.h | 5 +++++
28
target/arm/cpu64.c | 1 +
29
target/arm/op_helper.c | 9 +++++++++
30
target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++--
31
6 files changed, 66 insertions(+), 2 deletions(-)
15
32
16
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
33
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/armv7m_nvic.c
35
--- a/docs/system/arm/emulation.rst
19
+++ b/hw/intc/armv7m_nvic.c
36
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
* (higher than the highest possible priority value)
38
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
22
*/
39
- FEAT_HPDS (Hierarchical permission disables)
23
#define NVIC_NOEXC_PRIO 0x100
40
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
24
+/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
41
+- FEAT_IDST (ID space trap handling)
25
+#define NVIC_NS_PRIO_LIMIT 0x80
42
- FEAT_IESB (Implicit error synchronization event)
26
43
- FEAT_JSCVT (JavaScript conversion instructions)
27
static const uint8_t nvic_id[] = {
44
- FEAT_LOR (Limited ordering regions)
28
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
45
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
29
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
46
index XXXXXXX..XXXXXXX 100644
30
return false;
47
--- a/target/arm/cpregs.h
31
}
48
+++ b/target/arm/cpregs.h
32
49
@@ -XXX,XX +XXX,XX @@ static inline bool cp_access_ok(int current_el,
33
+static bool exc_is_banked(int exc)
50
/* Raw read of a coprocessor register (as needed for migration, etc) */
51
uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
52
53
+/*
54
+ * Return true if the cp register encoding is in the "feature ID space" as
55
+ * defined by FEAT_IDST (and thus should be reported with ER_ELx.EC
56
+ * as EC_SYSTEMREGISTERTRAP rather than EC_UNCATEGORIZED).
57
+ */
58
+static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1,
59
+ uint8_t opc2,
60
+ uint8_t crn, uint8_t crm)
34
+{
61
+{
35
+ /* Return true if this is one of the limited set of exceptions which
62
+ return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) &&
36
+ * are banked (and thus have state in sec_vectors[])
63
+ crn == 0 && crm < 8;
37
+ */
38
+ return exc == ARMV7M_EXCP_HARD ||
39
+ exc == ARMV7M_EXCP_MEM ||
40
+ exc == ARMV7M_EXCP_USAGE ||
41
+ exc == ARMV7M_EXCP_SVC ||
42
+ exc == ARMV7M_EXCP_PENDSV ||
43
+ exc == ARMV7M_EXCP_SYSTICK;
44
+}
64
+}
45
+
65
+
46
/* Return a mask word which clears the subpriority bits from
66
+/*
47
* a priority value for an M-profile exception, leaving only
67
+ * As arm_cpreg_encoding_in_idspace(), but take the encoding from an
48
* the group priority.
68
+ * ARMCPRegInfo.
49
*/
69
+ */
50
-static inline uint32_t nvic_gprio_mask(NVICState *s)
70
+static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri)
51
+static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
52
+{
71
+{
53
+ return ~0U << (s->prigroup[secure] + 1);
72
+ return ri->state == ARM_CP_STATE_AA64 &&
73
+ arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2,
74
+ ri->crn, ri->crm);
54
+}
75
+}
55
+
76
+
56
+static bool exc_targets_secure(NVICState *s, int exc)
77
#endif /* TARGET_ARM_CPREGS_H */
78
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/arm/cpu.h
81
+++ b/target/arm/cpu.h
82
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
83
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
84
}
85
86
+static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
57
+{
87
+{
58
+ /* Return true if this non-banked exception targets Secure state. */
88
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
59
+ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
60
+ return false;
61
+ }
62
+
63
+ if (exc >= NVIC_FIRST_IRQ) {
64
+ return !s->itns[exc];
65
+ }
66
+
67
+ /* Function shouldn't be called for banked exceptions. */
68
+ assert(!exc_is_banked(exc));
69
+
70
+ switch (exc) {
71
+ case ARMV7M_EXCP_NMI:
72
+ case ARMV7M_EXCP_BUS:
73
+ return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
74
+ case ARMV7M_EXCP_SECURE:
75
+ return true;
76
+ case ARMV7M_EXCP_DEBUG:
77
+ /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
78
+ return false;
79
+ default:
80
+ /* reset, and reserved (unused) low exception numbers.
81
+ * We'll get called by code that loops through all the exception
82
+ * numbers, but it doesn't matter what we return here as these
83
+ * non-existent exceptions will never be pended or active.
84
+ */
85
+ return true;
86
+ }
87
+}
89
+}
88
+
90
+
89
+static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
91
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
92
{
93
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
94
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/target/arm/cpu64.c
97
+++ b/target/arm/cpu64.c
98
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
99
t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
100
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
101
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
102
+ t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
103
t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
104
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
105
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
106
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/op_helper.c
109
+++ b/target/arm/op_helper.c
110
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
111
void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
112
uint32_t isread)
113
{
114
+ ARMCPU *cpu = env_archcpu(env);
115
const ARMCPRegInfo *ri = rip;
116
CPAccessResult res = CP_ACCESS_OK;
117
int target_el;
118
@@ -XXX,XX +XXX,XX @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
119
case CP_ACCESS_TRAP:
120
break;
121
case CP_ACCESS_TRAP_UNCATEGORIZED:
122
+ if (cpu_isar_feature(aa64_ids, cpu) && isread &&
123
+ arm_cpreg_in_idspace(ri)) {
124
+ /*
125
+ * FEAT_IDST says this should be reported as EC_SYSTEMREGISTERTRAP,
126
+ * not EC_UNCATEGORIZED
127
+ */
128
+ break;
129
+ }
130
syndrome = syn_uncategorized();
131
break;
132
default:
133
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/target/arm/translate-a64.c
136
+++ b/target/arm/translate-a64.c
137
@@ -XXX,XX +XXX,XX @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
138
tcg_temp_free_i32(nzcv);
139
}
140
141
+static void gen_sysreg_undef(DisasContext *s, bool isread,
142
+ uint8_t op0, uint8_t op1, uint8_t op2,
143
+ uint8_t crn, uint8_t crm, uint8_t rt)
90
+{
144
+{
91
+ /* Return the group priority for this exception, given its raw
145
+ /*
92
+ * (group-and-subgroup) priority value and whether it is targeting
146
+ * Generate code to emit an UNDEF with correct syndrome
93
+ * secure state or not.
147
+ * information for a failed system register access.
148
+ * This is EC_UNCATEGORIZED (ie a standard UNDEF) in most cases,
149
+ * but if FEAT_IDST is implemented then read accesses to registers
150
+ * in the feature ID space are reported with the EC_SYSTEMREGISTERTRAP
151
+ * syndrome.
94
+ */
152
+ */
95
+ if (rawprio < 0) {
153
+ uint32_t syndrome;
96
+ return rawprio;
154
+
155
+ if (isread && dc_isar_feature(aa64_ids, s) &&
156
+ arm_cpreg_encoding_in_idspace(op0, op1, op2, crn, crm)) {
157
+ syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
158
+ } else {
159
+ syndrome = syn_uncategorized();
97
+ }
160
+ }
98
+ rawprio &= nvic_gprio_mask(s, targets_secure);
161
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome,
99
+ /* AIRCR.PRIS causes us to squash all NS priorities into the
162
+ default_exception_el(s));
100
+ * lower half of the total range
101
+ */
102
+ if (!targets_secure &&
103
+ (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
104
+ rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
105
+ }
106
+ return rawprio;
107
+}
163
+}
108
+
164
+
109
+/* Recompute vectpending and exception_prio for a CPU which implements
165
/* MRS - move from system register
110
+ * the Security extension
166
* MSR (register) - move to system register
111
+ */
167
* SYS
112
+static void nvic_recompute_state_secure(NVICState *s)
168
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
113
{
169
qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
114
- return ~0U << (s->prigroup[M_REG_NS] + 1);
170
"system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
115
+ int i, bank;
171
isread ? "read" : "write", op0, op1, crn, crm, op2);
116
+ int pend_prio = NVIC_NOEXC_PRIO;
172
- unallocated_encoding(s);
117
+ int active_prio = NVIC_NOEXC_PRIO;
173
+ gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt);
118
+ int pend_irq = 0;
174
return;
119
+ bool pending_is_s_banked = false;
120
+
121
+ /* R_CQRV: precedence is by:
122
+ * - lowest group priority; if both the same then
123
+ * - lowest subpriority; if both the same then
124
+ * - lowest exception number; if both the same (ie banked) then
125
+ * - secure exception takes precedence
126
+ * Compare pseudocode RawExecutionPriority.
127
+ * Annoyingly, now we have two prigroup values (for S and NS)
128
+ * we can't do the loop comparison on raw priority values.
129
+ */
130
+ for (i = 1; i < s->num_irq; i++) {
131
+ for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
132
+ VecInfo *vec;
133
+ int prio;
134
+ bool targets_secure;
135
+
136
+ if (bank == M_REG_S) {
137
+ if (!exc_is_banked(i)) {
138
+ continue;
139
+ }
140
+ vec = &s->sec_vectors[i];
141
+ targets_secure = true;
142
+ } else {
143
+ vec = &s->vectors[i];
144
+ targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
145
+ }
146
+
147
+ prio = exc_group_prio(s, vec->prio, targets_secure);
148
+ if (vec->enabled && vec->pending && prio < pend_prio) {
149
+ pend_prio = prio;
150
+ pend_irq = i;
151
+ pending_is_s_banked = (bank == M_REG_S);
152
+ }
153
+ if (vec->active && prio < active_prio) {
154
+ active_prio = prio;
155
+ }
156
+ }
157
+ }
158
+
159
+ s->vectpending_is_s_banked = pending_is_s_banked;
160
+ s->vectpending = pend_irq;
161
+ s->vectpending_prio = pend_prio;
162
+ s->exception_prio = active_prio;
163
+
164
+ trace_nvic_recompute_state_secure(s->vectpending,
165
+ s->vectpending_is_s_banked,
166
+ s->vectpending_prio,
167
+ s->exception_prio);
168
}
169
170
/* Recompute vectpending and exception_prio */
171
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
172
int active_prio = NVIC_NOEXC_PRIO;
173
int pend_irq = 0;
174
175
+ /* In theory we could write one function that handled both
176
+ * the "security extension present" and "not present"; however
177
+ * the security related changes significantly complicate the
178
+ * recomputation just by themselves and mixing both cases together
179
+ * would be even worse, so we retain a separate non-secure-only
180
+ * version for CPUs which don't implement the security extension.
181
+ */
182
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
183
+ nvic_recompute_state_secure(s);
184
+ return;
185
+ }
186
+
187
for (i = 1; i < s->num_irq; i++) {
188
VecInfo *vec = &s->vectors[i];
189
190
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
191
}
175
}
192
176
193
if (active_prio > 0) {
177
/* Check access permissions */
194
- active_prio &= nvic_gprio_mask(s);
178
if (!cp_access_ok(s->current_el, ri, isread)) {
195
+ active_prio &= nvic_gprio_mask(s, false);
179
- unallocated_encoding(s);
180
+ gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt);
181
return;
196
}
182
}
197
183
198
if (pend_prio > 0) {
199
- pend_prio &= nvic_gprio_mask(s);
200
+ pend_prio &= nvic_gprio_mask(s, false);
201
}
202
203
s->vectpending = pend_irq;
204
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
205
} else if (env->v7m.primask[env->v7m.secure]) {
206
running = 0;
207
} else if (env->v7m.basepri[env->v7m.secure] > 0) {
208
- running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
209
+ running = env->v7m.basepri[env->v7m.secure] &
210
+ nvic_gprio_mask(s, env->v7m.secure);
211
} else {
212
running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
213
}
214
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/intc/trace-events
217
+++ b/hw/intc/trace-events
218
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
219
220
# hw/intc/armv7m_nvic.c
221
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
222
+nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
223
nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
224
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
225
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
226
--
184
--
227
2.7.4
185
2.25.1
228
229
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/31] target/arm: Remove out of date ARM ARM section references in A64 decoder
[PULL 06/22] target/arm: Drop unsupported_encoding() macro
1
In the A64 decoder, we have a lot of references to section numbers
1
The unsupported_encoding() macro logs a LOG_UNIMP message and then
2
from version A.a of the v8A ARM ARM (DDI0487). This version of the
2
generates code to raise the usual exception for an unallocated
3
document is now long obsolete (we are currently on revision B.a),
3
encoding. Back when we were still implementing the A64 decoder this
4
and various intervening versions renumbered all the sections.
4
was helpful for flagging up when guest code was using something we
5
hadn't yet implemented. Now we completely cover the A64 instruction
6
set it is barely used. The only remaining uses are for five
7
instructions whose semantics are "UNDEF, unless being run under
8
external halting debug":
9
* HLT (when not being used for semihosting)
10
* DCPSR1, DCPS2, DCPS3
11
* DRPS
5
12
6
The most recent B.a version of the document doesn't assign
13
QEMU doesn't implement external halting debug, so for us the UNDEF is
7
section numbers at all to the individual instruction classes
14
the architecturally correct behaviour (because it's not possible to
8
in the way that the various A.x versions did. The simplest thing
15
execute these instructions with halting debug enabled). The
9
to do is just to delete all the out of date C.x.x references.
16
LOG_UNIMP doesn't serve a useful purpose; replace these uses of
17
unsupported_encoding() with unallocated_encoding(), and delete the
18
macro.
10
19
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20170915150849.23557-1-peter.maydell@linaro.org
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20220509160443.3561604-1-peter.maydell@linaro.org
14
---
24
---
15
target/arm/translate-a64.c | 227 +++++++++++++++++++++++----------------------
25
target/arm/translate-a64.h | 9 ---------
16
1 file changed, 114 insertions(+), 113 deletions(-)
26
target/arm/translate-a64.c | 8 ++++----
27
2 files changed, 4 insertions(+), 13 deletions(-)
17
28
29
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate-a64.h
32
+++ b/target/arm/translate-a64.h
33
@@ -XXX,XX +XXX,XX @@
34
#ifndef TARGET_ARM_TRANSLATE_A64_H
35
#define TARGET_ARM_TRANSLATE_A64_H
36
37
-#define unsupported_encoding(s, insn) \
38
- do { \
39
- qemu_log_mask(LOG_UNIMP, \
40
- "%s:%d: unsupported instruction encoding 0x%08x " \
41
- "at pc=%016" PRIx64 "\n", \
42
- __FILE__, __LINE__, insn, s->pc_curr); \
43
- unallocated_encoding(s); \
44
- } while (0)
45
-
46
TCGv_i64 new_tmp_a64(DisasContext *s);
47
TCGv_i64 new_tmp_a64_local(DisasContext *s);
48
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
49
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
51
--- a/target/arm/translate-a64.c
21
+++ b/target/arm/translate-a64.c
52
+++ b/target/arm/translate-a64.c
22
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
53
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
23
}
54
* with our 32-bit semihosting).
24
55
*/
25
/*
56
if (s->current_el == 0) {
26
- * the instruction disassembly implemented here matches
57
- unsupported_encoding(s, insn);
27
- * the instruction encoding classifications in chapter 3 (C3)
58
+ unallocated_encoding(s);
28
- * of the ARM Architecture Reference Manual (DDI0487A_a)
59
break;
29
+ * The instruction disassembly implemented here matches
60
}
30
+ * the instruction encoding classifications in chapter C4
61
#endif
31
+ * of the ARM Architecture Reference Manual (DDI0487B_a);
62
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
32
+ * classification names and decode diagrams here should generally
63
} else {
33
+ * match up with those in the manual.
64
- unsupported_encoding(s, insn);
34
*/
65
+ unallocated_encoding(s);
35
36
-/* C3.2.7 Unconditional branch (immediate)
37
+/* Unconditional branch (immediate)
38
* 31 30 26 25 0
39
* +----+-----------+-------------------------------------+
40
* | op | 0 0 1 0 1 | imm26 |
41
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
42
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
43
44
if (insn & (1U << 31)) {
45
- /* C5.6.26 BL Branch with link */
46
+ /* BL Branch with link */
47
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
48
}
49
50
- /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
51
+ /* B Branch / BL Branch with link */
52
gen_goto_tb(s, 0, addr);
53
}
54
55
-/* C3.2.1 Compare & branch (immediate)
56
+/* Compare and branch (immediate)
57
* 31 30 25 24 23 5 4 0
58
* +----+-------------+----+---------------------+--------+
59
* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
60
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
61
gen_goto_tb(s, 1, addr);
62
}
63
64
-/* C3.2.5 Test & branch (immediate)
65
+/* Test and branch (immediate)
66
* 31 30 25 24 23 19 18 5 4 0
67
* +----+-------------+----+-------+-------------+------+
68
* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
69
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
70
gen_goto_tb(s, 1, addr);
71
}
72
73
-/* C3.2.2 / C5.6.19 Conditional branch (immediate)
74
+/* Conditional branch (immediate)
75
* 31 25 24 23 5 4 3 0
76
* +---------------+----+---------------------+----+------+
77
* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
78
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
79
}
80
}
81
82
-/* C5.6.68 HINT */
83
+/* HINT instruction group, including various allocated HINTs */
84
static void handle_hint(DisasContext *s, uint32_t insn,
85
unsigned int op1, unsigned int op2, unsigned int crm)
86
{
87
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
88
}
89
}
90
91
-/* C5.6.130 MSR (immediate) - move immediate to processor state field */
92
+/* MSR (immediate) - move immediate to processor state field */
93
static void handle_msr_i(DisasContext *s, uint32_t insn,
94
unsigned int op1, unsigned int op2, unsigned int crm)
95
{
96
@@ -XXX,XX +XXX,XX @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
97
tcg_temp_free_i32(nzcv);
98
}
99
100
-/* C5.6.129 MRS - move from system register
101
- * C5.6.131 MSR (register) - move to system register
102
- * C5.6.204 SYS
103
- * C5.6.205 SYSL
104
+/* MRS - move from system register
105
+ * MSR (register) - move to system register
106
+ * SYS
107
+ * SYSL
108
* These are all essentially the same insn in 'read' and 'write'
109
* versions, with varying op0 fields.
110
*/
111
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
112
}
113
}
114
115
-/* C3.2.4 System
116
+/* System
117
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
118
* +---------------------+---+-----+-----+-------+-------+-----+------+
119
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
120
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
121
return;
122
}
66
}
123
switch (crn) {
67
break;
124
- case 2: /* C5.6.68 HINT */
68
case 5:
125
+ case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
69
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
126
handle_hint(s, insn, op1, op2, crm);
127
break;
70
break;
128
case 3: /* CLREX, DSB, DMB, ISB */
71
}
129
handle_sync(s, insn, op1, op2, crm);
72
/* DCPS1, DCPS2, DCPS3 */
130
break;
73
- unsupported_encoding(s, insn);
131
- case 4: /* C5.6.130 MSR (immediate) */
74
+ unallocated_encoding(s);
132
+ case 4: /* MSR (immediate) */
75
break;
133
handle_msr_i(s, insn, op1, op2, crm);
76
default:
134
break;
77
unallocated_encoding(s);
135
default:
136
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
137
handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
138
}
139
140
-/* C3.2.3 Exception generation
141
+/* Exception generation
142
*
143
* 31 24 23 21 20 5 4 2 1 0
144
* +-----------------+-----+------------------------+-----+----+
145
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
146
}
147
}
148
149
-/* C3.2.7 Unconditional branch (register)
150
+/* Unconditional branch (register)
151
* 31 25 24 21 20 16 15 10 9 5 4 0
152
* +---------------+-------+-------+-------+------+-------+
153
* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
154
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
78
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
155
s->base.is_jmp = DISAS_JUMP;
79
if (op3 != 0 || op4 != 0 || rn != 0x1f) {
156
}
80
goto do_unallocated;
157
81
} else {
158
-/* C3.2 Branches, exception generating and system instructions */
82
- unsupported_encoding(s, insn);
159
+/* Branches, exception generating and system instructions */
83
+ unallocated_encoding(s);
160
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
84
}
161
{
85
return;
162
switch (extract32(insn, 25, 7)) {
86
163
@@ -XXX,XX +XXX,XX @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
164
return regsize == 64;
165
}
166
167
-/* C3.3.6 Load/store exclusive
168
+/* Load/store exclusive
169
*
170
* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
171
* +-----+-------------+----+---+----+------+----+-------+------+------+
172
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
173
}
174
175
/*
176
- * C3.3.5 Load register (literal)
177
+ * Load register (literal)
178
*
179
* 31 30 29 27 26 25 24 23 5 4 0
180
* +-----+-------+---+-----+-------------------+-------+
181
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
182
}
183
184
/*
185
- * C5.6.80 LDNP (Load Pair - non-temporal hint)
186
- * C5.6.81 LDP (Load Pair - non vector)
187
- * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
188
- * C5.6.176 STNP (Store Pair - non-temporal hint)
189
- * C5.6.177 STP (Store Pair - non vector)
190
- * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
191
- * C6.3.165 LDP (Load Pair of SIMD&FP)
192
- * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
193
- * C6.3.284 STP (Store Pair of SIMD&FP)
194
+ * LDNP (Load Pair - non-temporal hint)
195
+ * LDP (Load Pair - non vector)
196
+ * LDPSW (Load Pair Signed Word - non vector)
197
+ * STNP (Store Pair - non-temporal hint)
198
+ * STP (Store Pair - non vector)
199
+ * LDNP (Load Pair of SIMD&FP - non-temporal hint)
200
+ * LDP (Load Pair of SIMD&FP)
201
+ * STNP (Store Pair of SIMD&FP - non-temporal hint)
202
+ * STP (Store Pair of SIMD&FP)
203
*
204
* 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
205
* +-----+-------+---+---+-------+---+-----------------------------+
206
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
207
}
208
209
/*
210
- * C3.3.8 Load/store (immediate post-indexed)
211
- * C3.3.9 Load/store (immediate pre-indexed)
212
- * C3.3.12 Load/store (unscaled immediate)
213
+ * Load/store (immediate post-indexed)
214
+ * Load/store (immediate pre-indexed)
215
+ * Load/store (unscaled immediate)
216
*
217
* 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
218
* +----+-------+---+-----+-----+---+--------+-----+------+------+
219
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
220
}
221
222
/*
223
- * C3.3.10 Load/store (register offset)
224
+ * Load/store (register offset)
225
*
226
* 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
227
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
228
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
229
}
230
231
/*
232
- * C3.3.13 Load/store (unsigned immediate)
233
+ * Load/store (unsigned immediate)
234
*
235
* 31 30 29 27 26 25 24 23 22 21 10 9 5
236
* +----+-------+---+-----+-----+------------+-------+------+
237
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
238
}
239
}
240
241
-/* C3.3.1 AdvSIMD load/store multiple structures
242
+/* AdvSIMD load/store multiple structures
243
*
244
* 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
245
* +---+---+---------------+---+-------------+--------+------+------+------+
246
* | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
247
* +---+---+---------------+---+-------------+--------+------+------+------+
248
*
249
- * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
250
+ * AdvSIMD load/store multiple structures (post-indexed)
251
*
252
* 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
253
* +---+---+---------------+---+---+---------+--------+------+------+------+
254
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
255
tcg_temp_free_i64(tcg_addr);
256
}
257
258
-/* C3.3.3 AdvSIMD load/store single structure
259
+/* AdvSIMD load/store single structure
260
*
261
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
262
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
263
* | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
264
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
265
*
266
- * C3.3.4 AdvSIMD load/store single structure (post-indexed)
267
+ * AdvSIMD load/store single structure (post-indexed)
268
*
269
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
270
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
271
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
272
tcg_temp_free_i64(tcg_addr);
273
}
274
275
-/* C3.3 Loads and stores */
276
+/* Loads and stores */
277
static void disas_ldst(DisasContext *s, uint32_t insn)
278
{
279
switch (extract32(insn, 24, 6)) {
280
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
281
}
282
}
283
284
-/* C3.4.6 PC-rel. addressing
285
+/* PC-rel. addressing
286
* 31 30 29 28 24 23 5 4 0
287
* +----+-------+-----------+-------------------+------+
288
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
289
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
290
}
291
292
/*
293
- * C3.4.1 Add/subtract (immediate)
294
+ * Add/subtract (immediate)
295
*
296
* 31 30 29 28 24 23 22 21 10 9 5 4 0
297
* +--+--+--+-----------+-----+-------------+-----+-----+
298
@@ -XXX,XX +XXX,XX @@ static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
299
return true;
300
}
301
302
-/* C3.4.4 Logical (immediate)
303
+/* Logical (immediate)
304
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
305
* +----+-----+-------------+---+------+------+------+------+
306
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
307
@@ -XXX,XX +XXX,XX @@ static void disas_logic_imm(DisasContext *s, uint32_t insn)
308
}
309
310
/*
311
- * C3.4.5 Move wide (immediate)
312
+ * Move wide (immediate)
313
*
314
* 31 30 29 28 23 22 21 20 5 4 0
315
* +--+-----+-------------+-----+----------------+------+
316
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
317
}
318
}
319
320
-/* C3.4.2 Bitfield
321
+/* Bitfield
322
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
323
* +----+-----+-------------+---+------+------+------+------+
324
* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
325
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
326
}
327
}
328
329
-/* C3.4.3 Extract
330
+/* Extract
331
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
332
* +----+------+-------------+---+----+------+--------+------+------+
333
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
334
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
335
}
336
}
337
338
-/* C3.4 Data processing - immediate */
339
+/* Data processing - immediate */
340
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
341
{
342
switch (extract32(insn, 23, 6)) {
343
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
344
}
345
}
346
347
-/* C3.5.10 Logical (shifted register)
348
+/* Logical (shifted register)
349
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
350
* +----+-----+-----------+-------+---+------+--------+------+------+
351
* | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
352
@@ -XXX,XX +XXX,XX @@ static void disas_logic_reg(DisasContext *s, uint32_t insn)
353
}
354
355
/*
356
- * C3.5.1 Add/subtract (extended register)
357
+ * Add/subtract (extended register)
358
*
359
* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
360
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
361
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
362
}
363
364
/*
365
- * C3.5.2 Add/subtract (shifted register)
366
+ * Add/subtract (shifted register)
367
*
368
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
369
* +--+--+--+-----------+-----+--+-------+---------+------+------+
370
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
371
tcg_temp_free_i64(tcg_result);
372
}
373
374
-/* C3.5.9 Data-processing (3 source)
375
-
376
- 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
377
- +--+------+-----------+------+------+----+------+------+------+
378
- |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
379
- +--+------+-----------+------+------+----+------+------+------+
380
-
381
+/* Data-processing (3 source)
382
+ *
383
+ * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
384
+ * +--+------+-----------+------+------+----+------+------+------+
385
+ * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
386
+ * +--+------+-----------+------+------+----+------+------+------+
387
*/
388
static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
389
{
390
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
391
tcg_temp_free_i64(tcg_tmp);
392
}
393
394
-/* C3.5.3 - Add/subtract (with carry)
395
+/* Add/subtract (with carry)
396
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
397
* +--+--+--+------------------------+------+---------+------+-----+
398
* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
399
@@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
400
}
401
}
402
403
-/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
404
+/* Conditional compare (immediate / register)
405
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
406
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
407
* |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
408
@@ -XXX,XX +XXX,XX @@ static void disas_cc(DisasContext *s, uint32_t insn)
409
tcg_temp_free_i32(tcg_t2);
410
}
411
412
-/* C3.5.6 Conditional select
413
+/* Conditional select
414
* 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
415
* +----+----+---+-----------------+------+------+-----+------+------+
416
* | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
417
@@ -XXX,XX +XXX,XX @@ static void handle_rbit(DisasContext *s, unsigned int sf,
418
}
419
}
420
421
-/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
422
+/* REV with sf==1, opcode==3 ("REV64") */
423
static void handle_rev64(DisasContext *s, unsigned int sf,
424
unsigned int rn, unsigned int rd)
425
{
426
@@ -XXX,XX +XXX,XX @@ static void handle_rev64(DisasContext *s, unsigned int sf,
427
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
428
}
429
430
-/* C5.6.149 REV with sf==0, opcode==2
431
- * C5.6.151 REV32 (sf==1, opcode==2)
432
+/* REV with sf==0, opcode==2
433
+ * REV32 (sf==1, opcode==2)
434
*/
435
static void handle_rev32(DisasContext *s, unsigned int sf,
436
unsigned int rn, unsigned int rd)
437
@@ -XXX,XX +XXX,XX @@ static void handle_rev32(DisasContext *s, unsigned int sf,
438
}
439
}
440
441
-/* C5.6.150 REV16 (opcode==1) */
442
+/* REV16 (opcode==1) */
443
static void handle_rev16(DisasContext *s, unsigned int sf,
444
unsigned int rn, unsigned int rd)
445
{
446
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
447
tcg_temp_free_i64(tcg_tmp);
448
}
449
450
-/* C3.5.7 Data-processing (1 source)
451
+/* Data-processing (1 source)
452
* 31 30 29 28 21 20 16 15 10 9 5 4 0
453
* +----+---+---+-----------------+---------+--------+------+------+
454
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
455
@@ -XXX,XX +XXX,XX @@ static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
456
}
457
}
458
459
-/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
460
+/* LSLV, LSRV, ASRV, RORV */
461
static void handle_shift_reg(DisasContext *s,
462
enum a64_shift_type shift_type, unsigned int sf,
463
unsigned int rm, unsigned int rn, unsigned int rd)
464
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
465
tcg_temp_free_i32(tcg_bytes);
466
}
467
468
-/* C3.5.8 Data-processing (2 source)
469
+/* Data-processing (2 source)
470
* 31 30 29 28 21 20 16 15 10 9 5 4 0
471
* +----+---+---+-----------------+------+--------+------+------+
472
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
473
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
474
}
475
}
476
477
-/* C3.5 Data processing - register */
478
+/* Data processing - register */
479
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
480
{
481
switch (extract32(insn, 24, 5)) {
482
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
483
tcg_temp_free_i64(tcg_flags);
484
}
485
486
-/* C3.6.22 Floating point compare
487
+/* Floating point compare
488
* 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
489
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
490
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
491
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
492
handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
493
}
494
495
-/* C3.6.23 Floating point conditional compare
496
+/* Floating point conditional compare
497
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
498
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
499
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
500
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
501
}
502
}
503
504
-/* C3.6.24 Floating point conditional select
505
+/* Floating point conditional select
506
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
507
* +---+---+---+-----------+------+---+------+------+-----+------+------+
508
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
509
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
510
tcg_temp_free_i64(t_true);
511
}
512
513
-/* C3.6.25 Floating-point data-processing (1 source) - single precision */
514
+/* Floating-point data-processing (1 source) - single precision */
515
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
516
{
517
TCGv_ptr fpst;
518
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
519
tcg_temp_free_i32(tcg_res);
520
}
521
522
-/* C3.6.25 Floating-point data-processing (1 source) - double precision */
523
+/* Floating-point data-processing (1 source) - double precision */
524
static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
525
{
526
TCGv_ptr fpst;
527
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
528
}
529
}
530
531
-/* C3.6.25 Floating point data-processing (1 source)
532
+/* Floating point data-processing (1 source)
533
* 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
534
* +---+---+---+-----------+------+---+--------+-----------+------+------+
535
* | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
536
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
537
}
538
}
539
540
-/* C3.6.26 Floating-point data-processing (2 source) - single precision */
541
+/* Floating-point data-processing (2 source) - single precision */
542
static void handle_fp_2src_single(DisasContext *s, int opcode,
543
int rd, int rn, int rm)
544
{
545
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
546
tcg_temp_free_i32(tcg_res);
547
}
548
549
-/* C3.6.26 Floating-point data-processing (2 source) - double precision */
550
+/* Floating-point data-processing (2 source) - double precision */
551
static void handle_fp_2src_double(DisasContext *s, int opcode,
552
int rd, int rn, int rm)
553
{
554
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
555
tcg_temp_free_i64(tcg_res);
556
}
557
558
-/* C3.6.26 Floating point data-processing (2 source)
559
+/* Floating point data-processing (2 source)
560
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
561
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
562
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
563
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
564
}
565
}
566
567
-/* C3.6.27 Floating-point data-processing (3 source) - single precision */
568
+/* Floating-point data-processing (3 source) - single precision */
569
static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
570
int rd, int rn, int rm, int ra)
571
{
572
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
573
tcg_temp_free_i32(tcg_res);
574
}
575
576
-/* C3.6.27 Floating-point data-processing (3 source) - double precision */
577
+/* Floating-point data-processing (3 source) - double precision */
578
static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
579
int rd, int rn, int rm, int ra)
580
{
581
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
582
tcg_temp_free_i64(tcg_res);
583
}
584
585
-/* C3.6.27 Floating point data-processing (3 source)
586
+/* Floating point data-processing (3 source)
587
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
588
* +---+---+---+-----------+------+----+------+----+------+------+------+
589
* | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
590
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
591
}
592
}
593
594
-/* C3.6.28 Floating point immediate
595
+/* Floating point immediate
596
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
597
* +---+---+---+-----------+------+---+------------+-------+------+------+
598
* | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
599
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
600
tcg_temp_free_i32(tcg_shift);
601
}
602
603
-/* C3.6.29 Floating point <-> fixed point conversions
604
+/* Floating point <-> fixed point conversions
605
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
606
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
607
* | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
608
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
609
}
610
}
611
612
-/* C3.6.30 Floating point <-> integer conversions
613
+/* Floating point <-> integer conversions
614
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
615
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
616
* | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
617
@@ -XXX,XX +XXX,XX @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
618
tcg_temp_free_i64(tcg_tmp);
619
}
620
621
-/* C3.6.1 EXT
622
+/* EXT
623
* 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
624
* +---+---+-------------+-----+---+------+---+------+---+------+------+
625
* | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
626
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
627
tcg_temp_free_i64(tcg_resh);
628
}
629
630
-/* C3.6.2 TBL/TBX
631
+/* TBL/TBX
632
* 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
633
* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
634
* | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
635
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
636
tcg_temp_free_i64(tcg_resh);
637
}
638
639
-/* C3.6.3 ZIP/UZP/TRN
640
+/* ZIP/UZP/TRN
641
* 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
642
* +---+---+-------------+------+---+------+---+------------------+------+
643
* | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
644
@@ -XXX,XX +XXX,XX @@ static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
645
}
646
}
647
648
-/* C3.6.4 AdvSIMD across lanes
649
+/* AdvSIMD across lanes
650
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
651
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
652
* | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
653
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
654
tcg_temp_free_i64(tcg_res);
655
}
656
657
-/* C6.3.31 DUP (Element, Vector)
658
+/* DUP (Element, Vector)
659
*
660
* 31 30 29 21 20 16 15 10 9 5 4 0
661
* +---+---+-------------------+--------+-------------+------+------+
662
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
663
tcg_temp_free_i64(tmp);
664
}
665
666
-/* C6.3.31 DUP (element, scalar)
667
+/* DUP (element, scalar)
668
* 31 21 20 16 15 10 9 5 4 0
669
* +-----------------------+--------+-------------+------+------+
670
* | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
671
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupes(DisasContext *s, int rd, int rn,
672
tcg_temp_free_i64(tmp);
673
}
674
675
-/* C6.3.32 DUP (General)
676
+/* DUP (General)
677
*
678
* 31 30 29 21 20 16 15 10 9 5 4 0
679
* +---+---+-------------------+--------+-------------+------+------+
680
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
681
}
682
}
683
684
-/* C6.3.150 INS (Element)
685
+/* INS (Element)
686
*
687
* 31 21 20 16 15 14 11 10 9 5 4 0
688
* +-----------------------+--------+------------+---+------+------+
689
@@ -XXX,XX +XXX,XX @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
690
}
691
692
693
-/* C6.3.151 INS (General)
694
+/* INS (General)
695
*
696
* 31 21 20 16 15 10 9 5 4 0
697
* +-----------------------+--------+-------------+------+------+
698
@@ -XXX,XX +XXX,XX @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
699
}
700
701
/*
702
- * C6.3.321 UMOV (General)
703
- * C6.3.237 SMOV (General)
704
+ * UMOV (General)
705
+ * SMOV (General)
706
*
707
* 31 30 29 21 20 16 15 12 10 9 5 4 0
708
* +---+---+-------------------+--------+-------------+------+------+
709
@@ -XXX,XX +XXX,XX @@ static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
710
}
711
}
712
713
-/* C3.6.5 AdvSIMD copy
714
+/* AdvSIMD copy
715
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
716
* +---+---+----+-----------------+------+---+------+---+------+------+
717
* | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
718
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
719
}
720
}
721
722
-/* C3.6.6 AdvSIMD modified immediate
723
+/* AdvSIMD modified immediate
724
* 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
725
* +---+---+----+---------------------+-----+-------+----+---+-------+------+
726
* | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
727
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
728
tcg_temp_free_i64(tcg_imm);
729
}
730
731
-/* C3.6.7 AdvSIMD scalar copy
732
+/* AdvSIMD scalar copy
733
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
734
* +-----+----+-----------------+------+---+------+---+------+------+
735
* | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
736
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
737
handle_simd_dupes(s, rd, rn, imm5);
738
}
739
740
-/* C3.6.8 AdvSIMD scalar pairwise
741
+/* AdvSIMD scalar pairwise
742
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
743
* +-----+---+-----------+------+-----------+--------+-----+------+------+
744
* | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
745
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
746
tcg_temp_free_i32(tcg_rmode);
747
}
748
749
-/* C3.6.9 AdvSIMD scalar shift by immediate
750
+/* AdvSIMD scalar shift by immediate
751
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
752
* +-----+---+-------------+------+------+--------+---+------+------+
753
* | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
754
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
755
}
756
}
757
758
-/* C3.6.10 AdvSIMD scalar three different
759
+/* AdvSIMD scalar three different
760
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
761
* +-----+---+-----------+------+---+------+--------+-----+------+------+
762
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
763
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
764
}
765
}
766
767
-/* C3.6.11 AdvSIMD scalar three same
768
+/* AdvSIMD scalar three same
769
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
770
* +-----+---+-----------+------+---+------+--------+---+------+------+
771
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
772
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
773
}
774
}
775
776
-/* C3.6.12 AdvSIMD scalar two reg misc
777
+/* AdvSIMD scalar two reg misc
778
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
779
* +-----+---+-----------+------+-----------+--------+-----+------+------+
780
* | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
781
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
782
}
783
784
785
-/* C3.6.14 AdvSIMD shift by immediate
786
+/* AdvSIMD shift by immediate
787
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
788
* +---+---+---+-------------+------+------+--------+---+------+------+
789
* | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
790
@@ -XXX,XX +XXX,XX @@ static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
791
tcg_temp_free_i64(tcg_res);
792
}
793
794
-/* C3.6.15 AdvSIMD three different
795
+/* AdvSIMD three different
796
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
797
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
798
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
799
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
800
}
801
}
802
803
-/* C3.6.16 AdvSIMD three same
804
+/* AdvSIMD three same
805
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
806
* +---+---+---+-----------+------+---+------+--------+---+------+------+
807
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
808
@@ -XXX,XX +XXX,XX @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
809
}
810
}
811
812
-/* C3.6.17 AdvSIMD two reg misc
813
+/* AdvSIMD two reg misc
814
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
815
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
816
* | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
817
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
818
}
819
}
820
821
-/* C3.6.13 AdvSIMD scalar x indexed element
822
+/* AdvSIMD scalar x indexed element
823
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
824
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
825
* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
826
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
827
- * C3.6.18 AdvSIMD vector x indexed element
828
+ * AdvSIMD vector x indexed element
829
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
830
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
831
* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
832
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
833
}
834
}
835
836
-/* C3.6.19 Crypto AES
837
+/* Crypto AES
838
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
839
* +-----------------+------+-----------+--------+-----+------+------+
840
* | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
841
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
842
tcg_temp_free_i32(tcg_decrypt);
843
}
844
845
-/* C3.6.20 Crypto three-reg SHA
846
+/* Crypto three-reg SHA
847
* 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
848
* +-----------------+------+---+------+---+--------+-----+------+------+
849
* | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
850
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
851
tcg_temp_free_i32(tcg_rm_regno);
852
}
853
854
-/* C3.6.21 Crypto two-reg SHA
855
+/* Crypto two-reg SHA
856
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
857
* +-----------------+------+-----------+--------+-----+------+------+
858
* | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
859
--
87
--
860
2.7.4
88
2.25.1
861
89
862
90
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
[PULL 07/22] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters
1
Now that we have a banked FAULTMASK register and banked exceptions,
1
We allow a GICv3 to be connected to any CPU, but we don't do anything
2
we can implement the correct check in cpu_mmu_index() for whether
2
to handle the case where the CPU type doesn't in hardware have a
3
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
3
GICv3 CPU interface and so the various GIC configuration fields
4
handlers which have requested a negative execution priority to run
4
(gic_num_lrs, vprebits, vpribits) are not specified.
5
with the MPU disabled. In v8M the test has to check this for the
5
6
current security state and so takes account of banking.
6
The current behaviour is that we will add the EL1 CPU interface
7
registers, but will not put in the EL2 CPU interface registers, even
8
if the CPU has EL2, which will leave the GIC in a broken state and
9
probably result in the guest crashing as it tries to set it up. This
10
only affects the virt board when using the cortex-a15 or cortex-a7
11
CPU types (both 32-bit) with -machine gic-version=3 (or 'max')
12
and -machine virtualization=on.
13
14
Instead of failing to set up the EL2 registers, if the CPU doesn't
15
define the GIC configuration set it to a reasonable default, matching
16
the standard configuration for most Arm CPUs.
7
17
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
20
Message-id: 20220512151457.3899052-2-peter.maydell@linaro.org
11
---
21
---
12
target/arm/cpu.h | 21 ++++++++++++++++-----
22
hw/intc/arm_gicv3_cpuif.c | 18 +++++++++++++-----
13
hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++
23
1 file changed, 13 insertions(+), 5 deletions(-)
14
2 files changed, 45 insertions(+), 5 deletions(-)
15
24
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
17
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
27
--- a/hw/intc/arm_gicv3_cpuif.c
19
+++ b/target/arm/cpu.h
28
+++ b/hw/intc/arm_gicv3_cpuif.c
20
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq);
29
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
21
* (v8M ARM ARM I_PKLD.)
30
ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
22
*/
31
GICv3CPUState *cs = &s->cpu[i];
23
int armv7m_nvic_raw_execution_priority(void *opaque);
32
24
+/**
33
+ /*
25
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
34
+ * If the CPU doesn't define a GICv3 configuration, probably because
26
+ * priority is negative for the specified security state.
35
+ * in real hardware it doesn't have one, then we use default values
27
+ * @opaque: the NVIC
36
+ * matching the one used by most Arm CPUs. This applies to:
28
+ * @secure: the security state to test
37
+ * cpu->gic_num_lrs
29
+ * This corresponds to the pseudocode IsReqExecPriNeg().
38
+ * cpu->gic_vpribits
30
+ */
39
+ * cpu->gic_vprebits
31
+#ifndef CONFIG_USER_ONLY
40
+ */
32
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
33
+#else
34
+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
35
+{
36
+ return false;
37
+}
38
+#endif
39
40
/* Interface for defining coprocessor registers.
41
* Registers are defined in tables of arm_cp_reginfo structs
42
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
43
if (arm_feature(env, ARM_FEATURE_M)) {
44
ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
45
46
- /* Execution priority is negative if FAULTMASK is set or
47
- * we're in a HardFault or NMI handler.
48
- */
49
- if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
50
- || env->v7m.faultmask[env->v7m.secure]) {
51
+ if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
52
mmu_idx = ARMMMUIdx_MNegPri;
53
}
54
55
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/intc/armv7m_nvic.c
58
+++ b/hw/intc/armv7m_nvic.c
59
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
60
return MIN(running, s->exception_prio);
61
}
62
63
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
64
+{
65
+ /* Return true if the requested execution priority is negative
66
+ * for the specified security state, ie that security state
67
+ * has an active NMI or HardFault or has set its FAULTMASK.
68
+ * Note that this is not the same as whether the execution
69
+ * priority is actually negative (for instance AIRCR.PRIS may
70
+ * mean we don't allow FAULTMASK_NS to actually make the execution
71
+ * priority negative). Compare pseudocode IsReqExcPriNeg().
72
+ */
73
+ NVICState *s = opaque;
74
+
41
+
75
+ if (s->cpu->env.v7m.faultmask[secure]) {
42
/* Note that we can't just use the GICv3CPUState as an opaque pointer
76
+ return true;
43
* in define_arm_cp_regs_with_opaque(), because when we're called back
77
+ }
44
* it might be with code translated by CPU 0 but run by CPU 1, in
78
+
45
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
79
+ if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
46
* get back to the GICv3CPUState from the CPUARMState.
80
+ s->vectors[ARMV7M_EXCP_HARD].active) {
47
*/
81
+ return true;
48
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
82
+ }
49
- if (arm_feature(&cpu->env, ARM_FEATURE_EL2)
83
+
50
- && cpu->gic_num_lrs) {
84
+ if (s->vectors[ARMV7M_EXCP_NMI].active &&
51
+ if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
85
+ exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
52
int j;
86
+ return true;
53
87
+ }
54
- cs->num_list_regs = cpu->gic_num_lrs;
88
+
55
- cs->vpribits = cpu->gic_vpribits;
89
+ return false;
56
- cs->vprebits = cpu->gic_vprebits;
90
+}
57
+ cs->num_list_regs = cpu->gic_num_lrs ?: 4;
91
+
58
+ cs->vpribits = cpu->gic_vpribits ?: 5;
92
bool armv7m_nvic_can_take_pending_exception(void *opaque)
59
+ cs->vprebits = cpu->gic_vprebits ?: 5;
93
{
60
94
NVICState *s = opaque;
61
/* Check against architectural constraints: getting these
62
* wrong would be a bug in the CPU code defining these,
95
--
63
--
96
2.7.4
64
2.25.1
97
98
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/31] nvic: Make ICSR banked for v8M
[PULL 08/22] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
1
The ICSR NVIC register is banked for v8M. This doesn't
1
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
2
require any new state, but it does mean that some bits
2
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
3
are controlled by BFHNFNMINS and some bits must work
3
virtual priority bit setting, not the physical priority bit setting.
4
with the correct banked exception. There is also a new
4
(For QEMU currently we always implement 8 bits of physical priority,
5
in v8M PENDNMICLR bit.
5
so the PRIbits field was previously 7, since it is defined to be
6
"priority bits - 1".)
6
7
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 1505240046-11454-18-git-send-email-peter.maydell@linaro.org
10
Message-id: 20220512151457.3899052-3-peter.maydell@linaro.org
11
Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
10
---
12
---
11
hw/intc/armv7m_nvic.c | 45 ++++++++++++++++++++++++++++++++-------------
13
hw/intc/arm_gicv3_cpuif.c | 2 +-
12
1 file changed, 32 insertions(+), 13 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
13
15
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
16
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
18
--- a/hw/intc/arm_gicv3_cpuif.c
17
+++ b/hw/intc/armv7m_nvic.c
19
+++ b/hw/intc/arm_gicv3_cpuif.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
20
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
19
}
21
* should match the ones reported in ich_vtr_read().
20
case 0xd00: /* CPUID Base. */
22
*/
21
return cpu->midr;
23
value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
22
- case 0xd04: /* Interrupt Control State. */
24
- (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
23
+ case 0xd04: /* Interrupt Control State (ICSR) */
25
+ ((cs->vpribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT);
24
/* VECTACTIVE */
26
25
val = cpu->env.v7m.exception;
27
if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
26
/* VECTPENDING */
28
value |= ICC_CTLR_EL1_EOIMODE;
27
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
28
if (nvic_rettobase(s)) {
29
val |= (1 << 11);
30
}
31
- /* PENDSTSET */
32
- if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
33
- val |= (1 << 26);
34
- }
35
- /* PENDSVSET */
36
- if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
37
- val |= (1 << 28);
38
+ if (attrs.secure) {
39
+ /* PENDSTSET */
40
+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {
41
+ val |= (1 << 26);
42
+ }
43
+ /* PENDSVSET */
44
+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {
45
+ val |= (1 << 28);
46
+ }
47
+ } else {
48
+ /* PENDSTSET */
49
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
50
+ val |= (1 << 26);
51
+ }
52
+ /* PENDSVSET */
53
+ if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
54
+ val |= (1 << 28);
55
+ }
56
}
57
/* NMIPENDSET */
58
- if (s->vectors[ARMV7M_EXCP_NMI].pending) {
59
+ if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
60
+ s->vectors[ARMV7M_EXCP_NMI].pending) {
61
val |= (1 << 31);
62
}
63
- /* ISRPREEMPT not implemented */
64
+ /* ISRPREEMPT: RES0 when halting debug not implemented */
65
+ /* STTNS: RES0 for the Main Extension */
66
return val;
67
case 0xd08: /* Vector Table Offset. */
68
return cpu->env.v7m.vecbase[attrs.secure];
69
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
70
nvic_irq_update(s);
71
break;
72
}
73
- case 0xd04: /* Interrupt Control State. */
74
- if (value & (1 << 31)) {
75
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
76
+ case 0xd04: /* Interrupt Control State (ICSR) */
77
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
78
+ if (value & (1 << 31)) {
79
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
80
+ } else if (value & (1 << 30) &&
81
+ arm_feature(&cpu->env, ARM_FEATURE_V8)) {
82
+ /* PENDNMICLR didn't exist in v7M */
83
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false);
84
+ }
85
}
86
if (value & (1 << 28)) {
87
armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
88
--
29
--
89
2.7.4
30
2.25.1
90
91
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/31] hw/arm/palm.c: Don't use old_mmio for static_ops
[PULL 09/22] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant
1
Update the static_ops functions to use new-style mmio
1
The GIC_MIN_BPR constant defines the minimum BPR value that the TCG
2
rather than the legacy old_mmio functions.
2
emulated GICv3 supports. We're currently using this also as the
3
value we reset the KVM GICv3 ICC_BPR registers to, but this is only
4
right by accident.
5
6
We want to make the emulated GICv3 use a configurable number of
7
priority bits, which means that GIC_MIN_BPR will no longer be a
8
constant. Replace the uses in the KVM reset code with literal 0,
9
plus a constant explaining why this is reasonable.
3
10
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505580378-9044-2-git-send-email-peter.maydell@linaro.org
13
Message-id: 20220512151457.3899052-4-peter.maydell@linaro.org
14
Message-id: 20220506162129.2896966-3-peter.maydell@linaro.org
7
---
15
---
8
hw/arm/palm.c | 30 ++++++++++--------------------
16
hw/intc/arm_gicv3_kvm.c | 16 +++++++++++++---
9
1 file changed, 10 insertions(+), 20 deletions(-)
17
1 file changed, 13 insertions(+), 3 deletions(-)
10
18
11
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
19
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
12
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/palm.c
21
--- a/hw/intc/arm_gicv3_kvm.c
14
+++ b/hw/arm/palm.c
22
+++ b/hw/intc/arm_gicv3_kvm.c
15
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
16
#include "exec/address-spaces.h"
24
s = c->gic;
17
#include "cpu.h"
25
18
26
c->icc_pmr_el1 = 0;
19
-static uint32_t static_readb(void *opaque, hwaddr offset)
27
- c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
20
+static uint64_t static_read(void *opaque, hwaddr offset, unsigned size)
28
- c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
21
{
29
- c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
22
- uint32_t *val = (uint32_t *) opaque;
30
+ /*
23
- return *val >> ((offset & 3) << 3);
31
+ * Architecturally the reset value of the ICC_BPR registers
24
-}
32
+ * is UNKNOWN. We set them all to 0 here; when the kernel
25
+ uint32_t *val = (uint32_t *)opaque;
33
+ * uses these values to program the ICH_VMCR_EL2 fields that
26
+ uint32_t sizemask = 7 >> size;
34
+ * determine the guest-visible ICC_BPR register values, the
27
35
+ * hardware's "writing a value less than the minimum sets
28
-static uint32_t static_readh(void *opaque, hwaddr offset)
36
+ * the field to the minimum value" behaviour will result in
29
-{
37
+ * them effectively resetting to the correct minimum value
30
- uint32_t *val = (uint32_t *) opaque;
38
+ * for the host GIC.
31
- return *val >> ((offset & 1) << 3);
39
+ */
32
-}
40
+ c->icc_bpr[GICV3_G0] = 0;
33
-
41
+ c->icc_bpr[GICV3_G1] = 0;
34
-static uint32_t static_readw(void *opaque, hwaddr offset)
42
+ c->icc_bpr[GICV3_G1NS] = 0;
35
-{
43
36
- uint32_t *val = (uint32_t *) opaque;
44
c->icc_sre_el1 = 0x7;
37
- return *val >> ((offset & 0) << 3);
45
memset(c->icc_apr, 0, sizeof(c->icc_apr));
38
+ return *val >> ((offset & sizemask) << 3);
39
}
40
41
-static void static_write(void *opaque, hwaddr offset,
42
- uint32_t value)
43
+static void static_write(void *opaque, hwaddr offset, uint64_t value,
44
+ unsigned size)
45
{
46
#ifdef SPY
47
printf("%s: value %08lx written at " PA_FMT "\n",
48
@@ -XXX,XX +XXX,XX @@ static void static_write(void *opaque, hwaddr offset,
49
}
50
51
static const MemoryRegionOps static_ops = {
52
- .old_mmio = {
53
- .read = { static_readb, static_readh, static_readw, },
54
- .write = { static_write, static_write, static_write, },
55
- },
56
+ .read = static_read,
57
+ .write = static_write,
58
+ .valid.min_access_size = 1,
59
+ .valid.max_access_size = 4,
60
.endianness = DEVICE_NATIVE_ENDIAN,
61
};
62
63
--
46
--
64
2.7.4
47
2.25.1
65
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/31] hw/timer/omap_gptimer: Don't use old_mmio
[PULL 10/22] hw/intc/arm_gicv3: Support configurable number of physical priority bits
1
Don't use the old_mmio struct in memory region ops.
1
The GICv3 code has always supported a configurable number of virtual
2
priority and preemption bits, but our implementation currently
3
hardcodes the number of physical priority bits at 8. This is not
4
what most hardware implementations provide; for instance the
5
Cortex-A53 provides only 5 bits of physical priority.
6
7
Make the number of physical priority/preemption bits driven by fields
8
in the GICv3CPUState, the way that we already do for virtual
9
priority/preemption bits. We set cs->pribits to 8, so there is no
10
behavioural change in this commit. A following commit will add the
11
machinery for CPUs to set this to the correct value for their
12
implementation.
13
14
Note that changing the number of priority bits would be a migration
15
compatibility break, because the semantics of the icc_apr[][] array
16
changes.
2
17
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
20
Message-id: 20220512151457.3899052-5-peter.maydell@linaro.org
21
Message-id: 20220506162129.2896966-4-peter.maydell@linaro.org
6
---
22
---
7
hw/timer/omap_gptimer.c | 49 +++++++++++++++++++++++++++++++++++++------------
23
include/hw/intc/arm_gicv3_common.h | 7 +-
8
1 file changed, 37 insertions(+), 12 deletions(-)
24
hw/intc/arm_gicv3_cpuif.c | 182 ++++++++++++++++++++---------
25
2 files changed, 130 insertions(+), 59 deletions(-)
9
26
10
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
27
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
11
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/timer/omap_gptimer.c
29
--- a/include/hw/intc/arm_gicv3_common.h
13
+++ b/hw/timer/omap_gptimer.c
30
+++ b/include/hw/intc/arm_gicv3_common.h
14
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
31
@@ -XXX,XX +XXX,XX @@
15
s->writeh = (uint16_t) value;
32
/* Maximum number of list registers (architectural limit) */
33
#define GICV3_LR_MAX 16
34
35
-/* Minimum BPR for Secure, or when security not enabled */
36
-#define GIC_MIN_BPR 0
37
-/* Minimum BPR for Nonsecure when security is enabled */
38
-#define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
39
-
40
/* For some distributor fields we want to model the array of 32-bit
41
* register values which hold various bitmaps corresponding to enabled,
42
* pending, etc bits. These macros and functions facilitate that; the
43
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
44
int num_list_regs;
45
int vpribits; /* number of virtual priority bits */
46
int vprebits; /* number of virtual preemption bits */
47
+ int pribits; /* number of physical priority bits */
48
+ int prebits; /* number of physical preemption bits */
49
50
/* Current highest priority pending interrupt for this CPU.
51
* This is cached information that can be recalculated from the
52
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/intc/arm_gicv3_cpuif.c
55
+++ b/hw/intc/arm_gicv3_cpuif.c
56
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
57
return intid;
16
}
58
}
17
59
18
+static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,
60
+static uint32_t icc_fullprio_mask(GICv3CPUState *cs)
19
+ unsigned size)
20
+{
61
+{
21
+ switch (size) {
62
+ /*
22
+ case 1:
63
+ * Return a mask word which clears the unimplemented priority bits
23
+ return omap_badwidth_read32(opaque, addr);
64
+ * from a priority value for a physical interrupt. (Not to be confused
24
+ case 2:
65
+ * with the group priority, whose mask depends on the value of BPR
25
+ return omap_gp_timer_readh(opaque, addr);
66
+ * for the interrupt group.)
26
+ case 4:
67
+ */
27
+ return omap_gp_timer_readw(opaque, addr);
68
+ return ~0U << (8 - cs->pribits);
28
+ default:
29
+ g_assert_not_reached();
30
+ }
31
+}
69
+}
32
+
70
+
33
+static void omap_gp_timer_writefn(void *opaque, hwaddr addr,
71
+static inline int icc_min_bpr(GICv3CPUState *cs)
34
+ uint64_t value, unsigned size)
35
+{
72
+{
36
+ switch (size) {
73
+ /* The minimum BPR for the physical interface. */
37
+ case 1:
74
+ return 7 - cs->prebits;
38
+ omap_badwidth_write32(opaque, addr, value);
39
+ break;
40
+ case 2:
41
+ omap_gp_timer_writeh(opaque, addr, value);
42
+ break;
43
+ case 4:
44
+ omap_gp_timer_write(opaque, addr, value);
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
+}
75
+}
50
+
76
+
51
static const MemoryRegionOps omap_gp_timer_ops = {
77
+static inline int icc_min_bpr_ns(GICv3CPUState *cs)
52
- .old_mmio = {
78
+{
53
- .read = {
79
+ return icc_min_bpr(cs) + 1;
54
- omap_badwidth_read32,
80
+}
55
- omap_gp_timer_readh,
81
+
56
- omap_gp_timer_readw,
82
+static inline int icc_num_aprs(GICv3CPUState *cs)
57
- },
83
+{
58
- .write = {
84
+ /* Return the number of APR registers (1, 2, or 4) */
59
- omap_badwidth_write32,
85
+ int aprmax = 1 << MAX(cs->prebits - 5, 0);
60
- omap_gp_timer_writeh,
86
+ assert(aprmax <= ARRAY_SIZE(cs->icc_apr[0]));
61
- omap_gp_timer_write,
87
+ return aprmax;
62
- },
88
+}
63
- },
89
+
64
+ .read = omap_gp_timer_readfn,
90
static int icc_highest_active_prio(GICv3CPUState *cs)
65
+ .write = omap_gp_timer_writefn,
91
{
66
+ .valid.min_access_size = 1,
92
/* Calculate the current running priority based on the set bits
67
+ .valid.max_access_size = 4,
93
@@ -XXX,XX +XXX,XX @@ static int icc_highest_active_prio(GICv3CPUState *cs)
68
.endianness = DEVICE_NATIVE_ENDIAN,
94
*/
95
int i;
96
97
- for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) {
98
+ for (i = 0; i < icc_num_aprs(cs); i++) {
99
uint32_t apr = cs->icc_apr[GICV3_G0][i] |
100
cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i];
101
102
if (!apr) {
103
continue;
104
}
105
- return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1);
106
+ return (i * 32 + ctz32(apr)) << (icc_min_bpr(cs) + 1);
107
}
108
/* No current active interrupts: return idle priority */
109
return 0xff;
110
@@ -XXX,XX +XXX,XX @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
111
112
trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value);
113
114
- value &= 0xff;
115
+ value &= icc_fullprio_mask(cs);
116
117
if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
118
(env->cp15.scr_el3 & SCR_FIQ)) {
119
@@ -XXX,XX +XXX,XX @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
120
*/
121
uint32_t mask = icc_gprio_mask(cs, cs->hppi.grp);
122
int prio = cs->hppi.prio & mask;
123
- int aprbit = prio >> 1;
124
+ int aprbit = prio >> (8 - cs->prebits);
125
int regno = aprbit / 32;
126
int regbit = aprbit % 32;
127
128
@@ -XXX,XX +XXX,XX @@ static void icc_drop_prio(GICv3CPUState *cs, int grp)
129
*/
130
int i;
131
132
- for (i = 0; i < ARRAY_SIZE(cs->icc_apr[grp]); i++) {
133
+ for (i = 0; i < icc_num_aprs(cs); i++) {
134
uint64_t *papr = &cs->icc_apr[grp][i];
135
136
if (!*papr) {
137
@@ -XXX,XX +XXX,XX @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
138
return;
139
}
140
141
- minval = (grp == GICV3_G1NS) ? GIC_MIN_BPR_NS : GIC_MIN_BPR;
142
+ minval = (grp == GICV3_G1NS) ? icc_min_bpr_ns(cs) : icc_min_bpr(cs);
143
if (value < minval) {
144
value = minval;
145
}
146
@@ -XXX,XX +XXX,XX @@ static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
147
148
cs->icc_ctlr_el1[GICV3_S] = ICC_CTLR_EL1_A3V |
149
(1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
150
- (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
151
+ ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT);
152
cs->icc_ctlr_el1[GICV3_NS] = ICC_CTLR_EL1_A3V |
153
(1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
154
- (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
155
+ ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT);
156
cs->icc_pmr_el1 = 0;
157
- cs->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
158
- cs->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
159
- cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
160
+ cs->icc_bpr[GICV3_G0] = icc_min_bpr(cs);
161
+ cs->icc_bpr[GICV3_G1] = icc_min_bpr(cs);
162
+ cs->icc_bpr[GICV3_G1NS] = icc_min_bpr_ns(cs);
163
memset(cs->icc_apr, 0, sizeof(cs->icc_apr));
164
memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen));
165
cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V |
166
(1 << ICC_CTLR_EL3_IDBITS_SHIFT) |
167
- (7 << ICC_CTLR_EL3_PRIBITS_SHIFT);
168
+ ((cs->pribits - 1) << ICC_CTLR_EL3_PRIBITS_SHIFT);
169
170
memset(cs->ich_apr, 0, sizeof(cs->ich_apr));
171
cs->ich_hcr_el2 = 0;
172
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
173
.readfn = icc_ap_read,
174
.writefn = icc_ap_write,
175
},
176
- { .name = "ICC_AP0R1_EL1", .state = ARM_CP_STATE_BOTH,
177
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 5,
178
- .type = ARM_CP_IO | ARM_CP_NO_RAW,
179
- .access = PL1_RW, .accessfn = gicv3_fiq_access,
180
- .readfn = icc_ap_read,
181
- .writefn = icc_ap_write,
182
- },
183
- { .name = "ICC_AP0R2_EL1", .state = ARM_CP_STATE_BOTH,
184
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 6,
185
- .type = ARM_CP_IO | ARM_CP_NO_RAW,
186
- .access = PL1_RW, .accessfn = gicv3_fiq_access,
187
- .readfn = icc_ap_read,
188
- .writefn = icc_ap_write,
189
- },
190
- { .name = "ICC_AP0R3_EL1", .state = ARM_CP_STATE_BOTH,
191
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 7,
192
- .type = ARM_CP_IO | ARM_CP_NO_RAW,
193
- .access = PL1_RW, .accessfn = gicv3_fiq_access,
194
- .readfn = icc_ap_read,
195
- .writefn = icc_ap_write,
196
- },
197
/* All the ICC_AP1R*_EL1 registers are banked */
198
{ .name = "ICC_AP1R0_EL1", .state = ARM_CP_STATE_BOTH,
199
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0,
200
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
201
.readfn = icc_ap_read,
202
.writefn = icc_ap_write,
203
},
204
- { .name = "ICC_AP1R1_EL1", .state = ARM_CP_STATE_BOTH,
205
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1,
206
- .type = ARM_CP_IO | ARM_CP_NO_RAW,
207
- .access = PL1_RW, .accessfn = gicv3_irq_access,
208
- .readfn = icc_ap_read,
209
- .writefn = icc_ap_write,
210
- },
211
- { .name = "ICC_AP1R2_EL1", .state = ARM_CP_STATE_BOTH,
212
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 2,
213
- .type = ARM_CP_IO | ARM_CP_NO_RAW,
214
- .access = PL1_RW, .accessfn = gicv3_irq_access,
215
- .readfn = icc_ap_read,
216
- .writefn = icc_ap_write,
217
- },
218
- { .name = "ICC_AP1R3_EL1", .state = ARM_CP_STATE_BOTH,
219
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 3,
220
- .type = ARM_CP_IO | ARM_CP_NO_RAW,
221
- .access = PL1_RW, .accessfn = gicv3_irq_access,
222
- .readfn = icc_ap_read,
223
- .writefn = icc_ap_write,
224
- },
225
{ .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
226
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1,
227
.type = ARM_CP_IO | ARM_CP_NO_RAW,
228
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
229
},
69
};
230
};
70
231
232
+static const ARMCPRegInfo gicv3_cpuif_icc_apxr1_reginfo[] = {
233
+ { .name = "ICC_AP0R1_EL1", .state = ARM_CP_STATE_BOTH,
234
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 5,
235
+ .type = ARM_CP_IO | ARM_CP_NO_RAW,
236
+ .access = PL1_RW, .accessfn = gicv3_fiq_access,
237
+ .readfn = icc_ap_read,
238
+ .writefn = icc_ap_write,
239
+ },
240
+ { .name = "ICC_AP1R1_EL1", .state = ARM_CP_STATE_BOTH,
241
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1,
242
+ .type = ARM_CP_IO | ARM_CP_NO_RAW,
243
+ .access = PL1_RW, .accessfn = gicv3_irq_access,
244
+ .readfn = icc_ap_read,
245
+ .writefn = icc_ap_write,
246
+ },
247
+};
248
+
249
+static const ARMCPRegInfo gicv3_cpuif_icc_apxr23_reginfo[] = {
250
+ { .name = "ICC_AP0R2_EL1", .state = ARM_CP_STATE_BOTH,
251
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 6,
252
+ .type = ARM_CP_IO | ARM_CP_NO_RAW,
253
+ .access = PL1_RW, .accessfn = gicv3_fiq_access,
254
+ .readfn = icc_ap_read,
255
+ .writefn = icc_ap_write,
256
+ },
257
+ { .name = "ICC_AP0R3_EL1", .state = ARM_CP_STATE_BOTH,
258
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 7,
259
+ .type = ARM_CP_IO | ARM_CP_NO_RAW,
260
+ .access = PL1_RW, .accessfn = gicv3_fiq_access,
261
+ .readfn = icc_ap_read,
262
+ .writefn = icc_ap_write,
263
+ },
264
+ { .name = "ICC_AP1R2_EL1", .state = ARM_CP_STATE_BOTH,
265
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 2,
266
+ .type = ARM_CP_IO | ARM_CP_NO_RAW,
267
+ .access = PL1_RW, .accessfn = gicv3_irq_access,
268
+ .readfn = icc_ap_read,
269
+ .writefn = icc_ap_write,
270
+ },
271
+ { .name = "ICC_AP1R3_EL1", .state = ARM_CP_STATE_BOTH,
272
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 3,
273
+ .type = ARM_CP_IO | ARM_CP_NO_RAW,
274
+ .access = PL1_RW, .accessfn = gicv3_irq_access,
275
+ .readfn = icc_ap_read,
276
+ .writefn = icc_ap_write,
277
+ },
278
+};
279
+
280
static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
281
{
282
GICv3CPUState *cs = icc_cs_from_env(env);
283
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
284
* get back to the GICv3CPUState from the CPUARMState.
285
*/
286
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
287
+
288
+ /*
289
+ * For the moment, retain the existing behaviour of 8 priority bits;
290
+ * in a following commit we will take this from the CPU state,
291
+ * as we do for the virtual priority bits.
292
+ */
293
+ cs->pribits = 8;
294
+ /*
295
+ * The GICv3 has separate ID register fields for virtual priority
296
+ * and preemption bit values, but only a single ID register field
297
+ * for the physical priority bits. The preemption bit count is
298
+ * always the same as the priority bit count, except that 8 bits
299
+ * of priority means 7 preemption bits. We precalculate the
300
+ * preemption bits because it simplifies the code and makes the
301
+ * parallels between the virtual and physical bits of the GIC
302
+ * a bit clearer.
303
+ */
304
+ cs->prebits = cs->pribits;
305
+ if (cs->prebits == 8) {
306
+ cs->prebits--;
307
+ }
308
+ /*
309
+ * Check that CPU code defining pribits didn't violate
310
+ * architectural constraints our implementation relies on.
311
+ */
312
+ g_assert(cs->pribits >= 4 && cs->pribits <= 8);
313
+
314
+ /*
315
+ * gicv3_cpuif_reginfo[] defines ICC_AP*R0_EL1; add definitions
316
+ * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them.
317
+ */
318
+ if (cs->prebits >= 6) {
319
+ define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr1_reginfo);
320
+ }
321
+ if (cs->prebits == 7) {
322
+ define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr23_reginfo);
323
+ }
324
+
325
if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
326
int j;
327
71
--
328
--
72
2.7.4
329
2.25.1
73
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/31] nvic: Implement AIRCR changes for v8M
[PULL 11/22] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
1
The Application Interrupt and Reset Control Register has some changes
1
Make the GICv3 set its number of bits of physical priority from the
2
for v8M:
2
implementation-specific value provided in the CPU state struct, in
3
* new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
3
the same way we already do for virtual priority bits. Because this
4
real state if the security extension is implemented and otherwise
4
would be a migration compatibility break, we provide a property
5
are constant
5
force-8-bit-prio which is enabled for 7.0 and earlier versioned board
6
* the PRIGROUP field is banked between security states
6
models to retain the legacy "always use 8 bits" behaviour.
7
* non-secure code can be blocked from using the SYSRESET bit
8
to reset the system if SYSRESETREQS is set
9
10
Implement the new state and the changes to register read and write.
11
For the moment we ignore the effects of the secure PRIGROUP.
12
We will implement the effects of PRIS and BFHFNMIS later.
13
7
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
10
Message-id: 20220512151457.3899052-6-peter.maydell@linaro.org
11
Message-id: 20220506162129.2896966-5-peter.maydell@linaro.org
17
---
12
---
18
include/hw/intc/armv7m_nvic.h | 3 ++-
13
include/hw/intc/arm_gicv3_common.h | 1 +
19
target/arm/cpu.h | 12 +++++++++++
14
target/arm/cpu.h | 1 +
20
hw/intc/armv7m_nvic.c | 49 +++++++++++++++++++++++++++++++++----------
15
hw/core/machine.c | 4 +++-
21
target/arm/cpu.c | 7 +++++++
16
hw/intc/arm_gicv3_common.c | 5 +++++
22
4 files changed, 59 insertions(+), 12 deletions(-)
17
hw/intc/arm_gicv3_cpuif.c | 15 +++++++++++----
18
target/arm/cpu64.c | 6 ++++++
19
6 files changed, 27 insertions(+), 5 deletions(-)
23
20
24
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
21
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
25
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/intc/armv7m_nvic.h
23
--- a/include/hw/intc/arm_gicv3_common.h
27
+++ b/include/hw/intc/armv7m_nvic.h
24
+++ b/include/hw/intc/arm_gicv3_common.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
25
@@ -XXX,XX +XXX,XX @@ struct GICv3State {
29
* Entries in sec_vectors[] for non-banked exception numbers are unused.
26
uint32_t revision;
30
*/
27
bool lpi_enable;
31
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
28
bool security_extn;
32
- uint32_t prigroup;
29
+ bool force_8bit_prio;
33
+ /* The PRIGROUP field in AIRCR is banked */
30
bool irq_reset_nonsecure;
34
+ uint32_t prigroup[M_REG_NUM_BANKS];
31
bool gicd_no_migration_shift_bug;
35
32
36
/* The following fields are all cached state that can be recalculated
37
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
38
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
39
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu.h
35
--- a/target/arm/cpu.h
41
+++ b/target/arm/cpu.h
36
+++ b/target/arm/cpu.h
42
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
37
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
43
int exception;
38
int gic_num_lrs; /* number of list registers */
44
uint32_t primask[M_REG_NUM_BANKS];
39
int gic_vpribits; /* number of virtual priority bits */
45
uint32_t faultmask[M_REG_NUM_BANKS];
40
int gic_vprebits; /* number of virtual preemption bits */
46
+ uint32_t aircr; /* only holds r/w state if security extn implemented */
41
+ int gic_pribits; /* number of physical priority bits */
47
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
42
48
} v7m;
43
/* Whether the cfgend input is high (i.e. this CPU should reset into
49
44
* big-endian mode). This setting isn't used directly: instead it modifies
50
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1)
45
diff --git a/hw/core/machine.c b/hw/core/machine.c
51
FIELD(V7M_CCR, DC, 16, 1)
46
index XXXXXXX..XXXXXXX 100644
52
FIELD(V7M_CCR, IC, 17, 1)
47
--- a/hw/core/machine.c
53
48
+++ b/hw/core/machine.c
54
+/* V7M AIRCR bits */
49
@@ -XXX,XX +XXX,XX @@
55
+FIELD(V7M_AIRCR, VECTRESET, 0, 1)
50
#include "hw/virtio/virtio-pci.h"
56
+FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
51
#include "qom/object_interfaces.h"
57
+FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
52
58
+FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
53
-GlobalProperty hw_compat_7_0[] = {};
59
+FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
54
+GlobalProperty hw_compat_7_0[] = {
60
+FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
55
+ { "arm-gicv3-common", "force-8-bit-prio", "on" },
61
+FIELD(V7M_AIRCR, PRIS, 14, 1)
56
+};
62
+FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
57
const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0);
63
+FIELD(V7M_AIRCR, VECTKEY, 16, 16)
58
59
GlobalProperty hw_compat_6_2[] = {
60
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/intc/arm_gicv3_common.c
63
+++ b/hw/intc/arm_gicv3_common.c
64
@@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = {
65
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
66
DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
67
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
68
+ /*
69
+ * Compatibility property: force 8 bits of physical priority, even
70
+ * if the CPU being emulated should have fewer.
71
+ */
72
+ DEFINE_PROP_BOOL("force-8-bit-prio", GICv3State, force_8bit_prio, 0),
73
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
74
redist_region_count, qdev_prop_uint32, uint32_t),
75
DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
76
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/hw/intc/arm_gicv3_cpuif.c
79
+++ b/hw/intc/arm_gicv3_cpuif.c
80
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
81
* cpu->gic_num_lrs
82
* cpu->gic_vpribits
83
* cpu->gic_vprebits
84
+ * cpu->gic_pribits
85
*/
86
87
/* Note that we can't just use the GICv3CPUState as an opaque pointer
88
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
89
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
90
91
/*
92
- * For the moment, retain the existing behaviour of 8 priority bits;
93
- * in a following commit we will take this from the CPU state,
94
- * as we do for the virtual priority bits.
95
+ * The CPU implementation specifies the number of supported
96
+ * bits of physical priority. For backwards compatibility
97
+ * of migration, we have a compat property that forces use
98
+ * of 8 priority bits regardless of what the CPU really has.
99
*/
100
- cs->pribits = 8;
101
+ if (s->force_8bit_prio) {
102
+ cs->pribits = 8;
103
+ } else {
104
+ cs->pribits = cpu->gic_pribits ?: 5;
105
+ }
64
+
106
+
65
/* V7M CFSR bits for MMFSR */
107
/*
66
FIELD(V7M_CFSR, IACCVIOL, 0, 1)
108
* The GICv3 has separate ID register fields for virtual priority
67
FIELD(V7M_CFSR, DACCVIOL, 1, 1)
109
* and preemption bit values, but only a single ID register field
68
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
110
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
69
index XXXXXXX..XXXXXXX 100644
111
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/intc/armv7m_nvic.c
112
--- a/target/arm/cpu64.c
71
+++ b/hw/intc/armv7m_nvic.c
113
+++ b/target/arm/cpu64.c
72
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
114
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
73
*/
115
cpu->gic_num_lrs = 4;
74
static inline uint32_t nvic_gprio_mask(NVICState *s)
116
cpu->gic_vpribits = 5;
75
{
117
cpu->gic_vprebits = 5;
76
- return ~0U << (s->prigroup + 1);
118
+ cpu->gic_pribits = 5;
77
+ return ~0U << (s->prigroup[M_REG_NS] + 1);
119
define_cortex_a72_a57_a53_cp_reginfo(cpu);
78
}
120
}
79
121
80
/* Recompute vectpending and exception_prio */
122
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
81
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
123
cpu->gic_num_lrs = 4;
82
return val;
124
cpu->gic_vpribits = 5;
83
case 0xd08: /* Vector Table Offset. */
125
cpu->gic_vprebits = 5;
84
return cpu->env.v7m.vecbase[attrs.secure];
126
+ cpu->gic_pribits = 5;
85
- case 0xd0c: /* Application Interrupt/Reset Control. */
127
define_cortex_a72_a57_a53_cp_reginfo(cpu);
86
- return 0xfa050000 | (s->prigroup << 8);
128
}
87
+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
129
88
+ val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);
130
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
89
+ if (attrs.secure) {
131
cpu->gic_num_lrs = 4;
90
+ /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
132
cpu->gic_vpribits = 5;
91
+ val |= cpu->env.v7m.aircr;
133
cpu->gic_vprebits = 5;
92
+ } else {
134
+ cpu->gic_pribits = 5;
93
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
135
define_cortex_a72_a57_a53_cp_reginfo(cpu);
94
+ /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
136
}
95
+ * security isn't supported then BFHFNMINS is RAO (and
137
96
+ * the bit in env.v7m.aircr is always set).
138
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
97
+ */
139
cpu->gic_num_lrs = 4;
98
+ val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
140
cpu->gic_vpribits = 5;
99
+ }
141
cpu->gic_vprebits = 5;
100
+ }
142
+ cpu->gic_pribits = 5;
101
+ return val;
143
102
case 0xd10: /* System Control. */
144
/* From B5.1 AdvSIMD AArch64 register summary */
103
/* TODO: Implement SLEEPONEXIT. */
145
cpu->isar.mvfr0 = 0x10110222;
104
return 0;
146
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
105
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
147
cpu->gic_num_lrs = 4;
106
case 0xd08: /* Vector Table Offset. */
148
cpu->gic_vpribits = 5;
107
cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
149
cpu->gic_vprebits = 5;
108
break;
150
+ cpu->gic_pribits = 5;
109
- case 0xd0c: /* Application Interrupt/Reset Control. */
151
110
- if ((value >> 16) == 0x05fa) {
152
/* From B5.1 AdvSIMD AArch64 register summary */
111
- if (value & 4) {
153
cpu->isar.mvfr0 = 0x10110222;
112
- qemu_irq_pulse(s->sysresetreq);
154
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
113
+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
155
cpu->gic_num_lrs = 4;
114
+ if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
156
cpu->gic_vpribits = 5;
115
+ if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
157
cpu->gic_vprebits = 5;
116
+ if (attrs.secure ||
158
+ cpu->gic_pribits = 5;
117
+ !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
159
118
+ qemu_irq_pulse(s->sysresetreq);
160
/* Suppport of A64FX's vector length are 128,256 and 512bit only */
119
+ }
161
aarch64_add_sve_properties(obj);
120
}
121
- if (value & 2) {
122
+ if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
123
qemu_log_mask(LOG_GUEST_ERROR,
124
"Setting VECTCLRACTIVE when not in DEBUG mode "
125
"is UNPREDICTABLE\n");
126
}
127
- if (value & 1) {
128
+ if (value & R_V7M_AIRCR_VECTRESET_MASK) {
129
+ /* NB: this bit is RES0 in v8M */
130
qemu_log_mask(LOG_GUEST_ERROR,
131
"Setting VECTRESET when not in DEBUG mode "
132
"is UNPREDICTABLE\n");
133
}
134
- s->prigroup = extract32(value, 8, 3);
135
+ s->prigroup[attrs.secure] = extract32(value,
136
+ R_V7M_AIRCR_PRIGROUP_SHIFT,
137
+ R_V7M_AIRCR_PRIGROUP_LENGTH);
138
+ if (attrs.secure) {
139
+ /* These bits are only writable by secure */
140
+ cpu->env.v7m.aircr = value &
141
+ (R_V7M_AIRCR_SYSRESETREQS_MASK |
142
+ R_V7M_AIRCR_BFHFNMINS_MASK |
143
+ R_V7M_AIRCR_PRIS_MASK);
144
+ }
145
nvic_irq_update(s);
146
}
147
break;
148
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
149
.fields = (VMStateField[]) {
150
VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
151
vmstate_VecInfo, VecInfo),
152
+ VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
153
VMSTATE_END_OF_LIST()
154
}
155
};
156
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
157
.fields = (VMStateField[]) {
158
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
159
vmstate_VecInfo, VecInfo),
160
- VMSTATE_UINT32(prigroup, NVICState),
161
+ VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),
162
VMSTATE_END_OF_LIST()
163
},
164
.subsections = (const VMStateDescription*[]) {
165
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
166
index XXXXXXX..XXXXXXX 100644
167
--- a/target/arm/cpu.c
168
+++ b/target/arm/cpu.c
169
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
170
171
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
172
env->v7m.secure = true;
173
+ } else {
174
+ /* This bit resets to 0 if security is supported, but 1 if
175
+ * it is not. The bit is not present in v7M, but we set it
176
+ * here so we can avoid having to make checks on it conditional
177
+ * on ARM_FEATURE_V8 (we don't let the guest see the bit).
178
+ */
179
+ env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
180
}
181
182
/* In v7M the reset value of this bit is IMPDEF, but ARM recommends
183
--
162
--
184
2.7.4
163
2.25.1
185
186
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/31] hw/timer/omap_synctimer.c: Don't use old_mmio
[PULL 12/22] hw/intc/arm_gicv3: Provide ich_num_aprs()
1
Don't use the old_mmio in the memory region ops struct.
1
We previously open-coded the expression for the number of virtual APR
2
registers and the assertion that it was not going to cause us to
3
overflow the cs->ich_apr[] array. Factor this out into a new
4
ich_num_aprs() function, for consistency with the icc_num_aprs()
5
function we just added for the physical APR handling.
2
6
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-4-git-send-email-peter.maydell@linaro.org
9
Message-id: 20220512151457.3899052-7-peter.maydell@linaro.org
10
Message-id: 20220506162129.2896966-6-peter.maydell@linaro.org
6
---
11
---
7
hw/timer/omap_synctimer.c | 35 +++++++++++++++++++++--------------
12
hw/intc/arm_gicv3_cpuif.c | 16 ++++++++++------
8
1 file changed, 21 insertions(+), 14 deletions(-)
13
1 file changed, 10 insertions(+), 6 deletions(-)
9
14
10
diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
11
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/timer/omap_synctimer.c
17
--- a/hw/intc/arm_gicv3_cpuif.c
13
+++ b/hw/timer/omap_synctimer.c
18
+++ b/hw/intc/arm_gicv3_cpuif.c
14
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
19
@@ -XXX,XX +XXX,XX @@ static inline int icv_min_vbpr(GICv3CPUState *cs)
15
}
20
return 7 - cs->vprebits;
16
}
21
}
17
22
18
-static void omap_synctimer_write(void *opaque, hwaddr addr,
23
+static inline int ich_num_aprs(GICv3CPUState *cs)
19
- uint32_t value)
20
+static uint64_t omap_synctimer_readfn(void *opaque, hwaddr addr,
21
+ unsigned size)
22
+{
24
+{
23
+ switch (size) {
25
+ /* Return the number of virtual APR registers (1, 2, or 4) */
24
+ case 1:
26
+ int aprmax = 1 << (cs->vprebits - 5);
25
+ return omap_badwidth_read32(opaque, addr);
27
+ assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
26
+ case 2:
28
+ return aprmax;
27
+ return omap_synctimer_readh(opaque, addr);
28
+ case 4:
29
+ return omap_synctimer_readw(opaque, addr);
30
+ default:
31
+ g_assert_not_reached();
32
+ }
33
+}
29
+}
34
+
30
+
35
+static void omap_synctimer_writefn(void *opaque, hwaddr addr,
31
/* Simple accessor functions for LR fields */
36
+ uint64_t value, unsigned size)
32
static uint32_t ich_lr_vintid(uint64_t lr)
37
{
33
{
38
OMAP_BAD_REG(addr);
34
@@ -XXX,XX +XXX,XX @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs)
39
}
35
* in the ICH Active Priority Registers.
40
36
*/
41
static const MemoryRegionOps omap_synctimer_ops = {
37
int i;
42
- .old_mmio = {
38
- int aprmax = 1 << (cs->vprebits - 5);
43
- .read = {
39
-
44
- omap_badwidth_read32,
40
- assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
45
- omap_synctimer_readh,
41
+ int aprmax = ich_num_aprs(cs);
46
- omap_synctimer_readw,
42
47
- },
43
for (i = 0; i < aprmax; i++) {
48
- .write = {
44
uint32_t apr = cs->ich_apr[GICV3_G0][i] |
49
- omap_badwidth_write32,
45
@@ -XXX,XX +XXX,XX @@ static int icv_drop_prio(GICv3CPUState *cs)
50
- omap_synctimer_write,
46
* 32 bits are actually relevant.
51
- omap_synctimer_write,
47
*/
52
- },
48
int i;
53
- },
49
- int aprmax = 1 << (cs->vprebits - 5);
54
+ .read = omap_synctimer_readfn,
50
-
55
+ .write = omap_synctimer_writefn,
51
- assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
56
+ .valid.min_access_size = 1,
52
+ int aprmax = ich_num_aprs(cs);
57
+ .valid.max_access_size = 4,
53
58
.endianness = DEVICE_NATIVE_ENDIAN,
54
for (i = 0; i < aprmax; i++) {
59
};
55
uint64_t *papr0 = &cs->ich_apr[GICV3_G0][i];
60
61
--
56
--
62
2.7.4
57
2.25.1
63
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/31] target/arm: Implement MSR/MRS access to NS banked registers
[PULL 13/22] Fix aarch64 debug register names.
1
In v8M the MSR and MRS instructions have extra register value
1
From: Chris Howard <cvz185@web.de>
2
encodings to allow secure code to access the non-secure banked
3
version of various special registers.
4
2
5
(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because
3
Give all the debug registers their correct names including the
6
we don't currently implement the stack limit registers at all.)
4
index, rather than having multiple registers all with the
5
same name string, which is confusing when viewed over the
6
gdbstub interface.
7
7
8
Signed-off-by: CHRIS HOWARD <cvz185@web.de>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 4127D8CA-D54A-47C7-A039-0DB7361E30C0@web.de
11
[PMM: expanded commit message]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
11
---
13
---
12
target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++
14
target/arm/helper.c | 16 ++++++++++++----
13
1 file changed, 110 insertions(+)
15
1 file changed, 12 insertions(+), 4 deletions(-)
14
16
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
19
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
20
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
21
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
20
break;
21
case 20: /* CONTROL */
22
return env->v7m.control[env->v7m.secure];
23
+ case 0x94: /* CONTROL_NS */
24
+ /* We have to handle this here because unprivileged Secure code
25
+ * can read the NS CONTROL register.
26
+ */
27
+ if (!env->v7m.secure) {
28
+ return 0;
29
+ }
30
+ return env->v7m.control[M_REG_NS];
31
}
22
}
32
23
33
if (el == 0) {
24
for (i = 0; i < brps; i++) {
34
return 0; /* unprivileged reads others as zero */
25
+ char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i);
26
+ char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i);
27
ARMCPRegInfo dbgregs[] = {
28
- { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
29
+ { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
30
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
31
.access = PL1_RW, .accessfn = access_tda,
32
.fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
33
.writefn = dbgbvr_write, .raw_writefn = raw_write
34
},
35
- { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
36
+ { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
37
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
38
.access = PL1_RW, .accessfn = access_tda,
39
.fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
40
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
41
},
42
};
43
define_arm_cp_regs(cpu, dbgregs);
44
+ g_free(dbgbvr_el1_name);
45
+ g_free(dbgbcr_el1_name);
35
}
46
}
36
47
37
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
48
for (i = 0; i < wrps; i++) {
38
+ switch (reg) {
49
+ char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i);
39
+ case 0x88: /* MSP_NS */
50
+ char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i);
40
+ if (!env->v7m.secure) {
51
ARMCPRegInfo dbgregs[] = {
41
+ return 0;
52
- { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
42
+ }
53
+ { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
43
+ return env->v7m.other_ss_msp;
54
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
44
+ case 0x89: /* PSP_NS */
55
.access = PL1_RW, .accessfn = access_tda,
45
+ if (!env->v7m.secure) {
56
.fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
46
+ return 0;
57
.writefn = dbgwvr_write, .raw_writefn = raw_write
47
+ }
58
},
48
+ return env->v7m.other_ss_psp;
59
- { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
49
+ case 0x90: /* PRIMASK_NS */
60
+ { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
50
+ if (!env->v7m.secure) {
61
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
51
+ return 0;
62
.access = PL1_RW, .accessfn = access_tda,
52
+ }
63
.fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
53
+ return env->v7m.primask[M_REG_NS];
64
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
54
+ case 0x91: /* BASEPRI_NS */
65
},
55
+ if (!env->v7m.secure) {
66
};
56
+ return 0;
67
define_arm_cp_regs(cpu, dbgregs);
57
+ }
68
+ g_free(dbgwvr_el1_name);
58
+ return env->v7m.basepri[M_REG_NS];
69
+ g_free(dbgwcr_el1_name);
59
+ case 0x93: /* FAULTMASK_NS */
60
+ if (!env->v7m.secure) {
61
+ return 0;
62
+ }
63
+ return env->v7m.faultmask[M_REG_NS];
64
+ case 0x98: /* SP_NS */
65
+ {
66
+ /* This gives the non-secure SP selected based on whether we're
67
+ * currently in handler mode or not, using the NS CONTROL.SPSEL.
68
+ */
69
+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
70
+
71
+ if (!env->v7m.secure) {
72
+ return 0;
73
+ }
74
+ if (!arm_v7m_is_handler_mode(env) && spsel) {
75
+ return env->v7m.other_ss_psp;
76
+ } else {
77
+ return env->v7m.other_ss_msp;
78
+ }
79
+ }
80
+ default:
81
+ break;
82
+ }
83
+ }
84
+
85
switch (reg) {
86
case 8: /* MSP */
87
return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
88
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
89
return;
90
}
70
}
91
71
}
92
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
72
93
+ switch (reg) {
94
+ case 0x88: /* MSP_NS */
95
+ if (!env->v7m.secure) {
96
+ return;
97
+ }
98
+ env->v7m.other_ss_msp = val;
99
+ return;
100
+ case 0x89: /* PSP_NS */
101
+ if (!env->v7m.secure) {
102
+ return;
103
+ }
104
+ env->v7m.other_ss_psp = val;
105
+ return;
106
+ case 0x90: /* PRIMASK_NS */
107
+ if (!env->v7m.secure) {
108
+ return;
109
+ }
110
+ env->v7m.primask[M_REG_NS] = val & 1;
111
+ return;
112
+ case 0x91: /* BASEPRI_NS */
113
+ if (!env->v7m.secure) {
114
+ return;
115
+ }
116
+ env->v7m.basepri[M_REG_NS] = val & 0xff;
117
+ return;
118
+ case 0x93: /* FAULTMASK_NS */
119
+ if (!env->v7m.secure) {
120
+ return;
121
+ }
122
+ env->v7m.faultmask[M_REG_NS] = val & 1;
123
+ return;
124
+ case 0x98: /* SP_NS */
125
+ {
126
+ /* This gives the non-secure SP selected based on whether we're
127
+ * currently in handler mode or not, using the NS CONTROL.SPSEL.
128
+ */
129
+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
130
+
131
+ if (!env->v7m.secure) {
132
+ return;
133
+ }
134
+ if (!arm_v7m_is_handler_mode(env) && spsel) {
135
+ env->v7m.other_ss_psp = val;
136
+ } else {
137
+ env->v7m.other_ss_msp = val;
138
+ }
139
+ return;
140
+ }
141
+ default:
142
+ break;
143
+ }
144
+ }
145
+
146
switch (reg) {
147
case 0 ... 7: /* xPSR sub-fields */
148
/* only APSR is actually writable */
149
--
73
--
150
2.7.4
74
2.25.1
151
152
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/31] nvic: Add banked exception states
Deleted patch
1
For the v8M security extension, some exceptions must be banked
2
between security states. Add the new vecinfo array which holds
3
the state for the banked exceptions and migrate it if the
4
CPU the NVIC is attached to implements the security extension.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/hw/intc/armv7m_nvic.h | 14 ++++++++++++
10
hw/intc/armv7m_nvic.c | 53 ++++++++++++++++++++++++++++++++++++++++++-
11
2 files changed, 66 insertions(+), 1 deletion(-)
12
13
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/armv7m_nvic.h
16
+++ b/include/hw/intc/armv7m_nvic.h
17
@@ -XXX,XX +XXX,XX @@
18
19
/* Highest permitted number of exceptions (architectural limit) */
20
#define NVIC_MAX_VECTORS 512
21
+/* Number of internal exceptions */
22
+#define NVIC_INTERNAL_VECTORS 16
23
24
typedef struct VecInfo {
25
/* Exception priorities can range from -3 to 255; only the unmodifiable
26
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
27
ARMCPU *cpu;
28
29
VecInfo vectors[NVIC_MAX_VECTORS];
30
+ /* If the v8M security extension is implemented, some of the internal
31
+ * exceptions are banked between security states (ie there exists both
32
+ * a Secure and a NonSecure version of the exception and its state):
33
+ * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
34
+ * The rest (including all the external exceptions) are not banked, though
35
+ * they may be configurable to target either Secure or NonSecure state.
36
+ * We store the secure exception state in sec_vectors[] for the banked
37
+ * exceptions, and otherwise use only vectors[] (including for exceptions
38
+ * like SecureFault that unconditionally target Secure state).
39
+ * Entries in sec_vectors[] for non-banked exception numbers are unused.
40
+ */
41
+ VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
42
uint32_t prigroup;
43
44
/* vectpending and exception_prio are both cached state that can
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
49
@@ -XXX,XX +XXX,XX @@
50
* For historical reasons QEMU tends to use "interrupt" and
51
* "exception" more or less interchangeably.
52
*/
53
-#define NVIC_FIRST_IRQ 16
54
+#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
55
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
56
57
/* Effective running priority of the CPU when no exception is active
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
59
}
60
};
61
62
+static bool nvic_security_needed(void *opaque)
63
+{
64
+ NVICState *s = opaque;
65
+
66
+ return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
67
+}
68
+
69
+static int nvic_security_post_load(void *opaque, int version_id)
70
+{
71
+ NVICState *s = opaque;
72
+ int i;
73
+
74
+ /* Check for out of range priority settings */
75
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
76
+ return 1;
77
+ }
78
+ for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
79
+ if (s->sec_vectors[i].prio & ~0xff) {
80
+ return 1;
81
+ }
82
+ }
83
+ return 0;
84
+}
85
+
86
+static const VMStateDescription vmstate_nvic_security = {
87
+ .name = "nvic/m-security",
88
+ .version_id = 1,
89
+ .minimum_version_id = 1,
90
+ .needed = nvic_security_needed,
91
+ .post_load = &nvic_security_post_load,
92
+ .fields = (VMStateField[]) {
93
+ VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
94
+ vmstate_VecInfo, VecInfo),
95
+ VMSTATE_END_OF_LIST()
96
+ }
97
+};
98
+
99
static const VMStateDescription vmstate_nvic = {
100
.name = "armv7m_nvic",
101
.version_id = 4,
102
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
103
vmstate_VecInfo, VecInfo),
104
VMSTATE_UINT32(prigroup, NVICState),
105
VMSTATE_END_OF_LIST()
106
+ },
107
+ .subsections = (const VMStateDescription*[]) {
108
+ &vmstate_nvic_security,
109
+ NULL
110
}
111
};
112
113
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
114
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
115
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
116
117
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
118
+ s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;
119
+ s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;
120
+ s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
121
+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
122
+
123
+ /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
124
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
125
+ }
126
+
127
/* Strictly speaking the reset handler should be enabled.
128
* However, we don't simulate soft resets through the NVIC,
129
* and the reset vector should never be pended.
130
--
131
2.7.4
132
133
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/31] nvic: Add cached vectpending_is_s_banked state
Deleted patch
1
With banked exceptions, just the exception number in
2
s->vectpending is no longer sufficient to uniquely identify
3
the pending exception. Add a vectpending_is_s_banked bool
4
which is true if the exception is using the sec_vectors[]
5
array.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
9
---
10
include/hw/intc/armv7m_nvic.h | 11 +++++++++--
11
hw/intc/armv7m_nvic.c | 1 +
12
2 files changed, 10 insertions(+), 2 deletions(-)
13
14
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/intc/armv7m_nvic.h
17
+++ b/include/hw/intc/armv7m_nvic.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
19
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
20
uint32_t prigroup;
21
22
- /* vectpending and exception_prio are both cached state that can
23
- * be recalculated from the vectors[] array and the prigroup field.
24
+ /* The following fields are all cached state that can be recalculated
25
+ * from the vectors[] and sec_vectors[] arrays and the prigroup field:
26
+ * - vectpending
27
+ * - vectpending_is_secure
28
+ * - exception_prio
29
*/
30
unsigned int vectpending; /* highest prio pending enabled exception */
31
+ /* true if vectpending is a banked secure exception, ie it is in
32
+ * sec_vectors[] rather than vectors[]
33
+ */
34
+ bool vectpending_is_s_banked;
35
int exception_prio; /* group prio of the highest prio active exception */
36
37
MemoryRegion sysregmem;
38
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/intc/armv7m_nvic.c
41
+++ b/hw/intc/armv7m_nvic.c
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
43
44
s->exception_prio = NVIC_NOEXC_PRIO;
45
s->vectpending = 0;
46
+ s->vectpending_is_s_banked = false;
47
}
48
49
static void nvic_systick_trigger(void *opaque, int n, int level)
50
--
51
2.7.4
52
53
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/31] nvic: Add cached vectpending_prio state
[PULL 14/22] hw/adc/zynq-xadc: Use qemu_irq typedef
1
Instead of looking up the pending priority
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
in nvic_pending_prio(), cache it in a new state struct
3
field. The calculation of the pending priority given
4
the interrupt number is more complicated in v8M with
5
the security extension, so the caching will be worthwhile.
6
2
7
This changes nvic_pending_prio() from returning a full
3
Except hw/core/irq.c which implements the forward-declared opaque
8
(group + subpriority) priority value to returning a group
4
qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not
9
priority. This doesn't require changes to its callsites
5
using the typedef. Fix this single exception.
10
because we use it only in comparisons of the form
11
execution_prio > nvic_pending_prio()
12
and execution priority is always a group priority, so
13
a test (exec prio > full prio) is true if and only if
14
(execprio > group_prio).
15
6
16
(Architecturally the expected comparison is with the
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
group priority for this sort of "would we preempt" test;
8
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
18
we were only doing a test with a full priority as an
9
Message-id: 20220509202035.50335-1-philippe.mathieu.daude@gmail.com
19
optimisation to avoid the mask, which is possible
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
precisely because the two comparisons always give the
11
---
21
same answer.)
12
include/hw/adc/zynq-xadc.h | 3 +--
13
hw/adc/zynq-xadc.c | 4 ++--
14
2 files changed, 3 insertions(+), 4 deletions(-)
22
15
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
diff --git a/include/hw/adc/zynq-xadc.h b/include/hw/adc/zynq-xadc.h
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
26
---
27
include/hw/intc/armv7m_nvic.h | 2 ++
28
hw/intc/armv7m_nvic.c | 23 +++++++++++++----------
29
hw/intc/trace-events | 2 +-
30
3 files changed, 16 insertions(+), 11 deletions(-)
31
32
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
33
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/intc/armv7m_nvic.h
18
--- a/include/hw/adc/zynq-xadc.h
35
+++ b/include/hw/intc/armv7m_nvic.h
19
+++ b/include/hw/adc/zynq-xadc.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
20
@@ -XXX,XX +XXX,XX @@ struct ZynqXADCState {
37
* - vectpending
21
uint16_t xadc_dfifo[ZYNQ_XADC_FIFO_DEPTH];
38
* - vectpending_is_secure
22
uint16_t xadc_dfifo_entries;
39
* - exception_prio
23
40
+ * - vectpending_prio
24
- struct IRQState *qemu_irq;
41
*/
25
-
42
unsigned int vectpending; /* highest prio pending enabled exception */
26
+ qemu_irq irq;
43
/* true if vectpending is a banked secure exception, ie it is in
27
};
44
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
28
45
*/
29
#endif /* ZYNQ_XADC_H */
46
bool vectpending_is_s_banked;
30
diff --git a/hw/adc/zynq-xadc.c b/hw/adc/zynq-xadc.c
47
int exception_prio; /* group prio of the highest prio active exception */
48
+ int vectpending_prio; /* group prio of the exeception in vectpending */
49
50
MemoryRegion sysregmem;
51
MemoryRegion sysreg_ns_mem;
52
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
53
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/intc/armv7m_nvic.c
32
--- a/hw/adc/zynq-xadc.c
55
+++ b/hw/intc/armv7m_nvic.c
33
+++ b/hw/adc/zynq-xadc.c
56
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
34
@@ -XXX,XX +XXX,XX @@ static void zynq_xadc_update_ints(ZynqXADCState *s)
57
35
s->regs[INT_STS] |= INT_DFIFO_GTH;
58
static int nvic_pending_prio(NVICState *s)
36
}
59
{
37
60
- /* return the priority of the current pending interrupt,
38
- qemu_set_irq(s->qemu_irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK]));
61
+ /* return the group priority of the current pending interrupt,
39
+ qemu_set_irq(s->irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK]));
62
* or NVIC_NOEXC_PRIO if no interrupt is pending
63
*/
64
- return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
65
+ return s->vectpending_prio;
66
}
40
}
67
41
68
/* Return the value of the ISCR RETTOBASE bit:
42
static void zynq_xadc_reset(DeviceState *d)
69
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
43
@@ -XXX,XX +XXX,XX @@ static void zynq_xadc_init(Object *obj)
70
active_prio &= nvic_gprio_mask(s);
44
memory_region_init_io(&s->iomem, obj, &xadc_ops, s, "zynq-xadc",
71
}
45
ZYNQ_XADC_MMIO_SIZE);
72
46
sysbus_init_mmio(sbd, &s->iomem);
73
+ if (pend_prio > 0) {
47
- sysbus_init_irq(sbd, &s->qemu_irq);
74
+ pend_prio &= nvic_gprio_mask(s);
48
+ sysbus_init_irq(sbd, &s->irq);
75
+ }
76
+
77
s->vectpending = pend_irq;
78
+ s->vectpending_prio = pend_prio;
79
s->exception_prio = active_prio;
80
81
- trace_nvic_recompute_state(s->vectpending, s->exception_prio);
82
+ trace_nvic_recompute_state(s->vectpending,
83
+ s->vectpending_prio,
84
+ s->exception_prio);
85
}
49
}
86
50
87
/* Return the current execution priority of the CPU
51
static const VMStateDescription vmstate_zynq_xadc = {
88
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
89
CPUARMState *env = &s->cpu->env;
90
const int pending = s->vectpending;
91
const int running = nvic_exec_prio(s);
92
- int pendgroupprio;
93
VecInfo *vec;
94
95
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
96
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
97
assert(vec->enabled);
98
assert(vec->pending);
99
100
- pendgroupprio = vec->prio;
101
- if (pendgroupprio > 0) {
102
- pendgroupprio &= nvic_gprio_mask(s);
103
- }
104
- assert(pendgroupprio < running);
105
+ assert(s->vectpending_prio < running);
106
107
- trace_nvic_acknowledge_irq(pending, vec->prio);
108
+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
109
110
vec->active = 1;
111
vec->pending = 0;
112
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
113
s->exception_prio = NVIC_NOEXC_PRIO;
114
s->vectpending = 0;
115
s->vectpending_is_s_banked = false;
116
+ s->vectpending_prio = NVIC_NOEXC_PRIO;
117
}
118
119
static void nvic_systick_trigger(void *opaque, int n, int level)
120
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
121
index XXXXXXX..XXXXXXX 100644
122
--- a/hw/intc/trace-events
123
+++ b/hw/intc/trace-events
124
@@ -XXX,XX +XXX,XX @@ gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor 0x%x
125
gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending SGI %d"
126
127
# hw/intc/armv7m_nvic.c
128
-nvic_recompute_state(int vectpending, int exception_prio) "NVIC state recomputed: vectpending %d exception_prio %d"
129
+nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
130
nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
131
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
132
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
133
--
52
--
134
2.7.4
53
2.25.1
135
54
136
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked exceptions
Deleted patch
1
Update the code in nvic_rettobase() so that it checks the
2
sec_vectors[] array as well as the vectors[] array if needed.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505240046-11454-7-git-send-email-peter.maydell@linaro.org
7
---
8
hw/intc/armv7m_nvic.c | 5 ++++-
9
1 file changed, 4 insertions(+), 1 deletion(-)
10
11
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/armv7m_nvic.c
14
+++ b/hw/intc/armv7m_nvic.c
15
@@ -XXX,XX +XXX,XX @@ static int nvic_pending_prio(NVICState *s)
16
static bool nvic_rettobase(NVICState *s)
17
{
18
int irq, nhand = 0;
19
+ bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
20
21
for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
22
- if (s->vectors[irq].active) {
23
+ if (s->vectors[irq].active ||
24
+ (check_sec && irq < NVIC_INTERNAL_VECTORS &&
25
+ s->sec_vectors[irq].active)) {
26
nhand++;
27
if (nhand == 2) {
28
return 0;
29
--
30
2.7.4
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/31] nvic: Implement NVIC_ITNS<n> registers
Deleted patch
1
For v8M, the NVIC has a new set of registers per interrupt,
2
NVIC_ITNS<n>. These determine whether the interrupt targets Secure
3
or Non-secure state. Implement the register read/write code for
4
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
5
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
6
accesses to fields corresponding to interrupts which are
7
configured to target secure state.
8
1
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
12
---
13
include/hw/intc/armv7m_nvic.h | 3 ++
14
hw/intc/armv7m_nvic.c | 74 +++++++++++++++++++++++++++++++++++++++----
15
2 files changed, 70 insertions(+), 7 deletions(-)
16
17
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/intc/armv7m_nvic.h
20
+++ b/include/hw/intc/armv7m_nvic.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
22
/* The PRIGROUP field in AIRCR is banked */
23
uint32_t prigroup[M_REG_NUM_BANKS];
24
25
+ /* v8M NVIC_ITNS state (stored as a bool per bit) */
26
+ bool itns[NVIC_MAX_VECTORS];
27
+
28
/* The following fields are all cached state that can be recalculated
29
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
30
* - vectpending
31
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/intc/armv7m_nvic.c
34
+++ b/hw/intc/armv7m_nvic.c
35
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
36
switch (offset) {
37
case 4: /* Interrupt Control Type. */
38
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
39
+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
40
+ {
41
+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
42
+ int i;
43
+
44
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
45
+ goto bad_offset;
46
+ }
47
+ if (!attrs.secure) {
48
+ return 0;
49
+ }
50
+ val = 0;
51
+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
52
+ if (s->itns[startvec + i]) {
53
+ val |= (1 << i);
54
+ }
55
+ }
56
+ return val;
57
+ }
58
case 0xd00: /* CPUID Base. */
59
return cpu->midr;
60
case 0xd04: /* Interrupt Control State. */
61
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
62
ARMCPU *cpu = s->cpu;
63
64
switch (offset) {
65
+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
66
+ {
67
+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
68
+ int i;
69
+
70
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
71
+ goto bad_offset;
72
+ }
73
+ if (!attrs.secure) {
74
+ break;
75
+ }
76
+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
77
+ s->itns[startvec + i] = (value >> i) & 1;
78
+ }
79
+ nvic_irq_update(s);
80
+ break;
81
+ }
82
case 0xd04: /* Interrupt Control State. */
83
if (value & (1 << 31)) {
84
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
85
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
86
startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
87
88
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
89
- if (s->vectors[startvec + i].enabled) {
90
+ if (s->vectors[startvec + i].enabled &&
91
+ (attrs.secure || s->itns[startvec + i])) {
92
val |= (1 << i);
93
}
94
}
95
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
96
val = 0;
97
startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
98
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
99
- if (s->vectors[startvec + i].pending) {
100
+ if (s->vectors[startvec + i].pending &&
101
+ (attrs.secure || s->itns[startvec + i])) {
102
val |= (1 << i);
103
}
104
}
105
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
106
startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
107
108
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
109
- if (s->vectors[startvec + i].active) {
110
+ if (s->vectors[startvec + i].active &&
111
+ (attrs.secure || s->itns[startvec + i])) {
112
val |= (1 << i);
113
}
114
}
115
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
116
startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
117
118
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
119
- val |= s->vectors[startvec + i].prio << (8 * i);
120
+ if (attrs.secure || s->itns[startvec + i]) {
121
+ val |= s->vectors[startvec + i].prio << (8 * i);
122
+ }
123
}
124
break;
125
case 0xd18 ... 0xd23: /* System Handler Priority. */
126
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
127
startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
128
129
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
130
- if (value & (1 << i)) {
131
+ if (value & (1 << i) &&
132
+ (attrs.secure || s->itns[startvec + i])) {
133
s->vectors[startvec + i].enabled = setval;
134
}
135
}
136
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
137
startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
138
139
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
140
- if (value & (1 << i)) {
141
+ if (value & (1 << i) &&
142
+ (attrs.secure || s->itns[startvec + i])) {
143
s->vectors[startvec + i].pending = setval;
144
}
145
}
146
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
147
startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
148
149
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
150
- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
151
+ if (attrs.secure || s->itns[startvec + i]) {
152
+ set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
153
+ }
154
}
155
nvic_irq_update(s);
156
return MEMTX_OK;
157
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
158
VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
159
vmstate_VecInfo, VecInfo),
160
VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
161
+ VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),
162
VMSTATE_END_OF_LIST()
163
}
164
};
165
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
166
s->vectpending = 0;
167
s->vectpending_is_s_banked = false;
168
s->vectpending_prio = NVIC_NOEXC_PRIO;
169
+
170
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
171
+ memset(s->itns, 0, sizeof(s->itns));
172
+ } else {
173
+ /* This state is constant and not guest accessible in a non-security
174
+ * NVIC; we set the bits to true to avoid having to do a feature
175
+ * bit check in the NVIC enable/pend/etc register accessors.
176
+ */
177
+ int i;
178
+
179
+ for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {
180
+ s->itns[i] = true;
181
+ }
182
+ }
183
}
184
185
static void nvic_systick_trigger(void *opaque, int n, int level)
186
--
187
2.7.4
188
189
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
[PULL 15/22] target/arm/helper.c: Delete stray obsolete comment
1
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
1
In commit 88ce6c6ee85d we switched from directly fishing the number
2
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
2
of breakpoints and watchpoints out of the ID register fields to
3
preempt execution. The simple way to achieve this is to clear the
3
abstracting out functions to do this job, but we forgot to delete the
4
enable bit for it, since the enable bit isn't guest visible.
4
now-obsolete comment in define_debug_regs() about the relation
5
between the ID field value and the actual number of breakpoints and
6
watchpoints. Delete the obsolete comment.
5
7
8
Reported-by: CHRIS HOWARD <cvz185@web.de>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org
12
Message-id: 20220513131801.4082712-1-peter.maydell@linaro.org
9
---
13
---
10
hw/intc/armv7m_nvic.c | 12 ++++++++++--
14
target/arm/helper.c | 1 -
11
1 file changed, 10 insertions(+), 2 deletions(-)
15
1 file changed, 1 deletion(-)
12
16
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/armv7m_nvic.c
19
--- a/target/arm/helper.c
16
+++ b/hw/intc/armv7m_nvic.c
20
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
21
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
18
(R_V7M_AIRCR_SYSRESETREQS_MASK |
22
define_one_arm_cp_reg(cpu, &dbgdidr);
19
R_V7M_AIRCR_BFHFNMINS_MASK |
20
R_V7M_AIRCR_PRIS_MASK);
21
- /* BFHFNMINS changes the priority of Secure HardFault */
22
+ /* BFHFNMINS changes the priority of Secure HardFault, and
23
+ * allows a pending Non-secure HardFault to preempt (which
24
+ * we implement by marking it enabled).
25
+ */
26
if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
27
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
28
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
29
} else {
30
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
31
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
32
}
33
}
34
nvic_irq_update(s);
35
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
36
NVICState *s = NVIC(dev);
37
38
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
39
- s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
40
/* MEM, BUS, and USAGE are enabled through
41
* the System Handler Control register
42
*/
43
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
44
45
/* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
46
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
47
+ /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
48
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
49
+ } else {
50
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
51
}
23
}
52
24
53
/* Strictly speaking the reset handler should be enabled.
25
- /* Note that all these register fields hold "number of Xs minus 1". */
26
brps = arm_num_brps(cpu);
27
wrps = arm_num_wrps(cpu);
28
ctx_cmps = arm_num_ctx_cmps(cpu);
54
--
29
--
55
2.7.4
30
2.25.1
56
31
57
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/31] nvic: Support banked exceptions in acknowledge and complete
[PULL 16/22] target/arm: Make number of counters in PMCR follow the CPU
1
Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq()
1
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
2
to handle banked exceptions:
2
means that we don't provide the 6 counters that are required by the
3
* acknowledge needs to use the correct vector, which may be
3
Arm BSA (Base System Architecture) specification if the CPU supports
4
in sec_vectors[]
4
the Virtualization extensions.
5
* acknowledge needs to return to its caller whether the
5
6
exception should be taken to secure or non-secure state
6
Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
7
* complete needs its caller to tell it whether the exception
7
specify the PMCR reset value (obtained from the appropriate TRM), and
8
being completed is a secure one or not
8
use the 'N' field of that value to define the number of counters
9
provided.
10
11
This means that we now supply 6 counters instead of 4 for:
12
Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72,
13
Cortex-A76, Neoverse-N1, '-cpu max'
14
This CPU goes from 4 to 8 counters:
15
A64FX
16
These CPUs remain with 4 counters:
17
Cortex-A7, Cortex-A8
18
This CPU goes down from 4 to 3 counters:
19
Cortex-R5
20
21
Note that because we now use the PMCR reset value of the specific
22
implementation, we no longer set the LC bit out of reset. This has
23
an UNKNOWN value out of reset for all cores with any AArch32 support,
24
so guest software should be setting it anyway if it wants it.
25
26
This change was originally landed in commit f7fb73b8cdd3f7 (during
27
the 6.0 release cycle) but was then reverted by commit
28
21c2dd77a6aa517 before that release because it did not work with KVM.
29
This version fixes that by creating the scratch vCPU in
30
kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature
31
if KVM supports it, and then only asking KVM for the PMCR_EL0 value
32
if the vCPU has a PMU.
9
33
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
36
[PMM: Added the correct value for a64fx]
37
Message-id: 20220513122852.4063586-1-peter.maydell@linaro.org
13
---
38
---
14
target/arm/cpu.h | 15 +++++++++++++--
39
target/arm/cpu.h | 1 +
15
hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++++------
40
target/arm/internals.h | 4 +++-
16
target/arm/helper.c | 8 +++++---
41
target/arm/cpu64.c | 11 +++++++++++
17
hw/intc/trace-events | 4 ++--
42
target/arm/cpu_tcg.c | 6 ++++++
18
4 files changed, 40 insertions(+), 13 deletions(-)
43
target/arm/helper.c | 25 ++++++++++++++-----------
44
target/arm/kvm64.c | 12 ++++++++++++
45
6 files changed, 47 insertions(+), 12 deletions(-)
19
46
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
47
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
49
--- a/target/arm/cpu.h
23
+++ b/target/arm/cpu.h
50
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
51
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
25
* of architecturally banked exceptions.
52
uint64_t id_aa64dfr0;
26
*/
53
uint64_t id_aa64dfr1;
27
void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
54
uint64_t id_aa64zfr0;
28
-void armv7m_nvic_acknowledge_irq(void *opaque);
55
+ uint64_t reset_pmcr_el0;
29
+/**
56
} isar;
30
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
57
uint64_t midr;
31
+ * @opaque: the NVIC
58
uint32_t revidr;
32
+ *
59
diff --git a/target/arm/internals.h b/target/arm/internals.h
33
+ * Move the current highest priority pending exception from the pending
60
index XXXXXXX..XXXXXXX 100644
34
+ * state to the active state, and update v7m.exception to indicate that
61
--- a/target/arm/internals.h
35
+ * it is the exception currently being handled.
62
+++ b/target/arm/internals.h
36
+ *
63
@@ -XXX,XX +XXX,XX @@ enum MVEECIState {
37
+ * Returns: true if exception should be taken to Secure state, false for NS
64
38
+ */
65
static inline uint32_t pmu_num_counters(CPUARMState *env)
39
+bool armv7m_nvic_acknowledge_irq(void *opaque);
40
/**
41
* armv7m_nvic_complete_irq: complete specified interrupt or exception
42
* @opaque: the NVIC
43
* @irq: the exception number to complete
44
+ * @secure: true if this exception was secure
45
*
46
* Returns: -1 if the irq was not active
47
* 1 if completing this irq brought us back to base (no active irqs)
48
* 0 if there is still an irq active after this one was completed
49
* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
50
*/
51
-int armv7m_nvic_complete_irq(void *opaque, int irq);
52
+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
53
/**
54
* armv7m_nvic_raw_execution_priority: return the raw execution priority
55
* @opaque: the NVIC
56
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/armv7m_nvic.c
59
+++ b/hw/intc/armv7m_nvic.c
60
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
61
}
62
63
/* Make pending IRQ active. */
64
-void armv7m_nvic_acknowledge_irq(void *opaque)
65
+bool armv7m_nvic_acknowledge_irq(void *opaque)
66
{
66
{
67
NVICState *s = (NVICState *)opaque;
67
- return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
68
CPUARMState *env = &s->cpu->env;
68
+ ARMCPU *cpu = env_archcpu(env);
69
const int pending = s->vectpending;
69
+
70
const int running = nvic_exec_prio(s);
70
+ return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
71
VecInfo *vec;
71
}
72
+ bool targets_secure;
72
73
73
/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
74
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
74
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
75
75
index XXXXXXX..XXXXXXX 100644
76
- vec = &s->vectors[pending];
76
--- a/target/arm/cpu64.c
77
+ if (s->vectpending_is_s_banked) {
77
+++ b/target/arm/cpu64.c
78
+ vec = &s->sec_vectors[pending];
78
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
79
+ targets_secure = true;
79
cpu->isar.id_aa64isar0 = 0x00011120;
80
+ } else {
80
cpu->isar.id_aa64mmfr0 = 0x00001124;
81
+ vec = &s->vectors[pending];
81
cpu->isar.dbgdidr = 0x3516d000;
82
+ targets_secure = !exc_is_banked(s->vectpending) &&
82
+ cpu->isar.reset_pmcr_el0 = 0x41013000;
83
+ exc_targets_secure(s, s->vectpending);
83
cpu->clidr = 0x0a200023;
84
+ }
84
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
85
85
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
86
assert(vec->enabled);
86
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
87
assert(vec->pending);
87
cpu->isar.id_aa64isar0 = 0x00011120;
88
88
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
89
assert(s->vectpending_prio < running);
89
cpu->isar.dbgdidr = 0x3516d000;
90
90
+ cpu->isar.reset_pmcr_el0 = 0x41033000;
91
- trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
91
cpu->clidr = 0x0a200023;
92
+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio, targets_secure);
92
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
93
93
cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
94
vec->active = 1;
94
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
95
vec->pending = 0;
95
cpu->isar.id_aa64isar0 = 0x00011120;
96
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
96
cpu->isar.id_aa64mmfr0 = 0x00001124;
97
env->v7m.exception = s->vectpending;
97
cpu->isar.dbgdidr = 0x3516d000;
98
98
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
99
nvic_irq_update(s);
99
cpu->clidr = 0x0a200023;
100
+
100
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
101
+ return targets_secure;
101
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
102
}
102
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
103
103
cpu->isar.mvfr0 = 0x10110222;
104
-int armv7m_nvic_complete_irq(void *opaque, int irq)
104
cpu->isar.mvfr1 = 0x13211111;
105
+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
105
cpu->isar.mvfr2 = 0x00000043;
106
{
106
+
107
NVICState *s = (NVICState *)opaque;
107
+ /* From D5.1 AArch64 PMU register summary */
108
VecInfo *vec;
108
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
109
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq)
109
}
110
110
111
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
111
static void aarch64_neoverse_n1_initfn(Object *obj)
112
112
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
113
- vec = &s->vectors[irq];
113
cpu->isar.mvfr0 = 0x10110222;
114
+ if (secure && exc_is_banked(irq)) {
114
cpu->isar.mvfr1 = 0x13211111;
115
+ vec = &s->sec_vectors[irq];
115
cpu->isar.mvfr2 = 0x00000043;
116
+ } else {
116
+
117
+ vec = &s->vectors[irq];
117
+ /* From D5.1 AArch64 PMU register summary */
118
+ }
118
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
119
119
}
120
- trace_nvic_complete_irq(irq);
120
121
+ trace_nvic_complete_irq(irq, secure);
121
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
122
122
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
123
if (!vec->active) {
123
set_bit(1, cpu->sve_vq_supported); /* 256bit */
124
/* Tell the caller this was an illegal exception return */
124
set_bit(3, cpu->sve_vq_supported); /* 512bit */
125
126
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
127
+
128
/* TODO: Add A64FX specific HPC extension registers */
129
}
130
131
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/cpu_tcg.c
134
+++ b/target/arm/cpu_tcg.c
135
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
136
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
137
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
138
cpu->reset_auxcr = 2;
139
+ cpu->isar.reset_pmcr_el0 = 0x41002000;
140
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
141
}
142
143
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
144
cpu->clidr = (1 << 27) | (1 << 24) | 3;
145
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
146
cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
147
+ cpu->isar.reset_pmcr_el0 = 0x41093000;
148
define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
149
}
150
151
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
152
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
153
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
154
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
155
+ cpu->isar.reset_pmcr_el0 = 0x41072000;
156
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
157
}
158
159
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
160
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
161
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
162
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
163
+ cpu->isar.reset_pmcr_el0 = 0x410F3000;
164
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
165
}
166
167
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
168
cpu->isar.id_isar6 = 0x0;
169
cpu->mp_is_up = true;
170
cpu->pmsav7_dregion = 16;
171
+ cpu->isar.reset_pmcr_el0 = 0x41151800;
172
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
173
}
174
175
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
176
cpu->isar.id_isar5 = 0x00011121;
177
cpu->isar.id_isar6 = 0;
178
cpu->isar.dbgdidr = 0x3516d000;
179
+ cpu->isar.reset_pmcr_el0 = 0x41013000;
180
cpu->clidr = 0x0a200023;
181
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
182
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
125
diff --git a/target/arm/helper.c b/target/arm/helper.c
183
diff --git a/target/arm/helper.c b/target/arm/helper.c
126
index XXXXXXX..XXXXXXX 100644
184
index XXXXXXX..XXXXXXX 100644
127
--- a/target/arm/helper.c
185
--- a/target/arm/helper.c
128
+++ b/target/arm/helper.c
186
+++ b/target/arm/helper.c
129
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
187
@@ -XXX,XX +XXX,XX @@
130
bool return_to_sp_process = false;
188
#include "cpregs.h"
131
bool return_to_handler = false;
189
132
bool rettobase = false;
190
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
133
+ bool exc_secure = false;
191
-#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
134
192
135
/* We can only get here from an EXCP_EXCEPTION_EXIT, and
193
#ifndef CONFIG_USER_ONLY
136
* gen_bx_excret() enforces the architectural rule
194
137
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
195
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
138
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
196
.resetvalue = 0,
139
*/
197
.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
140
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
198
#endif
141
- int es = excret & R_V7M_EXCRET_ES_MASK;
199
- /* The only field of MDCR_EL2 that has a defined architectural reset value
142
+ exc_secure = excret & R_V7M_EXCRET_ES_MASK;
200
- * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
143
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
201
- */
144
- env->v7m.faultmask[es] = 0;
202
- { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
145
+ env->v7m.faultmask[exc_secure] = 0;
203
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
146
}
204
- .access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS,
147
} else {
205
- .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
148
env->v7m.faultmask[M_REG_NS] = 0;
206
{ .name = "HPFAR", .state = ARM_CP_STATE_AA32,
207
.cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
208
.access = PL2_RW, .accessfn = access_el3_aa32ns,
209
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
210
* field as main ID register, and we implement four counters in
211
* addition to the cycle count register.
212
*/
213
- unsigned int i, pmcrn = PMCR_NUM_COUNTERS;
214
+ unsigned int i, pmcrn = pmu_num_counters(&cpu->env);
215
ARMCPRegInfo pmcr = {
216
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
217
.access = PL0_RW,
218
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
219
.access = PL0_RW, .accessfn = pmreg_access,
220
.type = ARM_CP_IO,
221
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
222
- .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
223
- PMCRLC,
224
+ .resetvalue = cpu->isar.reset_pmcr_el0,
225
.writefn = pmcr_write, .raw_writefn = raw_write,
226
};
227
+
228
define_one_arm_cp_reg(cpu, &pmcr);
229
define_one_arm_cp_reg(cpu, &pmcr64);
230
for (i = 0; i < pmcrn; i++) {
231
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
232
.type = ARM_CP_EL3_NO_EL2_C_NZ,
233
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
234
};
235
+ /*
236
+ * The only field of MDCR_EL2 that has a defined architectural reset
237
+ * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
238
+ */
239
+ ARMCPRegInfo mdcr_el2 = {
240
+ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
241
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
242
+ .access = PL2_RW, .resetvalue = pmu_num_counters(env),
243
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2),
244
+ };
245
+ define_one_arm_cp_reg(cpu, &mdcr_el2);
246
define_arm_cp_regs(cpu, vpidr_regs);
247
define_arm_cp_regs(cpu, el2_cp_reginfo);
248
if (arm_feature(env, ARM_FEATURE_V8)) {
249
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
250
index XXXXXXX..XXXXXXX 100644
251
--- a/target/arm/kvm64.c
252
+++ b/target/arm/kvm64.c
253
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
254
*/
255
int fdarray[3];
256
bool sve_supported;
257
+ bool pmu_supported = false;
258
uint64_t features = 0;
259
uint64_t t;
260
int err;
261
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
262
1 << KVM_ARM_VCPU_PTRAUTH_GENERIC);
263
}
264
265
+ if (kvm_arm_pmu_supported()) {
266
+ init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
267
+ pmu_supported = true;
268
+ }
269
+
270
if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
271
return false;
272
}
273
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
274
dbgdidr |= (1 << 15); /* RES1 bit */
275
ahcf->isar.dbgdidr = dbgdidr;
149
}
276
}
277
+
278
+ if (pmu_supported) {
279
+ /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */
280
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
281
+ ARM64_SYS_REG(3, 3, 9, 12, 0));
282
+ }
150
}
283
}
151
284
152
- switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {
285
sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
153
+ switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception,
154
+ exc_secure)) {
155
case -1:
156
/* attempt to exit an exception that isn't active */
157
ufault = true;
158
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
159
index XXXXXXX..XXXXXXX 100644
160
--- a/hw/intc/trace-events
161
+++ b/hw/intc/trace-events
162
@@ -XXX,XX +XXX,XX @@ nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
163
nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
164
nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
165
nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
166
-nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
167
-nvic_complete_irq(int irq) "NVIC complete IRQ %d"
168
+nvic_acknowledge_irq(int irq, int prio, bool targets_secure) "NVIC acknowledge IRQ: %d now active (prio %d targets_secure %d)"
169
+nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
170
nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
171
nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
172
nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
173
--
286
--
174
2.7.4
287
2.25.1
175
176
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/31] nvic: Compare group priority for escalation to HF
[PULL 17/22] hw/arm/virt: Fix incorrect non-secure flash dtb node name
1
In armv7m_nvic_set_pending() we have to compare the
1
In the virt board with secure=on we put two nodes in the dtb
2
priority of an exception against the execution priority
2
for flash devices: one for the secure-only flash, and one
3
to decide whether it needs to be escalated to HardFault.
3
for the non-secure flash. We get the reg properties for these
4
In the specification this is a comparison against the
4
correct, but in the DT node name, which by convention includes
5
exception's group priority; for v7M we implemented it
5
the base address of devices, we used the wrong address. Fix it.
6
as a comparison against the raw exception priority
6
7
because the two comparisons will always give the
7
Spotted by dtc, which will complain
8
same answer. For v8M the existence of AIRCR.PRIS and
8
Warning (unique_unit_address): /flash@0: duplicate unit-address (also used in node /secflash@0)
9
the possibility of different PRIGROUP values for secure
9
if you dump the dtb from QEMU with -machine dumpdtb=file.dtb
10
and nonsecure exceptions means we need to explicitly
10
and then decompile it with dtc.
11
calculate the vector's group priority for this check.
12
11
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 1505240046-11454-12-git-send-email-peter.maydell@linaro.org
14
Message-id: 20220513131316.4081539-2-peter.maydell@linaro.org
16
---
15
---
17
hw/intc/armv7m_nvic.c | 2 +-
16
hw/arm/virt.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
19
18
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
21
--- a/hw/arm/virt.c
23
+++ b/hw/intc/armv7m_nvic.c
22
+++ b/hw/arm/virt.c
24
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
23
@@ -XXX,XX +XXX,XX @@ static void virt_flash_fdt(VirtMachineState *vms,
25
int running = nvic_exec_prio(s);
24
qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
26
bool escalate = false;
25
g_free(nodename);
27
26
28
- if (vec->prio >= running) {
27
- nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
29
+ if (exc_group_prio(s, vec->prio, secure) >= running) {
28
+ nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
30
trace_nvic_escalate_prio(irq, vec->prio, running);
29
qemu_fdt_add_subnode(ms->fdt, nodename);
31
escalate = true;
30
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
32
} else if (!vec->enabled) {
31
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
33
--
32
--
34
2.7.4
33
2.25.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/31] nvic: Make SHCSR banked for v8M
[PULL 18/22] hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node
1
Handle banking of SHCSR: some register bits are banked between
1
The virt board generates a gpio-keys node in the dtb, but it
2
Secure and Non-Secure, and some are only accessible to Secure.
2
incorrectly gives this node #size-cells and #address-cells
3
properties. If you dump the dtb with 'machine dumpdtb=file.dtb'
4
and run it through dtc, dtc will warn about this:
5
6
Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
7
8
Remove the bogus properties.
3
9
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505240046-11454-19-git-send-email-peter.maydell@linaro.org
12
Message-id: 20220513131316.4081539-3-peter.maydell@linaro.org
7
---
13
---
8
hw/intc/armv7m_nvic.c | 221 ++++++++++++++++++++++++++++++++++++++------------
14
hw/arm/virt.c | 2 --
9
1 file changed, 169 insertions(+), 52 deletions(-)
15
1 file changed, 2 deletions(-)
10
16
11
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/armv7m_nvic.c
19
--- a/hw/arm/virt.c
14
+++ b/hw/intc/armv7m_nvic.c
20
+++ b/hw/arm/virt.c
15
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
21
@@ -XXX,XX +XXX,XX @@ static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
16
val = cpu->env.v7m.ccr[attrs.secure];
22
17
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
23
qemu_fdt_add_subnode(fdt, "/gpio-keys");
18
return val;
24
qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
19
- case 0xd24: /* System Handler Status. */
25
- qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0);
20
+ case 0xd24: /* System Handler Control and State (SHCSR) */
26
- qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1);
21
val = 0;
27
22
- if (s->vectors[ARMV7M_EXCP_MEM].active) {
28
qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
23
- val |= (1 << 0);
29
qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
24
- }
25
- if (s->vectors[ARMV7M_EXCP_BUS].active) {
26
- val |= (1 << 1);
27
- }
28
- if (s->vectors[ARMV7M_EXCP_USAGE].active) {
29
- val |= (1 << 3);
30
+ if (attrs.secure) {
31
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
32
+ val |= (1 << 0);
33
+ }
34
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {
35
+ val |= (1 << 2);
36
+ }
37
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {
38
+ val |= (1 << 3);
39
+ }
40
+ if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {
41
+ val |= (1 << 7);
42
+ }
43
+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {
44
+ val |= (1 << 10);
45
+ }
46
+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {
47
+ val |= (1 << 11);
48
+ }
49
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {
50
+ val |= (1 << 12);
51
+ }
52
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {
53
+ val |= (1 << 13);
54
+ }
55
+ if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {
56
+ val |= (1 << 15);
57
+ }
58
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {
59
+ val |= (1 << 16);
60
+ }
61
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {
62
+ val |= (1 << 18);
63
+ }
64
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {
65
+ val |= (1 << 21);
66
+ }
67
+ /* SecureFault is not banked but is always RAZ/WI to NS */
68
+ if (s->vectors[ARMV7M_EXCP_SECURE].active) {
69
+ val |= (1 << 4);
70
+ }
71
+ if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {
72
+ val |= (1 << 19);
73
+ }
74
+ if (s->vectors[ARMV7M_EXCP_SECURE].pending) {
75
+ val |= (1 << 20);
76
+ }
77
+ } else {
78
+ if (s->vectors[ARMV7M_EXCP_MEM].active) {
79
+ val |= (1 << 0);
80
+ }
81
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
82
+ /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
83
+ if (s->vectors[ARMV7M_EXCP_HARD].active) {
84
+ val |= (1 << 2);
85
+ }
86
+ if (s->vectors[ARMV7M_EXCP_HARD].pending) {
87
+ val |= (1 << 21);
88
+ }
89
+ }
90
+ if (s->vectors[ARMV7M_EXCP_USAGE].active) {
91
+ val |= (1 << 3);
92
+ }
93
+ if (s->vectors[ARMV7M_EXCP_SVC].active) {
94
+ val |= (1 << 7);
95
+ }
96
+ if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
97
+ val |= (1 << 10);
98
+ }
99
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
100
+ val |= (1 << 11);
101
+ }
102
+ if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
103
+ val |= (1 << 12);
104
+ }
105
+ if (s->vectors[ARMV7M_EXCP_MEM].pending) {
106
+ val |= (1 << 13);
107
+ }
108
+ if (s->vectors[ARMV7M_EXCP_SVC].pending) {
109
+ val |= (1 << 15);
110
+ }
111
+ if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
112
+ val |= (1 << 16);
113
+ }
114
+ if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
115
+ val |= (1 << 18);
116
+ }
117
}
118
- if (s->vectors[ARMV7M_EXCP_SVC].active) {
119
- val |= (1 << 7);
120
+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
121
+ if (s->vectors[ARMV7M_EXCP_BUS].active) {
122
+ val |= (1 << 1);
123
+ }
124
+ if (s->vectors[ARMV7M_EXCP_BUS].pending) {
125
+ val |= (1 << 14);
126
+ }
127
+ if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
128
+ val |= (1 << 17);
129
+ }
130
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
131
+ s->vectors[ARMV7M_EXCP_NMI].active) {
132
+ /* NMIACT is not present in v7M */
133
+ val |= (1 << 5);
134
+ }
135
}
136
+
137
+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
138
if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
139
val |= (1 << 8);
140
}
141
- if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
142
- val |= (1 << 10);
143
- }
144
- if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
145
- val |= (1 << 11);
146
- }
147
- if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
148
- val |= (1 << 12);
149
- }
150
- if (s->vectors[ARMV7M_EXCP_MEM].pending) {
151
- val |= (1 << 13);
152
- }
153
- if (s->vectors[ARMV7M_EXCP_BUS].pending) {
154
- val |= (1 << 14);
155
- }
156
- if (s->vectors[ARMV7M_EXCP_SVC].pending) {
157
- val |= (1 << 15);
158
- }
159
- if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
160
- val |= (1 << 16);
161
- }
162
- if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
163
- val |= (1 << 17);
164
- }
165
- if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
166
- val |= (1 << 18);
167
- }
168
return val;
169
case 0xd28: /* Configurable Fault Status. */
170
/* The BFSR bits [15:8] are shared between security states
171
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
172
173
cpu->env.v7m.ccr[attrs.secure] = value;
174
break;
175
- case 0xd24: /* System Handler Control. */
176
- s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
177
- s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
178
- s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
179
- s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
180
+ case 0xd24: /* System Handler Control and State (SHCSR) */
181
+ if (attrs.secure) {
182
+ s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
183
+ /* Secure HardFault active bit cannot be written */
184
+ s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
185
+ s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
186
+ s->sec_vectors[ARMV7M_EXCP_PENDSV].active =
187
+ (value & (1 << 10)) != 0;
188
+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =
189
+ (value & (1 << 11)) != 0;
190
+ s->sec_vectors[ARMV7M_EXCP_USAGE].pending =
191
+ (value & (1 << 12)) != 0;
192
+ s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
193
+ s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
194
+ s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
195
+ s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
196
+ s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
197
+ (value & (1 << 18)) != 0;
198
+ /* SecureFault not banked, but RAZ/WI to NS */
199
+ s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
200
+ s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
201
+ s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;
202
+ } else {
203
+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
204
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
205
+ /* HARDFAULTPENDED is not present in v7M */
206
+ s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
207
+ }
208
+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
209
+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
210
+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
211
+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
212
+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
213
+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
214
+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
215
+ s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
216
+ s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
217
+ }
218
+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
219
+ s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
220
+ s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
221
+ s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
222
+ }
223
+ /* NMIACT can only be written if the write is of a zero, with
224
+ * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
225
+ */
226
+ if (!attrs.secure && cpu->env.v7m.secure &&
227
+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
228
+ (value & (1 << 5)) == 0) {
229
+ s->vectors[ARMV7M_EXCP_NMI].active = 0;
230
+ }
231
+ /* HARDFAULTACT can only be written if the write is of a zero
232
+ * to the non-secure HardFault state by the CPU in secure state.
233
+ * The only case where we can be targeting the non-secure HF state
234
+ * when in secure state is if this is a write via the NS alias
235
+ * and BFHFNMINS is 1.
236
+ */
237
+ if (!attrs.secure && cpu->env.v7m.secure &&
238
+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
239
+ (value & (1 << 2)) == 0) {
240
+ s->vectors[ARMV7M_EXCP_HARD].active = 0;
241
+ }
242
+
243
+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
244
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
245
- s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
246
- s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
247
- s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
248
- s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
249
- s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
250
- s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
251
- s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
252
- s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
253
- s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
254
nvic_irq_update(s);
255
break;
256
case 0xd28: /* Configurable Fault Status. */
257
--
30
--
258
2.7.4
31
2.25.1
259
260
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/31] hw/gpio/omap_gpio.c: Don't use old_mmio
[PULL 19/22] ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
1
Drop the use of old_mmio in the omap2_gpio memory ops.
1
The traditional ptimer behaviour includes a collection of weird edge
2
case behaviours. In 2016 we improved the ptimer implementation to
3
fix these and generally make the behaviour more flexible, with
4
ptimers opting in to the new behaviour by passing an appropriate set
5
of policy flags to ptimer_init(). For backwards-compatibility, we
6
defined PTIMER_POLICY_DEFAULT (which sets no flags) to give the old
7
weird behaviour.
8
9
This turns out to be a poor choice of name, because people writing
10
new devices which use ptimers are misled into thinking that the
11
default is probably a sensible choice of flags, when in fact it is
12
almost always not what you want. Rename PTIMER_POLICY_DEFAULT to
13
PTIMER_POLICY_LEGACY and beef up the comment to more clearly say that
14
new devices should not be using it.
15
16
The code-change part of this commit was produced by
17
sed -i -e 's/PTIMER_POLICY_DEFAULT/PTIMER_POLICY_LEGACY/g' $(git grep -l PTIMER_POLICY_DEFAULT)
18
with the exception of a test name string change in
19
tests/unit/ptimer-test.c which was added manually.
2
20
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-3-git-send-email-peter.maydell@linaro.org
24
Message-id: 20220516103058.162280-1-peter.maydell@linaro.org
6
---
25
---
7
hw/gpio/omap_gpio.c | 26 ++++++++++++--------------
26
include/hw/ptimer.h | 16 ++++++++++++----
8
1 file changed, 12 insertions(+), 14 deletions(-)
27
hw/arm/musicpal.c | 2 +-
28
hw/dma/xilinx_axidma.c | 2 +-
29
hw/dma/xlnx_csu_dma.c | 2 +-
30
hw/m68k/mcf5206.c | 2 +-
31
hw/m68k/mcf5208.c | 2 +-
32
hw/net/can/xlnx-zynqmp-can.c | 2 +-
33
hw/net/fsl_etsec/etsec.c | 2 +-
34
hw/net/lan9118.c | 2 +-
35
hw/rtc/exynos4210_rtc.c | 4 ++--
36
hw/timer/allwinner-a10-pit.c | 2 +-
37
hw/timer/altera_timer.c | 2 +-
38
hw/timer/arm_timer.c | 2 +-
39
hw/timer/digic-timer.c | 2 +-
40
hw/timer/etraxfs_timer.c | 6 +++---
41
hw/timer/exynos4210_mct.c | 6 +++---
42
hw/timer/exynos4210_pwm.c | 2 +-
43
hw/timer/grlib_gptimer.c | 2 +-
44
hw/timer/imx_epit.c | 4 ++--
45
hw/timer/imx_gpt.c | 2 +-
46
hw/timer/mss-timer.c | 2 +-
47
hw/timer/sh_timer.c | 2 +-
48
hw/timer/slavio_timer.c | 2 +-
49
hw/timer/xilinx_timer.c | 2 +-
50
tests/unit/ptimer-test.c | 6 +++---
51
25 files changed, 44 insertions(+), 36 deletions(-)
9
52
10
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
53
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
11
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/gpio/omap_gpio.c
55
--- a/include/hw/ptimer.h
13
+++ b/hw/gpio/omap_gpio.c
56
+++ b/include/hw/ptimer.h
14
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_write(void *opaque, hwaddr addr,
57
@@ -XXX,XX +XXX,XX @@
58
* to stderr when the guest attempts to enable the timer.
59
*/
60
61
-/* The default ptimer policy retains backward compatibility with the legacy
62
- * timers. Custom policies are adjusting the default one. Consider providing
63
- * a correct policy for your timer.
64
+/*
65
+ * The 'legacy' ptimer policy retains backward compatibility with the
66
+ * traditional ptimer behaviour from before policy flags were introduced.
67
+ * It has several weird behaviours which don't match typical hardware
68
+ * timer behaviour. For a new device using ptimers, you should not
69
+ * use PTIMER_POLICY_LEGACY, but instead check the actual behaviour
70
+ * that you need and specify the right set of policy flags to get that.
71
+ *
72
+ * If you are overhauling an existing device that uses PTIMER_POLICY_LEGACY
73
+ * and are in a position to check or test the real hardware behaviour,
74
+ * consider updating it to specify the right policy flags.
75
*
76
* The rough edges of the default policy:
77
* - Starting to run with a period = 0 emits error message and stops the
78
@@ -XXX,XX +XXX,XX @@
79
* since the last period, effectively restarting the timer with a
80
* counter = counter value at the moment of change (.i.e. one less).
81
*/
82
-#define PTIMER_POLICY_DEFAULT 0
83
+#define PTIMER_POLICY_LEGACY 0
84
85
/* Periodic timer counter stays with "0" for a one period before wrapping
86
* around. */
87
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/arm/musicpal.c
90
+++ b/hw/arm/musicpal.c
91
@@ -XXX,XX +XXX,XX @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
92
sysbus_init_irq(dev, &s->irq);
93
s->freq = freq;
94
95
- s->ptimer = ptimer_init(mv88w8618_timer_tick, s, PTIMER_POLICY_DEFAULT);
96
+ s->ptimer = ptimer_init(mv88w8618_timer_tick, s, PTIMER_POLICY_LEGACY);
97
}
98
99
static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset,
100
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/dma/xilinx_axidma.c
103
+++ b/hw/dma/xilinx_axidma.c
104
@@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
105
106
st->dma = s;
107
st->nr = i;
108
- st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT);
109
+ st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_LEGACY);
110
ptimer_transaction_begin(st->ptimer);
111
ptimer_set_freq(st->ptimer, s->freqhz);
112
ptimer_transaction_commit(st->ptimer);
113
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/hw/dma/xlnx_csu_dma.c
116
+++ b/hw/dma/xlnx_csu_dma.c
117
@@ -XXX,XX +XXX,XX @@ static void xlnx_csu_dma_realize(DeviceState *dev, Error **errp)
118
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
119
120
s->src_timer = ptimer_init(xlnx_csu_dma_src_timeout_hit,
121
- s, PTIMER_POLICY_DEFAULT);
122
+ s, PTIMER_POLICY_LEGACY);
123
124
s->attr = MEMTXATTRS_UNSPECIFIED;
125
126
diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/m68k/mcf5206.c
129
+++ b/hw/m68k/mcf5206.c
130
@@ -XXX,XX +XXX,XX @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq)
131
m5206_timer_state *s;
132
133
s = g_new0(m5206_timer_state, 1);
134
- s->timer = ptimer_init(m5206_timer_trigger, s, PTIMER_POLICY_DEFAULT);
135
+ s->timer = ptimer_init(m5206_timer_trigger, s, PTIMER_POLICY_LEGACY);
136
s->irq = irq;
137
m5206_timer_reset(s);
138
return s;
139
diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c
140
index XXXXXXX..XXXXXXX 100644
141
--- a/hw/m68k/mcf5208.c
142
+++ b/hw/m68k/mcf5208.c
143
@@ -XXX,XX +XXX,XX @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
144
/* Timers. */
145
for (i = 0; i < 2; i++) {
146
s = g_new0(m5208_timer_state, 1);
147
- s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT);
148
+ s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_LEGACY);
149
memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
150
"m5208-timer", 0x00004000);
151
memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
152
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/hw/net/can/xlnx-zynqmp-can.c
155
+++ b/hw/net/can/xlnx-zynqmp-can.c
156
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_can_realize(DeviceState *dev, Error **errp)
157
158
/* Allocate a new timer. */
159
s->can_timer = ptimer_init(xlnx_zynqmp_can_ptimer_cb, s,
160
- PTIMER_POLICY_DEFAULT);
161
+ PTIMER_POLICY_LEGACY);
162
163
ptimer_transaction_begin(s->can_timer);
164
165
diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c
166
index XXXXXXX..XXXXXXX 100644
167
--- a/hw/net/fsl_etsec/etsec.c
168
+++ b/hw/net/fsl_etsec/etsec.c
169
@@ -XXX,XX +XXX,XX @@ static void etsec_realize(DeviceState *dev, Error **errp)
170
object_get_typename(OBJECT(dev)), dev->id, etsec);
171
qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);
172
173
- etsec->ptimer = ptimer_init(etsec_timer_hit, etsec, PTIMER_POLICY_DEFAULT);
174
+ etsec->ptimer = ptimer_init(etsec_timer_hit, etsec, PTIMER_POLICY_LEGACY);
175
ptimer_transaction_begin(etsec->ptimer);
176
ptimer_set_freq(etsec->ptimer, 100);
177
ptimer_transaction_commit(etsec->ptimer);
178
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
179
index XXXXXXX..XXXXXXX 100644
180
--- a/hw/net/lan9118.c
181
+++ b/hw/net/lan9118.c
182
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
183
s->pmt_ctrl = 1;
184
s->txp = &s->tx_packet;
185
186
- s->timer = ptimer_init(lan9118_tick, s, PTIMER_POLICY_DEFAULT);
187
+ s->timer = ptimer_init(lan9118_tick, s, PTIMER_POLICY_LEGACY);
188
ptimer_transaction_begin(s->timer);
189
ptimer_set_freq(s->timer, 10000);
190
ptimer_set_limit(s->timer, 0xffff, 1);
191
diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c
192
index XXXXXXX..XXXXXXX 100644
193
--- a/hw/rtc/exynos4210_rtc.c
194
+++ b/hw/rtc/exynos4210_rtc.c
195
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj)
196
Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
197
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
198
199
- s->ptimer = ptimer_init(exynos4210_rtc_tick, s, PTIMER_POLICY_DEFAULT);
200
+ s->ptimer = ptimer_init(exynos4210_rtc_tick, s, PTIMER_POLICY_LEGACY);
201
ptimer_transaction_begin(s->ptimer);
202
ptimer_set_freq(s->ptimer, RTC_BASE_FREQ);
203
exynos4210_rtc_update_freq(s, 0);
204
ptimer_transaction_commit(s->ptimer);
205
206
s->ptimer_1Hz = ptimer_init(exynos4210_rtc_1Hz_tick,
207
- s, PTIMER_POLICY_DEFAULT);
208
+ s, PTIMER_POLICY_LEGACY);
209
ptimer_transaction_begin(s->ptimer_1Hz);
210
ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ);
211
ptimer_transaction_commit(s->ptimer_1Hz);
212
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
213
index XXXXXXX..XXXXXXX 100644
214
--- a/hw/timer/allwinner-a10-pit.c
215
+++ b/hw/timer/allwinner-a10-pit.c
216
@@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj)
217
218
tc->container = s;
219
tc->index = i;
220
- s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT);
221
+ s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_LEGACY);
15
}
222
}
16
}
223
}
17
224
18
-static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
225
diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c
19
+static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
226
index XXXXXXX..XXXXXXX 100644
20
+ unsigned size)
227
--- a/hw/timer/altera_timer.c
228
+++ b/hw/timer/altera_timer.c
229
@@ -XXX,XX +XXX,XX @@ static void altera_timer_realize(DeviceState *dev, Error **errp)
230
return;
231
}
232
233
- t->ptimer = ptimer_init(timer_hit, t, PTIMER_POLICY_DEFAULT);
234
+ t->ptimer = ptimer_init(timer_hit, t, PTIMER_POLICY_LEGACY);
235
ptimer_transaction_begin(t->ptimer);
236
ptimer_set_freq(t->ptimer, t->freq_hz);
237
ptimer_transaction_commit(t->ptimer);
238
diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c
239
index XXXXXXX..XXXXXXX 100644
240
--- a/hw/timer/arm_timer.c
241
+++ b/hw/timer/arm_timer.c
242
@@ -XXX,XX +XXX,XX @@ static arm_timer_state *arm_timer_init(uint32_t freq)
243
s->freq = freq;
244
s->control = TIMER_CTRL_IE;
245
246
- s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_DEFAULT);
247
+ s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY);
248
vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s);
249
return s;
250
}
251
diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c
252
index XXXXXXX..XXXXXXX 100644
253
--- a/hw/timer/digic-timer.c
254
+++ b/hw/timer/digic-timer.c
255
@@ -XXX,XX +XXX,XX @@ static void digic_timer_init(Object *obj)
21
{
256
{
22
return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
257
DigicTimerState *s = DIGIC_TIMER(obj);
258
259
- s->ptimer = ptimer_init(digic_timer_tick, NULL, PTIMER_POLICY_DEFAULT);
260
+ s->ptimer = ptimer_init(digic_timer_tick, NULL, PTIMER_POLICY_LEGACY);
261
262
/*
263
* FIXME: there is no documentation on Digic timer
264
diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
265
index XXXXXXX..XXXXXXX 100644
266
--- a/hw/timer/etraxfs_timer.c
267
+++ b/hw/timer/etraxfs_timer.c
268
@@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
269
ETRAXTimerState *t = ETRAX_TIMER(dev);
270
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
271
272
- t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_DEFAULT);
273
- t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_DEFAULT);
274
- t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_DEFAULT);
275
+ t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_LEGACY);
276
+ t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_LEGACY);
277
+ t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_LEGACY);
278
279
sysbus_init_irq(sbd, &t->irq);
280
sysbus_init_irq(sbd, &t->nmi);
281
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
282
index XXXXXXX..XXXXXXX 100644
283
--- a/hw/timer/exynos4210_mct.c
284
+++ b/hw/timer/exynos4210_mct.c
285
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj)
286
287
/* Global timer */
288
s->g_timer.ptimer_frc = ptimer_init(exynos4210_gfrc_event, s,
289
- PTIMER_POLICY_DEFAULT);
290
+ PTIMER_POLICY_LEGACY);
291
memset(&s->g_timer.reg, 0, sizeof(struct gregs));
292
293
/* Local timers */
294
for (i = 0; i < 2; i++) {
295
s->l_timer[i].tick_timer.ptimer_tick =
296
ptimer_init(exynos4210_ltick_event, &s->l_timer[i],
297
- PTIMER_POLICY_DEFAULT);
298
+ PTIMER_POLICY_LEGACY);
299
s->l_timer[i].ptimer_frc =
300
ptimer_init(exynos4210_lfrc_event, &s->l_timer[i],
301
- PTIMER_POLICY_DEFAULT);
302
+ PTIMER_POLICY_LEGACY);
303
s->l_timer[i].id = i;
304
}
305
306
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
307
index XXXXXXX..XXXXXXX 100644
308
--- a/hw/timer/exynos4210_pwm.c
309
+++ b/hw/timer/exynos4210_pwm.c
310
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj)
311
sysbus_init_irq(dev, &s->timer[i].irq);
312
s->timer[i].ptimer = ptimer_init(exynos4210_pwm_tick,
313
&s->timer[i],
314
- PTIMER_POLICY_DEFAULT);
315
+ PTIMER_POLICY_LEGACY);
316
s->timer[i].id = i;
317
s->timer[i].parent = s;
318
}
319
diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/timer/grlib_gptimer.c
322
+++ b/hw/timer/grlib_gptimer.c
323
@@ -XXX,XX +XXX,XX @@ static void grlib_gptimer_realize(DeviceState *dev, Error **errp)
324
325
timer->unit = unit;
326
timer->ptimer = ptimer_init(grlib_gptimer_hit, timer,
327
- PTIMER_POLICY_DEFAULT);
328
+ PTIMER_POLICY_LEGACY);
329
timer->id = i;
330
331
/* One IRQ line for each timer */
332
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/timer/imx_epit.c
335
+++ b/hw/timer/imx_epit.c
336
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
337
0x00001000);
338
sysbus_init_mmio(sbd, &s->iomem);
339
340
- s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_DEFAULT);
341
+ s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
342
343
- s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_DEFAULT);
344
+ s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
23
}
345
}
24
346
25
static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
347
static void imx_epit_class_init(ObjectClass *klass, void *data)
26
- uint32_t value)
348
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
27
+ uint64_t value, unsigned size)
349
index XXXXXXX..XXXXXXX 100644
350
--- a/hw/timer/imx_gpt.c
351
+++ b/hw/timer/imx_gpt.c
352
@@ -XXX,XX +XXX,XX @@ static void imx_gpt_realize(DeviceState *dev, Error **errp)
353
0x00001000);
354
sysbus_init_mmio(sbd, &s->iomem);
355
356
- s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_DEFAULT);
357
+ s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_LEGACY);
358
}
359
360
static void imx_gpt_class_init(ObjectClass *klass, void *data)
361
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
362
index XXXXXXX..XXXXXXX 100644
363
--- a/hw/timer/mss-timer.c
364
+++ b/hw/timer/mss-timer.c
365
@@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj)
366
for (i = 0; i < NUM_TIMERS; i++) {
367
struct Msf2Timer *st = &t->timers[i];
368
369
- st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT);
370
+ st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_LEGACY);
371
ptimer_transaction_begin(st->ptimer);
372
ptimer_set_freq(st->ptimer, t->freq_hz);
373
ptimer_transaction_commit(st->ptimer);
374
diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c
375
index XXXXXXX..XXXXXXX 100644
376
--- a/hw/timer/sh_timer.c
377
+++ b/hw/timer/sh_timer.c
378
@@ -XXX,XX +XXX,XX @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
379
s->enabled = 0;
380
s->irq = irq;
381
382
- s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
383
+ s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_LEGACY);
384
385
sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
386
sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
387
diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c
388
index XXXXXXX..XXXXXXX 100644
389
--- a/hw/timer/slavio_timer.c
390
+++ b/hw/timer/slavio_timer.c
391
@@ -XXX,XX +XXX,XX @@ static void slavio_timer_init(Object *obj)
392
tc->timer_index = i;
393
394
s->cputimer[i].timer = ptimer_init(slavio_timer_irq, tc,
395
- PTIMER_POLICY_DEFAULT);
396
+ PTIMER_POLICY_LEGACY);
397
ptimer_transaction_begin(s->cputimer[i].timer);
398
ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
399
ptimer_transaction_commit(s->cputimer[i].timer);
400
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
401
index XXXXXXX..XXXXXXX 100644
402
--- a/hw/timer/xilinx_timer.c
403
+++ b/hw/timer/xilinx_timer.c
404
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
405
406
xt->parent = t;
407
xt->nr = i;
408
- xt->ptimer = ptimer_init(timer_hit, xt, PTIMER_POLICY_DEFAULT);
409
+ xt->ptimer = ptimer_init(timer_hit, xt, PTIMER_POLICY_LEGACY);
410
ptimer_transaction_begin(xt->ptimer);
411
ptimer_set_freq(xt->ptimer, t->freq_hz);
412
ptimer_transaction_commit(xt->ptimer);
413
diff --git a/tests/unit/ptimer-test.c b/tests/unit/ptimer-test.c
414
index XXXXXXX..XXXXXXX 100644
415
--- a/tests/unit/ptimer-test.c
416
+++ b/tests/unit/ptimer-test.c
417
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
418
char policy_name[256] = "";
419
char *tmp;
420
421
- if (policy == PTIMER_POLICY_DEFAULT) {
422
- g_sprintf(policy_name, "default");
423
+ if (policy == PTIMER_POLICY_LEGACY) {
424
+ g_sprintf(policy_name, "legacy");
425
}
426
427
if (policy & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) {
428
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
429
static void add_all_ptimer_policies_comb_tests(void)
28
{
430
{
29
uint32_t cur = 0;
431
int last_policy = PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT;
30
uint32_t mask = 0xffff;
432
- int policy = PTIMER_POLICY_DEFAULT;
31
433
+ int policy = PTIMER_POLICY_LEGACY;
32
+ if (size == 4) {
434
33
+ omap2_gpio_module_write(opaque, addr, value);
435
for (; policy < (last_policy << 1); policy++) {
34
+ return;
436
if ((policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
35
+ }
36
+
37
switch (addr & ~3) {
38
case 0x00:    /* GPIO_REVISION */
39
case 0x14:    /* GPIO_SYSSTATUS */
40
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
41
}
42
43
static const MemoryRegionOps omap2_gpio_module_ops = {
44
- .old_mmio = {
45
- .read = {
46
- omap2_gpio_module_readp,
47
- omap2_gpio_module_readp,
48
- omap2_gpio_module_read,
49
- },
50
- .write = {
51
- omap2_gpio_module_writep,
52
- omap2_gpio_module_writep,
53
- omap2_gpio_module_write,
54
- },
55
- },
56
+ .read = omap2_gpio_module_readp,
57
+ .write = omap2_gpio_module_writep,
58
+ .valid.min_access_size = 1,
59
+ .valid.max_access_size = 4,
60
.endianness = DEVICE_NATIVE_ENDIAN,
61
};
62
63
--
437
--
64
2.7.4
438
2.25.1
65
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/31] msf2: Add Emcraft's Smartfusion2 SOM kit
[PULL 20/22] target/arm: Fix PAuth keys access checks for disabled SEL2
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Florian Lugou <florian.lugou@provenrun.com>
2
2
3
Emulated Emcraft's Smartfusion2 System On Module starter
3
As per the description of the HCR_EL2.APK field in the ARMv8 ARM,
4
kit.
4
Pointer Authentication keys accesses should only be trapped to Secure
5
EL2 if it is enabled.
5
6
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20170920201737.25723-6-f4bug@amsat.org
9
Message-id: 20220517145242.1215271-1-florian.lugou@provenrun.com
9
[PMD: drop cpu_model to directly use cpu type]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
hw/arm/Makefile.objs | 2 +-
12
target/arm/helper.c | 2 +-
13
hw/arm/msf2-som.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
2 files changed, 106 insertions(+), 1 deletion(-)
15
create mode 100644 hw/arm/msf2-som.c
16
14
17
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/Makefile.objs
17
--- a/target/arm/helper.c
20
+++ b/hw/arm/Makefile.objs
18
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
19
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
22
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
20
int el = arm_current_el(env);
23
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
21
24
obj-$(CONFIG_MPS2) += mps2.o
22
if (el < 2 &&
25
-obj-$(CONFIG_MSF2) += msf2-soc.o
23
- arm_feature(env, ARM_FEATURE_EL2) &&
26
+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
24
+ arm_is_el2_enabled(env) &&
27
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
25
!(arm_hcr_el2_eff(env) & HCR_APK)) {
28
new file mode 100644
26
return CP_ACCESS_TRAP_EL2;
29
index XXXXXXX..XXXXXXX
27
}
30
--- /dev/null
31
+++ b/hw/arm/msf2-som.c
32
@@ -XXX,XX +XXX,XX @@
33
+/*
34
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
35
+ *
36
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
37
+ *
38
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
39
+ * of this software and associated documentation files (the "Software"), to deal
40
+ * in the Software without restriction, including without limitation the rights
41
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
42
+ * copies of the Software, and to permit persons to whom the Software is
43
+ * furnished to do so, subject to the following conditions:
44
+ *
45
+ * The above copyright notice and this permission notice shall be included in
46
+ * all copies or substantial portions of the Software.
47
+ *
48
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
49
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
50
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
51
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
52
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
53
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
54
+ * THE SOFTWARE.
55
+ */
56
+
57
+#include "qemu/osdep.h"
58
+#include "qapi/error.h"
59
+#include "qemu/error-report.h"
60
+#include "hw/boards.h"
61
+#include "hw/arm/arm.h"
62
+#include "exec/address-spaces.h"
63
+#include "qemu/cutils.h"
64
+#include "hw/arm/msf2-soc.h"
65
+#include "cpu.h"
66
+
67
+#define DDR_BASE_ADDRESS 0xA0000000
68
+#define DDR_SIZE (64 * M_BYTE)
69
+
70
+#define M2S010_ENVM_SIZE (256 * K_BYTE)
71
+#define M2S010_ESRAM_SIZE (64 * K_BYTE)
72
+
73
+static void emcraft_sf2_s2s010_init(MachineState *machine)
74
+{
75
+ DeviceState *dev;
76
+ DeviceState *spi_flash;
77
+ MSF2State *soc;
78
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
79
+ DriveInfo *dinfo = drive_get_next(IF_MTD);
80
+ qemu_irq cs_line;
81
+ SSIBus *spi_bus;
82
+ MemoryRegion *sysmem = get_system_memory();
83
+ MemoryRegion *ddr = g_new(MemoryRegion, 1);
84
+
85
+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
86
+ error_report("This board can only be used with CPU %s",
87
+ mc->default_cpu_type);
88
+ }
89
+
90
+ memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
91
+ &error_fatal);
92
+ memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
93
+
94
+ dev = qdev_create(NULL, TYPE_MSF2_SOC);
95
+ qdev_prop_set_string(dev, "part-name", "M2S010");
96
+ qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
97
+
98
+ qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
99
+ qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
100
+
101
+ /*
102
+ * CPU clock and peripheral clocks(APB0, APB1)are configurable
103
+ * in Libero. CPU clock is divided by APB0 and APB1 divisors for
104
+ * peripherals. Emcraft's SoM kit comes with these settings by default.
105
+ */
106
+ qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
107
+ qdev_prop_set_uint32(dev, "apb0div", 2);
108
+ qdev_prop_set_uint32(dev, "apb1div", 2);
109
+
110
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
111
+
112
+ soc = MSF2_SOC(dev);
113
+
114
+ /* Attach SPI flash to SPI0 controller */
115
+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
116
+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
117
+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
118
+ if (dinfo) {
119
+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
120
+ &error_fatal);
121
+ }
122
+ qdev_init_nofail(spi_flash);
123
+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
124
+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
125
+
126
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
127
+ soc->envm_size);
128
+}
129
+
130
+static void emcraft_sf2_machine_init(MachineClass *mc)
131
+{
132
+ mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
133
+ mc->init = emcraft_sf2_s2s010_init;
134
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
135
+}
136
+
137
+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
138
--
28
--
139
2.7.4
29
2.25.1
140
141
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/31] msf2: Add Smartfusion2 SPI controller
[PULL 21/22] target/arm: Enable FEAT_HCX for -cpu max
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Modelled Microsemi's Smartfusion2 SPI controller.
3
This feature adds a new register, HCRX_EL2, which controls
4
many of the newer AArch64 features. So far the register is
5
effectively RES0, because none of the new features are done.
4
6
5
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20220517054850.177016-2-richard.henderson@linaro.org
8
Message-id: 20170920201737.25723-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/ssi/Makefile.objs | 1 +
12
target/arm/cpu.h | 20 ++++++++++++++++++
12
include/hw/ssi/mss-spi.h | 58 +++++++
13
target/arm/cpu64.c | 1 +
13
hw/ssi/mss-spi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++
14
target/arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++++++++
14
3 files changed, 463 insertions(+)
15
3 files changed, 71 insertions(+)
15
create mode 100644 include/hw/ssi/mss-spi.h
16
create mode 100644 hw/ssi/mss-spi.c
17
16
18
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ssi/Makefile.objs
19
--- a/target/arm/cpu.h
21
+++ b/hw/ssi/Makefile.objs
20
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
21
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
23
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
22
uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
24
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
23
uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
25
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
24
uint64_t hcr_el2; /* Hypervisor configuration register */
26
+common-obj-$(CONFIG_MSF2) += mss-spi.o
25
+ uint64_t hcrx_el2; /* Extended Hypervisor configuration register */
27
26
uint64_t scr_el3; /* Secure configuration register. */
28
obj-$(CONFIG_OMAP) += omap_spi.o
27
union { /* Fault status registers. */
29
obj-$(CONFIG_IMX) += imx_spi.o
28
struct {
30
diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
29
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
31
new file mode 100644
30
#define HCR_TWEDEN (1ULL << 59)
32
index XXXXXXX..XXXXXXX
31
#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
33
--- /dev/null
32
34
+++ b/include/hw/ssi/mss-spi.h
33
+#define HCRX_ENAS0 (1ULL << 0)
35
@@ -XXX,XX +XXX,XX @@
34
+#define HCRX_ENALS (1ULL << 1)
36
+/*
35
+#define HCRX_ENASR (1ULL << 2)
37
+ * Microsemi SmartFusion2 SPI
36
+#define HCRX_FNXS (1ULL << 3)
38
+ *
37
+#define HCRX_FGTNXS (1ULL << 4)
39
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
38
+#define HCRX_SMPME (1ULL << 5)
40
+ *
39
+#define HCRX_TALLINT (1ULL << 6)
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
40
+#define HCRX_VINMI (1ULL << 7)
42
+ * of this software and associated documentation files (the "Software"), to deal
41
+#define HCRX_VFNMI (1ULL << 8)
43
+ * in the Software without restriction, including without limitation the rights
42
+#define HCRX_CMOW (1ULL << 9)
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
43
+#define HCRX_MCE2 (1ULL << 10)
45
+ * copies of the Software, and to permit persons to whom the Software is
44
+#define HCRX_MSCEN (1ULL << 11)
46
+ * furnished to do so, subject to the following conditions:
47
+ *
48
+ * The above copyright notice and this permission notice shall be included in
49
+ * all copies or substantial portions of the Software.
50
+ *
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
57
+ * THE SOFTWARE.
58
+ */
59
+
45
+
60
+#ifndef HW_MSS_SPI_H
46
#define HPFAR_NS (1ULL << 63)
61
+#define HW_MSS_SPI_H
47
62
+
48
#define SCR_NS (1U << 0)
63
+#include "hw/sysbus.h"
49
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
64
+#include "hw/ssi/ssi.h"
50
* Not included here is HCR_RW.
65
+#include "qemu/fifo32.h"
51
*/
66
+
52
uint64_t arm_hcr_el2_eff(CPUARMState *env);
67
+#define TYPE_MSS_SPI "mss-spi"
53
+uint64_t arm_hcrx_el2_eff(CPUARMState *env);
68
+#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
54
69
+
55
/* Return true if the specified exception level is running in AArch64 state. */
70
+#define R_SPI_MAX 16
56
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
71
+
57
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
72
+typedef struct MSSSpiState {
58
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
73
+ SysBusDevice parent_obj;
59
}
74
+
60
75
+ MemoryRegion mmio;
61
+static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
76
+
77
+ qemu_irq irq;
78
+
79
+ qemu_irq cs_line;
80
+
81
+ SSIBus *spi;
82
+
83
+ Fifo32 rx_fifo;
84
+ Fifo32 tx_fifo;
85
+
86
+ int fifo_depth;
87
+ uint32_t frame_count;
88
+ bool enabled;
89
+
90
+ uint32_t regs[R_SPI_MAX];
91
+} MSSSpiState;
92
+
93
+#endif /* HW_MSS_SPI_H */
94
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
95
new file mode 100644
96
index XXXXXXX..XXXXXXX
97
--- /dev/null
98
+++ b/hw/ssi/mss-spi.c
99
@@ -XXX,XX +XXX,XX @@
100
+/*
101
+ * Block model of SPI controller present in
102
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
103
+ *
104
+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
105
+ *
106
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
107
+ * of this software and associated documentation files (the "Software"), to deal
108
+ * in the Software without restriction, including without limitation the rights
109
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
110
+ * copies of the Software, and to permit persons to whom the Software is
111
+ * furnished to do so, subject to the following conditions:
112
+ *
113
+ * The above copyright notice and this permission notice shall be included in
114
+ * all copies or substantial portions of the Software.
115
+ *
116
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
117
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
118
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
119
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
120
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
121
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
122
+ * THE SOFTWARE.
123
+ */
124
+
125
+#include "qemu/osdep.h"
126
+#include "hw/ssi/mss-spi.h"
127
+#include "qemu/log.h"
128
+
129
+#ifndef MSS_SPI_ERR_DEBUG
130
+#define MSS_SPI_ERR_DEBUG 0
131
+#endif
132
+
133
+#define DB_PRINT_L(lvl, fmt, args...) do { \
134
+ if (MSS_SPI_ERR_DEBUG >= lvl) { \
135
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
136
+ } \
137
+} while (0);
138
+
139
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
140
+
141
+#define FIFO_CAPACITY 32
142
+
143
+#define R_SPI_CONTROL 0
144
+#define R_SPI_DFSIZE 1
145
+#define R_SPI_STATUS 2
146
+#define R_SPI_INTCLR 3
147
+#define R_SPI_RX 4
148
+#define R_SPI_TX 5
149
+#define R_SPI_CLKGEN 6
150
+#define R_SPI_SS 7
151
+#define R_SPI_MIS 8
152
+#define R_SPI_RIS 9
153
+
154
+#define S_TXDONE (1 << 0)
155
+#define S_RXRDY (1 << 1)
156
+#define S_RXCHOVRF (1 << 2)
157
+#define S_RXFIFOFUL (1 << 4)
158
+#define S_RXFIFOFULNXT (1 << 5)
159
+#define S_RXFIFOEMP (1 << 6)
160
+#define S_RXFIFOEMPNXT (1 << 7)
161
+#define S_TXFIFOFUL (1 << 8)
162
+#define S_TXFIFOFULNXT (1 << 9)
163
+#define S_TXFIFOEMP (1 << 10)
164
+#define S_TXFIFOEMPNXT (1 << 11)
165
+#define S_FRAMESTART (1 << 12)
166
+#define S_SSEL (1 << 13)
167
+#define S_ACTIVE (1 << 14)
168
+
169
+#define C_ENABLE (1 << 0)
170
+#define C_MODE (1 << 1)
171
+#define C_INTRXDATA (1 << 4)
172
+#define C_INTTXDATA (1 << 5)
173
+#define C_INTRXOVRFLO (1 << 6)
174
+#define C_SPS (1 << 26)
175
+#define C_BIGFIFO (1 << 29)
176
+#define C_RESET (1 << 31)
177
+
178
+#define FRAMESZ_MASK 0x1F
179
+#define FMCOUNT_MASK 0x00FFFF00
180
+#define FMCOUNT_SHIFT 8
181
+
182
+static void txfifo_reset(MSSSpiState *s)
183
+{
62
+{
184
+ fifo32_reset(&s->tx_fifo);
63
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
185
+
186
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
187
+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
188
+}
64
+}
189
+
65
+
190
+static void rxfifo_reset(MSSSpiState *s)
66
static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
67
{
68
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
69
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/cpu64.c
72
+++ b/target/arm/cpu64.c
73
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
74
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
75
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
76
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
77
+ t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
78
cpu->isar.id_aa64mmfr1 = t;
79
80
t = cpu->isar.id_aa64mmfr2;
81
diff --git a/target/arm/helper.c b/target/arm/helper.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/helper.c
84
+++ b/target/arm/helper.c
85
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
86
return ret;
87
}
88
89
+static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
90
+ uint64_t value)
191
+{
91
+{
192
+ fifo32_reset(&s->rx_fifo);
92
+ uint64_t valid_mask = 0;
193
+
93
+
194
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
94
+ /* No features adding bits to HCRX are implemented. */
195
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
95
+
96
+ /* Clear RES0 bits. */
97
+ env->cp15.hcrx_el2 = value & valid_mask;
196
+}
98
+}
197
+
99
+
198
+static void set_fifodepth(MSSSpiState *s)
100
+static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri,
101
+ bool isread)
199
+{
102
+{
200
+ unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
103
+ if (arm_current_el(env) < 3
201
+
104
+ && arm_feature(env, ARM_FEATURE_EL3)
202
+ if (size <= 8) {
105
+ && !(env->cp15.scr_el3 & SCR_HXEN)) {
203
+ s->fifo_depth = 32;
106
+ return CP_ACCESS_TRAP_EL3;
204
+ } else if (size <= 16) {
205
+ s->fifo_depth = 16;
206
+ } else if (size <= 32) {
207
+ s->fifo_depth = 8;
208
+ } else {
209
+ s->fifo_depth = 4;
210
+ }
107
+ }
108
+ return CP_ACCESS_OK;
211
+}
109
+}
212
+
110
+
213
+static void update_mis(MSSSpiState *s)
111
+static const ARMCPRegInfo hcrx_el2_reginfo = {
112
+ .name = "HCRX_EL2", .state = ARM_CP_STATE_AA64,
113
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2,
114
+ .access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen,
115
+ .fieldoffset = offsetof(CPUARMState, cp15.hcrx_el2),
116
+};
117
+
118
+/* Return the effective value of HCRX_EL2. */
119
+uint64_t arm_hcrx_el2_eff(CPUARMState *env)
214
+{
120
+{
215
+ uint32_t reg = s->regs[R_SPI_CONTROL];
216
+ uint32_t tmp;
217
+
218
+ /*
121
+ /*
219
+ * form the Control register interrupt enable bits
122
+ * The bits in this register behave as 0 for all purposes other than
220
+ * same as RIS, MIS and Interrupt clear registers for simplicity
123
+ * direct reads of the register if:
124
+ * - EL2 is not enabled in the current security state,
125
+ * - SCR_EL3.HXEn is 0.
221
+ */
126
+ */
222
+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
127
+ if (!arm_is_el2_enabled(env)
223
+ ((reg & C_INTTXDATA) >> 5);
128
+ || (arm_feature(env, ARM_FEATURE_EL3)
224
+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
129
+ && !(env->cp15.scr_el3 & SCR_HXEN))) {
130
+ return 0;
131
+ }
132
+ return env->cp15.hcrx_el2;
225
+}
133
+}
226
+
134
+
227
+static void spi_update_irq(MSSSpiState *s)
135
static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
228
+{
136
uint64_t value)
229
+ int irq;
137
{
230
+
138
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
231
+ update_mis(s);
139
define_arm_cp_regs(cpu, zcr_reginfo);
232
+ irq = !!(s->regs[R_SPI_MIS]);
140
}
233
+
141
234
+ qemu_set_irq(s->irq, irq);
142
+ if (cpu_isar_feature(aa64_hcx, cpu)) {
235
+}
143
+ define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo);
236
+
237
+static void mss_spi_reset(DeviceState *d)
238
+{
239
+ MSSSpiState *s = MSS_SPI(d);
240
+
241
+ memset(s->regs, 0, sizeof s->regs);
242
+ s->regs[R_SPI_CONTROL] = 0x80000102;
243
+ s->regs[R_SPI_DFSIZE] = 0x4;
244
+ s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
245
+ s->regs[R_SPI_CLKGEN] = 0x7;
246
+ s->regs[R_SPI_RIS] = 0x0;
247
+
248
+ s->fifo_depth = 4;
249
+ s->frame_count = 1;
250
+ s->enabled = false;
251
+
252
+ rxfifo_reset(s);
253
+ txfifo_reset(s);
254
+}
255
+
256
+static uint64_t
257
+spi_read(void *opaque, hwaddr addr, unsigned int size)
258
+{
259
+ MSSSpiState *s = opaque;
260
+ uint32_t ret = 0;
261
+
262
+ addr >>= 2;
263
+ switch (addr) {
264
+ case R_SPI_RX:
265
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
266
+ s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
267
+ ret = fifo32_pop(&s->rx_fifo);
268
+ if (fifo32_is_empty(&s->rx_fifo)) {
269
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
270
+ }
271
+ break;
272
+
273
+ case R_SPI_MIS:
274
+ update_mis(s);
275
+ ret = s->regs[R_SPI_MIS];
276
+ break;
277
+
278
+ default:
279
+ if (addr < ARRAY_SIZE(s->regs)) {
280
+ ret = s->regs[addr];
281
+ } else {
282
+ qemu_log_mask(LOG_GUEST_ERROR,
283
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
284
+ addr * 4);
285
+ return ret;
286
+ }
287
+ break;
288
+ }
144
+ }
289
+
145
+
290
+ DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
146
#ifdef TARGET_AARCH64
291
+ spi_update_irq(s);
147
if (cpu_isar_feature(aa64_pauth, cpu)) {
292
+ return ret;
148
define_arm_cp_regs(cpu, pauth_reginfo);
293
+}
294
+
295
+static void assert_cs(MSSSpiState *s)
296
+{
297
+ qemu_set_irq(s->cs_line, 0);
298
+}
299
+
300
+static void deassert_cs(MSSSpiState *s)
301
+{
302
+ qemu_set_irq(s->cs_line, 1);
303
+}
304
+
305
+static void spi_flush_txfifo(MSSSpiState *s)
306
+{
307
+ uint32_t tx;
308
+ uint32_t rx;
309
+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
310
+
311
+ /*
312
+ * Chip Select(CS) is automatically controlled by this controller.
313
+ * If SPS bit is set in Control register then CS is asserted
314
+ * until all the frames set in frame count of Control register are
315
+ * transferred. If SPS is not set then CS pulses between frames.
316
+ * Note that Slave Select register specifies which of the CS line
317
+ * has to be controlled automatically by controller. Bits SS[7:1] are for
318
+ * masters in FPGA fabric since we model only Microcontroller subsystem
319
+ * of Smartfusion2 we control only one CS(SS[0]) line.
320
+ */
321
+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
322
+ assert_cs(s);
323
+
324
+ s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
325
+
326
+ tx = fifo32_pop(&s->tx_fifo);
327
+ DB_PRINT("data tx:0x%" PRIx32, tx);
328
+ rx = ssi_transfer(s->spi, tx);
329
+ DB_PRINT("data rx:0x%" PRIx32, rx);
330
+
331
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
332
+ s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
333
+ s->regs[R_SPI_RIS] |= S_RXCHOVRF;
334
+ } else {
335
+ fifo32_push(&s->rx_fifo, rx);
336
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
337
+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
338
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
339
+ } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
340
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
341
+ }
342
+ }
343
+ s->frame_count--;
344
+ if (!sps) {
345
+ deassert_cs(s);
346
+ }
347
+ }
348
+
349
+ if (!s->frame_count) {
350
+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
351
+ FMCOUNT_SHIFT;
352
+ deassert_cs(s);
353
+ s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
354
+ s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
355
+ }
356
+}
357
+
358
+static void spi_write(void *opaque, hwaddr addr,
359
+ uint64_t val64, unsigned int size)
360
+{
361
+ MSSSpiState *s = opaque;
362
+ uint32_t value = val64;
363
+
364
+ DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
365
+ addr >>= 2;
366
+
367
+ switch (addr) {
368
+ case R_SPI_TX:
369
+ /* adding to already full FIFO */
370
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
371
+ break;
372
+ }
373
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
374
+ fifo32_push(&s->tx_fifo, value);
375
+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
376
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
377
+ } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
378
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
379
+ }
380
+ if (s->enabled) {
381
+ spi_flush_txfifo(s);
382
+ }
383
+ break;
384
+
385
+ case R_SPI_CONTROL:
386
+ s->regs[R_SPI_CONTROL] = value;
387
+ if (value & C_BIGFIFO) {
388
+ set_fifodepth(s);
389
+ } else {
390
+ s->fifo_depth = 4;
391
+ }
392
+ s->enabled = value & C_ENABLE;
393
+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
394
+ if (value & C_RESET) {
395
+ mss_spi_reset(DEVICE(s));
396
+ }
397
+ break;
398
+
399
+ case R_SPI_DFSIZE:
400
+ if (s->enabled) {
401
+ break;
402
+ }
403
+ s->regs[R_SPI_DFSIZE] = value;
404
+ break;
405
+
406
+ case R_SPI_INTCLR:
407
+ s->regs[R_SPI_INTCLR] = value;
408
+ if (value & S_TXDONE) {
409
+ s->regs[R_SPI_RIS] &= ~S_TXDONE;
410
+ }
411
+ if (value & S_RXRDY) {
412
+ s->regs[R_SPI_RIS] &= ~S_RXRDY;
413
+ }
414
+ if (value & S_RXCHOVRF) {
415
+ s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
416
+ }
417
+ break;
418
+
419
+ case R_SPI_MIS:
420
+ case R_SPI_STATUS:
421
+ case R_SPI_RIS:
422
+ qemu_log_mask(LOG_GUEST_ERROR,
423
+ "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
424
+ __func__, addr * 4);
425
+ break;
426
+
427
+ default:
428
+ if (addr < ARRAY_SIZE(s->regs)) {
429
+ s->regs[addr] = value;
430
+ } else {
431
+ qemu_log_mask(LOG_GUEST_ERROR,
432
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
433
+ addr * 4);
434
+ }
435
+ break;
436
+ }
437
+
438
+ spi_update_irq(s);
439
+}
440
+
441
+static const MemoryRegionOps spi_ops = {
442
+ .read = spi_read,
443
+ .write = spi_write,
444
+ .endianness = DEVICE_NATIVE_ENDIAN,
445
+ .valid = {
446
+ .min_access_size = 1,
447
+ .max_access_size = 4
448
+ }
449
+};
450
+
451
+static void mss_spi_realize(DeviceState *dev, Error **errp)
452
+{
453
+ MSSSpiState *s = MSS_SPI(dev);
454
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
455
+
456
+ s->spi = ssi_create_bus(dev, "spi");
457
+
458
+ sysbus_init_irq(sbd, &s->irq);
459
+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
460
+ sysbus_init_irq(sbd, &s->cs_line);
461
+
462
+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
463
+ TYPE_MSS_SPI, R_SPI_MAX * 4);
464
+ sysbus_init_mmio(sbd, &s->mmio);
465
+
466
+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
467
+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
468
+}
469
+
470
+static const VMStateDescription vmstate_mss_spi = {
471
+ .name = TYPE_MSS_SPI,
472
+ .version_id = 1,
473
+ .minimum_version_id = 1,
474
+ .fields = (VMStateField[]) {
475
+ VMSTATE_FIFO32(tx_fifo, MSSSpiState),
476
+ VMSTATE_FIFO32(rx_fifo, MSSSpiState),
477
+ VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
478
+ VMSTATE_END_OF_LIST()
479
+ }
480
+};
481
+
482
+static void mss_spi_class_init(ObjectClass *klass, void *data)
483
+{
484
+ DeviceClass *dc = DEVICE_CLASS(klass);
485
+
486
+ dc->realize = mss_spi_realize;
487
+ dc->reset = mss_spi_reset;
488
+ dc->vmsd = &vmstate_mss_spi;
489
+}
490
+
491
+static const TypeInfo mss_spi_info = {
492
+ .name = TYPE_MSS_SPI,
493
+ .parent = TYPE_SYS_BUS_DEVICE,
494
+ .instance_size = sizeof(MSSSpiState),
495
+ .class_init = mss_spi_class_init,
496
+};
497
+
498
+static void mss_spi_register_types(void)
499
+{
500
+ type_register_static(&mss_spi_info);
501
+}
502
+
503
+type_init(mss_spi_register_types)
504
--
149
--
505
2.7.4
150
2.25.1
506
507
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/31] nvic: Make set_pending and clear_pending take a secure parameter
[PULL 22/22] target/arm: Use FIELD definitions for CPACR, CPTR_ELx
1
Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()
1
From: Richard Henderson <richard.henderson@linaro.org>
2
functions take a bool indicating whether to pend the secure
3
or non-secure version of a banked interrupt, and update the
4
callsites accordingly.
5
2
6
In most callsites we can simply pass the correct security
3
We had a few CPTR_* bits defined, but missed quite a few.
7
state in; in a couple of cases we use TODO comments to indicate
4
Complete all of the fields up to ARMv9.2.
8
that we will return the code in a subsequent commit.
5
Use FIELD_EX64 instead of manual extract32.
9
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220517054850.177016-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-10-git-send-email-peter.maydell@linaro.org
13
---
11
---
14
target/arm/cpu.h | 14 ++++++++++-
12
target/arm/cpu.h | 44 +++++++++++++++++++++++++++++++-----
15
hw/intc/armv7m_nvic.c | 64 ++++++++++++++++++++++++++++++++++++++-------------
13
hw/arm/boot.c | 2 +-
16
target/arm/helper.c | 24 +++++++++++--------
14
target/arm/cpu.c | 11 ++++++---
17
hw/intc/trace-events | 4 ++--
15
target/arm/helper.c | 54 ++++++++++++++++++++++-----------------------
18
4 files changed, 77 insertions(+), 29 deletions(-)
16
4 files changed, 75 insertions(+), 36 deletions(-)
19
17
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
20
--- a/target/arm/cpu.h
23
+++ b/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
22
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
25
return true;
23
#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
26
}
24
#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
25
26
-#define CPTR_TCPAC (1U << 31)
27
-#define CPTR_TTA (1U << 20)
28
-#define CPTR_TFP (1U << 10)
29
-#define CPTR_TZ (1U << 8) /* CPTR_EL2 */
30
-#define CPTR_EZ (1U << 8) /* CPTR_EL3 */
31
+/* Bit definitions for CPACR (AArch32 only) */
32
+FIELD(CPACR, CP10, 20, 2)
33
+FIELD(CPACR, CP11, 22, 2)
34
+FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
35
+FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
36
+FIELD(CPACR, ASEDIS, 31, 1)
37
+
38
+/* Bit definitions for CPACR_EL1 (AArch64 only) */
39
+FIELD(CPACR_EL1, ZEN, 16, 2)
40
+FIELD(CPACR_EL1, FPEN, 20, 2)
41
+FIELD(CPACR_EL1, SMEN, 24, 2)
42
+FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
43
+
44
+/* Bit definitions for HCPTR (AArch32 only) */
45
+FIELD(HCPTR, TCP10, 10, 1)
46
+FIELD(HCPTR, TCP11, 11, 1)
47
+FIELD(HCPTR, TASE, 15, 1)
48
+FIELD(HCPTR, TTA, 20, 1)
49
+FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
50
+FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
51
+
52
+/* Bit definitions for CPTR_EL2 (AArch64 only) */
53
+FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
54
+FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
55
+FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
56
+FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
57
+FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
58
+FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
59
+FIELD(CPTR_EL2, TTA, 28, 1)
60
+FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
61
+FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
62
+
63
+/* Bit definitions for CPTR_EL3 (AArch64 only) */
64
+FIELD(CPTR_EL3, EZ, 8, 1)
65
+FIELD(CPTR_EL3, TFP, 10, 1)
66
+FIELD(CPTR_EL3, ESM, 12, 1)
67
+FIELD(CPTR_EL3, TTA, 20, 1)
68
+FIELD(CPTR_EL3, TAM, 30, 1)
69
+FIELD(CPTR_EL3, TCPAC, 31, 1)
70
71
#define MDCR_EPMAD (1U << 21)
72
#define MDCR_EDAD (1U << 20)
73
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/arm/boot.c
76
+++ b/hw/arm/boot.c
77
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
78
env->cp15.scr_el3 |= SCR_ATA;
79
}
80
if (cpu_isar_feature(aa64_sve, cpu)) {
81
- env->cp15.cptr_el[3] |= CPTR_EZ;
82
+ env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
83
}
84
/* AArch64 kernels never boot in secure mode */
85
assert(!info->secure_boot);
86
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/cpu.c
89
+++ b/target/arm/cpu.c
90
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
91
/* Trap on btype=3 for PACIxSP. */
92
env->cp15.sctlr_el[1] |= SCTLR_BT0;
93
/* and to the FP/Neon instructions */
94
- env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
95
+ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
96
+ CPACR_EL1, FPEN, 3);
97
/* and to the SVE instructions */
98
- env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
99
+ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
100
+ CPACR_EL1, ZEN, 3);
101
/* with reasonable vector length */
102
if (cpu_isar_feature(aa64_sve, cpu)) {
103
env->vfp.zcr_el[1] =
104
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
105
} else {
106
#if defined(CONFIG_USER_ONLY)
107
/* Userspace expects access to cp10 and cp11 for FP/Neon */
108
- env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
109
+ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
110
+ CPACR, CP10, 3);
111
+ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
112
+ CPACR, CP11, 3);
27
#endif
113
#endif
28
-void armv7m_nvic_set_pending(void *opaque, int irq);
114
}
29
+/**
30
+ * armv7m_nvic_set_pending: mark the specified exception as pending
31
+ * @opaque: the NVIC
32
+ * @irq: the exception number to mark pending
33
+ * @secure: false for non-banked exceptions or for the nonsecure
34
+ * version of a banked exception, true for the secure version of a banked
35
+ * exception.
36
+ *
37
+ * Marks the specified exception as pending. Note that we will assert()
38
+ * if @secure is true and @irq does not specify one of the fixed set
39
+ * of architecturally banked exceptions.
40
+ */
41
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
42
void armv7m_nvic_acknowledge_irq(void *opaque);
43
/**
44
* armv7m_nvic_complete_irq: complete specified interrupt or exception
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
49
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
50
qemu_set_irq(s->excpout, lvl);
51
}
52
53
-static void armv7m_nvic_clear_pending(void *opaque, int irq)
54
+/**
55
+ * armv7m_nvic_clear_pending: mark the specified exception as not pending
56
+ * @opaque: the NVIC
57
+ * @irq: the exception number to mark as not pending
58
+ * @secure: false for non-banked exceptions or for the nonsecure
59
+ * version of a banked exception, true for the secure version of a banked
60
+ * exception.
61
+ *
62
+ * Marks the specified exception as not pending. Note that we will assert()
63
+ * if @secure is true and @irq does not specify one of the fixed set
64
+ * of architecturally banked exceptions.
65
+ */
66
+static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
67
{
68
NVICState *s = (NVICState *)opaque;
69
VecInfo *vec;
70
71
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
72
73
- vec = &s->vectors[irq];
74
- trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
75
+ if (secure) {
76
+ assert(exc_is_banked(irq));
77
+ vec = &s->sec_vectors[irq];
78
+ } else {
79
+ vec = &s->vectors[irq];
80
+ }
81
+ trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
82
if (vec->pending) {
83
vec->pending = 0;
84
nvic_irq_update(s);
85
}
86
}
87
88
-void armv7m_nvic_set_pending(void *opaque, int irq)
89
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
90
{
91
NVICState *s = (NVICState *)opaque;
92
+ bool banked = exc_is_banked(irq);
93
VecInfo *vec;
94
95
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
96
+ assert(!secure || banked);
97
98
- vec = &s->vectors[irq];
99
- trace_nvic_set_pending(irq, vec->enabled, vec->prio);
100
+ vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
101
102
+ trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);
103
104
if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
105
/* If a synchronous exception is pending then it may be
106
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq)
107
"(current priority %d)\n", irq, running);
108
}
109
110
- /* We can do the escalation, so we take HardFault instead */
111
+ /* We can do the escalation, so we take HardFault instead.
112
+ * If BFHFNMINS is set then we escalate to the banked HF for
113
+ * the target security state of the original exception; otherwise
114
+ * we take a Secure HardFault.
115
+ */
116
irq = ARMV7M_EXCP_HARD;
117
- vec = &s->vectors[irq];
118
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
119
+ (secure ||
120
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
121
+ vec = &s->sec_vectors[irq];
122
+ } else {
123
+ vec = &s->vectors[irq];
124
+ }
125
+ /* HF may be banked but there is only one shared HFSR */
126
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
127
}
128
}
129
@@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level)
130
if (level != vec->level) {
131
vec->level = level;
132
if (level) {
133
- armv7m_nvic_set_pending(s, n);
134
+ armv7m_nvic_set_pending(s, n, false);
135
}
136
}
137
}
138
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
139
}
140
case 0xd04: /* Interrupt Control State. */
141
if (value & (1 << 31)) {
142
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
143
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
144
}
145
if (value & (1 << 28)) {
146
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
147
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
148
} else if (value & (1 << 27)) {
149
- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
150
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
151
}
152
if (value & (1 << 26)) {
153
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
154
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
155
} else if (value & (1 << 25)) {
156
- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
157
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
158
}
159
break;
160
case 0xd08: /* Vector Table Offset. */
161
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
162
{
163
int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
164
if (excnum < s->num_irq) {
165
- armv7m_nvic_set_pending(s, excnum);
166
+ armv7m_nvic_set_pending(s, excnum, false);
167
}
168
break;
169
}
170
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
171
/* SysTick just asked us to pend its exception.
172
* (This is different from an external interrupt line's
173
* behaviour.)
174
+ * TODO: when we implement the banked systicks we must make
175
+ * this pend the correct banked exception.
176
*/
177
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
178
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);
179
}
180
}
181
115
182
diff --git a/target/arm/helper.c b/target/arm/helper.c
116
diff --git a/target/arm/helper.c b/target/arm/helper.c
183
index XXXXXXX..XXXXXXX 100644
117
index XXXXXXX..XXXXXXX 100644
184
--- a/target/arm/helper.c
118
--- a/target/arm/helper.c
185
+++ b/target/arm/helper.c
119
+++ b/target/arm/helper.c
186
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
120
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
187
* stack, directly take a usage fault on the current stack.
188
*/
121
*/
189
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
122
if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
190
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
123
/* VFP coprocessor: cp10 & cp11 [23:20] */
191
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
124
- mask |= (1 << 31) | (1 << 30) | (0xf << 20);
192
v7m_exception_taken(cpu, excret);
125
+ mask |= R_CPACR_ASEDIS_MASK |
193
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
126
+ R_CPACR_D32DIS_MASK |
194
"stackframe: failed exception return integrity check\n");
127
+ R_CPACR_CP11_MASK |
195
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
128
+ R_CPACR_CP10_MASK;
196
* exception return excret specified then this is a UsageFault.
129
197
*/
130
if (!arm_feature(env, ARM_FEATURE_NEON)) {
198
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
131
/* ASEDIS [31] bit is RAO/WI */
199
- /* Take an INVPC UsageFault by pushing the stack again. */
132
- value |= (1 << 31);
200
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
133
+ value |= R_CPACR_ASEDIS_MASK;
201
+ /* Take an INVPC UsageFault by pushing the stack again.
134
}
202
+ * TODO: the v8M version of this code should target the
135
203
+ * background state for this exception.
136
/* VFPv3 and upwards with NEON implement 32 double precision
204
+ */
137
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
205
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);
138
*/
206
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
139
if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
207
v7m_push_stack(cpu);
140
/* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
208
v7m_exception_taken(cpu, excret);
141
- value |= (1 << 30);
209
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
142
+ value |= R_CPACR_D32DIS_MASK;
210
handle it. */
143
}
211
switch (cs->exception_index) {
144
}
212
case EXCP_UDEF:
145
value &= mask;
213
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
146
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
214
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
147
*/
215
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
148
if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
216
break;
149
!arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
217
case EXCP_NOCP:
150
- value &= ~(0xf << 20);
218
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
151
- value |= env->cp15.cpacr_el1 & (0xf << 20);
219
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
152
+ mask = R_CPACR_CP11_MASK | R_CPACR_CP10_MASK;
220
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
153
+ value = (value & ~mask) | (env->cp15.cpacr_el1 & mask);
221
break;
154
}
222
case EXCP_INVSTATE:
155
223
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
156
env->cp15.cpacr_el1 = value;
224
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
157
@@ -XXX,XX +XXX,XX @@ static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
225
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
158
226
break;
159
if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
227
case EXCP_SWI:
160
!arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
228
/* The PC already points to the next instruction. */
161
- value &= ~(0xf << 20);
229
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
162
+ value = ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK);
230
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
163
}
231
break;
164
return value;
232
case EXCP_PREFETCH_ABORT:
165
}
233
case EXCP_DATA_ABORT:
166
@@ -XXX,XX +XXX,XX @@ static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
234
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
167
if (arm_feature(env, ARM_FEATURE_V8)) {
235
env->v7m.bfar);
168
/* Check if CPACR accesses are to be trapped to EL2 */
169
if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) &&
170
- (env->cp15.cptr_el[2] & CPTR_TCPAC)) {
171
+ FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) {
172
return CP_ACCESS_TRAP_EL2;
173
/* Check if CPACR accesses are to be trapped to EL3 */
174
} else if (arm_current_el(env) < 3 &&
175
- (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
176
+ FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) {
177
return CP_ACCESS_TRAP_EL3;
178
}
179
}
180
@@ -XXX,XX +XXX,XX @@ static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
181
bool isread)
182
{
183
/* Check if CPTR accesses are set to trap to EL3 */
184
- if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
185
+ if (arm_current_el(env) == 2 &&
186
+ FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) {
187
return CP_ACCESS_TRAP_EL3;
188
}
189
190
@@ -XXX,XX +XXX,XX @@ static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
191
*/
192
if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
193
!arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
194
- value &= ~(0x3 << 10);
195
- value |= env->cp15.cptr_el[2] & (0x3 << 10);
196
+ uint64_t mask = R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK;
197
+ value = (value & ~mask) | (env->cp15.cptr_el[2] & mask);
198
}
199
env->cp15.cptr_el[2] = value;
200
}
201
@@ -XXX,XX +XXX,XX @@ static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
202
203
if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
204
!arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
205
- value |= 0x3 << 10;
206
+ value |= R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK;
207
}
208
return value;
209
}
210
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
211
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
212
213
if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
214
- /* Check CPACR.ZEN. */
215
- switch (extract32(env->cp15.cpacr_el1, 16, 2)) {
216
+ switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) {
217
case 1:
218
if (el != 0) {
236
break;
219
break;
237
}
220
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
238
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
221
}
239
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
222
240
break;
223
/* Check CPACR.FPEN. */
241
default:
224
- switch (extract32(env->cp15.cpacr_el1, 20, 2)) {
242
/* All other FSR values are either MPU faults or "can't happen
225
+ switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) {
243
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
226
case 1:
244
env->v7m.mmfar[env->v7m.secure]);
227
if (el != 0) {
245
break;
228
break;
246
}
229
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
247
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
230
*/
248
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,
231
if (el <= 2) {
249
+ env->v7m.secure);
232
if (hcr_el2 & HCR_E2H) {
250
break;
233
- /* Check CPTR_EL2.ZEN. */
251
}
234
- switch (extract32(env->cp15.cptr_el[2], 16, 2)) {
252
break;
235
+ switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) {
253
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
236
case 1:
254
return;
237
if (el != 0 || !(hcr_el2 & HCR_TGE)) {
255
}
238
break;
256
}
239
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
257
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
240
return 2;
258
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
241
}
259
break;
242
260
case EXCP_IRQ:
243
- /* Check CPTR_EL2.FPEN. */
261
break;
244
- switch (extract32(env->cp15.cptr_el[2], 20, 2)) {
262
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
245
+ switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) {
263
index XXXXXXX..XXXXXXX 100644
246
case 1:
264
--- a/hw/intc/trace-events
247
if (el == 2 || !(hcr_el2 & HCR_TGE)) {
265
+++ b/hw/intc/trace-events
248
break;
266
@@ -XXX,XX +XXX,XX @@ nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
249
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
267
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
250
return 0;
268
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
251
}
269
nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
252
} else if (arm_is_el2_enabled(env)) {
270
-nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)"
253
- if (env->cp15.cptr_el[2] & CPTR_TZ) {
271
-nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)"
254
+ if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) {
272
+nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
255
return 2;
273
+nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
256
}
274
nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
257
- if (env->cp15.cptr_el[2] & CPTR_TFP) {
275
nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
258
+ if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) {
276
nvic_complete_irq(int irq) "NVIC complete IRQ %d"
259
return 0;
260
}
261
}
262
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
263
264
/* CPTR_EL3. Since EZ is negative we must check for EL3. */
265
if (arm_feature(env, ARM_FEATURE_EL3)
266
- && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
267
+ && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) {
268
return 3;
269
}
270
#endif
271
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
272
* This register is ignored if E2H+TGE are both set.
273
*/
274
if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
275
- int fpen = extract32(env->cp15.cpacr_el1, 20, 2);
276
+ int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN);
277
278
switch (fpen) {
279
case 0:
280
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
281
*/
282
if (cur_el <= 2) {
283
if (hcr_el2 & HCR_E2H) {
284
- /* Check CPTR_EL2.FPEN. */
285
- switch (extract32(env->cp15.cptr_el[2], 20, 2)) {
286
+ switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) {
287
case 1:
288
if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) {
289
break;
290
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
291
return 2;
292
}
293
} else if (arm_is_el2_enabled(env)) {
294
- if (env->cp15.cptr_el[2] & CPTR_TFP) {
295
+ if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) {
296
return 2;
297
}
298
}
299
}
300
301
/* CPTR_EL3 : present in v8 */
302
- if (env->cp15.cptr_el[3] & CPTR_TFP) {
303
+ if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) {
304
/* Trap all FP ops to EL3 */
305
return 3;
306
}
277
--
307
--
278
2.7.4
308
2.25.1
279
280
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/31] nvic: In escalation to HardFault, support HF not being priority -1
Deleted patch
1
When escalating to HardFault, we must go into Lockup if we
2
can't take the synchronous HardFault because the current
3
execution priority is already at or below the priority of
4
HardFault. In v7M HF is always priority -1 so a simple < 0
5
comparison sufficed; in v8M the priority of HardFault can
6
vary depending on whether it is a Secure or NonSecure
7
HardFault, so we must check against the priority of the
8
HardFault exception vector we're about to use.
9
1
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-13-git-send-email-peter.maydell@linaro.org
13
---
14
hw/intc/armv7m_nvic.c | 23 ++++++++++++-----------
15
1 file changed, 12 insertions(+), 11 deletions(-)
16
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
20
+++ b/hw/intc/armv7m_nvic.c
21
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
22
}
23
24
if (escalate) {
25
- if (running < 0) {
26
- /* We want to escalate to HardFault but we can't take a
27
- * synchronous HardFault at this point either. This is a
28
- * Lockup condition due to a guest bug. We don't model
29
- * Lockup, so report via cpu_abort() instead.
30
- */
31
- cpu_abort(&s->cpu->parent_obj,
32
- "Lockup: can't escalate %d to HardFault "
33
- "(current priority %d)\n", irq, running);
34
- }
35
36
- /* We can do the escalation, so we take HardFault instead.
37
+ /* We need to escalate this exception to a synchronous HardFault.
38
* If BFHFNMINS is set then we escalate to the banked HF for
39
* the target security state of the original exception; otherwise
40
* we take a Secure HardFault.
41
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
42
} else {
43
vec = &s->vectors[irq];
44
}
45
+ if (running <= vec->prio) {
46
+ /* We want to escalate to HardFault but we can't take the
47
+ * synchronous HardFault at this point either. This is a
48
+ * Lockup condition due to a guest bug. We don't model
49
+ * Lockup, so report via cpu_abort() instead.
50
+ */
51
+ cpu_abort(&s->cpu->parent_obj,
52
+ "Lockup: can't escalate %d to HardFault "
53
+ "(current priority %d)\n", irq, running);
54
+ }
55
+
56
/* HF may be banked but there is only one shared HFSR */
57
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
58
}
59
--
60
2.7.4
61
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions
Deleted patch
1
In v7M, the fixed-priority exceptions are:
2
Reset: -3
3
NMI: -2
4
HardFault: -1
5
1
6
In v8M, this changes because Secure HardFault may need
7
to be prioritised above NMI:
8
Reset: -4
9
Secure HardFault if AIRCR.BFHFNMINS == 1: -3
10
NMI: -2
11
Secure HardFault if AIRCR.BFHFNMINS == 0: -1
12
NonSecure HardFault: -1
13
14
Make these changes, including support for changing the
15
priority of Secure HardFault as AIRCR.BFHFNMINS changes.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 1505240046-11454-14-git-send-email-peter.maydell@linaro.org
20
---
21
hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++---
22
1 file changed, 19 insertions(+), 3 deletions(-)
23
24
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/intc/armv7m_nvic.c
27
+++ b/hw/intc/armv7m_nvic.c
28
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
29
(R_V7M_AIRCR_SYSRESETREQS_MASK |
30
R_V7M_AIRCR_BFHFNMINS_MASK |
31
R_V7M_AIRCR_PRIS_MASK);
32
+ /* BFHFNMINS changes the priority of Secure HardFault */
33
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
34
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
35
+ } else {
36
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
37
+ }
38
}
39
nvic_irq_update(s);
40
}
41
@@ -XXX,XX +XXX,XX @@ static int nvic_post_load(void *opaque, int version_id)
42
{
43
NVICState *s = opaque;
44
unsigned i;
45
+ int resetprio;
46
47
/* Check for out of range priority settings */
48
- if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
49
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
50
+
51
+ if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
52
s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
53
s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
54
return 1;
55
@@ -XXX,XX +XXX,XX @@ static int nvic_security_post_load(void *opaque, int version_id)
56
int i;
57
58
/* Check for out of range priority settings */
59
- if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
60
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
61
+ && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
62
+ /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
63
+ * if the CPU state has been migrated yet; a mismatch won't
64
+ * cause the emulation to blow up, though.
65
+ */
66
return 1;
67
}
68
for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
69
@@ -XXX,XX +XXX,XX @@ static Property props_nvic[] = {
70
71
static void armv7m_nvic_reset(DeviceState *dev)
72
{
73
+ int resetprio;
74
NVICState *s = NVIC(dev);
75
76
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
77
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
78
s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
79
s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
80
81
- s->vectors[ARMV7M_EXCP_RESET].prio = -3;
82
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
83
+ s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
84
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
85
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
86
87
--
88
2.7.4
89
90
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/31] msf2: Add Smartfusion2 System timer
Deleted patch
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
2
1
3
Modelled System Timer in Microsemi's Smartfusion2 Soc.
4
Timer has two 32bit down counters and two interrupts.
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20170920201737.25723-2-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/timer/Makefile.objs | 1 +
14
include/hw/timer/mss-timer.h | 64 ++++++++++
15
hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++
16
3 files changed, 354 insertions(+)
17
create mode 100644 include/hw/timer/mss-timer.h
18
create mode 100644 hw/timer/mss-timer.c
19
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
23
+++ b/hw/timer/Makefile.objs
24
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
25
26
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
27
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
28
+common-obj-$(CONFIG_MSF2) += mss-timer.o
29
diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
30
new file mode 100644
31
index XXXXXXX..XXXXXXX
32
--- /dev/null
33
+++ b/include/hw/timer/mss-timer.h
34
@@ -XXX,XX +XXX,XX @@
35
+/*
36
+ * Microsemi SmartFusion2 Timer.
37
+ *
38
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
39
+ *
40
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
41
+ * of this software and associated documentation files (the "Software"), to deal
42
+ * in the Software without restriction, including without limitation the rights
43
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
44
+ * copies of the Software, and to permit persons to whom the Software is
45
+ * furnished to do so, subject to the following conditions:
46
+ *
47
+ * The above copyright notice and this permission notice shall be included in
48
+ * all copies or substantial portions of the Software.
49
+ *
50
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
51
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
52
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
53
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
54
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
55
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
56
+ * THE SOFTWARE.
57
+ */
58
+
59
+#ifndef HW_MSS_TIMER_H
60
+#define HW_MSS_TIMER_H
61
+
62
+#include "hw/sysbus.h"
63
+#include "hw/ptimer.h"
64
+
65
+#define TYPE_MSS_TIMER "mss-timer"
66
+#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \
67
+ (obj), TYPE_MSS_TIMER)
68
+
69
+/*
70
+ * There are two 32-bit down counting timers.
71
+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer
72
+ * that operates either in Periodic mode or in One-shot mode.
73
+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
74
+ * In 64-bit mode, writing to the 32-bit registers has no effect.
75
+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers
76
+ * has no effect. Only two 32-bit timers are supported currently.
77
+ */
78
+#define NUM_TIMERS 2
79
+
80
+#define R_TIM1_MAX 6
81
+
82
+struct Msf2Timer {
83
+ QEMUBH *bh;
84
+ ptimer_state *ptimer;
85
+
86
+ uint32_t regs[R_TIM1_MAX];
87
+ qemu_irq irq;
88
+};
89
+
90
+typedef struct MSSTimerState {
91
+ SysBusDevice parent_obj;
92
+
93
+ MemoryRegion mmio;
94
+ uint32_t freq_hz;
95
+ struct Msf2Timer timers[NUM_TIMERS];
96
+} MSSTimerState;
97
+
98
+#endif /* HW_MSS_TIMER_H */
99
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
100
new file mode 100644
101
index XXXXXXX..XXXXXXX
102
--- /dev/null
103
+++ b/hw/timer/mss-timer.c
104
@@ -XXX,XX +XXX,XX @@
105
+/*
106
+ * Block model of System timer present in
107
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
108
+ *
109
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
110
+ *
111
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
112
+ * of this software and associated documentation files (the "Software"), to deal
113
+ * in the Software without restriction, including without limitation the rights
114
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
115
+ * copies of the Software, and to permit persons to whom the Software is
116
+ * furnished to do so, subject to the following conditions:
117
+ *
118
+ * The above copyright notice and this permission notice shall be included in
119
+ * all copies or substantial portions of the Software.
120
+ *
121
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
122
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
123
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
124
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
125
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
126
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
127
+ * THE SOFTWARE.
128
+ */
129
+
130
+#include "qemu/osdep.h"
131
+#include "qemu/main-loop.h"
132
+#include "qemu/log.h"
133
+#include "hw/timer/mss-timer.h"
134
+
135
+#ifndef MSS_TIMER_ERR_DEBUG
136
+#define MSS_TIMER_ERR_DEBUG 0
137
+#endif
138
+
139
+#define DB_PRINT_L(lvl, fmt, args...) do { \
140
+ if (MSS_TIMER_ERR_DEBUG >= lvl) { \
141
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
142
+ } \
143
+} while (0);
144
+
145
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
146
+
147
+#define R_TIM_VAL 0
148
+#define R_TIM_LOADVAL 1
149
+#define R_TIM_BGLOADVAL 2
150
+#define R_TIM_CTRL 3
151
+#define R_TIM_RIS 4
152
+#define R_TIM_MIS 5
153
+
154
+#define TIMER_CTRL_ENBL (1 << 0)
155
+#define TIMER_CTRL_ONESHOT (1 << 1)
156
+#define TIMER_CTRL_INTR (1 << 2)
157
+#define TIMER_RIS_ACK (1 << 0)
158
+#define TIMER_RST_CLR (1 << 6)
159
+#define TIMER_MODE (1 << 0)
160
+
161
+static void timer_update_irq(struct Msf2Timer *st)
162
+{
163
+ bool isr, ier;
164
+
165
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
166
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
167
+ qemu_set_irq(st->irq, (ier && isr));
168
+}
169
+
170
+static void timer_update(struct Msf2Timer *st)
171
+{
172
+ uint64_t count;
173
+
174
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
175
+ ptimer_stop(st->ptimer);
176
+ return;
177
+ }
178
+
179
+ count = st->regs[R_TIM_LOADVAL];
180
+ ptimer_set_limit(st->ptimer, count, 1);
181
+ ptimer_run(st->ptimer, 1);
182
+}
183
+
184
+static uint64_t
185
+timer_read(void *opaque, hwaddr offset, unsigned int size)
186
+{
187
+ MSSTimerState *t = opaque;
188
+ hwaddr addr;
189
+ struct Msf2Timer *st;
190
+ uint32_t ret = 0;
191
+ int timer = 0;
192
+ int isr;
193
+ int ier;
194
+
195
+ addr = offset >> 2;
196
+ /*
197
+ * Two independent timers has same base address.
198
+ * Based on address passed figure out which timer is being used.
199
+ */
200
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
201
+ timer = 1;
202
+ addr -= R_TIM1_MAX;
203
+ }
204
+
205
+ st = &t->timers[timer];
206
+
207
+ switch (addr) {
208
+ case R_TIM_VAL:
209
+ ret = ptimer_get_count(st->ptimer);
210
+ break;
211
+
212
+ case R_TIM_MIS:
213
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
214
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
215
+ ret = ier & isr;
216
+ break;
217
+
218
+ default:
219
+ if (addr < R_TIM1_MAX) {
220
+ ret = st->regs[addr];
221
+ } else {
222
+ qemu_log_mask(LOG_GUEST_ERROR,
223
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
224
+ return ret;
225
+ }
226
+ break;
227
+ }
228
+
229
+ DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset,
230
+ ret);
231
+ return ret;
232
+}
233
+
234
+static void
235
+timer_write(void *opaque, hwaddr offset,
236
+ uint64_t val64, unsigned int size)
237
+{
238
+ MSSTimerState *t = opaque;
239
+ hwaddr addr;
240
+ struct Msf2Timer *st;
241
+ int timer = 0;
242
+ uint32_t value = val64;
243
+
244
+ addr = offset >> 2;
245
+ /*
246
+ * Two independent timers has same base address.
247
+ * Based on addr passed figure out which timer is being used.
248
+ */
249
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
250
+ timer = 1;
251
+ addr -= R_TIM1_MAX;
252
+ }
253
+
254
+ st = &t->timers[timer];
255
+
256
+ DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
257
+ value, timer);
258
+
259
+ switch (addr) {
260
+ case R_TIM_CTRL:
261
+ st->regs[R_TIM_CTRL] = value;
262
+ timer_update(st);
263
+ break;
264
+
265
+ case R_TIM_RIS:
266
+ if (value & TIMER_RIS_ACK) {
267
+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
268
+ }
269
+ break;
270
+
271
+ case R_TIM_LOADVAL:
272
+ st->regs[R_TIM_LOADVAL] = value;
273
+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
274
+ timer_update(st);
275
+ }
276
+ break;
277
+
278
+ case R_TIM_BGLOADVAL:
279
+ st->regs[R_TIM_BGLOADVAL] = value;
280
+ st->regs[R_TIM_LOADVAL] = value;
281
+ break;
282
+
283
+ case R_TIM_VAL:
284
+ case R_TIM_MIS:
285
+ break;
286
+
287
+ default:
288
+ if (addr < R_TIM1_MAX) {
289
+ st->regs[addr] = value;
290
+ } else {
291
+ qemu_log_mask(LOG_GUEST_ERROR,
292
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
293
+ return;
294
+ }
295
+ break;
296
+ }
297
+ timer_update_irq(st);
298
+}
299
+
300
+static const MemoryRegionOps timer_ops = {
301
+ .read = timer_read,
302
+ .write = timer_write,
303
+ .endianness = DEVICE_NATIVE_ENDIAN,
304
+ .valid = {
305
+ .min_access_size = 1,
306
+ .max_access_size = 4
307
+ }
308
+};
309
+
310
+static void timer_hit(void *opaque)
311
+{
312
+ struct Msf2Timer *st = opaque;
313
+
314
+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
315
+
316
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
317
+ timer_update(st);
318
+ }
319
+ timer_update_irq(st);
320
+}
321
+
322
+static void mss_timer_init(Object *obj)
323
+{
324
+ MSSTimerState *t = MSS_TIMER(obj);
325
+ int i;
326
+
327
+ /* Init all the ptimers. */
328
+ for (i = 0; i < NUM_TIMERS; i++) {
329
+ struct Msf2Timer *st = &t->timers[i];
330
+
331
+ st->bh = qemu_bh_new(timer_hit, st);
332
+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
333
+ ptimer_set_freq(st->ptimer, t->freq_hz);
334
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
335
+ }
336
+
337
+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
338
+ NUM_TIMERS * R_TIM1_MAX * 4);
339
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
340
+}
341
+
342
+static const VMStateDescription vmstate_timers = {
343
+ .name = "mss-timer-block",
344
+ .version_id = 1,
345
+ .minimum_version_id = 1,
346
+ .fields = (VMStateField[]) {
347
+ VMSTATE_PTIMER(ptimer, struct Msf2Timer),
348
+ VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),
349
+ VMSTATE_END_OF_LIST()
350
+ }
351
+};
352
+
353
+static const VMStateDescription vmstate_mss_timer = {
354
+ .name = TYPE_MSS_TIMER,
355
+ .version_id = 1,
356
+ .minimum_version_id = 1,
357
+ .fields = (VMStateField[]) {
358
+ VMSTATE_UINT32(freq_hz, MSSTimerState),
359
+ VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
360
+ vmstate_timers, struct Msf2Timer),
361
+ VMSTATE_END_OF_LIST()
362
+ }
363
+};
364
+
365
+static Property mss_timer_properties[] = {
366
+ /* Libero GUI shows 100Mhz as default for clocks */
367
+ DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
368
+ 100 * 1000000),
369
+ DEFINE_PROP_END_OF_LIST(),
370
+};
371
+
372
+static void mss_timer_class_init(ObjectClass *klass, void *data)
373
+{
374
+ DeviceClass *dc = DEVICE_CLASS(klass);
375
+
376
+ dc->props = mss_timer_properties;
377
+ dc->vmsd = &vmstate_mss_timer;
378
+}
379
+
380
+static const TypeInfo mss_timer_info = {
381
+ .name = TYPE_MSS_TIMER,
382
+ .parent = TYPE_SYS_BUS_DEVICE,
383
+ .instance_size = sizeof(MSSTimerState),
384
+ .instance_init = mss_timer_init,
385
+ .class_init = mss_timer_class_init,
386
+};
387
+
388
+static void mss_timer_register_types(void)
389
+{
390
+ type_register_static(&mss_timer_info);
391
+}
392
+
393
+type_init(mss_timer_register_types)
394
--
395
2.7.4
396
397
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/31] msf2: Microsemi Smartfusion2 System Register block
Deleted patch
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
2
1
3
Added Sytem register block of Smartfusion2.
4
This block has PLL registers which are accessed by guest.
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20170920201737.25723-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/misc/Makefile.objs | 1 +
14
include/hw/misc/msf2-sysreg.h | 77 ++++++++++++++++++++
15
hw/misc/msf2-sysreg.c | 160 ++++++++++++++++++++++++++++++++++++++++++
16
hw/misc/trace-events | 5 ++
17
4 files changed, 243 insertions(+)
18
create mode 100644 include/hw/misc/msf2-sysreg.h
19
create mode 100644 hw/misc/msf2-sysreg.c
20
21
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/misc/Makefile.objs
24
+++ b/hw/misc/Makefile.objs
25
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
26
obj-$(CONFIG_AUX) += auxbus.o
27
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
28
obj-y += mmio_interface.o
29
+obj-$(CONFIG_MSF2) += msf2-sysreg.o
30
diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
31
new file mode 100644
32
index XXXXXXX..XXXXXXX
33
--- /dev/null
34
+++ b/include/hw/misc/msf2-sysreg.h
35
@@ -XXX,XX +XXX,XX @@
36
+/*
37
+ * Microsemi SmartFusion2 SYSREG
38
+ *
39
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
40
+ *
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
42
+ * of this software and associated documentation files (the "Software"), to deal
43
+ * in the Software without restriction, including without limitation the rights
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
45
+ * copies of the Software, and to permit persons to whom the Software is
46
+ * furnished to do so, subject to the following conditions:
47
+ *
48
+ * The above copyright notice and this permission notice shall be included in
49
+ * all copies or substantial portions of the Software.
50
+ *
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
57
+ * THE SOFTWARE.
58
+ */
59
+
60
+#ifndef HW_MSF2_SYSREG_H
61
+#define HW_MSF2_SYSREG_H
62
+
63
+#include "hw/sysbus.h"
64
+
65
+enum {
66
+ ESRAM_CR = 0x00 / 4,
67
+ ESRAM_MAX_LAT,
68
+ DDR_CR,
69
+ ENVM_CR,
70
+ ENVM_REMAP_BASE_CR,
71
+ ENVM_REMAP_FAB_CR,
72
+ CC_CR,
73
+ CC_REGION_CR,
74
+ CC_LOCK_BASE_ADDR_CR,
75
+ CC_FLUSH_INDX_CR,
76
+ DDRB_BUF_TIMER_CR,
77
+ DDRB_NB_ADDR_CR,
78
+ DDRB_NB_SIZE_CR,
79
+ DDRB_CR,
80
+
81
+ SOFT_RESET_CR = 0x48 / 4,
82
+ M3_CR,
83
+
84
+ GPIO_SYSRESET_SEL_CR = 0x58 / 4,
85
+
86
+ MDDR_CR = 0x60 / 4,
87
+
88
+ MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
89
+ MSSDDR_PLL_STATUS_HIGH_CR,
90
+ MSSDDR_FACC1_CR,
91
+ MSSDDR_FACC2_CR,
92
+
93
+ MSSDDR_PLL_STATUS = 0x150 / 4,
94
+};
95
+
96
+#define MSF2_SYSREG_MMIO_SIZE 0x300
97
+
98
+#define TYPE_MSF2_SYSREG "msf2-sysreg"
99
+#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
100
+
101
+typedef struct MSF2SysregState {
102
+ SysBusDevice parent_obj;
103
+
104
+ MemoryRegion iomem;
105
+
106
+ uint8_t apb0div;
107
+ uint8_t apb1div;
108
+
109
+ uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
110
+} MSF2SysregState;
111
+
112
+#endif /* HW_MSF2_SYSREG_H */
113
diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
114
new file mode 100644
115
index XXXXXXX..XXXXXXX
116
--- /dev/null
117
+++ b/hw/misc/msf2-sysreg.c
118
@@ -XXX,XX +XXX,XX @@
119
+/*
120
+ * System Register block model of Microsemi SmartFusion2.
121
+ *
122
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
123
+ *
124
+ * This program is free software; you can redistribute it and/or
125
+ * modify it under the terms of the GNU General Public License
126
+ * as published by the Free Software Foundation; either version
127
+ * 2 of the License, or (at your option) any later version.
128
+ *
129
+ * You should have received a copy of the GNU General Public License along
130
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
131
+ */
132
+
133
+#include "qemu/osdep.h"
134
+#include "qapi/error.h"
135
+#include "qemu/log.h"
136
+#include "hw/misc/msf2-sysreg.h"
137
+#include "qemu/error-report.h"
138
+#include "trace.h"
139
+
140
+static inline int msf2_divbits(uint32_t div)
141
+{
142
+ int r = ctz32(div);
143
+
144
+ return (div < 8) ? r : r + 1;
145
+}
146
+
147
+static void msf2_sysreg_reset(DeviceState *d)
148
+{
149
+ MSF2SysregState *s = MSF2_SYSREG(d);
150
+
151
+ s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
152
+ s->regs[MSSDDR_PLL_STATUS] = 0x3;
153
+ s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
154
+ msf2_divbits(s->apb1div) << 2;
155
+}
156
+
157
+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
158
+ unsigned size)
159
+{
160
+ MSF2SysregState *s = opaque;
161
+ uint32_t ret = 0;
162
+
163
+ offset >>= 2;
164
+ if (offset < ARRAY_SIZE(s->regs)) {
165
+ ret = s->regs[offset];
166
+ trace_msf2_sysreg_read(offset << 2, ret);
167
+ } else {
168
+ qemu_log_mask(LOG_GUEST_ERROR,
169
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
170
+ offset << 2);
171
+ }
172
+
173
+ return ret;
174
+}
175
+
176
+static void msf2_sysreg_write(void *opaque, hwaddr offset,
177
+ uint64_t val, unsigned size)
178
+{
179
+ MSF2SysregState *s = opaque;
180
+ uint32_t newval = val;
181
+
182
+ offset >>= 2;
183
+
184
+ switch (offset) {
185
+ case MSSDDR_PLL_STATUS:
186
+ trace_msf2_sysreg_write_pll_status();
187
+ break;
188
+
189
+ case ESRAM_CR:
190
+ case DDR_CR:
191
+ case ENVM_REMAP_BASE_CR:
192
+ if (newval != s->regs[offset]) {
193
+ qemu_log_mask(LOG_UNIMP,
194
+ TYPE_MSF2_SYSREG": remapping not supported\n");
195
+ }
196
+ break;
197
+
198
+ default:
199
+ if (offset < ARRAY_SIZE(s->regs)) {
200
+ trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);
201
+ s->regs[offset] = newval;
202
+ } else {
203
+ qemu_log_mask(LOG_GUEST_ERROR,
204
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
205
+ offset << 2);
206
+ }
207
+ break;
208
+ }
209
+}
210
+
211
+static const MemoryRegionOps sysreg_ops = {
212
+ .read = msf2_sysreg_read,
213
+ .write = msf2_sysreg_write,
214
+ .endianness = DEVICE_NATIVE_ENDIAN,
215
+};
216
+
217
+static void msf2_sysreg_init(Object *obj)
218
+{
219
+ MSF2SysregState *s = MSF2_SYSREG(obj);
220
+
221
+ memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
222
+ MSF2_SYSREG_MMIO_SIZE);
223
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
224
+}
225
+
226
+static const VMStateDescription vmstate_msf2_sysreg = {
227
+ .name = TYPE_MSF2_SYSREG,
228
+ .version_id = 1,
229
+ .minimum_version_id = 1,
230
+ .fields = (VMStateField[]) {
231
+ VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
+static Property msf2_sysreg_properties[] = {
237
+ /* default divisors in Libero GUI */
238
+ DEFINE_PROP_UINT8("apb0divisor", MSF2SysregState, apb0div, 2),
239
+ DEFINE_PROP_UINT8("apb1divisor", MSF2SysregState, apb1div, 2),
240
+ DEFINE_PROP_END_OF_LIST(),
241
+};
242
+
243
+static void msf2_sysreg_realize(DeviceState *dev, Error **errp)
244
+{
245
+ MSF2SysregState *s = MSF2_SYSREG(dev);
246
+
247
+ if ((s->apb0div > 32 || !is_power_of_2(s->apb0div))
248
+ || (s->apb1div > 32 || !is_power_of_2(s->apb1div))) {
249
+ error_setg(errp, "Invalid apb divisor value");
250
+ error_append_hint(errp, "apb divisor must be a power of 2"
251
+ " and maximum value is 32\n");
252
+ }
253
+}
254
+
255
+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
256
+{
257
+ DeviceClass *dc = DEVICE_CLASS(klass);
258
+
259
+ dc->vmsd = &vmstate_msf2_sysreg;
260
+ dc->reset = msf2_sysreg_reset;
261
+ dc->props = msf2_sysreg_properties;
262
+ dc->realize = msf2_sysreg_realize;
263
+}
264
+
265
+static const TypeInfo msf2_sysreg_info = {
266
+ .name = TYPE_MSF2_SYSREG,
267
+ .parent = TYPE_SYS_BUS_DEVICE,
268
+ .class_init = msf2_sysreg_class_init,
269
+ .instance_size = sizeof(MSF2SysregState),
270
+ .instance_init = msf2_sysreg_init,
271
+};
272
+
273
+static void msf2_sysreg_register_types(void)
274
+{
275
+ type_register_static(&msf2_sysreg_info);
276
+}
277
+
278
+type_init(msf2_sysreg_register_types)
279
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
280
index XXXXXXX..XXXXXXX 100644
281
--- a/hw/misc/trace-events
282
+++ b/hw/misc/trace-events
283
@@ -XXX,XX +XXX,XX @@ mps2_scc_reset(void) "MPS2 SCC: reset"
284
mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) "MPS2 SCC LEDs: %c%c%c%c%c%c%c%c"
285
mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
286
mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
287
+
288
+# hw/misc/msf2-sysreg.c
289
+msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
290
+msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
291
+msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
292
--
293
2.7.4
294
295
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/31] msf2: Add Smartfusion2 SoC
Deleted patch
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
2
1
3
Smartfusion2 SoC has hardened Microcontroller subsystem
4
and flash based FPGA fabric. This patch adds support for
5
Microcontroller subsystem in the SoC.
6
7
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20170920201737.25723-5-f4bug@amsat.org
11
[PMD: drop cpu_model to directly use cpu type, check m3clk non null]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/Makefile.objs | 1 +
15
include/hw/arm/msf2-soc.h | 67 +++++++++++
16
hw/arm/msf2-soc.c | 238 ++++++++++++++++++++++++++++++++++++++++
17
default-configs/arm-softmmu.mak | 1 +
18
4 files changed, 307 insertions(+)
19
create mode 100644 include/hw/arm/msf2-soc.h
20
create mode 100644 hw/arm/msf2-soc.c
21
22
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/Makefile.objs
25
+++ b/hw/arm/Makefile.objs
26
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
27
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
28
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
29
obj-$(CONFIG_MPS2) += mps2.o
30
+obj-$(CONFIG_MSF2) += msf2-soc.o
31
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
32
new file mode 100644
33
index XXXXXXX..XXXXXXX
34
--- /dev/null
35
+++ b/include/hw/arm/msf2-soc.h
36
@@ -XXX,XX +XXX,XX @@
37
+/*
38
+ * Microsemi Smartfusion2 SoC
39
+ *
40
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
41
+ *
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
43
+ * of this software and associated documentation files (the "Software"), to deal
44
+ * in the Software without restriction, including without limitation the rights
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
49
+ * The above copyright notice and this permission notice shall be included in
50
+ * all copies or substantial portions of the Software.
51
+ *
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
60
+
61
+#ifndef HW_ARM_MSF2_SOC_H
62
+#define HW_ARM_MSF2_SOC_H
63
+
64
+#include "hw/arm/armv7m.h"
65
+#include "hw/timer/mss-timer.h"
66
+#include "hw/misc/msf2-sysreg.h"
67
+#include "hw/ssi/mss-spi.h"
68
+
69
+#define TYPE_MSF2_SOC "msf2-soc"
70
+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
71
+
72
+#define MSF2_NUM_SPIS 2
73
+#define MSF2_NUM_UARTS 2
74
+
75
+/*
76
+ * System timer consists of two programmable 32-bit
77
+ * decrementing counters that generate individual interrupts to
78
+ * the Cortex-M3 processor
79
+ */
80
+#define MSF2_NUM_TIMERS 2
81
+
82
+typedef struct MSF2State {
83
+ /*< private >*/
84
+ SysBusDevice parent_obj;
85
+ /*< public >*/
86
+
87
+ ARMv7MState armv7m;
88
+
89
+ char *cpu_type;
90
+ char *part_name;
91
+ uint64_t envm_size;
92
+ uint64_t esram_size;
93
+
94
+ uint32_t m3clk;
95
+ uint8_t apb0div;
96
+ uint8_t apb1div;
97
+
98
+ MSF2SysregState sysreg;
99
+ MSSTimerState timer;
100
+ MSSSpiState spi[MSF2_NUM_SPIS];
101
+} MSF2State;
102
+
103
+#endif
104
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
105
new file mode 100644
106
index XXXXXXX..XXXXXXX
107
--- /dev/null
108
+++ b/hw/arm/msf2-soc.c
109
@@ -XXX,XX +XXX,XX @@
110
+/*
111
+ * SmartFusion2 SoC emulation.
112
+ *
113
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
114
+ *
115
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
116
+ * of this software and associated documentation files (the "Software"), to deal
117
+ * in the Software without restriction, including without limitation the rights
118
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
119
+ * copies of the Software, and to permit persons to whom the Software is
120
+ * furnished to do so, subject to the following conditions:
121
+ *
122
+ * The above copyright notice and this permission notice shall be included in
123
+ * all copies or substantial portions of the Software.
124
+ *
125
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
126
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
127
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
128
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
129
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
130
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
131
+ * THE SOFTWARE.
132
+ */
133
+
134
+#include "qemu/osdep.h"
135
+#include "qapi/error.h"
136
+#include "qemu-common.h"
137
+#include "hw/arm/arm.h"
138
+#include "exec/address-spaces.h"
139
+#include "hw/char/serial.h"
140
+#include "hw/boards.h"
141
+#include "sysemu/block-backend.h"
142
+#include "qemu/cutils.h"
143
+#include "hw/arm/msf2-soc.h"
144
+#include "hw/misc/unimp.h"
145
+
146
+#define MSF2_TIMER_BASE 0x40004000
147
+#define MSF2_SYSREG_BASE 0x40038000
148
+
149
+#define ENVM_BASE_ADDRESS 0x60000000
150
+
151
+#define SRAM_BASE_ADDRESS 0x20000000
152
+
153
+#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
154
+
155
+/*
156
+ * eSRAM max size is 80k without SECDED(Single error correction and
157
+ * dual error detection) feature and 64k with SECDED.
158
+ * We do not support SECDED now.
159
+ */
160
+#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
161
+
162
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
163
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
164
+
165
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
166
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
167
+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
168
+
169
+static void m2sxxx_soc_initfn(Object *obj)
170
+{
171
+ MSF2State *s = MSF2_SOC(obj);
172
+ int i;
173
+
174
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
175
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
176
+
177
+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
178
+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
179
+
180
+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
181
+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
182
+
183
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
184
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
185
+ TYPE_MSS_SPI);
186
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
187
+ }
188
+}
189
+
190
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
191
+{
192
+ MSF2State *s = MSF2_SOC(dev_soc);
193
+ DeviceState *dev, *armv7m;
194
+ SysBusDevice *busdev;
195
+ Error *err = NULL;
196
+ int i;
197
+
198
+ MemoryRegion *system_memory = get_system_memory();
199
+ MemoryRegion *nvm = g_new(MemoryRegion, 1);
200
+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
201
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
202
+
203
+ memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
204
+ &error_fatal);
205
+ /*
206
+ * On power-on, the eNVM region 0x60000000 is automatically
207
+ * remapped to the Cortex-M3 processor executable region
208
+ * start address (0x0). We do not support remapping other eNVM,
209
+ * eSRAM and DDR regions by guest(via Sysreg) currently.
210
+ */
211
+ memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
212
+ nvm, 0, s->envm_size);
213
+
214
+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
215
+ memory_region_add_subregion(system_memory, 0, nvm_alias);
216
+
217
+ memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
218
+ &error_fatal);
219
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
220
+
221
+ armv7m = DEVICE(&s->armv7m);
222
+ qdev_prop_set_uint32(armv7m, "num-irq", 81);
223
+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
224
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
225
+ "memory", &error_abort);
226
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
227
+ if (err != NULL) {
228
+ error_propagate(errp, err);
229
+ return;
230
+ }
231
+
232
+ if (!s->m3clk) {
233
+ error_setg(errp, "Invalid m3clk value");
234
+ error_append_hint(errp, "m3clk can not be zero\n");
235
+ return;
236
+ }
237
+ system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
238
+
239
+ for (i = 0; i < MSF2_NUM_UARTS; i++) {
240
+ if (serial_hds[i]) {
241
+ serial_mm_init(get_system_memory(), uart_addr[i], 2,
242
+ qdev_get_gpio_in(armv7m, uart_irq[i]),
243
+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
244
+ }
245
+ }
246
+
247
+ dev = DEVICE(&s->timer);
248
+ /* APB0 clock is the timer input clock */
249
+ qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
250
+ object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
251
+ if (err != NULL) {
252
+ error_propagate(errp, err);
253
+ return;
254
+ }
255
+ busdev = SYS_BUS_DEVICE(dev);
256
+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
257
+ sysbus_connect_irq(busdev, 0,
258
+ qdev_get_gpio_in(armv7m, timer_irq[0]));
259
+ sysbus_connect_irq(busdev, 1,
260
+ qdev_get_gpio_in(armv7m, timer_irq[1]));
261
+
262
+ dev = DEVICE(&s->sysreg);
263
+ qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
264
+ qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
265
+ object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
266
+ if (err != NULL) {
267
+ error_propagate(errp, err);
268
+ return;
269
+ }
270
+ busdev = SYS_BUS_DEVICE(dev);
271
+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
272
+
273
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
274
+ gchar *bus_name;
275
+
276
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
277
+ if (err != NULL) {
278
+ error_propagate(errp, err);
279
+ return;
280
+ }
281
+
282
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
283
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
284
+ qdev_get_gpio_in(armv7m, spi_irq[i]));
285
+
286
+ /* Alias controller SPI bus to the SoC itself */
287
+ bus_name = g_strdup_printf("spi%d", i);
288
+ object_property_add_alias(OBJECT(s), bus_name,
289
+ OBJECT(&s->spi[i]), "spi",
290
+ &error_abort);
291
+ g_free(bus_name);
292
+ }
293
+
294
+ /* Below devices are not modelled yet. */
295
+ create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
296
+ create_unimplemented_device("dma", 0x40003000, 0x1000);
297
+ create_unimplemented_device("watchdog", 0x40005000, 0x1000);
298
+ create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
299
+ create_unimplemented_device("gpio", 0x40013000, 0x1000);
300
+ create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
301
+ create_unimplemented_device("can", 0x40015000, 0x1000);
302
+ create_unimplemented_device("rtc", 0x40017000, 0x1000);
303
+ create_unimplemented_device("apb_config", 0x40020000, 0x10000);
304
+ create_unimplemented_device("emac", 0x40041000, 0x1000);
305
+ create_unimplemented_device("usb", 0x40043000, 0x1000);
306
+}
307
+
308
+static Property m2sxxx_soc_properties[] = {
309
+ /*
310
+ * part name specifies the type of SmartFusion2 device variant(this
311
+ * property is for information purpose only.
312
+ */
313
+ DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
314
+ DEFINE_PROP_STRING("part-name", MSF2State, part_name),
315
+ DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
316
+ DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
317
+ MSF2_ESRAM_MAX_SIZE),
318
+ /* Libero GUI shows 100Mhz as default for clocks */
319
+ DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
320
+ /* default divisors in Libero GUI */
321
+ DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
322
+ DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
323
+ DEFINE_PROP_END_OF_LIST(),
324
+};
325
+
326
+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
327
+{
328
+ DeviceClass *dc = DEVICE_CLASS(klass);
329
+
330
+ dc->realize = m2sxxx_soc_realize;
331
+ dc->props = m2sxxx_soc_properties;
332
+}
333
+
334
+static const TypeInfo m2sxxx_soc_info = {
335
+ .name = TYPE_MSF2_SOC,
336
+ .parent = TYPE_SYS_BUS_DEVICE,
337
+ .instance_size = sizeof(MSF2State),
338
+ .instance_init = m2sxxx_soc_initfn,
339
+ .class_init = m2sxxx_soc_class_init,
340
+};
341
+
342
+static void m2sxxx_soc_types(void)
343
+{
344
+ type_register_static(&m2sxxx_soc_info);
345
+}
346
+
347
+type_init(m2sxxx_soc_types)
348
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
349
index XXXXXXX..XXXXXXX 100644
350
--- a/default-configs/arm-softmmu.mak
351
+++ b/default-configs/arm-softmmu.mak
352
@@ -XXX,XX +XXX,XX @@ CONFIG_ACPI=y
353
CONFIG_SMBIOS=y
354
CONFIG_ASPEED_SOC=y
355
CONFIG_GPIO_KEY=y
356
+CONFIG_MSF2=y
357
--
358
2.7.4
359
360
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.