Series comparison

-[Qemu-devel] [PULL 00/31] target-arm queue
+[PULL 00/32] target-arm queue
-ARM queue: mostly patches from me, but also the Smartfusion2 board.
+target-arm queue: the big stuff here is the final part of
 rth's patches for Cortex-A76 and Neoverse-N1 support;
 also present are Gavin's NUMA series and a few other things.
 thanks
 -- PMM
-The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:
+The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
-  Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)
+  Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
-are available in the git repository at:
+are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
-for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:
+for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
-  msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)
+  hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * more preparatory work for v8M support
+ * MAINTAINERS/.mailmap: update email for Leif Lindholm
- * convert some omap devices away from old_mmio
+ * hw/arm: add version information to sbsa-ref machine DT
- * remove out of date ARM ARM section references in comments
+ * Enable new features for -cpu max:
- * add the Smartfusion2 board
+   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
    FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
  * Emulate Cortex-A76
  * Emulate Neoverse-N1
  * Fix the virt board default NUMA topology
 ----------------------------------------------------------------
-Peter Maydell (26):
+Gavin Shan (6):
-      target/arm: Implement MSR/MRS access to NS banked registers
+      qapi/machine.json: Add cluster-id
-      nvic: Add banked exception states
+      qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
-      nvic: Add cached vectpending_is_s_banked state
+      hw/arm/virt: Consider SMP configuration in CPU topology
-      nvic: Add cached vectpending_prio state
+      qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
-      nvic: Implement AIRCR changes for v8M
+      hw/arm/virt: Fix CPU's default NUMA node ID
-      nvic: Make ICSR.RETTOBASE handle banked exceptions
+      hw/acpi/aml-build: Use existing CPU topology to build PPTT table
       nvic: Implement NVIC_ITNS<n> registers
       nvic: Handle banked exceptions in nvic_recompute_state()
       nvic: Make set_pending and clear_pending take a secure parameter
       nvic: Make SHPR registers banked
       nvic: Compare group priority for escalation to HF
       nvic: In escalation to HardFault, support HF not being priority -1
       nvic: Implement v8M changes to fixed priority exceptions
       nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
       nvic: Handle v8M changes in nvic_exec_prio()
       target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
       nvic: Make ICSR banked for v8M
       nvic: Make SHCSR banked for v8M
       nvic: Support banked exceptions in acknowledge and complete
       target/arm: Remove out of date ARM ARM section references in A64 decoder
       hw/arm/palm.c: Don't use old_mmio for static_ops
       hw/gpio/omap_gpio.c: Don't use old_mmio
       hw/timer/omap_synctimer.c: Don't use old_mmio
       hw/timer/omap_gptimer: Don't use old_mmio
       hw/i2c/omap_i2c.c: Don't use old_mmio
       hw/arm/omap2.c: Don't use old_mmio
-Subbaraya Sundeep (5):
+Leif Lindholm (2):
-      msf2: Add Smartfusion2 System timer
+      MAINTAINERS/.mailmap: update email for Leif Lindholm
-      msf2: Microsemi Smartfusion2 System Register block
+      hw/arm: add versioning to sbsa-ref machine DT
       msf2: Add Smartfusion2 SPI controller
       msf2: Add Smartfusion2 SoC
       msf2: Add Emcraft's Smartfusion2 SOM kit
- hw/arm/Makefile.objs            |   1 +
+Richard Henderson (24):
- hw/misc/Makefile.objs           |   1 +
+      target/arm: Handle cpreg registration for missing EL
- hw/ssi/Makefile.objs            |   1 +
+      target/arm: Drop EL3 no EL2 fallbacks
- hw/timer/Makefile.objs          |   1 +
+      target/arm: Merge zcr reginfo
- include/hw/arm/msf2-soc.h       |  67 +++
+      target/arm: Adjust definition of CONTEXTIDR_EL2
- include/hw/intc/armv7m_nvic.h   |  33 +-
+      target/arm: Move cortex impdef sysregs to cpu_tcg.c
- include/hw/misc/msf2-sysreg.h   |  77 ++++
+      target/arm: Update qemu-system-arm -cpu max to cortex-a57
- include/hw/ssi/mss-spi.h        |  58 +++
+      target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
- include/hw/timer/mss-timer.h    |  64 +++
+      target/arm: Split out aa32_max_features
- target/arm/cpu.h                |  62 ++-
+      target/arm: Annotate arm_max_initfn with FEAT identifiers
- hw/arm/msf2-soc.c               | 238 +++++++++++
+      target/arm: Use field names for manipulating EL2 and EL3 modes
- hw/arm/msf2-som.c               | 105 +++++
+      target/arm: Enable FEAT_Debugv8p2 for -cpu max
- hw/arm/omap2.c                  |  49 ++-
+      target/arm: Enable FEAT_Debugv8p4 for -cpu max
- hw/arm/palm.c                   |  30 +-
+      target/arm: Add minimal RAS registers
- hw/gpio/omap_gpio.c             |  26 +-
+      target/arm: Enable SCR and HCR bits for RAS
- hw/i2c/omap_i2c.c               |  44 +-
+      target/arm: Implement virtual SError exceptions
- hw/intc/armv7m_nvic.c           | 913 ++++++++++++++++++++++++++++++++++------
+      target/arm: Implement ESB instruction
- hw/misc/msf2-sysreg.c           | 160 +++++++
+      target/arm: Enable FEAT_RAS for -cpu max
- hw/ssi/mss-spi.c                | 404 ++++++++++++++++++
+      target/arm: Enable FEAT_IESB for -cpu max
- hw/timer/mss-timer.c            | 289 +++++++++++++
+      target/arm: Enable FEAT_CSV2 for -cpu max
- hw/timer/omap_gptimer.c         |  49 ++-
+      target/arm: Enable FEAT_CSV2_2 for -cpu max
- hw/timer/omap_synctimer.c       |  35 +-
+      target/arm: Enable FEAT_CSV3 for -cpu max
- target/arm/cpu.c                |   7 +
+      target/arm: Enable FEAT_DGH for -cpu max
- target/arm/helper.c             | 142 ++++++-
+      target/arm: Define cortex-a76
- target/arm/translate-a64.c      | 227 +++++-----
+      target/arm: Define neoverse-n1
  default-configs/arm-softmmu.mak |   1 +
  hw/intc/trace-events            |  13 +-
  hw/misc/trace-events            |   5 +
 files changed, 2735 insertions(+), 367 deletions(-)
  create mode 100644 include/hw/arm/msf2-soc.h
  create mode 100644 include/hw/misc/msf2-sysreg.h
  create mode 100644 include/hw/ssi/mss-spi.h
  create mode 100644 include/hw/timer/mss-timer.h
  create mode 100644 hw/arm/msf2-soc.c
  create mode 100644 hw/arm/msf2-som.c
  create mode 100644 hw/misc/msf2-sysreg.c
  create mode 100644 hw/ssi/mss-spi.c
  create mode 100644 hw/timer/mss-timer.c
+ docs/system/arm/emulation.rst |  10 +
+ docs/system/arm/virt.rst      |   2 +
+ qapi/machine.json             |   6 +-
+ target/arm/cpregs.h           |  11 +
+ target/arm/cpu.h              |  23 ++
+ target/arm/helper.h           |   1 +
+ target/arm/internals.h        |  16 ++
+ target/arm/syndrome.h         |   5 +
+ target/arm/a32.decode         |  16 +-
+ target/arm/t32.decode         |  18 +-
+ hw/acpi/aml-build.c           | 111 ++++----
+ hw/arm/sbsa-ref.c             |  16 ++
+ hw/arm/virt.c                 |  21 +-
+ hw/core/machine-hmp-cmds.c    |   4 +
+ hw/core/machine.c             |  16 ++
+ target/arm/cpu.c              |  66 ++++-
+ target/arm/cpu64.c            | 353 ++++++++++++++-----------
+ target/arm/cpu_tcg.c          | 227 +++++++++++-----
+ target/arm/helper.c           | 600 +++++++++++++++++++++++++-----------------
+ target/arm/op_helper.c        |  43 +++
+ target/arm/translate-a64.c    |  18 ++
+ target/arm/translate.c        |  23 ++
+ tests/qtest/numa-test.c       |  19 +-
+ .mailmap                      |   3 +-
+ MAINTAINERS                   |   2 +-
+files changed, 1068 insertions(+), 562 deletions(-)

-[Qemu-devel] [PULL 28/31] msf2: Microsemi Smartfusion2 System Register block
+[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
-From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+From: Leif Lindholm <quic_llindhol@quicinc.com>
-Added Sytem register block of Smartfusion2.
+NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
-This block has PLL registers which are accessed by guest.
+separate infrastructure for a transitional period. We've now switched
 over to contributing as Qualcomm Innovation Center (quicinc), so update
 my email address to reflect this.
-Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
-Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Cc: Leif Lindholm <leif@nuviainc.com>
-Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Cc: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20170920201737.25723-3-f4bug@amsat.org
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 [Fixed commit message typo]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/misc/Makefile.objs         |   1 +
+ .mailmap    | 3 ++-
- include/hw/misc/msf2-sysreg.h |  77 ++++++++++++++++++++
+ MAINTAINERS | 2 +-
- hw/misc/msf2-sysreg.c         | 160 ++++++++++++++++++++++++++++++++++++++++++
+files changed, 3 insertions(+), 2 deletions(-)
  hw/misc/trace-events          |   5 ++
 files changed, 243 insertions(+)
  create mode 100644 include/hw/misc/msf2-sysreg.h
  create mode 100644 hw/misc/msf2-sysreg.c
-diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
+diff --git a/.mailmap b/.mailmap
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Makefile.objs
+--- a/.mailmap
-+++ b/hw/misc/Makefile.objs
++++ b/.mailmap
-@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
+@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
- obj-$(CONFIG_AUX) += auxbus.o
+ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
- obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
+ Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
- obj-y += mmio_interface.o
+ James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
-+obj-$(CONFIG_MSF2) += msf2-sysreg.o
+-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
-diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
++Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
-new file mode 100644
++Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
-index XXXXXXX..XXXXXXX
+ Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
---- /dev/null
+ Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
-+++ b/include/hw/misc/msf2-sysreg.h
+ Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
-@@ -XXX,XX +XXX,XX @@
+diff --git a/MAINTAINERS b/MAINTAINERS
 +/*
 + * Microsemi SmartFusion2 SYSREG
 + *
 + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_MSF2_SYSREG_H
 +#define HW_MSF2_SYSREG_H
 +
 +#include "hw/sysbus.h"
 +
 +enum {
 +    ESRAM_CR        = 0x00 / 4,
 +    ESRAM_MAX_LAT,
 +    DDR_CR,
 +    ENVM_CR,
 +    ENVM_REMAP_BASE_CR,
 +    ENVM_REMAP_FAB_CR,
 +    CC_CR,
 +    CC_REGION_CR,
 +    CC_LOCK_BASE_ADDR_CR,
 +    CC_FLUSH_INDX_CR,
 +    DDRB_BUF_TIMER_CR,
 +    DDRB_NB_ADDR_CR,
 +    DDRB_NB_SIZE_CR,
 +    DDRB_CR,
 +
 +    SOFT_RESET_CR  = 0x48 / 4,
 +    M3_CR,
 +
 +    GPIO_SYSRESET_SEL_CR = 0x58 / 4,
 +
 +    MDDR_CR = 0x60 / 4,
 +
 +    MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
 +    MSSDDR_PLL_STATUS_HIGH_CR,
 +    MSSDDR_FACC1_CR,
 +    MSSDDR_FACC2_CR,
 +
 +    MSSDDR_PLL_STATUS = 0x150 / 4,
 +};
 +
 +#define MSF2_SYSREG_MMIO_SIZE     0x300
 +
 +#define TYPE_MSF2_SYSREG          "msf2-sysreg"
 +#define MSF2_SYSREG(obj)  OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
 +
 +typedef struct MSF2SysregState {
 +    SysBusDevice parent_obj;
 +
 +    MemoryRegion iomem;
 +
 +    uint8_t apb0div;
 +    uint8_t apb1div;
 +
 +    uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
 +} MSF2SysregState;
 +
 +#endif /* HW_MSF2_SYSREG_H */
 diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/msf2-sysreg.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * System Register block model of Microsemi SmartFusion2.
 + *
 + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
 + * as published by the Free Software Foundation; either version
 + * 2 of the License, or (at your option) any later version.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "qemu/log.h"
 +#include "hw/misc/msf2-sysreg.h"
 +#include "qemu/error-report.h"
 +#include "trace.h"
 +
 +static inline int msf2_divbits(uint32_t div)
 +{
 +    int r = ctz32(div);
 +
 +    return (div < 8) ? r : r + 1;
 +}
 +
 +static void msf2_sysreg_reset(DeviceState *d)
 +{
 +    MSF2SysregState *s = MSF2_SYSREG(d);
 +
 +    s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
 +    s->regs[MSSDDR_PLL_STATUS] = 0x3;
 +    s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
 +                               msf2_divbits(s->apb1div) << 2;
 +}
 +
 +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
 +    unsigned size)
 +{
 +    MSF2SysregState *s = opaque;
 +    uint32_t ret = 0;
 +
 +    offset >>= 2;
 +    if (offset < ARRAY_SIZE(s->regs)) {
 +        ret = s->regs[offset];
 +        trace_msf2_sysreg_read(offset << 2, ret);
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                    "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
 +                    offset << 2);
 +    }
 +
 +    return ret;
 +}
 +
 +static void msf2_sysreg_write(void *opaque, hwaddr offset,
 +                          uint64_t val, unsigned size)
 +{
 +    MSF2SysregState *s = opaque;
 +    uint32_t newval = val;
 +
 +    offset >>= 2;
 +
 +    switch (offset) {
 +    case MSSDDR_PLL_STATUS:
 +        trace_msf2_sysreg_write_pll_status();
 +        break;
 +
 +    case ESRAM_CR:
 +    case DDR_CR:
 +    case ENVM_REMAP_BASE_CR:
 +        if (newval != s->regs[offset]) {
 +            qemu_log_mask(LOG_UNIMP,
 +                       TYPE_MSF2_SYSREG": remapping not supported\n");
 +        }
 +        break;
 +
 +    default:
 +        if (offset < ARRAY_SIZE(s->regs)) {
 +            trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);
 +            s->regs[offset] = newval;
 +        } else {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                        "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
 +                        offset << 2);
 +        }
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps sysreg_ops = {
 +    .read = msf2_sysreg_read,
 +    .write = msf2_sysreg_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +};
 +
 +static void msf2_sysreg_init(Object *obj)
 +{
 +    MSF2SysregState *s = MSF2_SYSREG(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
 +                          MSF2_SYSREG_MMIO_SIZE);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 +}
 +
 +static const VMStateDescription vmstate_msf2_sysreg = {
 +    .name = TYPE_MSF2_SYSREG,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static Property msf2_sysreg_properties[] = {
 +    /* default divisors in Libero GUI */
 +    DEFINE_PROP_UINT8("apb0divisor", MSF2SysregState, apb0div, 2),
 +    DEFINE_PROP_UINT8("apb1divisor", MSF2SysregState, apb1div, 2),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void msf2_sysreg_realize(DeviceState *dev, Error **errp)
 +{
 +    MSF2SysregState *s = MSF2_SYSREG(dev);
 +
 +    if ((s->apb0div > 32 || !is_power_of_2(s->apb0div))
 +        || (s->apb1div > 32 || !is_power_of_2(s->apb1div))) {
 +        error_setg(errp, "Invalid apb divisor value");
 +        error_append_hint(errp, "apb divisor must be a power of 2"
 +                           " and maximum value is 32\n");
 +    }
 +}
 +
 +static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->vmsd = &vmstate_msf2_sysreg;
 +    dc->reset = msf2_sysreg_reset;
 +    dc->props = msf2_sysreg_properties;
 +    dc->realize = msf2_sysreg_realize;
 +}
 +
 +static const TypeInfo msf2_sysreg_info = {
 +    .name  = TYPE_MSF2_SYSREG,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .class_init = msf2_sysreg_class_init,
 +    .instance_size  = sizeof(MSF2SysregState),
 +    .instance_init = msf2_sysreg_init,
 +};
 +
 +static void msf2_sysreg_register_types(void)
 +{
 +    type_register_static(&msf2_sysreg_info);
 +}
 +
 +type_init(msf2_sysreg_register_types)
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/trace-events
+--- a/MAINTAINERS
-+++ b/hw/misc/trace-events
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ mps2_scc_reset(void) "MPS2 SCC: reset"
+@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
- mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) "MPS2 SCC LEDs: %c%c%c%c%c%c%c%c"
+ SBSA-REF
- mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
+ M: Radoslaw Biernacki <rad@semihalf.com>
- mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
+ M: Peter Maydell <peter.maydell@linaro.org>
-+
+-R: Leif Lindholm <leif@nuviainc.com>
-+# hw/misc/msf2-sysreg.c
++R: Leif Lindholm <quic_llindhol@quicinc.com>
-+msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
+ L: qemu-arm@nongnu.org
-+msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
+ S: Maintained
-+msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
+ F: hw/arm/sbsa-ref.c
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 08/31] nvic: Handle banked exceptions in nvic_recompute_state()
+[PULL 02/32] target/arm: Handle cpreg registration for missing EL
-Update the nvic_recompute_state() code to handle the security
+From: Richard Henderson <richard.henderson@linaro.org>
-extension and its associated banked registers.
+More gracefully handle cpregs when EL2 and/or EL3 are missing.
-Code that uses the resulting cached state (ie the irq
+If the reg is entirely inaccessible, do not register it at all.
-acknowledge and complete code) will be updated in a later
+If the reg is for EL2, and EL3 is present but EL2 is not,
-commit.
+either discard, squash to res0, const, or keep unchanged.
 Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
 with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
 translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
 Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
 This will simplify cpreg registration for conditional arm features.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++--
+ target/arm/cpregs.h |  11 +++
- hw/intc/trace-events  |   1 +
+ target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
-files changed, 147 insertions(+), 5 deletions(-)
+files changed, 133 insertions(+), 56 deletions(-)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/target/arm/cpregs.h
-+++ b/hw/intc/armv7m_nvic.c
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ enum {
-  * (higher than the highest possible priority value)
+     ARM_CP_SVE                   = 1 << 14,
-  */
+     /* Flag: Do not expose in gdb sysreg xml. */
- #define NVIC_NOEXC_PRIO 0x100
+     ARM_CP_NO_GDB                = 1 << 15,
-+/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
++    /*
-+#define NVIC_NS_PRIO_LIMIT 0x80
++     * Flags: If EL3 but not EL2...
++     *   - UNDEF: discard the cpreg,
- static const uint8_t nvic_id[] = {
++     *   -  KEEP: retain the cpreg as is,
-x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
++     *   -  C_NZ: set const on the cpreg, but retain resetvalue,
-@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
++     *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
-     return false;
++     * See rule RJFFP in section D1.1.3 of DDI0487H.a.
  }
 +static bool exc_is_banked(int exc)
 +{
 +    /* Return true if this is one of the limited set of exceptions which
 +     * are banked (and thus have state in sec_vectors[])
 +     */
-+    return exc == ARMV7M_EXCP_HARD ||
++    ARM_CP_EL3_NO_EL2_UNDEF      = 1 << 16,
-+        exc == ARMV7M_EXCP_MEM ||
++    ARM_CP_EL3_NO_EL2_KEEP       = 1 << 17,
-+        exc == ARMV7M_EXCP_USAGE ||
++    ARM_CP_EL3_NO_EL2_C_NZ       = 1 << 18,
-+        exc == ARMV7M_EXCP_SVC ||
+ };
-+        exc == ARMV7M_EXCP_PENDSV ||
-+        exc == ARMV7M_EXCP_SYSTICK;
+ /*
-+}
+diff --git a/target/arm/helper.c b/target/arm/helper.c
-+
+index XXXXXXX..XXXXXXX 100644
- /* Return a mask word which clears the subpriority bits from
+--- a/target/arm/helper.c
-  * a priority value for an M-profile exception, leaving only
++++ b/target/arm/helper.c
-  * the group priority.
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-  */
+       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
--static inline uint32_t nvic_gprio_mask(NVICState *s)
+     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
-+static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
+       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
-+{
+-      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
-+    return ~0U << (s->prigroup[secure] + 1);
++      .access = PL2_RW,
-+}
++      .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
-+
+       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
-+static bool exc_targets_secure(NVICState *s, int exc)
+     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
-+{
+       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
-+    /* Return true if this non-banked exception targets Secure state. */
+-      .access = PL2_RW, .resetvalue = 0,
-+    if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
++      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
-+        return false;
+       .writefn = dacr_write, .raw_writefn = raw_write,
-+    }
+       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
-+
+     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
-+    if (exc >= NVIC_FIRST_IRQ) {
+       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
-+        return !s->itns[exc];
+-      .access = PL2_RW, .resetvalue = 0,
-+    }
++      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
-+
+       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
-+    /* Function shouldn't be called for banked exceptions. */
+     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
-+    assert(!exc_is_banked(exc));
+       .type = ARM_CP_ALIAS,
-+
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-+    switch (exc) {
+       .writefn = tlbimva_hyp_is_write },
-+    case ARMV7M_EXCP_NMI:
+     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
-+    case ARMV7M_EXCP_BUS:
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
-+        return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
+-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-+    case ARMV7M_EXCP_SECURE:
++      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-+        return true;
+       .writefn = tlbi_aa64_alle2_write },
-+    case ARMV7M_EXCP_DEBUG:
+     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
-+        /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
-+        return false;
+-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-+    default:
++      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-+        /* reset, and reserved (unused) low exception numbers.
+       .writefn = tlbi_aa64_vae2_write },
-+         * We'll get called by code that loops through all the exception
+     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
-+         * numbers, but it doesn't matter what we return here as these
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
-+         * non-existent exceptions will never be pended or active.
+-      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2_write },
      { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_alle2is_write },
      { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
      { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
  #ifndef CONFIG_USER_ONLY
      /* Unlike the other EL2-related AT operations, these must
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
      { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
        .access = PL2_W, .accessfn = at_s1e2_access,
 -      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
 +      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
 +      .writefn = ats_write64 },
      { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
        .access = PL2_W, .accessfn = at_s1e2_access,
 -      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
 +      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
 +      .writefn = ats_write64 },
      /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
       * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
       * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
        .access = PL2_RW, .accessfn = access_tda,
 -      .type = ARM_CP_NOP },
 +      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
      /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
       * Channel but Linux may try to access this register. The 32-bit
       * alias is DBGDCCINT.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .access = PL2_W, .type = ARM_CP_NOP },
      { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
      { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
        .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2is_write },
      { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2_write },
     { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_rvae2_write },
     { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_alle2is_write },
      { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
        .writefn = tlbi_aa64_alle1is_write },
      { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 +      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
        .writefn = tlbi_aa64_vae2is_write },
      { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
                .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -              .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
 +              .resetvalue = cpu->midr,
 +              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
              { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
                .access = PL2_RW, .resetvalue = cpu->midr,
 +              .type = ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
              { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
                .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -              .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
 +              .resetvalue = vmpidr_def,
 +              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
              { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
 -              .access = PL2_RW,
 -              .resetvalue = vmpidr_def,
 +              .access = PL2_RW, .resetvalue = vmpidr_def,
 +              .type = ARM_CP_EL3_NO_EL2_C_NZ,
                .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
          };
          define_arm_cp_regs(cpu, vpidr_regs);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                     int crm, int opc1, int opc2,
                                     const char *name)
  {
 +    CPUARMState *env = &cpu->env;
      uint32_t key;
      ARMCPRegInfo *r2;
      bool is64 = r->type & ARM_CP_64BIT;
      bool ns = secstate & ARM_CP_SECSTATE_NS;
      int cp = r->cp;
 -    bool isbanked;
      size_t name_len;
 +    bool make_const;
      switch (state) {
      case ARM_CP_STATE_AA32:
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
          }
      }
 +    /*
 +     * Eliminate registers that are not present because the EL is missing.
 +     * Doing this here makes it easier to put all registers for a given
 +     * feature into the same ARMCPRegInfo array and define them all at once.
 +     */
 +    make_const = false;
 +    if (arm_feature(env, ARM_FEATURE_EL3)) {
 +        /*
 +         * An EL2 register without EL2 but with EL3 is (usually) RES0.
 +         * See rule RJFFP in section D1.1.3 of DDI0487H.a.
 +         */
-+        return true;
++        int min_el = ctz32(r->access) / 2;
-+    }
++        if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
-+}
++            if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
-+
++                return;
 +static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
 +{
 +    /* Return the group priority for this exception, given its raw
 +     * (group-and-subgroup) priority value and whether it is targeting
 +     * secure state or not.
 +     */
 +    if (rawprio < 0) {
 +        return rawprio;
 +    }
 +    rawprio &= nvic_gprio_mask(s, targets_secure);
 +    /* AIRCR.PRIS causes us to squash all NS priorities into the
 +     * lower half of the total range
 +     */
 +    if (!targets_secure &&
 +        (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
 +        rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
 +    }
 +    return rawprio;
 +}
 +
 +/* Recompute vectpending and exception_prio for a CPU which implements
 + * the Security extension
 + */
 +static void nvic_recompute_state_secure(NVICState *s)
  {
 -    return ~0U << (s->prigroup[M_REG_NS] + 1);
 +    int i, bank;
 +    int pend_prio = NVIC_NOEXC_PRIO;
 +    int active_prio = NVIC_NOEXC_PRIO;
 +    int pend_irq = 0;
 +    bool pending_is_s_banked = false;
 +
 +    /* R_CQRV: precedence is by:
 +     *  - lowest group priority; if both the same then
 +     *  - lowest subpriority; if both the same then
 +     *  - lowest exception number; if both the same (ie banked) then
 +     *  - secure exception takes precedence
 +     * Compare pseudocode RawExecutionPriority.
 +     * Annoyingly, now we have two prigroup values (for S and NS)
 +     * we can't do the loop comparison on raw priority values.
 +     */
 +    for (i = 1; i < s->num_irq; i++) {
 +        for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
 +            VecInfo *vec;
 +            int prio;
 +            bool targets_secure;
 +
 +            if (bank == M_REG_S) {
 +                if (!exc_is_banked(i)) {
 +                    continue;
 +                }
 +                vec = &s->sec_vectors[i];
 +                targets_secure = true;
 +            } else {
 +                vec = &s->vectors[i];
 +                targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
 +            }
-+
++            make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
-+            prio = exc_group_prio(s, vec->prio, targets_secure);
++        }
-+            if (vec->enabled && vec->pending && prio < pend_prio) {
++    } else {
-+                pend_prio = prio;
++        CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
-+                pend_irq = i;
++                                 ? PL2_RW : PL1_RW);
-+                pending_is_s_banked = (bank == M_REG_S);
++        if ((r->access & max_el) == 0) {
-+            }
++            return;
 +            if (vec->active && prio < active_prio) {
 +                active_prio = prio;
 +            }
 +        }
 +    }
 +
-+    s->vectpending_is_s_banked = pending_is_s_banked;
+     /* Combine cpreg and name into one allocation. */
-+    s->vectpending = pend_irq;
+     name_len = strlen(name) + 1;
-+    s->vectpending_prio = pend_prio;
+     r2 = g_malloc(sizeof(*r2) + name_len);
-+    s->exception_prio = active_prio;
+@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-+
+         r2->opaque = opaque;
 +    trace_nvic_recompute_state_secure(s->vectpending,
 +                                      s->vectpending_is_s_banked,
 +                                      s->vectpending_prio,
 +                                      s->exception_prio);
  }
  /* Recompute vectpending and exception_prio */
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
      int active_prio = NVIC_NOEXC_PRIO;
      int pend_irq = 0;
 +    /* In theory we could write one function that handled both
 +     * the "security extension present" and "not present"; however
 +     * the security related changes significantly complicate the
 +     * recomputation just by themselves and mixing both cases together
 +     * would be even worse, so we retain a separate non-secure-only
 +     * version for CPUs which don't implement the security extension.
 +     */
 +    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
 +        nvic_recompute_state_secure(s);
 +        return;
 +    }
 +
      for (i = 1; i < s->num_irq; i++) {
          VecInfo *vec = &s->vectors[i];
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
      }
-     if (active_prio > 0) {
+-    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
--        active_prio &= nvic_gprio_mask(s);
+-    if (isbanked) {
-+        active_prio &= nvic_gprio_mask(s, false);
++    if (make_const) {
 +        /* This should not have been a very special register to begin. */
 +        int old_special = r2->type & ARM_CP_SPECIAL_MASK;
 +        assert(old_special == 0 || old_special == ARM_CP_NOP);
          /*
 -         * Register is banked (using both entries in array).
 -         * Overwriting fieldoffset as the array is only used to define
 -         * banked registers but later only fieldoffset is used.
 +         * Set the special function to CONST, retaining the other flags.
 +         * This is important for e.g. ARM_CP_SVE so that we still
 +         * take the SVE trap if CPTR_EL3.EZ == 0.
           */
 -        r2->fieldoffset = r->bank_fieldoffsets[ns];
 -    }
 +        r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
 +        /*
 +         * Usually, these registers become RES0, but there are a few
 +         * special cases like VPIDR_EL2 which have a constant non-zero
 +         * value with writes ignored.
 +         */
 +        if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
 +            r2->resetvalue = 0;
 +        }
 +        /*
 +         * ARM_CP_CONST has precedence, so removing the callbacks and
 +         * offsets are not strictly necessary, but it is potentially
 +         * less confusing to debug later.
 +         */
 +        r2->readfn = NULL;
 +        r2->writefn = NULL;
 +        r2->raw_readfn = NULL;
 +        r2->raw_writefn = NULL;
 +        r2->resetfn = NULL;
 +        r2->fieldoffset = 0;
 +        r2->bank_fieldoffsets[0] = 0;
 +        r2->bank_fieldoffsets[1] = 0;
 +    } else {
 +        bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 -    if (state == ARM_CP_STATE_AA32) {
          if (isbanked) {
              /*
 -             * If the register is banked then we don't need to migrate or
 -             * reset the 32-bit instance in certain cases:
 -             *
 -             * 1) If the register has both 32-bit and 64-bit instances then we
 -             *    can count on the 64-bit instance taking care of the
 -             *    non-secure bank.
 -             * 2) If ARMv8 is enabled then we can count on a 64-bit version
 -             *    taking care of the secure bank.  This requires that separate
 -             *    32 and 64-bit definitions are provided.
 +             * Register is banked (using both entries in array).
 +             * Overwriting fieldoffset as the array is only used to define
 +             * banked registers but later only fieldoffset is used.
               */
 -            if ((r->state == ARM_CP_STATE_BOTH && ns) ||
 -                (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
 +            r2->fieldoffset = r->bank_fieldoffsets[ns];
 +        }
 +        if (state == ARM_CP_STATE_AA32) {
 +            if (isbanked) {
 +                /*
 +                 * If the register is banked then we don't need to migrate or
 +                 * reset the 32-bit instance in certain cases:
 +                 *
 +                 * 1) If the register has both 32-bit and 64-bit instances
 +                 *    then we can count on the 64-bit instance taking care
 +                 *    of the non-secure bank.
 +                 * 2) If ARMv8 is enabled then we can count on a 64-bit
 +                 *    version taking care of the secure bank.  This requires
 +                 *    that separate 32 and 64-bit definitions are provided.
 +                 */
 +                if ((r->state == ARM_CP_STATE_BOTH && ns) ||
 +                    (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
 +                    r2->type |= ARM_CP_ALIAS;
 +                }
 +            } else if ((secstate != r->secure) && !ns) {
 +                /*
 +                 * The register is not banked so we only want to allow
 +                 * migration of the non-secure instance.
 +                 */
                  r2->type |= ARM_CP_ALIAS;
              }
 -        } else if ((secstate != r->secure) && !ns) {
 -            /*
 -             * The register is not banked so we only want to allow migration
 -             * of the non-secure instance.
 -             */
 -            r2->type |= ARM_CP_ALIAS;
 -        }
 -        if (HOST_BIG_ENDIAN &&
 -            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
 -            r2->fieldoffset += sizeof(uint32_t);
 +            if (HOST_BIG_ENDIAN &&
 +                r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
 +                r2->fieldoffset += sizeof(uint32_t);
 +            }
          }
      }
-     if (pend_prio > 0) {
+@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
--        pend_prio &= nvic_gprio_mask(s);
+      * multiple times. Special registers (ie NOP/WFI) are
-+        pend_prio &= nvic_gprio_mask(s, false);
+      * never migratable and not even raw-accessible.
       */
 -    if (r->type & ARM_CP_SPECIAL_MASK) {
 +    if (r2->type & ARM_CP_SPECIAL_MASK) {
          r2->type |= ARM_CP_NO_RAW;
      }
+     if (((r->crm == CP_ANY) && crm != 0) ||
      s->vectpending = pend_irq;
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
      } else if (env->v7m.primask[env->v7m.secure]) {
          running = 0;
      } else if (env->v7m.basepri[env->v7m.secure] > 0) {
 -        running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
 +        running = env->v7m.basepri[env->v7m.secure] &
 +            nvic_gprio_mask(s, env->v7m.secure);
      } else {
          running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
      }
 diff --git a/hw/intc/trace-events b/hw/intc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/trace-events
 +++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
  # hw/intc/armv7m_nvic.c
  nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
 +nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
  nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
  nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
  nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 31/31] msf2: Add Emcraft's Smartfusion2 SOM kit
+[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
-From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Emulated Emcraft's Smartfusion2 System On Module starter
+Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
-kit.
+vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
+while registering for v8.
-Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+This is a behavior change for v7 cpus with Security Extensions and
-Message-id: 20170920201737.25723-6-f4bug@amsat.org
+without Virtualization Extensions, in that the virtualization cpregs
-[PMD: drop cpu_model to directly use cpu type]
+are now correctly not present.  This would be a migration compatibility
 break, except that we have an existing bug in which migration of 32-bit
 cpus with Security Extensions enabled does not work.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/Makefile.objs |   2 +-
+ target/arm/helper.c | 158 ++++----------------------------------------
- hw/arm/msf2-som.c    | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++
+file changed, 13 insertions(+), 145 deletions(-)
-files changed, 106 insertions(+), 1 deletion(-)
- create mode 100644 hw/arm/msf2-som.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/Makefile.objs
+--- a/target/arm/helper.c
-+++ b/hw/arm/Makefile.objs
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
- obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
+       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
- obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
+ };
- obj-$(CONFIG_MPS2) += mps2.o
--obj-$(CONFIG_MSF2) += msf2-soc.o
+-/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
-+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
+-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
-diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
+-    { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
-new file mode 100644
+-      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
-index XXXXXXX..XXXXXXX
+-      .access = PL2_RW,
---- /dev/null
+-      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
-+++ b/hw/arm/msf2-som.c
+-    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
-@@ -XXX,XX +XXX,XX @@
+-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
-+/*
+-      .access = PL2_RW,
-+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
+-      .type = ARM_CP_CONST, .resetvalue = 0 },
-+ *
+-    { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
-+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
-+ *
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+-    { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
-+ * of this software and associated documentation files (the "Software"), to deal
+-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
-+ * in the Software without restriction, including without limitation the rights
+-      .access = PL2_RW,
-+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-      .type = ARM_CP_CONST, .resetvalue = 0 },
-+ * copies of the Software, and to permit persons to whom the Software is
+-    { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
-+ * furnished to do so, subject to the following conditions:
+-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
-+ *
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+ * The above copyright notice and this permission notice shall be included in
+-    { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
-+ * all copies or substantial portions of the Software.
+-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
-+ *
+-      .access = PL2_RW, .type = ARM_CP_CONST,
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-      .resetvalue = 0 },
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
-+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
-+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
-+ * THE SOFTWARE.
+-      .access = PL2_RW, .type = ARM_CP_CONST,
-+ */
+-      .resetvalue = 0 },
-+
+-    { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
-+#include "qemu/osdep.h"
+-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
-+#include "qapi/error.h"
+-      .access = PL2_RW, .type = ARM_CP_CONST,
-+#include "qemu/error-report.h"
+-      .resetvalue = 0 },
-+#include "hw/boards.h"
+-    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
-+#include "hw/arm/arm.h"
+-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
-+#include "exec/address-spaces.h"
+-      .access = PL2_RW, .type = ARM_CP_CONST,
-+#include "qemu/cutils.h"
+-      .resetvalue = 0 },
-+#include "hw/arm/msf2-soc.h"
+-    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
-+#include "cpu.h"
+-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
-+
+-      .access = PL2_RW, .type = ARM_CP_CONST,
-+#define DDR_BASE_ADDRESS      0xA0000000
+-      .resetvalue = 0 },
-+#define DDR_SIZE              (64 * M_BYTE)
+-    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
-+
+-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
-+#define M2S010_ENVM_SIZE      (256 * K_BYTE)
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+#define M2S010_ESRAM_SIZE     (64 * K_BYTE)
+-    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
-+
+-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
-+static void emcraft_sf2_s2s010_init(MachineState *machine)
+-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-+{
+-      .type = ARM_CP_CONST, .resetvalue = 0 },
-+    DeviceState *dev;
+-    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
-+    DeviceState *spi_flash;
+-      .cp = 15, .opc1 = 6, .crm = 2,
-+    MSF2State *soc;
+-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-+    MachineClass *mc = MACHINE_GET_CLASS(machine);
+-      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-+    DriveInfo *dinfo = drive_get_next(IF_MTD);
+-    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
-+    qemu_irq cs_line;
+-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
-+    SSIBus *spi_bus;
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+    MemoryRegion *sysmem = get_system_memory();
+-    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
-+    MemoryRegion *ddr = g_new(MemoryRegion, 1);
+-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
-+
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+    if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
+-    { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-+        error_report("This board can only be used with CPU %s",
+-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
-+                     mc->default_cpu_type);
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+    }
+-    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
-+
+-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
-+    memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+                           &error_fatal);
+-    { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
-+    memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
+-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-+
+-      .resetvalue = 0 },
-+    dev = qdev_create(NULL, TYPE_MSF2_SOC);
+-    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
-+    qdev_prop_set_string(dev, "part-name", "M2S010");
+-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
-+    qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+
+-    { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
-+    qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
+-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
-+    qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
+-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
 -      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
 -      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
 -      .resetvalue = 0 },
 -    { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
 -      .access = PL2_RW, .accessfn = access_tda,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
 -      .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
 -      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
 -      .type = ARM_CP_CONST,
 -      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
 -      .access = PL2_RW, .resetvalue = 0 },
 -};
 -
 -/* Ditto, but for registers which exist in ARMv8 but not v7 */
 -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
 -    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
 -      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
 -      .access = PL2_RW,
 -      .type = ARM_CP_CONST, .resetvalue = 0 },
 -};
 -
  static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
  {
      ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          define_arm_cp_regs(cpu, v8_idregs);
          define_arm_cp_regs(cpu, v8_cp_reginfo);
      }
 -    if (arm_feature(env, ARM_FEATURE_EL2)) {
 +
 +    /*
-+     * CPU clock and peripheral clocks(APB0, APB1)are configurable
++     * Register the base EL2 cpregs.
-+     * in Libero. CPU clock is divided by APB0 and APB1 divisors for
++     * Pre v8, these registers are implemented only as part of the
-+     * peripherals. Emcraft's SoM kit comes with these settings by default.
++     * Virtualization Extensions (EL2 present).  Beginning with v8,
 +     * if EL2 is missing but EL3 is enabled, mostly these become
 +     * RES0 from EL3, with some specific exceptions.
 +     */
-+    qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
++    if (arm_feature(env, ARM_FEATURE_EL2)
-+    qdev_prop_set_uint32(dev, "apb0div", 2);
++        || (arm_feature(env, ARM_FEATURE_EL3)
-+    qdev_prop_set_uint32(dev, "apb1div", 2);
++            && arm_feature(env, ARM_FEATURE_V8))) {
          uint64_t vmpidr_def = mpidr_read_val(env);
          ARMCPRegInfo vpidr_regs[] = {
              { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              };
              define_one_arm_cp_reg(cpu, &rvbar);
          }
 -    } else {
 -        /* If EL2 is missing but higher ELs are enabled, we need to
 -         * register the no_el2 reginfos.
 -         */
 -        if (arm_feature(env, ARM_FEATURE_EL3)) {
 -            /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
 -             * of MIDR_EL1 and MPIDR_EL1.
 -             */
 -            ARMCPRegInfo vpidr_regs[] = {
 -                { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
 -                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
 -                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -                  .type = ARM_CP_CONST, .resetvalue = cpu->midr,
 -                  .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
 -                { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
 -                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
 -                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
 -                  .type = ARM_CP_NO_RAW,
 -                  .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
 -            };
 -            define_arm_cp_regs(cpu, vpidr_regs);
 -            define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
 -            if (arm_feature(env, ARM_FEATURE_V8)) {
 -                define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
 -            }
 -        }
      }
 +
-+    object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
++    /* Register the base EL3 cpregs. */
-+
+     if (arm_feature(env, ARM_FEATURE_EL3)) {
-+    soc = MSF2_SOC(dev);
+         define_arm_cp_regs(cpu, el3_cp_reginfo);
-+
+         ARMCPRegInfo el3_regs[] = {
 +    /* Attach SPI flash to SPI0 controller */
 +    spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
 +    spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
 +    qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
 +    if (dinfo) {
 +        qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
 +                                    &error_fatal);
 +    }
 +    qdev_init_nofail(spi_flash);
 +    cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
 +
 +    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
 +                       soc->envm_size);
 +}
 +
 +static void emcraft_sf2_machine_init(MachineClass *mc)
 +{
 +    mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
 +    mc->init = emcraft_sf2_s2s010_init;
 +    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 +}
 +
 +DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 26/31] hw/arm/omap2.c: Don't use old_mmio
+[PULL 04/32] target/arm: Merge zcr reginfo
-Don't use old_mmio in the memory region ops struct.
+From: Richard Henderson <richard.henderson@linaro.org>
+Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
+now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
+while registering.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505580378-9044-7-git-send-email-peter.maydell@linaro.org
 ---
- hw/arm/omap2.c | 49 +++++++++++++++++++++++++++++++++++++------------
+ target/arm/helper.c | 55 ++++++++++++++-------------------------------
-file changed, 37 insertions(+), 12 deletions(-)
+file changed, 17 insertions(+), 38 deletions(-)
-diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/omap2.c
+--- a/target/arm/helper.c
-+++ b/hw/arm/omap2.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write(void *opaque, hwaddr addr,
+@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
      }
  }
-+static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
+-static const ARMCPRegInfo zcr_el1_reginfo = {
-+                                   unsigned size)
+-    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
-+{
+-    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
-+    switch (size) {
+-    .access = PL1_RW, .type = ARM_CP_SVE,
-+    case 1:
+-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
-+        return omap_sysctl_read8(opaque, addr);
+-    .writefn = zcr_write, .raw_writefn = raw_write
-+    case 2:
+-};
-+        return omap_badwidth_read32(opaque, addr); /* TODO */
+-
-+    case 4:
+-static const ARMCPRegInfo zcr_el2_reginfo = {
-+        return omap_sysctl_read(opaque, addr);
+-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-+    default:
+-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-+        g_assert_not_reached();
+-    .access = PL2_RW, .type = ARM_CP_SVE,
-+    }
+-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
-+}
+-    .writefn = zcr_write, .raw_writefn = raw_write
-+
+-};
-+static void omap_sysctl_writefn(void *opaque, hwaddr addr,
+-
-+                                uint64_t value, unsigned size)
+-static const ARMCPRegInfo zcr_no_el2_reginfo = {
-+{
+-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-+    switch (size) {
+-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-+    case 1:
+-    .access = PL2_RW, .type = ARM_CP_SVE,
-+        omap_sysctl_write8(opaque, addr, value);
+-    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
-+        break;
+-};
-+    case 2:
+-
-+        omap_badwidth_write32(opaque, addr, value); /* TODO */
+-static const ARMCPRegInfo zcr_el3_reginfo = {
-+        break;
+-    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
-+    case 4:
+-    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
-+        omap_sysctl_write(opaque, addr, value);
+-    .access = PL3_RW, .type = ARM_CP_SVE,
-+        break;
+-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
-+    default:
+-    .writefn = zcr_write, .raw_writefn = raw_write
-+        g_assert_not_reached();
++static const ARMCPRegInfo zcr_reginfo[] = {
-+    }
++    { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
-+}
++      .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
-+
++      .access = PL1_RW, .type = ARM_CP_SVE,
- static const MemoryRegionOps omap_sysctl_ops = {
++      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
--    .old_mmio = {
++      .writefn = zcr_write, .raw_writefn = raw_write },
--        .read = {
++    { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
--            omap_sysctl_read8,
++      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
--            omap_badwidth_read32,    /* TODO */
++      .access = PL2_RW, .type = ARM_CP_SVE,
--            omap_sysctl_read,
++      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
--        },
++      .writefn = zcr_write, .raw_writefn = raw_write },
--        .write = {
++    { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
--            omap_sysctl_write8,
++      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
--            omap_badwidth_write32,    /* TODO */
++      .access = PL3_RW, .type = ARM_CP_SVE,
--            omap_sysctl_write,
++      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
--        },
++      .writefn = zcr_write, .raw_writefn = raw_write },
 -    },
 +    .read = omap_sysctl_readfn,
 +    .write = omap_sysctl_writefn,
 +    .valid.min_access_size = 1,
 +    .valid.max_access_size = 4,
      .endianness = DEVICE_NATIVE_ENDIAN,
  };
+ void hw_watchpoint_update(ARMCPU *cpu, int n)
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+     }
+     if (cpu_isar_feature(aa64_sve, cpu)) {
+-        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
+-        if (arm_feature(env, ARM_FEATURE_EL2)) {
+-            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
+-        } else {
+-            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
+-        }
+-        if (arm_feature(env, ARM_FEATURE_EL3)) {
+-            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
+-        }
++        define_arm_cp_regs(cpu, zcr_reginfo);
+     }
+ #ifdef TARGET_AARCH64
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 02/31] nvic: Add banked exception states
+[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
-For the v8M security extension, some exceptions must be banked
+From: Richard Henderson <richard.henderson@linaro.org>
 between security states. Add the new vecinfo array which holds
 the state for the banked exceptions and migrate it if the
 CPU the NVIC is attached to implements the security extension.
+This register is present for either VHE or Debugv8p2.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/hw/intc/armv7m_nvic.h | 14 ++++++++++++
+ target/arm/helper.c | 15 +++++++++++----
- hw/intc/armv7m_nvic.c         | 53 ++++++++++++++++++++++++++++++++++++++++++-
+file changed, 11 insertions(+), 4 deletions(-)
 files changed, 66 insertions(+), 1 deletion(-)
-diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/armv7m_nvic.h
+--- a/target/arm/helper.c
-+++ b/include/hw/intc/armv7m_nvic.h
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
+       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  /* Highest permitted number of exceptions (architectural limit) */
  #define NVIC_MAX_VECTORS 512
 +/* Number of internal exceptions */
 +#define NVIC_INTERNAL_VECTORS 16
  typedef struct VecInfo {
      /* Exception priorities can range from -3 to 255; only the unmodifiable
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
      ARMCPU *cpu;
      VecInfo vectors[NVIC_MAX_VECTORS];
 +    /* If the v8M security extension is implemented, some of the internal
 +     * exceptions are banked between security states (ie there exists both
 +     * a Secure and a NonSecure version of the exception and its state):
 +     *  HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
 +     * The rest (including all the external exceptions) are not banked, though
 +     * they may be configurable to target either Secure or NonSecure state.
 +     * We store the secure exception state in sec_vectors[] for the banked
 +     * exceptions, and otherwise use only vectors[] (including for exceptions
 +     * like SecureFault that unconditionally target Secure state).
 +     * Entries in sec_vectors[] for non-banked exception numbers are unused.
 +     */
 +    VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
      uint32_t prigroup;
      /* vectpending and exception_prio are both cached state that can
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
   * For historical reasons QEMU tends to use "interrupt" and
   * "exception" more or less interchangeably.
   */
 -#define NVIC_FIRST_IRQ 16
 +#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
  #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
  /* Effective running priority of the CPU when no exception is active
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
      }
  };
-+static bool nvic_security_needed(void *opaque)
++static const ARMCPRegInfo contextidr_el2 = {
-+{
++    .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
-+    NVICState *s = opaque;
++    .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
-+
++    .access = PL2_RW,
-+    return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
++    .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
 +}
 +
 +static int nvic_security_post_load(void *opaque, int version_id)
 +{
 +    NVICState *s = opaque;
 +    int i;
 +
 +    /* Check for out of range priority settings */
 +    if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
 +        return 1;
 +    }
 +    for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
 +        if (s->sec_vectors[i].prio & ~0xff) {
 +            return 1;
 +        }
 +    }
 +    return 0;
 +}
 +
 +static const VMStateDescription vmstate_nvic_security = {
 +    .name = "nvic/m-security",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .needed = nvic_security_needed,
 +    .post_load = &nvic_security_post_load,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
 +                             vmstate_VecInfo, VecInfo),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
- static const VMStateDescription vmstate_nvic = {
+ static const ARMCPRegInfo vhe_reginfo[] = {
-     .name = "armv7m_nvic",
+-    { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
-     .version_id = 4,
+-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
+-      .access = PL2_RW,
-                              vmstate_VecInfo, VecInfo),
+-      .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
-         VMSTATE_UINT32(prigroup, NVICState),
+     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
-         VMSTATE_END_OF_LIST()
+       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
-+    },
+       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
-+    .subsections = (const VMStateDescription*[]) {
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-+        &vmstate_nvic_security,
+         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
 +        NULL
      }
- };
++    if (cpu_isar_feature(aa64_vh, cpu) ||
-@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
++        cpu_isar_feature(aa64_debugv8p2, cpu)) {
-     s->vectors[ARMV7M_EXCP_NMI].prio = -2;
++        define_one_arm_cp_reg(cpu, &contextidr_el2);
      s->vectors[ARMV7M_EXCP_HARD].prio = -1;
 +    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
 +        s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;
 +        s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;
 +        s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
 +        s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
 +
 +        /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
 +        s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
 +    }
-+
+     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
-     /* Strictly speaking the reset handler should be enabled.
+         define_arm_cp_regs(cpu, vhe_reginfo);
-      * However, we don't simulate soft resets through the NVIC,
+     }
       * and the reset vector should never be pended.
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 22/31] hw/gpio/omap_gpio.c: Don't use old_mmio
+[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
-Drop the use of old_mmio in the omap2_gpio memory ops.
+From: Richard Henderson <richard.henderson@linaro.org>
 Previously we were defining some of these in user-only mode,
 but none of them are accessible from user-only, therefore
 define them only in system mode.
 This will shortly be used from cpu_tcg.c also.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505580378-9044-3-git-send-email-peter.maydell@linaro.org
 ---
- hw/gpio/omap_gpio.c | 26 ++++++++++++--------------
+ target/arm/internals.h |  6 ++++
-file changed, 12 insertions(+), 14 deletions(-)
+ target/arm/cpu64.c     | 64 +++---------------------------------------
+ target/arm/cpu_tcg.c   | 59 ++++++++++++++++++++++++++++++++++++++
-diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
+files changed, 69 insertions(+), 60 deletions(-)
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/omap_gpio.c
+--- a/target/arm/internals.h
-+++ b/hw/gpio/omap_gpio.c
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_write(void *opaque, hwaddr addr,
+@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
-     }
+ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
  #endif
 +#ifdef CONFIG_USER_ONLY
 +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 +#else
 +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 +#endif
 +
  #endif
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
  #include "hvf_arm.h"
  #include "qapi/visitor.h"
  #include "hw/qdev-properties.h"
 -#include "cpregs.h"
 +#include "internals.h"
 -#ifndef CONFIG_USER_ONLY
 -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 -{
 -    ARMCPU *cpu = env_archcpu(env);
 -
 -    /* Number of cores is in [25:24]; otherwise we RAZ */
 -    return (cpu->core_count - 1) << 24;
 -}
 -#endif
 -
 -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
 -#ifndef CONFIG_USER_ONLY
 -    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
 -      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
 -      .writefn = arm_cp_write_ignore },
 -    { .name = "L2CTLR",
 -      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
 -      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
 -      .writefn = arm_cp_write_ignore },
 -#endif
 -    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2ECTLR",
 -      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUACTLR",
 -      .cp = 15, .opc1 = 0, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUECTLR",
 -      .cp = 15, .opc1 = 1, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "CPUMERRSR",
 -      .cp = 15, .opc1 = 2, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 -    { .name = "L2MERRSR",
 -      .cp = 15, .opc1 = 3, .crm = 15,
 -      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 -};
 -
  static void aarch64_a57_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
      cpu->gic_num_lrs = 4;
      cpu->gic_vpribits = 5;
      cpu->gic_vprebits = 5;
 -    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
--static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
+ static void aarch64_a53_initfn(Object *obj)
-+static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
-+                                        unsigned size)
+     cpu->gic_num_lrs = 4;
- {
+     cpu->gic_vpribits = 5;
-     return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
+     cpu->gic_vprebits = 5;
 -    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
- static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
+ static void aarch64_a72_initfn(Object *obj)
--                uint32_t value)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
-+                                     uint64_t value, unsigned size)
+     cpu->gic_num_lrs = 4;
- {
+     cpu->gic_vpribits = 5;
-     uint32_t cur = 0;
+     cpu->gic_vprebits = 5;
-     uint32_t mask = 0xffff;
+-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
++    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 +    if (size == 4) {
 +        omap2_gpio_module_write(opaque, addr, value);
 +        return;
 +    }
 +
      switch (addr & ~3) {
      case 0x00:    /* GPIO_REVISION */
      case 0x14:    /* GPIO_SYSSTATUS */
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
  }
- static const MemoryRegionOps omap2_gpio_module_ops = {
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
--    .old_mmio = {
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
--        .read = {
+index XXXXXXX..XXXXXXX 100644
--            omap2_gpio_module_readp,
+--- a/target/arm/cpu_tcg.c
--            omap2_gpio_module_readp,
++++ b/target/arm/cpu_tcg.c
--            omap2_gpio_module_read,
+@@ -XXX,XX +XXX,XX @@
--        },
+ #endif
--        .write = {
+ #include "cpregs.h"
--            omap2_gpio_module_writep,
--            omap2_gpio_module_writep,
++#ifndef CONFIG_USER_ONLY
--            omap2_gpio_module_write,
++static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
--        },
++{
--    },
++    ARMCPU *cpu = env_archcpu(env);
-+    .read = omap2_gpio_module_readp,
++
-+    .write = omap2_gpio_module_writep,
++    /* Number of cores is in [25:24]; otherwise we RAZ */
-+    .valid.min_access_size = 1,
++    return (cpu->core_count - 1) << 24;
-+    .valid.max_access_size = 4,
++}
-     .endianness = DEVICE_NATIVE_ENDIAN,
++
- };
++static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
 +    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
 +      .access = PL1_RW, .readfn = l2ctlr_read,
 +      .writefn = arm_cp_write_ignore },
 +    { .name = "L2CTLR",
 +      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
 +      .access = PL1_RW, .readfn = l2ctlr_read,
 +      .writefn = arm_cp_write_ignore },
 +    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2ECTLR",
 +      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUACTLR",
 +      .cp = 15, .opc1 = 0, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUECTLR",
 +      .cp = 15, .opc1 = 1, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "CPUMERRSR",
 +      .cp = 15, .opc1 = 2, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "L2MERRSR",
 +      .cp = 15, .opc1 = 3, .crm = 15,
 +      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 +};
 +
 +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
 +{
 +    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 +}
 +#endif /* !CONFIG_USER_ONLY */
 +
  /* CPU models. These are not needed for the AArch64 linux-user build. */
  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 25/31] hw/i2c/omap_i2c.c: Don't use old_mmio
+[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
-Don't use old_mmio in the memory region ops struct.
+From: Richard Henderson <richard.henderson@linaro.org>
+Instead of starting with cortex-a15 and adding v8 features to
+a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
+This fixes the long-standing to-do where we only enabled v8
+features for user-only.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505580378-9044-6-git-send-email-peter.maydell@linaro.org
 ---
- hw/i2c/omap_i2c.c | 44 ++++++++++++++++++++++++++++++++------------
+ target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
-file changed, 32 insertions(+), 12 deletions(-)
+file changed, 92 insertions(+), 59 deletions(-)
-diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/omap_i2c.c
+--- a/target/arm/cpu_tcg.c
-+++ b/hw/i2c/omap_i2c.c
++++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
+@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
-     }
+ static void arm_max_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 +    uint32_t t;
 -    cortex_a15_initfn(obj);
 +    /* aarch64_a57_initfn, advertising none of the aarch64 features */
 +    cpu->dtb_compatible = "arm,cortex-a57";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +    cpu->midr = 0x411fd070;
 +    cpu->revidr = 0x00000000;
 +    cpu->reset_fpsid = 0x41034070;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x8444c004;
 +    cpu->reset_sctlr = 0x00c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
 +    cpu->isar.id_dfr0 = 0x03010066;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x10101105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02102211;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x00011121;
 +    cpu->isar.id_isar6 = 0;
 +    cpu->isar.dbgdidr = 0x3516d000;
 +    cpu->clidr = 0x0a200023;
 +    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 -    /* old-style VFP short-vector support */
 -    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 +    /* Add additional features supported by QEMU */
 +    t = cpu->isar.id_isar5;
 +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 +    cpu->isar.id_isar5 = t;
 +
 +    t = cpu->isar.id_isar6;
 +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 +    cpu->isar.id_isar6 = t;
 +
 +    t = cpu->isar.mvfr1;
 +    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 +    cpu->isar.mvfr1 = t;
 +
 +    t = cpu->isar.mvfr2;
 +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 +    cpu->isar.mvfr2 = t;
 +
 +    t = cpu->isar.id_mmfr3;
 +    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +    cpu->isar.id_mmfr3 = t;
 +
 +    t = cpu->isar.id_mmfr4;
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +    cpu->isar.id_mmfr4 = t;
 +
 +    t = cpu->isar.id_pfr0;
 +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 +    cpu->isar.id_pfr0 = t;
 +
 +    t = cpu->isar.id_pfr2;
 +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 +    cpu->isar.id_pfr2 = t;
  #ifdef CONFIG_USER_ONLY
      /*
 -     * We don't set these in system emulation mode for the moment,
 -     * since we don't correctly set (all of) the ID registers to
 -     * advertise them.
 +     * Break with true ARMv8 and add back old-style VFP short-vector support.
 +     * Only do this for user-mode, where -cpu max is the default, so that
 +     * older v6 and v7 programs are more likely to work without adjustment.
       */
 -    set_feature(&cpu->env, ARM_FEATURE_V8);
 -    {
 -        uint32_t t;
 -
 -        t = cpu->isar.id_isar5;
 -        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 -        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 -        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 -        cpu->isar.id_isar5 = t;
 -
 -        t = cpu->isar.id_isar6;
 -        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 -        t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 -        cpu->isar.id_isar6 = t;
 -
 -        t = cpu->isar.mvfr1;
 -        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 -        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 -        cpu->isar.mvfr1 = t;
 -
 -        t = cpu->isar.mvfr2;
 -        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 -        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 -        cpu->isar.mvfr2 = t;
 -
 -        t = cpu->isar.id_mmfr3;
 -        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 -        cpu->isar.id_mmfr3 = t;
 -
 -        t = cpu->isar.id_mmfr4;
 -        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 -        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 -        cpu->isar.id_mmfr4 = t;
 -
 -        t = cpu->isar.id_pfr0;
 -        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 -        cpu->isar.id_pfr0 = t;
 -
 -        t = cpu->isar.id_pfr2;
 -        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 -        cpu->isar.id_pfr2 = t;
 -    }
 -#endif /* CONFIG_USER_ONLY */
 +    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 +#endif
  }
+ #endif /* !TARGET_AARCH64 */
 +static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
 +                                unsigned size)
 +{
 +    switch (size) {
 +    case 2:
 +        return omap_i2c_read(opaque, addr);
 +    default:
 +        return omap_badwidth_read16(opaque, addr);
 +    }
 +}
 +
 +static void omap_i2c_writefn(void *opaque, hwaddr addr,
 +                             uint64_t value, unsigned size)
 +{
 +    switch (size) {
 +    case 1:
 +        /* Only the last fifo write can be 8 bit. */
 +        omap_i2c_writeb(opaque, addr, value);
 +        break;
 +    case 2:
 +        omap_i2c_write(opaque, addr, value);
 +        break;
 +    default:
 +        omap_badwidth_write16(opaque, addr, value);
 +        break;
 +    }
 +}
 +
  static const MemoryRegionOps omap_i2c_ops = {
 -    .old_mmio = {
 -        .read = {
 -            omap_badwidth_read16,
 -            omap_i2c_read,
 -            omap_badwidth_read16,
 -        },
 -        .write = {
 -            omap_i2c_writeb, /* Only the last fifo write can be 8 bit.  */
 -            omap_i2c_write,
 -            omap_badwidth_write16,
 -        },
 -    },
 +    .read = omap_i2c_readfn,
 +    .write = omap_i2c_writefn,
 +    .valid.min_access_size = 1,
 +    .valid.max_access_size = 4,
      .endianness = DEVICE_NATIVE_ENDIAN,
  };
 --
-.7.4
+.25.1

-New patch
+[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
+From: Richard Henderson <richard.henderson@linaro.org>
+We set this for qemu-system-aarch64, but failed to do so
+for the strictly 32-bit emulation.
+Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu_tcg.c | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu_tcg.c
++++ b/target/arm/cpu_tcg.c
+@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
+     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+     cpu->isar.id_pfr2 = t;
++    t = cpu->isar.id_dfr0;
++    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
++    cpu->isar.id_dfr0 = t;
++
+ #ifdef CONFIG_USER_ONLY
+     /*
+      * Break with true ARMv8 and add back old-style VFP short-vector support.
+--
+.25.1

-[Qemu-devel] [PULL 27/31] msf2: Add Smartfusion2 System timer
+[PULL 09/32] target/arm: Split out aa32_max_features
-From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Modelled System Timer in Microsemi's Smartfusion2 Soc.
+Share the code to set AArch32 max features so that we no
-Timer has two 32bit down counters and two interrupts.
+longer have code drift between qemu{-system,}-{arm,aarch64}.
-Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20170920201737.25723-2-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/timer/Makefile.objs       |   1 +
+ target/arm/internals.h |   2 +
- include/hw/timer/mss-timer.h |  64 ++++++++++
+ target/arm/cpu64.c     |  50 +-----------------
- hw/timer/mss-timer.c         | 289 +++++++++++++++++++++++++++++++++++++++++++
+ target/arm/cpu_tcg.c   | 114 ++++++++++++++++++++++-------------------
-files changed, 354 insertions(+)
+files changed, 65 insertions(+), 101 deletions(-)
  create mode 100644 include/hw/timer/mss-timer.h
  create mode 100644 hw/timer/mss-timer.c
-diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/Makefile.objs
+--- a/target/arm/internals.h
-+++ b/hw/timer/Makefile.objs
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
+@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
- common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
+ #endif
- common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
-+common-obj-$(CONFIG_MSF2) += mss-timer.o
++void aa32_max_features(ARMCPU *cpu);
-diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
++
-new file mode 100644
+ #endif
-index XXXXXXX..XXXXXXX
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
---- /dev/null
+index XXXXXXX..XXXXXXX 100644
-+++ b/include/hw/timer/mss-timer.h
+--- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
      uint64_t t;
 -    uint32_t u;
      if (kvm_enabled() || hvf_enabled()) {
          /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
      cpu->isar.id_aa64zfr0 = t;
 -    /* Replicate the same data to the 32-bit id registers.  */
 -    u = cpu->isar.id_isar5;
 -    u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
 -    u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
 -    u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
 -    u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
 -    u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
 -    u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
 -    cpu->isar.id_isar5 = u;
 -
 -    u = cpu->isar.id_isar6;
 -    u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, DP, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, SB, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
 -    u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
 -    cpu->isar.id_isar6 = u;
 -
 -    u = cpu->isar.id_pfr0;
 -    u = FIELD_DP32(u, ID_PFR0, DIT, 1);
 -    cpu->isar.id_pfr0 = u;
 -
 -    u = cpu->isar.id_pfr2;
 -    u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
 -    cpu->isar.id_pfr2 = u;
 -
 -    u = cpu->isar.id_mmfr3;
 -    u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
 -    cpu->isar.id_mmfr3 = u;
 -
 -    u = cpu->isar.id_mmfr4;
 -    u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -    u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -    u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
 -    u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
 -    cpu->isar.id_mmfr4 = u;
 -
      t = cpu->isar.id_aa64dfr0;
      t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
      cpu->isar.id_aa64dfr0 = t;
 -    u = cpu->isar.id_dfr0;
 -    u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
 -    cpu->isar.id_dfr0 = u;
 -
 -    u = cpu->isar.mvfr1;
 -    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
 -    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
 -    cpu->isar.mvfr1 = u;
 +    /* Replicate the same data to the 32-bit id registers.  */
 +    aa32_max_features(cpu);
  #ifdef CONFIG_USER_ONLY
      /*
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
 @@ -XXX,XX +XXX,XX @@
-+/*
+ #endif
-+ * Microsemi SmartFusion2 Timer.
+ #include "cpregs.h"
-+ *
-+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
++
-+ *
++/* Share AArch32 -cpu max features with AArch64. */
-+ * Permission is hereby granted, free of charge, to any person obtaining a copy
++void aa32_max_features(ARMCPU *cpu)
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_MSS_TIMER_H
 +#define HW_MSS_TIMER_H
 +
 +#include "hw/sysbus.h"
 +#include "hw/ptimer.h"
 +
 +#define TYPE_MSS_TIMER     "mss-timer"
 +#define MSS_TIMER(obj)     OBJECT_CHECK(MSSTimerState, \
 +                              (obj), TYPE_MSS_TIMER)
 +
 +/*
 + * There are two 32-bit down counting timers.
 + * Timers 1 and 2 can be concatenated into a single 64-bit Timer
 + * that operates either in Periodic mode or in One-shot mode.
 + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
 + * In 64-bit mode, writing to the 32-bit registers has no effect.
 + * Similarly, in 32-bit mode, writing to the 64-bit mode registers
 + * has no effect. Only two 32-bit timers are supported currently.
 + */
 +#define NUM_TIMERS        2
 +
 +#define R_TIM1_MAX        6
 +
 +struct Msf2Timer {
 +    QEMUBH *bh;
 +    ptimer_state *ptimer;
 +
 +    uint32_t regs[R_TIM1_MAX];
 +    qemu_irq irq;
 +};
 +
 +typedef struct MSSTimerState {
 +    SysBusDevice parent_obj;
 +
 +    MemoryRegion mmio;
 +    uint32_t freq_hz;
 +    struct Msf2Timer timers[NUM_TIMERS];
 +} MSSTimerState;
 +
 +#endif /* HW_MSS_TIMER_H */
 diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/timer/mss-timer.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Block model of System timer present in
 + * Microsemi's SmartFusion2 and SmartFusion SoCs.
 + *
 + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/main-loop.h"
 +#include "qemu/log.h"
 +#include "hw/timer/mss-timer.h"
 +
 +#ifndef MSS_TIMER_ERR_DEBUG
 +#define MSS_TIMER_ERR_DEBUG  0
 +#endif
 +
 +#define DB_PRINT_L(lvl, fmt, args...) do { \
 +    if (MSS_TIMER_ERR_DEBUG >= lvl) { \
 +        qemu_log("%s: " fmt "\n", __func__, ## args); \
 +    } \
 +} while (0);
 +
 +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
 +
 +#define R_TIM_VAL         0
 +#define R_TIM_LOADVAL     1
 +#define R_TIM_BGLOADVAL   2
 +#define R_TIM_CTRL        3
 +#define R_TIM_RIS         4
 +#define R_TIM_MIS         5
 +
 +#define TIMER_CTRL_ENBL     (1 << 0)
 +#define TIMER_CTRL_ONESHOT  (1 << 1)
 +#define TIMER_CTRL_INTR     (1 << 2)
 +#define TIMER_RIS_ACK       (1 << 0)
 +#define TIMER_RST_CLR       (1 << 6)
 +#define TIMER_MODE          (1 << 0)
 +
 +static void timer_update_irq(struct Msf2Timer *st)
 +{
-+    bool isr, ier;
++    uint32_t t;
 +
-+    isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
++    /* Add additional features supported by QEMU */
-+    ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
++    t = cpu->isar.id_isar5;
-+    qemu_set_irq(st->irq, (ier && isr));
++    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 +    cpu->isar.id_isar5 = t;
 +
 +    t = cpu->isar.id_isar6;
 +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 +    cpu->isar.id_isar6 = t;
 +
 +    t = cpu->isar.mvfr1;
 +    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 +    cpu->isar.mvfr1 = t;
 +
 +    t = cpu->isar.mvfr2;
 +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 +    cpu->isar.mvfr2 = t;
 +
 +    t = cpu->isar.id_mmfr3;
 +    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +    cpu->isar.id_mmfr3 = t;
 +
 +    t = cpu->isar.id_mmfr4;
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +    cpu->isar.id_mmfr4 = t;
 +
 +    t = cpu->isar.id_pfr0;
 +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 +    cpu->isar.id_pfr0 = t;
 +
 +    t = cpu->isar.id_pfr2;
 +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 +    cpu->isar.id_pfr2 = t;
 +
 +    t = cpu->isar.id_dfr0;
 +    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
 +    cpu->isar.id_dfr0 = t;
 +}
 +
-+static void timer_update(struct Msf2Timer *st)
+ #ifndef CONFIG_USER_ONLY
-+{
+ static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-+    uint64_t count;
+ {
-+
+@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
-+    if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
+ static void arm_max_initfn(Object *obj)
-+        ptimer_stop(st->ptimer);
+ {
-+        return;
+     ARMCPU *cpu = ARM_CPU(obj);
-+    }
+-    uint32_t t;
-+
-+    count = st->regs[R_TIM_LOADVAL];
+     /* aarch64_a57_initfn, advertising none of the aarch64 features */
-+    ptimer_set_limit(st->ptimer, count, 1);
+     cpu->dtb_compatible = "arm,cortex-a57";
-+    ptimer_run(st->ptimer, 1);
+@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
-+}
+     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
-+
+     define_cortex_a72_a57_a53_cp_reginfo(cpu);
-+static uint64_t
-+timer_read(void *opaque, hwaddr offset, unsigned int size)
+-    /* Add additional features supported by QEMU */
-+{
+-    t = cpu->isar.id_isar5;
-+    MSSTimerState *t = opaque;
+-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-+    hwaddr addr;
+-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-+    struct Msf2Timer *st;
+-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-+    uint32_t ret = 0;
+-    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-+    int timer = 0;
+-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-+    int isr;
+-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-+    int ier;
+-    cpu->isar.id_isar5 = t;
-+
+-
-+    addr = offset >> 2;
+-    t = cpu->isar.id_isar6;
-+    /*
+-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-+     * Two independent timers has same base address.
+-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-+     * Based on address passed figure out which timer is being used.
+-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-+     */
+-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-+    if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
+-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-+        timer = 1;
+-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-+        addr -= R_TIM1_MAX;
+-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-+    }
+-    cpu->isar.id_isar6 = t;
-+
+-
-+    st = &t->timers[timer];
+-    t = cpu->isar.mvfr1;
-+
+-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-+    switch (addr) {
+-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-+    case R_TIM_VAL:
+-    cpu->isar.mvfr1 = t;
-+        ret = ptimer_get_count(st->ptimer);
+-
-+        break;
+-    t = cpu->isar.mvfr2;
-+
+-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-+    case R_TIM_MIS:
+-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-+        isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+-    cpu->isar.mvfr2 = t;
-+        ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+-
-+        ret = ier & isr;
+-    t = cpu->isar.id_mmfr3;
-+        break;
+-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-+
+-    cpu->isar.id_mmfr3 = t;
-+    default:
+-
-+        if (addr < R_TIM1_MAX) {
+-    t = cpu->isar.id_mmfr4;
-+            ret = st->regs[addr];
+-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-+        } else {
+-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-+            qemu_log_mask(LOG_GUEST_ERROR,
+-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-+                        TYPE_MSS_TIMER": 64-bit mode not supported\n");
+-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-+            return ret;
+-    cpu->isar.id_mmfr4 = t;
-+        }
+-
-+        break;
+-    t = cpu->isar.id_pfr0;
-+    }
+-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-+
+-    cpu->isar.id_pfr0 = t;
-+    DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset,
+-
-+            ret);
+-    t = cpu->isar.id_pfr2;
-+    return ret;
+-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-+}
+-    cpu->isar.id_pfr2 = t;
-+
+-
-+static void
+-    t = cpu->isar.id_dfr0;
-+timer_write(void *opaque, hwaddr offset,
+-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-+            uint64_t val64, unsigned int size)
+-    cpu->isar.id_dfr0 = t;
-+{
++    aa32_max_features(cpu);
-+    MSSTimerState *t = opaque;
-+    hwaddr addr;
+ #ifdef CONFIG_USER_ONLY
-+    struct Msf2Timer *st;
+     /*
 +    int timer = 0;
 +    uint32_t value = val64;
 +
 +    addr = offset >> 2;
 +    /*
 +     * Two independent timers has same base address.
 +     * Based on addr passed figure out which timer is being used.
 +     */
 +    if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
 +        timer = 1;
 +        addr -= R_TIM1_MAX;
 +    }
 +
 +    st = &t->timers[timer];
 +
 +    DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
 +            value, timer);
 +
 +    switch (addr) {
 +    case R_TIM_CTRL:
 +        st->regs[R_TIM_CTRL] = value;
 +        timer_update(st);
 +        break;
 +
 +    case R_TIM_RIS:
 +        if (value & TIMER_RIS_ACK) {
 +            st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
 +        }
 +        break;
 +
 +    case R_TIM_LOADVAL:
 +        st->regs[R_TIM_LOADVAL] = value;
 +        if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
 +            timer_update(st);
 +        }
 +        break;
 +
 +    case R_TIM_BGLOADVAL:
 +        st->regs[R_TIM_BGLOADVAL] = value;
 +        st->regs[R_TIM_LOADVAL] = value;
 +        break;
 +
 +    case R_TIM_VAL:
 +    case R_TIM_MIS:
 +        break;
 +
 +    default:
 +        if (addr < R_TIM1_MAX) {
 +            st->regs[addr] = value;
 +        } else {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                        TYPE_MSS_TIMER": 64-bit mode not supported\n");
 +            return;
 +        }
 +        break;
 +    }
 +    timer_update_irq(st);
 +}
 +
 +static const MemoryRegionOps timer_ops = {
 +    .read = timer_read,
 +    .write = timer_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 1,
 +        .max_access_size = 4
 +    }
 +};
 +
 +static void timer_hit(void *opaque)
 +{
 +    struct Msf2Timer *st = opaque;
 +
 +    st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
 +
 +    if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
 +        timer_update(st);
 +    }
 +    timer_update_irq(st);
 +}
 +
 +static void mss_timer_init(Object *obj)
 +{
 +    MSSTimerState *t = MSS_TIMER(obj);
 +    int i;
 +
 +    /* Init all the ptimers.  */
 +    for (i = 0; i < NUM_TIMERS; i++) {
 +        struct Msf2Timer *st = &t->timers[i];
 +
 +        st->bh = qemu_bh_new(timer_hit, st);
 +        st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
 +        ptimer_set_freq(st->ptimer, t->freq_hz);
 +        sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
 +    }
 +
 +    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
 +                          NUM_TIMERS * R_TIM1_MAX * 4);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
 +}
 +
 +static const VMStateDescription vmstate_timers = {
 +    .name = "mss-timer-block",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_PTIMER(ptimer, struct Msf2Timer),
 +        VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static const VMStateDescription vmstate_mss_timer = {
 +    .name = TYPE_MSS_TIMER,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(freq_hz, MSSTimerState),
 +        VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
 +                vmstate_timers, struct Msf2Timer),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static Property mss_timer_properties[] = {
 +    /* Libero GUI shows 100Mhz as default for clocks */
 +    DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
 +                      100 * 1000000),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void mss_timer_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->props = mss_timer_properties;
 +    dc->vmsd = &vmstate_mss_timer;
 +}
 +
 +static const TypeInfo mss_timer_info = {
 +    .name          = TYPE_MSS_TIMER,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(MSSTimerState),
 +    .instance_init = mss_timer_init,
 +    .class_init    = mss_timer_class_init,
 +};
 +
 +static void mss_timer_register_types(void)
 +{
 +    type_register_static(&mss_timer_info);
 +}
 +
 +type_init(mss_timer_register_types)
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 23/31] hw/timer/omap_synctimer.c: Don't use old_mmio
+[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
-Don't use the old_mmio in the memory region ops struct.
+From: Richard Henderson <richard.henderson@linaro.org>
+Update the legacy feature names to the current names.
+Provide feature names for id changes that were not marked.
+Sort the field updates into increasing bitfield order.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505580378-9044-4-git-send-email-peter.maydell@linaro.org
 ---
- hw/timer/omap_synctimer.c | 35 +++++++++++++++++++++--------------
+ target/arm/cpu64.c   | 100 +++++++++++++++++++++----------------------
-file changed, 21 insertions(+), 14 deletions(-)
+ target/arm/cpu_tcg.c |  48 ++++++++++-----------
 files changed, 74 insertions(+), 74 deletions(-)
-diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/omap_synctimer.c
+--- a/target/arm/cpu64.c
-+++ b/hw/timer/omap_synctimer.c
++++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     }
+     cpu->midr = t;
      t = cpu->isar.id_aa64isar0;
 -    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
      t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
 -    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
 -    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
 +    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
 +    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
      cpu->isar.id_aa64isar0 = t;
      t = cpu->isar.id_aa64isar1;
 -    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
 -    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
 -    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
 +    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
 +    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
      cpu->isar.id_aa64isar1 = t;
      t = cpu->isar.id_aa64pfr0;
 +    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
 +    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
      cpu->isar.id_aa64pfr0 = t;
      t = cpu->isar.id_aa64pfr1;
 -    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
 -    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
 +    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
 +    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
      /*
       * Begin with full support for MTE. This will be downgraded to MTE=0
       * during realize if the board provides no tag memory, much like
       * we do for EL2 with the virtualization=on property.
       */
 -    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
 +    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
      cpu->isar.id_aa64pfr1 = t;
      t = cpu->isar.id_aa64mmfr0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      cpu->isar.id_aa64mmfr0 = t;
      t = cpu->isar.id_aa64mmfr1;
 -    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
      cpu->isar.id_aa64mmfr1 = t;
      t = cpu->isar.id_aa64mmfr2;
 -    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
 -    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
 -    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
      cpu->isar.id_aa64mmfr2 = t;
      t = cpu->isar.id_aa64zfr0;
      t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
 -    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
 -    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
 +    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
 +    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
      cpu->isar.id_aa64zfr0 = t;
      t = cpu->isar.id_aa64dfr0;
 -    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
 +    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
      cpu->isar.id_aa64dfr0 = t;
      /* Replicate the same data to the 32-bit id registers.  */
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
      /* Add additional features supported by QEMU */
      t = cpu->isar.id_isar5;
 -    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 -    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
 +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
 +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
      t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 -    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
 +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
      cpu->isar.id_isar5 = t;
      t = cpu->isar.id_isar6;
 -    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
 -    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
 +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
 +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
 +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
 +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
 +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
 +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
 +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
      cpu->isar.id_isar6 = t;
      t = cpu->isar.mvfr1;
 -    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 -    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 +    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
 +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
      cpu->isar.mvfr1 = t;
      t = cpu->isar.mvfr2;
 -    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 -    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
 +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
      cpu->isar.mvfr2 = t;
      t = cpu->isar.id_mmfr3;
 -    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
      cpu->isar.id_mmfr3 = t;
      t = cpu->isar.id_mmfr4;
 -    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 -    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
 +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
 +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
      cpu->isar.id_mmfr4 = t;
      t = cpu->isar.id_pfr0;
 -    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
 +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
      cpu->isar.id_pfr0 = t;
      t = cpu->isar.id_pfr2;
 -    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
 +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
      cpu->isar.id_pfr2 = t;
      t = cpu->isar.id_dfr0;
 -    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
 +    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
      cpu->isar.id_dfr0 = t;
  }
--static void omap_synctimer_write(void *opaque, hwaddr addr,
--                uint32_t value)
-+static uint64_t omap_synctimer_readfn(void *opaque, hwaddr addr,
-+                                      unsigned size)
-+{
-+    switch (size) {
-+    case 1:
-+        return omap_badwidth_read32(opaque, addr);
-+    case 2:
-+        return omap_synctimer_readh(opaque, addr);
-+    case 4:
-+        return omap_synctimer_readw(opaque, addr);
-+    default:
-+        g_assert_not_reached();
-+    }
-+}
-+
-+static void omap_synctimer_writefn(void *opaque, hwaddr addr,
-+                                   uint64_t value, unsigned size)
- {
-     OMAP_BAD_REG(addr);
- }
- static const MemoryRegionOps omap_synctimer_ops = {
--    .old_mmio = {
--        .read = {
--            omap_badwidth_read32,
--            omap_synctimer_readh,
--            omap_synctimer_readw,
--        },
--        .write = {
--            omap_badwidth_write32,
--            omap_synctimer_write,
--            omap_synctimer_write,
--        },
--    },
-+    .read = omap_synctimer_readfn,
-+    .write = omap_synctimer_writefn,
-+    .valid.min_access_size = 1,
-+    .valid.max_access_size = 4,
-     .endianness = DEVICE_NATIVE_ENDIAN,
- };
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
+[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
-If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
+From: Richard Henderson <richard.henderson@linaro.org>
 can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
 preempt execution. The simple way to achieve this is to clear the
 enable bit for it, since the enable bit isn't guest visible.
+Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
+during arm_cpu_realizefn.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 12 ++++++++++--
+ target/arm/cpu.c | 22 +++++++++++++---------
-file changed, 10 insertions(+), 2 deletions(-)
+file changed, 13 insertions(+), 9 deletions(-)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/target/arm/cpu.c
-+++ b/hw/intc/armv7m_nvic.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-                     (R_V7M_AIRCR_SYSRESETREQS_MASK |
+          */
-                      R_V7M_AIRCR_BFHFNMINS_MASK |
+         unset_feature(env, ARM_FEATURE_EL3);
-                      R_V7M_AIRCR_PRIS_MASK);
--                /* BFHFNMINS changes the priority of Secure HardFault */
+-        /* Disable the security extension feature bits in the processor feature
-+                /* BFHFNMINS changes the priority of Secure HardFault, and
+-         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
-+                 * allows a pending Non-secure HardFault to preempt (which
++        /*
-+                 * we implement by marking it enabled).
++         * Disable the security extension feature bits in the processor
-+                 */
++         * feature registers as well.
-                 if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
+          */
-                     s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
+-        cpu->isar.id_pfr1 &= ~0xf0;
-+                    s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
+-        cpu->isar.id_aa64pfr0 &= ~0xf000;
-                 } else {
++        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
-                     s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
++        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-+                    s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
++                                           ID_AA64PFR0, EL3, 0);
                  }
              }
              nvic_irq_update(s);
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
      NVICState *s = NVIC(dev);
      s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
 -    s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
      /* MEM, BUS, and USAGE are enabled through
       * the System Handler Control register
       */
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
          /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
          s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
 +        /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
 +        s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
 +    } else {
 +        s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
      }
-     /* Strictly speaking the reset handler should be enabled.
+     if (!cpu->has_el2) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      }
      if (!arm_feature(env, ARM_FEATURE_EL2)) {
 -        /* Disable the hypervisor feature bits in the processor feature
 -         * registers if we don't have EL2. These are id_pfr1[15:12] and
 -         * id_aa64pfr0_el1[11:8].
 +        /*
 +         * Disable the hypervisor feature bits in the processor feature
 +         * registers if we don't have EL2.
           */
 -        cpu->isar.id_aa64pfr0 &= ~0xf00;
 -        cpu->isar.id_pfr1 &= ~0xf000;
 +        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
 +                                           ID_AA64PFR0, EL2, 0);
 +        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
 +                                       ID_PFR1, VIRTUALIZATION, 0);
      }
  #ifndef CONFIG_USER_ONLY
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 05/31] nvic: Implement AIRCR changes for v8M
+[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
-The Application Interrupt and Reset Control Register has some changes
+From: Richard Henderson <richard.henderson@linaro.org>
 for v8M:
  * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
    real state if the security extension is implemented and otherwise
    are constant
  * the PRIGROUP field is banked between security states
  * non-secure code can be blocked from using the SYSRESET bit
    to reset the system if SYSRESETREQS is set
-Implement the new state and the changes to register read and write.
+The only portion of FEAT_Debugv8p2 that is relevant to QEMU
-For the moment we ignore the effects of the secure PRIGROUP.
+is CONTEXTIDR_EL2, which is also conditionally implemented
-We will implement the effects of PRIS and BFHFNMIS later.
+with FEAT_VHE.  The rest of the debug extension concerns the
 External debug interface, which is outside the scope of QEMU.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
 ---
- include/hw/intc/armv7m_nvic.h |  3 ++-
+ docs/system/arm/emulation.rst | 1 +
- target/arm/cpu.h              | 12 +++++++++++
+ target/arm/cpu.c              | 1 +
- hw/intc/armv7m_nvic.c         | 49 +++++++++++++++++++++++++++++++++----------
+ target/arm/cpu64.c            | 1 +
- target/arm/cpu.c              |  7 +++++++
+ target/arm/cpu_tcg.c          | 2 ++
-files changed, 59 insertions(+), 12 deletions(-)
+files changed, 5 insertions(+)
-diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/armv7m_nvic.h
+--- a/docs/system/arm/emulation.rst
-+++ b/include/hw/intc/armv7m_nvic.h
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-      * Entries in sec_vectors[] for non-banked exception numbers are unused.
+ - FEAT_BTI (Branch Target Identification)
-      */
+ - FEAT_DIT (Data Independent Timing instructions)
-     VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
+ - FEAT_DPB (DC CVAP instruction)
--    uint32_t prigroup;
++- FEAT_Debugv8p2 (Debug changes for v8.2)
-+    /* The PRIGROUP field in AIRCR is banked */
+ - FEAT_DotProd (Advanced SIMD dot product instructions)
-+    uint32_t prigroup[M_REG_NUM_BANKS];
+ - FEAT_FCMA (Floating-point complex number instructions)
+ - FEAT_FHM (Floating-point half-precision multiplication instructions)
      /* The following fields are all cached state that can be recalculated
       * from the vectors[] and sec_vectors[] arrays and the prigroup field:
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
          int exception;
          uint32_t primask[M_REG_NUM_BANKS];
          uint32_t faultmask[M_REG_NUM_BANKS];
 +        uint32_t aircr; /* only holds r/w state if security extn implemented */
          uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
      } v7m;
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1)
  FIELD(V7M_CCR, DC, 16, 1)
  FIELD(V7M_CCR, IC, 17, 1)
 +/* V7M AIRCR bits */
 +FIELD(V7M_AIRCR, VECTRESET, 0, 1)
 +FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
 +FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
 +FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
 +FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
 +FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
 +FIELD(V7M_AIRCR, PRIS, 14, 1)
 +FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
 +FIELD(V7M_AIRCR, VECTKEY, 16, 16)
 +
  /* V7M CFSR bits for MMFSR */
  FIELD(V7M_CFSR, IACCVIOL, 0, 1)
  FIELD(V7M_CFSR, DACCVIOL, 1, 1)
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
   */
  static inline uint32_t nvic_gprio_mask(NVICState *s)
  {
 -    return ~0U << (s->prigroup + 1);
 +    return ~0U << (s->prigroup[M_REG_NS] + 1);
  }
  /* Recompute vectpending and exception_prio */
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
          return val;
      case 0xd08: /* Vector Table Offset.  */
          return cpu->env.v7m.vecbase[attrs.secure];
 -    case 0xd0c: /* Application Interrupt/Reset Control.  */
 -        return 0xfa050000 | (s->prigroup << 8);
 +    case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
 +        val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);
 +        if (attrs.secure) {
 +            /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
 +            val |= cpu->env.v7m.aircr;
 +        } else {
 +            if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
 +                /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
 +                 * security isn't supported then BFHFNMINS is RAO (and
 +                 * the bit in env.v7m.aircr is always set).
 +                 */
 +                val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
 +            }
 +        }
 +        return val;
      case 0xd10: /* System Control.  */
          /* TODO: Implement SLEEPONEXIT.  */
          return 0;
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
      case 0xd08: /* Vector Table Offset.  */
          cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
          break;
 -    case 0xd0c: /* Application Interrupt/Reset Control.  */
 -        if ((value >> 16) == 0x05fa) {
 -            if (value & 4) {
 -                qemu_irq_pulse(s->sysresetreq);
 +    case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
 +        if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
 +            if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
 +                if (attrs.secure ||
 +                    !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
 +                    qemu_irq_pulse(s->sysresetreq);
 +                }
              }
 -            if (value & 2) {
 +            if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
                  qemu_log_mask(LOG_GUEST_ERROR,
                                "Setting VECTCLRACTIVE when not in DEBUG mode "
                                "is UNPREDICTABLE\n");
              }
 -            if (value & 1) {
 +            if (value & R_V7M_AIRCR_VECTRESET_MASK) {
 +                /* NB: this bit is RES0 in v8M */
                  qemu_log_mask(LOG_GUEST_ERROR,
                                "Setting VECTRESET when not in DEBUG mode "
                                "is UNPREDICTABLE\n");
              }
 -            s->prigroup = extract32(value, 8, 3);
 +            s->prigroup[attrs.secure] = extract32(value,
 +                                                  R_V7M_AIRCR_PRIGROUP_SHIFT,
 +                                                  R_V7M_AIRCR_PRIGROUP_LENGTH);
 +            if (attrs.secure) {
 +                /* These bits are only writable by secure */
 +                cpu->env.v7m.aircr = value &
 +                    (R_V7M_AIRCR_SYSRESETREQS_MASK |
 +                     R_V7M_AIRCR_BFHFNMINS_MASK |
 +                     R_V7M_AIRCR_PRIS_MASK);
 +            }
              nvic_irq_update(s);
          }
          break;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
      .fields = (VMStateField[]) {
          VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
                               vmstate_VecInfo, VecInfo),
 +        VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
          VMSTATE_END_OF_LIST()
      }
  };
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
      .fields = (VMStateField[]) {
          VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
                               vmstate_VecInfo, VecInfo),
 -        VMSTATE_UINT32(prigroup, NVICState),
 +        VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),
          VMSTATE_END_OF_LIST()
      },
      .subsections = (const VMStateDescription*[]) {
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+          * feature registers as well.
-         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+          */
-             env->v7m.secure = true;
+         cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
-+        } else {
++        cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
-+            /* This bit resets to 0 if security is supported, but 1 if
+         cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
-+             * it is not. The bit is not present in v7M, but we set it
+                                            ID_AA64PFR0, EL3, 0);
-+             * here so we can avoid having to make checks on it conditional
+     }
-+             * on ARM_FEATURE_V8 (we don't let the guest see the bit).
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-+             */
+index XXXXXXX..XXXXXXX 100644
-+            env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
+--- a/target/arm/cpu64.c
-         }
++++ b/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-         /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
+     cpu->isar.id_aa64zfr0 = t;
      t = cpu->isar.id_aa64dfr0;
 +    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8);  /* FEAT_Debugv8p2 */
      t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
      cpu->isar.id_aa64dfr0 = t;
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
      cpu->isar.id_pfr2 = t;
      t = cpu->isar.id_dfr0;
 +    t = FIELD_DP32(t, ID_DFR0, COPDBG, 8);        /* FEAT_Debugv8p2 */
 +    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8);       /* FEAT_Debugv8p2 */
      t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
      cpu->isar.id_dfr0 = t;
  }
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 21/31] hw/arm/palm.c: Don't use old_mmio for static_ops
+[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
-Update the static_ops functions to use new-style mmio
+From: Richard Henderson <richard.henderson@linaro.org>
 rather than the legacy old_mmio functions.
+This extension concerns changes to the External Debug interface,
+with Secure and Non-secure access to the debug registers, and all
+of it is outside the scope of QEMU.  Indicating support for this
+is mandatory with FEAT_SEL2, which we do implement.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505580378-9044-2-git-send-email-peter.maydell@linaro.org
 ---
- hw/arm/palm.c | 30 ++++++++++--------------------
+ docs/system/arm/emulation.rst | 1 +
-file changed, 10 insertions(+), 20 deletions(-)
+ target/arm/cpu64.c            | 2 +-
  target/arm/cpu_tcg.c          | 4 ++--
 files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/hw/arm/palm.c b/hw/arm/palm.c
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/palm.c
+--- a/docs/system/arm/emulation.rst
-+++ b/hw/arm/palm.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- #include "exec/address-spaces.h"
+ - FEAT_DIT (Data Independent Timing instructions)
- #include "cpu.h"
+ - FEAT_DPB (DC CVAP instruction)
+ - FEAT_Debugv8p2 (Debug changes for v8.2)
--static uint32_t static_readb(void *opaque, hwaddr offset)
++- FEAT_Debugv8p4 (Debug changes for v8.4)
-+static uint64_t static_read(void *opaque, hwaddr offset, unsigned size)
+ - FEAT_DotProd (Advanced SIMD dot product instructions)
- {
+ - FEAT_FCMA (Floating-point complex number instructions)
--    uint32_t *val = (uint32_t *) opaque;
+ - FEAT_FHM (Floating-point half-precision multiplication instructions)
--    return *val >> ((offset & 3) << 3);
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
--}
+index XXXXXXX..XXXXXXX 100644
-+    uint32_t *val = (uint32_t *)opaque;
+--- a/target/arm/cpu64.c
-+    uint32_t sizemask = 7 >> size;
++++ b/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
--static uint32_t static_readh(void *opaque, hwaddr offset)
+     cpu->isar.id_aa64zfr0 = t;
--{
--    uint32_t *val = (uint32_t *) opaque;
+     t = cpu->isar.id_aa64dfr0;
--    return *val >> ((offset & 1) << 3);
+-    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8);  /* FEAT_Debugv8p2 */
--}
++    t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9);  /* FEAT_Debugv8p4 */
--
+     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
--static uint32_t static_readw(void *opaque, hwaddr offset)
+     cpu->isar.id_aa64dfr0 = t;
--{
--    uint32_t *val = (uint32_t *) opaque;
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
--    return *val >> ((offset & 0) << 3);
+index XXXXXXX..XXXXXXX 100644
-+    return *val >> ((offset & sizemask) << 3);
+--- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
      cpu->isar.id_pfr2 = t;
      t = cpu->isar.id_dfr0;
 -    t = FIELD_DP32(t, ID_DFR0, COPDBG, 8);        /* FEAT_Debugv8p2 */
 -    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8);       /* FEAT_Debugv8p2 */
 +    t = FIELD_DP32(t, ID_DFR0, COPDBG, 9);        /* FEAT_Debugv8p4 */
 +    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9);       /* FEAT_Debugv8p4 */
      t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
      cpu->isar.id_dfr0 = t;
  }
--static void static_write(void *opaque, hwaddr offset,
--                uint32_t value)
-+static void static_write(void *opaque, hwaddr offset, uint64_t value,
-+                         unsigned size)
- {
- #ifdef SPY
-     printf("%s: value %08lx written at " PA_FMT "\n",
-@@ -XXX,XX +XXX,XX @@ static void static_write(void *opaque, hwaddr offset,
- }
- static const MemoryRegionOps static_ops = {
--    .old_mmio = {
--        .read = { static_readb, static_readh, static_readw, },
--        .write = { static_write, static_write, static_write, },
--    },
-+    .read = static_read,
-+    .write = static_write,
-+    .valid.min_access_size = 1,
-+    .valid.max_access_size = 4,
-     .endianness = DEVICE_NATIVE_ENDIAN,
- };
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 09/31] nvic: Make set_pending and clear_pending take a secure parameter
+[PULL 14/32] target/arm: Add minimal RAS registers
-Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()
+From: Richard Henderson <richard.henderson@linaro.org>
 functions take a bool indicating whether to pend the secure
 or non-secure version of a banked interrupt, and update the
 callsites accordingly.
-In most callsites we can simply pass the correct security
+Add only the system registers required to implement zero error
-state in; in a couple of cases we use TODO comments to indicate
+records.  This means that all values for ERRSELR are out of range,
-that we will return the code in a subsequent commit.
+which means that it and all of the indexed error record registers
 need not be implemented.
+Add the EL2 registers required for injecting virtual SError.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-10-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/cpu.h      | 14 ++++++++++-
+ target/arm/cpu.h    |  5 +++
- hw/intc/armv7m_nvic.c | 64 ++++++++++++++++++++++++++++++++++++++-------------
+ target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
- target/arm/helper.c   | 24 +++++++++++--------
+files changed, 89 insertions(+)
  hw/intc/trace-events  |  4 ++--
 files changed, 77 insertions(+), 29 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
-     return true;
+         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
- }
+         uint64_t gcr_el1;
- #endif
+         uint64_t rgsr_el1;
--void armv7m_nvic_set_pending(void *opaque, int irq);
++
-+/**
++        /* Minimal RAS registers */
-+ * armv7m_nvic_set_pending: mark the specified exception as pending
++        uint64_t disr_el1;
-+ * @opaque: the NVIC
++        uint64_t vdisr_el2;
-+ * @irq: the exception number to mark pending
++        uint64_t vsesr_el2;
-+ * @secure: false for non-banked exceptions or for the nonsecure
+     } cp15;
-+ * version of a banked exception, true for the secure version of a banked
-+ * exception.
+     struct {
 + *
 + * Marks the specified exception as pending. Note that we will assert()
 + * if @secure is true and @irq does not specify one of the fixed set
 + * of architecturally banked exceptions.
 + */
 +void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
  void armv7m_nvic_acknowledge_irq(void *opaque);
  /**
   * armv7m_nvic_complete_irq: complete specified interrupt or exception
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
      qemu_set_irq(s->excpout, lvl);
  }
 -static void armv7m_nvic_clear_pending(void *opaque, int irq)
 +/**
 + * armv7m_nvic_clear_pending: mark the specified exception as not pending
 + * @opaque: the NVIC
 + * @irq: the exception number to mark as not pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Marks the specified exception as not pending. Note that we will assert()
 + * if @secure is true and @irq does not specify one of the fixed set
 + * of architecturally banked exceptions.
 + */
 +static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
  {
      NVICState *s = (NVICState *)opaque;
      VecInfo *vec;
      assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
 -    vec = &s->vectors[irq];
 -    trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
 +    if (secure) {
 +        assert(exc_is_banked(irq));
 +        vec = &s->sec_vectors[irq];
 +    } else {
 +        vec = &s->vectors[irq];
 +    }
 +    trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
      if (vec->pending) {
          vec->pending = 0;
          nvic_irq_update(s);
      }
  }
 -void armv7m_nvic_set_pending(void *opaque, int irq)
 +void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
  {
      NVICState *s = (NVICState *)opaque;
 +    bool banked = exc_is_banked(irq);
      VecInfo *vec;
      assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
 +    assert(!secure || banked);
 -    vec = &s->vectors[irq];
 -    trace_nvic_set_pending(irq, vec->enabled, vec->prio);
 +    vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
 +    trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);
      if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
          /* If a synchronous exception is pending then it may be
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq)
                            "(current priority %d)\n", irq, running);
              }
 -            /* We can do the escalation, so we take HardFault instead */
 +            /* We can do the escalation, so we take HardFault instead.
 +             * If BFHFNMINS is set then we escalate to the banked HF for
 +             * the target security state of the original exception; otherwise
 +             * we take a Secure HardFault.
 +             */
              irq = ARMV7M_EXCP_HARD;
 -            vec = &s->vectors[irq];
 +            if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
 +                (secure ||
 +                 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
 +                vec = &s->sec_vectors[irq];
 +            } else {
 +                vec = &s->vectors[irq];
 +            }
 +            /* HF may be banked but there is only one shared HFSR */
              s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
          }
      }
@@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level)
      if (level != vec->level) {
          vec->level = level;
          if (level) {
 -            armv7m_nvic_set_pending(s, n);
 +            armv7m_nvic_set_pending(s, n, false);
          }
      }
  }
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
      }
      case 0xd04: /* Interrupt Control State.  */
          if (value & (1 << 31)) {
 -            armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
 +            armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
          }
          if (value & (1 << 28)) {
 -            armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
 +            armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
          } else if (value & (1 << 27)) {
 -            armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
 +            armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
          }
          if (value & (1 << 26)) {
 -            armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
 +            armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
          } else if (value & (1 << 25)) {
 -            armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
 +            armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
          }
          break;
      case 0xd08: /* Vector Table Offset.  */
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
      {
          int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
          if (excnum < s->num_irq) {
 -            armv7m_nvic_set_pending(s, excnum);
 +            armv7m_nvic_set_pending(s, excnum, false);
          }
          break;
      }
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
          /* SysTick just asked us to pend its exception.
           * (This is different from an external interrupt line's
           * behaviour.)
 +         * TODO: when we implement the banked systicks we must make
 +         * this pend the correct banked exception.
           */
 -        armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
 +        armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);
      }
  }
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
-          * stack, directly take a usage fault on the current stack.
+       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
-          */
+ };
-         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
--        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
++/*
-+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
++ * Check for traps to RAS registers, which are controlled
-         v7m_exception_taken(cpu, excret);
++ * by HCR_EL2.TERR and SCR_EL3.TERR.
-         qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
++ */
-                       "stackframe: failed exception return integrity check\n");
++static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
-@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
++                                  bool isread)
-      * exception return excret specified then this is a UsageFault.
++{
-      */
++    int el = arm_current_el(env);
-     if (return_to_handler != arm_v7m_is_handler_mode(env)) {
++
--        /* Take an INVPC UsageFault by pushing the stack again. */
++    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
--        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
++        return CP_ACCESS_TRAP_EL2;
-+        /* Take an INVPC UsageFault by pushing the stack again.
++    }
-+         * TODO: the v8M version of this code should target the
++    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
-+         * background state for this exception.
++        return CP_ACCESS_TRAP_EL3;
-+         */
++    }
-+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);
++    return CP_ACCESS_OK;
-         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
++}
-         v7m_push_stack(cpu);
++
-         v7m_exception_taken(cpu, excret);
++static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
++{
-        handle it.  */
++    int el = arm_current_el(env);
-     switch (cs->exception_index) {
++
-     case EXCP_UDEF:
++    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
--        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
++        return env->cp15.vdisr_el2;
-+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
++    }
-         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
++    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
-         break;
++        return 0; /* RAZ/WI */
-     case EXCP_NOCP:
++    }
--        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
++    return env->cp15.disr_el1;
-+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
++}
-         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
++
-         break;
++static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
-     case EXCP_INVSTATE:
++{
--        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
++    int el = arm_current_el(env);
-+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
++
-         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
++    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
-         break;
++        env->cp15.vdisr_el2 = val;
-     case EXCP_SWI:
++        return;
-         /* The PC already points to the next instruction.  */
++    }
--        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
++    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
-+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
++        return; /* RAZ/WI */
-         break;
++    }
-     case EXCP_PREFETCH_ABORT:
++    env->cp15.disr_el1 = val;
-     case EXCP_DATA_ABORT:
++}
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
++
-                               env->v7m.bfar);
++/*
-                 break;
++ * Minimal RAS implementation with no Error Records.
-             }
++ * Which means that all of the Error Record registers:
--            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
++ *   ERXADDR_EL1
-+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
++ *   ERXCTLR_EL1
-             break;
++ *   ERXFR_EL1
-         default:
++ *   ERXMISC0_EL1
-             /* All other FSR values are either MPU faults or "can't happen
++ *   ERXMISC1_EL1
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
++ *   ERXMISC2_EL1
-                               env->v7m.mmfar[env->v7m.secure]);
++ *   ERXMISC3_EL1
-                 break;
++ *   ERXPFGCDN_EL1  (RASv1p1)
-             }
++ *   ERXPFGCTL_EL1  (RASv1p1)
--            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
++ *   ERXPFGF_EL1    (RASv1p1)
-+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,
++ *   ERXSTATUS_EL1
-+                                    env->v7m.secure);
++ * and
-             break;
++ *   ERRSELR_EL1
-         }
++ * may generate UNDEFINED, which is the effect we get by not
-         break;
++ * listing them at all.
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
++ */
-                 return;
++static const ARMCPRegInfo minimal_ras_reginfo[] = {
-             }
++    { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
-         }
++      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
--        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
++      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
-+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
++      .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
-         break;
++    { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
-     case EXCP_IRQ:
++      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
-         break;
++      .access = PL1_R, .accessfn = access_terr,
-diff --git a/hw/intc/trace-events b/hw/intc/trace-events
++      .type = ARM_CP_CONST, .resetvalue = 0 },
-index XXXXXXX..XXXXXXX 100644
++    { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
---- a/hw/intc/trace-events
++      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
-+++ b/hw/intc/trace-events
++      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
-@@ -XXX,XX +XXX,XX @@ nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
++    { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
- nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
++      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
- nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
++      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
- nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
++};
--nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)"
++
--nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)"
+ /* Return the exception level to which exceptions should be taken
-+nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
+  * via SVEAccessTrap.  If an exception should be routed through
-+nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
+  * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
- nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
- nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
+     if (cpu_isar_feature(aa64_ssbs, cpu)) {
- nvic_complete_irq(int irq) "NVIC complete IRQ %d"
+         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
      }
 +    if (cpu_isar_feature(any_ras, cpu)) {
 +        define_arm_cp_regs(cpu, minimal_ras_reginfo);
 +    }
      if (cpu_isar_feature(aa64_vh, cpu) ||
          cpu_isar_feature(aa64_debugv8p2, cpu)) {
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 01/31] target/arm: Implement MSR/MRS access to NS banked registers
+[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
-In v8M the MSR and MRS instructions have extra register value
+From: Richard Henderson <richard.henderson@linaro.org>
 encodings to allow secure code to access the non-secure banked
 version of various special registers.
-(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because
+Enable writes to the TERR and TEA bits when RAS is enabled.
-we don't currently implement the stack limit registers at all.)
+These bits are otherwise RES0.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++
+ target/arm/helper.c | 9 +++++++++
-file changed, 110 insertions(+)
+file changed, 9 insertions(+)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
+@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
-         break;
+         }
-     case 20: /* CONTROL */
+         valid_mask &= ~SCR_NET;
-         return env->v7m.control[env->v7m.secure];
-+    case 0x94: /* CONTROL_NS */
++        if (cpu_isar_feature(aa64_ras, cpu)) {
-+        /* We have to handle this here because unprivileged Secure code
++            valid_mask |= SCR_TERR;
 +         * can read the NS CONTROL register.
 +         */
 +        if (!env->v7m.secure) {
 +            return 0;
 +        }
-+        return env->v7m.control[M_REG_NS];
+         if (cpu_isar_feature(aa64_lor, cpu)) {
              valid_mask |= SCR_TLOR;
          }
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          }
      } else {
          valid_mask &= ~(SCR_RW | SCR_ST);
 +        if (cpu_isar_feature(aa32_ras, cpu)) {
 +            valid_mask |= SCR_TERR;
 +        }
      }
-     if (el == 0) {
+     if (!arm_feature(env, ARM_FEATURE_EL2)) {
-         return 0; /* unprivileged reads others as zero */
+@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
-     }
+         if (cpu_isar_feature(aa64_vh, cpu)) {
+             valid_mask |= HCR_E2H;
-+    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+         }
-+        switch (reg) {
++        if (cpu_isar_feature(aa64_ras, cpu)) {
-+        case 0x88: /* MSP_NS */
++            valid_mask |= HCR_TERR | HCR_TEA;
 +            if (!env->v7m.secure) {
 +                return 0;
 +            }
 +            return env->v7m.other_ss_msp;
 +        case 0x89: /* PSP_NS */
 +            if (!env->v7m.secure) {
 +                return 0;
 +            }
 +            return env->v7m.other_ss_psp;
 +        case 0x90: /* PRIMASK_NS */
 +            if (!env->v7m.secure) {
 +                return 0;
 +            }
 +            return env->v7m.primask[M_REG_NS];
 +        case 0x91: /* BASEPRI_NS */
 +            if (!env->v7m.secure) {
 +                return 0;
 +            }
 +            return env->v7m.basepri[M_REG_NS];
 +        case 0x93: /* FAULTMASK_NS */
 +            if (!env->v7m.secure) {
 +                return 0;
 +            }
 +            return env->v7m.faultmask[M_REG_NS];
 +        case 0x98: /* SP_NS */
 +        {
 +            /* This gives the non-secure SP selected based on whether we're
 +             * currently in handler mode or not, using the NS CONTROL.SPSEL.
 +             */
 +            bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
 +
 +            if (!env->v7m.secure) {
 +                return 0;
 +            }
 +            if (!arm_v7m_is_handler_mode(env) && spsel) {
 +                return env->v7m.other_ss_psp;
 +            } else {
 +                return env->v7m.other_ss_msp;
 +            }
 +        }
-+        default:
+         if (cpu_isar_feature(aa64_lor, cpu)) {
-+            break;
+             valid_mask |= HCR_TLOR;
-+        }
+         }
 +    }
 +
      switch (reg) {
      case 8: /* MSP */
          return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
          return;
      }
 +    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 +        switch (reg) {
 +        case 0x88: /* MSP_NS */
 +            if (!env->v7m.secure) {
 +                return;
 +            }
 +            env->v7m.other_ss_msp = val;
 +            return;
 +        case 0x89: /* PSP_NS */
 +            if (!env->v7m.secure) {
 +                return;
 +            }
 +            env->v7m.other_ss_psp = val;
 +            return;
 +        case 0x90: /* PRIMASK_NS */
 +            if (!env->v7m.secure) {
 +                return;
 +            }
 +            env->v7m.primask[M_REG_NS] = val & 1;
 +            return;
 +        case 0x91: /* BASEPRI_NS */
 +            if (!env->v7m.secure) {
 +                return;
 +            }
 +            env->v7m.basepri[M_REG_NS] = val & 0xff;
 +            return;
 +        case 0x93: /* FAULTMASK_NS */
 +            if (!env->v7m.secure) {
 +                return;
 +            }
 +            env->v7m.faultmask[M_REG_NS] = val & 1;
 +            return;
 +        case 0x98: /* SP_NS */
 +        {
 +            /* This gives the non-secure SP selected based on whether we're
 +             * currently in handler mode or not, using the NS CONTROL.SPSEL.
 +             */
 +            bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
 +
 +            if (!env->v7m.secure) {
 +                return;
 +            }
 +            if (!arm_v7m_is_handler_mode(env) && spsel) {
 +                env->v7m.other_ss_psp = val;
 +            } else {
 +                env->v7m.other_ss_msp = val;
 +            }
 +            return;
 +        }
 +        default:
 +            break;
 +        }
 +    }
 +
      switch (reg) {
      case 0 ... 7: /* xPSR sub-fields */
          /* only APSR is actually writable */
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 19/31] nvic: Support banked exceptions in acknowledge and complete
+[PULL 16/32] target/arm: Implement virtual SError exceptions
-Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq()
+From: Richard Henderson <richard.henderson@linaro.org>
 to handle banked exceptions:
  * acknowledge needs to use the correct vector, which may be
    in sec_vectors[]
  * acknowledge needs to return to its caller whether the
    exception should be taken to secure or non-secure state
  * complete needs its caller to tell it whether the exception
    being completed is a secure one or not
+Virtual SError exceptions are raised by setting HCR_EL2.VSE,
+and are routed to EL1 just like other virtual exceptions.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/cpu.h      | 15 +++++++++++++--
+ target/arm/cpu.h       |  2 ++
- hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++++------
+ target/arm/internals.h |  8 ++++++++
- target/arm/helper.c   |  8 +++++---
+ target/arm/syndrome.h  |  5 +++++
- hw/intc/trace-events  |  4 ++--
+ target/arm/cpu.c       | 38 +++++++++++++++++++++++++++++++++++++-
-files changed, 40 insertions(+), 13 deletions(-)
+ target/arm/helper.c    | 40 +++++++++++++++++++++++++++++++++++++++-
 files changed, 91 insertions(+), 2 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+@@ -XXX,XX +XXX,XX @@
-  * of architecturally banked exceptions.
+ #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
  #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
  #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
 +#define EXCP_VSERR          24
  /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
  #define ARMV7M_EXCP_RESET   1
@@ -XXX,XX +XXX,XX @@ enum {
  #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
  #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
  /* The usual mapping for an AArch64 system register to its AArch32
   * counterpart is for the 32 bit world to have access to the lower
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
   */
- void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
+ void arm_cpu_update_vfiq(ARMCPU *cpu);
--void armv7m_nvic_acknowledge_irq(void *opaque);
 +/**
-+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
++ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
 + * @opaque: the NVIC
 + *
-+ * Move the current highest priority pending exception from the pending
++ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
-+ * state to the active state, and update v7m.exception to indicate that
++ * following a change to the HCR_EL2.VSE bit.
 + * it is the exception currently being handled.
 + *
 + * Returns: true if exception should be taken to Secure state, false for NS
 + */
-+bool armv7m_nvic_acknowledge_irq(void *opaque);
++void arm_cpu_update_vserr(ARMCPU *cpu);
 +
  /**
-  * armv7m_nvic_complete_irq: complete specified interrupt or exception
+  * arm_mmu_idx_el:
-  * @opaque: the NVIC
+  * @env: The cpu environment
-  * @irq: the exception number to complete
+diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
-+ * @secure: true if this exception was secure
+index XXXXXXX..XXXXXXX 100644
-  *
+--- a/target/arm/syndrome.h
-  * Returns: -1 if the irq was not active
++++ b/target/arm/syndrome.h
-  *           1 if completing this irq brought us back to base (no active irqs)
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
-  *           0 if there is still an irq active after this one was completed
+     return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
-  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
+ }
-  */
--int armv7m_nvic_complete_irq(void *opaque, int irq);
++static inline uint32_t syn_serror(uint32_t extra)
-+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
++{
- /**
++    return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
-  * armv7m_nvic_raw_execution_priority: return the raw execution priority
++}
-  * @opaque: the NVIC
++
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+ #endif /* TARGET_ARM_SYNDROME_H */
-index XXXXXXX..XXXXXXX 100644
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
---- a/hw/intc/armv7m_nvic.c
+index XXXXXXX..XXXXXXX 100644
-+++ b/hw/intc/armv7m_nvic.c
+--- a/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
++++ b/target/arm/cpu.c
- }
+@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
+     return (cpu->power_state != PSCI_OFF)
- /* Make pending IRQ active.  */
+         && cs->interrupt_request &
--void armv7m_nvic_acknowledge_irq(void *opaque)
+         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
-+bool armv7m_nvic_acknowledge_irq(void *opaque)
+-         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
 +         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
           | CPU_INTERRUPT_EXITTB);
  }
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
              return false;
          }
          return !(env->daif & PSTATE_I);
 +    case EXCP_VSERR:
 +        if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
 +            /* VIRQs are only taken when hypervized.  */
 +            return false;
 +        }
 +        return !(env->daif & PSTATE_A);
      default:
          g_assert_not_reached();
      }
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
              goto found;
          }
      }
 +    if (interrupt_request & CPU_INTERRUPT_VSERR) {
 +        excp_idx = EXCP_VSERR;
 +        target_el = 1;
 +        if (arm_excp_unmasked(cs, excp_idx, target_el,
 +                              cur_el, secure, hcr_el2)) {
 +            /* Taking a virtual abort clears HCR_EL2.VSE */
 +            env->cp15.hcr_el2 &= ~HCR_VSE;
 +            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
 +            goto found;
 +        }
 +    }
      return false;
   found:
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
      }
  }
 +void arm_cpu_update_vserr(ARMCPU *cpu)
 +{
 +    /*
 +     * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
 +     */
 +    CPUARMState *env = &cpu->env;
 +    CPUState *cs = CPU(cpu);
 +
 +    bool new_state = env->cp15.hcr_el2 & HCR_VSE;
 +
 +    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
 +        if (new_state) {
 +            cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
 +        } else {
 +            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
 +        }
 +    }
 +}
 +
  #ifndef CONFIG_USER_ONLY
  static void arm_cpu_set_irq(void *opaque, int irq, int level)
  {
-     NVICState *s = (NVICState *)opaque;
-     CPUARMState *env = &s->cpu->env;
-     const int pending = s->vectpending;
-     const int running = nvic_exec_prio(s);
-     VecInfo *vec;
-+    bool targets_secure;
-     assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
--    vec = &s->vectors[pending];
-+    if (s->vectpending_is_s_banked) {
-+        vec = &s->sec_vectors[pending];
-+        targets_secure = true;
-+    } else {
-+        vec = &s->vectors[pending];
-+        targets_secure = !exc_is_banked(s->vectpending) &&
-+            exc_targets_secure(s, s->vectpending);
-+    }
-     assert(vec->enabled);
-     assert(vec->pending);
-     assert(s->vectpending_prio < running);
--    trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
-+    trace_nvic_acknowledge_irq(pending, s->vectpending_prio, targets_secure);
-     vec->active = 1;
-     vec->pending = 0;
-@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
-     env->v7m.exception = s->vectpending;
-     nvic_irq_update(s);
-+
-+    return targets_secure;
- }
--int armv7m_nvic_complete_irq(void *opaque, int irq)
-+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
- {
-     NVICState *s = (NVICState *)opaque;
-     VecInfo *vec;
-@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq)
-     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
--    vec = &s->vectors[irq];
-+    if (secure && exc_is_banked(irq)) {
-+        vec = &s->sec_vectors[irq];
-+    } else {
-+        vec = &s->vectors[irq];
-+    }
--    trace_nvic_complete_irq(irq);
-+    trace_nvic_complete_irq(irq, secure);
-     if (!vec->active) {
-         /* Tell the caller this was an illegal exception return */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
      bool return_to_sp_process = false;
      bool return_to_handler = false;
      bool rettobase = false;
 +    bool exc_secure = false;
      /* We can only get here from an EXCP_EXCEPTION_EXIT, and
       * gen_bx_excret() enforces the architectural rule
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
           * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
           */
          if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 -            int es = excret & R_V7M_EXCRET_ES_MASK;
 +            exc_secure = excret & R_V7M_EXCRET_ES_MASK;
              if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
 -                env->v7m.faultmask[es] = 0;
 +                env->v7m.faultmask[exc_secure] = 0;
              }
          } else {
              env->v7m.faultmask[M_REG_NS] = 0;
          }
      }
--    switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {
+-    /* External aborts are not possible in QEMU so A bit is always clear */
-+    switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception,
++    if (hcr_el2 & HCR_AMO) {
-+                                     exc_secure)) {
++        if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
-     case -1:
++            ret |= CPSR_A;
-         /* attempt to exit an exception that isn't active */
++        }
-         ufault = true;
++    }
-diff --git a/hw/intc/trace-events b/hw/intc/trace-events
++
-index XXXXXXX..XXXXXXX 100644
+     return ret;
---- a/hw/intc/trace-events
+ }
-+++ b/hw/intc/trace-events
-@@ -XXX,XX +XXX,XX @@ nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
+@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
- nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
+     g_assert(qemu_mutex_iothread_locked());
- nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
+     arm_cpu_update_virq(cpu);
- nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
+     arm_cpu_update_vfiq(cpu);
--nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
++    arm_cpu_update_vserr(cpu);
--nvic_complete_irq(int irq) "NVIC complete IRQ %d"
+ }
-+nvic_acknowledge_irq(int irq, int prio, bool targets_secure) "NVIC acknowledge IRQ: %d now active (prio %d targets_secure %d)"
-+nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
+ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
- nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
+@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
- nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
+             [EXCP_LSERR] = "v8M LSERR UsageFault",
- nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
+             [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
              [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
 +            [EXCP_VSERR] = "Virtual SERR",
          };
          if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
          mask = CPSR_A | CPSR_I | CPSR_F;
          offset = 4;
          break;
 +    case EXCP_VSERR:
 +        {
 +            /*
 +             * Note that this is reported as a data abort, but the DFAR
 +             * has an UNKNOWN value.  Construct the SError syndrome from
 +             * AET and ExT fields.
 +             */
 +            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
 +
 +            if (extended_addresses_enabled(env)) {
 +                env->exception.fsr = arm_fi_to_lfsc(&fi);
 +            } else {
 +                env->exception.fsr = arm_fi_to_sfsc(&fi);
 +            }
 +            env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
 +            A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
 +            qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
 +                          env->exception.fsr);
 +
 +            new_mode = ARM_CPU_MODE_ABT;
 +            addr = 0x10;
 +            mask = CPSR_A | CPSR_I;
 +            offset = 8;
 +        }
 +        break;
      case EXCP_SMC:
          new_mode = ARM_CPU_MODE_MON;
          addr = 0x08;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
      case EXCP_VFIQ:
          addr += 0x100;
          break;
 +    case EXCP_VSERR:
 +        addr += 0x180;
 +        /* Construct the SError syndrome from IDS and ISS fields. */
 +        env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
 +        env->cp15.esr_el[new_el] = env->exception.syndrome;
 +        break;
      default:
          cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
      }
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 29/31] msf2: Add Smartfusion2 SPI controller
+[PULL 17/32] target/arm: Implement ESB instruction
-From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Modelled Microsemi's Smartfusion2 SPI controller.
+Check for and defer any pending virtual SError.
-Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
 Message-id: 20170920201737.25723-4-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/ssi/Makefile.objs     |   1 +
+ target/arm/helper.h        |  1 +
- include/hw/ssi/mss-spi.h |  58 +++++++
+ target/arm/a32.decode      | 16 ++++++++------
- hw/ssi/mss-spi.c         | 404 +++++++++++++++++++++++++++++++++++++++++++++++
+ target/arm/t32.decode      | 18 ++++++++--------
-files changed, 463 insertions(+)
+ target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
- create mode 100644 include/hw/ssi/mss-spi.h
+ target/arm/translate-a64.c | 17 +++++++++++++++
- create mode 100644 hw/ssi/mss-spi.c
+ target/arm/translate.c     | 23 ++++++++++++++++++++
 files changed, 103 insertions(+), 15 deletions(-)
-diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
+diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/Makefile.objs
+--- a/target/arm/helper.h
-+++ b/hw/ssi/Makefile.objs
++++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
- common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
+ DEF_HELPER_1(yield, void, env)
- common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
+ DEF_HELPER_1(pre_hvc, void, env)
- common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
+ DEF_HELPER_2(pre_smc, void, env, i32)
-+common-obj-$(CONFIG_MSF2) += mss-spi.o
++DEF_HELPER_1(vesb, void, env)
- obj-$(CONFIG_OMAP) += omap_spi.o
+ DEF_HELPER_3(cpsr_write, void, env, i32, i32)
- obj-$(CONFIG_IMX) += imx_spi.o
+ DEF_HELPER_2(cpsr_write_eret, void, env, i32)
-diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
+diff --git a/target/arm/a32.decode b/target/arm/a32.decode
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/arm/a32.decode
---- /dev/null
++++ b/target/arm/a32.decode
-+++ b/include/hw/ssi/mss-spi.h
+@@ -XXX,XX +XXX,XX @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
-@@ -XXX,XX +XXX,XX @@
  {
    {
 -    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
 -    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
 -    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
 +    [
 +      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
 +      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
 +      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 -    # TODO: Implement SEV, SEVL; may help SMP performance.
 -    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
 -    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
 +      # TODO: Implement SEV, SEVL; may help SMP performance.
 +      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
 +      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
 +
 +      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
 +    ]
      # The canonical nop ends in 00000000, but the whole of the
      # rest of the space executes as nop if otherwise unsupported.
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
    [
      # Hints, and CPS
      {
 -      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
 -      WFE        1111 0011 1010 1111 1000 0000 0000 0010
 -      WFI        1111 0011 1010 1111 1000 0000 0000 0011
 +      [
 +        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
 +        WFE      1111 0011 1010 1111 1000 0000 0000 0010
 +        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 -      # TODO: Implement SEV, SEVL; may help SMP performance.
 -      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
 -      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
 +        # TODO: Implement SEV, SEVL; may help SMP performance.
 +        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
 +        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 -      # For M-profile minimal-RAS ESB can be a NOP, which is the
 -      # default behaviour since it is in the hint space.
 -      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +        ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +      ]
        # The canonical nop ends in 0000 0000, but the whole rest
        # of the space is "reserved hint, behaves as nop".
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/op_helper.c
 +++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                       access_type, mmu_idx, ra);
      }
  }
 +
 +/*
-+ * Microsemi SmartFusion2 SPI
++ * This function corresponds to AArch64.vESBOperation().
-+ *
++ * Note that the AArch32 version is not functionally different.
 + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
-+
++void HELPER(vesb)(CPUARMState *env)
 +#ifndef HW_MSS_SPI_H
 +#define HW_MSS_SPI_H
 +
 +#include "hw/sysbus.h"
 +#include "hw/ssi/ssi.h"
 +#include "qemu/fifo32.h"
 +
 +#define TYPE_MSS_SPI   "mss-spi"
 +#define MSS_SPI(obj)   OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
 +
 +#define R_SPI_MAX             16
 +
 +typedef struct MSSSpiState {
 +    SysBusDevice parent_obj;
 +
 +    MemoryRegion mmio;
 +
 +    qemu_irq irq;
 +
 +    qemu_irq cs_line;
 +
 +    SSIBus *spi;
 +
 +    Fifo32 rx_fifo;
 +    Fifo32 tx_fifo;
 +
 +    int fifo_depth;
 +    uint32_t frame_count;
 +    bool enabled;
 +
 +    uint32_t regs[R_SPI_MAX];
 +} MSSSpiState;
 +
 +#endif /* HW_MSS_SPI_H */
 diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/ssi/mss-spi.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Block model of SPI controller present in
 + * Microsemi's SmartFusion2 and SmartFusion SoCs.
 + *
 + * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/ssi/mss-spi.h"
 +#include "qemu/log.h"
 +
 +#ifndef MSS_SPI_ERR_DEBUG
 +#define MSS_SPI_ERR_DEBUG   0
 +#endif
 +
 +#define DB_PRINT_L(lvl, fmt, args...) do { \
 +    if (MSS_SPI_ERR_DEBUG >= lvl) { \
 +        qemu_log("%s: " fmt "\n", __func__, ## args); \
 +    } \
 +} while (0);
 +
 +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
 +
 +#define FIFO_CAPACITY         32
 +
 +#define R_SPI_CONTROL         0
 +#define R_SPI_DFSIZE          1
 +#define R_SPI_STATUS          2
 +#define R_SPI_INTCLR          3
 +#define R_SPI_RX              4
 +#define R_SPI_TX              5
 +#define R_SPI_CLKGEN          6
 +#define R_SPI_SS              7
 +#define R_SPI_MIS             8
 +#define R_SPI_RIS             9
 +
 +#define S_TXDONE             (1 << 0)
 +#define S_RXRDY              (1 << 1)
 +#define S_RXCHOVRF           (1 << 2)
 +#define S_RXFIFOFUL          (1 << 4)
 +#define S_RXFIFOFULNXT       (1 << 5)
 +#define S_RXFIFOEMP          (1 << 6)
 +#define S_RXFIFOEMPNXT       (1 << 7)
 +#define S_TXFIFOFUL          (1 << 8)
 +#define S_TXFIFOFULNXT       (1 << 9)
 +#define S_TXFIFOEMP          (1 << 10)
 +#define S_TXFIFOEMPNXT       (1 << 11)
 +#define S_FRAMESTART         (1 << 12)
 +#define S_SSEL               (1 << 13)
 +#define S_ACTIVE             (1 << 14)
 +
 +#define C_ENABLE             (1 << 0)
 +#define C_MODE               (1 << 1)
 +#define C_INTRXDATA          (1 << 4)
 +#define C_INTTXDATA          (1 << 5)
 +#define C_INTRXOVRFLO        (1 << 6)
 +#define C_SPS                (1 << 26)
 +#define C_BIGFIFO            (1 << 29)
 +#define C_RESET              (1 << 31)
 +
 +#define FRAMESZ_MASK         0x1F
 +#define FMCOUNT_MASK         0x00FFFF00
 +#define FMCOUNT_SHIFT        8
 +
 +static void txfifo_reset(MSSSpiState *s)
 +{
-+    fifo32_reset(&s->tx_fifo);
++    /*
-+
++     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
-+    s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
++     * and will return HCR_EL2.VSE == 0, so nothing happens.
-+    s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
++     */
-+}
++    uint64_t hcr = arm_hcr_el2_eff(env);
-+
++    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
-+static void rxfifo_reset(MSSSpiState *s)
++    bool pending = enabled && (hcr & HCR_VSE);
-+{
++    bool masked  = (env->daif & PSTATE_A);
-+    fifo32_reset(&s->rx_fifo);
++
-+
++    /* If VSE pending and masked, defer the exception.  */
-+    s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
++    if (pending && masked) {
-+    s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
++        uint32_t syndrome;
-+}
++
-+
++        if (arm_el_is_aa64(env, 1)) {
-+static void set_fifodepth(MSSSpiState *s)
++            /* Copy across IDS and ISS from VSESR. */
-+{
++            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
-+    unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
++        } else {
-+
++            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
-+    if (size <= 8) {
++
-+        s->fifo_depth = 32;
++            if (extended_addresses_enabled(env)) {
-+    } else if (size <= 16) {
++                syndrome = arm_fi_to_lfsc(&fi);
-+        s->fifo_depth = 16;
++            } else {
-+    } else if (size <= 32) {
++                syndrome = arm_fi_to_sfsc(&fi);
-+        s->fifo_depth = 8;
++            }
-+    } else {
++            /* Copy across AET and ExT from VSESR. */
-+        s->fifo_depth = 4;
++            syndrome |= env->cp15.vsesr_el2 & 0xd000;
 +        }
 +
 +        /* Set VDISR_EL2.A along with the syndrome. */
 +        env->cp15.vdisr_el2 = syndrome | (1u << 31);
 +
 +        /* Clear pending virtual SError */
 +        env->cp15.hcr_el2 &= ~HCR_VSE;
 +        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
 +    }
 +}
-+
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-+static void update_mis(MSSSpiState *s)
+index XXXXXXX..XXXXXXX 100644
-+{
+--- a/target/arm/translate-a64.c
-+    uint32_t reg = s->regs[R_SPI_CONTROL];
++++ b/target/arm/translate-a64.c
-+    uint32_t tmp;
+@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
-+
+             gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
-+    /*
+         }
-+     * form the Control register interrupt enable bits
+         break;
-+     * same as RIS, MIS and Interrupt clear registers for simplicity
++    case 0b10000: /* ESB */
-+     */
++        /* Without RAS, we must implement this as NOP. */
-+    tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
++        if (dc_isar_feature(aa64_ras, s)) {
-+           ((reg & C_INTTXDATA) >> 5);
++            /*
-+    s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
++             * QEMU does not have a source of physical SErrors,
-+}
++             * so we are only concerned with virtual SErrors.
-+
++             * The pseudocode in the ARM for this case is
-+static void spi_update_irq(MSSSpiState *s)
++             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
-+{
++             *      AArch64.vESBOperation();
-+    int irq;
++             * Most of the condition can be evaluated at translation time.
-+
++             * Test for EL2 present, and defer test for SEL2 to runtime.
-+    update_mis(s);
++             */
-+    irq = !!(s->regs[R_SPI_MIS]);
++            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
-+
++                gen_helper_vesb(cpu_env);
-+    qemu_set_irq(s->irq, irq);
++            }
 +}
 +
 +static void mss_spi_reset(DeviceState *d)
 +{
 +    MSSSpiState *s = MSS_SPI(d);
 +
 +    memset(s->regs, 0, sizeof s->regs);
 +    s->regs[R_SPI_CONTROL] = 0x80000102;
 +    s->regs[R_SPI_DFSIZE] = 0x4;
 +    s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
 +    s->regs[R_SPI_CLKGEN] = 0x7;
 +    s->regs[R_SPI_RIS] = 0x0;
 +
 +    s->fifo_depth = 4;
 +    s->frame_count = 1;
 +    s->enabled = false;
 +
 +    rxfifo_reset(s);
 +    txfifo_reset(s);
 +}
 +
 +static uint64_t
 +spi_read(void *opaque, hwaddr addr, unsigned int size)
 +{
 +    MSSSpiState *s = opaque;
 +    uint32_t ret = 0;
 +
 +    addr >>= 2;
 +    switch (addr) {
 +    case R_SPI_RX:
 +        s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
 +        s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
 +        ret = fifo32_pop(&s->rx_fifo);
 +        if (fifo32_is_empty(&s->rx_fifo)) {
 +            s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
 +        }
 +        break;
-+
+     case 0b11000: /* PACIAZ */
-+    case R_SPI_MIS:
+         if (s->pauth_active) {
-+        update_mis(s);
+             gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
-+        ret = s->regs[R_SPI_MIS];
+diff --git a/target/arm/translate.c b/target/arm/translate.c
-+        break;
+index XXXXXXX..XXXXXXX 100644
-+
+--- a/target/arm/translate.c
-+    default:
++++ b/target/arm/translate.c
-+        if (addr < ARRAY_SIZE(s->regs)) {
+@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
-+            ret = s->regs[addr];
+     return true;
-+        } else {
+ }
-+            qemu_log_mask(LOG_GUEST_ERROR,
-+                         "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
++static bool trans_ESB(DisasContext *s, arg_ESB *a)
 +                         addr * 4);
 +            return ret;
 +        }
 +        break;
 +    }
 +
 +    DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
 +    spi_update_irq(s);
 +    return ret;
 +}
 +
 +static void assert_cs(MSSSpiState *s)
 +{
-+    qemu_set_irq(s->cs_line, 0);
-+}
-+
-+static void deassert_cs(MSSSpiState *s)
-+{
-+    qemu_set_irq(s->cs_line, 1);
-+}
-+
-+static void spi_flush_txfifo(MSSSpiState *s)
-+{
-+    uint32_t tx;
-+    uint32_t rx;
-+    bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
-+
 +    /*
-+     * Chip Select(CS) is automatically controlled by this controller.
++     * For M-profile, minimal-RAS ESB can be a NOP.
-+     * If SPS bit is set in Control register then CS is asserted
++     * Without RAS, we must implement this as NOP.
 +     * until all the frames set in frame count of Control register are
 +     * transferred. If SPS is not set then CS pulses between frames.
 +     * Note that Slave Select register specifies which of the CS line
 +     * has to be controlled automatically by controller. Bits SS[7:1] are for
 +     * masters in FPGA fabric since we model only Microcontroller subsystem
 +     * of Smartfusion2 we control only one CS(SS[0]) line.
 +     */
-+    while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
++    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
-+        assert_cs(s);
++        /*
-+
++         * QEMU does not have a source of physical SErrors,
-+        s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
++         * so we are only concerned with virtual SErrors.
-+
++         * The pseudocode in the ARM for this case is
-+        tx = fifo32_pop(&s->tx_fifo);
++         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
-+        DB_PRINT("data tx:0x%" PRIx32, tx);
++         *      AArch32.vESBOperation();
-+        rx = ssi_transfer(s->spi, tx);
++         * Most of the condition can be evaluated at translation time.
-+        DB_PRINT("data rx:0x%" PRIx32, rx);
++         * Test for EL2 present, and defer test for SEL2 to runtime.
-+
++         */
-+        if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
++        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
-+            s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
++            gen_helper_vesb(cpu_env);
 +            s->regs[R_SPI_RIS] |= S_RXCHOVRF;
 +        } else {
 +            fifo32_push(&s->rx_fifo, rx);
 +            s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
 +            if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
 +                s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
 +            } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
 +                s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
 +            }
 +        }
 +        s->frame_count--;
 +        if (!sps) {
 +            deassert_cs(s);
 +        }
 +    }
-+
++    return true;
 +    if (!s->frame_count) {
 +        s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
 +                            FMCOUNT_SHIFT;
 +        deassert_cs(s);
 +        s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
 +        s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
 +   }
 +}
 +
-+static void spi_write(void *opaque, hwaddr addr,
+ static bool trans_NOP(DisasContext *s, arg_NOP *a)
-+            uint64_t val64, unsigned int size)
+ {
-+{
+     return true;
 +    MSSSpiState *s = opaque;
 +    uint32_t value = val64;
 +
 +    DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
 +    addr >>= 2;
 +
 +    switch (addr) {
 +    case R_SPI_TX:
 +        /* adding to already full FIFO */
 +        if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
 +            break;
 +        }
 +        s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
 +        fifo32_push(&s->tx_fifo, value);
 +        if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
 +            s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
 +        } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
 +            s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
 +        }
 +        if (s->enabled) {
 +            spi_flush_txfifo(s);
 +        }
 +        break;
 +
 +    case R_SPI_CONTROL:
 +        s->regs[R_SPI_CONTROL] = value;
 +        if (value & C_BIGFIFO) {
 +            set_fifodepth(s);
 +        } else {
 +            s->fifo_depth = 4;
 +        }
 +        s->enabled = value & C_ENABLE;
 +        s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
 +        if (value & C_RESET) {
 +            mss_spi_reset(DEVICE(s));
 +        }
 +        break;
 +
 +    case R_SPI_DFSIZE:
 +        if (s->enabled) {
 +            break;
 +        }
 +        s->regs[R_SPI_DFSIZE] = value;
 +        break;
 +
 +    case R_SPI_INTCLR:
 +        s->regs[R_SPI_INTCLR] = value;
 +        if (value & S_TXDONE) {
 +            s->regs[R_SPI_RIS] &= ~S_TXDONE;
 +        }
 +        if (value & S_RXRDY) {
 +            s->regs[R_SPI_RIS] &= ~S_RXRDY;
 +        }
 +        if (value & S_RXCHOVRF) {
 +            s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
 +        }
 +        break;
 +
 +    case R_SPI_MIS:
 +    case R_SPI_STATUS:
 +    case R_SPI_RIS:
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                         "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
 +                         __func__, addr * 4);
 +        break;
 +
 +    default:
 +        if (addr < ARRAY_SIZE(s->regs)) {
 +            s->regs[addr] = value;
 +        } else {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                         "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
 +                         addr * 4);
 +        }
 +        break;
 +    }
 +
 +    spi_update_irq(s);
 +}
 +
 +static const MemoryRegionOps spi_ops = {
 +    .read = spi_read,
 +    .write = spi_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 1,
 +        .max_access_size = 4
 +    }
 +};
 +
 +static void mss_spi_realize(DeviceState *dev, Error **errp)
 +{
 +    MSSSpiState *s = MSS_SPI(dev);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +
 +    s->spi = ssi_create_bus(dev, "spi");
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +    ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
 +    sysbus_init_irq(sbd, &s->cs_line);
 +
 +    memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
 +                          TYPE_MSS_SPI, R_SPI_MAX * 4);
 +    sysbus_init_mmio(sbd, &s->mmio);
 +
 +    fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
 +    fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
 +}
 +
 +static const VMStateDescription vmstate_mss_spi = {
 +    .name = TYPE_MSS_SPI,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_FIFO32(tx_fifo, MSSSpiState),
 +        VMSTATE_FIFO32(rx_fifo, MSSSpiState),
 +        VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void mss_spi_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = mss_spi_realize;
 +    dc->reset = mss_spi_reset;
 +    dc->vmsd = &vmstate_mss_spi;
 +}
 +
 +static const TypeInfo mss_spi_info = {
 +    .name           = TYPE_MSS_SPI,
 +    .parent         = TYPE_SYS_BUS_DEVICE,
 +    .instance_size  = sizeof(MSSSpiState),
 +    .class_init     = mss_spi_class_init,
 +};
 +
 +static void mss_spi_register_types(void)
 +{
 +    type_register_static(&mss_spi_info);
 +}
 +
 +type_init(mss_spi_register_types)
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 18/31] nvic: Make SHCSR banked for v8M
+[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
-Handle banking of SHCSR: some register bits are banked between
+From: Richard Henderson <richard.henderson@linaro.org>
 Secure and Non-Secure, and some are only accessible to Secure.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-19-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 221 ++++++++++++++++++++++++++++++++++++++------------
+ docs/system/arm/emulation.rst | 1 +
-file changed, 169 insertions(+), 52 deletions(-)
+ target/arm/cpu64.c            | 1 +
  target/arm/cpu_tcg.c          | 1 +
 files changed, 3 insertions(+)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/docs/system/arm/emulation.rst
-+++ b/hw/intc/armv7m_nvic.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-         val = cpu->env.v7m.ccr[attrs.secure];
+ - FEAT_PMULL (PMULL, PMULL2 instructions)
-         val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
+ - FEAT_PMUv3p1 (PMU Extensions v3.1)
-         return val;
+ - FEAT_PMUv3p4 (PMU Extensions v3.4)
--    case 0xd24: /* System Handler Status.  */
++- FEAT_RAS (Reliability, availability, and serviceability)
-+    case 0xd24: /* System Handler Control and State (SHCSR) */
+ - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
-         val = 0;
+ - FEAT_RNG (Random number generator)
--        if (s->vectors[ARMV7M_EXCP_MEM].active) {
+ - FEAT_SB (Speculation Barrier)
--            val |= (1 << 0);
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
--        }
+index XXXXXXX..XXXXXXX 100644
--        if (s->vectors[ARMV7M_EXCP_BUS].active) {
+--- a/target/arm/cpu64.c
--            val |= (1 << 1);
++++ b/target/arm/cpu64.c
--        }
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
--        if (s->vectors[ARMV7M_EXCP_USAGE].active) {
+     t = cpu->isar.id_aa64pfr0;
--            val |= (1 << 3);
+     t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
-+        if (attrs.secure) {
+     t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
-+            if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
++    t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1);       /* FEAT_RAS */
-+                val |= (1 << 0);
+     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-+            }
+     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
-+            if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {
+     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-+                val |= (1 << 2);
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-+            }
+index XXXXXXX..XXXXXXX 100644
-+            if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {
+--- a/target/arm/cpu_tcg.c
-+                val |= (1 << 3);
++++ b/target/arm/cpu_tcg.c
-+            }
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-+            if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {
-+                val |= (1 << 7);
+     t = cpu->isar.id_pfr0;
-+            }
+     t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
-+            if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {
++    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
-+                val |= (1 << 10);
+     cpu->isar.id_pfr0 = t;
-+            }
-+            if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {
+     t = cpu->isar.id_pfr2;
 +                val |= (1 << 11);
 +            }
 +            if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {
 +                val |= (1 << 12);
 +            }
 +            if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {
 +                val |= (1 << 13);
 +            }
 +            if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {
 +                val |= (1 << 15);
 +            }
 +            if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {
 +                val |= (1 << 16);
 +            }
 +            if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {
 +                val |= (1 << 18);
 +            }
 +            if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {
 +                val |= (1 << 21);
 +            }
 +            /* SecureFault is not banked but is always RAZ/WI to NS */
 +            if (s->vectors[ARMV7M_EXCP_SECURE].active) {
 +                val |= (1 << 4);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {
 +                val |= (1 << 19);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_SECURE].pending) {
 +                val |= (1 << 20);
 +            }
 +        } else {
 +            if (s->vectors[ARMV7M_EXCP_MEM].active) {
 +                val |= (1 << 0);
 +            }
 +            if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
 +                /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
 +                if (s->vectors[ARMV7M_EXCP_HARD].active) {
 +                    val |= (1 << 2);
 +                }
 +                if (s->vectors[ARMV7M_EXCP_HARD].pending) {
 +                    val |= (1 << 21);
 +                }
 +            }
 +            if (s->vectors[ARMV7M_EXCP_USAGE].active) {
 +                val |= (1 << 3);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_SVC].active) {
 +                val |= (1 << 7);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
 +                val |= (1 << 10);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
 +                val |= (1 << 11);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
 +                val |= (1 << 12);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_MEM].pending) {
 +                val |= (1 << 13);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_SVC].pending) {
 +                val |= (1 << 15);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
 +                val |= (1 << 16);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
 +                val |= (1 << 18);
 +            }
          }
 -        if (s->vectors[ARMV7M_EXCP_SVC].active) {
 -            val |= (1 << 7);
 +        if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
 +            if (s->vectors[ARMV7M_EXCP_BUS].active) {
 +                val |= (1 << 1);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_BUS].pending) {
 +                val |= (1 << 14);
 +            }
 +            if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
 +                val |= (1 << 17);
 +            }
 +            if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
 +                s->vectors[ARMV7M_EXCP_NMI].active) {
 +                /* NMIACT is not present in v7M */
 +                val |= (1 << 5);
 +            }
          }
 +
 +        /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
          if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
              val |= (1 << 8);
          }
 -        if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
 -            val |= (1 << 10);
 -        }
 -        if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
 -            val |= (1 << 11);
 -        }
 -        if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
 -            val |= (1 << 12);
 -        }
 -        if (s->vectors[ARMV7M_EXCP_MEM].pending) {
 -            val |= (1 << 13);
 -        }
 -        if (s->vectors[ARMV7M_EXCP_BUS].pending) {
 -            val |= (1 << 14);
 -        }
 -        if (s->vectors[ARMV7M_EXCP_SVC].pending) {
 -            val |= (1 << 15);
 -        }
 -        if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
 -            val |= (1 << 16);
 -        }
 -        if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
 -            val |= (1 << 17);
 -        }
 -        if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
 -            val |= (1 << 18);
 -        }
          return val;
      case 0xd28: /* Configurable Fault Status.  */
          /* The BFSR bits [15:8] are shared between security states
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
          cpu->env.v7m.ccr[attrs.secure] = value;
          break;
 -    case 0xd24: /* System Handler Control.  */
 -        s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
 -        s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
 -        s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
 -        s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
 +    case 0xd24: /* System Handler Control and State (SHCSR) */
 +        if (attrs.secure) {
 +            s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
 +            /* Secure HardFault active bit cannot be written */
 +            s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_PENDSV].active =
 +                (value & (1 << 10)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =
 +                (value & (1 << 11)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_USAGE].pending =
 +                (value & (1 << 12)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
 +            s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
 +                (value & (1 << 18)) != 0;
 +            /* SecureFault not banked, but RAZ/WI to NS */
 +            s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
 +            s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
 +            s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;
 +        } else {
 +            s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
 +            if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
 +                /* HARDFAULTPENDED is not present in v7M */
 +                s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
 +            }
 +            s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
 +            s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
 +            s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
 +            s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
 +            s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
 +            s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
 +            s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
 +            s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
 +            s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
 +        }
 +        if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
 +            s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
 +            s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
 +            s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
 +        }
 +        /* NMIACT can only be written if the write is of a zero, with
 +         * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
 +         */
 +        if (!attrs.secure && cpu->env.v7m.secure &&
 +            (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
 +            (value & (1 << 5)) == 0) {
 +            s->vectors[ARMV7M_EXCP_NMI].active = 0;
 +        }
 +        /* HARDFAULTACT can only be written if the write is of a zero
 +         * to the non-secure HardFault state by the CPU in secure state.
 +         * The only case where we can be targeting the non-secure HF state
 +         * when in secure state is if this is a write via the NS alias
 +         * and BFHFNMINS is 1.
 +         */
 +        if (!attrs.secure && cpu->env.v7m.secure &&
 +            (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
 +            (value & (1 << 2)) == 0) {
 +            s->vectors[ARMV7M_EXCP_HARD].active = 0;
 +        }
 +
 +        /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
          s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
 -        s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
 -        s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
 -        s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
 -        s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
 -        s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
 -        s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
 -        s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
 -        s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
 -        s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
          nvic_irq_update(s);
          break;
      case 0xd28: /* Configurable Fault Status.  */
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 17/31] nvic: Make ICSR banked for v8M
+[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
-The ICSR NVIC register is banked for v8M. This doesn't
+From: Richard Henderson <richard.henderson@linaro.org>
 require any new state, but it does mean that some bits
 are controlled by BFHNFNMINS and some bits must work
 with the correct banked exception. There is also a new
 in v8M PENDNMICLR bit.
+This feature is AArch64 only, and applies to physical SErrors,
+which QEMU does not implement, thus the feature is a nop.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-18-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 45 ++++++++++++++++++++++++++++++++-------------
+ docs/system/arm/emulation.rst | 1 +
-file changed, 32 insertions(+), 13 deletions(-)
+ target/arm/cpu64.c            | 1 +
 files changed, 2 insertions(+)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/docs/system/arm/emulation.rst
-+++ b/hw/intc/armv7m_nvic.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-     }
+ - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
-     case 0xd00: /* CPUID Base.  */
+ - FEAT_HPDS (Hierarchical permission disables)
-         return cpu->midr;
+ - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
--    case 0xd04: /* Interrupt Control State.  */
++- FEAT_IESB (Implicit error synchronization event)
-+    case 0xd04: /* Interrupt Control State (ICSR) */
+ - FEAT_JSCVT (JavaScript conversion instructions)
-         /* VECTACTIVE */
+ - FEAT_LOR (Limited ordering regions)
-         val = cpu->env.v7m.exception;
+ - FEAT_LPA (Large Physical Address space)
-         /* VECTPENDING */
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
+index XXXXXXX..XXXXXXX 100644
-         if (nvic_rettobase(s)) {
+--- a/target/arm/cpu64.c
-             val |= (1 << 11);
++++ b/target/arm/cpu64.c
-         }
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
--        /* PENDSTSET */
+     t = cpu->isar.id_aa64mmfr2;
--        if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
+     t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
--            val |= (1 << 26);
+     t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
--        }
++    t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1);     /* FEAT_IESB */
--        /* PENDSVSET */
+     t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
--        if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
+     t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
--            val |= (1 << 28);
+     t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
 +        if (attrs.secure) {
 +            /* PENDSTSET */
 +            if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {
 +                val |= (1 << 26);
 +            }
 +            /* PENDSVSET */
 +            if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {
 +                val |= (1 << 28);
 +            }
 +        } else {
 +            /* PENDSTSET */
 +            if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
 +                val |= (1 << 26);
 +            }
 +            /* PENDSVSET */
 +            if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
 +                val |= (1 << 28);
 +            }
          }
          /* NMIPENDSET */
 -        if (s->vectors[ARMV7M_EXCP_NMI].pending) {
 +        if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
 +            s->vectors[ARMV7M_EXCP_NMI].pending) {
              val |= (1 << 31);
          }
 -        /* ISRPREEMPT not implemented */
 +        /* ISRPREEMPT: RES0 when halting debug not implemented */
 +        /* STTNS: RES0 for the Main Extension */
          return val;
      case 0xd08: /* Vector Table Offset.  */
          return cpu->env.v7m.vecbase[attrs.secure];
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
          nvic_irq_update(s);
          break;
      }
 -    case 0xd04: /* Interrupt Control State.  */
 -        if (value & (1 << 31)) {
 -            armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
 +    case 0xd04: /* Interrupt Control State (ICSR) */
 +        if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
 +            if (value & (1 << 31)) {
 +                armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
 +            } else if (value & (1 << 30) &&
 +                       arm_feature(&cpu->env, ARM_FEATURE_V8)) {
 +                /* PENDNMICLR didn't exist in v7M */
 +                armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false);
 +            }
          }
          if (value & (1 << 28)) {
              armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 12/31] nvic: In escalation to HardFault, support HF not being priority -1
+[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
-When escalating to HardFault, we must go into Lockup if we
+From: Richard Henderson <richard.henderson@linaro.org>
 can't take the synchronous HardFault because the current
 execution priority is already at or below the priority of
 HardFault. In v7M HF is always priority -1 so a simple < 0
 comparison sufficed; in v8M the priority of HardFault can
 vary depending on whether it is a Secure or NonSecure
 HardFault, so we must check against the priority of the
 HardFault exception vector we're about to use.
+This extension concerns branch speculation, which TCG does
+not implement.  Thus we can trivially enable this feature.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-13-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 23 ++++++++++++-----------
+ docs/system/arm/emulation.rst | 1 +
-file changed, 12 insertions(+), 11 deletions(-)
+ target/arm/cpu64.c            | 1 +
  target/arm/cpu_tcg.c          | 1 +
 files changed, 3 insertions(+)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/docs/system/arm/emulation.rst
-+++ b/hw/intc/armv7m_nvic.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-         }
+ - FEAT_BBM at level 2 (Translation table break-before-make levels)
+ - FEAT_BF16 (AArch64 BFloat16 instructions)
-         if (escalate) {
+ - FEAT_BTI (Branch Target Identification)
--            if (running < 0) {
++- FEAT_CSV2 (Cache speculation variant 2)
--                /* We want to escalate to HardFault but we can't take a
+ - FEAT_DIT (Data Independent Timing instructions)
--                 * synchronous HardFault at this point either. This is a
+ - FEAT_DPB (DC CVAP instruction)
--                 * Lockup condition due to a guest bug. We don't model
+ - FEAT_Debugv8p2 (Debug changes for v8.2)
--                 * Lockup, so report via cpu_abort() instead.
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
--                 */
+index XXXXXXX..XXXXXXX 100644
--                cpu_abort(&s->cpu->parent_obj,
+--- a/target/arm/cpu64.c
--                          "Lockup: can't escalate %d to HardFault "
++++ b/target/arm/cpu64.c
--                          "(current priority %d)\n", irq, running);
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
--            }
+     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
--            /* We can do the escalation, so we take HardFault instead.
+     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-+            /* We need to escalate this exception to a synchronous HardFault.
++    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
-              * If BFHFNMINS is set then we escalate to the banked HF for
+     cpu->isar.id_aa64pfr0 = t;
-              * the target security state of the original exception; otherwise
-              * we take a Secure HardFault.
+     t = cpu->isar.id_aa64pfr1;
-@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-             } else {
+index XXXXXXX..XXXXXXX 100644
-                 vec = &s->vectors[irq];
+--- a/target/arm/cpu_tcg.c
-             }
++++ b/target/arm/cpu_tcg.c
-+            if (running <= vec->prio) {
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-+                /* We want to escalate to HardFault but we can't take the
+     cpu->isar.id_mmfr4 = t;
-+                 * synchronous HardFault at this point either. This is a
-+                 * Lockup condition due to a guest bug. We don't model
+     t = cpu->isar.id_pfr0;
-+                 * Lockup, so report via cpu_abort() instead.
++    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CVS2 */
-+                 */
+     t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
-+                cpu_abort(&s->cpu->parent_obj,
+     t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
-+                          "Lockup: can't escalate %d to HardFault "
+     cpu->isar.id_pfr0 = t;
 +                          "(current priority %d)\n", irq, running);
 +            }
 +
              /* HF may be banked but there is only one shared HFSR */
              s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
          }
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
+[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
-Now that we have a banked FAULTMASK register and banked exceptions,
+From: Richard Henderson <richard.henderson@linaro.org>
 we can implement the correct check in cpu_mmu_index() for whether
 the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
 handlers which have requested a negative execution priority to run
 with the MPU disabled. In v8M the test has to check this for the
 current security state and so takes account of banking.
+There is no branch prediction in TCG, therefore there is no
+need to actually include the context number into the predictor.
+Therefore all we need to do is add the state for SCXTNUM_ELx.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/cpu.h      | 21 ++++++++++++++++-----
+ docs/system/arm/emulation.rst |  3 ++
- hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++
+ target/arm/cpu.h              | 16 +++++++++
-files changed, 45 insertions(+), 5 deletions(-)
+ target/arm/cpu.c              |  5 +++
  target/arm/cpu64.c            |  3 +-
  target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
 files changed, 86 insertions(+), 2 deletions(-)
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/emulation.rst
++++ b/docs/system/arm/emulation.rst
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_BF16 (AArch64 BFloat16 instructions)
+ - FEAT_BTI (Branch Target Identification)
+ - FEAT_CSV2 (Cache speculation variant 2)
++- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
++- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
++- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
+ - FEAT_DIT (Data Independent Timing instructions)
+ - FEAT_DPB (DC CVAP instruction)
+ - FEAT_Debugv8p2 (Debug changes for v8.2)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq);
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
-  * (v8M ARM ARM I_PKLD.)
+         ARMPACKey apdb;
-  */
+         ARMPACKey apga;
- int armv7m_nvic_raw_execution_priority(void *opaque);
+     } keys;
-+/**
++
-+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
++    uint64_t scxtnum_el[4];
-+ * priority is negative for the specified security state.
+ #endif
-+ * @opaque: the NVIC
-+ * @secure: the security state to test
+ #if defined(CONFIG_USER_ONLY)
-+ * This corresponds to the pseudocode IsReqExecPriNeg().
+@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
-+ */
+ #define SCTLR_WXN     (1U << 19)
-+#ifndef CONFIG_USER_ONLY
+ #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
-+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
+ #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
-+#else
++#define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
-+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+ #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
  #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
  #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
      return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
  }
 +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
 +{
++    int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
++    if (key >= 2) {
++        return true;      /* FEAT_CSV2_2 */
++    }
++    if (key == 1) {
++        key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
++        return key >= 2;  /* FEAT_CSV2_1p2 */
++    }
 +    return false;
 +}
-+#endif
++
+ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
- /* Interface for defining coprocessor registers.
+ {
-  * Registers are defined in tables of arm_cp_reginfo structs
+     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
-@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-     if (arm_feature(env, ARM_FEATURE_M)) {
+index XXXXXXX..XXXXXXX 100644
-         ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
--        /* Execution priority is negative if FAULTMASK is set or
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
--         * we're in a HardFault or NMI handler.
+              */
--         */
+             env->cp15.gcr_el1 = 0x1ffff;
 -        if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
 -            || env->v7m.faultmask[env->v7m.secure]) {
 +        if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
              mmu_idx = ARMMMUIdx_MNegPri;
          }
++        /*
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
++         * Disable access to SCXTNUM_EL0 from CSV2_1p2.
-index XXXXXXX..XXXXXXX 100644
++         * This is not yet exposed from the Linux kernel in any way.
---- a/hw/intc/armv7m_nvic.c
++         */
-+++ b/hw/intc/armv7m_nvic.c
++        env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
-@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
+ #else
-     return MIN(running, s->exception_prio);
+         /* Reset into the highest available EL */
- }
+         if (arm_feature(env, ARM_FEATURE_EL3)) {
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
      t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
      t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
 -    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
 +    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
      cpu->isar.id_aa64pfr0 = t;
      t = cpu->isar.id_aa64pfr1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
       * we do for EL2 with the virtualization=on property.
       */
      t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
 +    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
      cpu->isar.id_aa64pfr1 = t;
      t = cpu->isar.id_aa64mmfr0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          if (cpu_isar_feature(aa64_mte, cpu)) {
              valid_mask |= SCR_ATA;
          }
 +        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
 +            valid_mask |= SCR_ENSCXT;
 +        }
      } else {
          valid_mask &= ~(SCR_RW | SCR_ST);
          if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
          if (cpu_isar_feature(aa64_mte, cpu)) {
              valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
          }
 +        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
 +            valid_mask |= HCR_ENSCXT;
 +        }
      }
      /* Clear RES0 bits.  */
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
          { K(3, 0,  5, 6, 0), K(3, 4,  5, 6, 0), K(3, 5, 5, 6, 0),
            "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
 +        { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
 +          "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
 +          isar_feature_aa64_scxtnum },
 +
          /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
          /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
      };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
      },
  };
 -#endif
 +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                     bool isread)
 +{
-+    /* Return true if the requested execution priority is negative
++    uint64_t hcr = arm_hcr_el2_eff(env);
-+     * for the specified security state, ie that security state
++    int el = arm_current_el(env);
-+     * has an active NMI or HardFault or has set its FAULTMASK.
++
-+     * Note that this is not the same as whether the execution
++    if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
-+     * priority is actually negative (for instance AIRCR.PRIS may
++        if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
-+     * mean we don't allow FAULTMASK_NS to actually make the execution
++            if (hcr & HCR_TGE) {
-+     * priority negative). Compare pseudocode IsReqExcPriNeg().
++                return CP_ACCESS_TRAP_EL2;
-+     */
++            }
-+    NVICState *s = opaque;
++            return CP_ACCESS_TRAP;
-+
++        }
-+    if (s->cpu->env.v7m.faultmask[secure]) {
++    } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
-+        return true;
++        return CP_ACCESS_TRAP_EL2;
 +    }
-+
++    if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
-+    if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
++        return CP_ACCESS_TRAP_EL2;
-+        s->vectors[ARMV7M_EXCP_HARD].active) {
++    }
-+        return true;
++    if (el < 3
-+    }
++        && arm_feature(env, ARM_FEATURE_EL3)
-+
++        && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
-+    if (s->vectors[ARMV7M_EXCP_NMI].active &&
++        return CP_ACCESS_TRAP_EL3;
-+        exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
++    }
-+        return true;
++    return CP_ACCESS_OK;
 +    }
 +
 +    return false;
 +}
 +
- bool armv7m_nvic_can_take_pending_exception(void *opaque)
++static const ARMCPRegInfo scxtnum_reginfo[] = {
- {
++    { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
-     NVICState *s = opaque;
++      .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL0_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
 +    { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL1_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
 +    { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL2_RW, .accessfn = access_scxtnum,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
 +    { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
 +      .access = PL3_RW,
 +      .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
 +};
 +#endif /* TARGET_AARCH64 */
  static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
                                       bool isread)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
          define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
      }
 +
 +    if (cpu_isar_feature(aa64_scxtnum, cpu)) {
 +        define_arm_cp_regs(cpu, scxtnum_reginfo);
 +    }
  #endif
      if (cpu_isar_feature(any_predinv, cpu)) {
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions
+[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
-In v7M, the fixed-priority exceptions are:
+From: Richard Henderson <richard.henderson@linaro.org>
  Reset: -3
  NMI: -2
  HardFault: -1
-In v8M, this changes because Secure HardFault may need
+This extension concerns cache speculation, which TCG does
-to be prioritised above NMI:
+not implement.  Thus we can trivially enable this feature.
  Reset: -4
  Secure HardFault if AIRCR.BFHFNMINS == 1: -3
  NMI: -2
  Secure HardFault if AIRCR.BFHFNMINS == 0: -1
  NonSecure HardFault: -1
-Make these changes, including support for changing the
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-priority of Secure HardFault as AIRCR.BFHFNMINS changes.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  docs/system/arm/emulation.rst | 1 +
  target/arm/cpu64.c            | 1 +
  target/arm/cpu_tcg.c          | 1 +
 files changed, 3 insertions(+)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 1505240046-11454-14-git-send-email-peter.maydell@linaro.org
 ---
  hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++---
 file changed, 19 insertions(+), 3 deletions(-)
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/docs/system/arm/emulation.rst
-+++ b/hw/intc/armv7m_nvic.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-                     (R_V7M_AIRCR_SYSRESETREQS_MASK |
+ - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
-                      R_V7M_AIRCR_BFHFNMINS_MASK |
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
-                      R_V7M_AIRCR_PRIS_MASK);
+ - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
-+                /* BFHFNMINS changes the priority of Secure HardFault */
++- FEAT_CSV3 (Cache speculation variant 3)
-+                if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
+ - FEAT_DIT (Data Independent Timing instructions)
-+                    s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
+ - FEAT_DPB (DC CVAP instruction)
-+                } else {
+ - FEAT_Debugv8p2 (Debug changes for v8.2)
-+                    s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-+                }
+index XXXXXXX..XXXXXXX 100644
-             }
+--- a/target/arm/cpu64.c
-             nvic_irq_update(s);
++++ b/target/arm/cpu64.c
-         }
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-@@ -XXX,XX +XXX,XX @@ static int nvic_post_load(void *opaque, int version_id)
+     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
- {
+     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-     NVICState *s = opaque;
+     t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
-     unsigned i;
++    t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1);      /* FEAT_CSV3 */
-+    int resetprio;
+     cpu->isar.id_aa64pfr0 = t;
-     /* Check for out of range priority settings */
+     t = cpu->isar.id_aa64pfr1;
--    if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
-+    resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
+index XXXXXXX..XXXXXXX 100644
-+
+--- a/target/arm/cpu_tcg.c
-+    if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
++++ b/target/arm/cpu_tcg.c
-         s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-         s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
+     cpu->isar.id_pfr0 = t;
-         return 1;
-@@ -XXX,XX +XXX,XX @@ static int nvic_security_post_load(void *opaque, int version_id)
+     t = cpu->isar.id_pfr2;
-     int i;
++    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
+     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
-     /* Check for out of range priority settings */
+     cpu->isar.id_pfr2 = t;
 -    if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
 +    if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
 +        && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
 +        /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
 +         * if the CPU state has been migrated yet; a mismatch won't
 +         * cause the emulation to blow up, though.
 +         */
          return 1;
      }
      for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
@@ -XXX,XX +XXX,XX @@ static Property props_nvic[] = {
  static void armv7m_nvic_reset(DeviceState *dev)
  {
 +    int resetprio;
      NVICState *s = NVIC(dev);
      s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
      s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
      s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
 -    s->vectors[ARMV7M_EXCP_RESET].prio = -3;
 +    resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
 +    s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
      s->vectors[ARMV7M_EXCP_NMI].prio = -2;
      s->vectors[ARMV7M_EXCP_HARD].prio = -1;
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 20/31] target/arm: Remove out of date ARM ARM section references in A64 decoder
+[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
-In the A64 decoder, we have a lot of references to section numbers
+From: Richard Henderson <richard.henderson@linaro.org>
 from version A.a of the v8A ARM ARM (DDI0487). This version of the
 document is now long obsolete (we are currently on revision B.a),
 and various intervening versions renumbered all the sections.
-The most recent B.a version of the document doesn't assign
+This extension concerns not merging memory access, which TCG does
-section numbers at all to the individual instruction classes
+not implement.  Thus we can trivially enable this feature.
-in the way that the various A.x versions did. The simplest thing
+Add a comment to handle_hint for the DGH instruction, but no code.
 to do is just to delete all the out of date C.x.x references.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20170915150849.23557-1-peter.maydell@linaro.org
 ---
- target/arm/translate-a64.c | 227 +++++++++++++++++++++++----------------------
+ docs/system/arm/emulation.rst | 1 +
-file changed, 114 insertions(+), 113 deletions(-)
+ target/arm/cpu64.c            | 1 +
  target/arm/translate-a64.c    | 1 +
 files changed, 3 insertions(+)
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/emulation.rst
++++ b/docs/system/arm/emulation.rst
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+ - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
+ - FEAT_CSV3 (Cache speculation variant 3)
++- FEAT_DGH (Data gathering hint)
+ - FEAT_DIT (Data Independent Timing instructions)
+ - FEAT_DPB (DC CVAP instruction)
+ - FEAT_Debugv8p2 (Debug changes for v8.2)
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu64.c
++++ b/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+     t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
+     t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
+     t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
++    t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1);      /* FEAT_DGH */
+     t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
+     cpu->isar.id_aa64isar1 = t;
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
+@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
- }
+         break;
+     case 0b00100: /* SEV */
- /*
+     case 0b00101: /* SEVL */
-- * the instruction disassembly implemented here matches
++    case 0b00110: /* DGH */
-- * the instruction encoding classifications in chapter 3 (C3)
+         /* we treat all as NOP at least for now */
-- * of the ARM Architecture Reference Manual (DDI0487A_a)
+         break;
-+ * The instruction disassembly implemented here matches
+     case 0b00111: /* XPACLRI */
 + * the instruction encoding classifications in chapter C4
 + * of the ARM Architecture Reference Manual (DDI0487B_a);
 + * classification names and decode diagrams here should generally
 + * match up with those in the manual.
   */
 -/* C3.2.7 Unconditional branch (immediate)
 +/* Unconditional branch (immediate)
   *   31  30       26 25                                  0
   * +----+-----------+-------------------------------------+
   * | op | 0 0 1 0 1 |                 imm26               |
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
      uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
      if (insn & (1U << 31)) {
 -        /* C5.6.26 BL Branch with link */
 +        /* BL Branch with link */
          tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
      }
 -    /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
 +    /* B Branch / BL Branch with link */
      gen_goto_tb(s, 0, addr);
  }
 -/* C3.2.1 Compare & branch (immediate)
 +/* Compare and branch (immediate)
   *   31  30         25  24  23                  5 4      0
   * +----+-------------+----+---------------------+--------+
   * | sf | 0 1 1 0 1 0 | op |         imm19       |   Rt   |
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
      gen_goto_tb(s, 1, addr);
  }
 -/* C3.2.5 Test & branch (immediate)
 +/* Test and branch (immediate)
   *   31  30         25  24  23   19 18          5 4    0
   * +----+-------------+----+-------+-------------+------+
   * | b5 | 0 1 1 0 1 1 | op |  b40  |    imm14    |  Rt  |
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
      gen_goto_tb(s, 1, addr);
  }
 -/* C3.2.2 / C5.6.19 Conditional branch (immediate)
 +/* Conditional branch (immediate)
   *  31           25  24  23                  5   4  3    0
   * +---------------+----+---------------------+----+------+
   * | 0 1 0 1 0 1 0 | o1 |         imm19       | o0 | cond |
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
      }
  }
 -/* C5.6.68 HINT */
 +/* HINT instruction group, including various allocated HINTs */
  static void handle_hint(DisasContext *s, uint32_t insn,
                          unsigned int op1, unsigned int op2, unsigned int crm)
  {
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
      }
  }
 -/* C5.6.130 MSR (immediate) - move immediate to processor state field */
 +/* MSR (immediate) - move immediate to processor state field */
  static void handle_msr_i(DisasContext *s, uint32_t insn,
                           unsigned int op1, unsigned int op2, unsigned int crm)
  {
@@ -XXX,XX +XXX,XX @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
      tcg_temp_free_i32(nzcv);
  }
 -/* C5.6.129 MRS - move from system register
 - * C5.6.131 MSR (register) - move to system register
 - * C5.6.204 SYS
 - * C5.6.205 SYSL
 +/* MRS - move from system register
 + * MSR (register) - move to system register
 + * SYS
 + * SYSL
   * These are all essentially the same insn in 'read' and 'write'
   * versions, with varying op0 fields.
   */
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
      }
  }
 -/* C3.2.4 System
 +/* System
   *  31                 22 21  20 19 18 16 15   12 11    8 7   5 4    0
   * +---------------------+---+-----+-----+-------+-------+-----+------+
   * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 |  CRn  |  CRm  | op2 |  Rt  |
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
              return;
          }
          switch (crn) {
 -        case 2: /* C5.6.68 HINT */
 +        case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
              handle_hint(s, insn, op1, op2, crm);
              break;
          case 3: /* CLREX, DSB, DMB, ISB */
              handle_sync(s, insn, op1, op2, crm);
              break;
 -        case 4: /* C5.6.130 MSR (immediate) */
 +        case 4: /* MSR (immediate) */
              handle_msr_i(s, insn, op1, op2, crm);
              break;
          default:
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
      handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
  }
 -/* C3.2.3 Exception generation
 +/* Exception generation
   *
   *  31             24 23 21 20                     5 4   2 1  0
   * +-----------------+-----+------------------------+-----+----+
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.2.7 Unconditional branch (register)
 +/* Unconditional branch (register)
   *  31           25 24   21 20   16 15   10 9    5 4     0
   * +---------------+-------+-------+-------+------+-------+
   * | 1 1 0 1 0 1 1 |  opc  |  op2  |  op3  |  Rn  |  op4  |
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
      s->base.is_jmp = DISAS_JUMP;
  }
 -/* C3.2 Branches, exception generating and system instructions */
 +/* Branches, exception generating and system instructions */
  static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
  {
      switch (extract32(insn, 25, 7)) {
@@ -XXX,XX +XXX,XX @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
      return regsize == 64;
  }
 -/* C3.3.6 Load/store exclusive
 +/* Load/store exclusive
   *
   *  31 30 29         24  23  22   21  20  16  15  14   10 9    5 4    0
   * +-----+-------------+----+---+----+------+----+-------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
  }
  /*
 - * C3.3.5 Load register (literal)
 + * Load register (literal)
   *
   *  31 30 29   27  26 25 24 23                5 4     0
   * +-----+-------+---+-----+-------------------+-------+
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
  }
  /*
 - * C5.6.80 LDNP (Load Pair - non-temporal hint)
 - * C5.6.81 LDP (Load Pair - non vector)
 - * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
 - * C5.6.176 STNP (Store Pair - non-temporal hint)
 - * C5.6.177 STP (Store Pair - non vector)
 - * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
 - * C6.3.165 LDP (Load Pair of SIMD&FP)
 - * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
 - * C6.3.284 STP (Store Pair of SIMD&FP)
 + * LDNP (Load Pair - non-temporal hint)
 + * LDP (Load Pair - non vector)
 + * LDPSW (Load Pair Signed Word - non vector)
 + * STNP (Store Pair - non-temporal hint)
 + * STP (Store Pair - non vector)
 + * LDNP (Load Pair of SIMD&FP - non-temporal hint)
 + * LDP (Load Pair of SIMD&FP)
 + * STNP (Store Pair of SIMD&FP - non-temporal hint)
 + * STP (Store Pair of SIMD&FP)
   *
   *  31 30 29   27  26  25 24   23  22 21   15 14   10 9    5 4    0
   * +-----+-------+---+---+-------+---+-----------------------------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
  }
  /*
 - * C3.3.8 Load/store (immediate post-indexed)
 - * C3.3.9 Load/store (immediate pre-indexed)
 - * C3.3.12 Load/store (unscaled immediate)
 + * Load/store (immediate post-indexed)
 + * Load/store (immediate pre-indexed)
 + * Load/store (unscaled immediate)
   *
   * 31 30 29   27  26 25 24 23 22 21  20    12 11 10 9    5 4    0
   * +----+-------+---+-----+-----+---+--------+-----+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
  }
  /*
 - * C3.3.10 Load/store (register offset)
 + * Load/store (register offset)
   *
   * 31 30 29   27  26 25 24 23 22 21  20  16 15 13 12 11 10 9  5 4  0
   * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
  }
  /*
 - * C3.3.13 Load/store (unsigned immediate)
 + * Load/store (unsigned immediate)
   *
   * 31 30 29   27  26 25 24 23 22 21        10 9     5
   * +----+-------+---+-----+-----+------------+-------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.3.1 AdvSIMD load/store multiple structures
 +/* AdvSIMD load/store multiple structures
   *
   *  31  30  29           23 22  21         16 15    12 11  10 9    5 4    0
   * +---+---+---------------+---+-------------+--------+------+------+------+
   * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size |  Rn  |  Rt  |
   * +---+---+---------------+---+-------------+--------+------+------+------+
   *
 - * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
 + * AdvSIMD load/store multiple structures (post-indexed)
   *
   *  31  30  29           23 22  21  20     16 15    12 11  10 9    5 4    0
   * +---+---+---------------+---+---+---------+--------+------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_addr);
  }
 -/* C3.3.3 AdvSIMD load/store single structure
 +/* AdvSIMD load/store single structure
   *
   *  31  30  29           23 22 21 20       16 15 13 12  11  10 9    5 4    0
   * +---+---+---------------+-----+-----------+-----+---+------+------+------+
   * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size |  Rn  |  Rt  |
   * +---+---+---------------+-----+-----------+-----+---+------+------+------+
   *
 - * C3.3.4 AdvSIMD load/store single structure (post-indexed)
 + * AdvSIMD load/store single structure (post-indexed)
   *
   *  31  30  29           23 22 21 20       16 15 13 12  11  10 9    5 4    0
   * +---+---+---------------+-----+-----------+-----+---+------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_addr);
  }
 -/* C3.3 Loads and stores */
 +/* Loads and stores */
  static void disas_ldst(DisasContext *s, uint32_t insn)
  {
      switch (extract32(insn, 24, 6)) {
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.4.6 PC-rel. addressing
 +/* PC-rel. addressing
   *   31  30   29 28       24 23                5 4    0
   * +----+-------+-----------+-------------------+------+
   * | op | immlo | 1 0 0 0 0 |       immhi       |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
  }
  /*
 - * C3.4.1 Add/subtract (immediate)
 + * Add/subtract (immediate)
   *
   *  31 30 29 28       24 23 22 21         10 9   5 4   0
   * +--+--+--+-----------+-----+-------------+-----+-----+
@@ -XXX,XX +XXX,XX @@ static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
      return true;
  }
 -/* C3.4.4 Logical (immediate)
 +/* Logical (immediate)
   *   31  30 29 28         23 22  21  16 15  10 9    5 4    0
   * +----+-----+-------------+---+------+------+------+------+
   * | sf | opc | 1 0 0 1 0 0 | N | immr | imms |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_logic_imm(DisasContext *s, uint32_t insn)
  }
  /*
 - * C3.4.5 Move wide (immediate)
 + * Move wide (immediate)
   *
   *  31 30 29 28         23 22 21 20             5 4    0
   * +--+-----+-------------+-----+----------------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.4.2 Bitfield
 +/* Bitfield
   *   31  30 29 28         23 22  21  16 15  10 9    5 4    0
   * +----+-----+-------------+---+------+------+------+------+
   * | sf | opc | 1 0 0 1 1 0 | N | immr | imms |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.4.3 Extract
 +/* Extract
   *   31  30  29 28         23 22   21  20  16 15    10 9    5 4    0
   * +----+------+-------------+---+----+------+--------+------+------+
   * | sf | op21 | 1 0 0 1 1 1 | N | o0 |  Rm  |  imms  |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.4 Data processing - immediate */
 +/* Data processing - immediate */
  static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
  {
      switch (extract32(insn, 23, 6)) {
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
      }
  }
 -/* C3.5.10 Logical (shifted register)
 +/* Logical (shifted register)
   *   31  30 29 28       24 23   22 21  20  16 15    10 9    5 4    0
   * +----+-----+-----------+-------+---+------+--------+------+------+
   * | sf | opc | 0 1 0 1 0 | shift | N |  Rm  |  imm6  |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_logic_reg(DisasContext *s, uint32_t insn)
  }
  /*
 - * C3.5.1 Add/subtract (extended register)
 + * Add/subtract (extended register)
   *
   *  31|30|29|28       24|23 22|21|20   16|15  13|12  10|9  5|4  0|
   * +--+--+--+-----------+-----+--+-------+------+------+----+----+
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
  }
  /*
 - * C3.5.2 Add/subtract (shifted register)
 + * Add/subtract (shifted register)
   *
   *  31 30 29 28       24 23 22 21 20   16 15     10 9    5 4    0
   * +--+--+--+-----------+-----+--+-------+---------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_result);
  }
 -/* C3.5.9 Data-processing (3 source)
 -
 -   31 30  29 28       24 23 21  20  16  15  14  10 9    5 4    0
 -  +--+------+-----------+------+------+----+------+------+------+
 -  |sf| op54 | 1 1 0 1 1 | op31 |  Rm  | o0 |  Ra  |  Rn  |  Rd  |
 -  +--+------+-----------+------+------+----+------+------+------+
 -
 +/* Data-processing (3 source)
 + *
 + *    31 30  29 28       24 23 21  20  16  15  14  10 9    5 4    0
 + *  +--+------+-----------+------+------+----+------+------+------+
 + *  |sf| op54 | 1 1 0 1 1 | op31 |  Rm  | o0 |  Ra  |  Rn  |  Rd  |
 + *  +--+------+-----------+------+------+----+------+------+------+
   */
  static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
  {
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_tmp);
  }
 -/* C3.5.3 - Add/subtract (with carry)
 +/* Add/subtract (with carry)
   *  31 30 29 28 27 26 25 24 23 22 21  20  16  15   10  9    5 4   0
   * +--+--+--+------------------------+------+---------+------+-----+
   * |sf|op| S| 1  1  0  1  0  0  0  0 |  rm  | opcode2 |  Rn  |  Rd |
@@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
 +/* Conditional compare (immediate / register)
   *  31 30 29 28 27 26 25 24 23 22 21  20    16 15  12  11  10  9   5  4 3   0
   * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
   * |sf|op| S| 1  1  0  1  0  0  1  0 |imm5/rm | cond |i/r |o2|  Rn  |o3|nzcv |
@@ -XXX,XX +XXX,XX @@ static void disas_cc(DisasContext *s, uint32_t insn)
      tcg_temp_free_i32(tcg_t2);
  }
 -/* C3.5.6 Conditional select
 +/* Conditional select
   *   31   30  29  28             21 20  16 15  12 11 10 9    5 4    0
   * +----+----+---+-----------------+------+------+-----+------+------+
   * | sf | op | S | 1 1 0 1 0 1 0 0 |  Rm  | cond | op2 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_rbit(DisasContext *s, unsigned int sf,
      }
  }
 -/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
 +/* REV with sf==1, opcode==3 ("REV64") */
  static void handle_rev64(DisasContext *s, unsigned int sf,
                           unsigned int rn, unsigned int rd)
  {
@@ -XXX,XX +XXX,XX @@ static void handle_rev64(DisasContext *s, unsigned int sf,
      tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
  }
 -/* C5.6.149 REV with sf==0, opcode==2
 - * C5.6.151 REV32 (sf==1, opcode==2)
 +/* REV with sf==0, opcode==2
 + * REV32 (sf==1, opcode==2)
   */
  static void handle_rev32(DisasContext *s, unsigned int sf,
                           unsigned int rn, unsigned int rd)
@@ -XXX,XX +XXX,XX @@ static void handle_rev32(DisasContext *s, unsigned int sf,
      }
  }
 -/* C5.6.150 REV16 (opcode==1) */
 +/* REV16 (opcode==1) */
  static void handle_rev16(DisasContext *s, unsigned int sf,
                           unsigned int rn, unsigned int rd)
  {
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
      tcg_temp_free_i64(tcg_tmp);
  }
 -/* C3.5.7 Data-processing (1 source)
 +/* Data-processing (1 source)
   *   31  30  29  28             21 20     16 15    10 9    5 4    0
   * +----+---+---+-----------------+---------+--------+------+------+
   * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
      }
  }
 -/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
 +/* LSLV, LSRV, ASRV, RORV */
  static void handle_shift_reg(DisasContext *s,
                               enum a64_shift_type shift_type, unsigned int sf,
                               unsigned int rm, unsigned int rn, unsigned int rd)
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
      tcg_temp_free_i32(tcg_bytes);
  }
 -/* C3.5.8 Data-processing (2 source)
 +/* Data-processing (2 source)
   *   31   30  29 28             21 20  16 15    10 9    5 4    0
   * +----+---+---+-----------------+------+--------+------+------+
   * | sf | 0 | S | 1 1 0 1 0 1 1 0 |  Rm  | opcode |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.5 Data processing - register */
 +/* Data processing - register */
  static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
  {
      switch (extract32(insn, 24, 5)) {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
      tcg_temp_free_i64(tcg_flags);
  }
 -/* C3.6.22 Floating point compare
 +/* Floating point compare
   *   31  30  29 28       24 23  22  21 20  16 15 14 13  10    9    5 4     0
   * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
   * | M | 0 | S | 1 1 1 1 0 | type | 1 |  Rm  | op  | 1 0 0 0 |  Rn  |  op2  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
      handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
  }
 -/* C3.6.23 Floating point conditional compare
 +/* Floating point conditional compare
   *   31  30  29 28       24 23  22  21 20  16 15  12 11 10 9    5  4   3    0
   * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
   * | M | 0 | S | 1 1 1 1 0 | type | 1 |  Rm  | cond | 0 1 |  Rn  | op | nzcv |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.24 Floating point conditional select
 +/* Floating point conditional select
   *   31  30  29 28       24 23  22  21 20  16 15  12 11 10 9    5 4    0
   * +---+---+---+-----------+------+---+------+------+-----+------+------+
   * | M | 0 | S | 1 1 1 1 0 | type | 1 |  Rm  | cond | 1 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(t_true);
  }
 -/* C3.6.25 Floating-point data-processing (1 source) - single precision */
 +/* Floating-point data-processing (1 source) - single precision */
  static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
  {
      TCGv_ptr fpst;
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
      tcg_temp_free_i32(tcg_res);
  }
 -/* C3.6.25 Floating-point data-processing (1 source) - double precision */
 +/* Floating-point data-processing (1 source) - double precision */
  static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
  {
      TCGv_ptr fpst;
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
      }
  }
 -/* C3.6.25 Floating point data-processing (1 source)
 +/* Floating point data-processing (1 source)
   *   31  30  29 28       24 23  22  21 20    15 14       10 9    5 4    0
   * +---+---+---+-----------+------+---+--------+-----------+------+------+
   * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.26 Floating-point data-processing (2 source) - single precision */
 +/* Floating-point data-processing (2 source) - single precision */
  static void handle_fp_2src_single(DisasContext *s, int opcode,
                                    int rd, int rn, int rm)
  {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
      tcg_temp_free_i32(tcg_res);
  }
 -/* C3.6.26 Floating-point data-processing (2 source) - double precision */
 +/* Floating-point data-processing (2 source) - double precision */
  static void handle_fp_2src_double(DisasContext *s, int opcode,
                                    int rd, int rn, int rm)
  {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
      tcg_temp_free_i64(tcg_res);
  }
 -/* C3.6.26 Floating point data-processing (2 source)
 +/* Floating point data-processing (2 source)
   *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
   * +---+---+---+-----------+------+---+------+--------+-----+------+------+
   * | M | 0 | S | 1 1 1 1 0 | type | 1 |  Rm  | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.27 Floating-point data-processing (3 source) - single precision */
 +/* Floating-point data-processing (3 source) - single precision */
  static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
                                    int rd, int rn, int rm, int ra)
  {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
      tcg_temp_free_i32(tcg_res);
  }
 -/* C3.6.27 Floating-point data-processing (3 source) - double precision */
 +/* Floating-point data-processing (3 source) - double precision */
  static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
                                    int rd, int rn, int rm, int ra)
  {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
      tcg_temp_free_i64(tcg_res);
  }
 -/* C3.6.27 Floating point data-processing (3 source)
 +/* Floating point data-processing (3 source)
   *   31  30  29 28       24 23  22  21  20  16  15  14  10 9    5 4    0
   * +---+---+---+-----------+------+----+------+----+------+------+------+
   * | M | 0 | S | 1 1 1 1 1 | type | o1 |  Rm  | o0 |  Ra  |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.28 Floating point immediate
 +/* Floating point immediate
   *   31  30  29 28       24 23  22  21 20        13 12   10 9    5 4    0
   * +---+---+---+-----------+------+---+------------+-------+------+------+
   * | M | 0 | S | 1 1 1 1 0 | type | 1 |    imm8    | 1 0 0 | imm5 |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
      tcg_temp_free_i32(tcg_shift);
  }
 -/* C3.6.29 Floating point <-> fixed point conversions
 +/* Floating point <-> fixed point conversions
   *   31   30  29 28       24 23  22  21 20   19 18    16 15   10 9    5 4    0
   * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
   * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
      }
  }
 -/* C3.6.30 Floating point <-> integer conversions
 +/* Floating point <-> integer conversions
   *   31   30  29 28       24 23  22  21 20   19 18 16 15         10 9  5 4  0
   * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
   * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
@@ -XXX,XX +XXX,XX @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
      tcg_temp_free_i64(tcg_tmp);
  }
 -/* C3.6.1 EXT
 +/* EXT
   *   31  30 29         24 23 22  21 20  16 15  14  11 10  9    5 4    0
   * +---+---+-------------+-----+---+------+---+------+---+------+------+
   * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | imm4 | 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_resh);
  }
 -/* C3.6.2 TBL/TBX
 +/* TBL/TBX
   *   31  30 29         24 23 22  21 20  16 15  14 13  12  11 10 9    5 4    0
   * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
   * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | len | op | 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_resh);
  }
 -/* C3.6.3 ZIP/UZP/TRN
 +/* ZIP/UZP/TRN
   *   31  30 29         24 23  22  21 20   16 15 14 12 11 10 9    5 4    0
   * +---+---+-------------+------+---+------+---+------------------+------+
   * | 0 | Q | 0 0 1 1 1 0 | size | 0 |  Rm  | 0 | opc | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
      }
  }
 -/* C3.6.4 AdvSIMD across lanes
 +/* AdvSIMD across lanes
   *   31  30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
   * +---+---+---+-----------+------+-----------+--------+-----+------+------+
   * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_res);
  }
 -/* C6.3.31 DUP (Element, Vector)
 +/* DUP (Element, Vector)
   *
   *  31  30   29              21 20    16 15        10  9    5 4    0
   * +---+---+-------------------+--------+-------------+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
      tcg_temp_free_i64(tmp);
  }
 -/* C6.3.31 DUP (element, scalar)
 +/* DUP (element, scalar)
   *  31                   21 20    16 15        10  9    5 4    0
   * +-----------------------+--------+-------------+------+------+
   * | 0 1 0 1 1 1 1 0 0 0 0 |  imm5  | 0 0 0 0 0 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupes(DisasContext *s, int rd, int rn,
      tcg_temp_free_i64(tmp);
  }
 -/* C6.3.32 DUP (General)
 +/* DUP (General)
   *
   *  31  30   29              21 20    16 15        10  9    5 4    0
   * +---+---+-------------------+--------+-------------+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
      }
  }
 -/* C6.3.150 INS (Element)
 +/* INS (Element)
   *
   *  31                   21 20    16 15  14    11  10 9    5 4    0
   * +-----------------------+--------+------------+---+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
  }
 -/* C6.3.151 INS (General)
 +/* INS (General)
   *
   *  31                   21 20    16 15        10  9    5 4    0
   * +-----------------------+--------+-------------+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
  }
  /*
 - * C6.3.321 UMOV (General)
 - * C6.3.237 SMOV (General)
 + * UMOV (General)
 + * SMOV (General)
   *
   *  31  30   29              21 20    16 15    12   10 9    5 4    0
   * +---+---+-------------------+--------+-------------+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
      }
  }
 -/* C3.6.5 AdvSIMD copy
 +/* AdvSIMD copy
   *   31  30  29  28             21 20  16 15  14  11 10  9    5 4    0
   * +---+---+----+-----------------+------+---+------+---+------+------+
   * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.6 AdvSIMD modified immediate
 +/* AdvSIMD modified immediate
   *  31  30   29  28                 19 18 16 15   12  11  10  9     5 4    0
   * +---+---+----+---------------------+-----+-------+----+---+-------+------+
   * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
      tcg_temp_free_i64(tcg_imm);
  }
 -/* C3.6.7 AdvSIMD scalar copy
 +/* AdvSIMD scalar copy
   *  31 30  29  28             21 20  16 15  14  11 10  9    5 4    0
   * +-----+----+-----------------+------+---+------+---+------+------+
   * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
      handle_simd_dupes(s, rd, rn, imm5);
  }
 -/* C3.6.8 AdvSIMD scalar pairwise
 +/* AdvSIMD scalar pairwise
   *  31 30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
   * +-----+---+-----------+------+-----------+--------+-----+------+------+
   * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
      tcg_temp_free_i32(tcg_rmode);
  }
 -/* C3.6.9 AdvSIMD scalar shift by immediate
 +/* AdvSIMD scalar shift by immediate
   *  31 30  29 28         23 22  19 18  16 15    11  10 9    5 4    0
   * +-----+---+-------------+------+------+--------+---+------+------+
   * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.10 AdvSIMD scalar three different
 +/* AdvSIMD scalar three different
   *  31 30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
   * +-----+---+-----------+------+---+------+--------+-----+------+------+
   * | 0 1 | U | 1 1 1 1 0 | size | 1 |  Rm  | opcode | 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
      }
  }
 -/* C3.6.11 AdvSIMD scalar three same
 +/* AdvSIMD scalar three same
   *  31 30  29 28       24 23  22  21 20  16 15    11  10 9    5 4    0
   * +-----+---+-----------+------+---+------+--------+---+------+------+
   * | 0 1 | U | 1 1 1 1 0 | size | 1 |  Rm  | opcode | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
      }
  }
 -/* C3.6.12 AdvSIMD scalar two reg misc
 +/* AdvSIMD scalar two reg misc
   *  31 30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
   * +-----+---+-----------+------+-----------+--------+-----+------+------+
   * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
  }
 -/* C3.6.14 AdvSIMD shift by immediate
 +/* AdvSIMD shift by immediate
   *  31  30   29 28         23 22  19 18  16 15    11  10 9    5 4    0
   * +---+---+---+-------------+------+------+--------+---+------+------+
   * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
      tcg_temp_free_i64(tcg_res);
  }
 -/* C3.6.15 AdvSIMD three different
 +/* AdvSIMD three different
   *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
   * +---+---+---+-----------+------+---+------+--------+-----+------+------+
   * | 0 | Q | U | 0 1 1 1 0 | size | 1 |  Rm  | opcode | 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.16 AdvSIMD three same
 +/* AdvSIMD three same
   *  31  30  29  28       24 23  22  21 20  16 15    11  10 9    5 4    0
   * +---+---+---+-----------+------+---+------+--------+---+------+------+
   * | 0 | Q | U | 0 1 1 1 0 | size | 1 |  Rm  | opcode | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
      }
  }
 -/* C3.6.17 AdvSIMD two reg misc
 +/* AdvSIMD two reg misc
   *   31  30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
   * +---+---+---+-----------+------+-----------+--------+-----+------+------+
   * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.13 AdvSIMD scalar x indexed element
 +/* AdvSIMD scalar x indexed element
   *  31 30  29 28       24 23  22 21  20  19  16 15 12  11  10 9    5 4    0
   * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
   * | 0 1 | U | 1 1 1 1 1 | size | L | M |  Rm  | opc | H | 0 |  Rn  |  Rd  |
   * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
 - * C3.6.18 AdvSIMD vector x indexed element
 + * AdvSIMD vector x indexed element
   *   31  30  29 28       24 23  22 21  20  19  16 15 12  11  10 9    5 4    0
   * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
   * | 0 | Q | U | 0 1 1 1 1 | size | L | M |  Rm  | opc | H | 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
      }
  }
 -/* C3.6.19 Crypto AES
 +/* Crypto AES
   *  31             24 23  22 21       17 16    12 11 10 9    5 4    0
   * +-----------------+------+-----------+--------+-----+------+------+
   * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
      tcg_temp_free_i32(tcg_decrypt);
  }
 -/* C3.6.20 Crypto three-reg SHA
 +/* Crypto three-reg SHA
   *  31             24 23  22  21 20  16  15 14    12 11 10 9    5 4    0
   * +-----------------+------+---+------+---+--------+-----+------+------+
   * | 0 1 0 1 1 1 1 0 | size | 0 |  Rm  | 0 | opcode | 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
      tcg_temp_free_i32(tcg_rm_regno);
  }
 -/* C3.6.21 Crypto two-reg SHA
 +/* Crypto two-reg SHA
   *  31             24 23  22 21       17 16    12 11 10 9    5 4    0
   * +-----------------+------+-----------+--------+-----+------+------+
   * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 |  Rn  |  Rd  |
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 24/31] hw/timer/omap_gptimer: Don't use old_mmio
+[PULL 24/32] target/arm: Define cortex-a76
-Don't use the old_mmio struct in memory region ops.
+From: Richard Henderson <richard.henderson@linaro.org>
+Enable the a76 for virt and sbsa board use.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
 ---
- hw/timer/omap_gptimer.c | 49 +++++++++++++++++++++++++++++++++++++------------
+ docs/system/arm/virt.rst |  1 +
-file changed, 37 insertions(+), 12 deletions(-)
+ hw/arm/sbsa-ref.c        |  1 +
  hw/arm/virt.c            |  1 +
  target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 files changed, 69 insertions(+)
-diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
+diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/omap_gptimer.c
+--- a/docs/system/arm/virt.rst
-+++ b/hw/timer/omap_gptimer.c
++++ b/docs/system/arm/virt.rst
-@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
+@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
-         s->writeh = (uint16_t) value;
+ - ``cortex-a53`` (64-bit)
  - ``cortex-a57`` (64-bit)
  - ``cortex-a72`` (64-bit)
 +- ``cortex-a76`` (64-bit)
  - ``a64fx`` (64-bit)
  - ``host`` (with KVM only)
  - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/sbsa-ref.c
 +++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
  static const char * const valid_cpus[] = {
      ARM_CPU_TYPE_NAME("cortex-a57"),
      ARM_CPU_TYPE_NAME("cortex-a72"),
 +    ARM_CPU_TYPE_NAME("cortex-a76"),
      ARM_CPU_TYPE_NAME("max"),
  };
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
      ARM_CPU_TYPE_NAME("cortex-a53"),
      ARM_CPU_TYPE_NAME("cortex-a57"),
      ARM_CPU_TYPE_NAME("cortex-a72"),
 +    ARM_CPU_TYPE_NAME("cortex-a76"),
      ARM_CPU_TYPE_NAME("a64fx"),
      ARM_CPU_TYPE_NAME("host"),
      ARM_CPU_TYPE_NAME("max"),
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      define_cortex_a72_a57_a53_cp_reginfo(cpu);
  }
-+static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,
++static void aarch64_a76_initfn(Object *obj)
 +                                     unsigned size)
 +{
-+    switch (size) {
++    ARMCPU *cpu = ARM_CPU(obj);
-+    case 1:
++
-+        return omap_badwidth_read32(opaque, addr);
++    cpu->dtb_compatible = "arm,cortex-a76";
-+    case 2:
++    set_feature(&cpu->env, ARM_FEATURE_V8);
-+        return omap_gp_timer_readh(opaque, addr);
++    set_feature(&cpu->env, ARM_FEATURE_NEON);
-+    case 4:
++    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+        return omap_gp_timer_readw(opaque, addr);
++    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-+    default:
++    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-+        g_assert_not_reached();
++    set_feature(&cpu->env, ARM_FEATURE_EL2);
-+    }
++    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444C004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0b1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.18 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
 +
 +    /* From B2.93 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +}
 +
-+static void omap_gp_timer_writefn(void *opaque, hwaddr addr,
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
-+                                  uint64_t value, unsigned size)
+ {
-+{
+     /*
-+    switch (size) {
+@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
-+    case 1:
+     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
-+        omap_badwidth_write32(opaque, addr, value);
+     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
-+        break;
+     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
-+    case 2:
++    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
-+        omap_gp_timer_writeh(opaque, addr, value);
+     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
-+        break;
+     { .name = "max",                .initfn = aarch64_max_initfn },
-+    case 4:
+ #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
 +        omap_gp_timer_write(opaque, addr, value);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
  static const MemoryRegionOps omap_gp_timer_ops = {
 -    .old_mmio = {
 -        .read = {
 -            omap_badwidth_read32,
 -            omap_gp_timer_readh,
 -            omap_gp_timer_readw,
 -        },
 -        .write = {
 -            omap_badwidth_write32,
 -            omap_gp_timer_writeh,
 -            omap_gp_timer_write,
 -        },
 -    },
 +    .read = omap_gp_timer_readfn,
 +    .write = omap_gp_timer_writefn,
 +    .valid.min_access_size = 1,
 +    .valid.max_access_size = 4,
      .endianness = DEVICE_NATIVE_ENDIAN,
  };
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 10/31] nvic: Make SHPR registers banked
+[PULL 25/32] target/arm: Define neoverse-n1
-Make the set_prio() function take a bool indicating
+From: Richard Henderson <richard.henderson@linaro.org>
 whether to pend the secure or non-secure version of a banked
 interrupt, and use this to implement the correct banking
 semantics for the SHPR registers.
+Enable the n1 for virt and sbsa board use.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-----
+ docs/system/arm/virt.rst |  1 +
- hw/intc/trace-events  |  2 +-
+ hw/arm/sbsa-ref.c        |  1 +
-files changed, 88 insertions(+), 10 deletions(-)
+ hw/arm/virt.c            |  1 +
  target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 files changed, 69 insertions(+)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/docs/system/arm/virt.rst
-+++ b/hw/intc/armv7m_nvic.c
++++ b/docs/system/arm/virt.rst
-@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_raw_execution_priority(void *opaque)
+@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
-     return s->exception_prio;
+ - ``cortex-a76`` (64-bit)
  - ``a64fx`` (64-bit)
  - ``host`` (with KVM only)
 +- ``neoverse-n1`` (64-bit)
  - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
  Note that the default is ``cortex-a15``, so for an AArch64 guest you must
 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/sbsa-ref.c
 +++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
      ARM_CPU_TYPE_NAME("cortex-a57"),
      ARM_CPU_TYPE_NAME("cortex-a72"),
      ARM_CPU_TYPE_NAME("cortex-a76"),
 +    ARM_CPU_TYPE_NAME("neoverse-n1"),
      ARM_CPU_TYPE_NAME("max"),
  };
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
      ARM_CPU_TYPE_NAME("cortex-a72"),
      ARM_CPU_TYPE_NAME("cortex-a76"),
      ARM_CPU_TYPE_NAME("a64fx"),
 +    ARM_CPU_TYPE_NAME("neoverse-n1"),
      ARM_CPU_TYPE_NAME("host"),
      ARM_CPU_TYPE_NAME("max"),
  };
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
      cpu->isar.mvfr2 = 0x00000043;
  }
--/* caller must call nvic_irq_update() after this */
++static void aarch64_neoverse_n1_initfn(Object *obj)
--static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
++{
-+/* caller must call nvic_irq_update() after this.
++    ARMCPU *cpu = ARM_CPU(obj);
 + * secure indicates the bank to use for banked exceptions (we assert if
 + * we are passed secure=true for a non-banked exception).
 + */
 +static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
  {
      assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
      assert(irq < s->num_irq);
 -    s->vectors[irq].prio = prio;
 +    if (secure) {
 +        assert(exc_is_banked(irq));
 +        s->sec_vectors[irq].prio = prio;
 +    } else {
 +        s->vectors[irq].prio = prio;
 +    }
 +
-+    trace_nvic_set_prio(irq, secure, prio);
++    cpu->dtb_compatible = "arm,neoverse-n1";
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    set_feature(&cpu->env, ARM_FEATURE_NEON);
 +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 +    set_feature(&cpu->env, ARM_FEATURE_EL2);
 +    set_feature(&cpu->env, ARM_FEATURE_EL3);
 +    set_feature(&cpu->env, ARM_FEATURE_PMU);
 +
 +    /* Ordered by B2.4 AArch64 registers by functional group */
 +    cpu->clidr = 0x82000023;
 +    cpu->ctr = 0x8444c004;
 +    cpu->dcz_blocksize = 4;
 +    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x414fd0c1;          /* r4p1 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.23 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
 +    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
 +
 +    /* From B2.98 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.23 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +
 +    /* From B5.1 AdvSIMD AArch64 register summary */
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +}
 +
-+/* Return the current raw priority register value.
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
-+ * secure indicates the bank to use for banked exceptions (we assert if
+ {
-+ * we are passed secure=true for a non-banked exception).
+     /*
-+ */
+@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
-+static int get_prio(NVICState *s, unsigned irq, bool secure)
+     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
-+{
+     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
-+    assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
+     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
-+    assert(irq < s->num_irq);
++    { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
+     { .name = "max",                .initfn = aarch64_max_initfn },
--    trace_nvic_set_prio(irq, prio);
+ #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-+    if (secure) {
+     { .name = "host",               .initfn = aarch64_host_initfn },
 +        assert(exc_is_banked(irq));
 +        return s->sec_vectors[irq].prio;
 +    } else {
 +        return s->vectors[irq].prio;
 +    }
  }
  /* Recompute state and assert irq line accordingly.
@@ -XXX,XX +XXX,XX @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
      }
  }
 +static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
 +{
 +    /* Behaviour for the SHPR register field for this exception:
 +     * return M_REG_NS to use the nonsecure vector (including for
 +     * non-banked exceptions), M_REG_S for the secure version of
 +     * a banked exception, and -1 if this field should RAZ/WI.
 +     */
 +    switch (exc) {
 +    case ARMV7M_EXCP_MEM:
 +    case ARMV7M_EXCP_USAGE:
 +    case ARMV7M_EXCP_SVC:
 +    case ARMV7M_EXCP_PENDSV:
 +    case ARMV7M_EXCP_SYSTICK:
 +        /* Banked exceptions */
 +        return attrs.secure;
 +    case ARMV7M_EXCP_BUS:
 +        /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
 +        if (!attrs.secure &&
 +            !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
 +            return -1;
 +        }
 +        return M_REG_NS;
 +    case ARMV7M_EXCP_SECURE:
 +        /* Not banked, RAZ/WI from nonsecure */
 +        if (!attrs.secure) {
 +            return -1;
 +        }
 +        return M_REG_NS;
 +    case ARMV7M_EXCP_DEBUG:
 +        /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
 +        return M_REG_NS;
 +    case 8 ... 10:
 +    case 13:
 +        /* RES0 */
 +        return -1;
 +    default:
 +        /* Not reachable due to decode of SHPR register addresses */
 +        g_assert_not_reached();
 +    }
 +}
 +
  static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
                                      uint64_t *data, unsigned size,
                                      MemTxAttrs attrs)
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
              }
          }
          break;
 -    case 0xd18 ... 0xd23: /* System Handler Priority.  */
 +    case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
          val = 0;
          for (i = 0; i < size; i++) {
 -            val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
 +            unsigned hdlidx = (offset - 0xd14) + i;
 +            int sbank = shpr_bank(s, hdlidx, attrs);
 +
 +            if (sbank < 0) {
 +                continue;
 +            }
 +            val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
          }
          break;
      case 0xfe0 ... 0xfff: /* ID.  */
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
          for (i = 0; i < size && startvec + i < s->num_irq; i++) {
              if (attrs.secure || s->itns[startvec + i]) {
 -                set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
 +                set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
              }
          }
          nvic_irq_update(s);
          return MEMTX_OK;
 -    case 0xd18 ... 0xd23: /* System Handler Priority.  */
 +    case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
          for (i = 0; i < size; i++) {
              unsigned hdlidx = (offset - 0xd14) + i;
 -            set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
 +            int newprio = extract32(value, i * 8, 8);
 +            int sbank = shpr_bank(s, hdlidx, attrs);
 +
 +            if (sbank < 0) {
 +                continue;
 +            }
 +            set_prio(s, hdlidx, sbank, newprio);
          }
          nvic_irq_update(s);
          return MEMTX_OK;
 diff --git a/hw/intc/trace-events b/hw/intc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/trace-events
 +++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
  # hw/intc/armv7m_nvic.c
  nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
  nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
 -nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
 +nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
  nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
  nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
  nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 11/31] nvic: Compare group priority for escalation to HF
+[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
-In armv7m_nvic_set_pending() we have to compare the
+From: Leif Lindholm <quic_llindhol@quicinc.com>
 priority of an exception against the execution priority
 to decide whether it needs to be escalated to HardFault.
 In the specification this is a comparison against the
 exception's group priority; for v7M we implemented it
 as a comparison against the raw exception priority
 because the two comparisons will always give the
 same answer. For v8M the existence of AIRCR.PRIS and
 the possibility of different PRIGROUP values for secure
 and nonsecure exceptions means we need to explicitly
 calculate the vector's group priority for this check.
+The sbsa-ref machine is continuously evolving. Some of the changes we
+want to make in the near future, to align with real components (e.g.
+the GIC-700), will break compatibility for existing firmware.
+Introduce two new properties to the DT generated on machine generation:
+- machine-version-major
+  To be incremented when a platform change makes the machine
+  incompatible with existing firmware.
+- machine-version-minor
+  To be incremented when functionality is added to the machine
+  without causing incompatibility with existing firmware.
+  to be reset to 0 when machine-version-major is incremented.
+This versioning scheme is *neither*:
+- A QEMU versioned machine type; a given version of QEMU will emulate
+  a given version of the platform.
+- A reflection of level of SBSA (now SystemReady SR) support provided.
+The version will increment on guest-visible functional changes only,
+akin to a revision ID register found on a physical platform.
+These properties are both introduced with the value 0.
+(Hence, a machine where the DT is lacking these nodes is equivalent
+to version 0.0.)
+Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
+Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
+Cc: Peter Maydell <peter.maydell@linaro.org>
+Cc: Radoslaw Biernacki <rad@semihalf.com>
+Cc: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-12-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 2 +-
+ hw/arm/sbsa-ref.c | 14 ++++++++++++++
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 14 insertions(+)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/hw/arm/sbsa-ref.c
-+++ b/hw/intc/armv7m_nvic.c
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
-         int running = nvic_exec_prio(s);
+     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
-         bool escalate = false;
+     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
--        if (vec->prio >= running) {
++    /*
-+        if (exc_group_prio(s, vec->prio, secure) >= running) {
++     * This versioning scheme is for informing platform fw only. It is neither:
-             trace_nvic_escalate_prio(irq, vec->prio, running);
++     * - A QEMU versioned machine type; a given version of QEMU will emulate
-             escalate = true;
++     *   a given version of the platform.
-         } else if (!vec->enabled) {
++     * - A reflection of level of SBSA (now SystemReady SR) support provided.
 +     *
 +     * machine-version-major: updated when changes breaking fw compatibility
 +     *                        are introduced.
 +     * machine-version-minor: updated when features are added that don't break
 +     *                        fw compatibility.
 +     */
 +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
 +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
 +
      if (ms->numa_state->have_numa_distance) {
          int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
          uint32_t *matrix = g_malloc0(size);
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 30/31] msf2: Add Smartfusion2 SoC
+[PULL 27/32] qapi/machine.json: Add cluster-id
-From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+From: Gavin Shan <gshan@redhat.com>
-Smartfusion2 SoC has hardened Microcontroller subsystem
+This adds cluster-id in CPU instance properties, which will be used
-and flash based FPGA fabric. This patch adds support for
+by arm/virt machine. Besides, the cluster-id is also verified or
-Microcontroller subsystem in the SoC.
+dumped in various spots:
-Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+  * hw/core/machine.c::machine_set_cpu_numa_node() to associate
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+    CPU with its NUMA node.
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20170920201737.25723-5-f4bug@amsat.org
+  * hw/core/machine.c::machine_numa_finish_cpu_init() to record
-[PMD: drop cpu_model to directly use cpu type, check m3clk non null]
+    CPU slots with no NUMA mapping set.
   * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
     cluster-id.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
 Acked-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20220503140304.855514-2-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/Makefile.objs            |   1 +
+ qapi/machine.json          |  6 ++++--
- include/hw/arm/msf2-soc.h       |  67 +++++++++++
+ hw/core/machine-hmp-cmds.c |  4 ++++
- hw/arm/msf2-soc.c               | 238 ++++++++++++++++++++++++++++++++++++++++
+ hw/core/machine.c          | 16 ++++++++++++++++
- default-configs/arm-softmmu.mak |   1 +
+files changed, 24 insertions(+), 2 deletions(-)
 files changed, 307 insertions(+)
  create mode 100644 include/hw/arm/msf2-soc.h
  create mode 100644 hw/arm/msf2-soc.c
-diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
+diff --git a/qapi/machine.json b/qapi/machine.json
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/Makefile.objs
+--- a/qapi/machine.json
-+++ b/hw/arm/Makefile.objs
++++ b/qapi/machine.json
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
  obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
  obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
  obj-$(CONFIG_MPS2) += mps2.o
 +obj-$(CONFIG_MSF2) += msf2-soc.o
 diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/arm/msf2-soc.h
 @@ -XXX,XX +XXX,XX @@
-+/*
+ # @node-id: NUMA node ID the CPU belongs to
-+ * Microsemi Smartfusion2 SoC
+ # @socket-id: socket number within node/board the CPU belongs to
-+ *
+ # @die-id: die number within socket the CPU belongs to (since 4.1)
-+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+-# @core-id: core number within die the CPU belongs to
-+ *
++# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
-+ * Permission is hereby granted, free of charge, to any person obtaining a copy
++# @core-id: core number within cluster the CPU belongs to
-+ * of this software and associated documentation files (the "Software"), to deal
+ # @thread-id: thread number within core the CPU belongs to
-+ * in the Software without restriction, including without limitation the rights
+ #
-+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-# Note: currently there are 5 properties that could be present
-+ * copies of the Software, and to permit persons to whom the Software is
++# Note: currently there are 6 properties that could be present
-+ * furnished to do so, subject to the following conditions:
+ #       but management should be prepared to pass through other
-+ *
+ #       properties with device_add command to allow for future
-+ * The above copyright notice and this permission notice shall be included in
+ #       interface extension. This also requires the filed names to be kept in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_ARM_MSF2_SOC_H
 +#define HW_ARM_MSF2_SOC_H
 +
 +#include "hw/arm/armv7m.h"
 +#include "hw/timer/mss-timer.h"
 +#include "hw/misc/msf2-sysreg.h"
 +#include "hw/ssi/mss-spi.h"
 +
 +#define TYPE_MSF2_SOC     "msf2-soc"
 +#define MSF2_SOC(obj)     OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
 +
 +#define MSF2_NUM_SPIS         2
 +#define MSF2_NUM_UARTS        2
 +
 +/*
 + * System timer consists of two programmable 32-bit
 + * decrementing counters that generate individual interrupts to
 + * the Cortex-M3 processor
 + */
 +#define MSF2_NUM_TIMERS       2
 +
 +typedef struct MSF2State {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +    /*< public >*/
 +
 +    ARMv7MState armv7m;
 +
 +    char *cpu_type;
 +    char *part_name;
 +    uint64_t envm_size;
 +    uint64_t esram_size;
 +
 +    uint32_t m3clk;
 +    uint8_t apb0div;
 +    uint8_t apb1div;
 +
 +    MSF2SysregState sysreg;
 +    MSSTimerState timer;
 +    MSSSpiState spi[MSF2_NUM_SPIS];
 +} MSF2State;
 +
 +#endif
 diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/msf2-soc.c
 @@ -XXX,XX +XXX,XX @@
-+/*
+   'data': { '*node-id': 'int',
-+ * SmartFusion2 SoC emulation.
+             '*socket-id': 'int',
-+ *
+             '*die-id': 'int',
-+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
++            '*cluster-id': 'int',
-+ *
+             '*core-id': 'int',
-+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+             '*thread-id': 'int'
-+ * of this software and associated documentation files (the "Software"), to deal
+   }
-+ * in the Software without restriction, including without limitation the rights
+diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
-+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+index XXXXXXX..XXXXXXX 100644
-+ * copies of the Software, and to permit persons to whom the Software is
+--- a/hw/core/machine-hmp-cmds.c
-+ * furnished to do so, subject to the following conditions:
++++ b/hw/core/machine-hmp-cmds.c
-+ *
+@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
-+ * The above copyright notice and this permission notice shall be included in
+         if (c->has_die_id) {
-+ * all copies or substantial portions of the Software.
+             monitor_printf(mon, "    die-id: \"%" PRIu64 "\"\n", c->die_id);
-+ *
+         }
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++        if (c->has_cluster_id) {
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++            monitor_printf(mon, "    cluster-id: \"%" PRIu64 "\"\n",
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++                           c->cluster_id);
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "qemu-common.h"
 +#include "hw/arm/arm.h"
 +#include "exec/address-spaces.h"
 +#include "hw/char/serial.h"
 +#include "hw/boards.h"
 +#include "sysemu/block-backend.h"
 +#include "qemu/cutils.h"
 +#include "hw/arm/msf2-soc.h"
 +#include "hw/misc/unimp.h"
 +
 +#define MSF2_TIMER_BASE       0x40004000
 +#define MSF2_SYSREG_BASE      0x40038000
 +
 +#define ENVM_BASE_ADDRESS     0x60000000
 +
 +#define SRAM_BASE_ADDRESS     0x20000000
 +
 +#define MSF2_ENVM_MAX_SIZE    (512 * K_BYTE)
 +
 +/*
 + * eSRAM max size is 80k without SECDED(Single error correction and
 + * dual error detection) feature and 64k with SECDED.
 + * We do not support SECDED now.
 + */
 +#define MSF2_ESRAM_MAX_SIZE       (80 * K_BYTE)
 +
 +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
 +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
 +
 +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
 +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
 +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
 +
 +static void m2sxxx_soc_initfn(Object *obj)
 +{
 +    MSF2State *s = MSF2_SOC(obj);
 +    int i;
 +
 +    object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
 +    qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
 +
 +    object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
 +    qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
 +
 +    object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
 +    qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
 +
 +    for (i = 0; i < MSF2_NUM_SPIS; i++) {
 +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
 +                          TYPE_MSS_SPI);
 +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 +    }
 +}
 +
 +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
 +{
 +    MSF2State *s = MSF2_SOC(dev_soc);
 +    DeviceState *dev, *armv7m;
 +    SysBusDevice *busdev;
 +    Error *err = NULL;
 +    int i;
 +
 +    MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *nvm = g_new(MemoryRegion, 1);
 +    MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
 +    MemoryRegion *sram = g_new(MemoryRegion, 1);
 +
 +    memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
 +                           &error_fatal);
 +    /*
 +     * On power-on, the eNVM region 0x60000000 is automatically
 +     * remapped to the Cortex-M3 processor executable region
 +     * start address (0x0). We do not support remapping other eNVM,
 +     * eSRAM and DDR regions by guest(via Sysreg) currently.
 +     */
 +    memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
 +                             nvm, 0, s->envm_size);
 +
 +    memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
 +    memory_region_add_subregion(system_memory, 0, nvm_alias);
 +
 +    memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
 +                           &error_fatal);
 +    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 +
 +    armv7m = DEVICE(&s->armv7m);
 +    qdev_prop_set_uint32(armv7m, "num-irq", 81);
 +    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 +    object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
 +                                     "memory", &error_abort);
 +    object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
 +    if (err != NULL) {
 +        error_propagate(errp, err);
 +        return;
 +    }
 +
 +    if (!s->m3clk) {
 +        error_setg(errp, "Invalid m3clk value");
 +        error_append_hint(errp, "m3clk can not be zero\n");
 +        return;
 +    }
 +    system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
 +
 +    for (i = 0; i < MSF2_NUM_UARTS; i++) {
 +        if (serial_hds[i]) {
 +            serial_mm_init(get_system_memory(), uart_addr[i], 2,
 +                           qdev_get_gpio_in(armv7m, uart_irq[i]),
 +                           115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
 +        }
-+    }
+         if (c->has_core_id) {
-+
+             monitor_printf(mon, "    core-id: \"%" PRIu64 "\"\n", c->core_id);
-+    dev = DEVICE(&s->timer);
+         }
-+    /* APB0 clock is the timer input clock */
+diff --git a/hw/core/machine.c b/hw/core/machine.c
-+    qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
+index XXXXXXX..XXXXXXX 100644
-+    object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
+--- a/hw/core/machine.c
-+    if (err != NULL) {
++++ b/hw/core/machine.c
-+        error_propagate(errp, err);
+@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
-+        return;
+             return;
-+    }
+         }
-+    busdev = SYS_BUS_DEVICE(dev);
-+    sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
++        if (props->has_cluster_id && !slot->props.has_cluster_id) {
-+    sysbus_connect_irq(busdev, 0,
++            error_setg(errp, "cluster-id is not supported");
 +                           qdev_get_gpio_in(armv7m, timer_irq[0]));
 +    sysbus_connect_irq(busdev, 1,
 +                           qdev_get_gpio_in(armv7m, timer_irq[1]));
 +
 +    dev = DEVICE(&s->sysreg);
 +    qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
 +    qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
 +    object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
 +    if (err != NULL) {
 +        error_propagate(errp, err);
 +        return;
 +    }
 +    busdev = SYS_BUS_DEVICE(dev);
 +    sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
 +
 +    for (i = 0; i < MSF2_NUM_SPIS; i++) {
 +        gchar *bus_name;
 +
 +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 +        if (err != NULL) {
 +            error_propagate(errp, err);
 +            return;
 +        }
 +
-+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
+         if (props->has_socket_id && !slot->props.has_socket_id) {
-+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+             error_setg(errp, "socket-id is not supported");
-+                           qdev_get_gpio_in(armv7m, spi_irq[i]));
+             return;
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
                  continue;
          }
 +        if (props->has_cluster_id &&
 +            props->cluster_id != slot->props.cluster_id) {
 +                continue;
 +        }
 +
-+        /* Alias controller SPI bus to the SoC itself */
+         if (props->has_die_id && props->die_id != slot->props.die_id) {
-+        bus_name = g_strdup_printf("spi%d", i);
+                 continue;
-+        object_property_add_alias(OBJECT(s), bus_name,
+         }
-+                                  OBJECT(&s->spi[i]), "spi",
+@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
-+                                  &error_abort);
+         }
-+        g_free(bus_name);
+         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
      }
 +    if (cpu->props.has_cluster_id) {
 +        if (s->len) {
 +            g_string_append_printf(s, ", ");
 +        }
 +        g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
 +    }
-+
+     if (cpu->props.has_core_id) {
-+    /* Below devices are not modelled yet. */
+         if (s->len) {
-+    create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
+             g_string_append_printf(s, ", ");
 +    create_unimplemented_device("dma", 0x40003000, 0x1000);
 +    create_unimplemented_device("watchdog", 0x40005000, 0x1000);
 +    create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
 +    create_unimplemented_device("gpio", 0x40013000, 0x1000);
 +    create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
 +    create_unimplemented_device("can", 0x40015000, 0x1000);
 +    create_unimplemented_device("rtc", 0x40017000, 0x1000);
 +    create_unimplemented_device("apb_config", 0x40020000, 0x10000);
 +    create_unimplemented_device("emac", 0x40041000, 0x1000);
 +    create_unimplemented_device("usb", 0x40043000, 0x1000);
 +}
 +
 +static Property m2sxxx_soc_properties[] = {
 +    /*
 +     * part name specifies the type of SmartFusion2 device variant(this
 +     * property is for information purpose only.
 +     */
 +    DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
 +    DEFINE_PROP_STRING("part-name", MSF2State, part_name),
 +    DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
 +    DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
 +                        MSF2_ESRAM_MAX_SIZE),
 +    /* Libero GUI shows 100Mhz as default for clocks */
 +    DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
 +    /* default divisors in Libero GUI */
 +    DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
 +    DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = m2sxxx_soc_realize;
 +    dc->props = m2sxxx_soc_properties;
 +}
 +
 +static const TypeInfo m2sxxx_soc_info = {
 +    .name          = TYPE_MSF2_SOC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(MSF2State),
 +    .instance_init = m2sxxx_soc_initfn,
 +    .class_init    = m2sxxx_soc_class_init,
 +};
 +
 +static void m2sxxx_soc_types(void)
 +{
 +    type_register_static(&m2sxxx_soc_info);
 +}
 +
 +type_init(m2sxxx_soc_types)
 diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/default-configs/arm-softmmu.mak
 +++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_ACPI=y
  CONFIG_SMBIOS=y
  CONFIG_ASPEED_SOC=y
  CONFIG_GPIO_KEY=y
 +CONFIG_MSF2=y
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 07/31] nvic: Implement NVIC_ITNS<n> registers
+[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
-For v8M, the NVIC has a new set of registers per interrupt,
+From: Gavin Shan <gshan@redhat.com>
 NVIC_ITNS<n>. These determine whether the interrupt targets Secure
 or Non-secure state. Implement the register read/write code for
 these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
 NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
 accesses to fields corresponding to interrupts which are
 configured to target secure state.
+The CPU topology isn't enabled on arm/virt machine yet, but we're
+going to do it in next patch. After the CPU topology is enabled by
+next patch, "thread-id=1" becomes invalid because the CPU core is
+preferred on arm/virt machine. It means these two CPUs have 0/1
+as their core IDs, but their thread IDs are all 0. It will trigger
+test failure as the following message indicates:
+  [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test  ERROR
+.48s   killed by signal 6 SIGABRT
+  >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
+      QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon         \
+      QTEST_QEMU_BINARY=./qemu-system-aarch64                                       \
+      QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83                                  \
+      /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
+  ――――――――――――――――――――――――――――――――――――――――――――――
+  stderr:
+  qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
+This fixes the issue by providing comprehensive SMP configurations
+in aarch64_numa_cpu(). The SMP configurations aren't used before
+the CPU topology is enabled in next patch.
+Signed-off-by: Gavin Shan <gshan@redhat.com>
+Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Message-id: 20220503140304.855514-3-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
 ---
- include/hw/intc/armv7m_nvic.h |  3 ++
+ tests/qtest/numa-test.c | 3 ++-
- hw/intc/armv7m_nvic.c         | 74 +++++++++++++++++++++++++++++++++++++++----
+file changed, 2 insertions(+), 1 deletion(-)
 files changed, 70 insertions(+), 7 deletions(-)
-diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
+diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/armv7m_nvic.h
+--- a/tests/qtest/numa-test.c
-+++ b/include/hw/intc/armv7m_nvic.h
++++ b/tests/qtest/numa-test.c
-@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
+@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
-     /* The PRIGROUP field in AIRCR is banked */
+     QTestState *qts;
-     uint32_t prigroup[M_REG_NUM_BANKS];
+     g_autofree char *cli = NULL;
-+    /* v8M NVIC_ITNS state (stored as a bool per bit) */
+-    cli = make_cli(data, "-machine smp.cpus=2 "
-+    bool itns[NVIC_MAX_VECTORS];
++    cli = make_cli(data, "-machine "
-+
++        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
-     /* The following fields are all cached state that can be recalculated
+         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
-      * from the vectors[] and sec_vectors[] arrays and the prigroup field:
+         "-numa cpu,node-id=1,thread-id=0 "
-      *  - vectpending
+         "-numa cpu,node-id=0,thread-id=1");
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
      switch (offset) {
      case 4: /* Interrupt Control Type.  */
          return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
 +    case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
 +    {
 +        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
 +        int i;
 +
 +        if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
 +            goto bad_offset;
 +        }
 +        if (!attrs.secure) {
 +            return 0;
 +        }
 +        val = 0;
 +        for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
 +            if (s->itns[startvec + i]) {
 +                val |= (1 << i);
 +            }
 +        }
 +        return val;
 +    }
      case 0xd00: /* CPUID Base.  */
          return cpu->midr;
      case 0xd04: /* Interrupt Control State.  */
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
      ARMCPU *cpu = s->cpu;
      switch (offset) {
 +    case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
 +    {
 +        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
 +        int i;
 +
 +        if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
 +            goto bad_offset;
 +        }
 +        if (!attrs.secure) {
 +            break;
 +        }
 +        for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
 +            s->itns[startvec + i] = (value >> i) & 1;
 +        }
 +        nvic_irq_update(s);
 +        break;
 +    }
      case 0xd04: /* Interrupt Control State.  */
          if (value & (1 << 31)) {
              armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
          startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
          for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
 -            if (s->vectors[startvec + i].enabled) {
 +            if (s->vectors[startvec + i].enabled &&
 +                (attrs.secure || s->itns[startvec + i])) {
                  val |= (1 << i);
              }
          }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
          val = 0;
          startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
          for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
 -            if (s->vectors[startvec + i].pending) {
 +            if (s->vectors[startvec + i].pending &&
 +                (attrs.secure || s->itns[startvec + i])) {
                  val |= (1 << i);
              }
          }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
          startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
          for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
 -            if (s->vectors[startvec + i].active) {
 +            if (s->vectors[startvec + i].active &&
 +                (attrs.secure || s->itns[startvec + i])) {
                  val |= (1 << i);
              }
          }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
          startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
          for (i = 0; i < size && startvec + i < s->num_irq; i++) {
 -            val |= s->vectors[startvec + i].prio << (8 * i);
 +            if (attrs.secure || s->itns[startvec + i]) {
 +                val |= s->vectors[startvec + i].prio << (8 * i);
 +            }
          }
          break;
      case 0xd18 ... 0xd23: /* System Handler Priority.  */
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
          startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
          for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
 -            if (value & (1 << i)) {
 +            if (value & (1 << i) &&
 +                (attrs.secure || s->itns[startvec + i])) {
                  s->vectors[startvec + i].enabled = setval;
              }
          }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
          startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
          for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
 -            if (value & (1 << i)) {
 +            if (value & (1 << i) &&
 +                (attrs.secure || s->itns[startvec + i])) {
                  s->vectors[startvec + i].pending = setval;
              }
          }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
          startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
          for (i = 0; i < size && startvec + i < s->num_irq; i++) {
 -            set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
 +            if (attrs.secure || s->itns[startvec + i]) {
 +                set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
 +            }
          }
          nvic_irq_update(s);
          return MEMTX_OK;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
          VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
                               vmstate_VecInfo, VecInfo),
          VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
 +        VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),
          VMSTATE_END_OF_LIST()
      }
  };
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
      s->vectpending = 0;
      s->vectpending_is_s_banked = false;
      s->vectpending_prio = NVIC_NOEXC_PRIO;
 +
 +    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
 +        memset(s->itns, 0, sizeof(s->itns));
 +    } else {
 +        /* This state is constant and not guest accessible in a non-security
 +         * NVIC; we set the bits to true to avoid having to do a feature
 +         * bit check in the NVIC enable/pend/etc register accessors.
 +         */
 +        int i;
 +
 +        for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {
 +            s->itns[i] = true;
 +        }
 +    }
  }
  static void nvic_systick_trigger(void *opaque, int n, int level)
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 15/31] nvic: Handle v8M changes in nvic_exec_prio()
+[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
-Update nvic_exec_prio() to support the v8M changes:
+From: Gavin Shan <gshan@redhat.com>
  * BASEPRI, FAULTMASK and PRIMASK are all banked
  * AIRCR.PRIS can affect NS priorities
  * AIRCR.BFHFNMINS affects FAULTMASK behaviour
-These changes mean that it's no longer possible to
+Currently, the SMP configuration isn't considered when the CPU
-definitely say that if FAULTMASK is set it overrides
+topology is populated. In this case, it's impossible to provide
-PRIMASK, and if PRIMASK is set it overrides BASEPRI
+the default CPU-to-NUMA mapping or association based on the socket
-(since if PRIMASK_NS is set and AIRCR.PRIS is set then
+ID of the given CPU.
 whether that 0x80 priority should take effect or the
 priority in BASEPRI_S depends on the value of BASEPRI_S,
 for instance). So we switch to the same approach used
 by the pseudocode of working through BASEPRI, PRIMASK
 and FAULTMASK and overriding the previous values if
 needed.
+This takes account of SMP configuration when the CPU topology
+is populated. The die ID for the given CPU isn't assigned since
+it's not supported on arm/virt machine. Besides, the used SMP
+configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
+to avoid testing failure
+Signed-off-by: Gavin Shan <gshan@redhat.com>
+Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Acked-by: Igor Mammedov <imammedo@redhat.com>
+Message-id: 20220503140304.855514-4-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-16-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 51 ++++++++++++++++++++++++++++++++++++++++++---------
+ hw/arm/virt.c | 15 ++++++++++++++-
-file changed, 42 insertions(+), 9 deletions(-)
+file changed, 14 insertions(+), 1 deletion(-)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/hw/arm/virt.c
-+++ b/hw/intc/armv7m_nvic.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
+@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
- static inline int nvic_exec_prio(NVICState *s)
+     int n;
- {
+     unsigned int max_cpus = ms->smp.max_cpus;
-     CPUARMState *env = &s->cpu->env;
+     VirtMachineState *vms = VIRT_MACHINE(ms);
--    int running;
++    MachineClass *mc = MACHINE_GET_CLASS(vms);
-+    int running = NVIC_NOEXC_PRIO;
+     if (ms->possible_cpus) {
--    if (env->v7m.faultmask[env->v7m.secure]) {
+         assert(ms->possible_cpus->len == max_cpus);
--        running = -1;
+@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
--    } else if (env->v7m.primask[env->v7m.secure]) {
+         ms->possible_cpus->cpus[n].type = ms->cpu_type;
-+    if (env->v7m.basepri[M_REG_NS] > 0) {
+         ms->possible_cpus->cpus[n].arch_id =
-+        running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
+             virt_cpu_mp_affinity(vms, n);
 +    }
 +
-+    if (env->v7m.basepri[M_REG_S] > 0) {
++        assert(!mc->smp_props.dies_supported);
-+        int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
++        ms->possible_cpus->cpus[n].props.has_socket_id = true;
-+        if (running > basepri) {
++        ms->possible_cpus->cpus[n].props.socket_id =
-+            running = basepri;
++            n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
-+        }
++        ms->possible_cpus->cpus[n].props.has_cluster_id = true;
-+    }
++        ms->possible_cpus->cpus[n].props.cluster_id =
-+
++            (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
-+    if (env->v7m.primask[M_REG_NS]) {
++        ms->possible_cpus->cpus[n].props.has_core_id = true;
-+        if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
++        ms->possible_cpus->cpus[n].props.core_id =
-+            if (running > NVIC_NS_PRIO_LIMIT) {
++            (n / ms->smp.threads) % ms->smp.cores;
-+                running = NVIC_NS_PRIO_LIMIT;
+         ms->possible_cpus->cpus[n].props.has_thread_id = true;
-+            }
+-        ms->possible_cpus->cpus[n].props.thread_id = n;
-+        } else {
++        ms->possible_cpus->cpus[n].props.thread_id =
-+            running = 0;
++            n % ms->smp.threads;
 +        }
 +    }
 +
 +    if (env->v7m.primask[M_REG_S]) {
          running = 0;
 -    } else if (env->v7m.basepri[env->v7m.secure] > 0) {
 -        running = env->v7m.basepri[env->v7m.secure] &
 -            nvic_gprio_mask(s, env->v7m.secure);
 -    } else {
 -        running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
      }
-+
+     return ms->possible_cpus;
 +    if (env->v7m.faultmask[M_REG_NS]) {
 +        if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
 +            running = -1;
 +        } else {
 +            if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
 +                if (running > NVIC_NS_PRIO_LIMIT) {
 +                    running = NVIC_NS_PRIO_LIMIT;
 +                }
 +            } else {
 +                running = 0;
 +            }
 +        }
 +    }
 +
 +    if (env->v7m.faultmask[M_REG_S]) {
 +        running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
 +    }
 +
      /* consider priority of active handler */
      return MIN(running, s->exception_prio);
  }
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked exceptions
+[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
-Update the code in nvic_rettobase() so that it checks the
+From: Gavin Shan <gshan@redhat.com>
 sec_vectors[] array as well as the vectors[] array if needed.
+In aarch64_numa_cpu(), the CPU and NUMA association is something
+like below. Two threads in the same core/cluster/socket are
+associated with two individual NUMA nodes, which is unreal as
+Igor Mammedov mentioned. We don't expect the association to break
+NUMA-to-socket boundary, which matches with the real world.
+    NUMA-node  socket  cluster   core   thread
+    ------------------------------------------
+0        0        0      0
+0        0        0      1
+This corrects the topology for CPUs and their association with
+NUMA nodes. After this patch is applied, the CPU and NUMA
+association becomes something like below, which looks real.
+Besides, socket/cluster/core/thread IDs are all checked when
+the NUMA node IDs are verified. It helps to check if the CPU
+topology is properly populated or not.
+    NUMA-node  socket  cluster   core   thread
+    ------------------------------------------
+1        0        0       0
+0        0        0       0
+Suggested-by: Igor Mammedov <imammedo@redhat.com>
+Signed-off-by: Gavin Shan <gshan@redhat.com>
+Acked-by: Igor Mammedov <imammedo@redhat.com>
+Message-id: 20220503140304.855514-5-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-7-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 5 ++++-
+ tests/qtest/numa-test.c | 18 ++++++++++++------
-file changed, 4 insertions(+), 1 deletion(-)
+file changed, 12 insertions(+), 6 deletions(-)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/tests/qtest/numa-test.c
-+++ b/hw/intc/armv7m_nvic.c
++++ b/tests/qtest/numa-test.c
-@@ -XXX,XX +XXX,XX @@ static int nvic_pending_prio(NVICState *s)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
- static bool nvic_rettobase(NVICState *s)
+     g_autofree char *cli = NULL;
- {
-     int irq, nhand = 0;
+     cli = make_cli(data, "-machine "
-+    bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
+-        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
++        "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
-     for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
+         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
--        if (s->vectors[irq].active) {
+-        "-numa cpu,node-id=1,thread-id=0 "
-+        if (s->vectors[irq].active ||
+-        "-numa cpu,node-id=0,thread-id=1");
-+            (check_sec && irq < NVIC_INTERNAL_VECTORS &&
++        "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
-+             s->sec_vectors[irq].active)) {
++        "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
-             nhand++;
+     qts = qtest_init(cli);
-             if (nhand == 2) {
+     cpus = get_cpus(qts, &resp);
-                 return 0;
+     g_assert(cpus);
      while ((e = qlist_pop(cpus))) {
          QDict *cpu, *props;
 -        int64_t thread, node;
 +        int64_t socket, cluster, core, thread, node;
          cpu = qobject_to(QDict, e);
          g_assert(qdict_haskey(cpu, "props"));
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
          g_assert(qdict_haskey(props, "node-id"));
          node = qdict_get_int(props, "node-id");
 +        g_assert(qdict_haskey(props, "socket-id"));
 +        socket = qdict_get_int(props, "socket-id");
 +        g_assert(qdict_haskey(props, "cluster-id"));
 +        cluster = qdict_get_int(props, "cluster-id");
 +        g_assert(qdict_haskey(props, "core-id"));
 +        core = qdict_get_int(props, "core-id");
          g_assert(qdict_haskey(props, "thread-id"));
          thread = qdict_get_int(props, "thread-id");
 -        if (thread == 0) {
 +        if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
              g_assert_cmpint(node, ==, 1);
 -        } else if (thread == 1) {
 +        } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
              g_assert_cmpint(node, ==, 0);
          } else {
              g_assert(false);
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 04/31] nvic: Add cached vectpending_prio state
+[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
-Instead of looking up the pending priority
+From: Gavin Shan <gshan@redhat.com>
 in nvic_pending_prio(), cache it in a new state struct
 field. The calculation of the pending priority given
 the interrupt number is more complicated in v8M with
 the security extension, so the caching will be worthwhile.
-This changes nvic_pending_prio() from returning a full
+When CPU-to-NUMA association isn't explicitly provided by users,
-(group + subpriority) priority value to returning a group
+the default one is given by mc->get_default_cpu_node_id(). However,
-priority. This doesn't require changes to its callsites
+the CPU topology isn't fully considered in the default association
-because we use it only in comparisons of the form
+and this causes CPU topology broken warnings on booting Linux guest.
   execution_prio > nvic_pending_prio()
 and execution priority is always a group priority, so
 a test (exec prio > full prio) is true if and only if
 (execprio > group_prio).
-(Architecturally the expected comparison is with the
+For example, the following warning messages are observed when the
-group priority for this sort of "would we preempt" test;
+Linux guest is booted with the following command lines.
 we were only doing a test with a full priority as an
 optimisation to avoid the mask, which is possible
 precisely because the two comparisons always give the
 same answer.)
+  /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
+  -accel kvm -machine virt,gic-version=host               \
+  -cpu host                                               \
+  -smp 6,sockets=2,cores=3,threads=1                      \
+  -m 1024M,slots=16,maxmem=64G                            \
+  -object memory-backend-ram,id=mem0,size=128M            \
+  -object memory-backend-ram,id=mem1,size=128M            \
+  -object memory-backend-ram,id=mem2,size=128M            \
+  -object memory-backend-ram,id=mem3,size=128M            \
+  -object memory-backend-ram,id=mem4,size=128M            \
+  -object memory-backend-ram,id=mem4,size=384M            \
+  -numa node,nodeid=0,memdev=mem0                         \
+  -numa node,nodeid=1,memdev=mem1                         \
+  -numa node,nodeid=2,memdev=mem2                         \
+  -numa node,nodeid=3,memdev=mem3                         \
+  -numa node,nodeid=4,memdev=mem4                         \
+  -numa node,nodeid=5,memdev=mem5
+         :
+  alternatives: patching kernel code
+  BUG: arch topology borken
+  the CLS domain not a subset of the MC domain
+  <the above error log repeats>
+  BUG: arch topology borken
+  the DIE domain not a subset of the NODE domain
+With current implementation of mc->get_default_cpu_node_id(),
+CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
+That's incorrect because CPU#0/1/2 should be associated with same
+NUMA node because they're seated in same socket.
+This fixes the issue by considering the socket ID when the default
+CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
+With this applied, no more CPU topology broken warnings are seen
+from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
+there are no CPUs associated with NODE#2/3/4/5.
+Signed-off-by: Gavin Shan <gshan@redhat.com>
+Reviewed-by: Igor Mammedov <imammedo@redhat.com>
+Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Message-id: 20220503140304.855514-6-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
 ---
- include/hw/intc/armv7m_nvic.h |  2 ++
+ hw/arm/virt.c | 4 +++-
- hw/intc/armv7m_nvic.c         | 23 +++++++++++++----------
+file changed, 3 insertions(+), 1 deletion(-)
  hw/intc/trace-events          |  2 +-
 files changed, 16 insertions(+), 11 deletions(-)
-diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/armv7m_nvic.h
+--- a/hw/arm/virt.c
-+++ b/include/hw/intc/armv7m_nvic.h
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
+@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
-      *  - vectpending
-      *  - vectpending_is_secure
+ static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
       *  - exception_prio
 +     *  - vectpending_prio
       */
      unsigned int vectpending; /* highest prio pending enabled exception */
      /* true if vectpending is a banked secure exception, ie it is in
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
       */
      bool vectpending_is_s_banked;
      int exception_prio; /* group prio of the highest prio active exception */
 +    int vectpending_prio; /* group prio of the exeception in vectpending */
      MemoryRegion sysregmem;
      MemoryRegion sysreg_ns_mem;
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
  static int nvic_pending_prio(NVICState *s)
  {
--    /* return the priority of the current pending interrupt,
+-    return idx % ms->numa_state->num_nodes;
-+    /* return the group priority of the current pending interrupt,
++    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
-      * or NVIC_NOEXC_PRIO if no interrupt is pending
++
-      */
++    return socket_id % ms->numa_state->num_nodes;
 -    return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
 +    return s->vectpending_prio;
  }
- /* Return the value of the ISCR RETTOBASE bit:
+ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
          active_prio &= nvic_gprio_mask(s);
      }
 +    if (pend_prio > 0) {
 +        pend_prio &= nvic_gprio_mask(s);
 +    }
 +
      s->vectpending = pend_irq;
 +    s->vectpending_prio = pend_prio;
      s->exception_prio = active_prio;
 -    trace_nvic_recompute_state(s->vectpending, s->exception_prio);
 +    trace_nvic_recompute_state(s->vectpending,
 +                               s->vectpending_prio,
 +                               s->exception_prio);
  }
  /* Return the current execution priority of the CPU
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
      CPUARMState *env = &s->cpu->env;
      const int pending = s->vectpending;
      const int running = nvic_exec_prio(s);
 -    int pendgroupprio;
      VecInfo *vec;
      assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
      assert(vec->enabled);
      assert(vec->pending);
 -    pendgroupprio = vec->prio;
 -    if (pendgroupprio > 0) {
 -        pendgroupprio &= nvic_gprio_mask(s);
 -    }
 -    assert(pendgroupprio < running);
 +    assert(s->vectpending_prio < running);
 -    trace_nvic_acknowledge_irq(pending, vec->prio);
 +    trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
      vec->active = 1;
      vec->pending = 0;
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
      s->exception_prio = NVIC_NOEXC_PRIO;
      s->vectpending = 0;
      s->vectpending_is_s_banked = false;
 +    s->vectpending_prio = NVIC_NOEXC_PRIO;
  }
  static void nvic_systick_trigger(void *opaque, int n, int level)
 diff --git a/hw/intc/trace-events b/hw/intc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/trace-events
 +++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor 0x%x
  gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending SGI %d"
  # hw/intc/armv7m_nvic.c
 -nvic_recompute_state(int vectpending, int exception_prio) "NVIC state recomputed: vectpending %d exception_prio %d"
 +nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
  nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
  nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
  nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
 --
-.7.4
+.25.1

-[Qemu-devel] [PULL 03/31] nvic: Add cached vectpending_is_s_banked state
+[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
-With banked exceptions, just the exception number in
+From: Gavin Shan <gshan@redhat.com>
 s->vectpending is no longer sufficient to uniquely identify
 the pending exception. Add a vectpending_is_s_banked bool
 which is true if the exception is using the sec_vectors[]
 array.
+When the PPTT table is built, the CPU topology is re-calculated, but
+it's unecessary because the CPU topology has been populated in
+virt_possible_cpu_arch_ids() on arm/virt machine.
+This reworks build_pptt() to avoid by reusing the existing IDs in
+ms->possible_cpus. Currently, the only user of build_pptt() is
+arm/virt machine.
+Signed-off-by: Gavin Shan <gshan@redhat.com>
+Tested-by: Yanan Wang <wangyanan55@huawei.com>
+Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
+Acked-by: Igor Mammedov <imammedo@redhat.com>
+Acked-by: Michael S. Tsirkin <mst@redhat.com>
+Message-id: 20220503140304.855514-7-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
 ---
- include/hw/intc/armv7m_nvic.h | 11 +++++++++--
+ hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
- hw/intc/armv7m_nvic.c         |  1 +
+file changed, 48 insertions(+), 63 deletions(-)
 files changed, 10 insertions(+), 2 deletions(-)
-diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
+diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/armv7m_nvic.h
+--- a/hw/acpi/aml-build.c
-+++ b/include/hw/intc/armv7m_nvic.h
++++ b/hw/acpi/aml-build.c
-@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
+@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
-     VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
+                 const char *oem_id, const char *oem_table_id)
-     uint32_t prigroup;
+ {
+     MachineClass *mc = MACHINE_GET_CLASS(ms);
--    /* vectpending and exception_prio are both cached state that can
+-    GQueue *list = g_queue_new();
--     * be recalculated from the vectors[] array and the prigroup field.
+-    guint pptt_start = table_data->len;
-+    /* The following fields are all cached state that can be recalculated
+-    guint parent_offset;
-+     * from the vectors[] and sec_vectors[] arrays and the prigroup field:
+-    guint length, i;
-+     *  - vectpending
+-    int uid = 0;
-+     *  - vectpending_is_secure
+-    int socket;
-+     *  - exception_prio
++    CPUArchIdList *cpus = ms->possible_cpus;
-      */
++    int64_t socket_id = -1, cluster_id = -1, core_id = -1;
-     unsigned int vectpending; /* highest prio pending enabled exception */
++    uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
-+    /* true if vectpending is a banked secure exception, ie it is in
++    uint32_t pptt_start = table_data->len;
-+     * sec_vectors[] rather than vectors[]
++    int n;
      AcpiTable table = { .sig = "PPTT", .rev = 2,
                          .oem_id = oem_id, .oem_table_id = oem_table_id };
      acpi_table_begin(&table, table_data);
 -    for (socket = 0; socket < ms->smp.sockets; socket++) {
 -        g_queue_push_tail(list,
 -            GUINT_TO_POINTER(table_data->len - pptt_start));
 -        build_processor_hierarchy_node(
 -            table_data,
 -            /*
 -             * Physical package - represents the boundary
 -             * of a physical package
 -             */
 -            (1 << 0),
 -            0, socket, NULL, 0);
 -    }
 -
 -    if (mc->smp_props.clusters_supported) {
 -        length = g_queue_get_length(list);
 -        for (i = 0; i < length; i++) {
 -            int cluster;
 -
 -            parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -            for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
 -                g_queue_push_tail(list,
 -                    GUINT_TO_POINTER(table_data->len - pptt_start));
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (0 << 0), /* not a physical package */
 -                    parent_offset, cluster, NULL, 0);
 -            }
 +    /*
 +     * This works with the assumption that cpus[n].props.*_id has been
 +     * sorted from top to down levels in mc->possible_cpu_arch_ids().
 +     * Otherwise, the unexpected and duplicated containers will be
 +     * created.
 +     */
-+    bool vectpending_is_s_banked;
++    for (n = 0; n < cpus->len; n++) {
-     int exception_prio; /* group prio of the highest prio active exception */
++        if (cpus->cpus[n].props.socket_id != socket_id) {
++            assert(cpus->cpus[n].props.socket_id > socket_id);
-     MemoryRegion sysregmem;
++            socket_id = cpus->cpus[n].props.socket_id;
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
++            cluster_id = -1;
-index XXXXXXX..XXXXXXX 100644
++            core_id = -1;
---- a/hw/intc/armv7m_nvic.c
++            socket_offset = table_data->len - pptt_start;
-+++ b/hw/intc/armv7m_nvic.c
++            build_processor_hierarchy_node(table_data,
-@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
++                (1 << 0), /* Physical package */
++                0, socket_id, NULL, 0);
-     s->exception_prio = NVIC_NOEXC_PRIO;
+         }
-     s->vectpending = 0;
+-    }
-+    s->vectpending_is_s_banked = false;
 -    length = g_queue_get_length(list);
 -    for (i = 0; i < length; i++) {
 -        int core;
 -
 -        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -        for (core = 0; core < ms->smp.cores; core++) {
 -            if (ms->smp.threads > 1) {
 -                g_queue_push_tail(list,
 -                    GUINT_TO_POINTER(table_data->len - pptt_start));
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (0 << 0), /* not a physical package */
 -                    parent_offset, core, NULL, 0);
 -            } else {
 -                build_processor_hierarchy_node(
 -                    table_data,
 -                    (1 << 1) | /* ACPI Processor ID valid */
 -                    (1 << 3),  /* Node is a Leaf */
 -                    parent_offset, uid++, NULL, 0);
 +        if (mc->smp_props.clusters_supported) {
 +            if (cpus->cpus[n].props.cluster_id != cluster_id) {
 +                assert(cpus->cpus[n].props.cluster_id > cluster_id);
 +                cluster_id = cpus->cpus[n].props.cluster_id;
 +                core_id = -1;
 +                cluster_offset = table_data->len - pptt_start;
 +                build_processor_hierarchy_node(table_data,
 +                    (0 << 0), /* Not a physical package */
 +                    socket_offset, cluster_id, NULL, 0);
              }
 +        } else {
 +            cluster_offset = socket_offset;
          }
 -    }
 -    length = g_queue_get_length(list);
 -    for (i = 0; i < length; i++) {
 -        int thread;
 +        if (ms->smp.threads == 1) {
 +            build_processor_hierarchy_node(table_data,
 +                (1 << 1) | /* ACPI Processor ID valid */
 +                (1 << 3),  /* Node is a Leaf */
 +                cluster_offset, n, NULL, 0);
 +        } else {
 +            if (cpus->cpus[n].props.core_id != core_id) {
 +                assert(cpus->cpus[n].props.core_id > core_id);
 +                core_id = cpus->cpus[n].props.core_id;
 +                core_offset = table_data->len - pptt_start;
 +                build_processor_hierarchy_node(table_data,
 +                    (0 << 0), /* Not a physical package */
 +                    cluster_offset, core_id, NULL, 0);
 +            }
 -        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
 -        for (thread = 0; thread < ms->smp.threads; thread++) {
 -            build_processor_hierarchy_node(
 -                table_data,
 +            build_processor_hierarchy_node(table_data,
                  (1 << 1) | /* ACPI Processor ID valid */
                  (1 << 2) | /* Processor is a Thread */
                  (1 << 3),  /* Node is a Leaf */
 -                parent_offset, uid++, NULL, 0);
 +                core_offset, n, NULL, 0);
          }
      }
 -    g_queue_free(list);
      acpi_table_end(linker, &table);
  }
- static void nvic_systick_trigger(void *opaque, int n, int level)
 --
-.7.4
+.25.1

ARM queue: mostly patches from me, but also the Smartfusion2 board.

thanks
-- PMM

The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:

Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921

for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:

msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)

----------------------------------------------------------------
target-arm queue:
 * more preparatory work for v8M support
 * convert some omap devices away from old_mmio
 * remove out of date ARM ARM section references in comments
 * add the Smartfusion2 board

----------------------------------------------------------------
Peter Maydell (26):
      target/arm: Implement MSR/MRS access to NS banked registers
      nvic: Add banked exception states
      nvic: Add cached vectpending_is_s_banked state
      nvic: Add cached vectpending_prio state
      nvic: Implement AIRCR changes for v8M
      nvic: Make ICSR.RETTOBASE handle banked exceptions
      nvic: Implement NVIC_ITNS<n> registers
      nvic: Handle banked exceptions in nvic_recompute_state()
      nvic: Make set_pending and clear_pending take a secure parameter
      nvic: Make SHPR registers banked
      nvic: Compare group priority for escalation to HF
      nvic: In escalation to HardFault, support HF not being priority -1
      nvic: Implement v8M changes to fixed priority exceptions
      nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
      nvic: Handle v8M changes in nvic_exec_prio()
      target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
      nvic: Make ICSR banked for v8M
      nvic: Make SHCSR banked for v8M
      nvic: Support banked exceptions in acknowledge and complete
      target/arm: Remove out of date ARM ARM section references in A64 decoder
      hw/arm/palm.c: Don't use old_mmio for static_ops
      hw/gpio/omap_gpio.c: Don't use old_mmio
      hw/timer/omap_synctimer.c: Don't use old_mmio
      hw/timer/omap_gptimer: Don't use old_mmio
      hw/i2c/omap_i2c.c: Don't use old_mmio
      hw/arm/omap2.c: Don't use old_mmio

Subbaraya Sundeep (5):
      msf2: Add Smartfusion2 System timer
      msf2: Microsemi Smartfusion2 System Register block
      msf2: Add Smartfusion2 SPI controller
      msf2: Add Smartfusion2 SoC
      msf2: Add Emcraft's Smartfusion2 SOM kit

hw/arm/Makefile.objs            |   1 +
 hw/misc/Makefile.objs           |   1 +
 hw/ssi/Makefile.objs            |   1 +
 hw/timer/Makefile.objs          |   1 +
 include/hw/arm/msf2-soc.h       |  67 +++
 include/hw/intc/armv7m_nvic.h   |  33 +-
 include/hw/misc/msf2-sysreg.h   |  77 ++++
 include/hw/ssi/mss-spi.h        |  58 +++
 include/hw/timer/mss-timer.h    |  64 +++
 target/arm/cpu.h                |  62 ++-
 hw/arm/msf2-soc.c               | 238 +++++++++++
 hw/arm/msf2-som.c               | 105 +++++
 hw/arm/omap2.c                  |  49 ++-
 hw/arm/palm.c                   |  30 +-
 hw/gpio/omap_gpio.c             |  26 +-
 hw/i2c/omap_i2c.c               |  44 +-
 hw/intc/armv7m_nvic.c           | 913 ++++++++++++++++++++++++++++++++++------
 hw/misc/msf2-sysreg.c           | 160 +++++++
 hw/ssi/mss-spi.c                | 404 ++++++++++++++++++
 hw/timer/mss-timer.c            | 289 +++++++++++++
 hw/timer/omap_gptimer.c         |  49 ++-
 hw/timer/omap_synctimer.c       |  35 +-
 target/arm/cpu.c                |   7 +
 target/arm/helper.c             | 142 ++++++-
 target/arm/translate-a64.c      | 227 +++++-----
 default-configs/arm-softmmu.mak |   1 +
 hw/intc/trace-events            |  13 +-
 hw/misc/trace-events            |   5 +
 28 files changed, 2735 insertions(+), 367 deletions(-)
 create mode 100644 include/hw/arm/msf2-soc.h
 create mode 100644 include/hw/misc/msf2-sysreg.h
 create mode 100644 include/hw/ssi/mss-spi.h
 create mode 100644 include/hw/timer/mss-timer.h
 create mode 100644 hw/arm/msf2-soc.c
 create mode 100644 hw/arm/msf2-som.c
 create mode 100644 hw/misc/msf2-sysreg.c
 create mode 100644 hw/ssi/mss-spi.c
 create mode 100644 hw/timer/mss-timer.c

In v8M the MSR and MRS instructions have extra register value
encodings to allow secure code to access the non-secure banked
version of various special registers.

(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because
we don't currently implement the stack limit registers at all.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
         break;
     case 20: /* CONTROL */
         return env->v7m.control[env->v7m.secure];
+    case 0x94: /* CONTROL_NS */
+        /* We have to handle this here because unprivileged Secure code
+         * can read the NS CONTROL register.
+         */
+        if (!env->v7m.secure) {
+            return 0;
+        }
+        return env->v7m.control[M_REG_NS];
     }
 
     if (el == 0) {
         return 0; /* unprivileged reads others as zero */
     }
 
+    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+        switch (reg) {
+        case 0x88: /* MSP_NS */
+            if (!env->v7m.secure) {
+                return 0;
+            }
+            return env->v7m.other_ss_msp;
+        case 0x89: /* PSP_NS */
+            if (!env->v7m.secure) {
+                return 0;
+            }
+            return env->v7m.other_ss_psp;
+        case 0x90: /* PRIMASK_NS */
+            if (!env->v7m.secure) {
+                return 0;
+            }
+            return env->v7m.primask[M_REG_NS];
+        case 0x91: /* BASEPRI_NS */
+            if (!env->v7m.secure) {
+                return 0;
+            }
+            return env->v7m.basepri[M_REG_NS];
+        case 0x93: /* FAULTMASK_NS */
+            if (!env->v7m.secure) {
+                return 0;
+            }
+            return env->v7m.faultmask[M_REG_NS];
+        case 0x98: /* SP_NS */
+        {
+            /* This gives the non-secure SP selected based on whether we're
+             * currently in handler mode or not, using the NS CONTROL.SPSEL.
+             */
+            bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
+
+            if (!env->v7m.secure) {
+                return 0;
+            }
+            if (!arm_v7m_is_handler_mode(env) && spsel) {
+                return env->v7m.other_ss_psp;
+            } else {
+                return env->v7m.other_ss_msp;
+            }
+        }
+        default:
+            break;
+        }
+    }
+
     switch (reg) {
     case 8: /* MSP */
         return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
         return;
     }
 
+    if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+        switch (reg) {
+        case 0x88: /* MSP_NS */
+            if (!env->v7m.secure) {
+                return;
+            }
+            env->v7m.other_ss_msp = val;
+            return;
+        case 0x89: /* PSP_NS */
+            if (!env->v7m.secure) {
+                return;
+            }
+            env->v7m.other_ss_psp = val;
+            return;
+        case 0x90: /* PRIMASK_NS */
+            if (!env->v7m.secure) {
+                return;
+            }
+            env->v7m.primask[M_REG_NS] = val & 1;
+            return;
+        case 0x91: /* BASEPRI_NS */
+            if (!env->v7m.secure) {
+                return;
+            }
+            env->v7m.basepri[M_REG_NS] = val & 0xff;
+            return;
+        case 0x93: /* FAULTMASK_NS */
+            if (!env->v7m.secure) {
+                return;
+            }
+            env->v7m.faultmask[M_REG_NS] = val & 1;
+            return;
+        case 0x98: /* SP_NS */
+        {
+            /* This gives the non-secure SP selected based on whether we're
+             * currently in handler mode or not, using the NS CONTROL.SPSEL.
+             */
+            bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
+
+            if (!env->v7m.secure) {
+                return;
+            }
+            if (!arm_v7m_is_handler_mode(env) && spsel) {
+                env->v7m.other_ss_psp = val;
+            } else {
+                env->v7m.other_ss_msp = val;
+            }
+            return;
+        }
+        default:
+            break;
+        }
+    }
+
     switch (reg) {
     case 0 ... 7: /* xPSR sub-fields */
         /* only APSR is actually writable */
-- 
2.7.4

For the v8M security extension, some exceptions must be banked
between security states. Add the new vecinfo array which holds
the state for the banked exceptions and migrate it if the
CPU the NVIC is attached to implements the security extension.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 14 ++++++++++++
 hw/intc/armv7m_nvic.c         | 53 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@
 
 /* Highest permitted number of exceptions (architectural limit) */
 #define NVIC_MAX_VECTORS 512
+/* Number of internal exceptions */
+#define NVIC_INTERNAL_VECTORS 16
 
 typedef struct VecInfo {
     /* Exception priorities can range from -3 to 255; only the unmodifiable
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
     ARMCPU *cpu;
 
     VecInfo vectors[NVIC_MAX_VECTORS];
+    /* If the v8M security extension is implemented, some of the internal
+     * exceptions are banked between security states (ie there exists both
+     * a Secure and a NonSecure version of the exception and its state):
+     *  HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
+     * The rest (including all the external exceptions) are not banked, though
+     * they may be configurable to target either Secure or NonSecure state.
+     * We store the secure exception state in sec_vectors[] for the banked
+     * exceptions, and otherwise use only vectors[] (including for exceptions
+     * like SecureFault that unconditionally target Secure state).
+     * Entries in sec_vectors[] for non-banked exception numbers are unused.
+     */
+    VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
     uint32_t prigroup;
 
     /* vectpending and exception_prio are both cached state that can
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
  * For historical reasons QEMU tends to use "interrupt" and
  * "exception" more or less interchangeably.
  */
-#define NVIC_FIRST_IRQ 16
+#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
 
 /* Effective running priority of the CPU when no exception is active
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
     }
 };
 
+static bool nvic_security_needed(void *opaque)
+{
+    NVICState *s = opaque;
+
+    return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
+}
+
+static int nvic_security_post_load(void *opaque, int version_id)
+{
+    NVICState *s = opaque;
+    int i;
+
+    /* Check for out of range priority settings */
+    if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
+        return 1;
+    }
+    for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
+        if (s->sec_vectors[i].prio & ~0xff) {
+            return 1;
+        }
+    }
+    return 0;
+}
+
+static const VMStateDescription vmstate_nvic_security = {
+    .name = "nvic/m-security",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = nvic_security_needed,
+    .post_load = &nvic_security_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
+                             vmstate_VecInfo, VecInfo),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_nvic = {
     .name = "armv7m_nvic",
     .version_id = 4,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
                              vmstate_VecInfo, VecInfo),
         VMSTATE_UINT32(prigroup, NVICState),
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription*[]) {
+        &vmstate_nvic_security,
+        NULL
     }
 };
 
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
     s->vectors[ARMV7M_EXCP_NMI].prio = -2;
     s->vectors[ARMV7M_EXCP_HARD].prio = -1;
 
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
+        s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;
+        s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;
+        s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
+        s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
+
+        /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
+        s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+    }
+
     /* Strictly speaking the reset handler should be enabled.
      * However, we don't simulate soft resets through the NVIC,
      * and the reset vector should never be pended.
-- 
2.7.4

With banked exceptions, just the exception number in
s->vectpending is no longer sufficient to uniquely identify
the pending exception. Add a vectpending_is_s_banked bool
which is true if the exception is using the sec_vectors[]
array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
---
 include/hw/intc/armv7m_nvic.h | 11 +++++++++--
 hw/intc/armv7m_nvic.c         |  1 +
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
     VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
     uint32_t prigroup;
 
-    /* vectpending and exception_prio are both cached state that can
-     * be recalculated from the vectors[] array and the prigroup field.
+    /* The following fields are all cached state that can be recalculated
+     * from the vectors[] and sec_vectors[] arrays and the prigroup field:
+     *  - vectpending
+     *  - vectpending_is_secure
+     *  - exception_prio
      */
     unsigned int vectpending; /* highest prio pending enabled exception */
+    /* true if vectpending is a banked secure exception, ie it is in
+     * sec_vectors[] rather than vectors[]
+     */
+    bool vectpending_is_s_banked;
     int exception_prio; /* group prio of the highest prio active exception */
 
     MemoryRegion sysregmem;
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
 
     s->exception_prio = NVIC_NOEXC_PRIO;
     s->vectpending = 0;
+    s->vectpending_is_s_banked = false;
 }
 
 static void nvic_systick_trigger(void *opaque, int n, int level)
-- 
2.7.4

Instead of looking up the pending priority
in nvic_pending_prio(), cache it in a new state struct
field. The calculation of the pending priority given
the interrupt number is more complicated in v8M with
the security extension, so the caching will be worthwhile.

This changes nvic_pending_prio() from returning a full
(group + subpriority) priority value to returning a group
priority. This doesn't require changes to its callsites
because we use it only in comparisons of the form
  execution_prio > nvic_pending_prio()
and execution priority is always a group priority, so
a test (exec prio > full prio) is true if and only if
(execprio > group_prio).

(Architecturally the expected comparison is with the
group priority for this sort of "would we preempt" test;
we were only doing a test with a full priority as an
optimisation to avoid the mask, which is possible
precisely because the two comparisons always give the
same answer.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
---
 include/hw/intc/armv7m_nvic.h |  2 ++
 hw/intc/armv7m_nvic.c         | 23 +++++++++++++----------
 hw/intc/trace-events          |  2 +-
 3 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
      *  - vectpending
      *  - vectpending_is_secure
      *  - exception_prio
+     *  - vectpending_prio
      */
     unsigned int vectpending; /* highest prio pending enabled exception */
     /* true if vectpending is a banked secure exception, ie it is in
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
      */
     bool vectpending_is_s_banked;
     int exception_prio; /* group prio of the highest prio active exception */
+    int vectpending_prio; /* group prio of the exeception in vectpending */
 
     MemoryRegion sysregmem;
     MemoryRegion sysreg_ns_mem;
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
 
 static int nvic_pending_prio(NVICState *s)
 {
-    /* return the priority of the current pending interrupt,
+    /* return the group priority of the current pending interrupt,
      * or NVIC_NOEXC_PRIO if no interrupt is pending
      */
-    return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
+    return s->vectpending_prio;
 }
 
 /* Return the value of the ISCR RETTOBASE bit:
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
         active_prio &= nvic_gprio_mask(s);
     }
 
+    if (pend_prio > 0) {
+        pend_prio &= nvic_gprio_mask(s);
+    }
+
     s->vectpending = pend_irq;
+    s->vectpending_prio = pend_prio;
     s->exception_prio = active_prio;
 
-    trace_nvic_recompute_state(s->vectpending, s->exception_prio);
+    trace_nvic_recompute_state(s->vectpending,
+                               s->vectpending_prio,
+                               s->exception_prio);
 }
 
 /* Return the current execution priority of the CPU
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
     CPUARMState *env = &s->cpu->env;
     const int pending = s->vectpending;
     const int running = nvic_exec_prio(s);
-    int pendgroupprio;
     VecInfo *vec;
 
     assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
     assert(vec->enabled);
     assert(vec->pending);
 
-    pendgroupprio = vec->prio;
-    if (pendgroupprio > 0) {
-        pendgroupprio &= nvic_gprio_mask(s);
-    }
-    assert(pendgroupprio < running);
+    assert(s->vectpending_prio < running);
 
-    trace_nvic_acknowledge_irq(pending, vec->prio);
+    trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
 
     vec->active = 1;
     vec->pending = 0;
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
     s->exception_prio = NVIC_NOEXC_PRIO;
     s->vectpending = 0;
     s->vectpending_is_s_banked = false;
+    s->vectpending_prio = NVIC_NOEXC_PRIO;
 }
 
 static void nvic_systick_trigger(void *opaque, int n, int level)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor 0x%x
 gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending SGI %d"
 
 # hw/intc/armv7m_nvic.c
-nvic_recompute_state(int vectpending, int exception_prio) "NVIC state recomputed: vectpending %d exception_prio %d"
+nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
 nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
 nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
 nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
-- 
2.7.4

The Application Interrupt and Reset Control Register has some changes
for v8M:
 * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
   real state if the security extension is implemented and otherwise
   are constant
 * the PRIGROUP field is banked between security states
 * non-secure code can be blocked from using the SYSRESET bit
   to reset the system if SYSRESETREQS is set

Implement the new state and the changes to register read and write.
For the moment we ignore the effects of the secure PRIGROUP.
We will implement the effects of PRIS and BFHFNMIS later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
---
 include/hw/intc/armv7m_nvic.h |  3 ++-
 target/arm/cpu.h              | 12 +++++++++++
 hw/intc/armv7m_nvic.c         | 49 +++++++++++++++++++++++++++++++++----------
 target/arm/cpu.c              |  7 +++++++
 4 files changed, 59 insertions(+), 12 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
      * Entries in sec_vectors[] for non-banked exception numbers are unused.
      */
     VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
-    uint32_t prigroup;
+    /* The PRIGROUP field in AIRCR is banked */
+    uint32_t prigroup[M_REG_NUM_BANKS];
 
     /* The following fields are all cached state that can be recalculated
      * from the vectors[] and sec_vectors[] arrays and the prigroup field:
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
         int exception;
         uint32_t primask[M_REG_NUM_BANKS];
         uint32_t faultmask[M_REG_NUM_BANKS];
+        uint32_t aircr; /* only holds r/w state if security extn implemented */
         uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
     } v7m;
 
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1)
 FIELD(V7M_CCR, DC, 16, 1)
 FIELD(V7M_CCR, IC, 17, 1)
 
+/* V7M AIRCR bits */
+FIELD(V7M_AIRCR, VECTRESET, 0, 1)
+FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
+FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
+FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
+FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
+FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
+FIELD(V7M_AIRCR, PRIS, 14, 1)
+FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
+FIELD(V7M_AIRCR, VECTKEY, 16, 16)
+
 /* V7M CFSR bits for MMFSR */
 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
  */
 static inline uint32_t nvic_gprio_mask(NVICState *s)
 {
-    return ~0U << (s->prigroup + 1);
+    return ~0U << (s->prigroup[M_REG_NS] + 1);
 }
 
 /* Recompute vectpending and exception_prio */
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         return val;
     case 0xd08: /* Vector Table Offset.  */
         return cpu->env.v7m.vecbase[attrs.secure];
-    case 0xd0c: /* Application Interrupt/Reset Control.  */
-        return 0xfa050000 | (s->prigroup << 8);
+    case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
+        val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);
+        if (attrs.secure) {
+            /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
+            val |= cpu->env.v7m.aircr;
+        } else {
+            if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+                /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
+                 * security isn't supported then BFHFNMINS is RAO (and
+                 * the bit in env.v7m.aircr is always set).
+                 */
+                val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
+            }
+        }
+        return val;
     case 0xd10: /* System Control.  */
         /* TODO: Implement SLEEPONEXIT.  */
         return 0;
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
     case 0xd08: /* Vector Table Offset.  */
         cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
         break;
-    case 0xd0c: /* Application Interrupt/Reset Control.  */
-        if ((value >> 16) == 0x05fa) {
-            if (value & 4) {
-                qemu_irq_pulse(s->sysresetreq);
+    case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
+        if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
+            if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
+                if (attrs.secure ||
+                    !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
+                    qemu_irq_pulse(s->sysresetreq);
+                }
             }
-            if (value & 2) {
+            if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
                 qemu_log_mask(LOG_GUEST_ERROR,
                               "Setting VECTCLRACTIVE when not in DEBUG mode "
                               "is UNPREDICTABLE\n");
             }
-            if (value & 1) {
+            if (value & R_V7M_AIRCR_VECTRESET_MASK) {
+                /* NB: this bit is RES0 in v8M */
                 qemu_log_mask(LOG_GUEST_ERROR,
                               "Setting VECTRESET when not in DEBUG mode "
                               "is UNPREDICTABLE\n");
             }
-            s->prigroup = extract32(value, 8, 3);
+            s->prigroup[attrs.secure] = extract32(value,
+                                                  R_V7M_AIRCR_PRIGROUP_SHIFT,
+                                                  R_V7M_AIRCR_PRIGROUP_LENGTH);
+            if (attrs.secure) {
+                /* These bits are only writable by secure */
+                cpu->env.v7m.aircr = value &
+                    (R_V7M_AIRCR_SYSRESETREQS_MASK |
+                     R_V7M_AIRCR_BFHFNMINS_MASK |
+                     R_V7M_AIRCR_PRIS_MASK);
+            }
             nvic_irq_update(s);
         }
         break;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
     .fields = (VMStateField[]) {
         VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
                              vmstate_VecInfo, VecInfo),
+        VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
     .fields = (VMStateField[]) {
         VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
                              vmstate_VecInfo, VecInfo),
-        VMSTATE_UINT32(prigroup, NVICState),
+        VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),
         VMSTATE_END_OF_LIST()
     },
     .subsections = (const VMStateDescription*[]) {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
 
         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
             env->v7m.secure = true;
+        } else {
+            /* This bit resets to 0 if security is supported, but 1 if
+             * it is not. The bit is not present in v7M, but we set it
+             * here so we can avoid having to make checks on it conditional
+             * on ARM_FEATURE_V8 (we don't let the guest see the bit).
+             */
+            env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
         }
 
         /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
-- 
2.7.4

Update the code in nvic_rettobase() so that it checks the
sec_vectors[] array as well as the vectors[] array if needed.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-7-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static int nvic_pending_prio(NVICState *s)
 static bool nvic_rettobase(NVICState *s)
 {
     int irq, nhand = 0;
+    bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
 
     for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
-        if (s->vectors[irq].active) {
+        if (s->vectors[irq].active ||
+            (check_sec && irq < NVIC_INTERNAL_VECTORS &&
+             s->sec_vectors[irq].active)) {
             nhand++;
             if (nhand == 2) {
                 return 0;
-- 
2.7.4

For v8M, the NVIC has a new set of registers per interrupt,
NVIC_ITNS<n>. These determine whether the interrupt targets Secure
or Non-secure state. Implement the register read/write code for
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
accesses to fields corresponding to interrupts which are
configured to target secure state.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
---
 include/hw/intc/armv7m_nvic.h |  3 ++
 hw/intc/armv7m_nvic.c         | 74 +++++++++++++++++++++++++++++++++++++++----
 2 files changed, 70 insertions(+), 7 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
     /* The PRIGROUP field in AIRCR is banked */
     uint32_t prigroup[M_REG_NUM_BANKS];
 
+    /* v8M NVIC_ITNS state (stored as a bool per bit) */
+    bool itns[NVIC_MAX_VECTORS];
+
     /* The following fields are all cached state that can be recalculated
      * from the vectors[] and sec_vectors[] arrays and the prigroup field:
      *  - vectpending
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
     switch (offset) {
     case 4: /* Interrupt Control Type.  */
         return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
+    case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
+    {
+        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
+        int i;
+
+        if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+            goto bad_offset;
+        }
+        if (!attrs.secure) {
+            return 0;
+        }
+        val = 0;
+        for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
+            if (s->itns[startvec + i]) {
+                val |= (1 << i);
+            }
+        }
+        return val;
+    }
     case 0xd00: /* CPUID Base.  */
         return cpu->midr;
     case 0xd04: /* Interrupt Control State.  */
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
     ARMCPU *cpu = s->cpu;
 
     switch (offset) {
+    case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
+    {
+        int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
+        int i;
+
+        if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+            goto bad_offset;
+        }
+        if (!attrs.secure) {
+            break;
+        }
+        for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
+            s->itns[startvec + i] = (value >> i) & 1;
+        }
+        nvic_irq_update(s);
+        break;
+    }
     case 0xd04: /* Interrupt Control State.  */
         if (value & (1 << 31)) {
             armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
         startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
 
         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
-            if (s->vectors[startvec + i].enabled) {
+            if (s->vectors[startvec + i].enabled &&
+                (attrs.secure || s->itns[startvec + i])) {
                 val |= (1 << i);
             }
         }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
         val = 0;
         startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
-            if (s->vectors[startvec + i].pending) {
+            if (s->vectors[startvec + i].pending &&
+                (attrs.secure || s->itns[startvec + i])) {
                 val |= (1 << i);
             }
         }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
         startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
 
         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
-            if (s->vectors[startvec + i].active) {
+            if (s->vectors[startvec + i].active &&
+                (attrs.secure || s->itns[startvec + i])) {
                 val |= (1 << i);
             }
         }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
         startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
 
         for (i = 0; i < size && startvec + i < s->num_irq; i++) {
-            val |= s->vectors[startvec + i].prio << (8 * i);
+            if (attrs.secure || s->itns[startvec + i]) {
+                val |= s->vectors[startvec + i].prio << (8 * i);
+            }
         }
         break;
     case 0xd18 ... 0xd23: /* System Handler Priority.  */
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
         startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
 
         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
-            if (value & (1 << i)) {
+            if (value & (1 << i) &&
+                (attrs.secure || s->itns[startvec + i])) {
                 s->vectors[startvec + i].enabled = setval;
             }
         }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
         startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
 
         for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
-            if (value & (1 << i)) {
+            if (value & (1 << i) &&
+                (attrs.secure || s->itns[startvec + i])) {
                 s->vectors[startvec + i].pending = setval;
             }
         }
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
         startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
 
         for (i = 0; i < size && startvec + i < s->num_irq; i++) {
-            set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
+            if (attrs.secure || s->itns[startvec + i]) {
+                set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
+            }
         }
         nvic_irq_update(s);
         return MEMTX_OK;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
         VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
                              vmstate_VecInfo, VecInfo),
         VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
+        VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
     s->vectpending = 0;
     s->vectpending_is_s_banked = false;
     s->vectpending_prio = NVIC_NOEXC_PRIO;
+
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
+        memset(s->itns, 0, sizeof(s->itns));
+    } else {
+        /* This state is constant and not guest accessible in a non-security
+         * NVIC; we set the bits to true to avoid having to do a feature
+         * bit check in the NVIC enable/pend/etc register accessors.
+         */
+        int i;
+
+        for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {
+            s->itns[i] = true;
+        }
+    }
 }
 
 static void nvic_systick_trigger(void *opaque, int n, int level)
-- 
2.7.4

Update the nvic_recompute_state() code to handle the security
extension and its associated banked registers.

Code that uses the resulting cached state (ie the irq
acknowledge and complete code) will be updated in a later
commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++--
 hw/intc/trace-events  |   1 +
 2 files changed, 147 insertions(+), 5 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
  * (higher than the highest possible priority value)
  */
 #define NVIC_NOEXC_PRIO 0x100
+/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
+#define NVIC_NS_PRIO_LIMIT 0x80
 
 static const uint8_t nvic_id[] = {
     0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
     return false;
 }
 
+static bool exc_is_banked(int exc)
+{
+    /* Return true if this is one of the limited set of exceptions which
+     * are banked (and thus have state in sec_vectors[])
+     */
+    return exc == ARMV7M_EXCP_HARD ||
+        exc == ARMV7M_EXCP_MEM ||
+        exc == ARMV7M_EXCP_USAGE ||
+        exc == ARMV7M_EXCP_SVC ||
+        exc == ARMV7M_EXCP_PENDSV ||
+        exc == ARMV7M_EXCP_SYSTICK;
+}
+
 /* Return a mask word which clears the subpriority bits from
  * a priority value for an M-profile exception, leaving only
  * the group priority.
  */
-static inline uint32_t nvic_gprio_mask(NVICState *s)
+static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
+{
+    return ~0U << (s->prigroup[secure] + 1);
+}
+
+static bool exc_targets_secure(NVICState *s, int exc)
+{
+    /* Return true if this non-banked exception targets Secure state. */
+    if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
+        return false;
+    }
+
+    if (exc >= NVIC_FIRST_IRQ) {
+        return !s->itns[exc];
+    }
+
+    /* Function shouldn't be called for banked exceptions. */
+    assert(!exc_is_banked(exc));
+
+    switch (exc) {
+    case ARMV7M_EXCP_NMI:
+    case ARMV7M_EXCP_BUS:
+        return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
+    case ARMV7M_EXCP_SECURE:
+        return true;
+    case ARMV7M_EXCP_DEBUG:
+        /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
+        return false;
+    default:
+        /* reset, and reserved (unused) low exception numbers.
+         * We'll get called by code that loops through all the exception
+         * numbers, but it doesn't matter what we return here as these
+         * non-existent exceptions will never be pended or active.
+         */
+        return true;
+    }
+}
+
+static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
+{
+    /* Return the group priority for this exception, given its raw
+     * (group-and-subgroup) priority value and whether it is targeting
+     * secure state or not.
+     */
+    if (rawprio < 0) {
+        return rawprio;
+    }
+    rawprio &= nvic_gprio_mask(s, targets_secure);
+    /* AIRCR.PRIS causes us to squash all NS priorities into the
+     * lower half of the total range
+     */
+    if (!targets_secure &&
+        (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
+        rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
+    }
+    return rawprio;
+}
+
+/* Recompute vectpending and exception_prio for a CPU which implements
+ * the Security extension
+ */
+static void nvic_recompute_state_secure(NVICState *s)
 {
-    return ~0U << (s->prigroup[M_REG_NS] + 1);
+    int i, bank;
+    int pend_prio = NVIC_NOEXC_PRIO;
+    int active_prio = NVIC_NOEXC_PRIO;
+    int pend_irq = 0;
+    bool pending_is_s_banked = false;
+
+    /* R_CQRV: precedence is by:
+     *  - lowest group priority; if both the same then
+     *  - lowest subpriority; if both the same then
+     *  - lowest exception number; if both the same (ie banked) then
+     *  - secure exception takes precedence
+     * Compare pseudocode RawExecutionPriority.
+     * Annoyingly, now we have two prigroup values (for S and NS)
+     * we can't do the loop comparison on raw priority values.
+     */
+    for (i = 1; i < s->num_irq; i++) {
+        for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
+            VecInfo *vec;
+            int prio;
+            bool targets_secure;
+
+            if (bank == M_REG_S) {
+                if (!exc_is_banked(i)) {
+                    continue;
+                }
+                vec = &s->sec_vectors[i];
+                targets_secure = true;
+            } else {
+                vec = &s->vectors[i];
+                targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
+            }
+
+            prio = exc_group_prio(s, vec->prio, targets_secure);
+            if (vec->enabled && vec->pending && prio < pend_prio) {
+                pend_prio = prio;
+                pend_irq = i;
+                pending_is_s_banked = (bank == M_REG_S);
+            }
+            if (vec->active && prio < active_prio) {
+                active_prio = prio;
+            }
+        }
+    }
+
+    s->vectpending_is_s_banked = pending_is_s_banked;
+    s->vectpending = pend_irq;
+    s->vectpending_prio = pend_prio;
+    s->exception_prio = active_prio;
+
+    trace_nvic_recompute_state_secure(s->vectpending,
+                                      s->vectpending_is_s_banked,
+                                      s->vectpending_prio,
+                                      s->exception_prio);
 }
 
 /* Recompute vectpending and exception_prio */
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
     int active_prio = NVIC_NOEXC_PRIO;
     int pend_irq = 0;
 
+    /* In theory we could write one function that handled both
+     * the "security extension present" and "not present"; however
+     * the security related changes significantly complicate the
+     * recomputation just by themselves and mixing both cases together
+     * would be even worse, so we retain a separate non-secure-only
+     * version for CPUs which don't implement the security extension.
+     */
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
+        nvic_recompute_state_secure(s);
+        return;
+    }
+
     for (i = 1; i < s->num_irq; i++) {
         VecInfo *vec = &s->vectors[i];
 
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
     }
 
     if (active_prio > 0) {
-        active_prio &= nvic_gprio_mask(s);
+        active_prio &= nvic_gprio_mask(s, false);
     }
 
     if (pend_prio > 0) {
-        pend_prio &= nvic_gprio_mask(s);
+        pend_prio &= nvic_gprio_mask(s, false);
     }
 
     s->vectpending = pend_irq;
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
     } else if (env->v7m.primask[env->v7m.secure]) {
         running = 0;
     } else if (env->v7m.basepri[env->v7m.secure] > 0) {
-        running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
+        running = env->v7m.basepri[env->v7m.secure] &
+            nvic_gprio_mask(s, env->v7m.secure);
     } else {
         running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
     }
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
 
 # hw/intc/armv7m_nvic.c
 nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
+nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
 nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
 nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
 nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
-- 
2.7.4

Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()
functions take a bool indicating whether to pend the secure
or non-secure version of a banked interrupt, and update the
callsites accordingly.

In most callsites we can simply pass the correct security
state in; in a couple of cases we use TODO comments to indicate
that we will return the code in a subsequent commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-10-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h      | 14 ++++++++++-
 hw/intc/armv7m_nvic.c | 64 ++++++++++++++++++++++++++++++++++++++-------------
 target/arm/helper.c   | 24 +++++++++++--------
 hw/intc/trace-events  |  4 ++--
 4 files changed, 77 insertions(+), 29 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
     return true;
 }
 #endif
-void armv7m_nvic_set_pending(void *opaque, int irq);
+/**
+ * armv7m_nvic_set_pending: mark the specified exception as pending
+ * @opaque: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Marks the specified exception as pending. Note that we will assert()
+ * if @secure is true and @irq does not specify one of the fixed set
+ * of architecturally banked exceptions.
+ */
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
 void armv7m_nvic_acknowledge_irq(void *opaque);
 /**
  * armv7m_nvic_complete_irq: complete specified interrupt or exception
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
     qemu_set_irq(s->excpout, lvl);
 }
 
-static void armv7m_nvic_clear_pending(void *opaque, int irq)
+/**
+ * armv7m_nvic_clear_pending: mark the specified exception as not pending
+ * @opaque: the NVIC
+ * @irq: the exception number to mark as not pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Marks the specified exception as not pending. Note that we will assert()
+ * if @secure is true and @irq does not specify one of the fixed set
+ * of architecturally banked exceptions.
+ */
+static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
 {
     NVICState *s = (NVICState *)opaque;
     VecInfo *vec;
 
     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
 
-    vec = &s->vectors[irq];
-    trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
+    if (secure) {
+        assert(exc_is_banked(irq));
+        vec = &s->sec_vectors[irq];
+    } else {
+        vec = &s->vectors[irq];
+    }
+    trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
     if (vec->pending) {
         vec->pending = 0;
         nvic_irq_update(s);
     }
 }
 
-void armv7m_nvic_set_pending(void *opaque, int irq)
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
 {
     NVICState *s = (NVICState *)opaque;
+    bool banked = exc_is_banked(irq);
     VecInfo *vec;
 
     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
+    assert(!secure || banked);
 
-    vec = &s->vectors[irq];
-    trace_nvic_set_pending(irq, vec->enabled, vec->prio);
+    vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
 
+    trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);
 
     if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
         /* If a synchronous exception is pending then it may be
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq)
                           "(current priority %d)\n", irq, running);
             }
 
-            /* We can do the escalation, so we take HardFault instead */
+            /* We can do the escalation, so we take HardFault instead.
+             * If BFHFNMINS is set then we escalate to the banked HF for
+             * the target security state of the original exception; otherwise
+             * we take a Secure HardFault.
+             */
             irq = ARMV7M_EXCP_HARD;
-            vec = &s->vectors[irq];
+            if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
+                (secure ||
+                 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
+                vec = &s->sec_vectors[irq];
+            } else {
+                vec = &s->vectors[irq];
+            }
+            /* HF may be banked but there is only one shared HFSR */
             s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
         }
     }
@@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level)
     if (level != vec->level) {
         vec->level = level;
         if (level) {
-            armv7m_nvic_set_pending(s, n);
+            armv7m_nvic_set_pending(s, n, false);
         }
     }
 }
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
     }
     case 0xd04: /* Interrupt Control State.  */
         if (value & (1 << 31)) {
-            armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
+            armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
         }
         if (value & (1 << 28)) {
-            armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
+            armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
         } else if (value & (1 << 27)) {
-            armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
+            armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
         }
         if (value & (1 << 26)) {
-            armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
+            armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
         } else if (value & (1 << 25)) {
-            armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
+            armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
         }
         break;
     case 0xd08: /* Vector Table Offset.  */
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
     {
         int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
         if (excnum < s->num_irq) {
-            armv7m_nvic_set_pending(s, excnum);
+            armv7m_nvic_set_pending(s, excnum, false);
         }
         break;
     }
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
         /* SysTick just asked us to pend its exception.
          * (This is different from an external interrupt line's
          * behaviour.)
+         * TODO: when we implement the banked systicks we must make
+         * this pend the correct banked exception.
          */
-        armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
+        armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);
     }
 }
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
          * stack, directly take a usage fault on the current stack.
          */
         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
         v7m_exception_taken(cpu, excret);
         qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
                       "stackframe: failed exception return integrity check\n");
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
      * exception return excret specified then this is a UsageFault.
      */
     if (return_to_handler != arm_v7m_is_handler_mode(env)) {
-        /* Take an INVPC UsageFault by pushing the stack again. */
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+        /* Take an INVPC UsageFault by pushing the stack again.
+         * TODO: the v8M version of this code should target the
+         * background state for this exception.
+         */
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);
         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
         v7m_push_stack(cpu);
         v7m_exception_taken(cpu, excret);
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
        handle it.  */
     switch (cs->exception_index) {
     case EXCP_UDEF:
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
         break;
     case EXCP_NOCP:
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
         break;
     case EXCP_INVSTATE:
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
         break;
     case EXCP_SWI:
         /* The PC already points to the next instruction.  */
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
         break;
     case EXCP_PREFETCH_ABORT:
     case EXCP_DATA_ABORT:
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
                               env->v7m.bfar);
                 break;
             }
-            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
             break;
         default:
             /* All other FSR values are either MPU faults or "can't happen
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
                               env->v7m.mmfar[env->v7m.secure]);
                 break;
             }
-            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,
+                                    env->v7m.secure);
             break;
         }
         break;
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
                 return;
             }
         }
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
         break;
     case EXCP_IRQ:
         break;
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
 nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
 nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
 nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
-nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)"
-nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)"
+nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
+nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
 nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
 nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
 nvic_complete_irq(int irq) "NVIC complete IRQ %d"
-- 
2.7.4

Make the set_prio() function take a bool indicating
whether to pend the secure or non-secure version of a banked
interrupt, and use this to implement the correct banking
semantics for the SHPR registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-----
 hw/intc/trace-events  |  2 +-
 2 files changed, 88 insertions(+), 10 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_raw_execution_priority(void *opaque)
     return s->exception_prio;
 }
 
-/* caller must call nvic_irq_update() after this */
-static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
+/* caller must call nvic_irq_update() after this.
+ * secure indicates the bank to use for banked exceptions (we assert if
+ * we are passed secure=true for a non-banked exception).
+ */
+static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
 {
     assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
     assert(irq < s->num_irq);
 
-    s->vectors[irq].prio = prio;
+    if (secure) {
+        assert(exc_is_banked(irq));
+        s->sec_vectors[irq].prio = prio;
+    } else {
+        s->vectors[irq].prio = prio;
+    }
+
+    trace_nvic_set_prio(irq, secure, prio);
+}
+
+/* Return the current raw priority register value.
+ * secure indicates the bank to use for banked exceptions (we assert if
+ * we are passed secure=true for a non-banked exception).
+ */
+static int get_prio(NVICState *s, unsigned irq, bool secure)
+{
+    assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
+    assert(irq < s->num_irq);
 
-    trace_nvic_set_prio(irq, prio);
+    if (secure) {
+        assert(exc_is_banked(irq));
+        return s->sec_vectors[irq].prio;
+    } else {
+        return s->vectors[irq].prio;
+    }
 }
 
 /* Recompute state and assert irq line accordingly.
@@ -XXX,XX +XXX,XX @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
     }
 }
 
+static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
+{
+    /* Behaviour for the SHPR register field for this exception:
+     * return M_REG_NS to use the nonsecure vector (including for
+     * non-banked exceptions), M_REG_S for the secure version of
+     * a banked exception, and -1 if this field should RAZ/WI.
+     */
+    switch (exc) {
+    case ARMV7M_EXCP_MEM:
+    case ARMV7M_EXCP_USAGE:
+    case ARMV7M_EXCP_SVC:
+    case ARMV7M_EXCP_PENDSV:
+    case ARMV7M_EXCP_SYSTICK:
+        /* Banked exceptions */
+        return attrs.secure;
+    case ARMV7M_EXCP_BUS:
+        /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
+        if (!attrs.secure &&
+            !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
+            return -1;
+        }
+        return M_REG_NS;
+    case ARMV7M_EXCP_SECURE:
+        /* Not banked, RAZ/WI from nonsecure */
+        if (!attrs.secure) {
+            return -1;
+        }
+        return M_REG_NS;
+    case ARMV7M_EXCP_DEBUG:
+        /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
+        return M_REG_NS;
+    case 8 ... 10:
+    case 13:
+        /* RES0 */
+        return -1;
+    default:
+        /* Not reachable due to decode of SHPR register addresses */
+        g_assert_not_reached();
+    }
+}
+
 static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
                                     uint64_t *data, unsigned size,
                                     MemTxAttrs attrs)
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
             }
         }
         break;
-    case 0xd18 ... 0xd23: /* System Handler Priority.  */
+    case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
         val = 0;
         for (i = 0; i < size; i++) {
-            val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
+            unsigned hdlidx = (offset - 0xd14) + i;
+            int sbank = shpr_bank(s, hdlidx, attrs);
+
+            if (sbank < 0) {
+                continue;
+            }
+            val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
         }
         break;
     case 0xfe0 ... 0xfff: /* ID.  */
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
 
         for (i = 0; i < size && startvec + i < s->num_irq; i++) {
             if (attrs.secure || s->itns[startvec + i]) {
-                set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
+                set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
             }
         }
         nvic_irq_update(s);
         return MEMTX_OK;
-    case 0xd18 ... 0xd23: /* System Handler Priority.  */
+    case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
         for (i = 0; i < size; i++) {
             unsigned hdlidx = (offset - 0xd14) + i;
-            set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
+            int newprio = extract32(value, i * 8, 8);
+            int sbank = shpr_bank(s, hdlidx, attrs);
+
+            if (sbank < 0) {
+                continue;
+            }
+            set_prio(s, hdlidx, sbank, newprio);
         }
         nvic_irq_update(s);
         return MEMTX_OK;
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
 # hw/intc/armv7m_nvic.c
 nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
 nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
-nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
+nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
 nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
 nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
 nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
-- 
2.7.4

In armv7m_nvic_set_pending() we have to compare the
priority of an exception against the execution priority
to decide whether it needs to be escalated to HardFault.
In the specification this is a comparison against the
exception's group priority; for v7M we implemented it
as a comparison against the raw exception priority
because the two comparisons will always give the
same answer. For v8M the existence of AIRCR.PRIS and
the possibility of different PRIGROUP values for secure
and nonsecure exceptions means we need to explicitly
calculate the vector's group priority for this check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-12-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
         int running = nvic_exec_prio(s);
         bool escalate = false;
 
-        if (vec->prio >= running) {
+        if (exc_group_prio(s, vec->prio, secure) >= running) {
             trace_nvic_escalate_prio(irq, vec->prio, running);
             escalate = true;
         } else if (!vec->enabled) {
-- 
2.7.4

When escalating to HardFault, we must go into Lockup if we
can't take the synchronous HardFault because the current
execution priority is already at or below the priority of
HardFault. In v7M HF is always priority -1 so a simple < 0
comparison sufficed; in v8M the priority of HardFault can
vary depending on whether it is a Secure or NonSecure
HardFault, so we must check against the priority of the
HardFault exception vector we're about to use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-13-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
         }
 
         if (escalate) {
-            if (running < 0) {
-                /* We want to escalate to HardFault but we can't take a
-                 * synchronous HardFault at this point either. This is a
-                 * Lockup condition due to a guest bug. We don't model
-                 * Lockup, so report via cpu_abort() instead.
-                 */
-                cpu_abort(&s->cpu->parent_obj,
-                          "Lockup: can't escalate %d to HardFault "
-                          "(current priority %d)\n", irq, running);
-            }
 
-            /* We can do the escalation, so we take HardFault instead.
+            /* We need to escalate this exception to a synchronous HardFault.
              * If BFHFNMINS is set then we escalate to the banked HF for
              * the target security state of the original exception; otherwise
              * we take a Secure HardFault.
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
             } else {
                 vec = &s->vectors[irq];
             }
+            if (running <= vec->prio) {
+                /* We want to escalate to HardFault but we can't take the
+                 * synchronous HardFault at this point either. This is a
+                 * Lockup condition due to a guest bug. We don't model
+                 * Lockup, so report via cpu_abort() instead.
+                 */
+                cpu_abort(&s->cpu->parent_obj,
+                          "Lockup: can't escalate %d to HardFault "
+                          "(current priority %d)\n", irq, running);
+            }
+
             /* HF may be banked but there is only one shared HFSR */
             s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
         }
-- 
2.7.4

In v7M, the fixed-priority exceptions are:
 Reset: -3
 NMI: -2
 HardFault: -1

In v8M, this changes because Secure HardFault may need
to be prioritised above NMI:
 Reset: -4
 Secure HardFault if AIRCR.BFHFNMINS == 1: -3
 NMI: -2
 Secure HardFault if AIRCR.BFHFNMINS == 0: -1
 NonSecure HardFault: -1

Make these changes, including support for changing the
priority of Secure HardFault as AIRCR.BFHFNMINS changes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-14-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
                     (R_V7M_AIRCR_SYSRESETREQS_MASK |
                      R_V7M_AIRCR_BFHFNMINS_MASK |
                      R_V7M_AIRCR_PRIS_MASK);
+                /* BFHFNMINS changes the priority of Secure HardFault */
+                if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
+                    s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
+                } else {
+                    s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+                }
             }
             nvic_irq_update(s);
         }
@@ -XXX,XX +XXX,XX @@ static int nvic_post_load(void *opaque, int version_id)
 {
     NVICState *s = opaque;
     unsigned i;
+    int resetprio;
 
     /* Check for out of range priority settings */
-    if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
+    resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
+
+    if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
         s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
         s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
         return 1;
@@ -XXX,XX +XXX,XX @@ static int nvic_security_post_load(void *opaque, int version_id)
     int i;
 
     /* Check for out of range priority settings */
-    if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
+    if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
+        && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
+        /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
+         * if the CPU state has been migrated yet; a mismatch won't
+         * cause the emulation to blow up, though.
+         */
         return 1;
     }
     for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
@@ -XXX,XX +XXX,XX @@ static Property props_nvic[] = {
 
 static void armv7m_nvic_reset(DeviceState *dev)
 {
+    int resetprio;
     NVICState *s = NVIC(dev);
 
     s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
     s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
     s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
 
-    s->vectors[ARMV7M_EXCP_RESET].prio = -3;
+    resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
+    s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
     s->vectors[ARMV7M_EXCP_NMI].prio = -2;
     s->vectors[ARMV7M_EXCP_HARD].prio = -1;
 
-- 
2.7.4

If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
preempt execution. The simple way to achieve this is to clear the
enable bit for it, since the enable bit isn't guest visible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
                     (R_V7M_AIRCR_SYSRESETREQS_MASK |
                      R_V7M_AIRCR_BFHFNMINS_MASK |
                      R_V7M_AIRCR_PRIS_MASK);
-                /* BFHFNMINS changes the priority of Secure HardFault */
+                /* BFHFNMINS changes the priority of Secure HardFault, and
+                 * allows a pending Non-secure HardFault to preempt (which
+                 * we implement by marking it enabled).
+                 */
                 if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
                     s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
+                    s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
                 } else {
                     s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+                    s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
                 }
             }
             nvic_irq_update(s);
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
     NVICState *s = NVIC(dev);
 
     s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
-    s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
     /* MEM, BUS, and USAGE are enabled through
      * the System Handler Control register
      */
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
 
         /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
         s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+        /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
+        s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
+    } else {
+        s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
     }
 
     /* Strictly speaking the reset handler should be enabled.
-- 
2.7.4

Update nvic_exec_prio() to support the v8M changes:
 * BASEPRI, FAULTMASK and PRIMASK are all banked
 * AIRCR.PRIS can affect NS priorities
 * AIRCR.BFHFNMINS affects FAULTMASK behaviour

These changes mean that it's no longer possible to
definitely say that if FAULTMASK is set it overrides
PRIMASK, and if PRIMASK is set it overrides BASEPRI
(since if PRIMASK_NS is set and AIRCR.PRIS is set then
whether that 0x80 priority should take effect or the
priority in BASEPRI_S depends on the value of BASEPRI_S,
for instance). So we switch to the same approach used
by the pseudocode of working through BASEPRI, PRIMASK
and FAULTMASK and overriding the previous values if
needed.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-16-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 51 ++++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 42 insertions(+), 9 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
 static inline int nvic_exec_prio(NVICState *s)
 {
     CPUARMState *env = &s->cpu->env;
-    int running;
+    int running = NVIC_NOEXC_PRIO;
 
-    if (env->v7m.faultmask[env->v7m.secure]) {
-        running = -1;
-    } else if (env->v7m.primask[env->v7m.secure]) {
+    if (env->v7m.basepri[M_REG_NS] > 0) {
+        running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
+    }
+
+    if (env->v7m.basepri[M_REG_S] > 0) {
+        int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
+        if (running > basepri) {
+            running = basepri;
+        }
+    }
+
+    if (env->v7m.primask[M_REG_NS]) {
+        if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
+            if (running > NVIC_NS_PRIO_LIMIT) {
+                running = NVIC_NS_PRIO_LIMIT;
+            }
+        } else {
+            running = 0;
+        }
+    }
+
+    if (env->v7m.primask[M_REG_S]) {
         running = 0;
-    } else if (env->v7m.basepri[env->v7m.secure] > 0) {
-        running = env->v7m.basepri[env->v7m.secure] &
-            nvic_gprio_mask(s, env->v7m.secure);
-    } else {
-        running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
     }
+
+    if (env->v7m.faultmask[M_REG_NS]) {
+        if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
+            running = -1;
+        } else {
+            if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
+                if (running > NVIC_NS_PRIO_LIMIT) {
+                    running = NVIC_NS_PRIO_LIMIT;
+                }
+            } else {
+                running = 0;
+            }
+        }
+    }
+
+    if (env->v7m.faultmask[M_REG_S]) {
+        running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
+    }
+
     /* consider priority of active handler */
     return MIN(running, s->exception_prio);
 }
-- 
2.7.4

Now that we have a banked FAULTMASK register and banked exceptions,
we can implement the correct check in cpu_mmu_index() for whether
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
handlers which have requested a negative execution priority to run
with the MPU disabled. In v8M the test has to check this for the
current security state and so takes account of banking.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h      | 21 ++++++++++++++++-----
 hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq);
  * (v8M ARM ARM I_PKLD.)
  */
 int armv7m_nvic_raw_execution_priority(void *opaque);
+/**
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
+ * priority is negative for the specified security state.
+ * @opaque: the NVIC
+ * @secure: the security state to test
+ * This corresponds to the pseudocode IsReqExecPriNeg().
+ */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
+#else
+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+{
+    return false;
+}
+#endif
 
 /* Interface for defining coprocessor registers.
  * Registers are defined in tables of arm_cp_reginfo structs
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
     if (arm_feature(env, ARM_FEATURE_M)) {
         ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
 
-        /* Execution priority is negative if FAULTMASK is set or
-         * we're in a HardFault or NMI handler.
-         */
-        if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
-            || env->v7m.faultmask[env->v7m.secure]) {
+        if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
             mmu_idx = ARMMMUIdx_MNegPri;
         }
 
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
     return MIN(running, s->exception_prio);
 }
 
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+{
+    /* Return true if the requested execution priority is negative
+     * for the specified security state, ie that security state
+     * has an active NMI or HardFault or has set its FAULTMASK.
+     * Note that this is not the same as whether the execution
+     * priority is actually negative (for instance AIRCR.PRIS may
+     * mean we don't allow FAULTMASK_NS to actually make the execution
+     * priority negative). Compare pseudocode IsReqExcPriNeg().
+     */
+    NVICState *s = opaque;
+
+    if (s->cpu->env.v7m.faultmask[secure]) {
+        return true;
+    }
+
+    if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
+        s->vectors[ARMV7M_EXCP_HARD].active) {
+        return true;
+    }
+
+    if (s->vectors[ARMV7M_EXCP_NMI].active &&
+        exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
+        return true;
+    }
+
+    return false;
+}
+
 bool armv7m_nvic_can_take_pending_exception(void *opaque)
 {
     NVICState *s = opaque;
-- 
2.7.4

The ICSR NVIC register is banked for v8M. This doesn't
require any new state, but it does mean that some bits
are controlled by BFHNFNMINS and some bits must work
with the correct banked exception. There is also a new
in v8M PENDNMICLR bit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-18-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 45 ++++++++++++++++++++++++++++++++-------------
 1 file changed, 32 insertions(+), 13 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
     }
     case 0xd00: /* CPUID Base.  */
         return cpu->midr;
-    case 0xd04: /* Interrupt Control State.  */
+    case 0xd04: /* Interrupt Control State (ICSR) */
         /* VECTACTIVE */
         val = cpu->env.v7m.exception;
         /* VECTPENDING */
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         if (nvic_rettobase(s)) {
             val |= (1 << 11);
         }
-        /* PENDSTSET */
-        if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
-            val |= (1 << 26);
-        }
-        /* PENDSVSET */
-        if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
-            val |= (1 << 28);
+        if (attrs.secure) {
+            /* PENDSTSET */
+            if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {
+                val |= (1 << 26);
+            }
+            /* PENDSVSET */
+            if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {
+                val |= (1 << 28);
+            }
+        } else {
+            /* PENDSTSET */
+            if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
+                val |= (1 << 26);
+            }
+            /* PENDSVSET */
+            if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
+                val |= (1 << 28);
+            }
         }
         /* NMIPENDSET */
-        if (s->vectors[ARMV7M_EXCP_NMI].pending) {
+        if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
+            s->vectors[ARMV7M_EXCP_NMI].pending) {
             val |= (1 << 31);
         }
-        /* ISRPREEMPT not implemented */
+        /* ISRPREEMPT: RES0 when halting debug not implemented */
+        /* STTNS: RES0 for the Main Extension */
         return val;
     case 0xd08: /* Vector Table Offset.  */
         return cpu->env.v7m.vecbase[attrs.secure];
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
         nvic_irq_update(s);
         break;
     }
-    case 0xd04: /* Interrupt Control State.  */
-        if (value & (1 << 31)) {
-            armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
+    case 0xd04: /* Interrupt Control State (ICSR) */
+        if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
+            if (value & (1 << 31)) {
+                armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
+            } else if (value & (1 << 30) &&
+                       arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+                /* PENDNMICLR didn't exist in v7M */
+                armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false);
+            }
         }
         if (value & (1 << 28)) {
             armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
-- 
2.7.4

Handle banking of SHCSR: some register bits are banked between
Secure and Non-Secure, and some are only accessible to Secure.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-19-git-send-email-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 221 ++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 169 insertions(+), 52 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         val = cpu->env.v7m.ccr[attrs.secure];
         val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
         return val;
-    case 0xd24: /* System Handler Status.  */
+    case 0xd24: /* System Handler Control and State (SHCSR) */
         val = 0;
-        if (s->vectors[ARMV7M_EXCP_MEM].active) {
-            val |= (1 << 0);
-        }
-        if (s->vectors[ARMV7M_EXCP_BUS].active) {
-            val |= (1 << 1);
-        }
-        if (s->vectors[ARMV7M_EXCP_USAGE].active) {
-            val |= (1 << 3);
+        if (attrs.secure) {
+            if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
+                val |= (1 << 0);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {
+                val |= (1 << 2);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {
+                val |= (1 << 3);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {
+                val |= (1 << 7);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {
+                val |= (1 << 10);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {
+                val |= (1 << 11);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {
+                val |= (1 << 12);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {
+                val |= (1 << 13);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {
+                val |= (1 << 15);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {
+                val |= (1 << 16);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {
+                val |= (1 << 18);
+            }
+            if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {
+                val |= (1 << 21);
+            }
+            /* SecureFault is not banked but is always RAZ/WI to NS */
+            if (s->vectors[ARMV7M_EXCP_SECURE].active) {
+                val |= (1 << 4);
+            }
+            if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {
+                val |= (1 << 19);
+            }
+            if (s->vectors[ARMV7M_EXCP_SECURE].pending) {
+                val |= (1 << 20);
+            }
+        } else {
+            if (s->vectors[ARMV7M_EXCP_MEM].active) {
+                val |= (1 << 0);
+            }
+            if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+                /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
+                if (s->vectors[ARMV7M_EXCP_HARD].active) {
+                    val |= (1 << 2);
+                }
+                if (s->vectors[ARMV7M_EXCP_HARD].pending) {
+                    val |= (1 << 21);
+                }
+            }
+            if (s->vectors[ARMV7M_EXCP_USAGE].active) {
+                val |= (1 << 3);
+            }
+            if (s->vectors[ARMV7M_EXCP_SVC].active) {
+                val |= (1 << 7);
+            }
+            if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
+                val |= (1 << 10);
+            }
+            if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
+                val |= (1 << 11);
+            }
+            if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
+                val |= (1 << 12);
+            }
+            if (s->vectors[ARMV7M_EXCP_MEM].pending) {
+                val |= (1 << 13);
+            }
+            if (s->vectors[ARMV7M_EXCP_SVC].pending) {
+                val |= (1 << 15);
+            }
+            if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
+                val |= (1 << 16);
+            }
+            if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
+                val |= (1 << 18);
+            }
         }
-        if (s->vectors[ARMV7M_EXCP_SVC].active) {
-            val |= (1 << 7);
+        if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
+            if (s->vectors[ARMV7M_EXCP_BUS].active) {
+                val |= (1 << 1);
+            }
+            if (s->vectors[ARMV7M_EXCP_BUS].pending) {
+                val |= (1 << 14);
+            }
+            if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
+                val |= (1 << 17);
+            }
+            if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
+                s->vectors[ARMV7M_EXCP_NMI].active) {
+                /* NMIACT is not present in v7M */
+                val |= (1 << 5);
+            }
         }
+
+        /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
         if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
             val |= (1 << 8);
         }
-        if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
-            val |= (1 << 10);
-        }
-        if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
-            val |= (1 << 11);
-        }
-        if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
-            val |= (1 << 12);
-        }
-        if (s->vectors[ARMV7M_EXCP_MEM].pending) {
-            val |= (1 << 13);
-        }
-        if (s->vectors[ARMV7M_EXCP_BUS].pending) {
-            val |= (1 << 14);
-        }
-        if (s->vectors[ARMV7M_EXCP_SVC].pending) {
-            val |= (1 << 15);
-        }
-        if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
-            val |= (1 << 16);
-        }
-        if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
-            val |= (1 << 17);
-        }
-        if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
-            val |= (1 << 18);
-        }
         return val;
     case 0xd28: /* Configurable Fault Status.  */
         /* The BFSR bits [15:8] are shared between security states
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
 
         cpu->env.v7m.ccr[attrs.secure] = value;
         break;
-    case 0xd24: /* System Handler Control.  */
-        s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
-        s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
-        s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
-        s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
+    case 0xd24: /* System Handler Control and State (SHCSR) */
+        if (attrs.secure) {
+            s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
+            /* Secure HardFault active bit cannot be written */
+            s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_PENDSV].active =
+                (value & (1 << 10)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =
+                (value & (1 << 11)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_USAGE].pending =
+                (value & (1 << 12)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
+            s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
+                (value & (1 << 18)) != 0;
+            /* SecureFault not banked, but RAZ/WI to NS */
+            s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
+            s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
+            s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;
+        } else {
+            s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
+            if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+                /* HARDFAULTPENDED is not present in v7M */
+                s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
+            }
+            s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
+            s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
+            s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
+            s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
+            s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
+            s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
+            s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
+            s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
+            s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
+        }
+        if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
+            s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
+            s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
+            s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
+        }
+        /* NMIACT can only be written if the write is of a zero, with
+         * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
+         */
+        if (!attrs.secure && cpu->env.v7m.secure &&
+            (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
+            (value & (1 << 5)) == 0) {
+            s->vectors[ARMV7M_EXCP_NMI].active = 0;
+        }
+        /* HARDFAULTACT can only be written if the write is of a zero
+         * to the non-secure HardFault state by the CPU in secure state.
+         * The only case where we can be targeting the non-secure HF state
+         * when in secure state is if this is a write via the NS alias
+         * and BFHFNMINS is 1.
+         */
+        if (!attrs.secure && cpu->env.v7m.secure &&
+            (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
+            (value & (1 << 2)) == 0) {
+            s->vectors[ARMV7M_EXCP_HARD].active = 0;
+        }
+
+        /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
         s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
-        s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
-        s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
-        s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
-        s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
-        s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
-        s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
-        s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
-        s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
-        s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
         nvic_irq_update(s);
         break;
     case 0xd28: /* Configurable Fault Status.  */
-- 
2.7.4

Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq()
to handle banked exceptions:
 * acknowledge needs to use the correct vector, which may be
   in sec_vectors[]
 * acknowledge needs to return to its caller whether the
   exception should be taken to secure or non-secure state
 * complete needs its caller to tell it whether the exception
   being completed is a secure one or not

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h      | 15 +++++++++++++--
 hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++++------
 target/arm/helper.c   |  8 +++++---
 hw/intc/trace-events  |  4 ++--
 4 files changed, 40 insertions(+), 13 deletions(-)

In the A64 decoder, we have a lot of references to section numbers
from version A.a of the v8A ARM ARM (DDI0487). This version of the
document is now long obsolete (we are currently on revision B.a),
and various intervening versions renumbered all the sections.

The most recent B.a version of the document doesn't assign
section numbers at all to the individual instruction classes
in the way that the various A.x versions did. The simplest thing
to do is just to delete all the out of date C.x.x references.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20170915150849.23557-1-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 227 +++++++++++++++++++++++----------------------
 1 file changed, 114 insertions(+), 113 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
 }
 
 /*
- * the instruction disassembly implemented here matches
- * the instruction encoding classifications in chapter 3 (C3)
- * of the ARM Architecture Reference Manual (DDI0487A_a)
+ * The instruction disassembly implemented here matches
+ * the instruction encoding classifications in chapter C4
+ * of the ARM Architecture Reference Manual (DDI0487B_a);
+ * classification names and decode diagrams here should generally
+ * match up with those in the manual.
  */
 
-/* C3.2.7 Unconditional branch (immediate)
+/* Unconditional branch (immediate)
  *   31  30       26 25                                  0
  * +----+-----------+-------------------------------------+
  * | op | 0 0 1 0 1 |                 imm26               |
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
     uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
 
     if (insn & (1U << 31)) {
-        /* C5.6.26 BL Branch with link */
+        /* BL Branch with link */
         tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
     }
 
-    /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
+    /* B Branch / BL Branch with link */
     gen_goto_tb(s, 0, addr);
 }
 
-/* C3.2.1 Compare & branch (immediate)
+/* Compare and branch (immediate)
  *   31  30         25  24  23                  5 4      0
  * +----+-------------+----+---------------------+--------+
  * | sf | 0 1 1 0 1 0 | op |         imm19       |   Rt   |
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
     gen_goto_tb(s, 1, addr);
 }
 
-/* C3.2.5 Test & branch (immediate)
+/* Test and branch (immediate)
  *   31  30         25  24  23   19 18          5 4    0
  * +----+-------------+----+-------+-------------+------+
  * | b5 | 0 1 1 0 1 1 | op |  b40  |    imm14    |  Rt  |
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
     gen_goto_tb(s, 1, addr);
 }
 
-/* C3.2.2 / C5.6.19 Conditional branch (immediate)
+/* Conditional branch (immediate)
  *  31           25  24  23                  5   4  3    0
  * +---------------+----+---------------------+----+------+
  * | 0 1 0 1 0 1 0 | o1 |         imm19       | o0 | cond |
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C5.6.68 HINT */
+/* HINT instruction group, including various allocated HINTs */
 static void handle_hint(DisasContext *s, uint32_t insn,
                         unsigned int op1, unsigned int op2, unsigned int crm)
 {
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
     }
 }
 
-/* C5.6.130 MSR (immediate) - move immediate to processor state field */
+/* MSR (immediate) - move immediate to processor state field */
 static void handle_msr_i(DisasContext *s, uint32_t insn,
                          unsigned int op1, unsigned int op2, unsigned int crm)
 {
@@ -XXX,XX +XXX,XX @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
     tcg_temp_free_i32(nzcv);
 }
 
-/* C5.6.129 MRS - move from system register
- * C5.6.131 MSR (register) - move to system register
- * C5.6.204 SYS
- * C5.6.205 SYSL
+/* MRS - move from system register
+ * MSR (register) - move to system register
+ * SYS
+ * SYSL
  * These are all essentially the same insn in 'read' and 'write'
  * versions, with varying op0 fields.
  */
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
     }
 }
 
-/* C3.2.4 System
+/* System
  *  31                 22 21  20 19 18 16 15   12 11    8 7   5 4    0
  * +---------------------+---+-----+-----+-------+-------+-----+------+
  * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 |  CRn  |  CRm  | op2 |  Rt  |
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
             return;
         }
         switch (crn) {
-        case 2: /* C5.6.68 HINT */
+        case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
             handle_hint(s, insn, op1, op2, crm);
             break;
         case 3: /* CLREX, DSB, DMB, ISB */
             handle_sync(s, insn, op1, op2, crm);
             break;
-        case 4: /* C5.6.130 MSR (immediate) */
+        case 4: /* MSR (immediate) */
             handle_msr_i(s, insn, op1, op2, crm);
             break;
         default:
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
     handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
 }
 
-/* C3.2.3 Exception generation
+/* Exception generation
  *
  *  31             24 23 21 20                     5 4   2 1  0
  * +-----------------+-----+------------------------+-----+----+
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.2.7 Unconditional branch (register)
+/* Unconditional branch (register)
  *  31           25 24   21 20   16 15   10 9    5 4     0
  * +---------------+-------+-------+-------+------+-------+
  * | 1 1 0 1 0 1 1 |  opc  |  op2  |  op3  |  Rn  |  op4  |
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
     s->base.is_jmp = DISAS_JUMP;
 }
 
-/* C3.2 Branches, exception generating and system instructions */
+/* Branches, exception generating and system instructions */
 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
 {
     switch (extract32(insn, 25, 7)) {
@@ -XXX,XX +XXX,XX @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
     return regsize == 64;
 }
 
-/* C3.3.6 Load/store exclusive
+/* Load/store exclusive
  *
  *  31 30 29         24  23  22   21  20  16  15  14   10 9    5 4    0
  * +-----+-------------+----+---+----+------+----+-------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
 }
 
 /*
- * C3.3.5 Load register (literal)
+ * Load register (literal)
  *
  *  31 30 29   27  26 25 24 23                5 4     0
  * +-----+-------+---+-----+-------------------+-------+
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
 }
 
 /*
- * C5.6.80 LDNP (Load Pair - non-temporal hint)
- * C5.6.81 LDP (Load Pair - non vector)
- * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
- * C5.6.176 STNP (Store Pair - non-temporal hint)
- * C5.6.177 STP (Store Pair - non vector)
- * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
- * C6.3.165 LDP (Load Pair of SIMD&FP)
- * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
- * C6.3.284 STP (Store Pair of SIMD&FP)
+ * LDNP (Load Pair - non-temporal hint)
+ * LDP (Load Pair - non vector)
+ * LDPSW (Load Pair Signed Word - non vector)
+ * STNP (Store Pair - non-temporal hint)
+ * STP (Store Pair - non vector)
+ * LDNP (Load Pair of SIMD&FP - non-temporal hint)
+ * LDP (Load Pair of SIMD&FP)
+ * STNP (Store Pair of SIMD&FP - non-temporal hint)
+ * STP (Store Pair of SIMD&FP)
  *
  *  31 30 29   27  26  25 24   23  22 21   15 14   10 9    5 4    0
  * +-----+-------+---+---+-------+---+-----------------------------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
 }
 
 /*
- * C3.3.8 Load/store (immediate post-indexed)
- * C3.3.9 Load/store (immediate pre-indexed)
- * C3.3.12 Load/store (unscaled immediate)
+ * Load/store (immediate post-indexed)
+ * Load/store (immediate pre-indexed)
+ * Load/store (unscaled immediate)
  *
  * 31 30 29   27  26 25 24 23 22 21  20    12 11 10 9    5 4    0
  * +----+-------+---+-----+-----+---+--------+-----+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
 }
 
 /*
- * C3.3.10 Load/store (register offset)
+ * Load/store (register offset)
  *
  * 31 30 29   27  26 25 24 23 22 21  20  16 15 13 12 11 10 9  5 4  0
  * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
 }
 
 /*
- * C3.3.13 Load/store (unsigned immediate)
+ * Load/store (unsigned immediate)
  *
  * 31 30 29   27  26 25 24 23 22 21        10 9     5
  * +----+-------+---+-----+-----+------------+-------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.3.1 AdvSIMD load/store multiple structures
+/* AdvSIMD load/store multiple structures
  *
  *  31  30  29           23 22  21         16 15    12 11  10 9    5 4    0
  * +---+---+---------------+---+-------------+--------+------+------+------+
  * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size |  Rn  |  Rt  |
  * +---+---+---------------+---+-------------+--------+------+------+------+
  *
- * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
+ * AdvSIMD load/store multiple structures (post-indexed)
  *
  *  31  30  29           23 22  21  20     16 15    12 11  10 9    5 4    0
  * +---+---+---------------+---+---+---------+--------+------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_addr);
 }
 
-/* C3.3.3 AdvSIMD load/store single structure
+/* AdvSIMD load/store single structure
  *
  *  31  30  29           23 22 21 20       16 15 13 12  11  10 9    5 4    0
  * +---+---+---------------+-----+-----------+-----+---+------+------+------+
  * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size |  Rn  |  Rt  |
  * +---+---+---------------+-----+-----------+-----+---+------+------+------+
  *
- * C3.3.4 AdvSIMD load/store single structure (post-indexed)
+ * AdvSIMD load/store single structure (post-indexed)
  *
  *  31  30  29           23 22 21 20       16 15 13 12  11  10 9    5 4    0
  * +---+---+---------------+-----+-----------+-----+---+------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_addr);
 }
 
-/* C3.3 Loads and stores */
+/* Loads and stores */
 static void disas_ldst(DisasContext *s, uint32_t insn)
 {
     switch (extract32(insn, 24, 6)) {
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.4.6 PC-rel. addressing
+/* PC-rel. addressing
  *   31  30   29 28       24 23                5 4    0
  * +----+-------+-----------+-------------------+------+
  * | op | immlo | 1 0 0 0 0 |       immhi       |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
 }
 
 /*
- * C3.4.1 Add/subtract (immediate)
+ * Add/subtract (immediate)
  *
  *  31 30 29 28       24 23 22 21         10 9   5 4   0
  * +--+--+--+-----------+-----+-------------+-----+-----+
@@ -XXX,XX +XXX,XX @@ static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
     return true;
 }
 
-/* C3.4.4 Logical (immediate)
+/* Logical (immediate)
  *   31  30 29 28         23 22  21  16 15  10 9    5 4    0
  * +----+-----+-------------+---+------+------+------+------+
  * | sf | opc | 1 0 0 1 0 0 | N | immr | imms |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_logic_imm(DisasContext *s, uint32_t insn)
 }
 
 /*
- * C3.4.5 Move wide (immediate)
+ * Move wide (immediate)
  *
  *  31 30 29 28         23 22 21 20             5 4    0
  * +--+-----+-------------+-----+----------------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.4.2 Bitfield
+/* Bitfield
  *   31  30 29 28         23 22  21  16 15  10 9    5 4    0
  * +----+-----+-------------+---+------+------+------+------+
  * | sf | opc | 1 0 0 1 1 0 | N | immr | imms |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.4.3 Extract
+/* Extract
  *   31  30  29 28         23 22   21  20  16 15    10 9    5 4    0
  * +----+------+-------------+---+----+------+--------+------+------+
  * | sf | op21 | 1 0 0 1 1 1 | N | o0 |  Rm  |  imms  |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.4 Data processing - immediate */
+/* Data processing - immediate */
 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
 {
     switch (extract32(insn, 23, 6)) {
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
     }
 }
 
-/* C3.5.10 Logical (shifted register)
+/* Logical (shifted register)
  *   31  30 29 28       24 23   22 21  20  16 15    10 9    5 4    0
  * +----+-----+-----------+-------+---+------+--------+------+------+
  * | sf | opc | 0 1 0 1 0 | shift | N |  Rm  |  imm6  |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_logic_reg(DisasContext *s, uint32_t insn)
 }
 
 /*
- * C3.5.1 Add/subtract (extended register)
+ * Add/subtract (extended register)
  *
  *  31|30|29|28       24|23 22|21|20   16|15  13|12  10|9  5|4  0|
  * +--+--+--+-----------+-----+--+-------+------+------+----+----+
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
 }
 
 /*
- * C3.5.2 Add/subtract (shifted register)
+ * Add/subtract (shifted register)
  *
  *  31 30 29 28       24 23 22 21 20   16 15     10 9    5 4    0
  * +--+--+--+-----------+-----+--+-------+---------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_result);
 }
 
-/* C3.5.9 Data-processing (3 source)
-
-   31 30  29 28       24 23 21  20  16  15  14  10 9    5 4    0
-  +--+------+-----------+------+------+----+------+------+------+
-  |sf| op54 | 1 1 0 1 1 | op31 |  Rm  | o0 |  Ra  |  Rn  |  Rd  |
-  +--+------+-----------+------+------+----+------+------+------+
-
+/* Data-processing (3 source)
+ *
+ *    31 30  29 28       24 23 21  20  16  15  14  10 9    5 4    0
+ *  +--+------+-----------+------+------+----+------+------+------+
+ *  |sf| op54 | 1 1 0 1 1 | op31 |  Rm  | o0 |  Ra  |  Rn  |  Rd  |
+ *  +--+------+-----------+------+------+----+------+------+------+
  */
 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
 {
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_tmp);
 }
 
-/* C3.5.3 - Add/subtract (with carry)
+/* Add/subtract (with carry)
  *  31 30 29 28 27 26 25 24 23 22 21  20  16  15   10  9    5 4   0
  * +--+--+--+------------------------+------+---------+------+-----+
  * |sf|op| S| 1  1  0  1  0  0  0  0 |  rm  | opcode2 |  Rn  |  Rd |
@@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
+/* Conditional compare (immediate / register)
  *  31 30 29 28 27 26 25 24 23 22 21  20    16 15  12  11  10  9   5  4 3   0
  * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
  * |sf|op| S| 1  1  0  1  0  0  1  0 |imm5/rm | cond |i/r |o2|  Rn  |o3|nzcv |
@@ -XXX,XX +XXX,XX @@ static void disas_cc(DisasContext *s, uint32_t insn)
     tcg_temp_free_i32(tcg_t2);
 }
 
-/* C3.5.6 Conditional select
+/* Conditional select
  *   31   30  29  28             21 20  16 15  12 11 10 9    5 4    0
  * +----+----+---+-----------------+------+------+-----+------+------+
  * | sf | op | S | 1 1 0 1 0 1 0 0 |  Rm  | cond | op2 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_rbit(DisasContext *s, unsigned int sf,
     }
 }
 
-/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
+/* REV with sf==1, opcode==3 ("REV64") */
 static void handle_rev64(DisasContext *s, unsigned int sf,
                          unsigned int rn, unsigned int rd)
 {
@@ -XXX,XX +XXX,XX @@ static void handle_rev64(DisasContext *s, unsigned int sf,
     tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
 }
 
-/* C5.6.149 REV with sf==0, opcode==2
- * C5.6.151 REV32 (sf==1, opcode==2)
+/* REV with sf==0, opcode==2
+ * REV32 (sf==1, opcode==2)
  */
 static void handle_rev32(DisasContext *s, unsigned int sf,
                          unsigned int rn, unsigned int rd)
@@ -XXX,XX +XXX,XX @@ static void handle_rev32(DisasContext *s, unsigned int sf,
     }
 }
 
-/* C5.6.150 REV16 (opcode==1) */
+/* REV16 (opcode==1) */
 static void handle_rev16(DisasContext *s, unsigned int sf,
                          unsigned int rn, unsigned int rd)
 {
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
     tcg_temp_free_i64(tcg_tmp);
 }
 
-/* C3.5.7 Data-processing (1 source)
+/* Data-processing (1 source)
  *   31  30  29  28             21 20     16 15    10 9    5 4    0
  * +----+---+---+-----------------+---------+--------+------+------+
  * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
     }
 }
 
-/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
+/* LSLV, LSRV, ASRV, RORV */
 static void handle_shift_reg(DisasContext *s,
                              enum a64_shift_type shift_type, unsigned int sf,
                              unsigned int rm, unsigned int rn, unsigned int rd)
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
     tcg_temp_free_i32(tcg_bytes);
 }
 
-/* C3.5.8 Data-processing (2 source)
+/* Data-processing (2 source)
  *   31   30  29 28             21 20  16 15    10 9    5 4    0
  * +----+---+---+-----------------+------+--------+------+------+
  * | sf | 0 | S | 1 1 0 1 0 1 1 0 |  Rm  | opcode |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.5 Data processing - register */
+/* Data processing - register */
 static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
 {
     switch (extract32(insn, 24, 5)) {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
     tcg_temp_free_i64(tcg_flags);
 }
 
-/* C3.6.22 Floating point compare
+/* Floating point compare
  *   31  30  29 28       24 23  22  21 20  16 15 14 13  10    9    5 4     0
  * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
  * | M | 0 | S | 1 1 1 1 0 | type | 1 |  Rm  | op  | 1 0 0 0 |  Rn  |  op2  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
     handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
 }
 
-/* C3.6.23 Floating point conditional compare
+/* Floating point conditional compare
  *   31  30  29 28       24 23  22  21 20  16 15  12 11 10 9    5  4   3    0
  * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
  * | M | 0 | S | 1 1 1 1 0 | type | 1 |  Rm  | cond | 0 1 |  Rn  | op | nzcv |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.24 Floating point conditional select
+/* Floating point conditional select
  *   31  30  29 28       24 23  22  21 20  16 15  12 11 10 9    5 4    0
  * +---+---+---+-----------+------+---+------+------+-----+------+------+
  * | M | 0 | S | 1 1 1 1 0 | type | 1 |  Rm  | cond | 1 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(t_true);
 }
 
-/* C3.6.25 Floating-point data-processing (1 source) - single precision */
+/* Floating-point data-processing (1 source) - single precision */
 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
 {
     TCGv_ptr fpst;
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
     tcg_temp_free_i32(tcg_res);
 }
 
-/* C3.6.25 Floating-point data-processing (1 source) - double precision */
+/* Floating-point data-processing (1 source) - double precision */
 static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
 {
     TCGv_ptr fpst;
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
     }
 }
 
-/* C3.6.25 Floating point data-processing (1 source)
+/* Floating point data-processing (1 source)
  *   31  30  29 28       24 23  22  21 20    15 14       10 9    5 4    0
  * +---+---+---+-----------+------+---+--------+-----------+------+------+
  * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.26 Floating-point data-processing (2 source) - single precision */
+/* Floating-point data-processing (2 source) - single precision */
 static void handle_fp_2src_single(DisasContext *s, int opcode,
                                   int rd, int rn, int rm)
 {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
     tcg_temp_free_i32(tcg_res);
 }
 
-/* C3.6.26 Floating-point data-processing (2 source) - double precision */
+/* Floating-point data-processing (2 source) - double precision */
 static void handle_fp_2src_double(DisasContext *s, int opcode,
                                   int rd, int rn, int rm)
 {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
     tcg_temp_free_i64(tcg_res);
 }
 
-/* C3.6.26 Floating point data-processing (2 source)
+/* Floating point data-processing (2 source)
  *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
  * +---+---+---+-----------+------+---+------+--------+-----+------+------+
  * | M | 0 | S | 1 1 1 1 0 | type | 1 |  Rm  | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.27 Floating-point data-processing (3 source) - single precision */
+/* Floating-point data-processing (3 source) - single precision */
 static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
                                   int rd, int rn, int rm, int ra)
 {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
     tcg_temp_free_i32(tcg_res);
 }
 
-/* C3.6.27 Floating-point data-processing (3 source) - double precision */
+/* Floating-point data-processing (3 source) - double precision */
 static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
                                   int rd, int rn, int rm, int ra)
 {
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
     tcg_temp_free_i64(tcg_res);
 }
 
-/* C3.6.27 Floating point data-processing (3 source)
+/* Floating point data-processing (3 source)
  *   31  30  29 28       24 23  22  21  20  16  15  14  10 9    5 4    0
  * +---+---+---+-----------+------+----+------+----+------+------+------+
  * | M | 0 | S | 1 1 1 1 1 | type | o1 |  Rm  | o0 |  Ra  |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.28 Floating point immediate
+/* Floating point immediate
  *   31  30  29 28       24 23  22  21 20        13 12   10 9    5 4    0
  * +---+---+---+-----------+------+---+------------+-------+------+------+
  * | M | 0 | S | 1 1 1 1 0 | type | 1 |    imm8    | 1 0 0 | imm5 |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
     tcg_temp_free_i32(tcg_shift);
 }
 
-/* C3.6.29 Floating point <-> fixed point conversions
+/* Floating point <-> fixed point conversions
  *   31   30  29 28       24 23  22  21 20   19 18    16 15   10 9    5 4    0
  * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
  * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
     }
 }
 
-/* C3.6.30 Floating point <-> integer conversions
+/* Floating point <-> integer conversions
  *   31   30  29 28       24 23  22  21 20   19 18 16 15         10 9  5 4  0
  * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
  * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
@@ -XXX,XX +XXX,XX @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
     tcg_temp_free_i64(tcg_tmp);
 }
 
-/* C3.6.1 EXT
+/* EXT
  *   31  30 29         24 23 22  21 20  16 15  14  11 10  9    5 4    0
  * +---+---+-------------+-----+---+------+---+------+---+------+------+
  * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | imm4 | 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resh);
 }
 
-/* C3.6.2 TBL/TBX
+/* TBL/TBX
  *   31  30 29         24 23 22  21 20  16 15  14 13  12  11 10 9    5 4    0
  * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
  * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 |  Rm  | 0 | len | op | 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resh);
 }
 
-/* C3.6.3 ZIP/UZP/TRN
+/* ZIP/UZP/TRN
  *   31  30 29         24 23  22  21 20   16 15 14 12 11 10 9    5 4    0
  * +---+---+-------------+------+---+------+---+------------------+------+
  * | 0 | Q | 0 0 1 1 1 0 | size | 0 |  Rm  | 0 | opc | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
     }
 }
 
-/* C3.6.4 AdvSIMD across lanes
+/* AdvSIMD across lanes
  *   31  30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
  * +---+---+---+-----------+------+-----------+--------+-----+------+------+
  * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_res);
 }
 
-/* C6.3.31 DUP (Element, Vector)
+/* DUP (Element, Vector)
  *
  *  31  30   29              21 20    16 15        10  9    5 4    0
  * +---+---+-------------------+--------+-------------+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
     tcg_temp_free_i64(tmp);
 }
 
-/* C6.3.31 DUP (element, scalar)
+/* DUP (element, scalar)
  *  31                   21 20    16 15        10  9    5 4    0
  * +-----------------------+--------+-------------+------+------+
  * | 0 1 0 1 1 1 1 0 0 0 0 |  imm5  | 0 0 0 0 0 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupes(DisasContext *s, int rd, int rn,
     tcg_temp_free_i64(tmp);
 }
 
-/* C6.3.32 DUP (General)
+/* DUP (General)
  *
  *  31  30   29              21 20    16 15        10  9    5 4    0
  * +---+---+-------------------+--------+-------------+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
     }
 }
 
-/* C6.3.150 INS (Element)
+/* INS (Element)
  *
  *  31                   21 20    16 15  14    11  10 9    5 4    0
  * +-----------------------+--------+------------+---+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
 }
 
 
-/* C6.3.151 INS (General)
+/* INS (General)
  *
  *  31                   21 20    16 15        10  9    5 4    0
  * +-----------------------+--------+-------------+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
 }
 
 /*
- * C6.3.321 UMOV (General)
- * C6.3.237 SMOV (General)
+ * UMOV (General)
+ * SMOV (General)
  *
  *  31  30   29              21 20    16 15    12   10 9    5 4    0
  * +---+---+-------------------+--------+-------------+------+------+
@@ -XXX,XX +XXX,XX @@ static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
     }
 }
 
-/* C3.6.5 AdvSIMD copy
+/* AdvSIMD copy
  *   31  30  29  28             21 20  16 15  14  11 10  9    5 4    0
  * +---+---+----+-----------------+------+---+------+---+------+------+
  * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.6 AdvSIMD modified immediate
+/* AdvSIMD modified immediate
  *  31  30   29  28                 19 18 16 15   12  11  10  9     5 4    0
  * +---+---+----+---------------------+-----+-------+----+---+-------+------+
  * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_imm);
 }
 
-/* C3.6.7 AdvSIMD scalar copy
+/* AdvSIMD scalar copy
  *  31 30  29  28             21 20  16 15  14  11 10  9    5 4    0
  * +-----+----+-----------------+------+---+------+---+------+------+
  * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
     handle_simd_dupes(s, rd, rn, imm5);
 }
 
-/* C3.6.8 AdvSIMD scalar pairwise
+/* AdvSIMD scalar pairwise
  *  31 30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
  * +-----+---+-----------+------+-----------+--------+-----+------+------+
  * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
     tcg_temp_free_i32(tcg_rmode);
 }
 
-/* C3.6.9 AdvSIMD scalar shift by immediate
+/* AdvSIMD scalar shift by immediate
  *  31 30  29 28         23 22  19 18  16 15    11  10 9    5 4    0
  * +-----+---+-------------+------+------+--------+---+------+------+
  * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.10 AdvSIMD scalar three different
+/* AdvSIMD scalar three different
  *  31 30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
  * +-----+---+-----------+------+---+------+--------+-----+------+------+
  * | 0 1 | U | 1 1 1 1 0 | size | 1 |  Rm  | opcode | 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
     }
 }
 
-/* C3.6.11 AdvSIMD scalar three same
+/* AdvSIMD scalar three same
  *  31 30  29 28       24 23  22  21 20  16 15    11  10 9    5 4    0
  * +-----+---+-----------+------+---+------+--------+---+------+------+
  * | 0 1 | U | 1 1 1 1 0 | size | 1 |  Rm  | opcode | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
     }
 }
 
-/* C3.6.12 AdvSIMD scalar two reg misc
+/* AdvSIMD scalar two reg misc
  *  31 30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
  * +-----+---+-----------+------+-----------+--------+-----+------+------+
  * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
 }
 
 
-/* C3.6.14 AdvSIMD shift by immediate
+/* AdvSIMD shift by immediate
  *  31  30   29 28         23 22  19 18  16 15    11  10 9    5 4    0
  * +---+---+---+-------------+------+------+--------+---+------+------+
  * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
     tcg_temp_free_i64(tcg_res);
 }
 
-/* C3.6.15 AdvSIMD three different
+/* AdvSIMD three different
  *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
  * +---+---+---+-----------+------+---+------+--------+-----+------+------+
  * | 0 | Q | U | 0 1 1 1 0 | size | 1 |  Rm  | opcode | 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.16 AdvSIMD three same
+/* AdvSIMD three same
  *  31  30  29  28       24 23  22  21 20  16 15    11  10 9    5 4    0
  * +---+---+---+-----------+------+---+------+--------+---+------+------+
  * | 0 | Q | U | 0 1 1 1 0 | size | 1 |  Rm  | opcode | 1 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
     }
 }
 
-/* C3.6.17 AdvSIMD two reg misc
+/* AdvSIMD two reg misc
  *   31  30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
  * +---+---+---+-----------+------+-----------+--------+-----+------+------+
  * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.13 AdvSIMD scalar x indexed element
+/* AdvSIMD scalar x indexed element
  *  31 30  29 28       24 23  22 21  20  19  16 15 12  11  10 9    5 4    0
  * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
  * | 0 1 | U | 1 1 1 1 1 | size | L | M |  Rm  | opc | H | 0 |  Rn  |  Rd  |
  * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
- * C3.6.18 AdvSIMD vector x indexed element
+ * AdvSIMD vector x indexed element
  *   31  30  29 28       24 23  22 21  20  19  16 15 12  11  10 9    5 4    0
  * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
  * | 0 | Q | U | 0 1 1 1 1 | size | L | M |  Rm  | opc | H | 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
     }
 }
 
-/* C3.6.19 Crypto AES
+/* Crypto AES
  *  31             24 23  22 21       17 16    12 11 10 9    5 4    0
  * +-----------------+------+-----------+--------+-----+------+------+
  * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
     tcg_temp_free_i32(tcg_decrypt);
 }
 
-/* C3.6.20 Crypto three-reg SHA
+/* Crypto three-reg SHA
  *  31             24 23  22  21 20  16  15 14    12 11 10 9    5 4    0
  * +-----------------+------+---+------+---+--------+-----+------+------+
  * | 0 1 0 1 1 1 1 0 | size | 0 |  Rm  | 0 | opcode | 0 0 |  Rn  |  Rd  |
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
     tcg_temp_free_i32(tcg_rm_regno);
 }
 
-/* C3.6.21 Crypto two-reg SHA
+/* Crypto two-reg SHA
  *  31             24 23  22 21       17 16    12 11 10 9    5 4    0
  * +-----------------+------+-----------+--------+-----+------+------+
  * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 |  Rn  |  Rd  |
-- 
2.7.4

Update the static_ops functions to use new-style mmio
rather than the legacy old_mmio functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505580378-9044-2-git-send-email-peter.maydell@linaro.org
---
 hw/arm/palm.c | 30 ++++++++++--------------------
 1 file changed, 10 insertions(+), 20 deletions(-)

diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "cpu.h"
 
-static uint32_t static_readb(void *opaque, hwaddr offset)
+static uint64_t static_read(void *opaque, hwaddr offset, unsigned size)
 {
-    uint32_t *val = (uint32_t *) opaque;
-    return *val >> ((offset & 3) << 3);
-}
+    uint32_t *val = (uint32_t *)opaque;
+    uint32_t sizemask = 7 >> size;
 
-static uint32_t static_readh(void *opaque, hwaddr offset)
-{
-    uint32_t *val = (uint32_t *) opaque;
-    return *val >> ((offset & 1) << 3);
-}
-
-static uint32_t static_readw(void *opaque, hwaddr offset)
-{
-    uint32_t *val = (uint32_t *) opaque;
-    return *val >> ((offset & 0) << 3);
+    return *val >> ((offset & sizemask) << 3);
 }
 
-static void static_write(void *opaque, hwaddr offset,
-                uint32_t value)
+static void static_write(void *opaque, hwaddr offset, uint64_t value,
+                         unsigned size)
 {
 #ifdef SPY
     printf("%s: value %08lx written at " PA_FMT "\n",
@@ -XXX,XX +XXX,XX @@ static void static_write(void *opaque, hwaddr offset,
 }
 
 static const MemoryRegionOps static_ops = {
-    .old_mmio = {
-        .read = { static_readb, static_readh, static_readw, },
-        .write = { static_write, static_write, static_write, },
-    },
+    .read = static_read,
+    .write = static_write,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-- 
2.7.4

Drop the use of old_mmio in the omap2_gpio memory ops.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505580378-9044-3-git-send-email-peter.maydell@linaro.org
---
 hw/gpio/omap_gpio.c | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/omap_gpio.c
+++ b/hw/gpio/omap_gpio.c
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_write(void *opaque, hwaddr addr,
     }
 }
 
-static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
+static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
+                                        unsigned size)
 {
     return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
 }
 
 static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
-                uint32_t value)
+                                     uint64_t value, unsigned size)
 {
     uint32_t cur = 0;
     uint32_t mask = 0xffff;
 
+    if (size == 4) {
+        omap2_gpio_module_write(opaque, addr, value);
+        return;
+    }
+
     switch (addr & ~3) {
     case 0x00:	/* GPIO_REVISION */
     case 0x14:	/* GPIO_SYSSTATUS */
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
 }
 
 static const MemoryRegionOps omap2_gpio_module_ops = {
-    .old_mmio = {
-        .read = {
-            omap2_gpio_module_readp,
-            omap2_gpio_module_readp,
-            omap2_gpio_module_read,
-        },
-        .write = {
-            omap2_gpio_module_writep,
-            omap2_gpio_module_writep,
-            omap2_gpio_module_write,
-        },
-    },
+    .read = omap2_gpio_module_readp,
+    .write = omap2_gpio_module_writep,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-- 
2.7.4

Don't use the old_mmio in the memory region ops struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505580378-9044-4-git-send-email-peter.maydell@linaro.org
---
 hw/timer/omap_synctimer.c | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/omap_synctimer.c
+++ b/hw/timer/omap_synctimer.c
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
     }
 }
 
-static void omap_synctimer_write(void *opaque, hwaddr addr,
-                uint32_t value)
+static uint64_t omap_synctimer_readfn(void *opaque, hwaddr addr,
+                                      unsigned size)
+{
+    switch (size) {
+    case 1:
+        return omap_badwidth_read32(opaque, addr);
+    case 2:
+        return omap_synctimer_readh(opaque, addr);
+    case 4:
+        return omap_synctimer_readw(opaque, addr);
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void omap_synctimer_writefn(void *opaque, hwaddr addr,
+                                   uint64_t value, unsigned size)
 {
     OMAP_BAD_REG(addr);
 }
 
 static const MemoryRegionOps omap_synctimer_ops = {
-    .old_mmio = {
-        .read = {
-            omap_badwidth_read32,
-            omap_synctimer_readh,
-            omap_synctimer_readw,
-        },
-        .write = {
-            omap_badwidth_write32,
-            omap_synctimer_write,
-            omap_synctimer_write,
-        },
-    },
+    .read = omap_synctimer_readfn,
+    .write = omap_synctimer_writefn,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-- 
2.7.4

Don't use the old_mmio struct in memory region ops.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
---
 hw/timer/omap_gptimer.c | 49 +++++++++++++++++++++++++++++++++++++------------
 1 file changed, 37 insertions(+), 12 deletions(-)

diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/omap_gptimer.c
+++ b/hw/timer/omap_gptimer.c
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
         s->writeh = (uint16_t) value;
 }
 
+static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,
+                                     unsigned size)
+{
+    switch (size) {
+    case 1:
+        return omap_badwidth_read32(opaque, addr);
+    case 2:
+        return omap_gp_timer_readh(opaque, addr);
+    case 4:
+        return omap_gp_timer_readw(opaque, addr);
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void omap_gp_timer_writefn(void *opaque, hwaddr addr,
+                                  uint64_t value, unsigned size)
+{
+    switch (size) {
+    case 1:
+        omap_badwidth_write32(opaque, addr, value);
+        break;
+    case 2:
+        omap_gp_timer_writeh(opaque, addr, value);
+        break;
+    case 4:
+        omap_gp_timer_write(opaque, addr, value);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static const MemoryRegionOps omap_gp_timer_ops = {
-    .old_mmio = {
-        .read = {
-            omap_badwidth_read32,
-            omap_gp_timer_readh,
-            omap_gp_timer_readw,
-        },
-        .write = {
-            omap_badwidth_write32,
-            omap_gp_timer_writeh,
-            omap_gp_timer_write,
-        },
-    },
+    .read = omap_gp_timer_readfn,
+    .write = omap_gp_timer_writefn,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-- 
2.7.4

Don't use old_mmio in the memory region ops struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505580378-9044-6-git-send-email-peter.maydell@linaro.org
---
 hw/i2c/omap_i2c.c | 44 ++++++++++++++++++++++++++++++++------------
 1 file changed, 32 insertions(+), 12 deletions(-)

diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/omap_i2c.c
+++ b/hw/i2c/omap_i2c.c
@@ -XXX,XX +XXX,XX @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
     }
 }
 
+static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
+                                unsigned size)
+{
+    switch (size) {
+    case 2:
+        return omap_i2c_read(opaque, addr);
+    default:
+        return omap_badwidth_read16(opaque, addr);
+    }
+}
+
+static void omap_i2c_writefn(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+{
+    switch (size) {
+    case 1:
+        /* Only the last fifo write can be 8 bit. */
+        omap_i2c_writeb(opaque, addr, value);
+        break;
+    case 2:
+        omap_i2c_write(opaque, addr, value);
+        break;
+    default:
+        omap_badwidth_write16(opaque, addr, value);
+        break;
+    }
+}
+
 static const MemoryRegionOps omap_i2c_ops = {
-    .old_mmio = {
-        .read = {
-            omap_badwidth_read16,
-            omap_i2c_read,
-            omap_badwidth_read16,
-        },
-        .write = {
-            omap_i2c_writeb, /* Only the last fifo write can be 8 bit.  */
-            omap_i2c_write,
-            omap_badwidth_write16,
-        },
-    },
+    .read = omap_i2c_readfn,
+    .write = omap_i2c_writefn,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-- 
2.7.4

Don't use old_mmio in the memory region ops struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505580378-9044-7-git-send-email-peter.maydell@linaro.org
---
 hw/arm/omap2.c | 49 +++++++++++++++++++++++++++++++++++++------------
 1 file changed, 37 insertions(+), 12 deletions(-)

diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write(void *opaque, hwaddr addr,
     }
 }
 
+static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
+                                   unsigned size)
+{
+    switch (size) {
+    case 1:
+        return omap_sysctl_read8(opaque, addr);
+    case 2:
+        return omap_badwidth_read32(opaque, addr); /* TODO */
+    case 4:
+        return omap_sysctl_read(opaque, addr);
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void omap_sysctl_writefn(void *opaque, hwaddr addr,
+                                uint64_t value, unsigned size)
+{
+    switch (size) {
+    case 1:
+        omap_sysctl_write8(opaque, addr, value);
+        break;
+    case 2:
+        omap_badwidth_write32(opaque, addr, value); /* TODO */
+        break;
+    case 4:
+        omap_sysctl_write(opaque, addr, value);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static const MemoryRegionOps omap_sysctl_ops = {
-    .old_mmio = {
-        .read = {
-            omap_sysctl_read8,
-            omap_badwidth_read32,	/* TODO */
-            omap_sysctl_read,
-        },
-        .write = {
-            omap_sysctl_write8,
-            omap_badwidth_write32,	/* TODO */
-            omap_sysctl_write,
-        },
-    },
+    .read = omap_sysctl_readfn,
+    .write = omap_sysctl_writefn,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-- 
2.7.4

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Modelled System Timer in Microsemi's Smartfusion2 Soc.
Timer has two 32bit down counters and two interrupts.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170920201737.25723-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/Makefile.objs       |   1 +
 include/hw/timer/mss-timer.h |  64 ++++++++++
 hw/timer/mss-timer.c         | 289 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 354 insertions(+)
 create mode 100644 include/hw/timer/mss-timer.h
 create mode 100644 hw/timer/mss-timer.c

diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
 
 common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
 common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
+common-obj-$(CONFIG_MSF2) += mss-timer.o
diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/timer/mss-timer.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microsemi SmartFusion2 Timer.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSS_TIMER_H
+#define HW_MSS_TIMER_H
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+
+#define TYPE_MSS_TIMER     "mss-timer"
+#define MSS_TIMER(obj)     OBJECT_CHECK(MSSTimerState, \
+                              (obj), TYPE_MSS_TIMER)
+
+/*
+ * There are two 32-bit down counting timers.
+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer
+ * that operates either in Periodic mode or in One-shot mode.
+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
+ * In 64-bit mode, writing to the 32-bit registers has no effect.
+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers
+ * has no effect. Only two 32-bit timers are supported currently.
+ */
+#define NUM_TIMERS        2
+
+#define R_TIM1_MAX        6
+
+struct Msf2Timer {
+    QEMUBH *bh;
+    ptimer_state *ptimer;
+
+    uint32_t regs[R_TIM1_MAX];
+    qemu_irq irq;
+};
+
+typedef struct MSSTimerState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    uint32_t freq_hz;
+    struct Msf2Timer timers[NUM_TIMERS];
+} MSSTimerState;
+
+#endif /* HW_MSS_TIMER_H */
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/timer/mss-timer.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Block model of System timer present in
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "qemu/log.h"
+#include "hw/timer/mss-timer.h"
+
+#ifndef MSS_TIMER_ERR_DEBUG
+#define MSS_TIMER_ERR_DEBUG  0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+    if (MSS_TIMER_ERR_DEBUG >= lvl) { \
+        qemu_log("%s: " fmt "\n", __func__, ## args); \
+    } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+#define R_TIM_VAL         0
+#define R_TIM_LOADVAL     1
+#define R_TIM_BGLOADVAL   2
+#define R_TIM_CTRL        3
+#define R_TIM_RIS         4
+#define R_TIM_MIS         5
+
+#define TIMER_CTRL_ENBL     (1 << 0)
+#define TIMER_CTRL_ONESHOT  (1 << 1)
+#define TIMER_CTRL_INTR     (1 << 2)
+#define TIMER_RIS_ACK       (1 << 0)
+#define TIMER_RST_CLR       (1 << 6)
+#define TIMER_MODE          (1 << 0)
+
+static void timer_update_irq(struct Msf2Timer *st)
+{
+    bool isr, ier;
+
+    isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+    ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+    qemu_set_irq(st->irq, (ier && isr));
+}
+
+static void timer_update(struct Msf2Timer *st)
+{
+    uint64_t count;
+
+    if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
+        ptimer_stop(st->ptimer);
+        return;
+    }
+
+    count = st->regs[R_TIM_LOADVAL];
+    ptimer_set_limit(st->ptimer, count, 1);
+    ptimer_run(st->ptimer, 1);
+}
+
+static uint64_t
+timer_read(void *opaque, hwaddr offset, unsigned int size)
+{
+    MSSTimerState *t = opaque;
+    hwaddr addr;
+    struct Msf2Timer *st;
+    uint32_t ret = 0;
+    int timer = 0;
+    int isr;
+    int ier;
+
+    addr = offset >> 2;
+    /*
+     * Two independent timers has same base address.
+     * Based on address passed figure out which timer is being used.
+     */
+    if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
+        timer = 1;
+        addr -= R_TIM1_MAX;
+    }
+
+    st = &t->timers[timer];
+
+    switch (addr) {
+    case R_TIM_VAL:
+        ret = ptimer_get_count(st->ptimer);
+        break;
+
+    case R_TIM_MIS:
+        isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+        ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+        ret = ier & isr;
+        break;
+
+    default:
+        if (addr < R_TIM1_MAX) {
+            ret = st->regs[addr];
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                        TYPE_MSS_TIMER": 64-bit mode not supported\n");
+            return ret;
+        }
+        break;
+    }
+
+    DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset,
+            ret);
+    return ret;
+}
+
+static void
+timer_write(void *opaque, hwaddr offset,
+            uint64_t val64, unsigned int size)
+{
+    MSSTimerState *t = opaque;
+    hwaddr addr;
+    struct Msf2Timer *st;
+    int timer = 0;
+    uint32_t value = val64;
+
+    addr = offset >> 2;
+    /*
+     * Two independent timers has same base address.
+     * Based on addr passed figure out which timer is being used.
+     */
+    if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
+        timer = 1;
+        addr -= R_TIM1_MAX;
+    }
+
+    st = &t->timers[timer];
+
+    DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
+            value, timer);
+
+    switch (addr) {
+    case R_TIM_CTRL:
+        st->regs[R_TIM_CTRL] = value;
+        timer_update(st);
+        break;
+
+    case R_TIM_RIS:
+        if (value & TIMER_RIS_ACK) {
+            st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
+        }
+        break;
+
+    case R_TIM_LOADVAL:
+        st->regs[R_TIM_LOADVAL] = value;
+        if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
+            timer_update(st);
+        }
+        break;
+
+    case R_TIM_BGLOADVAL:
+        st->regs[R_TIM_BGLOADVAL] = value;
+        st->regs[R_TIM_LOADVAL] = value;
+        break;
+
+    case R_TIM_VAL:
+    case R_TIM_MIS:
+        break;
+
+    default:
+        if (addr < R_TIM1_MAX) {
+            st->regs[addr] = value;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                        TYPE_MSS_TIMER": 64-bit mode not supported\n");
+            return;
+        }
+        break;
+    }
+    timer_update_irq(st);
+}
+
+static const MemoryRegionOps timer_ops = {
+    .read = timer_read,
+    .write = timer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 4
+    }
+};
+
+static void timer_hit(void *opaque)
+{
+    struct Msf2Timer *st = opaque;
+
+    st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
+
+    if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
+        timer_update(st);
+    }
+    timer_update_irq(st);
+}
+
+static void mss_timer_init(Object *obj)
+{
+    MSSTimerState *t = MSS_TIMER(obj);
+    int i;
+
+    /* Init all the ptimers.  */
+    for (i = 0; i < NUM_TIMERS; i++) {
+        struct Msf2Timer *st = &t->timers[i];
+
+        st->bh = qemu_bh_new(timer_hit, st);
+        st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
+        ptimer_set_freq(st->ptimer, t->freq_hz);
+        sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
+    }
+
+    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
+                          NUM_TIMERS * R_TIM1_MAX * 4);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
+}
+
+static const VMStateDescription vmstate_timers = {
+    .name = "mss-timer-block",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_PTIMER(ptimer, struct Msf2Timer),
+        VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static const VMStateDescription vmstate_mss_timer = {
+    .name = TYPE_MSS_TIMER,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(freq_hz, MSSTimerState),
+        VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
+                vmstate_timers, struct Msf2Timer),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static Property mss_timer_properties[] = {
+    /* Libero GUI shows 100Mhz as default for clocks */
+    DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
+                      100 * 1000000),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void mss_timer_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->props = mss_timer_properties;
+    dc->vmsd = &vmstate_mss_timer;
+}
+
+static const TypeInfo mss_timer_info = {
+    .name          = TYPE_MSS_TIMER,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MSSTimerState),
+    .instance_init = mss_timer_init,
+    .class_init    = mss_timer_class_init,
+};
+
+static void mss_timer_register_types(void)
+{
+    type_register_static(&mss_timer_info);
+}
+
+type_init(mss_timer_register_types)
-- 
2.7.4

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Added Sytem register block of Smartfusion2.
This block has PLL registers which are accessed by guest.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170920201737.25723-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/Makefile.objs         |   1 +
 include/hw/misc/msf2-sysreg.h |  77 ++++++++++++++++++++
 hw/misc/msf2-sysreg.c         | 160 ++++++++++++++++++++++++++++++++++++++++++
 hw/misc/trace-events          |   5 ++
 4 files changed, 243 insertions(+)
 create mode 100644 include/hw/misc/msf2-sysreg.h
 create mode 100644 hw/misc/msf2-sysreg.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
 obj-$(CONFIG_AUX) += auxbus.o
 obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
 obj-y += mmio_interface.o
+obj-$(CONFIG_MSF2) += msf2-sysreg.o
diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/msf2-sysreg.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microsemi SmartFusion2 SYSREG
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSF2_SYSREG_H
+#define HW_MSF2_SYSREG_H
+
+#include "hw/sysbus.h"
+
+enum {
+    ESRAM_CR        = 0x00 / 4,
+    ESRAM_MAX_LAT,
+    DDR_CR,
+    ENVM_CR,
+    ENVM_REMAP_BASE_CR,
+    ENVM_REMAP_FAB_CR,
+    CC_CR,
+    CC_REGION_CR,
+    CC_LOCK_BASE_ADDR_CR,
+    CC_FLUSH_INDX_CR,
+    DDRB_BUF_TIMER_CR,
+    DDRB_NB_ADDR_CR,
+    DDRB_NB_SIZE_CR,
+    DDRB_CR,
+
+    SOFT_RESET_CR  = 0x48 / 4,
+    M3_CR,
+
+    GPIO_SYSRESET_SEL_CR = 0x58 / 4,
+
+    MDDR_CR = 0x60 / 4,
+
+    MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
+    MSSDDR_PLL_STATUS_HIGH_CR,
+    MSSDDR_FACC1_CR,
+    MSSDDR_FACC2_CR,
+
+    MSSDDR_PLL_STATUS = 0x150 / 4,
+};
+
+#define MSF2_SYSREG_MMIO_SIZE     0x300
+
+#define TYPE_MSF2_SYSREG          "msf2-sysreg"
+#define MSF2_SYSREG(obj)  OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
+
+typedef struct MSF2SysregState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+
+    uint8_t apb0div;
+    uint8_t apb1div;
+
+    uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
+} MSF2SysregState;
+
+#endif /* HW_MSF2_SYSREG_H */
diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/msf2-sysreg.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * System Register block model of Microsemi SmartFusion2.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "hw/misc/msf2-sysreg.h"
+#include "qemu/error-report.h"
+#include "trace.h"
+
+static inline int msf2_divbits(uint32_t div)
+{
+    int r = ctz32(div);
+
+    return (div < 8) ? r : r + 1;
+}
+
+static void msf2_sysreg_reset(DeviceState *d)
+{
+    MSF2SysregState *s = MSF2_SYSREG(d);
+
+    s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
+    s->regs[MSSDDR_PLL_STATUS] = 0x3;
+    s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
+                               msf2_divbits(s->apb1div) << 2;
+}
+
+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
+    unsigned size)
+{
+    MSF2SysregState *s = opaque;
+    uint32_t ret = 0;
+
+    offset >>= 2;
+    if (offset < ARRAY_SIZE(s->regs)) {
+        ret = s->regs[offset];
+        trace_msf2_sysreg_read(offset << 2, ret);
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                    "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
+                    offset << 2);
+    }
+
+    return ret;
+}
+
+static void msf2_sysreg_write(void *opaque, hwaddr offset,
+                          uint64_t val, unsigned size)
+{
+    MSF2SysregState *s = opaque;
+    uint32_t newval = val;
+
+    offset >>= 2;
+
+    switch (offset) {
+    case MSSDDR_PLL_STATUS:
+        trace_msf2_sysreg_write_pll_status();
+        break;
+
+    case ESRAM_CR:
+    case DDR_CR:
+    case ENVM_REMAP_BASE_CR:
+        if (newval != s->regs[offset]) {
+            qemu_log_mask(LOG_UNIMP,
+                       TYPE_MSF2_SYSREG": remapping not supported\n");
+        }
+        break;
+
+    default:
+        if (offset < ARRAY_SIZE(s->regs)) {
+            trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);
+            s->regs[offset] = newval;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                        "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
+                        offset << 2);
+        }
+        break;
+    }
+}
+
+static const MemoryRegionOps sysreg_ops = {
+    .read = msf2_sysreg_read,
+    .write = msf2_sysreg_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void msf2_sysreg_init(Object *obj)
+{
+    MSF2SysregState *s = MSF2_SYSREG(obj);
+
+    memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
+                          MSF2_SYSREG_MMIO_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
+
+static const VMStateDescription vmstate_msf2_sysreg = {
+    .name = TYPE_MSF2_SYSREG,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static Property msf2_sysreg_properties[] = {
+    /* default divisors in Libero GUI */
+    DEFINE_PROP_UINT8("apb0divisor", MSF2SysregState, apb0div, 2),
+    DEFINE_PROP_UINT8("apb1divisor", MSF2SysregState, apb1div, 2),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void msf2_sysreg_realize(DeviceState *dev, Error **errp)
+{
+    MSF2SysregState *s = MSF2_SYSREG(dev);
+
+    if ((s->apb0div > 32 || !is_power_of_2(s->apb0div))
+        || (s->apb1div > 32 || !is_power_of_2(s->apb1div))) {
+        error_setg(errp, "Invalid apb divisor value");
+        error_append_hint(errp, "apb divisor must be a power of 2"
+                           " and maximum value is 32\n");
+    }
+}
+
+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_msf2_sysreg;
+    dc->reset = msf2_sysreg_reset;
+    dc->props = msf2_sysreg_properties;
+    dc->realize = msf2_sysreg_realize;
+}
+
+static const TypeInfo msf2_sysreg_info = {
+    .name  = TYPE_MSF2_SYSREG,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .class_init = msf2_sysreg_class_init,
+    .instance_size  = sizeof(MSF2SysregState),
+    .instance_init = msf2_sysreg_init,
+};
+
+static void msf2_sysreg_register_types(void)
+{
+    type_register_static(&msf2_sysreg_info);
+}
+
+type_init(msf2_sysreg_register_types)
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ mps2_scc_reset(void) "MPS2 SCC: reset"
 mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) "MPS2 SCC LEDs: %c%c%c%c%c%c%c%c"
 mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
 mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
+
+# hw/misc/msf2-sysreg.c
+msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
+msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
+msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
-- 
2.7.4

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Modelled Microsemi's Smartfusion2 SPI controller.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170920201737.25723-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/Makefile.objs     |   1 +
 include/hw/ssi/mss-spi.h |  58 +++++++
 hw/ssi/mss-spi.c         | 404 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 463 insertions(+)
 create mode 100644 include/hw/ssi/mss-spi.h
 create mode 100644 hw/ssi/mss-spi.c

diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
 common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
 common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
+common-obj-$(CONFIG_MSF2) += mss-spi.o
 
 obj-$(CONFIG_OMAP) += omap_spi.o
 obj-$(CONFIG_IMX) += imx_spi.o
diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/ssi/mss-spi.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microsemi SmartFusion2 SPI
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSS_SPI_H
+#define HW_MSS_SPI_H
+
+#include "hw/sysbus.h"
+#include "hw/ssi/ssi.h"
+#include "qemu/fifo32.h"
+
+#define TYPE_MSS_SPI   "mss-spi"
+#define MSS_SPI(obj)   OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
+
+#define R_SPI_MAX             16
+
+typedef struct MSSSpiState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+
+    qemu_irq irq;
+
+    qemu_irq cs_line;
+
+    SSIBus *spi;
+
+    Fifo32 rx_fifo;
+    Fifo32 tx_fifo;
+
+    int fifo_depth;
+    uint32_t frame_count;
+    bool enabled;
+
+    uint32_t regs[R_SPI_MAX];
+} MSSSpiState;
+
+#endif /* HW_MSS_SPI_H */
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/ssi/mss-spi.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Block model of SPI controller present in
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
+ *
+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/ssi/mss-spi.h"
+#include "qemu/log.h"
+
+#ifndef MSS_SPI_ERR_DEBUG
+#define MSS_SPI_ERR_DEBUG   0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+    if (MSS_SPI_ERR_DEBUG >= lvl) { \
+        qemu_log("%s: " fmt "\n", __func__, ## args); \
+    } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+#define FIFO_CAPACITY         32
+
+#define R_SPI_CONTROL         0
+#define R_SPI_DFSIZE          1
+#define R_SPI_STATUS          2
+#define R_SPI_INTCLR          3
+#define R_SPI_RX              4
+#define R_SPI_TX              5
+#define R_SPI_CLKGEN          6
+#define R_SPI_SS              7
+#define R_SPI_MIS             8
+#define R_SPI_RIS             9
+
+#define S_TXDONE             (1 << 0)
+#define S_RXRDY              (1 << 1)
+#define S_RXCHOVRF           (1 << 2)
+#define S_RXFIFOFUL          (1 << 4)
+#define S_RXFIFOFULNXT       (1 << 5)
+#define S_RXFIFOEMP          (1 << 6)
+#define S_RXFIFOEMPNXT       (1 << 7)
+#define S_TXFIFOFUL          (1 << 8)
+#define S_TXFIFOFULNXT       (1 << 9)
+#define S_TXFIFOEMP          (1 << 10)
+#define S_TXFIFOEMPNXT       (1 << 11)
+#define S_FRAMESTART         (1 << 12)
+#define S_SSEL               (1 << 13)
+#define S_ACTIVE             (1 << 14)
+
+#define C_ENABLE             (1 << 0)
+#define C_MODE               (1 << 1)
+#define C_INTRXDATA          (1 << 4)
+#define C_INTTXDATA          (1 << 5)
+#define C_INTRXOVRFLO        (1 << 6)
+#define C_SPS                (1 << 26)
+#define C_BIGFIFO            (1 << 29)
+#define C_RESET              (1 << 31)
+
+#define FRAMESZ_MASK         0x1F
+#define FMCOUNT_MASK         0x00FFFF00
+#define FMCOUNT_SHIFT        8
+
+static void txfifo_reset(MSSSpiState *s)
+{
+    fifo32_reset(&s->tx_fifo);
+
+    s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
+    s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
+}
+
+static void rxfifo_reset(MSSSpiState *s)
+{
+    fifo32_reset(&s->rx_fifo);
+
+    s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+    s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+}
+
+static void set_fifodepth(MSSSpiState *s)
+{
+    unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
+
+    if (size <= 8) {
+        s->fifo_depth = 32;
+    } else if (size <= 16) {
+        s->fifo_depth = 16;
+    } else if (size <= 32) {
+        s->fifo_depth = 8;
+    } else {
+        s->fifo_depth = 4;
+    }
+}
+
+static void update_mis(MSSSpiState *s)
+{
+    uint32_t reg = s->regs[R_SPI_CONTROL];
+    uint32_t tmp;
+
+    /*
+     * form the Control register interrupt enable bits
+     * same as RIS, MIS and Interrupt clear registers for simplicity
+     */
+    tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
+           ((reg & C_INTTXDATA) >> 5);
+    s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
+}
+
+static void spi_update_irq(MSSSpiState *s)
+{
+    int irq;
+
+    update_mis(s);
+    irq = !!(s->regs[R_SPI_MIS]);
+
+    qemu_set_irq(s->irq, irq);
+}
+
+static void mss_spi_reset(DeviceState *d)
+{
+    MSSSpiState *s = MSS_SPI(d);
+
+    memset(s->regs, 0, sizeof s->regs);
+    s->regs[R_SPI_CONTROL] = 0x80000102;
+    s->regs[R_SPI_DFSIZE] = 0x4;
+    s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
+    s->regs[R_SPI_CLKGEN] = 0x7;
+    s->regs[R_SPI_RIS] = 0x0;
+
+    s->fifo_depth = 4;
+    s->frame_count = 1;
+    s->enabled = false;
+
+    rxfifo_reset(s);
+    txfifo_reset(s);
+}
+
+static uint64_t
+spi_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    MSSSpiState *s = opaque;
+    uint32_t ret = 0;
+
+    addr >>= 2;
+    switch (addr) {
+    case R_SPI_RX:
+        s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+        s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
+        ret = fifo32_pop(&s->rx_fifo);
+        if (fifo32_is_empty(&s->rx_fifo)) {
+            s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+        }
+        break;
+
+    case R_SPI_MIS:
+        update_mis(s);
+        ret = s->regs[R_SPI_MIS];
+        break;
+
+    default:
+        if (addr < ARRAY_SIZE(s->regs)) {
+            ret = s->regs[addr];
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                         "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
+                         addr * 4);
+            return ret;
+        }
+        break;
+    }
+
+    DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
+    spi_update_irq(s);
+    return ret;
+}
+
+static void assert_cs(MSSSpiState *s)
+{
+    qemu_set_irq(s->cs_line, 0);
+}
+
+static void deassert_cs(MSSSpiState *s)
+{
+    qemu_set_irq(s->cs_line, 1);
+}
+
+static void spi_flush_txfifo(MSSSpiState *s)
+{
+    uint32_t tx;
+    uint32_t rx;
+    bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
+
+    /*
+     * Chip Select(CS) is automatically controlled by this controller.
+     * If SPS bit is set in Control register then CS is asserted
+     * until all the frames set in frame count of Control register are
+     * transferred. If SPS is not set then CS pulses between frames.
+     * Note that Slave Select register specifies which of the CS line
+     * has to be controlled automatically by controller. Bits SS[7:1] are for
+     * masters in FPGA fabric since we model only Microcontroller subsystem
+     * of Smartfusion2 we control only one CS(SS[0]) line.
+     */
+    while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
+        assert_cs(s);
+
+        s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
+
+        tx = fifo32_pop(&s->tx_fifo);
+        DB_PRINT("data tx:0x%" PRIx32, tx);
+        rx = ssi_transfer(s->spi, tx);
+        DB_PRINT("data rx:0x%" PRIx32, rx);
+
+        if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
+            s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
+            s->regs[R_SPI_RIS] |= S_RXCHOVRF;
+        } else {
+            fifo32_push(&s->rx_fifo, rx);
+            s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
+            if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
+                s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
+            } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
+                s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
+            }
+        }
+        s->frame_count--;
+        if (!sps) {
+            deassert_cs(s);
+        }
+    }
+
+    if (!s->frame_count) {
+        s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
+                            FMCOUNT_SHIFT;
+        deassert_cs(s);
+        s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
+        s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
+   }
+}
+
+static void spi_write(void *opaque, hwaddr addr,
+            uint64_t val64, unsigned int size)
+{
+    MSSSpiState *s = opaque;
+    uint32_t value = val64;
+
+    DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
+    addr >>= 2;
+
+    switch (addr) {
+    case R_SPI_TX:
+        /* adding to already full FIFO */
+        if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
+            break;
+        }
+        s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
+        fifo32_push(&s->tx_fifo, value);
+        if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
+            s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
+        } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
+            s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
+        }
+        if (s->enabled) {
+            spi_flush_txfifo(s);
+        }
+        break;
+
+    case R_SPI_CONTROL:
+        s->regs[R_SPI_CONTROL] = value;
+        if (value & C_BIGFIFO) {
+            set_fifodepth(s);
+        } else {
+            s->fifo_depth = 4;
+        }
+        s->enabled = value & C_ENABLE;
+        s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
+        if (value & C_RESET) {
+            mss_spi_reset(DEVICE(s));
+        }
+        break;
+
+    case R_SPI_DFSIZE:
+        if (s->enabled) {
+            break;
+        }
+        s->regs[R_SPI_DFSIZE] = value;
+        break;
+
+    case R_SPI_INTCLR:
+        s->regs[R_SPI_INTCLR] = value;
+        if (value & S_TXDONE) {
+            s->regs[R_SPI_RIS] &= ~S_TXDONE;
+        }
+        if (value & S_RXRDY) {
+            s->regs[R_SPI_RIS] &= ~S_RXRDY;
+        }
+        if (value & S_RXCHOVRF) {
+            s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
+        }
+        break;
+
+    case R_SPI_MIS:
+    case R_SPI_STATUS:
+    case R_SPI_RIS:
+            qemu_log_mask(LOG_GUEST_ERROR,
+                         "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
+                         __func__, addr * 4);
+        break;
+
+    default:
+        if (addr < ARRAY_SIZE(s->regs)) {
+            s->regs[addr] = value;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                         "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
+                         addr * 4);
+        }
+        break;
+    }
+
+    spi_update_irq(s);
+}
+
+static const MemoryRegionOps spi_ops = {
+    .read = spi_read,
+    .write = spi_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 4
+    }
+};
+
+static void mss_spi_realize(DeviceState *dev, Error **errp)
+{
+    MSSSpiState *s = MSS_SPI(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+    s->spi = ssi_create_bus(dev, "spi");
+
+    sysbus_init_irq(sbd, &s->irq);
+    ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
+    sysbus_init_irq(sbd, &s->cs_line);
+
+    memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
+                          TYPE_MSS_SPI, R_SPI_MAX * 4);
+    sysbus_init_mmio(sbd, &s->mmio);
+
+    fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
+    fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
+}
+
+static const VMStateDescription vmstate_mss_spi = {
+    .name = TYPE_MSS_SPI,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_FIFO32(tx_fifo, MSSSpiState),
+        VMSTATE_FIFO32(rx_fifo, MSSSpiState),
+        VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void mss_spi_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = mss_spi_realize;
+    dc->reset = mss_spi_reset;
+    dc->vmsd = &vmstate_mss_spi;
+}
+
+static const TypeInfo mss_spi_info = {
+    .name           = TYPE_MSS_SPI,
+    .parent         = TYPE_SYS_BUS_DEVICE,
+    .instance_size  = sizeof(MSSSpiState),
+    .class_init     = mss_spi_class_init,
+};
+
+static void mss_spi_register_types(void)
+{
+    type_register_static(&mss_spi_info);
+}
+
+type_init(mss_spi_register_types)
-- 
2.7.4

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Smartfusion2 SoC has hardened Microcontroller subsystem
and flash based FPGA fabric. This patch adds support for
Microcontroller subsystem in the SoC.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170920201737.25723-5-f4bug@amsat.org
[PMD: drop cpu_model to directly use cpu type, check m3clk non null]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/Makefile.objs            |   1 +
 include/hw/arm/msf2-soc.h       |  67 +++++++++++
 hw/arm/msf2-soc.c               | 238 ++++++++++++++++++++++++++++++++++++++++
 default-configs/arm-softmmu.mak |   1 +
 4 files changed, 307 insertions(+)
 create mode 100644 include/hw/arm/msf2-soc.h
 create mode 100644 hw/arm/msf2-soc.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
 obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
 obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
 obj-$(CONFIG_MPS2) += mps2.o
+obj-$(CONFIG_MSF2) += msf2-soc.o
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/arm/msf2-soc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microsemi Smartfusion2 SoC
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_MSF2_SOC_H
+#define HW_ARM_MSF2_SOC_H
+
+#include "hw/arm/armv7m.h"
+#include "hw/timer/mss-timer.h"
+#include "hw/misc/msf2-sysreg.h"
+#include "hw/ssi/mss-spi.h"
+
+#define TYPE_MSF2_SOC     "msf2-soc"
+#define MSF2_SOC(obj)     OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
+
+#define MSF2_NUM_SPIS         2
+#define MSF2_NUM_UARTS        2
+
+/*
+ * System timer consists of two programmable 32-bit
+ * decrementing counters that generate individual interrupts to
+ * the Cortex-M3 processor
+ */
+#define MSF2_NUM_TIMERS       2
+
+typedef struct MSF2State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+
+    ARMv7MState armv7m;
+
+    char *cpu_type;
+    char *part_name;
+    uint64_t envm_size;
+    uint64_t esram_size;
+
+    uint32_t m3clk;
+    uint8_t apb0div;
+    uint8_t apb1div;
+
+    MSF2SysregState sysreg;
+    MSSTimerState timer;
+    MSSSpiState spi[MSF2_NUM_SPIS];
+} MSF2State;
+
+#endif
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/msf2-soc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SmartFusion2 SoC emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "hw/char/serial.h"
+#include "hw/boards.h"
+#include "sysemu/block-backend.h"
+#include "qemu/cutils.h"
+#include "hw/arm/msf2-soc.h"
+#include "hw/misc/unimp.h"
+
+#define MSF2_TIMER_BASE       0x40004000
+#define MSF2_SYSREG_BASE      0x40038000
+
+#define ENVM_BASE_ADDRESS     0x60000000
+
+#define SRAM_BASE_ADDRESS     0x20000000
+
+#define MSF2_ENVM_MAX_SIZE    (512 * K_BYTE)
+
+/*
+ * eSRAM max size is 80k without SECDED(Single error correction and
+ * dual error detection) feature and 64k with SECDED.
+ * We do not support SECDED now.
+ */
+#define MSF2_ESRAM_MAX_SIZE       (80 * K_BYTE)
+
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
+
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
+
+static void m2sxxx_soc_initfn(Object *obj)
+{
+    MSF2State *s = MSF2_SOC(obj);
+    int i;
+
+    object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
+    qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
+
+    object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
+    qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
+
+    object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
+    qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
+
+    for (i = 0; i < MSF2_NUM_SPIS; i++) {
+        object_initialize(&s->spi[i], sizeof(s->spi[i]),
+                          TYPE_MSS_SPI);
+        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+    }
+}
+
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+    MSF2State *s = MSF2_SOC(dev_soc);
+    DeviceState *dev, *armv7m;
+    SysBusDevice *busdev;
+    Error *err = NULL;
+    int i;
+
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *nvm = g_new(MemoryRegion, 1);
+    MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
+    MemoryRegion *sram = g_new(MemoryRegion, 1);
+
+    memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
+                           &error_fatal);
+    /*
+     * On power-on, the eNVM region 0x60000000 is automatically
+     * remapped to the Cortex-M3 processor executable region
+     * start address (0x0). We do not support remapping other eNVM,
+     * eSRAM and DDR regions by guest(via Sysreg) currently.
+     */
+    memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
+                             nvm, 0, s->envm_size);
+
+    memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
+    memory_region_add_subregion(system_memory, 0, nvm_alias);
+
+    memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
+                           &error_fatal);
+    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+    armv7m = DEVICE(&s->armv7m);
+    qdev_prop_set_uint32(armv7m, "num-irq", 81);
+    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+    object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
+                                     "memory", &error_abort);
+    object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    if (!s->m3clk) {
+        error_setg(errp, "Invalid m3clk value");
+        error_append_hint(errp, "m3clk can not be zero\n");
+        return;
+    }
+    system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
+
+    for (i = 0; i < MSF2_NUM_UARTS; i++) {
+        if (serial_hds[i]) {
+            serial_mm_init(get_system_memory(), uart_addr[i], 2,
+                           qdev_get_gpio_in(armv7m, uart_irq[i]),
+                           115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
+        }
+    }
+
+    dev = DEVICE(&s->timer);
+    /* APB0 clock is the timer input clock */
+    qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
+    object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
+    sysbus_connect_irq(busdev, 0,
+                           qdev_get_gpio_in(armv7m, timer_irq[0]));
+    sysbus_connect_irq(busdev, 1,
+                           qdev_get_gpio_in(armv7m, timer_irq[1]));
+
+    dev = DEVICE(&s->sysreg);
+    qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
+    qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
+    object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
+
+    for (i = 0; i < MSF2_NUM_SPIS; i++) {
+        gchar *bus_name;
+
+        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+                           qdev_get_gpio_in(armv7m, spi_irq[i]));
+
+        /* Alias controller SPI bus to the SoC itself */
+        bus_name = g_strdup_printf("spi%d", i);
+        object_property_add_alias(OBJECT(s), bus_name,
+                                  OBJECT(&s->spi[i]), "spi",
+                                  &error_abort);
+        g_free(bus_name);
+    }
+
+    /* Below devices are not modelled yet. */
+    create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
+    create_unimplemented_device("dma", 0x40003000, 0x1000);
+    create_unimplemented_device("watchdog", 0x40005000, 0x1000);
+    create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
+    create_unimplemented_device("gpio", 0x40013000, 0x1000);
+    create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
+    create_unimplemented_device("can", 0x40015000, 0x1000);
+    create_unimplemented_device("rtc", 0x40017000, 0x1000);
+    create_unimplemented_device("apb_config", 0x40020000, 0x10000);
+    create_unimplemented_device("emac", 0x40041000, 0x1000);
+    create_unimplemented_device("usb", 0x40043000, 0x1000);
+}
+
+static Property m2sxxx_soc_properties[] = {
+    /*
+     * part name specifies the type of SmartFusion2 device variant(this
+     * property is for information purpose only.
+     */
+    DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
+    DEFINE_PROP_STRING("part-name", MSF2State, part_name),
+    DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
+    DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
+                        MSF2_ESRAM_MAX_SIZE),
+    /* Libero GUI shows 100Mhz as default for clocks */
+    DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
+    /* default divisors in Libero GUI */
+    DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
+    DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = m2sxxx_soc_realize;
+    dc->props = m2sxxx_soc_properties;
+}
+
+static const TypeInfo m2sxxx_soc_info = {
+    .name          = TYPE_MSF2_SOC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MSF2State),
+    .instance_init = m2sxxx_soc_initfn,
+    .class_init    = m2sxxx_soc_class_init,
+};
+
+static void m2sxxx_soc_types(void)
+{
+    type_register_static(&m2sxxx_soc_info);
+}
+
+type_init(m2sxxx_soc_types)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_ACPI=y
 CONFIG_SMBIOS=y
 CONFIG_ASPEED_SOC=y
 CONFIG_GPIO_KEY=y
+CONFIG_MSF2=y
-- 
2.7.4

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Emulated Emcraft's Smartfusion2 System On Module starter
kit.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170920201737.25723-6-f4bug@amsat.org
[PMD: drop cpu_model to directly use cpu type]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/Makefile.objs |   2 +-
 hw/arm/msf2-som.c    | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 106 insertions(+), 1 deletion(-)
 create mode 100644 hw/arm/msf2-som.c

target-arm queue: the big stuff here is the final part of
rth's patches for Cortex-A76 and Neoverse-N1 support;
also present are Gavin's NUMA series and a few other things.

thanks
-- PMM

The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:

Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509

for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:

hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)

----------------------------------------------------------------
target-arm queue:
 * MAINTAINERS/.mailmap: update email for Leif Lindholm
 * hw/arm: add version information to sbsa-ref machine DT
 * Enable new features for -cpu max:
   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
   FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
 * Emulate Cortex-A76
 * Emulate Neoverse-N1
 * Fix the virt board default NUMA topology

----------------------------------------------------------------
Gavin Shan (6):
      qapi/machine.json: Add cluster-id
      qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
      hw/arm/virt: Consider SMP configuration in CPU topology
      qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
      hw/arm/virt: Fix CPU's default NUMA node ID
      hw/acpi/aml-build: Use existing CPU topology to build PPTT table

Leif Lindholm (2):
      MAINTAINERS/.mailmap: update email for Leif Lindholm
      hw/arm: add versioning to sbsa-ref machine DT

Richard Henderson (24):
      target/arm: Handle cpreg registration for missing EL
      target/arm: Drop EL3 no EL2 fallbacks
      target/arm: Merge zcr reginfo
      target/arm: Adjust definition of CONTEXTIDR_EL2
      target/arm: Move cortex impdef sysregs to cpu_tcg.c
      target/arm: Update qemu-system-arm -cpu max to cortex-a57
      target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
      target/arm: Split out aa32_max_features
      target/arm: Annotate arm_max_initfn with FEAT identifiers
      target/arm: Use field names for manipulating EL2 and EL3 modes
      target/arm: Enable FEAT_Debugv8p2 for -cpu max
      target/arm: Enable FEAT_Debugv8p4 for -cpu max
      target/arm: Add minimal RAS registers
      target/arm: Enable SCR and HCR bits for RAS
      target/arm: Implement virtual SError exceptions
      target/arm: Implement ESB instruction
      target/arm: Enable FEAT_RAS for -cpu max
      target/arm: Enable FEAT_IESB for -cpu max
      target/arm: Enable FEAT_CSV2 for -cpu max
      target/arm: Enable FEAT_CSV2_2 for -cpu max
      target/arm: Enable FEAT_CSV3 for -cpu max
      target/arm: Enable FEAT_DGH for -cpu max
      target/arm: Define cortex-a76
      target/arm: Define neoverse-n1

From: Leif Lindholm <quic_llindhol@quicinc.com>

NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innovation Center (quicinc), so update
my email address to reflect this.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[Fixed commit message typo]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 .mailmap    | 3 ++-
 MAINTAINERS | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.mailmap b/.mailmap
index XXXXXXX..XXXXXXX 100644
--- a/.mailmap
+++ b/.mailmap
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
 Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
 James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
 Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
 Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
 Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
 SBSA-REF
 M: Radoslaw Biernacki <rad@semihalf.com>
 M: Peter Maydell <peter.maydell@linaro.org>
-R: Leif Lindholm <leif@nuviainc.com>
+R: Leif Lindholm <quic_llindhol@quicinc.com>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/sbsa-ref.c
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.

Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.

This will simplify cpreg registration for conditional arm features.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h |  11 +++
 target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
 2 files changed, 133 insertions(+), 56 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SVE                   = 1 << 14,
     /* Flag: Do not expose in gdb sysreg xml. */
     ARM_CP_NO_GDB                = 1 << 15,
+    /*
+     * Flags: If EL3 but not EL2...
+     *   - UNDEF: discard the cpreg,
+     *   -  KEEP: retain the cpreg as is,
+     *   -  C_NZ: set const on the cpreg, but retain resetvalue,
+     *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
+     * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+     */
+    ARM_CP_EL3_NO_EL2_UNDEF      = 1 << 16,
+    ARM_CP_EL3_NO_EL2_KEEP       = 1 << 17,
+    ARM_CP_EL3_NO_EL2_C_NZ       = 1 << 18,
 };
 
 /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
+      .access = PL2_RW,
+      .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
       .writefn = dacr_write, .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
-      .access = PL2_RW, .resetvalue = 0,
+      .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
       .type = ARM_CP_ALIAS,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .writefn = tlbimva_hyp_is_write },
     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2_write },
     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2_write },
     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2_write },
     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2is_write },
     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
 #ifndef CONFIG_USER_ONLY
     /* Unlike the other EL2-related AT operations, these must
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
       .access = PL2_W, .accessfn = at_s1e2_access,
-      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn = ats_write64 },
     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
       .access = PL2_W, .accessfn = at_s1e2_access,
-      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
+      .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn = ats_write64 },
     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .accessfn = access_tda,
-      .type = ARM_CP_NOP },
+      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
     /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
      * Channel but Linux may try to access this register. The 32-bit
      * alias is DBGDCCINT.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
    { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NOP },
    { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
    { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2is_write },
     { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2_write },
    { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_rvae2_write },
    { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_alle2is_write },
     { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
    { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
       .writefn = tlbi_aa64_alle1is_write },
     { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
     { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL2_RW, .accessfn = access_el3_aa32ns,
-              .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
+              .resetvalue = cpu->midr,
+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL2_RW, .resetvalue = cpu->midr,
+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
               .access = PL2_RW, .accessfn = access_el3_aa32ns,
-              .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
+              .resetvalue = vmpidr_def,
+              .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-              .access = PL2_RW,
-              .resetvalue = vmpidr_def,
+              .access = PL2_RW, .resetvalue = vmpidr_def,
+              .type = ARM_CP_EL3_NO_EL2_C_NZ,
               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
         };
         define_arm_cp_regs(cpu, vpidr_regs);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {
+    CPUARMState *env = &cpu->env;
     uint32_t key;
     ARMCPRegInfo *r2;
     bool is64 = r->type & ARM_CP_64BIT;
     bool ns = secstate & ARM_CP_SECSTATE_NS;
     int cp = r->cp;
-    bool isbanked;
     size_t name_len;
+    bool make_const;
 
     switch (state) {
     case ARM_CP_STATE_AA32:
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         }
     }
 
+    /*
+     * Eliminate registers that are not present because the EL is missing.
+     * Doing this here makes it easier to put all registers for a given
+     * feature into the same ARMCPRegInfo array and define them all at once.
+     */
+    make_const = false;
+    if (arm_feature(env, ARM_FEATURE_EL3)) {
+        /*
+         * An EL2 register without EL2 but with EL3 is (usually) RES0.
+         * See rule RJFFP in section D1.1.3 of DDI0487H.a.
+         */
+        int min_el = ctz32(r->access) / 2;
+        if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
+            if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
+                return;
+            }
+            make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
+        }
+    } else {
+        CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
+                                 ? PL2_RW : PL1_RW);
+        if ((r->access & max_el) == 0) {
+            return;
+        }
+    }
+
     /* Combine cpreg and name into one allocation. */
     name_len = strlen(name) + 1;
     r2 = g_malloc(sizeof(*r2) + name_len);
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
         r2->opaque = opaque;
     }
 
-    isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
-    if (isbanked) {
+    if (make_const) {
+        /* This should not have been a very special register to begin. */
+        int old_special = r2->type & ARM_CP_SPECIAL_MASK;
+        assert(old_special == 0 || old_special == ARM_CP_NOP);
         /*
-         * Register is banked (using both entries in array).
-         * Overwriting fieldoffset as the array is only used to define
-         * banked registers but later only fieldoffset is used.
+         * Set the special function to CONST, retaining the other flags.
+         * This is important for e.g. ARM_CP_SVE so that we still
+         * take the SVE trap if CPTR_EL3.EZ == 0.
          */
-        r2->fieldoffset = r->bank_fieldoffsets[ns];
-    }
+        r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
+        /*
+         * Usually, these registers become RES0, but there are a few
+         * special cases like VPIDR_EL2 which have a constant non-zero
+         * value with writes ignored.
+         */
+        if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
+            r2->resetvalue = 0;
+        }
+        /*
+         * ARM_CP_CONST has precedence, so removing the callbacks and
+         * offsets are not strictly necessary, but it is potentially
+         * less confusing to debug later.
+         */
+        r2->readfn = NULL;
+        r2->writefn = NULL;
+        r2->raw_readfn = NULL;
+        r2->raw_writefn = NULL;
+        r2->resetfn = NULL;
+        r2->fieldoffset = 0;
+        r2->bank_fieldoffsets[0] = 0;
+        r2->bank_fieldoffsets[1] = 0;
+    } else {
+        bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
 
-    if (state == ARM_CP_STATE_AA32) {
         if (isbanked) {
             /*
-             * If the register is banked then we don't need to migrate or
-             * reset the 32-bit instance in certain cases:
-             *
-             * 1) If the register has both 32-bit and 64-bit instances then we
-             *    can count on the 64-bit instance taking care of the
-             *    non-secure bank.
-             * 2) If ARMv8 is enabled then we can count on a 64-bit version
-             *    taking care of the secure bank.  This requires that separate
-             *    32 and 64-bit definitions are provided.
+             * Register is banked (using both entries in array).
+             * Overwriting fieldoffset as the array is only used to define
+             * banked registers but later only fieldoffset is used.
              */
-            if ((r->state == ARM_CP_STATE_BOTH && ns) ||
-                (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
+            r2->fieldoffset = r->bank_fieldoffsets[ns];
+        }
+        if (state == ARM_CP_STATE_AA32) {
+            if (isbanked) {
+                /*
+                 * If the register is banked then we don't need to migrate or
+                 * reset the 32-bit instance in certain cases:
+                 *
+                 * 1) If the register has both 32-bit and 64-bit instances
+                 *    then we can count on the 64-bit instance taking care
+                 *    of the non-secure bank.
+                 * 2) If ARMv8 is enabled then we can count on a 64-bit
+                 *    version taking care of the secure bank.  This requires
+                 *    that separate 32 and 64-bit definitions are provided.
+                 */
+                if ((r->state == ARM_CP_STATE_BOTH && ns) ||
+                    (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
+                    r2->type |= ARM_CP_ALIAS;
+                }
+            } else if ((secstate != r->secure) && !ns) {
+                /*
+                 * The register is not banked so we only want to allow
+                 * migration of the non-secure instance.
+                 */
                 r2->type |= ARM_CP_ALIAS;
             }
-        } else if ((secstate != r->secure) && !ns) {
-            /*
-             * The register is not banked so we only want to allow migration
-             * of the non-secure instance.
-             */
-            r2->type |= ARM_CP_ALIAS;
-        }
 
-        if (HOST_BIG_ENDIAN &&
-            r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
-            r2->fieldoffset += sizeof(uint32_t);
+            if (HOST_BIG_ENDIAN &&
+                r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
+                r2->fieldoffset += sizeof(uint32_t);
+            }
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
      * multiple times. Special registers (ie NOP/WFI) are
      * never migratable and not even raw-accessible.
      */
-    if (r->type & ARM_CP_SPECIAL_MASK) {
+    if (r2->type & ARM_CP_SPECIAL_MASK) {
         r2->type |= ARM_CP_NO_RAW;
     }
     if (((r->crm == CP_ANY) && crm != 0) ||
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.

This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that the virtualization cpregs
are now correctly not present.  This would be a migration compatibility
break, except that we have an existing bug in which migration of 32-bit
cpus with Security Extensions enabled does not work.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 158 ++++----------------------------------------
 1 file changed, 13 insertions(+), 145 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
 };
 
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
-    { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
-      .access = PL2_RW,
-      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
-    { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 6, .crm = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
-      .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
-      .resetvalue = 0 },
-    { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
-      .access = PL2_RW, .accessfn = access_tda,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
-      .type = ARM_CP_CONST,
-      .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
-      .access = PL2_RW, .resetvalue = 0 },
-};
-
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
-    { .name = "HCR2", .state = ARM_CP_STATE_AA32,
-      .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
-      .access = PL2_RW,
-      .type = ARM_CP_CONST, .resetvalue = 0 },
-};
-
 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, v8_idregs);
         define_arm_cp_regs(cpu, v8_cp_reginfo);
     }
-    if (arm_feature(env, ARM_FEATURE_EL2)) {
+
+    /*
+     * Register the base EL2 cpregs.
+     * Pre v8, these registers are implemented only as part of the
+     * Virtualization Extensions (EL2 present).  Beginning with v8,
+     * if EL2 is missing but EL3 is enabled, mostly these become
+     * RES0 from EL3, with some specific exceptions.
+     */
+    if (arm_feature(env, ARM_FEATURE_EL2)
+        || (arm_feature(env, ARM_FEATURE_EL3)
+            && arm_feature(env, ARM_FEATURE_V8))) {
         uint64_t vmpidr_def = mpidr_read_val(env);
         ARMCPRegInfo vpidr_regs[] = {
             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             };
             define_one_arm_cp_reg(cpu, &rvbar);
         }
-    } else {
-        /* If EL2 is missing but higher ELs are enabled, we need to
-         * register the no_el2 reginfos.
-         */
-        if (arm_feature(env, ARM_FEATURE_EL3)) {
-            /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
-             * of MIDR_EL1 and MPIDR_EL1.
-             */
-            ARMCPRegInfo vpidr_regs[] = {
-                { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
-                  .type = ARM_CP_CONST, .resetvalue = cpu->midr,
-                  .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
-                { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
-                  .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
-                  .type = ARM_CP_NO_RAW,
-                  .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
-            };
-            define_arm_cp_regs(cpu, vpidr_regs);
-            define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
-            if (arm_feature(env, ARM_FEATURE_V8)) {
-                define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
-            }
-        }
     }
+
+    /* Register the base EL3 cpregs. */
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         define_arm_cp_regs(cpu, el3_cp_reginfo);
         ARMCPRegInfo el3_regs[] = {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 55 ++++++++++++++-------------------------------
 1 file changed, 17 insertions(+), 38 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 }
 
-static const ARMCPRegInfo zcr_el1_reginfo = {
-    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL1_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
-    .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_el2_reginfo = {
-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL2_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
-    .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
-    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL2_RW, .type = ARM_CP_SVE,
-    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
-};
-
-static const ARMCPRegInfo zcr_el3_reginfo = {
-    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
-    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
-    .access = PL3_RW, .type = ARM_CP_SVE,
-    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
-    .writefn = zcr_write, .raw_writefn = raw_write
+static const ARMCPRegInfo zcr_reginfo[] = {
+    { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
+    { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
+    { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
+      .access = PL3_RW, .type = ARM_CP_SVE,
+      .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
+      .writefn = zcr_write, .raw_writefn = raw_write },
 };
 
 void hw_watchpoint_update(ARMCPU *cpu, int n)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (cpu_isar_feature(aa64_sve, cpu)) {
-        define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
-        if (arm_feature(env, ARM_FEATURE_EL2)) {
-            define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
-        } else {
-            define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
-        }
-        if (arm_feature(env, ARM_FEATURE_EL3)) {
-            define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
-        }
+        define_arm_cp_regs(cpu, zcr_reginfo);
     }
 
 #ifdef TARGET_AARCH64
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This register is present for either VHE or Debugv8p2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 };
 
+static const ARMCPRegInfo contextidr_el2 = {
+    .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+    .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+    .access = PL2_RW,
+    .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
 static const ARMCPRegInfo vhe_reginfo[] = {
-    { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
-      .access = PL2_RW,
-      .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
     }
 
+    if (cpu_isar_feature(aa64_vh, cpu) ||
+        cpu_isar_feature(aa64_debugv8p2, cpu)) {
+        define_one_arm_cp_reg(cpu, &contextidr_el2);
+    }
     if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
         define_arm_cp_regs(cpu, vhe_reginfo);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.

This will shortly be used from cpu_tcg.c also.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h |  6 ++++
 target/arm/cpu64.c     | 64 +++---------------------------------------
 target/arm/cpu_tcg.c   | 59 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+), 60 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
 #endif
 
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "hvf_arm.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
-#include "cpregs.h"
+#include "internals.h"
 
 
-#ifndef CONFIG_USER_ONLY
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
-    ARMCPU *cpu = env_archcpu(env);
-
-    /* Number of cores is in [25:24]; otherwise we RAZ */
-    return (cpu->core_count - 1) << 24;
-}
-#endif
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
-#ifndef CONFIG_USER_ONLY
-    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
-    { .name = "L2CTLR",
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
-      .writefn = arm_cp_write_ignore },
-#endif
-    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2ECTLR",
-      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUACTLR",
-      .cp = 15, .opc1 = 0, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUECTLR",
-      .cp = 15, .opc1 = 1, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "CPUMERRSR",
-      .cp = 15, .opc1 = 2, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    { .name = "L2MERRSR",
-      .cp = 15, .opc1 = 3, .crm = 15,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-};
-
 static void aarch64_a57_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 static void aarch64_a53_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 static void aarch64_a72_initfn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #endif
 #include "cpregs.h"
 
+#ifndef CONFIG_USER_ONLY
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    /* Number of cores is in [25:24]; otherwise we RAZ */
+    return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+      .access = PL1_RW, .readfn = l2ctlr_read,
+      .writefn = arm_cp_write_ignore },
+    { .name = "L2CTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+      .access = PL1_RW, .readfn = l2ctlr_read,
+      .writefn = arm_cp_write_ignore },
+    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2ECTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUACTLR",
+      .cp = 15, .opc1 = 0, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUECTLR",
+      .cp = 15, .opc1 = 1, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "CPUMERRSR",
+      .cp = 15, .opc1 = 2, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "L2MERRSR",
+      .cp = 15, .opc1 = 3, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
+#endif /* !CONFIG_USER_ONLY */
+
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
 1 file changed, 92 insertions(+), 59 deletions(-)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t t;
 
-    cortex_a15_initfn(obj);
+    /* aarch64_a57_initfn, advertising none of the aarch64 features */
+    cpu->dtb_compatible = "arm,cortex-a57";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x411fd070;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10101105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0;
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
-    /* old-style VFP short-vector support */
-    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+    /* Add additional features supported by QEMU */
+    t = cpu->isar.id_isar5;
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    cpu->isar.id_isar5 = t;
+
+    t = cpu->isar.id_isar6;
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    cpu->isar.id_isar6 = t;
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    t = cpu->isar.id_mmfr3;
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    cpu->isar.id_mmfr3 = t;
+
+    t = cpu->isar.id_mmfr4;
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    cpu->isar.id_mmfr4 = t;
+
+    t = cpu->isar.id_pfr0;
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    cpu->isar.id_pfr0 = t;
+
+    t = cpu->isar.id_pfr2;
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    cpu->isar.id_pfr2 = t;
 
 #ifdef CONFIG_USER_ONLY
     /*
-     * We don't set these in system emulation mode for the moment,
-     * since we don't correctly set (all of) the ID registers to
-     * advertise them.
+     * Break with true ARMv8 and add back old-style VFP short-vector support.
+     * Only do this for user-mode, where -cpu max is the default, so that
+     * older v6 and v7 programs are more likely to work without adjustment.
      */
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    {
-        uint32_t t;
-
-        t = cpu->isar.id_isar5;
-        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-        cpu->isar.id_isar5 = t;
-
-        t = cpu->isar.id_isar6;
-        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-        t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-        t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-        cpu->isar.id_isar6 = t;
-
-        t = cpu->isar.mvfr1;
-        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-        cpu->isar.mvfr1 = t;
-
-        t = cpu->isar.mvfr2;
-        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-        cpu->isar.mvfr2 = t;
-
-        t = cpu->isar.id_mmfr3;
-        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-        cpu->isar.id_mmfr3 = t;
-
-        t = cpu->isar.id_mmfr4;
-        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-        cpu->isar.id_mmfr4 = t;
-
-        t = cpu->isar.id_pfr0;
-        t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-        cpu->isar.id_pfr0 = t;
-
-        t = cpu->isar.id_pfr2;
-        t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-        cpu->isar.id_pfr2 = t;
-    }
-#endif /* CONFIG_USER_ONLY */
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+#endif
 }
 #endif /* !TARGET_AARCH64 */
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.

Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
     cpu->isar.id_pfr2 = t;
 
+    t = cpu->isar.id_dfr0;
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    cpu->isar.id_dfr0 = t;
+
 #ifdef CONFIG_USER_ONLY
     /*
      * Break with true ARMv8 and add back old-style VFP short-vector support.
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h |   2 +
 target/arm/cpu64.c     |  50 +-----------------
 target/arm/cpu_tcg.c   | 114 ++++++++++++++++++++++-------------------
 3 files changed, 65 insertions(+), 101 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+void aa32_max_features(ARMCPU *cpu);
+
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     uint64_t t;
-    uint32_t u;
 
     if (kvm_enabled() || hvf_enabled()) {
         /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
     cpu->isar.id_aa64zfr0 = t;
 
-    /* Replicate the same data to the 32-bit id registers.  */
-    u = cpu->isar.id_isar5;
-    u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
-    u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
-    u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
-    u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
-    u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
-    u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
-    cpu->isar.id_isar5 = u;
-
-    u = cpu->isar.id_isar6;
-    u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
-    u = FIELD_DP32(u, ID_ISAR6, DP, 1);
-    u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
-    u = FIELD_DP32(u, ID_ISAR6, SB, 1);
-    u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
-    u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
-    u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
-    cpu->isar.id_isar6 = u;
-
-    u = cpu->isar.id_pfr0;
-    u = FIELD_DP32(u, ID_PFR0, DIT, 1);
-    cpu->isar.id_pfr0 = u;
-
-    u = cpu->isar.id_pfr2;
-    u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
-    cpu->isar.id_pfr2 = u;
-
-    u = cpu->isar.id_mmfr3;
-    u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
-    cpu->isar.id_mmfr3 = u;
-
-    u = cpu->isar.id_mmfr4;
-    u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
-    u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
-    cpu->isar.id_mmfr4 = u;
-
     t = cpu->isar.id_aa64dfr0;
     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
     cpu->isar.id_aa64dfr0 = t;
 
-    u = cpu->isar.id_dfr0;
-    u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-    cpu->isar.id_dfr0 = u;
-
-    u = cpu->isar.mvfr1;
-    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
-    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
-    cpu->isar.mvfr1 = u;
+    /* Replicate the same data to the 32-bit id registers.  */
+    aa32_max_features(cpu);
 
 #ifdef CONFIG_USER_ONLY
     /*
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #endif
 #include "cpregs.h"
 
+
+/* Share AArch32 -cpu max features with AArch64. */
+void aa32_max_features(ARMCPU *cpu)
+{
+    uint32_t t;
+
+    /* Add additional features supported by QEMU */
+    t = cpu->isar.id_isar5;
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    cpu->isar.id_isar5 = t;
+
+    t = cpu->isar.id_isar6;
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    cpu->isar.id_isar6 = t;
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    t = cpu->isar.id_mmfr3;
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    cpu->isar.id_mmfr3 = t;
+
+    t = cpu->isar.id_mmfr4;
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    cpu->isar.id_mmfr4 = t;
+
+    t = cpu->isar.id_pfr0;
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    cpu->isar.id_pfr0 = t;
+
+    t = cpu->isar.id_pfr2;
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    cpu->isar.id_pfr2 = t;
+
+    t = cpu->isar.id_dfr0;
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    cpu->isar.id_dfr0 = t;
+}
+
 #ifndef CONFIG_USER_ONLY
 static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    uint32_t t;
 
     /* aarch64_a57_initfn, advertising none of the aarch64 features */
     cpu->dtb_compatible = "arm,cortex-a57";
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
-    /* Add additional features supported by QEMU */
-    t = cpu->isar.id_isar5;
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-    cpu->isar.id_isar5 = t;
-
-    t = cpu->isar.id_isar6;
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
-    cpu->isar.id_isar6 = t;
-
-    t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-    cpu->isar.mvfr1 = t;
-
-    t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-    cpu->isar.mvfr2 = t;
-
-    t = cpu->isar.id_mmfr3;
-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-    cpu->isar.id_mmfr3 = t;
-
-    t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-    cpu->isar.id_mmfr4 = t;
-
-    t = cpu->isar.id_pfr0;
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
-    cpu->isar.id_pfr0 = t;
-
-    t = cpu->isar.id_pfr2;
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
-    cpu->isar.id_pfr2 = t;
-
-    t = cpu->isar.id_dfr0;
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-    cpu->isar.id_dfr0 = t;
+    aa32_max_features(cpu);
 
 #ifdef CONFIG_USER_ONLY
     /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu64.c   | 100 +++++++++++++++++++++----------------------
 target/arm/cpu_tcg.c |  48 ++++++++++-----------
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     cpu->midr = t;
 
     t = cpu->isar.id_aa64isar0;
-    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
     t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
-    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
-    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
-    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
+    t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
+    t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
+    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
+    t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
+    t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
     cpu->isar.id_aa64isar0 = t;
 
     t = cpu->isar.id_aa64isar1;
-    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
-    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
-    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
+    t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
+    t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
+    t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
+    t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
+    t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
+    t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
     cpu->isar.id_aa64isar1 = t;
 
     t = cpu->isar.id_aa64pfr0;
+    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
+    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
-    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
+    t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
     cpu->isar.id_aa64pfr0 = t;
 
     t = cpu->isar.id_aa64pfr1;
-    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
-    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
+    t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
+    t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
     /*
      * Begin with full support for MTE. This will be downgraded to MTE=0
      * during realize if the board provides no tag memory, much like
      * we do for EL2 with the virtualization=on property.
      */
-    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
+    t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
     cpu->isar.id_aa64pfr1 = t;
 
     t = cpu->isar.id_aa64mmfr0;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     cpu->isar.id_aa64mmfr0 = t;
 
     t = cpu->isar.id_aa64mmfr1;
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
-    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
-    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
-    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
+    t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
+    t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2);      /* FEAT_PAN2 */
+    t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
     cpu->isar.id_aa64mmfr1 = t;
 
     t = cpu->isar.id_aa64mmfr2;
-    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
-    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
-    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
-    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
-    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
-    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
+    t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
+    t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
+    t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
+    t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
+    t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
+    t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
     cpu->isar.id_aa64mmfr2 = t;
 
     t = cpu->isar.id_aa64zfr0;
     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
-    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
-    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
+    t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
+    t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
+    t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
+    t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
+    t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
     cpu->isar.id_aa64zfr0 = t;
 
     t = cpu->isar.id_aa64dfr0;
-    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+    t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
     cpu->isar.id_aa64dfr0 = t;
 
     /* Replicate the same data to the 32-bit id registers.  */
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
 
     /* Add additional features supported by QEMU */
     t = cpu->isar.id_isar5;
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
     t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
     cpu->isar.id_isar5 = t;
 
     t = cpu->isar.id_isar6;
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
     cpu->isar.id_isar6 = t;
 
     t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
     cpu->isar.mvfr1 = t;
 
     t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
     cpu->isar.mvfr2 = t;
 
     t = cpu->isar.id_mmfr3;
-    t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+    t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX*/
     cpu->isar.id_mmfr4 = t;
 
     t = cpu->isar.id_pfr0;
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
     cpu->isar.id_pfr0 = t;
 
     t = cpu->isar.id_pfr2;
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
     cpu->isar.id_pfr2 = t;
 
     t = cpu->isar.id_dfr0;
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 5);       /* FEAT_PMUv3p4 */
     cpu->isar.id_dfr0 = t;
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          */
         unset_feature(env, ARM_FEATURE_EL3);
 
-        /* Disable the security extension feature bits in the processor feature
-         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
+        /*
+         * Disable the security extension feature bits in the processor
+         * feature registers as well.
          */
-        cpu->isar.id_pfr1 &= ~0xf0;
-        cpu->isar.id_aa64pfr0 &= ~0xf000;
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL3, 0);
     }
 
     if (!cpu->has_el2) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
-        /* Disable the hypervisor feature bits in the processor feature
-         * registers if we don't have EL2. These are id_pfr1[15:12] and
-         * id_aa64pfr0_el1[11:8].
+        /*
+         * Disable the hypervisor feature bits in the processor feature
+         * registers if we don't have EL2.
          */
-        cpu->isar.id_aa64pfr0 &= ~0xf00;
-        cpu->isar.id_pfr1 &= ~0xf000;
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL2, 0);
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
+                                       ID_PFR1, VIRTUALIZATION, 0);
     }
 
 #ifndef CONFIG_USER_ONLY
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE.  The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu.c              | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 2 ++
 4 files changed, 5 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU.  Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 2 +-
 target/arm/cpu_tcg.c          | 4 ++--
 3 files changed, 4 insertions(+), 3 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Add only the system registers required to implement zero error
records.  This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.

Add the EL2 registers required for injecting virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  5 +++
 target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0.  */
         uint64_t gcr_el1;
         uint64_t rgsr_el1;
+
+        /* Minimal RAS registers */
+        uint64_t disr_el1;
+        uint64_t vdisr_el2;
+        uint64_t vsesr_el2;
     } cp15;
 
     struct {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
 };
 
+/*
+ * Check for traps to RAS registers, which are controlled
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
+ */
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+        return env->cp15.vdisr_el2;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+        return 0; /* RAZ/WI */
+    }
+    return env->cp15.disr_el1;
+}
+
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
+{
+    int el = arm_current_el(env);
+
+    if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
+        env->cp15.vdisr_el2 = val;
+        return;
+    }
+    if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
+        return; /* RAZ/WI */
+    }
+    env->cp15.disr_el1 = val;
+}
+
+/*
+ * Minimal RAS implementation with no Error Records.
+ * Which means that all of the Error Record registers:
+ *   ERXADDR_EL1
+ *   ERXCTLR_EL1
+ *   ERXFR_EL1
+ *   ERXMISC0_EL1
+ *   ERXMISC1_EL1
+ *   ERXMISC2_EL1
+ *   ERXMISC3_EL1
+ *   ERXPFGCDN_EL1  (RASv1p1)
+ *   ERXPFGCTL_EL1  (RASv1p1)
+ *   ERXPFGF_EL1    (RASv1p1)
+ *   ERXSTATUS_EL1
+ * and
+ *   ERRSELR_EL1
+ * may generate UNDEFINED, which is the effect we get by not
+ * listing them at all.
+ */
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
+    { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
+      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
+      .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
+    { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
+      .access = PL1_R, .accessfn = access_terr,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
+    { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
+};
+
 /* Return the exception level to which exceptions should be taken
  * via SVEAccessTrap.  If an exception should be routed through
  * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_ssbs, cpu)) {
         define_one_arm_cp_reg(cpu, &ssbs_reginfo);
     }
+    if (cpu_isar_feature(any_ras, cpu)) {
+        define_arm_cp_regs(cpu, minimal_ras_reginfo);
+    }
 
     if (cpu_isar_feature(aa64_vh, cpu) ||
         cpu_isar_feature(aa64_debugv8p2, cpu)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
         valid_mask &= ~SCR_NET;
 
+        if (cpu_isar_feature(aa64_ras, cpu)) {
+            valid_mask |= SCR_TERR;
+        }
         if (cpu_isar_feature(aa64_lor, cpu)) {
             valid_mask |= SCR_TLOR;
         }
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
+        if (cpu_isar_feature(aa32_ras, cpu)) {
+            valid_mask |= SCR_TERR;
+        }
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         if (cpu_isar_feature(aa64_vh, cpu)) {
             valid_mask |= HCR_E2H;
         }
+        if (cpu_isar_feature(aa64_ras, cpu)) {
+            valid_mask |= HCR_TERR | HCR_TEA;
+        }
         if (cpu_isar_feature(aa64_lor, cpu)) {
             valid_mask |= HCR_TLOR;
         }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |  2 ++
 target/arm/internals.h |  8 ++++++++
 target/arm/syndrome.h  |  5 +++++
 target/arm/cpu.c       | 38 +++++++++++++++++++++++++++++++++++++-
 target/arm/helper.c    | 40 +++++++++++++++++++++++++++++++++++++++-
 5 files changed, 91 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define EXCP_LSERR          21   /* v8M LSERR SecureFault */
 #define EXCP_UNALIGNED      22   /* v7M UNALIGNED UsageFault */
 #define EXCP_DIVBYZERO      23   /* v7M DIVBYZERO UsageFault */
+#define EXCP_VSERR          24
 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
 
 #define ARMV7M_EXCP_RESET   1
@@ -XXX,XX +XXX,XX @@ enum {
 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
 #define CPU_INTERRUPT_VIRQ  CPU_INTERRUPT_TGT_EXT_2
 #define CPU_INTERRUPT_VFIQ  CPU_INTERRUPT_TGT_EXT_3
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
 
 /* The usual mapping for an AArch64 system register to its AArch32
  * counterpart is for the 32 bit world to have access to the lower
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
  */
 void arm_cpu_update_vfiq(ARMCPU *cpu);
 
+/**
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
+ *
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
+ * following a change to the HCR_EL2.VSE bit.
+ */
+void arm_cpu_update_vserr(ARMCPU *cpu);
+
 /**
  * arm_mmu_idx_el:
  * @env: The cpu environment
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
     return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 }
 
+static inline uint32_t syn_serror(uint32_t extra)
+{
+    return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
+}
+
 #endif /* TARGET_ARM_SYNDROME_H */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
     return (cpu->power_state != PSCI_OFF)
         && cs->interrupt_request &
         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
-         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
+         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
          | CPU_INTERRUPT_EXITTB);
 }
 
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
             return false;
         }
         return !(env->daif & PSTATE_I);
+    case EXCP_VSERR:
+        if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
+            /* VIRQs are only taken when hypervized.  */
+            return false;
+        }
+        return !(env->daif & PSTATE_A);
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
             goto found;
         }
     }
+    if (interrupt_request & CPU_INTERRUPT_VSERR) {
+        excp_idx = EXCP_VSERR;
+        target_el = 1;
+        if (arm_excp_unmasked(cs, excp_idx, target_el,
+                              cur_el, secure, hcr_el2)) {
+            /* Taking a virtual abort clears HCR_EL2.VSE */
+            env->cp15.hcr_el2 &= ~HCR_VSE;
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+            goto found;
+        }
+    }
     return false;
 
  found:
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
     }
 }
 
+void arm_cpu_update_vserr(ARMCPU *cpu)
+{
+    /*
+     * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
+     */
+    CPUARMState *env = &cpu->env;
+    CPUState *cs = CPU(cpu);
+
+    bool new_state = env->cp15.hcr_el2 & HCR_VSE;
+
+    if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
+        if (new_state) {
+            cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
+        } else {
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
+        }
+    }
+}
+
 #ifndef CONFIG_USER_ONLY
 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
         }
     }
 
-    /* External aborts are not possible in QEMU so A bit is always clear */
+    if (hcr_el2 & HCR_AMO) {
+        if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
+            ret |= CPSR_A;
+        }
+    }
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
     g_assert(qemu_mutex_iothread_locked());
     arm_cpu_update_virq(cpu);
     arm_cpu_update_vfiq(cpu);
+    arm_cpu_update_vserr(cpu);
 }
 
 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
             [EXCP_LSERR] = "v8M LSERR UsageFault",
             [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
             [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
+            [EXCP_VSERR] = "Virtual SERR",
         };
 
         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
         mask = CPSR_A | CPSR_I | CPSR_F;
         offset = 4;
         break;
+    case EXCP_VSERR:
+        {
+            /*
+             * Note that this is reported as a data abort, but the DFAR
+             * has an UNKNOWN value.  Construct the SError syndrome from
+             * AET and ExT fields.
+             */
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
+
+            if (extended_addresses_enabled(env)) {
+                env->exception.fsr = arm_fi_to_lfsc(&fi);
+            } else {
+                env->exception.fsr = arm_fi_to_sfsc(&fi);
+            }
+            env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
+            A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
+            qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
+                          env->exception.fsr);
+
+            new_mode = ARM_CPU_MODE_ABT;
+            addr = 0x10;
+            mask = CPSR_A | CPSR_I;
+            offset = 8;
+        }
+        break;
     case EXCP_SMC:
         new_mode = ARM_CPU_MODE_MON;
         addr = 0x08;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     case EXCP_VFIQ:
         addr += 0x100;
         break;
+    case EXCP_VSERR:
+        addr += 0x180;
+        /* Construct the SError syndrome from IDS and ISS fields. */
+        env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
+        env->cp15.esr_el[new_el] = env->exception.syndrome;
+        break;
     default:
         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Check for and defer any pending virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  1 +
 target/arm/a32.decode      | 16 ++++++++------
 target/arm/t32.decode      | 18 ++++++++--------
 target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c | 17 +++++++++++++++
 target/arm/translate.c     | 23 ++++++++++++++++++++
 6 files changed, 103 insertions(+), 15 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
 DEF_HELPER_1(yield, void, env)
 DEF_HELPER_1(pre_hvc, void, env)
 DEF_HELPER_2(pre_smc, void, env, i32)
+DEF_HELPER_1(vesb, void, env)
 
 DEF_HELPER_3(cpsr_write, void, env, i32, i32)
 DEF_HELPER_2(cpsr_write_eret, void, env, i32)
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -XXX,XX +XXX,XX @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
 
 {
   {
-    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
-    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
-    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
+    [
+      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
+      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
+      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 
-    # TODO: Implement SEV, SEVL; may help SMP performance.
-    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
-    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
+      # TODO: Implement SEV, SEVL; may help SMP performance.
+      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
+      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
+
+      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
+    ]
 
     # The canonical nop ends in 00000000, but the whole of the
     # rest of the space executes as nop if otherwise unsupported.
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
   [
     # Hints, and CPS
     {
-      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
-      WFE        1111 0011 1010 1111 1000 0000 0000 0010
-      WFI        1111 0011 1010 1111 1000 0000 0000 0011
+      [
+        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
+        WFE      1111 0011 1010 1111 1000 0000 0000 0010
+        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 
-      # TODO: Implement SEV, SEVL; may help SMP performance.
-      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
-      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
+        # TODO: Implement SEV, SEVL; may help SMP performance.
+        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
+        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 
-      # For M-profile minimal-RAS ESB can be a NOP, which is the
-      # default behaviour since it is in the hint space.
-      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
+        ESB      1111 0011 1010 1111 1000 0000 0001 0000
+      ]
 
       # The canonical nop ends in 0000 0000, but the whole rest
       # of the space is "reserved hint, behaves as nop".
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                      access_type, mmu_idx, ra);
     }
 }
+
+/*
+ * This function corresponds to AArch64.vESBOperation().
+ * Note that the AArch32 version is not functionally different.
+ */
+void HELPER(vesb)(CPUARMState *env)
+{
+    /*
+     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
+     * and will return HCR_EL2.VSE == 0, so nothing happens.
+     */
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
+    bool pending = enabled && (hcr & HCR_VSE);
+    bool masked  = (env->daif & PSTATE_A);
+
+    /* If VSE pending and masked, defer the exception.  */
+    if (pending && masked) {
+        uint32_t syndrome;
+
+        if (arm_el_is_aa64(env, 1)) {
+            /* Copy across IDS and ISS from VSESR. */
+            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
+        } else {
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
+
+            if (extended_addresses_enabled(env)) {
+                syndrome = arm_fi_to_lfsc(&fi);
+            } else {
+                syndrome = arm_fi_to_sfsc(&fi);
+            }
+            /* Copy across AET and ExT from VSESR. */
+            syndrome |= env->cp15.vsesr_el2 & 0xd000;
+        }
+
+        /* Set VDISR_EL2.A along with the syndrome. */
+        env->cp15.vdisr_el2 = syndrome | (1u << 31);
+
+        /* Clear pending virtual SError */
+        env->cp15.hcr_el2 &= ~HCR_VSE;
+        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
+    }
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
             gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
         }
         break;
+    case 0b10000: /* ESB */
+        /* Without RAS, we must implement this as NOP. */
+        if (dc_isar_feature(aa64_ras, s)) {
+            /*
+             * QEMU does not have a source of physical SErrors,
+             * so we are only concerned with virtual SErrors.
+             * The pseudocode in the ARM for this case is
+             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+             *      AArch64.vESBOperation();
+             * Most of the condition can be evaluated at translation time.
+             * Test for EL2 present, and defer test for SEL2 to runtime.
+             */
+            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+                gen_helper_vesb(cpu_env);
+            }
+        }
+        break;
     case 0b11000: /* PACIAZ */
         if (s->pauth_active) {
             gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
     return true;
 }
 
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
+{
+    /*
+     * For M-profile, minimal-RAS ESB can be a NOP.
+     * Without RAS, we must implement this as NOP.
+     */
+    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
+        /*
+         * QEMU does not have a source of physical SErrors,
+         * so we are only concerned with virtual SErrors.
+         * The pseudocode in the ARM for this case is
+         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+         *      AArch32.vESBOperation();
+         * Most of the condition can be evaluated at translation time.
+         * Test for EL2 present, and defer test for SEL2 to runtime.
+         */
+        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+            gen_helper_vesb(cpu_env);
+        }
+    }
+    return true;
+}
+
 static bool trans_NOP(DisasContext *s, arg_NOP *a)
 {
     return true;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 2 files changed, 2 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns branch speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst |  3 ++
 target/arm/cpu.h              | 16 +++++++++
 target/arm/cpu.c              |  5 +++
 target/arm/cpu64.c            |  3 +-
 target/arm/helper.c           | 61 ++++++++++++++++++++++++++++++++++-
 5 files changed, 86 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_BF16 (AArch64 BFloat16 instructions)
 - FEAT_BTI (Branch Target Identification)
 - FEAT_CSV2 (Cache speculation variant 2)
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
 - FEAT_DIT (Data Independent Timing instructions)
 - FEAT_DPB (DC CVAP instruction)
 - FEAT_Debugv8p2 (Debug changes for v8.2)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         ARMPACKey apdb;
         ARMPACKey apga;
     } keys;
+
+    uint64_t scxtnum_el[4];
 #endif
 
 #if defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
 #define SCTLR_WXN     (1U << 19)
 #define SCTLR_ST      (1U << 20) /* up to ??, RAZ in v6 */
 #define SCTLR_UWXN    (1U << 20) /* v7 onward, AArch32 only */
+#define SCTLR_TSCXT   (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
 #define SCTLR_FI      (1U << 21) /* up to v7, v8 RES0 */
 #define SCTLR_IESB    (1U << 21) /* v8.2-IESB, AArch64 only */
 #define SCTLR_U       (1U << 22) /* up to v6, RAO in v7 */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
 }
 
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
+{
+    int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
+    if (key >= 2) {
+        return true;      /* FEAT_CSV2_2 */
+    }
+    if (key == 1) {
+        key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
+        return key >= 2;  /* FEAT_CSV2_1p2 */
+    }
+    return false;
+}
+
 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
              */
             env->cp15.gcr_el1 = 0x1ffff;
         }
+        /*
+         * Disable access to SCXTNUM_EL0 from CSV2_1p2.
+         * This is not yet exposed from the Linux kernel in any way.
+         */
+        env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
 #else
         /* Reset into the highest available EL */
         if (arm_feature(env, ARM_FEATURE_EL3)) {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1);      /* FEAT_CSV2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr0 = t;
 
     t = cpu->isar.id_aa64pfr1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      * we do for EL2 with the virtualization=on property.
      */
     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
+    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr1 = t;
 
     t = cpu->isar.id_aa64mmfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= SCR_ATA;
         }
+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+            valid_mask |= SCR_ENSCXT;
+        }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
         if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
         }
+        if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+            valid_mask |= HCR_ENSCXT;
+        }
     }
 
     /* Clear RES0 bits.  */
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
         { K(3, 0,  5, 6, 0), K(3, 4,  5, 6, 0), K(3, 5, 5, 6, 0),
           "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
 
+        { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
+          "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
+          isar_feature_aa64_scxtnum },
+
         /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
         /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
     };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
     },
 };
 
-#endif
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
+                                     bool isread)
+{
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    int el = arm_current_el(env);
+
+    if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
+        if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
+            if (hcr & HCR_TGE) {
+                return CP_ACCESS_TRAP_EL2;
+            }
+            return CP_ACCESS_TRAP;
+        }
+    } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3
+        && arm_feature(env, ARM_FEATURE_EL3)
+        && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static const ARMCPRegInfo scxtnum_reginfo[] = {
+    { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL0_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
+    { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL1_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
+    { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL2_RW, .accessfn = access_scxtnum,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
+    { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
+      .access = PL3_RW,
+      .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
+};
+#endif /* TARGET_AARCH64 */
 
 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
                                      bool isread)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     }
+
+    if (cpu_isar_feature(aa64_scxtnum, cpu)) {
+        define_arm_cp_regs(cpu, scxtnum_reginfo);
+    }
 #endif
 
     if (cpu_isar_feature(any_predinv, cpu)) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns cache speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This extension concerns not merging memory access, which TCG does
not implement.  Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/translate-a64.c    | 1 +
 3 files changed, 3 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

Enable the a76 for virt and sbsa board use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/sbsa-ref.c        |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a53`` (64-bit)
 - ``cortex-a57`` (64-bit)
 - ``cortex-a72`` (64-bit)
+- ``cortex-a76`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
 static const char * const valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("max"),
 };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a53"),
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("a64fx"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
+static void aarch64_a76_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a76";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444C004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0b1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.18 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+    /* From B2.93 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+}
+
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
+    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable the n1 for virt and sbsa board use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/sbsa-ref.c        |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 66 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a76`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
+- ``neoverse-n1`` (64-bit)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
 
 Note that the default is ``cortex-a15``, so for an AArch64 guest you must
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
+    ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("max"),
 };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("a64fx"),
+    ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
     cpu->isar.mvfr2 = 0x00000043;
 }
 
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,neoverse-n1";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444c004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd0c1;          /* r4p1 */
+    cpu->revidr = 0;
+
+    /* From B2.23 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+    /* From B2.98 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+}
+
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+    { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
     { .name = "host",               .initfn = aarch64_host_initfn },
-- 
2.25.1

From: Leif Lindholm <quic_llindhol@quicinc.com>

The sbsa-ref machine is continuously evolving. Some of the changes we
want to make in the near future, to align with real components (e.g.
the GIC-700), will break compatibility for existing firmware.

Introduce two new properties to the DT generated on machine generation:
- machine-version-major
  To be incremented when a platform change makes the machine
  incompatible with existing firmware.
- machine-version-minor
  To be incremented when functionality is added to the machine
  without causing incompatibility with existing firmware.
  to be reset to 0 when machine-version-major is incremented.

This versioning scheme is *neither*:
- A QEMU versioned machine type; a given version of QEMU will emulate
  a given version of the platform.
- A reflection of level of SBSA (now SystemReady SR) support provided.

The version will increment on guest-visible functional changes only,
akin to a revision ID register found on a physical platform.

These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 
+    /*
+     * This versioning scheme is for informing platform fw only. It is neither:
+     * - A QEMU versioned machine type; a given version of QEMU will emulate
+     *   a given version of the platform.
+     * - A reflection of level of SBSA (now SystemReady SR) support provided.
+     *
+     * machine-version-major: updated when changes breaking fw compatibility
+     *                        are introduced.
+     * machine-version-minor: updated when features are added that don't break
+     *                        fw compatibility.
+     */
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
+
     if (ms->numa_state->have_numa_distance) {
         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
         uint32_t *matrix = g_malloc0(size);
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:

* hw/core/machine.c::machine_set_cpu_numa_node() to associate
    CPU with its NUMA node.

* hw/core/machine.c::machine_numa_finish_cpu_init() to record
    CPU slots with no NUMA mapping set.

* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
    cluster-id.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 qapi/machine.json          |  6 ++++--
 hw/core/machine-hmp-cmds.c |  4 ++++
 hw/core/machine.c          | 16 ++++++++++++++++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/qapi/machine.json b/qapi/machine.json
index XXXXXXX..XXXXXXX 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -XXX,XX +XXX,XX @@
 # @node-id: NUMA node ID the CPU belongs to
 # @socket-id: socket number within node/board the CPU belongs to
 # @die-id: die number within socket the CPU belongs to (since 4.1)
-# @core-id: core number within die the CPU belongs to
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
+# @core-id: core number within cluster the CPU belongs to
 # @thread-id: thread number within core the CPU belongs to
 #
-# Note: currently there are 5 properties that could be present
+# Note: currently there are 6 properties that could be present
 #       but management should be prepared to pass through other
 #       properties with device_add command to allow for future
 #       interface extension. This also requires the filed names to be kept in
@@ -XXX,XX +XXX,XX @@
   'data': { '*node-id': 'int',
             '*socket-id': 'int',
             '*die-id': 'int',
+            '*cluster-id': 'int',
             '*core-id': 'int',
             '*thread-id': 'int'
   }
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine-hmp-cmds.c
+++ b/hw/core/machine-hmp-cmds.c
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
         if (c->has_die_id) {
             monitor_printf(mon, "    die-id: \"%" PRIu64 "\"\n", c->die_id);
         }
+        if (c->has_cluster_id) {
+            monitor_printf(mon, "    cluster-id: \"%" PRIu64 "\"\n",
+                           c->cluster_id);
+        }
         if (c->has_core_id) {
             monitor_printf(mon, "    core-id: \"%" PRIu64 "\"\n", c->core_id);
         }
diff --git a/hw/core/machine.c b/hw/core/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
             return;
         }
 
+        if (props->has_cluster_id && !slot->props.has_cluster_id) {
+            error_setg(errp, "cluster-id is not supported");
+            return;
+        }
+
         if (props->has_socket_id && !slot->props.has_socket_id) {
             error_setg(errp, "socket-id is not supported");
             return;
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
                 continue;
         }
 
+        if (props->has_cluster_id &&
+            props->cluster_id != slot->props.cluster_id) {
+                continue;
+        }
+
         if (props->has_die_id && props->die_id != slot->props.die_id) {
                 continue;
         }
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
         }
         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
     }
+    if (cpu->props.has_cluster_id) {
+        if (s->len) {
+            g_string_append_printf(s, ", ");
+        }
+        g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
+    }
     if (cpu->props.has_core_id) {
         if (s->len) {
             g_string_append_printf(s, ", ");
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

The CPU topology isn't enabled on arm/virt machine yet, but we're
going to do it in next patch. After the CPU topology is enabled by
next patch, "thread-id=1" becomes invalid because the CPU core is
preferred on arm/virt machine. It means these two CPUs have 0/1
as their core IDs, but their thread IDs are all 0. It will trigger
test failure as the following message indicates:

[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test  ERROR
  1.48s   killed by signal 6 SIGABRT
  >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
      QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon         \
      QTEST_QEMU_BINARY=./qemu-system-aarch64                                       \
      QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83                                  \
      /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
  ――――――――――――――――――――――――――――――――――――――――――――――
  stderr:
  qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found

This fixes the issue by providing comprehensive SMP configurations
in aarch64_numa_cpu(). The SMP configurations aren't used before
the CPU topology is enabled in next patch.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/numa-test.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Gavin Shan <gshan@redhat.com>

Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.

This takes account of SMP configuration when the CPU topology
is populated. The die ID for the given CPU isn't assigned since
it's not supported on arm/virt machine. Besides, the used SMP
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
to avoid testing failure

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-4-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
     int n;
     unsigned int max_cpus = ms->smp.max_cpus;
     VirtMachineState *vms = VIRT_MACHINE(ms);
+    MachineClass *mc = MACHINE_GET_CLASS(vms);
 
     if (ms->possible_cpus) {
         assert(ms->possible_cpus->len == max_cpus);
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
         ms->possible_cpus->cpus[n].type = ms->cpu_type;
         ms->possible_cpus->cpus[n].arch_id =
             virt_cpu_mp_affinity(vms, n);
+
+        assert(!mc->smp_props.dies_supported);
+        ms->possible_cpus->cpus[n].props.has_socket_id = true;
+        ms->possible_cpus->cpus[n].props.socket_id =
+            n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
+        ms->possible_cpus->cpus[n].props.has_cluster_id = true;
+        ms->possible_cpus->cpus[n].props.cluster_id =
+            (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
+        ms->possible_cpus->cpus[n].props.has_core_id = true;
+        ms->possible_cpus->cpus[n].props.core_id =
+            (n / ms->smp.threads) % ms->smp.cores;
         ms->possible_cpus->cpus[n].props.has_thread_id = true;
-        ms->possible_cpus->cpus[n].props.thread_id = n;
+        ms->possible_cpus->cpus[n].props.thread_id =
+            n % ms->smp.threads;
     }
     return ms->possible_cpus;
 }
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

In aarch64_numa_cpu(), the CPU and NUMA association is something
like below. Two threads in the same core/cluster/socket are
associated with two individual NUMA nodes, which is unreal as
Igor Mammedov mentioned. We don't expect the association to break
NUMA-to-socket boundary, which matches with the real world.

NUMA-node  socket  cluster   core   thread
    ------------------------------------------
        0       0        0        0      0
        1       0        0        0      1

This corrects the topology for CPUs and their association with
NUMA nodes. After this patch is applied, the CPU and NUMA
association becomes something like below, which looks real.
Besides, socket/cluster/core/thread IDs are all checked when
the NUMA node IDs are verified. It helps to check if the CPU
topology is properly populated or not.

NUMA-node  socket  cluster   core   thread
    ------------------------------------------
       0        1        0        0       0
       1        0        0        0       0

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-5-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/numa-test.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/numa-test.c
+++ b/tests/qtest/numa-test.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
     g_autofree char *cli = NULL;
 
     cli = make_cli(data, "-machine "
-        "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
+        "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
         "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
-        "-numa cpu,node-id=1,thread-id=0 "
-        "-numa cpu,node-id=0,thread-id=1");
+        "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
+        "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
     qts = qtest_init(cli);
     cpus = get_cpus(qts, &resp);
     g_assert(cpus);
 
     while ((e = qlist_pop(cpus))) {
         QDict *cpu, *props;
-        int64_t thread, node;
+        int64_t socket, cluster, core, thread, node;
 
         cpu = qobject_to(QDict, e);
         g_assert(qdict_haskey(cpu, "props"));
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
 
         g_assert(qdict_haskey(props, "node-id"));
         node = qdict_get_int(props, "node-id");
+        g_assert(qdict_haskey(props, "socket-id"));
+        socket = qdict_get_int(props, "socket-id");
+        g_assert(qdict_haskey(props, "cluster-id"));
+        cluster = qdict_get_int(props, "cluster-id");
+        g_assert(qdict_haskey(props, "core-id"));
+        core = qdict_get_int(props, "core-id");
         g_assert(qdict_haskey(props, "thread-id"));
         thread = qdict_get_int(props, "thread-id");
 
-        if (thread == 0) {
+        if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
             g_assert_cmpint(node, ==, 1);
-        } else if (thread == 1) {
+        } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
             g_assert_cmpint(node, ==, 0);
         } else {
             g_assert(false);
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.

For example, the following warning messages are observed when the
Linux guest is booted with the following command lines.

/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
  -accel kvm -machine virt,gic-version=host               \
  -cpu host                                               \
  -smp 6,sockets=2,cores=3,threads=1                      \
  -m 1024M,slots=16,maxmem=64G                            \
  -object memory-backend-ram,id=mem0,size=128M            \
  -object memory-backend-ram,id=mem1,size=128M            \
  -object memory-backend-ram,id=mem2,size=128M            \
  -object memory-backend-ram,id=mem3,size=128M            \
  -object memory-backend-ram,id=mem4,size=128M            \
  -object memory-backend-ram,id=mem4,size=384M            \
  -numa node,nodeid=0,memdev=mem0                         \
  -numa node,nodeid=1,memdev=mem1                         \
  -numa node,nodeid=2,memdev=mem2                         \
  -numa node,nodeid=3,memdev=mem3                         \
  -numa node,nodeid=4,memdev=mem4                         \
  -numa node,nodeid=5,memdev=mem5
         :
  alternatives: patching kernel code
  BUG: arch topology borken
  the CLS domain not a subset of the MC domain
  <the above error log repeats>
  BUG: arch topology borken
  the DIE domain not a subset of the NODE domain

With current implementation of mc->get_default_cpu_node_id(),
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
That's incorrect because CPU#0/1/2 should be associated with same
NUMA node because they're seated in same socket.

This fixes the issue by considering the socket ID when the default
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
With this applied, no more CPU topology broken warnings are seen
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
there are no CPUs associated with NODE#2/3/4/5.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 
 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
 {
-    return idx % ms->numa_state->num_nodes;
+    int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
+
+    return socket_id % ms->numa_state->num_nodes;
 }
 
 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.

This reworks build_pptt() to avoid by reusing the existing IDs in
ms->possible_cpus. Currently, the only user of build_pptt() is
arm/virt machine.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Tested-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20220503140304.855514-7-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
 1 file changed, 48 insertions(+), 63 deletions(-)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
                 const char *oem_id, const char *oem_table_id)
 {
     MachineClass *mc = MACHINE_GET_CLASS(ms);
-    GQueue *list = g_queue_new();
-    guint pptt_start = table_data->len;
-    guint parent_offset;
-    guint length, i;
-    int uid = 0;
-    int socket;
+    CPUArchIdList *cpus = ms->possible_cpus;
+    int64_t socket_id = -1, cluster_id = -1, core_id = -1;
+    uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
+    uint32_t pptt_start = table_data->len;
+    int n;
     AcpiTable table = { .sig = "PPTT", .rev = 2,
                         .oem_id = oem_id, .oem_table_id = oem_table_id };
 
     acpi_table_begin(&table, table_data);
 
-    for (socket = 0; socket < ms->smp.sockets; socket++) {
-        g_queue_push_tail(list,
-            GUINT_TO_POINTER(table_data->len - pptt_start));
-        build_processor_hierarchy_node(
-            table_data,
-            /*
-             * Physical package - represents the boundary
-             * of a physical package
-             */
-            (1 << 0),
-            0, socket, NULL, 0);
-    }
-
-    if (mc->smp_props.clusters_supported) {
-        length = g_queue_get_length(list);
-        for (i = 0; i < length; i++) {
-            int cluster;
-
-            parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-            for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
-                g_queue_push_tail(list,
-                    GUINT_TO_POINTER(table_data->len - pptt_start));
-                build_processor_hierarchy_node(
-                    table_data,
-                    (0 << 0), /* not a physical package */
-                    parent_offset, cluster, NULL, 0);
-            }
+    /*
+     * This works with the assumption that cpus[n].props.*_id has been
+     * sorted from top to down levels in mc->possible_cpu_arch_ids().
+     * Otherwise, the unexpected and duplicated containers will be
+     * created.
+     */
+    for (n = 0; n < cpus->len; n++) {
+        if (cpus->cpus[n].props.socket_id != socket_id) {
+            assert(cpus->cpus[n].props.socket_id > socket_id);
+            socket_id = cpus->cpus[n].props.socket_id;
+            cluster_id = -1;
+            core_id = -1;
+            socket_offset = table_data->len - pptt_start;
+            build_processor_hierarchy_node(table_data,
+                (1 << 0), /* Physical package */
+                0, socket_id, NULL, 0);
         }
-    }
 
-    length = g_queue_get_length(list);
-    for (i = 0; i < length; i++) {
-        int core;
-
-        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-        for (core = 0; core < ms->smp.cores; core++) {
-            if (ms->smp.threads > 1) {
-                g_queue_push_tail(list,
-                    GUINT_TO_POINTER(table_data->len - pptt_start));
-                build_processor_hierarchy_node(
-                    table_data,
-                    (0 << 0), /* not a physical package */
-                    parent_offset, core, NULL, 0);
-            } else {
-                build_processor_hierarchy_node(
-                    table_data,
-                    (1 << 1) | /* ACPI Processor ID valid */
-                    (1 << 3),  /* Node is a Leaf */
-                    parent_offset, uid++, NULL, 0);
+        if (mc->smp_props.clusters_supported) {
+            if (cpus->cpus[n].props.cluster_id != cluster_id) {
+                assert(cpus->cpus[n].props.cluster_id > cluster_id);
+                cluster_id = cpus->cpus[n].props.cluster_id;
+                core_id = -1;
+                cluster_offset = table_data->len - pptt_start;
+                build_processor_hierarchy_node(table_data,
+                    (0 << 0), /* Not a physical package */
+                    socket_offset, cluster_id, NULL, 0);
             }
+        } else {
+            cluster_offset = socket_offset;
         }
-    }
 
-    length = g_queue_get_length(list);
-    for (i = 0; i < length; i++) {
-        int thread;
+        if (ms->smp.threads == 1) {
+            build_processor_hierarchy_node(table_data,
+                (1 << 1) | /* ACPI Processor ID valid */
+                (1 << 3),  /* Node is a Leaf */
+                cluster_offset, n, NULL, 0);
+        } else {
+            if (cpus->cpus[n].props.core_id != core_id) {
+                assert(cpus->cpus[n].props.core_id > core_id);
+                core_id = cpus->cpus[n].props.core_id;
+                core_offset = table_data->len - pptt_start;
+                build_processor_hierarchy_node(table_data,
+                    (0 << 0), /* Not a physical package */
+                    cluster_offset, core_id, NULL, 0);
+            }
 
-        parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
-        for (thread = 0; thread < ms->smp.threads; thread++) {
-            build_processor_hierarchy_node(
-                table_data,
+            build_processor_hierarchy_node(table_data,
                 (1 << 1) | /* ACPI Processor ID valid */
                 (1 << 2) | /* Processor is a Thread */
                 (1 << 3),  /* Node is a Leaf */
-                parent_offset, uid++, NULL, 0);
+                core_offset, n, NULL, 0);
         }
     }
 
-    g_queue_free(list);
     acpi_table_end(linker, &table);
 }
 
-- 
2.25.1