[Qemu-devel] [PULL 00/31] target-arm queue
[PULL 00/24] target-arm queue
1
ARM queue: mostly patches from me, but also the Smartfusion2 board.
1
The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
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2
3
thanks
3
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
4
-- PMM
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4
6
The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:
5
are available in the Git repository at:
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6
8
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
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8
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are available in the git repository at:
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for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
11
10
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921
11
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
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14
for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:
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16
msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* more preparatory work for v8M support
15
* more MVE instructions
21
* convert some omap devices away from old_mmio
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
22
* remove out of date ARM ARM section references in comments
17
* target/arm: Check NaN mode before silencing NaN
23
* add the Smartfusion2 board
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
19
* hw/arm: Add basic power management to raspi.
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
24
21
25
----------------------------------------------------------------
22
----------------------------------------------------------------
26
Peter Maydell (26):
23
Joe Komlodi (1):
27
target/arm: Implement MSR/MRS access to NS banked registers
24
target/arm: Check NaN mode before silencing NaN
28
nvic: Add banked exception states
29
nvic: Add cached vectpending_is_s_banked state
30
nvic: Add cached vectpending_prio state
31
nvic: Implement AIRCR changes for v8M
32
nvic: Make ICSR.RETTOBASE handle banked exceptions
33
nvic: Implement NVIC_ITNS<n> registers
34
nvic: Handle banked exceptions in nvic_recompute_state()
35
nvic: Make set_pending and clear_pending take a secure parameter
36
nvic: Make SHPR registers banked
37
nvic: Compare group priority for escalation to HF
38
nvic: In escalation to HardFault, support HF not being priority -1
39
nvic: Implement v8M changes to fixed priority exceptions
40
nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
41
nvic: Handle v8M changes in nvic_exec_prio()
42
target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
43
nvic: Make ICSR banked for v8M
44
nvic: Make SHCSR banked for v8M
45
nvic: Support banked exceptions in acknowledge and complete
46
target/arm: Remove out of date ARM ARM section references in A64 decoder
47
hw/arm/palm.c: Don't use old_mmio for static_ops
48
hw/gpio/omap_gpio.c: Don't use old_mmio
49
hw/timer/omap_synctimer.c: Don't use old_mmio
50
hw/timer/omap_gptimer: Don't use old_mmio
51
hw/i2c/omap_i2c.c: Don't use old_mmio
52
hw/arm/omap2.c: Don't use old_mmio
53
25
54
Subbaraya Sundeep (5):
26
Maxim Uvarov (1):
55
msf2: Add Smartfusion2 System timer
27
hw/gpio/gpio_pwr: use shutdown function for reboot
56
msf2: Microsemi Smartfusion2 System Register block
57
msf2: Add Smartfusion2 SPI controller
58
msf2: Add Smartfusion2 SoC
59
msf2: Add Emcraft's Smartfusion2 SOM kit
60
28
61
hw/arm/Makefile.objs | 1 +
29
Nolan Leake (1):
62
hw/misc/Makefile.objs | 1 +
30
hw/arm: Add basic power management to raspi.
63
hw/ssi/Makefile.objs | 1 +
64
hw/timer/Makefile.objs | 1 +
65
include/hw/arm/msf2-soc.h | 67 +++
66
include/hw/intc/armv7m_nvic.h | 33 +-
67
include/hw/misc/msf2-sysreg.h | 77 ++++
68
include/hw/ssi/mss-spi.h | 58 +++
69
include/hw/timer/mss-timer.h | 64 +++
70
target/arm/cpu.h | 62 ++-
71
hw/arm/msf2-soc.c | 238 +++++++++++
72
hw/arm/msf2-som.c | 105 +++++
73
hw/arm/omap2.c | 49 ++-
74
hw/arm/palm.c | 30 +-
75
hw/gpio/omap_gpio.c | 26 +-
76
hw/i2c/omap_i2c.c | 44 +-
77
hw/intc/armv7m_nvic.c | 913 ++++++++++++++++++++++++++++++++++------
78
hw/misc/msf2-sysreg.c | 160 +++++++
79
hw/ssi/mss-spi.c | 404 ++++++++++++++++++
80
hw/timer/mss-timer.c | 289 +++++++++++++
81
hw/timer/omap_gptimer.c | 49 ++-
82
hw/timer/omap_synctimer.c | 35 +-
83
target/arm/cpu.c | 7 +
84
target/arm/helper.c | 142 ++++++-
85
target/arm/translate-a64.c | 227 +++++-----
86
default-configs/arm-softmmu.mak | 1 +
87
hw/intc/trace-events | 13 +-
88
hw/misc/trace-events | 5 +
89
28 files changed, 2735 insertions(+), 367 deletions(-)
90
create mode 100644 include/hw/arm/msf2-soc.h
91
create mode 100644 include/hw/misc/msf2-sysreg.h
92
create mode 100644 include/hw/ssi/mss-spi.h
93
create mode 100644 include/hw/timer/mss-timer.h
94
create mode 100644 hw/arm/msf2-soc.c
95
create mode 100644 hw/arm/msf2-som.c
96
create mode 100644 hw/misc/msf2-sysreg.c
97
create mode 100644 hw/ssi/mss-spi.c
98
create mode 100644 hw/timer/mss-timer.c
99
31
32
Patrick Venture (2):
33
docs/system/arm: Add quanta-q7l1-bmc reference
34
docs/system/arm: Add quanta-gbs-bmc reference
35
36
Peter Maydell (18):
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
39
target/arm: Make asimd_imm_const() public
40
target/arm: Use asimd_imm_const for A64 decode
41
target/arm: Use dup_const() instead of bitfield_replicate()
42
target/arm: Implement MVE logical immediate insns
43
target/arm: Implement MVE vector shift left by immediate insns
44
target/arm: Implement MVE vector shift right by immediate insns
45
target/arm: Implement MVE VSHLL
46
target/arm: Implement MVE VSRI, VSLI
47
target/arm: Implement MVE VSHRN, VRSHRN
48
target/arm: Implement MVE saturating narrowing shifts
49
target/arm: Implement MVE VSHLC
50
target/arm: Implement MVE VADDLV
51
target/arm: Implement MVE long shifts by immediate
52
target/arm: Implement MVE long shifts by register
53
target/arm: Implement MVE shifts by immediate
54
target/arm: Implement MVE shifts by register
55
56
Philippe Mathieu-Daudé (1):
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
58
59
docs/system/arm/aspeed.rst | 1 +
60
docs/system/arm/nuvoton.rst | 5 +-
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
82
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/31] msf2: Add Emcraft's Smartfusion2 SOM kit
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
Emulated Emcraft's Smartfusion2 System On Module starter
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
kit.
4
entry.
5
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20170920201737.25723-6-f4bug@amsat.org
8
Message-id: 20210615192848.1065297-2-venture@google.com
9
[PMD: drop cpu_model to directly use cpu type]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/arm/Makefile.objs | 2 +-
11
docs/system/arm/aspeed.rst | 1 +
13
hw/arm/msf2-som.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++
12
1 file changed, 1 insertion(+)
14
2 files changed, 106 insertions(+), 1 deletion(-)
15
create mode 100644 hw/arm/msf2-som.c
16
13
17
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/Makefile.objs
16
--- a/docs/system/arm/aspeed.rst
20
+++ b/hw/arm/Makefile.objs
17
+++ b/docs/system/arm/aspeed.rst
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
18
@@ -XXX,XX +XXX,XX @@ etc.
22
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
19
AST2400 SoC based machines :
23
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
20
24
obj-$(CONFIG_MPS2) += mps2.o
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
25
-obj-$(CONFIG_MSF2) += msf2-soc.o
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
26
+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
23
27
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
24
AST2500 SoC based machines :
28
new file mode 100644
25
29
index XXXXXXX..XXXXXXX
30
--- /dev/null
31
+++ b/hw/arm/msf2-som.c
32
@@ -XXX,XX +XXX,XX @@
33
+/*
34
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
35
+ *
36
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
37
+ *
38
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
39
+ * of this software and associated documentation files (the "Software"), to deal
40
+ * in the Software without restriction, including without limitation the rights
41
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
42
+ * copies of the Software, and to permit persons to whom the Software is
43
+ * furnished to do so, subject to the following conditions:
44
+ *
45
+ * The above copyright notice and this permission notice shall be included in
46
+ * all copies or substantial portions of the Software.
47
+ *
48
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
49
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
50
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
51
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
52
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
53
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
54
+ * THE SOFTWARE.
55
+ */
56
+
57
+#include "qemu/osdep.h"
58
+#include "qapi/error.h"
59
+#include "qemu/error-report.h"
60
+#include "hw/boards.h"
61
+#include "hw/arm/arm.h"
62
+#include "exec/address-spaces.h"
63
+#include "qemu/cutils.h"
64
+#include "hw/arm/msf2-soc.h"
65
+#include "cpu.h"
66
+
67
+#define DDR_BASE_ADDRESS 0xA0000000
68
+#define DDR_SIZE (64 * M_BYTE)
69
+
70
+#define M2S010_ENVM_SIZE (256 * K_BYTE)
71
+#define M2S010_ESRAM_SIZE (64 * K_BYTE)
72
+
73
+static void emcraft_sf2_s2s010_init(MachineState *machine)
74
+{
75
+ DeviceState *dev;
76
+ DeviceState *spi_flash;
77
+ MSF2State *soc;
78
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
79
+ DriveInfo *dinfo = drive_get_next(IF_MTD);
80
+ qemu_irq cs_line;
81
+ SSIBus *spi_bus;
82
+ MemoryRegion *sysmem = get_system_memory();
83
+ MemoryRegion *ddr = g_new(MemoryRegion, 1);
84
+
85
+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
86
+ error_report("This board can only be used with CPU %s",
87
+ mc->default_cpu_type);
88
+ }
89
+
90
+ memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
91
+ &error_fatal);
92
+ memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
93
+
94
+ dev = qdev_create(NULL, TYPE_MSF2_SOC);
95
+ qdev_prop_set_string(dev, "part-name", "M2S010");
96
+ qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
97
+
98
+ qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
99
+ qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
100
+
101
+ /*
102
+ * CPU clock and peripheral clocks(APB0, APB1)are configurable
103
+ * in Libero. CPU clock is divided by APB0 and APB1 divisors for
104
+ * peripherals. Emcraft's SoM kit comes with these settings by default.
105
+ */
106
+ qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
107
+ qdev_prop_set_uint32(dev, "apb0div", 2);
108
+ qdev_prop_set_uint32(dev, "apb1div", 2);
109
+
110
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
111
+
112
+ soc = MSF2_SOC(dev);
113
+
114
+ /* Attach SPI flash to SPI0 controller */
115
+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
116
+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
117
+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
118
+ if (dinfo) {
119
+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
120
+ &error_fatal);
121
+ }
122
+ qdev_init_nofail(spi_flash);
123
+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
124
+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
125
+
126
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
127
+ soc->envm_size);
128
+}
129
+
130
+static void emcraft_sf2_machine_init(MachineClass *mc)
131
+{
132
+ mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
133
+ mc->init = emcraft_sf2_s2s010_init;
134
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
135
+}
136
+
137
+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
138
--
26
--
139
2.7.4
27
2.20.1
140
28
141
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/31] msf2: Add Smartfusion2 SoC
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
Smartfusion2 SoC has hardened Microcontroller subsystem
3
Add line item reference to quanta-gbs-bmc machine.
4
and flash based FPGA fabric. This patch adds support for
5
Microcontroller subsystem in the SoC.
6
4
7
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
5
Signed-off-by: Patrick Venture <venture@google.com>
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210615192848.1065297-3-venture@google.com
10
Message-id: 20170920201737.25723-5-f4bug@amsat.org
8
[PMM: fixed underline Sphinx warning]
11
[PMD: drop cpu_model to directly use cpu type, check m3clk non null]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/arm/Makefile.objs | 1 +
11
docs/system/arm/nuvoton.rst | 5 +++--
15
include/hw/arm/msf2-soc.h | 67 +++++++++++
12
1 file changed, 3 insertions(+), 2 deletions(-)
16
hw/arm/msf2-soc.c | 238 ++++++++++++++++++++++++++++++++++++++++
17
default-configs/arm-softmmu.mak | 1 +
18
4 files changed, 307 insertions(+)
19
create mode 100644 include/hw/arm/msf2-soc.h
20
create mode 100644 hw/arm/msf2-soc.c
21
13
22
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
23
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/Makefile.objs
16
--- a/docs/system/arm/nuvoton.rst
25
+++ b/hw/arm/Makefile.objs
17
+++ b/docs/system/arm/nuvoton.rst
26
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
27
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
28
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
29
obj-$(CONFIG_MPS2) += mps2.o
30
+obj-$(CONFIG_MSF2) += msf2-soc.o
31
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
32
new file mode 100644
33
index XXXXXXX..XXXXXXX
34
--- /dev/null
35
+++ b/include/hw/arm/msf2-soc.h
36
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@
37
+/*
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
38
+ * Microsemi Smartfusion2 SoC
20
-=====================================================
39
+ *
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
40
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
22
+================================================================
41
+ *
23
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
43
+ * of this software and associated documentation files (the "Software"), to deal
25
designed to be used as Baseboard Management Controllers (BMCs) in various
44
+ * in the Software without restriction, including without limitation the rights
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
46
+ * copies of the Software, and to permit persons to whom the Software is
28
Hyperscale applications. The following machines are based on this chip :
47
+ * furnished to do so, subject to the following conditions:
29
48
+ *
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
49
+ * The above copyright notice and this permission notice shall be included in
31
- ``quanta-gsj`` Quanta GSJ server BMC
50
+ * all copies or substantial portions of the Software.
32
51
+ *
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
60
+
61
+#ifndef HW_ARM_MSF2_SOC_H
62
+#define HW_ARM_MSF2_SOC_H
63
+
64
+#include "hw/arm/armv7m.h"
65
+#include "hw/timer/mss-timer.h"
66
+#include "hw/misc/msf2-sysreg.h"
67
+#include "hw/ssi/mss-spi.h"
68
+
69
+#define TYPE_MSF2_SOC "msf2-soc"
70
+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
71
+
72
+#define MSF2_NUM_SPIS 2
73
+#define MSF2_NUM_UARTS 2
74
+
75
+/*
76
+ * System timer consists of two programmable 32-bit
77
+ * decrementing counters that generate individual interrupts to
78
+ * the Cortex-M3 processor
79
+ */
80
+#define MSF2_NUM_TIMERS 2
81
+
82
+typedef struct MSF2State {
83
+ /*< private >*/
84
+ SysBusDevice parent_obj;
85
+ /*< public >*/
86
+
87
+ ARMv7MState armv7m;
88
+
89
+ char *cpu_type;
90
+ char *part_name;
91
+ uint64_t envm_size;
92
+ uint64_t esram_size;
93
+
94
+ uint32_t m3clk;
95
+ uint8_t apb0div;
96
+ uint8_t apb1div;
97
+
98
+ MSF2SysregState sysreg;
99
+ MSSTimerState timer;
100
+ MSSSpiState spi[MSF2_NUM_SPIS];
101
+} MSF2State;
102
+
103
+#endif
104
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
105
new file mode 100644
106
index XXXXXXX..XXXXXXX
107
--- /dev/null
108
+++ b/hw/arm/msf2-soc.c
109
@@ -XXX,XX +XXX,XX @@
110
+/*
111
+ * SmartFusion2 SoC emulation.
112
+ *
113
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
114
+ *
115
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
116
+ * of this software and associated documentation files (the "Software"), to deal
117
+ * in the Software without restriction, including without limitation the rights
118
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
119
+ * copies of the Software, and to permit persons to whom the Software is
120
+ * furnished to do so, subject to the following conditions:
121
+ *
122
+ * The above copyright notice and this permission notice shall be included in
123
+ * all copies or substantial portions of the Software.
124
+ *
125
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
126
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
127
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
128
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
129
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
130
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
131
+ * THE SOFTWARE.
132
+ */
133
+
134
+#include "qemu/osdep.h"
135
+#include "qapi/error.h"
136
+#include "qemu-common.h"
137
+#include "hw/arm/arm.h"
138
+#include "exec/address-spaces.h"
139
+#include "hw/char/serial.h"
140
+#include "hw/boards.h"
141
+#include "sysemu/block-backend.h"
142
+#include "qemu/cutils.h"
143
+#include "hw/arm/msf2-soc.h"
144
+#include "hw/misc/unimp.h"
145
+
146
+#define MSF2_TIMER_BASE 0x40004000
147
+#define MSF2_SYSREG_BASE 0x40038000
148
+
149
+#define ENVM_BASE_ADDRESS 0x60000000
150
+
151
+#define SRAM_BASE_ADDRESS 0x20000000
152
+
153
+#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
154
+
155
+/*
156
+ * eSRAM max size is 80k without SECDED(Single error correction and
157
+ * dual error detection) feature and 64k with SECDED.
158
+ * We do not support SECDED now.
159
+ */
160
+#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
161
+
162
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
163
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
164
+
165
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
166
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
167
+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
168
+
169
+static void m2sxxx_soc_initfn(Object *obj)
170
+{
171
+ MSF2State *s = MSF2_SOC(obj);
172
+ int i;
173
+
174
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
175
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
176
+
177
+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
178
+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
179
+
180
+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
181
+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
182
+
183
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
184
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
185
+ TYPE_MSS_SPI);
186
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
187
+ }
188
+}
189
+
190
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
191
+{
192
+ MSF2State *s = MSF2_SOC(dev_soc);
193
+ DeviceState *dev, *armv7m;
194
+ SysBusDevice *busdev;
195
+ Error *err = NULL;
196
+ int i;
197
+
198
+ MemoryRegion *system_memory = get_system_memory();
199
+ MemoryRegion *nvm = g_new(MemoryRegion, 1);
200
+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
201
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
202
+
203
+ memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
204
+ &error_fatal);
205
+ /*
206
+ * On power-on, the eNVM region 0x60000000 is automatically
207
+ * remapped to the Cortex-M3 processor executable region
208
+ * start address (0x0). We do not support remapping other eNVM,
209
+ * eSRAM and DDR regions by guest(via Sysreg) currently.
210
+ */
211
+ memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
212
+ nvm, 0, s->envm_size);
213
+
214
+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
215
+ memory_region_add_subregion(system_memory, 0, nvm_alias);
216
+
217
+ memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
218
+ &error_fatal);
219
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
220
+
221
+ armv7m = DEVICE(&s->armv7m);
222
+ qdev_prop_set_uint32(armv7m, "num-irq", 81);
223
+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
224
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
225
+ "memory", &error_abort);
226
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
227
+ if (err != NULL) {
228
+ error_propagate(errp, err);
229
+ return;
230
+ }
231
+
232
+ if (!s->m3clk) {
233
+ error_setg(errp, "Invalid m3clk value");
234
+ error_append_hint(errp, "m3clk can not be zero\n");
235
+ return;
236
+ }
237
+ system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
238
+
239
+ for (i = 0; i < MSF2_NUM_UARTS; i++) {
240
+ if (serial_hds[i]) {
241
+ serial_mm_init(get_system_memory(), uart_addr[i], 2,
242
+ qdev_get_gpio_in(armv7m, uart_irq[i]),
243
+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
244
+ }
245
+ }
246
+
247
+ dev = DEVICE(&s->timer);
248
+ /* APB0 clock is the timer input clock */
249
+ qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
250
+ object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
251
+ if (err != NULL) {
252
+ error_propagate(errp, err);
253
+ return;
254
+ }
255
+ busdev = SYS_BUS_DEVICE(dev);
256
+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
257
+ sysbus_connect_irq(busdev, 0,
258
+ qdev_get_gpio_in(armv7m, timer_irq[0]));
259
+ sysbus_connect_irq(busdev, 1,
260
+ qdev_get_gpio_in(armv7m, timer_irq[1]));
261
+
262
+ dev = DEVICE(&s->sysreg);
263
+ qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
264
+ qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
265
+ object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
266
+ if (err != NULL) {
267
+ error_propagate(errp, err);
268
+ return;
269
+ }
270
+ busdev = SYS_BUS_DEVICE(dev);
271
+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
272
+
273
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
274
+ gchar *bus_name;
275
+
276
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
277
+ if (err != NULL) {
278
+ error_propagate(errp, err);
279
+ return;
280
+ }
281
+
282
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
283
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
284
+ qdev_get_gpio_in(armv7m, spi_irq[i]));
285
+
286
+ /* Alias controller SPI bus to the SoC itself */
287
+ bus_name = g_strdup_printf("spi%d", i);
288
+ object_property_add_alias(OBJECT(s), bus_name,
289
+ OBJECT(&s->spi[i]), "spi",
290
+ &error_abort);
291
+ g_free(bus_name);
292
+ }
293
+
294
+ /* Below devices are not modelled yet. */
295
+ create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
296
+ create_unimplemented_device("dma", 0x40003000, 0x1000);
297
+ create_unimplemented_device("watchdog", 0x40005000, 0x1000);
298
+ create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
299
+ create_unimplemented_device("gpio", 0x40013000, 0x1000);
300
+ create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
301
+ create_unimplemented_device("can", 0x40015000, 0x1000);
302
+ create_unimplemented_device("rtc", 0x40017000, 0x1000);
303
+ create_unimplemented_device("apb_config", 0x40020000, 0x10000);
304
+ create_unimplemented_device("emac", 0x40041000, 0x1000);
305
+ create_unimplemented_device("usb", 0x40043000, 0x1000);
306
+}
307
+
308
+static Property m2sxxx_soc_properties[] = {
309
+ /*
310
+ * part name specifies the type of SmartFusion2 device variant(this
311
+ * property is for information purpose only.
312
+ */
313
+ DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
314
+ DEFINE_PROP_STRING("part-name", MSF2State, part_name),
315
+ DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
316
+ DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
317
+ MSF2_ESRAM_MAX_SIZE),
318
+ /* Libero GUI shows 100Mhz as default for clocks */
319
+ DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
320
+ /* default divisors in Libero GUI */
321
+ DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
322
+ DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
323
+ DEFINE_PROP_END_OF_LIST(),
324
+};
325
+
326
+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
327
+{
328
+ DeviceClass *dc = DEVICE_CLASS(klass);
329
+
330
+ dc->realize = m2sxxx_soc_realize;
331
+ dc->props = m2sxxx_soc_properties;
332
+}
333
+
334
+static const TypeInfo m2sxxx_soc_info = {
335
+ .name = TYPE_MSF2_SOC,
336
+ .parent = TYPE_SYS_BUS_DEVICE,
337
+ .instance_size = sizeof(MSF2State),
338
+ .instance_init = m2sxxx_soc_initfn,
339
+ .class_init = m2sxxx_soc_class_init,
340
+};
341
+
342
+static void m2sxxx_soc_types(void)
343
+{
344
+ type_register_static(&m2sxxx_soc_info);
345
+}
346
+
347
+type_init(m2sxxx_soc_types)
348
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
349
index XXXXXXX..XXXXXXX 100644
350
--- a/default-configs/arm-softmmu.mak
351
+++ b/default-configs/arm-softmmu.mak
352
@@ -XXX,XX +XXX,XX @@ CONFIG_ACPI=y
353
CONFIG_SMBIOS=y
354
CONFIG_ASPEED_SOC=y
355
CONFIG_GPIO_KEY=y
356
+CONFIG_MSF2=y
357
--
34
--
358
2.7.4
35
2.20.1
359
36
360
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/31] msf2: Add Smartfusion2 SPI controller
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
Modelled Microsemi's Smartfusion2 SPI controller.
3
This is just enough to make reboot and poweroff work. Works for
4
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
6
do what linux does for reset.
7
8
The watchdog timer functionality is not yet implemented.
9
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20170920201737.25723-4-f4bug@amsat.org
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
18
---
11
hw/ssi/Makefile.objs | 1 +
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
12
include/hw/ssi/mss-spi.h | 58 +++++++
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
13
hw/ssi/mss-spi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++
21
hw/arm/bcm2835_peripherals.c | 13 ++-
14
3 files changed, 463 insertions(+)
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
15
create mode 100644 include/hw/ssi/mss-spi.h
23
hw/misc/meson.build | 1 +
16
create mode 100644 hw/ssi/mss-spi.c
24
5 files changed, 204 insertions(+), 2 deletions(-)
17
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
18
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
26
create mode 100644 hw/misc/bcm2835_powermgt.c
27
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
19
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ssi/Makefile.objs
30
--- a/include/hw/arm/bcm2835_peripherals.h
21
+++ b/hw/ssi/Makefile.objs
31
+++ b/include/hw/arm/bcm2835_peripherals.h
22
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
32
@@ -XXX,XX +XXX,XX @@
23
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
33
#include "hw/misc/bcm2835_mphi.h"
24
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
34
#include "hw/misc/bcm2835_thermal.h"
25
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
35
#include "hw/misc/bcm2835_cprman.h"
26
+common-obj-$(CONFIG_MSF2) += mss-spi.o
36
+#include "hw/misc/bcm2835_powermgt.h"
27
37
#include "hw/sd/sdhci.h"
28
obj-$(CONFIG_OMAP) += omap_spi.o
38
#include "hw/sd/bcm2835_sdhost.h"
29
obj-$(CONFIG_IMX) += imx_spi.o
39
#include "hw/gpio/bcm2835_gpio.h"
30
diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
41
BCM2835MphiState mphi;
42
UnimplementedDeviceState txp;
43
UnimplementedDeviceState armtmr;
44
- UnimplementedDeviceState powermgt;
45
+ BCM2835PowerMgtState powermgt;
46
BCM2835CprmanState cprman;
47
PL011State uart0;
48
BCM2835AuxState aux;
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
31
new file mode 100644
50
new file mode 100644
32
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
33
--- /dev/null
52
--- /dev/null
34
+++ b/include/hw/ssi/mss-spi.h
53
+++ b/include/hw/misc/bcm2835_powermgt.h
35
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
36
+/*
55
+/*
37
+ * Microsemi SmartFusion2 SPI
56
+ * BCM2835 Power Management emulation
38
+ *
57
+ *
39
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
40
+ *
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
60
+ *
42
+ * of this software and associated documentation files (the "Software"), to deal
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
43
+ * in the Software without restriction, including without limitation the rights
62
+ * See the COPYING file in the top-level directory.
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
45
+ * copies of the Software, and to permit persons to whom the Software is
46
+ * furnished to do so, subject to the following conditions:
47
+ *
48
+ * The above copyright notice and this permission notice shall be included in
49
+ * all copies or substantial portions of the Software.
50
+ *
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
57
+ * THE SOFTWARE.
58
+ */
63
+ */
59
+
64
+
60
+#ifndef HW_MSS_SPI_H
65
+#ifndef BCM2835_POWERMGT_H
61
+#define HW_MSS_SPI_H
66
+#define BCM2835_POWERMGT_H
62
+
67
+
63
+#include "hw/sysbus.h"
68
+#include "hw/sysbus.h"
64
+#include "hw/ssi/ssi.h"
69
+#include "qom/object.h"
65
+#include "qemu/fifo32.h"
70
+
66
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
67
+#define TYPE_MSS_SPI "mss-spi"
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
68
+#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
73
+
69
+
74
+struct BCM2835PowerMgtState {
70
+#define R_SPI_MAX 16
75
+ SysBusDevice busdev;
71
+
76
+ MemoryRegion iomem;
72
+typedef struct MSSSpiState {
77
+
73
+ SysBusDevice parent_obj;
78
+ uint32_t rstc;
74
+
79
+ uint32_t rsts;
75
+ MemoryRegion mmio;
80
+ uint32_t wdog;
76
+
81
+};
77
+ qemu_irq irq;
82
+
78
+
83
+#endif
79
+ qemu_irq cs_line;
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
80
+
85
index XXXXXXX..XXXXXXX 100644
81
+ SSIBus *spi;
86
--- a/hw/arm/bcm2835_peripherals.c
82
+
87
+++ b/hw/arm/bcm2835_peripherals.c
83
+ Fifo32 rx_fifo;
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
84
+ Fifo32 tx_fifo;
89
85
+
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
86
+ int fifo_depth;
91
OBJECT(&s->gpu_bus_mr));
87
+ uint32_t frame_count;
92
+
88
+ bool enabled;
93
+ /* Power Management */
89
+
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
90
+ uint32_t regs[R_SPI_MAX];
95
+ TYPE_BCM2835_POWERMGT);
91
+} MSSSpiState;
96
}
92
+
97
93
+#endif /* HW_MSS_SPI_H */
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
94
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
101
INTERRUPT_USB));
102
103
+ /* Power Management */
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
105
+ return;
106
+ }
107
+
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
110
+
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
95
new file mode 100644
118
new file mode 100644
96
index XXXXXXX..XXXXXXX
119
index XXXXXXX..XXXXXXX
97
--- /dev/null
120
--- /dev/null
98
+++ b/hw/ssi/mss-spi.c
121
+++ b/hw/misc/bcm2835_powermgt.c
99
@@ -XXX,XX +XXX,XX @@
122
@@ -XXX,XX +XXX,XX @@
100
+/*
123
+/*
101
+ * Block model of SPI controller present in
124
+ * BCM2835 Power Management emulation
102
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
125
+ *
103
+ *
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
104
+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
105
+ *
128
+ *
106
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
107
+ * of this software and associated documentation files (the "Software"), to deal
130
+ * See the COPYING file in the top-level directory.
108
+ * in the Software without restriction, including without limitation the rights
109
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
110
+ * copies of the Software, and to permit persons to whom the Software is
111
+ * furnished to do so, subject to the following conditions:
112
+ *
113
+ * The above copyright notice and this permission notice shall be included in
114
+ * all copies or substantial portions of the Software.
115
+ *
116
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
117
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
118
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
119
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
120
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
121
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
122
+ * THE SOFTWARE.
123
+ */
131
+ */
124
+
132
+
125
+#include "qemu/osdep.h"
133
+#include "qemu/osdep.h"
126
+#include "hw/ssi/mss-spi.h"
127
+#include "qemu/log.h"
134
+#include "qemu/log.h"
128
+
135
+#include "qemu/module.h"
129
+#ifndef MSS_SPI_ERR_DEBUG
136
+#include "hw/misc/bcm2835_powermgt.h"
130
+#define MSS_SPI_ERR_DEBUG 0
137
+#include "migration/vmstate.h"
131
+#endif
138
+#include "sysemu/runstate.h"
132
+
139
+
133
+#define DB_PRINT_L(lvl, fmt, args...) do { \
140
+#define PASSWORD 0x5a000000
134
+ if (MSS_SPI_ERR_DEBUG >= lvl) { \
141
+#define PASSWORD_MASK 0xff000000
135
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
142
+
136
+ } \
143
+#define R_RSTC 0x1c
137
+} while (0);
144
+#define V_RSTC_RESET 0x20
138
+
145
+#define R_RSTS 0x20
139
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
140
+
147
+#define R_WDOG 0x24
141
+#define FIFO_CAPACITY 32
148
+
142
+
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
143
+#define R_SPI_CONTROL 0
150
+ unsigned size)
144
+#define R_SPI_DFSIZE 1
151
+{
145
+#define R_SPI_STATUS 2
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
146
+#define R_SPI_INTCLR 3
153
+ uint32_t res = 0;
147
+#define R_SPI_RX 4
154
+
148
+#define R_SPI_TX 5
155
+ switch (offset) {
149
+#define R_SPI_CLKGEN 6
156
+ case R_RSTC:
150
+#define R_SPI_SS 7
157
+ res = s->rstc;
151
+#define R_SPI_MIS 8
158
+ break;
152
+#define R_SPI_RIS 9
159
+ case R_RSTS:
153
+
160
+ res = s->rsts;
154
+#define S_TXDONE (1 << 0)
161
+ break;
155
+#define S_RXRDY (1 << 1)
162
+ case R_WDOG:
156
+#define S_RXCHOVRF (1 << 2)
163
+ res = s->wdog;
157
+#define S_RXFIFOFUL (1 << 4)
158
+#define S_RXFIFOFULNXT (1 << 5)
159
+#define S_RXFIFOEMP (1 << 6)
160
+#define S_RXFIFOEMPNXT (1 << 7)
161
+#define S_TXFIFOFUL (1 << 8)
162
+#define S_TXFIFOFULNXT (1 << 9)
163
+#define S_TXFIFOEMP (1 << 10)
164
+#define S_TXFIFOEMPNXT (1 << 11)
165
+#define S_FRAMESTART (1 << 12)
166
+#define S_SSEL (1 << 13)
167
+#define S_ACTIVE (1 << 14)
168
+
169
+#define C_ENABLE (1 << 0)
170
+#define C_MODE (1 << 1)
171
+#define C_INTRXDATA (1 << 4)
172
+#define C_INTTXDATA (1 << 5)
173
+#define C_INTRXOVRFLO (1 << 6)
174
+#define C_SPS (1 << 26)
175
+#define C_BIGFIFO (1 << 29)
176
+#define C_RESET (1 << 31)
177
+
178
+#define FRAMESZ_MASK 0x1F
179
+#define FMCOUNT_MASK 0x00FFFF00
180
+#define FMCOUNT_SHIFT 8
181
+
182
+static void txfifo_reset(MSSSpiState *s)
183
+{
184
+ fifo32_reset(&s->tx_fifo);
185
+
186
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
187
+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
188
+}
189
+
190
+static void rxfifo_reset(MSSSpiState *s)
191
+{
192
+ fifo32_reset(&s->rx_fifo);
193
+
194
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
195
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
196
+}
197
+
198
+static void set_fifodepth(MSSSpiState *s)
199
+{
200
+ unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
201
+
202
+ if (size <= 8) {
203
+ s->fifo_depth = 32;
204
+ } else if (size <= 16) {
205
+ s->fifo_depth = 16;
206
+ } else if (size <= 32) {
207
+ s->fifo_depth = 8;
208
+ } else {
209
+ s->fifo_depth = 4;
210
+ }
211
+}
212
+
213
+static void update_mis(MSSSpiState *s)
214
+{
215
+ uint32_t reg = s->regs[R_SPI_CONTROL];
216
+ uint32_t tmp;
217
+
218
+ /*
219
+ * form the Control register interrupt enable bits
220
+ * same as RIS, MIS and Interrupt clear registers for simplicity
221
+ */
222
+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
223
+ ((reg & C_INTTXDATA) >> 5);
224
+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
225
+}
226
+
227
+static void spi_update_irq(MSSSpiState *s)
228
+{
229
+ int irq;
230
+
231
+ update_mis(s);
232
+ irq = !!(s->regs[R_SPI_MIS]);
233
+
234
+ qemu_set_irq(s->irq, irq);
235
+}
236
+
237
+static void mss_spi_reset(DeviceState *d)
238
+{
239
+ MSSSpiState *s = MSS_SPI(d);
240
+
241
+ memset(s->regs, 0, sizeof s->regs);
242
+ s->regs[R_SPI_CONTROL] = 0x80000102;
243
+ s->regs[R_SPI_DFSIZE] = 0x4;
244
+ s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
245
+ s->regs[R_SPI_CLKGEN] = 0x7;
246
+ s->regs[R_SPI_RIS] = 0x0;
247
+
248
+ s->fifo_depth = 4;
249
+ s->frame_count = 1;
250
+ s->enabled = false;
251
+
252
+ rxfifo_reset(s);
253
+ txfifo_reset(s);
254
+}
255
+
256
+static uint64_t
257
+spi_read(void *opaque, hwaddr addr, unsigned int size)
258
+{
259
+ MSSSpiState *s = opaque;
260
+ uint32_t ret = 0;
261
+
262
+ addr >>= 2;
263
+ switch (addr) {
264
+ case R_SPI_RX:
265
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
266
+ s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
267
+ ret = fifo32_pop(&s->rx_fifo);
268
+ if (fifo32_is_empty(&s->rx_fifo)) {
269
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
270
+ }
271
+ break;
272
+
273
+ case R_SPI_MIS:
274
+ update_mis(s);
275
+ ret = s->regs[R_SPI_MIS];
276
+ break;
164
+ break;
277
+
165
+
278
+ default:
166
+ default:
279
+ if (addr < ARRAY_SIZE(s->regs)) {
167
+ qemu_log_mask(LOG_UNIMP,
280
+ ret = s->regs[addr];
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
281
+ } else {
169
+ "\n", offset);
282
+ qemu_log_mask(LOG_GUEST_ERROR,
170
+ res = 0;
283
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
171
+ break;
284
+ addr * 4);
172
+ }
285
+ return ret;
173
+
286
+ }
174
+ return res;
287
+ break;
175
+}
288
+ }
176
+
289
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
290
+ DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
178
+ uint64_t value, unsigned size)
291
+ spi_update_irq(s);
179
+{
292
+ return ret;
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
293
+}
181
+
294
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
295
+static void assert_cs(MSSSpiState *s)
183
+ qemu_log_mask(LOG_GUEST_ERROR,
296
+{
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
297
+ qemu_set_irq(s->cs_line, 0);
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
298
+}
186
+ value, offset);
299
+
187
+ return;
300
+static void deassert_cs(MSSSpiState *s)
188
+ }
301
+{
189
+
302
+ qemu_set_irq(s->cs_line, 1);
190
+ value = value & ~PASSWORD_MASK;
303
+}
191
+
304
+
192
+ switch (offset) {
305
+static void spi_flush_txfifo(MSSSpiState *s)
193
+ case R_RSTC:
306
+{
194
+ s->rstc = value;
307
+ uint32_t tx;
195
+ if (value & V_RSTC_RESET) {
308
+ uint32_t rx;
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
309
+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
310
+
198
+ } else {
311
+ /*
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
312
+ * Chip Select(CS) is automatically controlled by this controller.
313
+ * If SPS bit is set in Control register then CS is asserted
314
+ * until all the frames set in frame count of Control register are
315
+ * transferred. If SPS is not set then CS pulses between frames.
316
+ * Note that Slave Select register specifies which of the CS line
317
+ * has to be controlled automatically by controller. Bits SS[7:1] are for
318
+ * masters in FPGA fabric since we model only Microcontroller subsystem
319
+ * of Smartfusion2 we control only one CS(SS[0]) line.
320
+ */
321
+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
322
+ assert_cs(s);
323
+
324
+ s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
325
+
326
+ tx = fifo32_pop(&s->tx_fifo);
327
+ DB_PRINT("data tx:0x%" PRIx32, tx);
328
+ rx = ssi_transfer(s->spi, tx);
329
+ DB_PRINT("data rx:0x%" PRIx32, rx);
330
+
331
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
332
+ s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
333
+ s->regs[R_SPI_RIS] |= S_RXCHOVRF;
334
+ } else {
335
+ fifo32_push(&s->rx_fifo, rx);
336
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
337
+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
338
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
339
+ } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
340
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
341
+ }
200
+ }
342
+ }
201
+ }
343
+ s->frame_count--;
202
+ break;
344
+ if (!sps) {
203
+ case R_RSTS:
345
+ deassert_cs(s);
204
+ qemu_log_mask(LOG_UNIMP,
346
+ }
205
+ "bcm2835_powermgt_write: RSTS\n");
347
+ }
206
+ s->rsts = value;
348
+
207
+ break;
349
+ if (!s->frame_count) {
208
+ case R_WDOG:
350
+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
209
+ qemu_log_mask(LOG_UNIMP,
351
+ FMCOUNT_SHIFT;
210
+ "bcm2835_powermgt_write: WDOG\n");
352
+ deassert_cs(s);
211
+ s->wdog = value;
353
+ s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
354
+ s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
355
+ }
356
+}
357
+
358
+static void spi_write(void *opaque, hwaddr addr,
359
+ uint64_t val64, unsigned int size)
360
+{
361
+ MSSSpiState *s = opaque;
362
+ uint32_t value = val64;
363
+
364
+ DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
365
+ addr >>= 2;
366
+
367
+ switch (addr) {
368
+ case R_SPI_TX:
369
+ /* adding to already full FIFO */
370
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
371
+ break;
372
+ }
373
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
374
+ fifo32_push(&s->tx_fifo, value);
375
+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
376
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
377
+ } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
378
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
379
+ }
380
+ if (s->enabled) {
381
+ spi_flush_txfifo(s);
382
+ }
383
+ break;
384
+
385
+ case R_SPI_CONTROL:
386
+ s->regs[R_SPI_CONTROL] = value;
387
+ if (value & C_BIGFIFO) {
388
+ set_fifodepth(s);
389
+ } else {
390
+ s->fifo_depth = 4;
391
+ }
392
+ s->enabled = value & C_ENABLE;
393
+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
394
+ if (value & C_RESET) {
395
+ mss_spi_reset(DEVICE(s));
396
+ }
397
+ break;
398
+
399
+ case R_SPI_DFSIZE:
400
+ if (s->enabled) {
401
+ break;
402
+ }
403
+ s->regs[R_SPI_DFSIZE] = value;
404
+ break;
405
+
406
+ case R_SPI_INTCLR:
407
+ s->regs[R_SPI_INTCLR] = value;
408
+ if (value & S_TXDONE) {
409
+ s->regs[R_SPI_RIS] &= ~S_TXDONE;
410
+ }
411
+ if (value & S_RXRDY) {
412
+ s->regs[R_SPI_RIS] &= ~S_RXRDY;
413
+ }
414
+ if (value & S_RXCHOVRF) {
415
+ s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
416
+ }
417
+ break;
418
+
419
+ case R_SPI_MIS:
420
+ case R_SPI_STATUS:
421
+ case R_SPI_RIS:
422
+ qemu_log_mask(LOG_GUEST_ERROR,
423
+ "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
424
+ __func__, addr * 4);
425
+ break;
212
+ break;
426
+
213
+
427
+ default:
214
+ default:
428
+ if (addr < ARRAY_SIZE(s->regs)) {
215
+ qemu_log_mask(LOG_UNIMP,
429
+ s->regs[addr] = value;
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
430
+ } else {
217
+ "\n", offset);
431
+ qemu_log_mask(LOG_GUEST_ERROR,
218
+ break;
432
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
219
+ }
433
+ addr * 4);
220
+}
434
+ }
221
+
435
+ break;
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
436
+ }
223
+ .read = bcm2835_powermgt_read,
437
+
224
+ .write = bcm2835_powermgt_write,
438
+ spi_update_irq(s);
439
+}
440
+
441
+static const MemoryRegionOps spi_ops = {
442
+ .read = spi_read,
443
+ .write = spi_write,
444
+ .endianness = DEVICE_NATIVE_ENDIAN,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
445
+ .valid = {
226
+ .impl.min_access_size = 4,
446
+ .min_access_size = 1,
227
+ .impl.max_access_size = 4,
447
+ .max_access_size = 4
228
+};
448
+ }
229
+
449
+};
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
450
+
231
+ .name = TYPE_BCM2835_POWERMGT,
451
+static void mss_spi_realize(DeviceState *dev, Error **errp)
452
+{
453
+ MSSSpiState *s = MSS_SPI(dev);
454
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
455
+
456
+ s->spi = ssi_create_bus(dev, "spi");
457
+
458
+ sysbus_init_irq(sbd, &s->irq);
459
+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
460
+ sysbus_init_irq(sbd, &s->cs_line);
461
+
462
+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
463
+ TYPE_MSS_SPI, R_SPI_MAX * 4);
464
+ sysbus_init_mmio(sbd, &s->mmio);
465
+
466
+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
467
+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
468
+}
469
+
470
+static const VMStateDescription vmstate_mss_spi = {
471
+ .name = TYPE_MSS_SPI,
472
+ .version_id = 1,
232
+ .version_id = 1,
473
+ .minimum_version_id = 1,
233
+ .minimum_version_id = 1,
474
+ .fields = (VMStateField[]) {
234
+ .fields = (VMStateField[]) {
475
+ VMSTATE_FIFO32(tx_fifo, MSSSpiState),
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
476
+ VMSTATE_FIFO32(rx_fifo, MSSSpiState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
477
+ VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
478
+ VMSTATE_END_OF_LIST()
238
+ VMSTATE_END_OF_LIST()
479
+ }
239
+ }
480
+};
240
+};
481
+
241
+
482
+static void mss_spi_class_init(ObjectClass *klass, void *data)
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
483
+{
262
+{
484
+ DeviceClass *dc = DEVICE_CLASS(klass);
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
485
+
264
+
486
+ dc->realize = mss_spi_realize;
265
+ dc->reset = bcm2835_powermgt_reset;
487
+ dc->reset = mss_spi_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
488
+ dc->vmsd = &vmstate_mss_spi;
267
+}
489
+}
268
+
490
+
269
+static TypeInfo bcm2835_powermgt_info = {
491
+static const TypeInfo mss_spi_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
492
+ .name = TYPE_MSS_SPI,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
493
+ .parent = TYPE_SYS_BUS_DEVICE,
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
494
+ .instance_size = sizeof(MSSSpiState),
273
+ .class_init = bcm2835_powermgt_class_init,
495
+ .class_init = mss_spi_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
496
+};
275
+};
497
+
276
+
498
+static void mss_spi_register_types(void)
277
+static void bcm2835_powermgt_register_types(void)
499
+{
278
+{
500
+ type_register_static(&mss_spi_info);
279
+ type_register_static(&bcm2835_powermgt_info);
501
+}
280
+}
502
+
281
+
503
+type_init(mss_spi_register_types)
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
504
--
295
--
505
2.7.4
296
2.20.1
506
297
507
298
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/31] msf2: Microsemi Smartfusion2 System Register block
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Added Sytem register block of Smartfusion2.
3
Add a test booting and quickly shutdown a raspi2 machine,
4
This block has PLL registers which are accessed by guest.
4
to test the power management model:
5
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
8
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
Message-id: 20170920201737.25723-3-f4bug@amsat.org
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
44
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
49
---
13
hw/misc/Makefile.objs | 1 +
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
14
include/hw/misc/msf2-sysreg.h | 77 ++++++++++++++++++++
51
1 file changed, 43 insertions(+)
15
hw/misc/msf2-sysreg.c | 160 ++++++++++++++++++++++++++++++++++++++++++
16
hw/misc/trace-events | 5 ++
17
4 files changed, 243 insertions(+)
18
create mode 100644 include/hw/misc/msf2-sysreg.h
19
create mode 100644 hw/misc/msf2-sysreg.c
20
52
21
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
22
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/misc/Makefile.objs
55
--- a/tests/acceptance/boot_linux_console.py
24
+++ b/hw/misc/Makefile.objs
56
+++ b/tests/acceptance/boot_linux_console.py
25
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
26
obj-$(CONFIG_AUX) += auxbus.o
27
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
28
obj-y += mmio_interface.o
29
+obj-$(CONFIG_MSF2) += msf2-sysreg.o
30
diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
31
new file mode 100644
32
index XXXXXXX..XXXXXXX
33
--- /dev/null
34
+++ b/include/hw/misc/msf2-sysreg.h
35
@@ -XXX,XX +XXX,XX @@
57
@@ -XXX,XX +XXX,XX @@
36
+/*
58
from avocado import skip
37
+ * Microsemi SmartFusion2 SYSREG
59
from avocado import skipUnless
38
+ *
60
from avocado_qemu import Test
39
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
61
+from avocado_qemu import exec_command
40
+ *
62
from avocado_qemu import exec_command_and_wait_for_pattern
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
63
from avocado_qemu import interrupt_interactive_console_until_pattern
42
+ * of this software and associated documentation files (the "Software"), to deal
64
from avocado_qemu import wait_for_console_pattern
43
+ * in the Software without restriction, including without limitation the rights
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
66
"""
45
+ * copies of the Software, and to permit persons to whom the Software is
67
self.do_test_arm_raspi2(0)
46
+ * furnished to do so, subject to the following conditions:
68
47
+ *
69
+ def test_arm_raspi2_initrd(self):
48
+ * The above copyright notice and this permission notice shall be included in
70
+ """
49
+ * all copies or substantial portions of the Software.
71
+ :avocado: tags=arch:arm
50
+ *
72
+ :avocado: tags=machine:raspi2
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
73
+ """
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
75
+ 'pool/main/r/raspberrypi-firmware/'
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
57
+ * THE SOFTWARE.
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
58
+ */
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
59
+
81
+
60
+#ifndef HW_MSF2_SYSREG_H
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
61
+#define HW_MSF2_SYSREG_H
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
84
+ 'arm/rootfs-armv7a.cpio.gz')
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
62
+
89
+
63
+#include "hw/sysbus.h"
90
+ self.vm.set_console()
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
93
+ 'panic=-1 noreboot ' +
94
+ 'dwc_otg.fiq_fsm_enable=0')
95
+ self.vm.add_args('-kernel', kernel_path,
96
+ '-dtb', dtb_path,
97
+ '-initrd', initrd_path,
98
+ '-append', kernel_command_line,
99
+ '-no-reboot')
100
+ self.vm.launch()
101
+ self.wait_for_console_pattern('Boot successful.')
64
+
102
+
65
+enum {
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
66
+ ESRAM_CR = 0x00 / 4,
104
+ 'BCM2835')
67
+ ESRAM_MAX_LAT,
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
68
+ DDR_CR,
106
+ '/soc/cprman@7e101000')
69
+ ENVM_CR,
107
+ exec_command(self, 'halt')
70
+ ENVM_REMAP_BASE_CR,
108
+ # Wait for VM to shut down gracefully
71
+ ENVM_REMAP_FAB_CR,
109
+ self.vm.wait()
72
+ CC_CR,
73
+ CC_REGION_CR,
74
+ CC_LOCK_BASE_ADDR_CR,
75
+ CC_FLUSH_INDX_CR,
76
+ DDRB_BUF_TIMER_CR,
77
+ DDRB_NB_ADDR_CR,
78
+ DDRB_NB_SIZE_CR,
79
+ DDRB_CR,
80
+
110
+
81
+ SOFT_RESET_CR = 0x48 / 4,
111
def test_arm_exynos4210_initrd(self):
82
+ M3_CR,
112
"""
83
+
113
:avocado: tags=arch:arm
84
+ GPIO_SYSRESET_SEL_CR = 0x58 / 4,
85
+
86
+ MDDR_CR = 0x60 / 4,
87
+
88
+ MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
89
+ MSSDDR_PLL_STATUS_HIGH_CR,
90
+ MSSDDR_FACC1_CR,
91
+ MSSDDR_FACC2_CR,
92
+
93
+ MSSDDR_PLL_STATUS = 0x150 / 4,
94
+};
95
+
96
+#define MSF2_SYSREG_MMIO_SIZE 0x300
97
+
98
+#define TYPE_MSF2_SYSREG "msf2-sysreg"
99
+#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
100
+
101
+typedef struct MSF2SysregState {
102
+ SysBusDevice parent_obj;
103
+
104
+ MemoryRegion iomem;
105
+
106
+ uint8_t apb0div;
107
+ uint8_t apb1div;
108
+
109
+ uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
110
+} MSF2SysregState;
111
+
112
+#endif /* HW_MSF2_SYSREG_H */
113
diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
114
new file mode 100644
115
index XXXXXXX..XXXXXXX
116
--- /dev/null
117
+++ b/hw/misc/msf2-sysreg.c
118
@@ -XXX,XX +XXX,XX @@
119
+/*
120
+ * System Register block model of Microsemi SmartFusion2.
121
+ *
122
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
123
+ *
124
+ * This program is free software; you can redistribute it and/or
125
+ * modify it under the terms of the GNU General Public License
126
+ * as published by the Free Software Foundation; either version
127
+ * 2 of the License, or (at your option) any later version.
128
+ *
129
+ * You should have received a copy of the GNU General Public License along
130
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
131
+ */
132
+
133
+#include "qemu/osdep.h"
134
+#include "qapi/error.h"
135
+#include "qemu/log.h"
136
+#include "hw/misc/msf2-sysreg.h"
137
+#include "qemu/error-report.h"
138
+#include "trace.h"
139
+
140
+static inline int msf2_divbits(uint32_t div)
141
+{
142
+ int r = ctz32(div);
143
+
144
+ return (div < 8) ? r : r + 1;
145
+}
146
+
147
+static void msf2_sysreg_reset(DeviceState *d)
148
+{
149
+ MSF2SysregState *s = MSF2_SYSREG(d);
150
+
151
+ s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
152
+ s->regs[MSSDDR_PLL_STATUS] = 0x3;
153
+ s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
154
+ msf2_divbits(s->apb1div) << 2;
155
+}
156
+
157
+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
158
+ unsigned size)
159
+{
160
+ MSF2SysregState *s = opaque;
161
+ uint32_t ret = 0;
162
+
163
+ offset >>= 2;
164
+ if (offset < ARRAY_SIZE(s->regs)) {
165
+ ret = s->regs[offset];
166
+ trace_msf2_sysreg_read(offset << 2, ret);
167
+ } else {
168
+ qemu_log_mask(LOG_GUEST_ERROR,
169
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
170
+ offset << 2);
171
+ }
172
+
173
+ return ret;
174
+}
175
+
176
+static void msf2_sysreg_write(void *opaque, hwaddr offset,
177
+ uint64_t val, unsigned size)
178
+{
179
+ MSF2SysregState *s = opaque;
180
+ uint32_t newval = val;
181
+
182
+ offset >>= 2;
183
+
184
+ switch (offset) {
185
+ case MSSDDR_PLL_STATUS:
186
+ trace_msf2_sysreg_write_pll_status();
187
+ break;
188
+
189
+ case ESRAM_CR:
190
+ case DDR_CR:
191
+ case ENVM_REMAP_BASE_CR:
192
+ if (newval != s->regs[offset]) {
193
+ qemu_log_mask(LOG_UNIMP,
194
+ TYPE_MSF2_SYSREG": remapping not supported\n");
195
+ }
196
+ break;
197
+
198
+ default:
199
+ if (offset < ARRAY_SIZE(s->regs)) {
200
+ trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);
201
+ s->regs[offset] = newval;
202
+ } else {
203
+ qemu_log_mask(LOG_GUEST_ERROR,
204
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
205
+ offset << 2);
206
+ }
207
+ break;
208
+ }
209
+}
210
+
211
+static const MemoryRegionOps sysreg_ops = {
212
+ .read = msf2_sysreg_read,
213
+ .write = msf2_sysreg_write,
214
+ .endianness = DEVICE_NATIVE_ENDIAN,
215
+};
216
+
217
+static void msf2_sysreg_init(Object *obj)
218
+{
219
+ MSF2SysregState *s = MSF2_SYSREG(obj);
220
+
221
+ memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
222
+ MSF2_SYSREG_MMIO_SIZE);
223
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
224
+}
225
+
226
+static const VMStateDescription vmstate_msf2_sysreg = {
227
+ .name = TYPE_MSF2_SYSREG,
228
+ .version_id = 1,
229
+ .minimum_version_id = 1,
230
+ .fields = (VMStateField[]) {
231
+ VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
+static Property msf2_sysreg_properties[] = {
237
+ /* default divisors in Libero GUI */
238
+ DEFINE_PROP_UINT8("apb0divisor", MSF2SysregState, apb0div, 2),
239
+ DEFINE_PROP_UINT8("apb1divisor", MSF2SysregState, apb1div, 2),
240
+ DEFINE_PROP_END_OF_LIST(),
241
+};
242
+
243
+static void msf2_sysreg_realize(DeviceState *dev, Error **errp)
244
+{
245
+ MSF2SysregState *s = MSF2_SYSREG(dev);
246
+
247
+ if ((s->apb0div > 32 || !is_power_of_2(s->apb0div))
248
+ || (s->apb1div > 32 || !is_power_of_2(s->apb1div))) {
249
+ error_setg(errp, "Invalid apb divisor value");
250
+ error_append_hint(errp, "apb divisor must be a power of 2"
251
+ " and maximum value is 32\n");
252
+ }
253
+}
254
+
255
+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
256
+{
257
+ DeviceClass *dc = DEVICE_CLASS(klass);
258
+
259
+ dc->vmsd = &vmstate_msf2_sysreg;
260
+ dc->reset = msf2_sysreg_reset;
261
+ dc->props = msf2_sysreg_properties;
262
+ dc->realize = msf2_sysreg_realize;
263
+}
264
+
265
+static const TypeInfo msf2_sysreg_info = {
266
+ .name = TYPE_MSF2_SYSREG,
267
+ .parent = TYPE_SYS_BUS_DEVICE,
268
+ .class_init = msf2_sysreg_class_init,
269
+ .instance_size = sizeof(MSF2SysregState),
270
+ .instance_init = msf2_sysreg_init,
271
+};
272
+
273
+static void msf2_sysreg_register_types(void)
274
+{
275
+ type_register_static(&msf2_sysreg_info);
276
+}
277
+
278
+type_init(msf2_sysreg_register_types)
279
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
280
index XXXXXXX..XXXXXXX 100644
281
--- a/hw/misc/trace-events
282
+++ b/hw/misc/trace-events
283
@@ -XXX,XX +XXX,XX @@ mps2_scc_reset(void) "MPS2 SCC: reset"
284
mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) "MPS2 SCC LEDs: %c%c%c%c%c%c%c%c"
285
mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
286
mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
287
+
288
+# hw/misc/msf2-sysreg.c
289
+msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
290
+msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
291
+msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
292
--
114
--
293
2.7.4
115
2.20.1
294
116
295
117
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/31] nvic: Make SHCSR banked for v8M
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
Handle banking of SHCSR: some register bits are banked between
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
Secure and Non-Secure, and some are only accessible to Secure.
3
2
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
assert due to fpst->default_nan_mode being set.
6
7
To avoid this, we check to see what NaN mode we're running in before we call
8
floatxx_silence_nan().
9
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505240046-11454-19-git-send-email-peter.maydell@linaro.org
7
---
15
---
8
hw/intc/armv7m_nvic.c | 221 ++++++++++++++++++++++++++++++++++++++------------
16
target/arm/helper-a64.c | 12 +++++++++---
9
1 file changed, 169 insertions(+), 52 deletions(-)
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
18
2 files changed, 27 insertions(+), 9 deletions(-)
10
19
11
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/armv7m_nvic.c
22
--- a/target/arm/helper-a64.c
14
+++ b/hw/intc/armv7m_nvic.c
23
+++ b/target/arm/helper-a64.c
15
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
16
val = cpu->env.v7m.ccr[attrs.secure];
25
float16 nan = a;
17
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
26
if (float16_is_signaling_nan(a, fpst)) {
18
return val;
27
float_raise(float_flag_invalid, fpst);
19
- case 0xd24: /* System Handler Status. */
28
- nan = float16_silence_nan(a, fpst);
20
+ case 0xd24: /* System Handler Control and State (SHCSR) */
29
+ if (!fpst->default_nan_mode) {
21
val = 0;
30
+ nan = float16_silence_nan(a, fpst);
22
- if (s->vectors[ARMV7M_EXCP_MEM].active) {
23
- val |= (1 << 0);
24
- }
25
- if (s->vectors[ARMV7M_EXCP_BUS].active) {
26
- val |= (1 << 1);
27
- }
28
- if (s->vectors[ARMV7M_EXCP_USAGE].active) {
29
- val |= (1 << 3);
30
+ if (attrs.secure) {
31
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
32
+ val |= (1 << 0);
33
+ }
34
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {
35
+ val |= (1 << 2);
36
+ }
37
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {
38
+ val |= (1 << 3);
39
+ }
40
+ if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {
41
+ val |= (1 << 7);
42
+ }
43
+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {
44
+ val |= (1 << 10);
45
+ }
46
+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {
47
+ val |= (1 << 11);
48
+ }
49
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {
50
+ val |= (1 << 12);
51
+ }
52
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {
53
+ val |= (1 << 13);
54
+ }
55
+ if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {
56
+ val |= (1 << 15);
57
+ }
58
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {
59
+ val |= (1 << 16);
60
+ }
61
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {
62
+ val |= (1 << 18);
63
+ }
64
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {
65
+ val |= (1 << 21);
66
+ }
67
+ /* SecureFault is not banked but is always RAZ/WI to NS */
68
+ if (s->vectors[ARMV7M_EXCP_SECURE].active) {
69
+ val |= (1 << 4);
70
+ }
71
+ if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {
72
+ val |= (1 << 19);
73
+ }
74
+ if (s->vectors[ARMV7M_EXCP_SECURE].pending) {
75
+ val |= (1 << 20);
76
+ }
77
+ } else {
78
+ if (s->vectors[ARMV7M_EXCP_MEM].active) {
79
+ val |= (1 << 0);
80
+ }
81
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
82
+ /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
83
+ if (s->vectors[ARMV7M_EXCP_HARD].active) {
84
+ val |= (1 << 2);
85
+ }
86
+ if (s->vectors[ARMV7M_EXCP_HARD].pending) {
87
+ val |= (1 << 21);
88
+ }
89
+ }
90
+ if (s->vectors[ARMV7M_EXCP_USAGE].active) {
91
+ val |= (1 << 3);
92
+ }
93
+ if (s->vectors[ARMV7M_EXCP_SVC].active) {
94
+ val |= (1 << 7);
95
+ }
96
+ if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
97
+ val |= (1 << 10);
98
+ }
99
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
100
+ val |= (1 << 11);
101
+ }
102
+ if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
103
+ val |= (1 << 12);
104
+ }
105
+ if (s->vectors[ARMV7M_EXCP_MEM].pending) {
106
+ val |= (1 << 13);
107
+ }
108
+ if (s->vectors[ARMV7M_EXCP_SVC].pending) {
109
+ val |= (1 << 15);
110
+ }
111
+ if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
112
+ val |= (1 << 16);
113
+ }
114
+ if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
115
+ val |= (1 << 18);
116
+ }
31
+ }
117
}
32
}
118
- if (s->vectors[ARMV7M_EXCP_SVC].active) {
33
if (fpst->default_nan_mode) {
119
- val |= (1 << 7);
34
nan = float16_default_nan(fpst);
120
+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
121
+ if (s->vectors[ARMV7M_EXCP_BUS].active) {
36
float32 nan = a;
122
+ val |= (1 << 1);
37
if (float32_is_signaling_nan(a, fpst)) {
123
+ }
38
float_raise(float_flag_invalid, fpst);
124
+ if (s->vectors[ARMV7M_EXCP_BUS].pending) {
39
- nan = float32_silence_nan(a, fpst);
125
+ val |= (1 << 14);
40
+ if (!fpst->default_nan_mode) {
126
+ }
41
+ nan = float32_silence_nan(a, fpst);
127
+ if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
128
+ val |= (1 << 17);
129
+ }
130
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
131
+ s->vectors[ARMV7M_EXCP_NMI].active) {
132
+ /* NMIACT is not present in v7M */
133
+ val |= (1 << 5);
134
+ }
42
+ }
135
}
43
}
136
+
44
if (fpst->default_nan_mode) {
137
+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
45
nan = float32_default_nan(fpst);
138
if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
139
val |= (1 << 8);
47
float64 nan = a;
48
if (float64_is_signaling_nan(a, fpst)) {
49
float_raise(float_flag_invalid, fpst);
50
- nan = float64_silence_nan(a, fpst);
51
+ if (!fpst->default_nan_mode) {
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
140
}
54
}
141
- if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
55
if (fpst->default_nan_mode) {
142
- val |= (1 << 10);
56
nan = float64_default_nan(fpst);
143
- }
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
144
- if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
58
index XXXXXXX..XXXXXXX 100644
145
- val |= (1 << 11);
59
--- a/target/arm/vfp_helper.c
146
- }
60
+++ b/target/arm/vfp_helper.c
147
- if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
148
- val |= (1 << 12);
62
float16 nan = f16;
149
- }
63
if (float16_is_signaling_nan(f16, fpst)) {
150
- if (s->vectors[ARMV7M_EXCP_MEM].pending) {
64
float_raise(float_flag_invalid, fpst);
151
- val |= (1 << 13);
65
- nan = float16_silence_nan(f16, fpst);
152
- }
66
+ if (!fpst->default_nan_mode) {
153
- if (s->vectors[ARMV7M_EXCP_BUS].pending) {
67
+ nan = float16_silence_nan(f16, fpst);
154
- val |= (1 << 14);
155
- }
156
- if (s->vectors[ARMV7M_EXCP_SVC].pending) {
157
- val |= (1 << 15);
158
- }
159
- if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
160
- val |= (1 << 16);
161
- }
162
- if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
163
- val |= (1 << 17);
164
- }
165
- if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
166
- val |= (1 << 18);
167
- }
168
return val;
169
case 0xd28: /* Configurable Fault Status. */
170
/* The BFSR bits [15:8] are shared between security states
171
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
172
173
cpu->env.v7m.ccr[attrs.secure] = value;
174
break;
175
- case 0xd24: /* System Handler Control. */
176
- s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
177
- s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
178
- s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
179
- s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
180
+ case 0xd24: /* System Handler Control and State (SHCSR) */
181
+ if (attrs.secure) {
182
+ s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
183
+ /* Secure HardFault active bit cannot be written */
184
+ s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
185
+ s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
186
+ s->sec_vectors[ARMV7M_EXCP_PENDSV].active =
187
+ (value & (1 << 10)) != 0;
188
+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =
189
+ (value & (1 << 11)) != 0;
190
+ s->sec_vectors[ARMV7M_EXCP_USAGE].pending =
191
+ (value & (1 << 12)) != 0;
192
+ s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
193
+ s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
194
+ s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
195
+ s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
196
+ s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
197
+ (value & (1 << 18)) != 0;
198
+ /* SecureFault not banked, but RAZ/WI to NS */
199
+ s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
200
+ s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
201
+ s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;
202
+ } else {
203
+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
204
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
205
+ /* HARDFAULTPENDED is not present in v7M */
206
+ s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
207
+ }
68
+ }
208
+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
69
}
209
+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
70
if (fpst->default_nan_mode) {
210
+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
71
nan = float16_default_nan(fpst);
211
+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
212
+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
73
float32 nan = f32;
213
+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
74
if (float32_is_signaling_nan(f32, fpst)) {
214
+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
75
float_raise(float_flag_invalid, fpst);
215
+ s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
76
- nan = float32_silence_nan(f32, fpst);
216
+ s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
77
+ if (!fpst->default_nan_mode) {
217
+ }
78
+ nan = float32_silence_nan(f32, fpst);
218
+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
79
+ }
219
+ s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
80
}
220
+ s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
81
if (fpst->default_nan_mode) {
221
+ s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
82
nan = float32_default_nan(fpst);
222
+ }
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
223
+ /* NMIACT can only be written if the write is of a zero, with
84
float64 nan = f64;
224
+ * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
85
if (float64_is_signaling_nan(f64, fpst)) {
225
+ */
86
float_raise(float_flag_invalid, fpst);
226
+ if (!attrs.secure && cpu->env.v7m.secure &&
87
- nan = float64_silence_nan(f64, fpst);
227
+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
88
+ if (!fpst->default_nan_mode) {
228
+ (value & (1 << 5)) == 0) {
89
+ nan = float64_silence_nan(f64, fpst);
229
+ s->vectors[ARMV7M_EXCP_NMI].active = 0;
90
+ }
230
+ }
91
}
231
+ /* HARDFAULTACT can only be written if the write is of a zero
92
if (fpst->default_nan_mode) {
232
+ * to the non-secure HardFault state by the CPU in secure state.
93
nan = float64_default_nan(fpst);
233
+ * The only case where we can be targeting the non-secure HF state
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
234
+ * when in secure state is if this is a write via the NS alias
95
float16 nan = f16;
235
+ * and BFHFNMINS is 1.
96
if (float16_is_signaling_nan(f16, s)) {
236
+ */
97
float_raise(float_flag_invalid, s);
237
+ if (!attrs.secure && cpu->env.v7m.secure &&
98
- nan = float16_silence_nan(f16, s);
238
+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
99
+ if (!s->default_nan_mode) {
239
+ (value & (1 << 2)) == 0) {
100
+ nan = float16_silence_nan(f16, fpstp);
240
+ s->vectors[ARMV7M_EXCP_HARD].active = 0;
101
+ }
241
+ }
102
}
242
+
103
if (s->default_nan_mode) {
243
+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
104
nan = float16_default_nan(s);
244
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
245
- s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
106
float32 nan = f32;
246
- s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
107
if (float32_is_signaling_nan(f32, s)) {
247
- s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
108
float_raise(float_flag_invalid, s);
248
- s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
109
- nan = float32_silence_nan(f32, s);
249
- s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
110
+ if (!s->default_nan_mode) {
250
- s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
111
+ nan = float32_silence_nan(f32, fpstp);
251
- s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
112
+ }
252
- s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
113
}
253
- s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
114
if (s->default_nan_mode) {
254
nvic_irq_update(s);
115
nan = float32_default_nan(s);
255
break;
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
256
case 0xd28: /* Configurable Fault Status. */
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
257
--
127
--
258
2.7.4
128
2.20.1
259
129
260
130
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/31] hw/arm/omap2.c: Don't use old_mmio
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
Don't use old_mmio in the memory region ops struct.
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
function has to be used for machine shutdown. Otherwise we cause
5
a reset with a bogus "cause" value, when we intended a shutdown.
6
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
10
[PMM: tweaked commit message]
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-7-git-send-email-peter.maydell@linaro.org
6
---
12
---
7
hw/arm/omap2.c | 49 +++++++++++++++++++++++++++++++++++++------------
13
hw/gpio/gpio_pwr.c | 2 +-
8
1 file changed, 37 insertions(+), 12 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
9
15
10
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
11
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/arm/omap2.c
18
--- a/hw/gpio/gpio_pwr.c
13
+++ b/hw/arm/omap2.c
19
+++ b/hw/gpio/gpio_pwr.c
14
@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write(void *opaque, hwaddr addr,
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
22
{
23
if (level) {
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
15
}
26
}
16
}
27
}
17
28
18
+static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
19
+ unsigned size)
20
+{
21
+ switch (size) {
22
+ case 1:
23
+ return omap_sysctl_read8(opaque, addr);
24
+ case 2:
25
+ return omap_badwidth_read32(opaque, addr); /* TODO */
26
+ case 4:
27
+ return omap_sysctl_read(opaque, addr);
28
+ default:
29
+ g_assert_not_reached();
30
+ }
31
+}
32
+
33
+static void omap_sysctl_writefn(void *opaque, hwaddr addr,
34
+ uint64_t value, unsigned size)
35
+{
36
+ switch (size) {
37
+ case 1:
38
+ omap_sysctl_write8(opaque, addr, value);
39
+ break;
40
+ case 2:
41
+ omap_badwidth_write32(opaque, addr, value); /* TODO */
42
+ break;
43
+ case 4:
44
+ omap_sysctl_write(opaque, addr, value);
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
+}
50
+
51
static const MemoryRegionOps omap_sysctl_ops = {
52
- .old_mmio = {
53
- .read = {
54
- omap_sysctl_read8,
55
- omap_badwidth_read32,    /* TODO */
56
- omap_sysctl_read,
57
- },
58
- .write = {
59
- omap_sysctl_write8,
60
- omap_badwidth_write32,    /* TODO */
61
- omap_sysctl_write,
62
- },
63
- },
64
+ .read = omap_sysctl_readfn,
65
+ .write = omap_sysctl_writefn,
66
+ .valid.min_access_size = 1,
67
+ .valid.max_access_size = 4,
68
.endianness = DEVICE_NATIVE_ENDIAN,
69
};
70
71
--
29
--
72
2.7.4
30
2.20.1
73
31
74
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/31] hw/timer/omap_synctimer.c: Don't use old_mmio
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
Don't use the old_mmio in the memory region ops struct.
1
In do_ldst(), the calculation of the offset needs to be based on the
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
2
5
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-4-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
6
---
9
---
7
hw/timer/omap_synctimer.c | 35 +++++++++++++++++++++--------------
10
target/arm/translate-mve.c | 17 +++++++++--------
8
1 file changed, 21 insertions(+), 14 deletions(-)
11
1 file changed, 9 insertions(+), 8 deletions(-)
9
12
10
diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
11
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/timer/omap_synctimer.c
15
--- a/target/arm/translate-mve.c
13
+++ b/hw/timer/omap_synctimer.c
16
+++ b/target/arm/translate-mve.c
14
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
15
}
18
}
16
}
19
}
17
20
18
-static void omap_synctimer_write(void *opaque, hwaddr addr,
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
19
- uint32_t value)
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
20
+static uint64_t omap_synctimer_readfn(void *opaque, hwaddr addr,
23
+ unsigned msize)
21
+ unsigned size)
22
+{
23
+ switch (size) {
24
+ case 1:
25
+ return omap_badwidth_read32(opaque, addr);
26
+ case 2:
27
+ return omap_synctimer_readh(opaque, addr);
28
+ case 4:
29
+ return omap_synctimer_readw(opaque, addr);
30
+ default:
31
+ g_assert_not_reached();
32
+ }
33
+}
34
+
35
+static void omap_synctimer_writefn(void *opaque, hwaddr addr,
36
+ uint64_t value, unsigned size)
37
{
24
{
38
OMAP_BAD_REG(addr);
25
TCGv_i32 addr;
26
uint32_t offset;
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
28
return true;
29
}
30
31
- offset = a->imm << a->size;
32
+ offset = a->imm << msize;
33
if (!a->a) {
34
offset = -offset;
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
38
{ NULL, NULL }
39
};
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
39
}
42
}
40
43
41
static const MemoryRegionOps omap_synctimer_ops = {
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
42
- .old_mmio = {
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
43
- .read = {
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
44
- omap_badwidth_read32,
47
{ \
45
- omap_synctimer_readh,
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
46
- omap_synctimer_readw,
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
47
- },
50
{ NULL, gen_helper_mve_##ULD }, \
48
- .write = {
51
}; \
49
- omap_badwidth_write32,
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
50
- omap_synctimer_write,
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
51
- omap_synctimer_write,
54
}
52
- },
55
53
- },
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
54
+ .read = omap_synctimer_readfn,
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
55
+ .write = omap_synctimer_writefn,
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
56
+ .valid.min_access_size = 1,
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
57
+ .valid.max_access_size = 4,
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
58
.endianness = DEVICE_NATIVE_ENDIAN,
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
59
};
62
60
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
61
--
65
--
62
2.7.4
66
2.20.1
63
67
64
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/31] nvic: Support banked exceptions in acknowledge and complete
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq()
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
to handle banked exceptions:
2
insns had some bugs:
3
* acknowledge needs to use the correct vector, which may be
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
in sec_vectors[]
4
not 32x32->64
5
* acknowledge needs to return to its caller whether the
5
* we were incorrectly maintaining the accumulator in its full
6
exception should be taken to secure or non-secure state
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
* complete needs its caller to tell it whether the exception
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
being completed is a secure one or not
8
registers after each beat
9
9
10
In particular, fixing the second of these allows us to recast
11
the implementation to avoid 128-bit arithmetic entirely.
12
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
13
---
20
---
14
target/arm/cpu.h | 15 +++++++++++++--
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
15
hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++++------
22
1 file changed, 21 insertions(+), 17 deletions(-)
16
target/arm/helper.c | 8 +++++---
17
hw/intc/trace-events | 4 ++--
18
4 files changed, 40 insertions(+), 13 deletions(-)
19
23
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
21
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
26
--- a/target/arm/mve_helper.c
23
+++ b/target/arm/cpu.h
27
+++ b/target/arm/mve_helper.c
24
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
28
@@ -XXX,XX +XXX,XX @@
25
* of architecturally banked exceptions.
26
*/
29
*/
27
void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
30
28
-void armv7m_nvic_acknowledge_irq(void *opaque);
31
#include "qemu/osdep.h"
29
+/**
32
-#include "qemu/int128.h"
30
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
33
#include "cpu.h"
31
+ * @opaque: the NVIC
34
#include "internals.h"
32
+ *
35
#include "vec_internal.h"
33
+ * Move the current highest priority pending exception from the pending
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
34
+ * state to the active state, and update v7m.exception to indicate that
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
35
+ * it is the exception currently being handled.
38
36
+ *
39
/*
37
+ * Returns: true if exception should be taken to Secure state, false for NS
40
- * Rounding multiply add long dual accumulate high: we must keep
38
+ */
41
- * a 72-bit internal accumulator value and return the top 64 bits.
39
+bool armv7m_nvic_acknowledge_irq(void *opaque);
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
40
/**
43
+ * this is implemented with a 72-bit internal accumulator value of which
41
* armv7m_nvic_complete_irq: complete specified interrupt or exception
44
+ * the top 64 bits are returned. We optimize this to avoid having to
42
* @opaque: the NVIC
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
43
* @irq: the exception number to complete
46
+ * is squashed back into 64-bits after each beat.
44
+ * @secure: true if this exception was secure
45
*
46
* Returns: -1 if the irq was not active
47
* 1 if completing this irq brought us back to base (no active irqs)
48
* 0 if there is still an irq active after this one was completed
49
* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
50
*/
47
*/
51
-int armv7m_nvic_complete_irq(void *opaque, int irq);
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
52
+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
53
/**
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
54
* armv7m_nvic_raw_execution_priority: return the raw execution priority
51
void *vm, uint64_t a) \
55
* @opaque: the NVIC
52
{ \
56
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
53
uint16_t mask = mve_element_mask(env); \
57
index XXXXXXX..XXXXXXX 100644
54
unsigned e; \
58
--- a/hw/intc/armv7m_nvic.c
55
TYPE *n = vn, *m = vm; \
59
+++ b/hw/intc/armv7m_nvic.c
56
- Int128 acc = int128_lshift(TO128(a), 8); \
60
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
61
}
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
59
if (mask & 1) { \
63
/* Make pending IRQ active. */
60
+ LTYPE mul; \
64
-void armv7m_nvic_acknowledge_irq(void *opaque)
61
if (e & 1) { \
65
+bool armv7m_nvic_acknowledge_irq(void *opaque)
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
66
{
63
- m[H##ESIZE(e)])); \
67
NVICState *s = (NVICState *)opaque;
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
68
CPUARMState *env = &s->cpu->env;
65
+ if (SUB) { \
69
const int pending = s->vectpending;
66
+ mul = -mul; \
70
const int running = nvic_exec_prio(s);
67
+ } \
71
VecInfo *vec;
68
} else { \
72
+ bool targets_secure;
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
73
70
- m[H##ESIZE(e)])); \
74
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
75
72
} \
76
- vec = &s->vectors[pending];
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
77
+ if (s->vectpending_is_s_banked) {
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
78
+ vec = &s->sec_vectors[pending];
75
+ a += mul; \
79
+ targets_secure = true;
76
} \
80
+ } else {
77
} \
81
+ vec = &s->vectors[pending];
78
mve_advance_vpt(env); \
82
+ targets_secure = !exc_is_banked(s->vectpending) &&
79
- return int128_getlo(int128_rshift(acc, 8)); \
83
+ exc_targets_secure(s, s->vectpending);
80
+ return a; \
84
+ }
85
86
assert(vec->enabled);
87
assert(vec->pending);
88
89
assert(s->vectpending_prio < running);
90
91
- trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
92
+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio, targets_secure);
93
94
vec->active = 1;
95
vec->pending = 0;
96
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
97
env->v7m.exception = s->vectpending;
98
99
nvic_irq_update(s);
100
+
101
+ return targets_secure;
102
}
103
104
-int armv7m_nvic_complete_irq(void *opaque, int irq)
105
+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
106
{
107
NVICState *s = (NVICState *)opaque;
108
VecInfo *vec;
109
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq)
110
111
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
112
113
- vec = &s->vectors[irq];
114
+ if (secure && exc_is_banked(irq)) {
115
+ vec = &s->sec_vectors[irq];
116
+ } else {
117
+ vec = &s->vectors[irq];
118
+ }
119
120
- trace_nvic_complete_irq(irq);
121
+ trace_nvic_complete_irq(irq, secure);
122
123
if (!vec->active) {
124
/* Tell the caller this was an illegal exception return */
125
diff --git a/target/arm/helper.c b/target/arm/helper.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/target/arm/helper.c
128
+++ b/target/arm/helper.c
129
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
130
bool return_to_sp_process = false;
131
bool return_to_handler = false;
132
bool rettobase = false;
133
+ bool exc_secure = false;
134
135
/* We can only get here from an EXCP_EXCEPTION_EXIT, and
136
* gen_bx_excret() enforces the architectural rule
137
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
138
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
139
*/
140
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
141
- int es = excret & R_V7M_EXCRET_ES_MASK;
142
+ exc_secure = excret & R_V7M_EXCRET_ES_MASK;
143
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
144
- env->v7m.faultmask[es] = 0;
145
+ env->v7m.faultmask[exc_secure] = 0;
146
}
147
} else {
148
env->v7m.faultmask[M_REG_NS] = 0;
149
}
150
}
81
}
151
82
152
- switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
153
+ switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception,
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
154
+ exc_secure)) {
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
155
case -1:
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
156
/* attempt to exit an exception that isn't active */
87
157
ufault = true;
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
158
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
159
index XXXXXXX..XXXXXXX 100644
90
160
--- a/hw/intc/trace-events
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
161
+++ b/hw/intc/trace-events
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
162
@@ -XXX,XX +XXX,XX @@ nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
163
nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
164
nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
95
165
nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
96
/* Vector add across vector */
166
-nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
97
#define DO_VADDV(OP, ESIZE, TYPE) \
167
-nvic_complete_irq(int irq) "NVIC complete IRQ %d"
168
+nvic_acknowledge_irq(int irq, int prio, bool targets_secure) "NVIC acknowledge IRQ: %d now active (prio %d targets_secure %d)"
169
+nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
170
nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
171
nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
172
nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
173
--
98
--
174
2.7.4
99
2.20.1
175
100
176
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/31] hw/arm/palm.c: Don't use old_mmio for static_ops
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
Update the static_ops functions to use new-style mmio
1
The function asimd_imm_const() in translate-neon.c is an
2
rather than the legacy old_mmio functions.
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
3
5
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505580378-9044-2-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
7
---
9
---
8
hw/arm/palm.c | 30 ++++++++++--------------------
10
target/arm/translate.h | 16 ++++++++++
9
1 file changed, 10 insertions(+), 20 deletions(-)
11
target/arm/translate-neon.c | 63 -------------------------------------
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
10
14
11
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/palm.c
17
--- a/target/arm/translate.h
14
+++ b/hw/arm/palm.c
18
+++ b/target/arm/translate.h
15
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
16
#include "exec/address-spaces.h"
20
return opc | s->be_data;
17
#include "cpu.h"
21
}
18
22
19
-static uint32_t static_readb(void *opaque, hwaddr offset)
23
+/**
20
+static uint64_t static_read(void *opaque, hwaddr offset, unsigned size)
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
21
{
25
+ *
22
- uint32_t *val = (uint32_t *) opaque;
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
23
- return *val >> ((offset & 3) << 3);
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
24
-}
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
25
+ uint32_t *val = (uint32_t *)opaque;
29
+ *
26
+ uint32_t sizemask = 7 >> size;
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
27
31
+ * callers must catch this.
28
-static uint32_t static_readh(void *opaque, hwaddr offset)
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
29
-{
49
-{
30
- uint32_t *val = (uint32_t *) opaque;
50
- /*
31
- return *val >> ((offset & 1) << 3);
51
- * Expand the encoded constant.
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
32
-}
109
-}
33
-
110
-
34
-static uint32_t static_readw(void *opaque, hwaddr offset)
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
35
-{
112
GVecGen2iFn *fn)
36
- uint32_t *val = (uint32_t *) opaque;
113
{
37
- return *val >> ((offset & 0) << 3);
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
38
+ return *val >> ((offset & sizemask) << 3);
115
index XXXXXXX..XXXXXXX 100644
116
--- a/target/arm/translate.c
117
+++ b/target/arm/translate.c
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
119
a64_translate_init();
39
}
120
}
40
121
41
-static void static_write(void *opaque, hwaddr offset,
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
42
- uint32_t value)
123
+{
43
+static void static_write(void *opaque, hwaddr offset, uint64_t value,
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
44
+ unsigned size)
125
+ switch (cmode) {
126
+ case 0: case 1:
127
+ /* no-op */
128
+ break;
129
+ case 2: case 3:
130
+ imm <<= 8;
131
+ break;
132
+ case 4: case 5:
133
+ imm <<= 16;
134
+ break;
135
+ case 6: case 7:
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
159
+ for (n = 0; n < 8; n++) {
160
+ if (imm & (1 << n)) {
161
+ imm64 |= (0xffULL << (n * 8));
162
+ }
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
45
{
181
{
46
#ifdef SPY
47
printf("%s: value %08lx written at " PA_FMT "\n",
48
@@ -XXX,XX +XXX,XX @@ static void static_write(void *opaque, hwaddr offset,
49
}
50
51
static const MemoryRegionOps static_ops = {
52
- .old_mmio = {
53
- .read = { static_readb, static_readh, static_readw, },
54
- .write = { static_write, static_write, static_write, },
55
- },
56
+ .read = static_read,
57
+ .write = static_write,
58
+ .valid.min_access_size = 1,
59
+ .valid.max_access_size = 4,
60
.endianness = DEVICE_NATIVE_ENDIAN,
61
};
62
63
--
182
--
64
2.7.4
183
2.20.1
65
184
66
185
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
preempt execution. The simple way to achieve this is to clear the
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
enable bit for it, since the enable bit isn't guest visible.
4
reimplementing it all.
5
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
9
---
9
---
10
hw/intc/armv7m_nvic.c | 12 ++++++++++--
10
target/arm/translate.h | 3 +-
11
1 file changed, 10 insertions(+), 2 deletions(-)
11
target/arm/translate-a64.c | 86 ++++----------------------------------
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
12
14
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/armv7m_nvic.c
17
--- a/target/arm/translate.h
16
+++ b/hw/intc/armv7m_nvic.c
18
+++ b/target/arm/translate.h
17
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
18
(R_V7M_AIRCR_SYSRESETREQS_MASK |
20
* VMVN and VBIC (when cmode < 14 && op == 1).
19
R_V7M_AIRCR_BFHFNMINS_MASK |
21
*
20
R_V7M_AIRCR_PRIS_MASK);
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
21
- /* BFHFNMINS changes the priority of Secure HardFault */
23
- * callers must catch this.
22
+ /* BFHFNMINS changes the priority of Secure HardFault, and
24
+ * callers must catch this; we return the 64-bit constant value defined
23
+ * allows a pending Non-secure HardFault to preempt (which
25
+ * for AArch64.
24
+ * we implement by marking it enabled).
26
*
25
+ */
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
26
if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
27
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
28
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
30
index XXXXXXX..XXXXXXX 100644
29
} else {
31
--- a/target/arm/translate-a64.c
30
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
32
+++ b/target/arm/translate-a64.c
31
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
32
}
34
{
33
}
35
int rd = extract32(insn, 0, 5);
34
nvic_irq_update(s);
36
int cmode = extract32(insn, 12, 4);
35
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
37
- int cmode_3_1 = extract32(cmode, 1, 3);
36
NVICState *s = NVIC(dev);
38
- int cmode_0 = extract32(cmode, 0, 1);
37
39
int o2 = extract32(insn, 11, 1);
38
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
39
- s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
41
bool is_neg = extract32(insn, 29, 1);
40
/* MEM, BUS, and USAGE are enabled through
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
41
* the System Handler Control register
43
return;
42
*/
44
}
43
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
45
44
46
- /* See AdvSIMDExpandImm() in ARM ARM */
45
/* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
47
- switch (cmode_3_1) {
46
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
47
+ /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
48
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
52
- {
53
- int shift = cmode_3_1 * 8;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
55
- break;
56
- }
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
120
-
121
- if (cmode_3_1 != 7 && is_neg) {
122
- imm = ~imm;
123
+ if (cmode == 15 && o2 && !is_neg) {
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
49
+ } else {
128
+ } else {
50
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
51
}
130
}
52
131
53
/* Strictly speaking the reset handler should be enabled.
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/target/arm/translate.c
136
+++ b/target/arm/translate.c
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
138
case 14:
139
if (op) {
140
/*
141
- * This is the only case where the top and bottom 32 bits
142
- * of the encoded constant differ.
143
+ * This and cmode == 15 op == 1 are the only cases where
144
+ * the top and bottom 32 bits of the encoded constant differ.
145
*/
146
uint64_t imm64 = 0;
147
int n;
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
150
break;
151
case 15:
152
+ if (op) {
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
155
+ if (imm & 0x80) {
156
+ imm64 |= 0x8000000000000000ULL;
157
+ }
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
54
--
168
--
55
2.7.4
169
2.20.1
56
170
57
171
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/31] target/arm: Remove out of date ARM ARM section references in A64 decoder
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
In the A64 decoder, we have a lot of references to section numbers
1
Use dup_const() instead of bitfield_replicate() in
2
from version A.a of the v8A ARM ARM (DDI0487). This version of the
2
disas_simd_mod_imm().
3
document is now long obsolete (we are currently on revision B.a),
4
and various intervening versions renumbered all the sections.
5
3
6
The most recent B.a version of the document doesn't assign
4
(We can't replace the other use of bitfield_replicate() in this file,
7
section numbers at all to the individual instruction classes
5
in logic_imm_decode_wmask(), because that location needs to handle 2
8
in the way that the various A.x versions did. The simplest thing
6
and 4 bit elements, which dup_const() cannot.)
9
to do is just to delete all the out of date C.x.x references.
10
7
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20170915150849.23557-1-peter.maydell@linaro.org
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
14
---
11
---
15
target/arm/translate-a64.c | 227 +++++++++++++++++++++++----------------------
12
target/arm/translate-a64.c | 2 +-
16
1 file changed, 114 insertions(+), 113 deletions(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
17
14
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
21
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
22
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
23
}
20
/* FMOV (vector, immediate) - half-precision */
24
21
imm = vfp_expand_imm(MO_16, abcdefgh);
25
/*
22
/* now duplicate across the lanes */
26
- * the instruction disassembly implemented here matches
23
- imm = bitfield_replicate(imm, 16);
27
- * the instruction encoding classifications in chapter 3 (C3)
24
+ imm = dup_const(MO_16, imm);
28
- * of the ARM Architecture Reference Manual (DDI0487A_a)
25
} else {
29
+ * The instruction disassembly implemented here matches
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
30
+ * the instruction encoding classifications in chapter C4
31
+ * of the ARM Architecture Reference Manual (DDI0487B_a);
32
+ * classification names and decode diagrams here should generally
33
+ * match up with those in the manual.
34
*/
35
36
-/* C3.2.7 Unconditional branch (immediate)
37
+/* Unconditional branch (immediate)
38
* 31 30 26 25 0
39
* +----+-----------+-------------------------------------+
40
* | op | 0 0 1 0 1 | imm26 |
41
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
42
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
43
44
if (insn & (1U << 31)) {
45
- /* C5.6.26 BL Branch with link */
46
+ /* BL Branch with link */
47
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
48
}
27
}
49
50
- /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
51
+ /* B Branch / BL Branch with link */
52
gen_goto_tb(s, 0, addr);
53
}
54
55
-/* C3.2.1 Compare & branch (immediate)
56
+/* Compare and branch (immediate)
57
* 31 30 25 24 23 5 4 0
58
* +----+-------------+----+---------------------+--------+
59
* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
60
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
61
gen_goto_tb(s, 1, addr);
62
}
63
64
-/* C3.2.5 Test & branch (immediate)
65
+/* Test and branch (immediate)
66
* 31 30 25 24 23 19 18 5 4 0
67
* +----+-------------+----+-------+-------------+------+
68
* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
69
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
70
gen_goto_tb(s, 1, addr);
71
}
72
73
-/* C3.2.2 / C5.6.19 Conditional branch (immediate)
74
+/* Conditional branch (immediate)
75
* 31 25 24 23 5 4 3 0
76
* +---------------+----+---------------------+----+------+
77
* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
78
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
79
}
80
}
81
82
-/* C5.6.68 HINT */
83
+/* HINT instruction group, including various allocated HINTs */
84
static void handle_hint(DisasContext *s, uint32_t insn,
85
unsigned int op1, unsigned int op2, unsigned int crm)
86
{
87
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
88
}
89
}
90
91
-/* C5.6.130 MSR (immediate) - move immediate to processor state field */
92
+/* MSR (immediate) - move immediate to processor state field */
93
static void handle_msr_i(DisasContext *s, uint32_t insn,
94
unsigned int op1, unsigned int op2, unsigned int crm)
95
{
96
@@ -XXX,XX +XXX,XX @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
97
tcg_temp_free_i32(nzcv);
98
}
99
100
-/* C5.6.129 MRS - move from system register
101
- * C5.6.131 MSR (register) - move to system register
102
- * C5.6.204 SYS
103
- * C5.6.205 SYSL
104
+/* MRS - move from system register
105
+ * MSR (register) - move to system register
106
+ * SYS
107
+ * SYSL
108
* These are all essentially the same insn in 'read' and 'write'
109
* versions, with varying op0 fields.
110
*/
111
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
112
}
113
}
114
115
-/* C3.2.4 System
116
+/* System
117
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
118
* +---------------------+---+-----+-----+-------+-------+-----+------+
119
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
120
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
121
return;
122
}
123
switch (crn) {
124
- case 2: /* C5.6.68 HINT */
125
+ case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
126
handle_hint(s, insn, op1, op2, crm);
127
break;
128
case 3: /* CLREX, DSB, DMB, ISB */
129
handle_sync(s, insn, op1, op2, crm);
130
break;
131
- case 4: /* C5.6.130 MSR (immediate) */
132
+ case 4: /* MSR (immediate) */
133
handle_msr_i(s, insn, op1, op2, crm);
134
break;
135
default:
136
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
137
handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
138
}
139
140
-/* C3.2.3 Exception generation
141
+/* Exception generation
142
*
143
* 31 24 23 21 20 5 4 2 1 0
144
* +-----------------+-----+------------------------+-----+----+
145
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
146
}
147
}
148
149
-/* C3.2.7 Unconditional branch (register)
150
+/* Unconditional branch (register)
151
* 31 25 24 21 20 16 15 10 9 5 4 0
152
* +---------------+-------+-------+-------+------+-------+
153
* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
154
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
155
s->base.is_jmp = DISAS_JUMP;
156
}
157
158
-/* C3.2 Branches, exception generating and system instructions */
159
+/* Branches, exception generating and system instructions */
160
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
161
{
162
switch (extract32(insn, 25, 7)) {
163
@@ -XXX,XX +XXX,XX @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
164
return regsize == 64;
165
}
166
167
-/* C3.3.6 Load/store exclusive
168
+/* Load/store exclusive
169
*
170
* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
171
* +-----+-------------+----+---+----+------+----+-------+------+------+
172
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
173
}
174
175
/*
176
- * C3.3.5 Load register (literal)
177
+ * Load register (literal)
178
*
179
* 31 30 29 27 26 25 24 23 5 4 0
180
* +-----+-------+---+-----+-------------------+-------+
181
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
182
}
183
184
/*
185
- * C5.6.80 LDNP (Load Pair - non-temporal hint)
186
- * C5.6.81 LDP (Load Pair - non vector)
187
- * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
188
- * C5.6.176 STNP (Store Pair - non-temporal hint)
189
- * C5.6.177 STP (Store Pair - non vector)
190
- * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
191
- * C6.3.165 LDP (Load Pair of SIMD&FP)
192
- * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
193
- * C6.3.284 STP (Store Pair of SIMD&FP)
194
+ * LDNP (Load Pair - non-temporal hint)
195
+ * LDP (Load Pair - non vector)
196
+ * LDPSW (Load Pair Signed Word - non vector)
197
+ * STNP (Store Pair - non-temporal hint)
198
+ * STP (Store Pair - non vector)
199
+ * LDNP (Load Pair of SIMD&FP - non-temporal hint)
200
+ * LDP (Load Pair of SIMD&FP)
201
+ * STNP (Store Pair of SIMD&FP - non-temporal hint)
202
+ * STP (Store Pair of SIMD&FP)
203
*
204
* 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
205
* +-----+-------+---+---+-------+---+-----------------------------+
206
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
207
}
208
209
/*
210
- * C3.3.8 Load/store (immediate post-indexed)
211
- * C3.3.9 Load/store (immediate pre-indexed)
212
- * C3.3.12 Load/store (unscaled immediate)
213
+ * Load/store (immediate post-indexed)
214
+ * Load/store (immediate pre-indexed)
215
+ * Load/store (unscaled immediate)
216
*
217
* 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
218
* +----+-------+---+-----+-----+---+--------+-----+------+------+
219
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
220
}
221
222
/*
223
- * C3.3.10 Load/store (register offset)
224
+ * Load/store (register offset)
225
*
226
* 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
227
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
228
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
229
}
230
231
/*
232
- * C3.3.13 Load/store (unsigned immediate)
233
+ * Load/store (unsigned immediate)
234
*
235
* 31 30 29 27 26 25 24 23 22 21 10 9 5
236
* +----+-------+---+-----+-----+------------+-------+------+
237
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
238
}
239
}
240
241
-/* C3.3.1 AdvSIMD load/store multiple structures
242
+/* AdvSIMD load/store multiple structures
243
*
244
* 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
245
* +---+---+---------------+---+-------------+--------+------+------+------+
246
* | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
247
* +---+---+---------------+---+-------------+--------+------+------+------+
248
*
249
- * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
250
+ * AdvSIMD load/store multiple structures (post-indexed)
251
*
252
* 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
253
* +---+---+---------------+---+---+---------+--------+------+------+------+
254
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
255
tcg_temp_free_i64(tcg_addr);
256
}
257
258
-/* C3.3.3 AdvSIMD load/store single structure
259
+/* AdvSIMD load/store single structure
260
*
261
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
262
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
263
* | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
264
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
265
*
266
- * C3.3.4 AdvSIMD load/store single structure (post-indexed)
267
+ * AdvSIMD load/store single structure (post-indexed)
268
*
269
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
270
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
271
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
272
tcg_temp_free_i64(tcg_addr);
273
}
274
275
-/* C3.3 Loads and stores */
276
+/* Loads and stores */
277
static void disas_ldst(DisasContext *s, uint32_t insn)
278
{
279
switch (extract32(insn, 24, 6)) {
280
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
281
}
282
}
283
284
-/* C3.4.6 PC-rel. addressing
285
+/* PC-rel. addressing
286
* 31 30 29 28 24 23 5 4 0
287
* +----+-------+-----------+-------------------+------+
288
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
289
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
290
}
291
292
/*
293
- * C3.4.1 Add/subtract (immediate)
294
+ * Add/subtract (immediate)
295
*
296
* 31 30 29 28 24 23 22 21 10 9 5 4 0
297
* +--+--+--+-----------+-----+-------------+-----+-----+
298
@@ -XXX,XX +XXX,XX @@ static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
299
return true;
300
}
301
302
-/* C3.4.4 Logical (immediate)
303
+/* Logical (immediate)
304
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
305
* +----+-----+-------------+---+------+------+------+------+
306
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
307
@@ -XXX,XX +XXX,XX @@ static void disas_logic_imm(DisasContext *s, uint32_t insn)
308
}
309
310
/*
311
- * C3.4.5 Move wide (immediate)
312
+ * Move wide (immediate)
313
*
314
* 31 30 29 28 23 22 21 20 5 4 0
315
* +--+-----+-------------+-----+----------------+------+
316
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
317
}
318
}
319
320
-/* C3.4.2 Bitfield
321
+/* Bitfield
322
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
323
* +----+-----+-------------+---+------+------+------+------+
324
* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
325
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
326
}
327
}
328
329
-/* C3.4.3 Extract
330
+/* Extract
331
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
332
* +----+------+-------------+---+----+------+--------+------+------+
333
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
334
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
335
}
336
}
337
338
-/* C3.4 Data processing - immediate */
339
+/* Data processing - immediate */
340
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
341
{
342
switch (extract32(insn, 23, 6)) {
343
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
344
}
345
}
346
347
-/* C3.5.10 Logical (shifted register)
348
+/* Logical (shifted register)
349
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
350
* +----+-----+-----------+-------+---+------+--------+------+------+
351
* | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
352
@@ -XXX,XX +XXX,XX @@ static void disas_logic_reg(DisasContext *s, uint32_t insn)
353
}
354
355
/*
356
- * C3.5.1 Add/subtract (extended register)
357
+ * Add/subtract (extended register)
358
*
359
* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
360
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
361
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
362
}
363
364
/*
365
- * C3.5.2 Add/subtract (shifted register)
366
+ * Add/subtract (shifted register)
367
*
368
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
369
* +--+--+--+-----------+-----+--+-------+---------+------+------+
370
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
371
tcg_temp_free_i64(tcg_result);
372
}
373
374
-/* C3.5.9 Data-processing (3 source)
375
-
376
- 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
377
- +--+------+-----------+------+------+----+------+------+------+
378
- |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
379
- +--+------+-----------+------+------+----+------+------+------+
380
-
381
+/* Data-processing (3 source)
382
+ *
383
+ * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
384
+ * +--+------+-----------+------+------+----+------+------+------+
385
+ * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
386
+ * +--+------+-----------+------+------+----+------+------+------+
387
*/
388
static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
389
{
390
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
391
tcg_temp_free_i64(tcg_tmp);
392
}
393
394
-/* C3.5.3 - Add/subtract (with carry)
395
+/* Add/subtract (with carry)
396
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
397
* +--+--+--+------------------------+------+---------+------+-----+
398
* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
399
@@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
400
}
401
}
402
403
-/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
404
+/* Conditional compare (immediate / register)
405
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
406
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
407
* |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
408
@@ -XXX,XX +XXX,XX @@ static void disas_cc(DisasContext *s, uint32_t insn)
409
tcg_temp_free_i32(tcg_t2);
410
}
411
412
-/* C3.5.6 Conditional select
413
+/* Conditional select
414
* 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
415
* +----+----+---+-----------------+------+------+-----+------+------+
416
* | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
417
@@ -XXX,XX +XXX,XX @@ static void handle_rbit(DisasContext *s, unsigned int sf,
418
}
419
}
420
421
-/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
422
+/* REV with sf==1, opcode==3 ("REV64") */
423
static void handle_rev64(DisasContext *s, unsigned int sf,
424
unsigned int rn, unsigned int rd)
425
{
426
@@ -XXX,XX +XXX,XX @@ static void handle_rev64(DisasContext *s, unsigned int sf,
427
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
428
}
429
430
-/* C5.6.149 REV with sf==0, opcode==2
431
- * C5.6.151 REV32 (sf==1, opcode==2)
432
+/* REV with sf==0, opcode==2
433
+ * REV32 (sf==1, opcode==2)
434
*/
435
static void handle_rev32(DisasContext *s, unsigned int sf,
436
unsigned int rn, unsigned int rd)
437
@@ -XXX,XX +XXX,XX @@ static void handle_rev32(DisasContext *s, unsigned int sf,
438
}
439
}
440
441
-/* C5.6.150 REV16 (opcode==1) */
442
+/* REV16 (opcode==1) */
443
static void handle_rev16(DisasContext *s, unsigned int sf,
444
unsigned int rn, unsigned int rd)
445
{
446
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
447
tcg_temp_free_i64(tcg_tmp);
448
}
449
450
-/* C3.5.7 Data-processing (1 source)
451
+/* Data-processing (1 source)
452
* 31 30 29 28 21 20 16 15 10 9 5 4 0
453
* +----+---+---+-----------------+---------+--------+------+------+
454
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
455
@@ -XXX,XX +XXX,XX @@ static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
456
}
457
}
458
459
-/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
460
+/* LSLV, LSRV, ASRV, RORV */
461
static void handle_shift_reg(DisasContext *s,
462
enum a64_shift_type shift_type, unsigned int sf,
463
unsigned int rm, unsigned int rn, unsigned int rd)
464
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
465
tcg_temp_free_i32(tcg_bytes);
466
}
467
468
-/* C3.5.8 Data-processing (2 source)
469
+/* Data-processing (2 source)
470
* 31 30 29 28 21 20 16 15 10 9 5 4 0
471
* +----+---+---+-----------------+------+--------+------+------+
472
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
473
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
474
}
475
}
476
477
-/* C3.5 Data processing - register */
478
+/* Data processing - register */
479
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
480
{
481
switch (extract32(insn, 24, 5)) {
482
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
483
tcg_temp_free_i64(tcg_flags);
484
}
485
486
-/* C3.6.22 Floating point compare
487
+/* Floating point compare
488
* 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
489
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
490
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
491
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
492
handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
493
}
494
495
-/* C3.6.23 Floating point conditional compare
496
+/* Floating point conditional compare
497
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
498
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
499
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
500
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
501
}
502
}
503
504
-/* C3.6.24 Floating point conditional select
505
+/* Floating point conditional select
506
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
507
* +---+---+---+-----------+------+---+------+------+-----+------+------+
508
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
509
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
510
tcg_temp_free_i64(t_true);
511
}
512
513
-/* C3.6.25 Floating-point data-processing (1 source) - single precision */
514
+/* Floating-point data-processing (1 source) - single precision */
515
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
516
{
517
TCGv_ptr fpst;
518
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
519
tcg_temp_free_i32(tcg_res);
520
}
521
522
-/* C3.6.25 Floating-point data-processing (1 source) - double precision */
523
+/* Floating-point data-processing (1 source) - double precision */
524
static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
525
{
526
TCGv_ptr fpst;
527
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
528
}
529
}
530
531
-/* C3.6.25 Floating point data-processing (1 source)
532
+/* Floating point data-processing (1 source)
533
* 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
534
* +---+---+---+-----------+------+---+--------+-----------+------+------+
535
* | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
536
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
537
}
538
}
539
540
-/* C3.6.26 Floating-point data-processing (2 source) - single precision */
541
+/* Floating-point data-processing (2 source) - single precision */
542
static void handle_fp_2src_single(DisasContext *s, int opcode,
543
int rd, int rn, int rm)
544
{
545
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
546
tcg_temp_free_i32(tcg_res);
547
}
548
549
-/* C3.6.26 Floating-point data-processing (2 source) - double precision */
550
+/* Floating-point data-processing (2 source) - double precision */
551
static void handle_fp_2src_double(DisasContext *s, int opcode,
552
int rd, int rn, int rm)
553
{
554
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
555
tcg_temp_free_i64(tcg_res);
556
}
557
558
-/* C3.6.26 Floating point data-processing (2 source)
559
+/* Floating point data-processing (2 source)
560
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
561
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
562
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
563
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
564
}
565
}
566
567
-/* C3.6.27 Floating-point data-processing (3 source) - single precision */
568
+/* Floating-point data-processing (3 source) - single precision */
569
static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
570
int rd, int rn, int rm, int ra)
571
{
572
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
573
tcg_temp_free_i32(tcg_res);
574
}
575
576
-/* C3.6.27 Floating-point data-processing (3 source) - double precision */
577
+/* Floating-point data-processing (3 source) - double precision */
578
static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
579
int rd, int rn, int rm, int ra)
580
{
581
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
582
tcg_temp_free_i64(tcg_res);
583
}
584
585
-/* C3.6.27 Floating point data-processing (3 source)
586
+/* Floating point data-processing (3 source)
587
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
588
* +---+---+---+-----------+------+----+------+----+------+------+------+
589
* | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
590
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
591
}
592
}
593
594
-/* C3.6.28 Floating point immediate
595
+/* Floating point immediate
596
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
597
* +---+---+---+-----------+------+---+------------+-------+------+------+
598
* | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
599
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
600
tcg_temp_free_i32(tcg_shift);
601
}
602
603
-/* C3.6.29 Floating point <-> fixed point conversions
604
+/* Floating point <-> fixed point conversions
605
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
606
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
607
* | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
608
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
609
}
610
}
611
612
-/* C3.6.30 Floating point <-> integer conversions
613
+/* Floating point <-> integer conversions
614
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
615
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
616
* | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
617
@@ -XXX,XX +XXX,XX @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
618
tcg_temp_free_i64(tcg_tmp);
619
}
620
621
-/* C3.6.1 EXT
622
+/* EXT
623
* 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
624
* +---+---+-------------+-----+---+------+---+------+---+------+------+
625
* | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
626
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
627
tcg_temp_free_i64(tcg_resh);
628
}
629
630
-/* C3.6.2 TBL/TBX
631
+/* TBL/TBX
632
* 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
633
* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
634
* | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
635
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
636
tcg_temp_free_i64(tcg_resh);
637
}
638
639
-/* C3.6.3 ZIP/UZP/TRN
640
+/* ZIP/UZP/TRN
641
* 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
642
* +---+---+-------------+------+---+------+---+------------------+------+
643
* | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
644
@@ -XXX,XX +XXX,XX @@ static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
645
}
646
}
647
648
-/* C3.6.4 AdvSIMD across lanes
649
+/* AdvSIMD across lanes
650
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
651
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
652
* | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
653
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
654
tcg_temp_free_i64(tcg_res);
655
}
656
657
-/* C6.3.31 DUP (Element, Vector)
658
+/* DUP (Element, Vector)
659
*
660
* 31 30 29 21 20 16 15 10 9 5 4 0
661
* +---+---+-------------------+--------+-------------+------+------+
662
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
663
tcg_temp_free_i64(tmp);
664
}
665
666
-/* C6.3.31 DUP (element, scalar)
667
+/* DUP (element, scalar)
668
* 31 21 20 16 15 10 9 5 4 0
669
* +-----------------------+--------+-------------+------+------+
670
* | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
671
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupes(DisasContext *s, int rd, int rn,
672
tcg_temp_free_i64(tmp);
673
}
674
675
-/* C6.3.32 DUP (General)
676
+/* DUP (General)
677
*
678
* 31 30 29 21 20 16 15 10 9 5 4 0
679
* +---+---+-------------------+--------+-------------+------+------+
680
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
681
}
682
}
683
684
-/* C6.3.150 INS (Element)
685
+/* INS (Element)
686
*
687
* 31 21 20 16 15 14 11 10 9 5 4 0
688
* +-----------------------+--------+------------+---+------+------+
689
@@ -XXX,XX +XXX,XX @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
690
}
691
692
693
-/* C6.3.151 INS (General)
694
+/* INS (General)
695
*
696
* 31 21 20 16 15 10 9 5 4 0
697
* +-----------------------+--------+-------------+------+------+
698
@@ -XXX,XX +XXX,XX @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
699
}
700
701
/*
702
- * C6.3.321 UMOV (General)
703
- * C6.3.237 SMOV (General)
704
+ * UMOV (General)
705
+ * SMOV (General)
706
*
707
* 31 30 29 21 20 16 15 12 10 9 5 4 0
708
* +---+---+-------------------+--------+-------------+------+------+
709
@@ -XXX,XX +XXX,XX @@ static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
710
}
711
}
712
713
-/* C3.6.5 AdvSIMD copy
714
+/* AdvSIMD copy
715
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
716
* +---+---+----+-----------------+------+---+------+---+------+------+
717
* | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
718
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
719
}
720
}
721
722
-/* C3.6.6 AdvSIMD modified immediate
723
+/* AdvSIMD modified immediate
724
* 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
725
* +---+---+----+---------------------+-----+-------+----+---+-------+------+
726
* | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
727
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
728
tcg_temp_free_i64(tcg_imm);
729
}
730
731
-/* C3.6.7 AdvSIMD scalar copy
732
+/* AdvSIMD scalar copy
733
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
734
* +-----+----+-----------------+------+---+------+---+------+------+
735
* | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
736
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
737
handle_simd_dupes(s, rd, rn, imm5);
738
}
739
740
-/* C3.6.8 AdvSIMD scalar pairwise
741
+/* AdvSIMD scalar pairwise
742
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
743
* +-----+---+-----------+------+-----------+--------+-----+------+------+
744
* | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
745
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
746
tcg_temp_free_i32(tcg_rmode);
747
}
748
749
-/* C3.6.9 AdvSIMD scalar shift by immediate
750
+/* AdvSIMD scalar shift by immediate
751
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
752
* +-----+---+-------------+------+------+--------+---+------+------+
753
* | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
754
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
755
}
756
}
757
758
-/* C3.6.10 AdvSIMD scalar three different
759
+/* AdvSIMD scalar three different
760
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
761
* +-----+---+-----------+------+---+------+--------+-----+------+------+
762
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
763
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
764
}
765
}
766
767
-/* C3.6.11 AdvSIMD scalar three same
768
+/* AdvSIMD scalar three same
769
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
770
* +-----+---+-----------+------+---+------+--------+---+------+------+
771
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
772
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
773
}
774
}
775
776
-/* C3.6.12 AdvSIMD scalar two reg misc
777
+/* AdvSIMD scalar two reg misc
778
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
779
* +-----+---+-----------+------+-----------+--------+-----+------+------+
780
* | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
781
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
782
}
783
784
785
-/* C3.6.14 AdvSIMD shift by immediate
786
+/* AdvSIMD shift by immediate
787
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
788
* +---+---+---+-------------+------+------+--------+---+------+------+
789
* | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
790
@@ -XXX,XX +XXX,XX @@ static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
791
tcg_temp_free_i64(tcg_res);
792
}
793
794
-/* C3.6.15 AdvSIMD three different
795
+/* AdvSIMD three different
796
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
797
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
798
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
799
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
800
}
801
}
802
803
-/* C3.6.16 AdvSIMD three same
804
+/* AdvSIMD three same
805
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
806
* +---+---+---+-----------+------+---+------+--------+---+------+------+
807
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
808
@@ -XXX,XX +XXX,XX @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
809
}
810
}
811
812
-/* C3.6.17 AdvSIMD two reg misc
813
+/* AdvSIMD two reg misc
814
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
815
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
816
* | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
817
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
818
}
819
}
820
821
-/* C3.6.13 AdvSIMD scalar x indexed element
822
+/* AdvSIMD scalar x indexed element
823
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
824
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
825
* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
826
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
827
- * C3.6.18 AdvSIMD vector x indexed element
828
+ * AdvSIMD vector x indexed element
829
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
830
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
831
* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
832
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
833
}
834
}
835
836
-/* C3.6.19 Crypto AES
837
+/* Crypto AES
838
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
839
* +-----------------+------+-----------+--------+-----+------+------+
840
* | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
841
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
842
tcg_temp_free_i32(tcg_decrypt);
843
}
844
845
-/* C3.6.20 Crypto three-reg SHA
846
+/* Crypto three-reg SHA
847
* 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
848
* +-----------------+------+---+------+---+--------+-----+------+------+
849
* | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
850
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
851
tcg_temp_free_i32(tcg_rm_regno);
852
}
853
854
-/* C3.6.21 Crypto two-reg SHA
855
+/* Crypto two-reg SHA
856
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
857
* +-----------------+------+-----------+--------+-----+------+------+
858
* | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
859
--
28
--
860
2.7.4
29
2.20.1
861
30
862
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/31] nvic: Handle v8M changes in nvic_exec_prio()
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
Update nvic_exec_prio() to support the v8M changes:
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
* BASEPRI, FAULTMASK and PRIMASK are all banked
2
VORR and VBIC). These have essentially the same encoding
3
* AIRCR.PRIS can affect NS priorities
3
as their Neon equivalents, and we implement the decode
4
* AIRCR.BFHFNMINS affects FAULTMASK behaviour
4
in the same way.
5
6
These changes mean that it's no longer possible to
7
definitely say that if FAULTMASK is set it overrides
8
PRIMASK, and if PRIMASK is set it overrides BASEPRI
9
(since if PRIMASK_NS is set and AIRCR.PRIS is set then
10
whether that 0x80 priority should take effect or the
11
priority in BASEPRI_S depends on the value of BASEPRI_S,
12
for instance). So we switch to the same approach used
13
by the pseudocode of working through BASEPRI, PRIMASK
14
and FAULTMASK and overriding the previous values if
15
needed.
16
5
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 1505240046-11454-16-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
20
---
9
---
21
hw/intc/armv7m_nvic.c | 51 ++++++++++++++++++++++++++++++++++++++++++---------
10
target/arm/helper-mve.h | 4 +++
22
1 file changed, 42 insertions(+), 9 deletions(-)
11
target/arm/mve.decode | 17 +++++++++++++
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
23
15
24
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
25
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/intc/armv7m_nvic.c
18
--- a/target/arm/helper-mve.h
27
+++ b/hw/intc/armv7m_nvic.c
19
+++ b/target/arm/helper-mve.h
28
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
29
static inline int nvic_exec_prio(NVICState *s)
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
30
{
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
31
CPUARMState *env = &s->cpu->env;
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
32
- int running;
24
+
33
+ int running = NVIC_NOEXC_PRIO;
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
34
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
35
- if (env->v7m.faultmask[env->v7m.secure]) {
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
36
- running = -1;
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
37
- } else if (env->v7m.primask[env->v7m.secure]) {
29
index XXXXXXX..XXXXXXX 100644
38
+ if (env->v7m.basepri[M_REG_NS] > 0) {
30
--- a/target/arm/mve.decode
39
+ running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
31
+++ b/target/arm/mve.decode
32
@@ -XXX,XX +XXX,XX @@
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
34
%size_28 28:1 !function=plus_1
35
36
+# 1imm format immediate
37
+%imm_28_16_0 28:1 16:3 0:4
38
+
39
&vldr_vstr rn qd imm p a w size l u
40
&1op qd qm size
41
&2op qd qm qn size
42
&2scalar qd qn rm size
43
+&1imm qd imm cmode op
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
74
+++ b/target/arm/mve_helper.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
79
+/*
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
81
+ * All these insns work at 64-bit widths.
82
+ */
83
+#define DO_1OP_IMM(OP, FN) \
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
85
+ { \
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
40
+ }
93
+ }
41
+
94
+
42
+ if (env->v7m.basepri[M_REG_S] > 0) {
95
+#define DO_MOVI(N, I) (I)
43
+ int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
96
+#define DO_ANDI(N, I) ((N) & (I))
44
+ if (running > basepri) {
97
+#define DO_ORRI(N, I) ((N) | (I))
45
+ running = basepri;
98
+
46
+ }
99
+DO_1OP_IMM(vmovi, DO_MOVI)
100
+DO_1OP_IMM(vandi, DO_ANDI)
101
+DO_1OP_IMM(vorri, DO_ORRI)
102
+
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
122
+
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
124
+{
125
+ TCGv_ptr qd;
126
+ uint64_t imm;
127
+
128
+ if (!dc_isar_feature(aa32_mve, s) ||
129
+ !mve_check_qreg_bank(s, a->qd) ||
130
+ !fn) {
131
+ return false;
132
+ }
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ return true;
47
+ }
135
+ }
48
+
136
+
49
+ if (env->v7m.primask[M_REG_NS]) {
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
50
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
138
+
51
+ if (running > NVIC_NS_PRIO_LIMIT) {
139
+ qd = mve_qreg_ptr(a->qd);
52
+ running = NVIC_NS_PRIO_LIMIT;
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
53
+ }
141
+ tcg_temp_free_ptr(qd);
142
+ mve_update_eci(s);
143
+ return true;
144
+}
145
+
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
147
+{
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
150
+
151
+ if ((a->cmode & 1) && a->cmode < 12) {
152
+ if (a->op) {
153
+ /*
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
155
+ * so the VBIC becomes a logical AND operation.
156
+ */
157
+ fn = gen_helper_mve_vandi;
54
+ } else {
158
+ } else {
55
+ running = 0;
159
+ fn = gen_helper_mve_vorri;
56
+ }
160
+ }
161
+ } else {
162
+ /* There is one unallocated cmode/op combination in this space */
163
+ if (a->cmode == 15 && a->op == 1) {
164
+ return false;
165
+ }
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
167
+ fn = gen_helper_mve_vmovi;
57
+ }
168
+ }
58
+
169
+ return do_1imm(s, a, fn);
59
+ if (env->v7m.primask[M_REG_S]) {
170
+}
60
running = 0;
61
- } else if (env->v7m.basepri[env->v7m.secure] > 0) {
62
- running = env->v7m.basepri[env->v7m.secure] &
63
- nvic_gprio_mask(s, env->v7m.secure);
64
- } else {
65
- running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
66
}
67
+
68
+ if (env->v7m.faultmask[M_REG_NS]) {
69
+ if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
70
+ running = -1;
71
+ } else {
72
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
73
+ if (running > NVIC_NS_PRIO_LIMIT) {
74
+ running = NVIC_NS_PRIO_LIMIT;
75
+ }
76
+ } else {
77
+ running = 0;
78
+ }
79
+ }
80
+ }
81
+
82
+ if (env->v7m.faultmask[M_REG_S]) {
83
+ running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
84
+ }
85
+
86
/* consider priority of active handler */
87
return MIN(running, s->exception_prio);
88
}
89
--
171
--
90
2.7.4
172
2.20.1
91
173
92
174
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/31] hw/timer/omap_gptimer: Don't use old_mmio
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
Don't use the old_mmio struct in memory region ops.
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
and VQSHLU.
3
4
The size-and-immediate encoding here is the same as Neon, and we
5
handle it the same way neon-dp.decode does.
2
6
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
6
---
10
---
7
hw/timer/omap_gptimer.c | 49 +++++++++++++++++++++++++++++++++++++------------
11
target/arm/helper-mve.h | 16 +++++++++++
8
1 file changed, 37 insertions(+), 12 deletions(-)
12
target/arm/mve.decode | 23 +++++++++++++++
9
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
10
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
11
index XXXXXXX..XXXXXXX 100644
15
4 files changed, 147 insertions(+)
12
--- a/hw/timer/omap_gptimer.c
16
13
+++ b/hw/timer/omap_gptimer.c
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
18
index XXXXXXX..XXXXXXX 100644
15
s->writeh = (uint16_t) value;
19
--- a/target/arm/helper-mve.h
20
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
+
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
16
}
173
}
17
174
+
18
+static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
19
+ unsigned size)
176
+ bool negateshift)
20
+{
177
+{
21
+ switch (size) {
178
+ TCGv_ptr qd, qm;
22
+ case 1:
179
+ int shift = a->shift;
23
+ return omap_badwidth_read32(opaque, addr);
180
+
24
+ case 2:
181
+ if (!dc_isar_feature(aa32_mve, s) ||
25
+ return omap_gp_timer_readh(opaque, addr);
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
26
+ case 4:
183
+ !fn) {
27
+ return omap_gp_timer_readw(opaque, addr);
184
+ return false;
28
+ default:
185
+ }
29
+ g_assert_not_reached();
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
30
+ }
187
+ return true;
188
+ }
189
+
190
+ /*
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
194
+ */
195
+ if (negateshift) {
196
+ shift = -shift;
197
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
31
+}
206
+}
32
+
207
+
33
+static void omap_gp_timer_writefn(void *opaque, hwaddr addr,
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
34
+ uint64_t value, unsigned size)
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
35
+{
210
+ { \
36
+ switch (size) {
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
37
+ case 1:
212
+ gen_helper_mve_##FN##b, \
38
+ omap_badwidth_write32(opaque, addr, value);
213
+ gen_helper_mve_##FN##h, \
39
+ break;
214
+ gen_helper_mve_##FN##w, \
40
+ case 2:
215
+ NULL, \
41
+ omap_gp_timer_writeh(opaque, addr, value);
216
+ }; \
42
+ break;
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
43
+ case 4:
218
+ }
44
+ omap_gp_timer_write(opaque, addr, value);
219
+
45
+ break;
220
+DO_2SHIFT(VSHLI, vshli_u, false)
46
+ default:
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
47
+ g_assert_not_reached();
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
48
+ }
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
49
+}
50
+
51
static const MemoryRegionOps omap_gp_timer_ops = {
52
- .old_mmio = {
53
- .read = {
54
- omap_badwidth_read32,
55
- omap_gp_timer_readh,
56
- omap_gp_timer_readw,
57
- },
58
- .write = {
59
- omap_badwidth_write32,
60
- omap_gp_timer_writeh,
61
- omap_gp_timer_write,
62
- },
63
- },
64
+ .read = omap_gp_timer_readfn,
65
+ .write = omap_gp_timer_writefn,
66
+ .valid.min_access_size = 1,
67
+ .valid.max_access_size = 4,
68
.endianness = DEVICE_NATIVE_ENDIAN,
69
};
70
71
--
224
--
72
2.7.4
225
2.20.1
73
226
74
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/31] nvic: Handle banked exceptions in nvic_recompute_state()
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
Update the nvic_recompute_state() code to handle the security
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
extension and its associated banked registers.
2
VRSHRI. As with Neon, we implement these by using helper functions
3
3
which perform left shifts but allow negative shift counts to indicate
4
Code that uses the resulting cached state (ie the irq
4
right shifts.
5
acknowledge and complete code) will be updated in a later
6
commit.
7
5
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
11
---
9
---
12
hw/intc/armv7m_nvic.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++--
10
target/arm/helper-mve.h | 12 ++++++++++++
13
hw/intc/trace-events | 1 +
11
target/arm/translate.h | 20 ++++++++++++++++++++
14
2 files changed, 147 insertions(+), 5 deletions(-)
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
15
17
16
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/armv7m_nvic.c
20
--- a/target/arm/helper-mve.h
19
+++ b/hw/intc/armv7m_nvic.c
21
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
21
* (higher than the highest possible priority value)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
22
*/
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
23
#define NVIC_NOEXC_PRIO 0x100
25
24
+/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+#define NVIC_NS_PRIO_LIMIT 0x80
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
static const uint8_t nvic_id[] = {
29
+
28
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
return false;
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate.h
48
+++ b/target/arm/translate.h
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
50
return x * 2 + 1;
31
}
51
}
32
52
33
+static bool exc_is_banked(int exc)
53
+static inline int rsub_64(DisasContext *s, int x)
34
+{
54
+{
35
+ /* Return true if this is one of the limited set of exceptions which
55
+ return 64 - x;
36
+ * are banked (and thus have state in sec_vectors[])
37
+ */
38
+ return exc == ARMV7M_EXCP_HARD ||
39
+ exc == ARMV7M_EXCP_MEM ||
40
+ exc == ARMV7M_EXCP_USAGE ||
41
+ exc == ARMV7M_EXCP_SVC ||
42
+ exc == ARMV7M_EXCP_PENDSV ||
43
+ exc == ARMV7M_EXCP_SYSTICK;
44
+}
56
+}
45
+
57
+
46
/* Return a mask word which clears the subpriority bits from
58
+static inline int rsub_32(DisasContext *s, int x)
47
* a priority value for an M-profile exception, leaving only
48
* the group priority.
49
*/
50
-static inline uint32_t nvic_gprio_mask(NVICState *s)
51
+static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
52
+{
59
+{
53
+ return ~0U << (s->prigroup[secure] + 1);
60
+ return 32 - x;
54
+}
61
+}
55
+
62
+
56
+static bool exc_targets_secure(NVICState *s, int exc)
63
+static inline int rsub_16(DisasContext *s, int x)
57
+{
64
+{
58
+ /* Return true if this non-banked exception targets Secure state. */
65
+ return 16 - x;
59
+ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
60
+ return false;
61
+ }
62
+
63
+ if (exc >= NVIC_FIRST_IRQ) {
64
+ return !s->itns[exc];
65
+ }
66
+
67
+ /* Function shouldn't be called for banked exceptions. */
68
+ assert(!exc_is_banked(exc));
69
+
70
+ switch (exc) {
71
+ case ARMV7M_EXCP_NMI:
72
+ case ARMV7M_EXCP_BUS:
73
+ return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
74
+ case ARMV7M_EXCP_SECURE:
75
+ return true;
76
+ case ARMV7M_EXCP_DEBUG:
77
+ /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
78
+ return false;
79
+ default:
80
+ /* reset, and reserved (unused) low exception numbers.
81
+ * We'll get called by code that loops through all the exception
82
+ * numbers, but it doesn't matter what we return here as these
83
+ * non-existent exceptions will never be pended or active.
84
+ */
85
+ return true;
86
+ }
87
+}
66
+}
88
+
67
+
89
+static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
68
+static inline int rsub_8(DisasContext *s, int x)
90
+{
69
+{
91
+ /* Return the group priority for this exception, given its raw
70
+ return 8 - x;
92
+ * (group-and-subgroup) priority value and whether it is targeting
93
+ * secure state or not.
94
+ */
95
+ if (rawprio < 0) {
96
+ return rawprio;
97
+ }
98
+ rawprio &= nvic_gprio_mask(s, targets_secure);
99
+ /* AIRCR.PRIS causes us to squash all NS priorities into the
100
+ * lower half of the total range
101
+ */
102
+ if (!targets_secure &&
103
+ (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
104
+ rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
105
+ }
106
+ return rawprio;
107
+}
71
+}
108
+
72
+
109
+/* Recompute vectpending and exception_prio for a CPU which implements
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
110
+ * the Security extension
111
+ */
112
+static void nvic_recompute_state_secure(NVICState *s)
113
{
74
{
114
- return ~0U << (s->prigroup[M_REG_NS] + 1);
75
return (dc->features & (1ULL << feature)) != 0;
115
+ int i, bank;
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
116
+ int pend_prio = NVIC_NOEXC_PRIO;
77
index XXXXXXX..XXXXXXX 100644
117
+ int active_prio = NVIC_NOEXC_PRIO;
78
--- a/target/arm/mve.decode
118
+ int pend_irq = 0;
79
+++ b/target/arm/mve.decode
119
+ bool pending_is_s_banked = false;
80
@@ -XXX,XX +XXX,XX @@
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
83
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
120
+
88
+
121
+ /* R_CQRV: precedence is by:
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
122
+ * - lowest group priority; if both the same then
90
+ size=0 shift=%rshift_i3
123
+ * - lowest subpriority; if both the same then
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
124
+ * - lowest exception number; if both the same (ie banked) then
92
+ size=1 shift=%rshift_i4
125
+ * - secure exception takes precedence
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
126
+ * Compare pseudocode RawExecutionPriority.
94
+ size=2 shift=%rshift_i5
127
+ * Annoyingly, now we have two prigroup values (for S and NS)
128
+ * we can't do the loop comparison on raw priority values.
129
+ */
130
+ for (i = 1; i < s->num_irq; i++) {
131
+ for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
132
+ VecInfo *vec;
133
+ int prio;
134
+ bool targets_secure;
135
+
95
+
136
+ if (bank == M_REG_S) {
96
# Vector loads and stores
137
+ if (!exc_is_banked(i)) {
97
138
+ continue;
98
# Widening loads and narrowing stores:
139
+ }
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
140
+ vec = &s->sec_vectors[i];
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
141
+ targets_secure = true;
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
142
+ } else {
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
143
+ vec = &s->vectors[i];
144
+ targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
145
+ }
146
+
103
+
147
+ prio = exc_group_prio(s, vec->prio, targets_secure);
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
148
+ if (vec->enabled && vec->pending && prio < pend_prio) {
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
149
+ pend_prio = prio;
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
150
+ pend_irq = i;
151
+ pending_is_s_banked = (bank == M_REG_S);
152
+ }
153
+ if (vec->active && prio < active_prio) {
154
+ active_prio = prio;
155
+ }
156
+ }
157
+ }
158
+
107
+
159
+ s->vectpending_is_s_banked = pending_is_s_banked;
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
160
+ s->vectpending = pend_irq;
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
161
+ s->vectpending_prio = pend_prio;
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
162
+ s->exception_prio = active_prio;
163
+
111
+
164
+ trace_nvic_recompute_state_secure(s->vectpending,
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
165
+ s->vectpending_is_s_banked,
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
166
+ s->vectpending_prio,
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
167
+ s->exception_prio);
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
168
}
163
}
169
164
170
/* Recompute vectpending and exception_prio */
165
-static inline int rsub_64(DisasContext *s, int x)
171
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
166
-{
172
int active_prio = NVIC_NOEXC_PRIO;
167
- return 64 - x;
173
int pend_irq = 0;
168
-}
174
169
-
175
+ /* In theory we could write one function that handled both
170
-static inline int rsub_32(DisasContext *s, int x)
176
+ * the "security extension present" and "not present"; however
171
-{
177
+ * the security related changes significantly complicate the
172
- return 32 - x;
178
+ * recomputation just by themselves and mixing both cases together
173
-}
179
+ * would be even worse, so we retain a separate non-secure-only
174
-static inline int rsub_16(DisasContext *s, int x)
180
+ * version for CPUs which don't implement the security extension.
175
-{
181
+ */
176
- return 16 - x;
182
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
177
-}
183
+ nvic_recompute_state_secure(s);
178
-static inline int rsub_8(DisasContext *s, int x)
184
+ return;
179
-{
185
+ }
180
- return 8 - x;
186
+
181
-}
187
for (i = 1; i < s->num_irq; i++) {
182
-
188
VecInfo *vec = &s->vectors[i];
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
189
184
{
190
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
191
}
192
193
if (active_prio > 0) {
194
- active_prio &= nvic_gprio_mask(s);
195
+ active_prio &= nvic_gprio_mask(s, false);
196
}
197
198
if (pend_prio > 0) {
199
- pend_prio &= nvic_gprio_mask(s);
200
+ pend_prio &= nvic_gprio_mask(s, false);
201
}
202
203
s->vectpending = pend_irq;
204
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
205
} else if (env->v7m.primask[env->v7m.secure]) {
206
running = 0;
207
} else if (env->v7m.basepri[env->v7m.secure] > 0) {
208
- running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
209
+ running = env->v7m.basepri[env->v7m.secure] &
210
+ nvic_gprio_mask(s, env->v7m.secure);
211
} else {
212
running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
213
}
214
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/intc/trace-events
217
+++ b/hw/intc/trace-events
218
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
219
220
# hw/intc/armv7m_nvic.c
221
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
222
+nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
223
nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
224
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
225
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
226
--
186
--
227
2.7.4
187
2.20.1
228
188
229
189
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/31] nvic: Add banked exception states
[PULL 15/24] target/arm: Implement MVE VSHLL
1
For the v8M security extension, some exceptions must be banked
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
between security states. Add the new vecinfo array which holds
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
the state for the banked exceptions and migrate it if the
3
and the T2 encoding is a special case where the shift count is always
4
CPU the NVIC is attached to implements the security extension.
4
equal to the element size.
5
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
8
---
9
---
9
include/hw/intc/armv7m_nvic.h | 14 ++++++++++++
10
target/arm/helper-mve.h | 9 +++++++
10
hw/intc/armv7m_nvic.c | 53 ++++++++++++++++++++++++++++++++++++++++++-
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
11
2 files changed, 66 insertions(+), 1 deletion(-)
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
12
15
13
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/armv7m_nvic.h
18
--- a/target/arm/helper-mve.h
16
+++ b/include/hw/intc/armv7m_nvic.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
17
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
18
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
19
/* Highest permitted number of exceptions (architectural limit) */
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
20
#define NVIC_MAX_VECTORS 512
40
21
+/* Number of internal exceptions */
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
22
+#define NVIC_INTERNAL_VECTORS 16
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
23
43
+# VSHLL encoding T2 where shift == esize
24
typedef struct VecInfo {
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
25
/* Exception priorities can range from -3 to 255; only the unmodifiable
45
+ qd=%qd qm=%qm size=0 shift=8
26
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
27
ARMCPU *cpu;
47
+ qd=%qd qm=%qm size=1 shift=16
28
48
+
29
VecInfo vectors[NVIC_MAX_VECTORS];
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
30
+ /* If the v8M security extension is implemented, some of the internal
50
%rshift_i5 16:5 !function=rsub_32
31
+ * exceptions are banked between security states (ie there exists both
51
%rshift_i4 16:4 !function=rsub_16
32
+ * a Secure and a NonSecure version of the exception and its state):
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
33
+ * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
34
+ * The rest (including all the external exceptions) are not banked, though
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
35
+ * they may be configurable to target either Secure or NonSecure state.
55
36
+ * We store the secure exception state in sec_vectors[] for the banked
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
37
+ * exceptions, and otherwise use only vectors[] (including for exceptions
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
38
+ * like SecureFault that unconditionally target Secure state).
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
39
+ * Entries in sec_vectors[] for non-banked exception numbers are unused.
59
+# overlaps what would be size=0b11 VMULH/VRMULH
40
+ */
41
+ VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
42
uint32_t prigroup;
43
44
/* vectpending and exception_prio are both cached state that can
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
49
@@ -XXX,XX +XXX,XX @@
50
* For historical reasons QEMU tends to use "interrupt" and
51
* "exception" more or less interchangeably.
52
*/
53
-#define NVIC_FIRST_IRQ 16
54
+#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
55
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
56
57
/* Effective running priority of the CPU when no exception is active
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
59
}
60
};
61
62
+static bool nvic_security_needed(void *opaque)
63
+{
60
+{
64
+ NVICState *s = opaque;
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
65
+
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
66
+ return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
63
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
67
+}
67
+}
68
+
68
+
69
+static int nvic_security_post_load(void *opaque, int version_id)
70
+{
69
+{
71
+ NVICState *s = opaque;
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
72
+ int i;
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
73
+
72
+
74
+ /* Check for out of range priority settings */
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
75
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
76
+ return 1;
77
+ }
78
+ for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
79
+ if (s->sec_vectors[i].prio & ~0xff) {
80
+ return 1;
81
+ }
82
+ }
83
+ return 0;
84
+}
74
+}
85
+
75
+
86
+static const VMStateDescription vmstate_nvic_security = {
76
+{
87
+ .name = "nvic/m-security",
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
88
+ .version_id = 1,
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
89
+ .minimum_version_id = 1,
90
+ .needed = nvic_security_needed,
91
+ .post_load = &nvic_security_post_load,
92
+ .fields = (VMStateField[]) {
93
+ VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
94
+ vmstate_VecInfo, VecInfo),
95
+ VMSTATE_END_OF_LIST()
96
+ }
97
+};
98
+
79
+
99
static const VMStateDescription vmstate_nvic = {
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
100
.name = "armv7m_nvic",
81
+}
101
.version_id = 4,
102
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
103
vmstate_VecInfo, VecInfo),
104
VMSTATE_UINT32(prigroup, NVICState),
105
VMSTATE_END_OF_LIST()
106
+ },
107
+ .subsections = (const VMStateDescription*[]) {
108
+ &vmstate_nvic_security,
109
+ NULL
110
}
111
};
112
113
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
114
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
115
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
116
117
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
118
+ s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;
119
+ s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;
120
+ s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
121
+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
122
+
82
+
123
+ /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
83
+{
124
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
86
+
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
88
+}
89
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
96
+
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
100
+
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
103
+
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
106
+
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/arm/mve_helper.c
112
+++ b/target/arm/mve_helper.c
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
117
+
118
+/*
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
121
+ * the input, and LESIZE, LTYPE for the output.
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
123
+ * because the long shift is strictly left-only.
124
+ */
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
125
+ }
139
+ }
126
+
140
+
127
/* Strictly speaking the reset handler should be enabled.
141
+#define DO_VSHLL_ALL(OP, TOP) \
128
* However, we don't simulate soft resets through the NVIC,
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
129
* and the reset vector should never be pended.
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
146
+
147
+DO_VSHLL_ALL(vshllb, false)
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
+
158
+#define DO_VSHLL(INSN, FN) \
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
160
+ { \
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
167
+
168
+DO_VSHLL(VSHLL_BS, vshllbs)
169
+DO_VSHLL(VSHLL_BU, vshllbu)
170
+DO_VSHLL(VSHLL_TS, vshllts)
171
+DO_VSHLL(VSHLL_TU, vshlltu)
130
--
172
--
131
2.7.4
173
2.20.1
132
174
133
175
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/31] hw/gpio/omap_gpio.c: Don't use old_mmio
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
Drop the use of old_mmio in the omap2_gpio memory ops.
1
Implement the MVE VSRI and VSLI insns, which perform a
2
shift-and-insert operation.
2
3
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-3-git-send-email-peter.maydell@linaro.org
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
6
---
7
---
7
hw/gpio/omap_gpio.c | 26 ++++++++++++--------------
8
target/arm/helper-mve.h | 8 ++++++++
8
1 file changed, 12 insertions(+), 14 deletions(-)
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
9
13
10
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
11
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/gpio/omap_gpio.c
16
--- a/target/arm/helper-mve.h
13
+++ b/hw/gpio/omap_gpio.c
17
+++ b/target/arm/helper-mve.h
14
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_write(void *opaque, hwaddr addr,
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
15
}
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
16
}
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
17
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
-static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
22
+
19
+static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
+ unsigned size)
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
{
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
26
+
23
}
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
- uint32_t value)
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
27
+ uint64_t value, unsigned size)
31
index XXXXXXX..XXXXXXX 100644
28
{
32
--- a/target/arm/mve.decode
29
uint32_t cur = 0;
33
+++ b/target/arm/mve.decode
30
uint32_t mask = 0xffff;
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
31
35
32
+ if (size == 4) {
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
33
+ omap2_gpio_module_write(opaque, addr, value);
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
34
+ return;
38
+
39
+# Shift-and-insert
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
+
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
35
+ }
83
+ }
36
+
84
+
37
switch (addr & ~3) {
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
38
case 0x00:    /* GPIO_REVISION */
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
39
case 0x14:    /* GPIO_SYSSTATUS */
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
40
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
41
}
89
+
42
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
43
static const MemoryRegionOps omap2_gpio_module_ops = {
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
44
- .old_mmio = {
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
45
- .read = {
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
46
- omap2_gpio_module_readp,
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
47
- omap2_gpio_module_readp,
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
48
- omap2_gpio_module_read,
96
+
49
- },
97
/*
50
- .write = {
98
* Long shifts taking half-sized inputs from top or bottom of the input
51
- omap2_gpio_module_writep,
99
* vector and producing a double-width result. ESIZE, TYPE are for
52
- omap2_gpio_module_writep,
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
53
- omap2_gpio_module_write,
101
index XXXXXXX..XXXXXXX 100644
54
- },
102
--- a/target/arm/translate-mve.c
55
- },
103
+++ b/target/arm/translate-mve.c
56
+ .read = omap2_gpio_module_readp,
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
57
+ .write = omap2_gpio_module_writep,
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
58
+ .valid.min_access_size = 1,
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
59
+ .valid.max_access_size = 4,
107
60
.endianness = DEVICE_NATIVE_ENDIAN,
108
+DO_2SHIFT(VSRI, vsri, false)
61
};
109
+DO_2SHIFT(VSLI, vsli, false)
62
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
63
--
114
--
64
2.7.4
115
2.20.1
65
116
66
117
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/31] nvic: Make SHPR registers banked
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
Make the set_prio() function take a bool indicating
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
whether to pend the secure or non-secure version of a banked
2
3
interrupt, and use this to implement the correct banking
3
do_urshr() is borrowed from sve_helper.c.
4
semantics for the SHPR registers.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
9
---
8
---
10
hw/intc/armv7m_nvic.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-----
9
target/arm/helper-mve.h | 10 ++++++++++
11
hw/intc/trace-events | 2 +-
10
target/arm/mve.decode | 11 +++++++++++
12
2 files changed, 88 insertions(+), 10 deletions(-)
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
13
14
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
17
--- a/target/arm/helper-mve.h
17
+++ b/hw/intc/armv7m_nvic.c
18
+++ b/target/arm/helper-mve.h
18
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_raw_execution_priority(void *opaque)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
return s->exception_prio;
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
}
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
-/* caller must call nvic_irq_update() after this */
23
+
23
-static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+/* caller must call nvic_irq_update() after this.
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+ * secure indicates the bank to use for banked exceptions (we assert if
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+ * we are passed secure=true for a non-banked exception).
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
41
+
42
+# Narrowing shifts (which only support b and h sizes)
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
47
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
61
+/*
62
+ * Narrowing right shifts, taking a double sized input, shifting it
63
+ * and putting the result in either the top or bottom half of the output.
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
27
+ */
65
+ */
28
+static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
29
{
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
30
assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
68
+ void *vm, uint32_t shift) \
31
assert(irq < s->num_irq);
69
+ { \
32
70
+ LTYPE *m = vm; \
33
- s->vectors[irq].prio = prio;
71
+ TYPE *d = vd; \
34
+ if (secure) {
72
+ uint16_t mask = mve_element_mask(env); \
35
+ assert(exc_is_banked(irq));
73
+ unsigned le; \
36
+ s->sec_vectors[irq].prio = prio;
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
37
+ } else {
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
38
+ s->vectors[irq].prio = prio;
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
39
+ }
79
+ }
40
+
80
+
41
+ trace_nvic_set_prio(irq, secure, prio);
81
+#define DO_VSHRN_ALL(OP, FN) \
42
+}
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
43
+
86
+
44
+/* Return the current raw priority register value.
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
45
+ * secure indicates the bank to use for banked exceptions (we assert if
46
+ * we are passed secure=true for a non-banked exception).
47
+ */
48
+static int get_prio(NVICState *s, unsigned irq, bool secure)
49
+{
88
+{
50
+ assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
89
+ if (likely(sh < 64)) {
51
+ assert(irq < s->num_irq);
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
52
91
+ } else if (sh == 64) {
53
- trace_nvic_set_prio(irq, prio);
92
+ return x >> 63;
54
+ if (secure) {
55
+ assert(exc_is_banked(irq));
56
+ return s->sec_vectors[irq].prio;
57
+ } else {
93
+ } else {
58
+ return s->vectors[irq].prio;
94
+ return 0;
59
+ }
60
}
61
62
/* Recompute state and assert irq line accordingly.
63
@@ -XXX,XX +XXX,XX @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
64
}
65
}
66
67
+static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
68
+{
69
+ /* Behaviour for the SHPR register field for this exception:
70
+ * return M_REG_NS to use the nonsecure vector (including for
71
+ * non-banked exceptions), M_REG_S for the secure version of
72
+ * a banked exception, and -1 if this field should RAZ/WI.
73
+ */
74
+ switch (exc) {
75
+ case ARMV7M_EXCP_MEM:
76
+ case ARMV7M_EXCP_USAGE:
77
+ case ARMV7M_EXCP_SVC:
78
+ case ARMV7M_EXCP_PENDSV:
79
+ case ARMV7M_EXCP_SYSTICK:
80
+ /* Banked exceptions */
81
+ return attrs.secure;
82
+ case ARMV7M_EXCP_BUS:
83
+ /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
84
+ if (!attrs.secure &&
85
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
86
+ return -1;
87
+ }
88
+ return M_REG_NS;
89
+ case ARMV7M_EXCP_SECURE:
90
+ /* Not banked, RAZ/WI from nonsecure */
91
+ if (!attrs.secure) {
92
+ return -1;
93
+ }
94
+ return M_REG_NS;
95
+ case ARMV7M_EXCP_DEBUG:
96
+ /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
97
+ return M_REG_NS;
98
+ case 8 ... 10:
99
+ case 13:
100
+ /* RES0 */
101
+ return -1;
102
+ default:
103
+ /* Not reachable due to decode of SHPR register addresses */
104
+ g_assert_not_reached();
105
+ }
95
+ }
106
+}
96
+}
107
+
97
+
108
static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
109
uint64_t *data, unsigned size,
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
110
MemTxAttrs attrs)
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
111
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
101
index XXXXXXX..XXXXXXX 100644
112
}
102
--- a/target/arm/translate-mve.c
113
}
103
+++ b/target/arm/translate-mve.c
114
break;
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
115
- case 0xd18 ... 0xd23: /* System Handler Priority. */
105
DO_VSHLL(VSHLL_BU, vshllbu)
116
+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
106
DO_VSHLL(VSHLL_TS, vshllts)
117
val = 0;
107
DO_VSHLL(VSHLL_TU, vshlltu)
118
for (i = 0; i < size; i++) {
119
- val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
120
+ unsigned hdlidx = (offset - 0xd14) + i;
121
+ int sbank = shpr_bank(s, hdlidx, attrs);
122
+
108
+
123
+ if (sbank < 0) {
109
+#define DO_2SHIFT_N(INSN, FN) \
124
+ continue;
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
125
+ }
111
+ { \
126
+ val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
127
}
113
+ gen_helper_mve_##FN##b, \
128
break;
114
+ gen_helper_mve_##FN##h, \
129
case 0xfe0 ... 0xfff: /* ID. */
115
+ }; \
130
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
116
+ return do_2shift(s, a, fns[a->size], false); \
131
117
+ }
132
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
133
if (attrs.secure || s->itns[startvec + i]) {
134
- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
135
+ set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
136
}
137
}
138
nvic_irq_update(s);
139
return MEMTX_OK;
140
- case 0xd18 ... 0xd23: /* System Handler Priority. */
141
+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
142
for (i = 0; i < size; i++) {
143
unsigned hdlidx = (offset - 0xd14) + i;
144
- set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
145
+ int newprio = extract32(value, i * 8, 8);
146
+ int sbank = shpr_bank(s, hdlidx, attrs);
147
+
118
+
148
+ if (sbank < 0) {
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
149
+ continue;
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
150
+ }
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
151
+ set_prio(s, hdlidx, sbank, newprio);
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
152
}
153
nvic_irq_update(s);
154
return MEMTX_OK;
155
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
156
index XXXXXXX..XXXXXXX 100644
157
--- a/hw/intc/trace-events
158
+++ b/hw/intc/trace-events
159
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
160
# hw/intc/armv7m_nvic.c
161
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
162
nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
163
-nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
164
+nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
165
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
166
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
167
nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
168
--
123
--
169
2.7.4
124
2.20.1
170
125
171
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/31] hw/i2c/omap_i2c.c: Don't use old_mmio
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
Don't use old_mmio in the memory region ops struct.
1
Implement the MVE saturating shift-right-and-narrow insns
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
4
do_srshr() is borrowed from sve_helper.c.
2
5
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-6-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
6
---
9
---
7
hw/i2c/omap_i2c.c | 44 ++++++++++++++++++++++++++++++++------------
10
target/arm/helper-mve.h | 30 +++++++++++
8
1 file changed, 32 insertions(+), 12 deletions(-)
11
target/arm/mve.decode | 28 ++++++++++
9
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
10
diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
13
target/arm/translate-mve.c | 12 +++++
11
index XXXXXXX..XXXXXXX 100644
14
4 files changed, 174 insertions(+)
12
--- a/hw/i2c/omap_i2c.c
15
13
+++ b/hw/i2c/omap_i2c.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
@@ -XXX,XX +XXX,XX @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
57
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
62
+
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
15
}
95
}
16
}
96
}
17
97
18
+static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
19
+ unsigned size)
20
+{
99
+{
21
+ switch (size) {
100
+ if (likely(sh < 64)) {
22
+ case 2:
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
23
+ return omap_i2c_read(opaque, addr);
102
+ } else {
24
+ default:
103
+ /* Rounding the sign bit always produces 0. */
25
+ return omap_badwidth_read16(opaque, addr);
104
+ return 0;
26
+ }
105
+ }
27
+}
106
+}
28
+
107
+
29
+static void omap_i2c_writefn(void *opaque, hwaddr addr,
108
DO_VSHRN_ALL(vshrn, DO_SHR)
30
+ uint64_t value, unsigned size)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
31
+{
113
+{
32
+ switch (size) {
114
+ if (val > max) {
33
+ case 1:
115
+ *satp = true;
34
+ /* Only the last fifo write can be 8 bit. */
116
+ return max;
35
+ omap_i2c_writeb(opaque, addr, value);
117
+ } else if (val < min) {
36
+ break;
118
+ *satp = true;
37
+ case 2:
119
+ return min;
38
+ omap_i2c_write(opaque, addr, value);
120
+ } else {
39
+ break;
121
+ return val;
40
+ default:
41
+ omap_badwidth_write16(opaque, addr, value);
42
+ break;
43
+ }
122
+ }
44
+}
123
+}
45
+
124
+
46
static const MemoryRegionOps omap_i2c_ops = {
125
+/* Saturating narrowing right shifts */
47
- .old_mmio = {
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
48
- .read = {
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
49
- omap_badwidth_read16,
128
+ void *vm, uint32_t shift) \
50
- omap_i2c_read,
129
+ { \
51
- omap_badwidth_read16,
130
+ LTYPE *m = vm; \
52
- },
131
+ TYPE *d = vd; \
53
- .write = {
132
+ uint16_t mask = mve_element_mask(env); \
54
- omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
133
+ bool qc = false; \
55
- omap_i2c_write,
134
+ unsigned le; \
56
- omap_badwidth_write16,
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
57
- },
136
+ bool sat = false; \
58
- },
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
59
+ .read = omap_i2c_readfn,
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
60
+ .write = omap_i2c_writefn,
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
61
+ .valid.min_access_size = 1,
140
+ } \
62
+ .valid.max_access_size = 4,
141
+ if (qc) { \
63
.endianness = DEVICE_NATIVE_ENDIAN,
142
+ env->vfp.qc[0] = qc; \
64
};
143
+ } \
65
144
+ mve_advance_vpt(env); \
145
+ }
146
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
150
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
154
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
66
--
224
--
67
2.7.4
225
2.20.1
68
226
69
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/31] target/arm: Implement MSR/MRS access to NS banked registers
[PULL 19/24] target/arm: Implement MVE VSHLC
1
In v8M the MSR and MRS instructions have extra register value
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
encodings to allow secure code to access the non-secure banked
2
entire vector with carry in bits provided from a general purpose
3
version of various special registers.
3
register and carry out bits written back to that register.
4
5
(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because
6
we don't currently implement the stack limit registers at all.)
7
4
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
11
---
8
---
12
target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++
9
target/arm/helper-mve.h | 2 ++
13
1 file changed, 110 insertions(+)
10
target/arm/mve.decode | 2 ++
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
14
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
17
--- a/target/arm/helper-mve.h
18
+++ b/target/arm/helper.c
18
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
break;
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
case 20: /* CONTROL */
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
return env->v7m.control[env->v7m.secure];
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+ case 0x94: /* CONTROL_NS */
23
+
24
+ /* We have to handle this here because unprivileged Secure code
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
25
+ * can read the NS CONTROL register.
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
26
+ */
26
index XXXXXXX..XXXXXXX 100644
27
+ if (!env->v7m.secure) {
27
--- a/target/arm/mve.decode
28
+ return 0;
28
+++ b/target/arm/mve.decode
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
33
+
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
51
+
52
+ /*
53
+ * For each 32-bit element, we shift it left, bringing in the
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
29
+ }
66
+ }
30
+ return env->v7m.control[M_REG_NS];
67
+ } else {
31
}
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
32
69
+
33
if (el == 0) {
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
34
return 0; /* unprivileged reads others as zero */
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
35
}
72
+ if (mask & 1) {
36
73
+ rdm = d[H4(e)] >> (32 - shift);
37
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
38
+ switch (reg) {
39
+ case 0x88: /* MSP_NS */
40
+ if (!env->v7m.secure) {
41
+ return 0;
42
+ }
74
+ }
43
+ return env->v7m.other_ss_msp;
75
+ mergemask(&d[H4(e)], r, mask);
44
+ case 0x89: /* PSP_NS */
45
+ if (!env->v7m.secure) {
46
+ return 0;
47
+ }
48
+ return env->v7m.other_ss_psp;
49
+ case 0x90: /* PRIMASK_NS */
50
+ if (!env->v7m.secure) {
51
+ return 0;
52
+ }
53
+ return env->v7m.primask[M_REG_NS];
54
+ case 0x91: /* BASEPRI_NS */
55
+ if (!env->v7m.secure) {
56
+ return 0;
57
+ }
58
+ return env->v7m.basepri[M_REG_NS];
59
+ case 0x93: /* FAULTMASK_NS */
60
+ if (!env->v7m.secure) {
61
+ return 0;
62
+ }
63
+ return env->v7m.faultmask[M_REG_NS];
64
+ case 0x98: /* SP_NS */
65
+ {
66
+ /* This gives the non-secure SP selected based on whether we're
67
+ * currently in handler mode or not, using the NS CONTROL.SPSEL.
68
+ */
69
+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
70
+
71
+ if (!env->v7m.secure) {
72
+ return 0;
73
+ }
74
+ if (!arm_v7m_is_handler_mode(env) && spsel) {
75
+ return env->v7m.other_ss_psp;
76
+ } else {
77
+ return env->v7m.other_ss_msp;
78
+ }
79
+ }
80
+ default:
81
+ break;
82
+ }
76
+ }
83
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
84
+
89
+
85
switch (reg) {
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
86
case 8: /* MSP */
91
+{
87
return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
92
+ /*
88
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
93
+ * Whole Vector Left Shift with Carry. The carry is taken
89
return;
94
+ * from a general purpose register and written back there.
90
}
95
+ * An imm of 0 means "shift by 32".
91
96
+ */
92
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
97
+ TCGv_ptr qd;
93
+ switch (reg) {
98
+ TCGv_i32 rdm;
94
+ case 0x88: /* MSP_NS */
95
+ if (!env->v7m.secure) {
96
+ return;
97
+ }
98
+ env->v7m.other_ss_msp = val;
99
+ return;
100
+ case 0x89: /* PSP_NS */
101
+ if (!env->v7m.secure) {
102
+ return;
103
+ }
104
+ env->v7m.other_ss_psp = val;
105
+ return;
106
+ case 0x90: /* PRIMASK_NS */
107
+ if (!env->v7m.secure) {
108
+ return;
109
+ }
110
+ env->v7m.primask[M_REG_NS] = val & 1;
111
+ return;
112
+ case 0x91: /* BASEPRI_NS */
113
+ if (!env->v7m.secure) {
114
+ return;
115
+ }
116
+ env->v7m.basepri[M_REG_NS] = val & 0xff;
117
+ return;
118
+ case 0x93: /* FAULTMASK_NS */
119
+ if (!env->v7m.secure) {
120
+ return;
121
+ }
122
+ env->v7m.faultmask[M_REG_NS] = val & 1;
123
+ return;
124
+ case 0x98: /* SP_NS */
125
+ {
126
+ /* This gives the non-secure SP selected based on whether we're
127
+ * currently in handler mode or not, using the NS CONTROL.SPSEL.
128
+ */
129
+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
130
+
99
+
131
+ if (!env->v7m.secure) {
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
132
+ return;
101
+ return false;
133
+ }
102
+ }
134
+ if (!arm_v7m_is_handler_mode(env) && spsel) {
103
+ if (a->rdm == 13 || a->rdm == 15) {
135
+ env->v7m.other_ss_psp = val;
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
136
+ } else {
105
+ return false;
137
+ env->v7m.other_ss_msp = val;
106
+ }
138
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
139
+ return;
108
+ return true;
140
+ }
141
+ default:
142
+ break;
143
+ }
144
+ }
109
+ }
145
+
110
+
146
switch (reg) {
111
+ qd = mve_qreg_ptr(a->qd);
147
case 0 ... 7: /* xPSR sub-fields */
112
+ rdm = load_reg(s, a->rdm);
148
/* only APSR is actually writable */
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
117
+ return true;
118
+}
149
--
119
--
150
2.7.4
120
2.20.1
151
121
152
122
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/31] nvic: Add cached vectpending_is_s_banked state
Deleted patch
1
With banked exceptions, just the exception number in
2
s->vectpending is no longer sufficient to uniquely identify
3
the pending exception. Add a vectpending_is_s_banked bool
4
which is true if the exception is using the sec_vectors[]
5
array.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
9
---
10
include/hw/intc/armv7m_nvic.h | 11 +++++++++--
11
hw/intc/armv7m_nvic.c | 1 +
12
2 files changed, 10 insertions(+), 2 deletions(-)
13
14
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/intc/armv7m_nvic.h
17
+++ b/include/hw/intc/armv7m_nvic.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
19
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
20
uint32_t prigroup;
21
22
- /* vectpending and exception_prio are both cached state that can
23
- * be recalculated from the vectors[] array and the prigroup field.
24
+ /* The following fields are all cached state that can be recalculated
25
+ * from the vectors[] and sec_vectors[] arrays and the prigroup field:
26
+ * - vectpending
27
+ * - vectpending_is_secure
28
+ * - exception_prio
29
*/
30
unsigned int vectpending; /* highest prio pending enabled exception */
31
+ /* true if vectpending is a banked secure exception, ie it is in
32
+ * sec_vectors[] rather than vectors[]
33
+ */
34
+ bool vectpending_is_s_banked;
35
int exception_prio; /* group prio of the highest prio active exception */
36
37
MemoryRegion sysregmem;
38
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/intc/armv7m_nvic.c
41
+++ b/hw/intc/armv7m_nvic.c
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
43
44
s->exception_prio = NVIC_NOEXC_PRIO;
45
s->vectpending = 0;
46
+ s->vectpending_is_s_banked = false;
47
}
48
49
static void nvic_systick_trigger(void *opaque, int n, int level)
50
--
51
2.7.4
52
53
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
[PULL 20/24] target/arm: Implement MVE VADDLV
1
Now that we have a banked FAULTMASK register and banked exceptions,
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
we can implement the correct check in cpu_mmu_index() for whether
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
3
stored in a pair of general-purpose registers.
4
handlers which have requested a negative execution priority to run
5
with the MPU disabled. In v8M the test has to check this for the
6
current security state and so takes account of banking.
7
4
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
11
---
8
---
12
target/arm/cpu.h | 21 ++++++++++++++++-----
9
target/arm/helper-mve.h | 3 ++
13
hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++
10
target/arm/mve.decode | 6 +++-
14
2 files changed, 45 insertions(+), 5 deletions(-)
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
15
14
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
17
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/cpu.h
18
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq);
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
* (v8M ARM ARM I_PKLD.)
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
*/
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
int armv7m_nvic_raw_execution_priority(void *opaque);
22
24
+/**
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
25
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
26
+ * priority is negative for the specified security state.
25
+
27
+ * @opaque: the NVIC
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
+ * @secure: the security state to test
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
29
+ * This corresponds to the pseudocode IsReqExecPriNeg().
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
30
+ */
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
31
+#ifndef CONFIG_USER_ONLY
30
index XXXXXXX..XXXXXXX 100644
32
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
31
--- a/target/arm/mve.decode
33
+#else
32
+++ b/target/arm/mve.decode
34
+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
35
+{
38
+{
36
+ return false;
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
37
+}
42
+}
38
+#endif
43
39
44
# Predicate operations
40
/* Interface for defining coprocessor registers.
45
%mask_22_13 22:1 13:3
41
* Registers are defined in tables of arm_cp_reginfo structs
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
42
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
43
if (arm_feature(env, ARM_FEATURE_M)) {
44
ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
45
46
- /* Execution priority is negative if FAULTMASK is set or
47
- * we're in a HardFault or NMI handler.
48
- */
49
- if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
50
- || env->v7m.faultmask[env->v7m.secure]) {
51
+ if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
52
mmu_idx = ARMMMUIdx_MNegPri;
53
}
54
55
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
56
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/intc/armv7m_nvic.c
48
--- a/target/arm/mve_helper.c
58
+++ b/hw/intc/armv7m_nvic.c
49
+++ b/target/arm/mve_helper.c
59
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
60
return MIN(running, s->exception_prio);
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
61
}
82
}
62
83
63
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
64
+{
85
+{
65
+ /* Return true if the requested execution priority is negative
86
+ /*
66
+ * for the specified security state, ie that security state
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
67
+ * has an active NMI or HardFault or has set its FAULTMASK.
88
+ * elements of the vector into a 64-bit result stored in
68
+ * Note that this is not the same as whether the execution
89
+ * a pair of general-purpose registers.
69
+ * priority is actually negative (for instance AIRCR.PRIS may
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
70
+ * mean we don't allow FAULTMASK_NS to actually make the execution
71
+ * priority negative). Compare pseudocode IsReqExcPriNeg().
72
+ */
91
+ */
73
+ NVICState *s = opaque;
92
+ TCGv_ptr qm;
93
+ TCGv_i64 rda;
94
+ TCGv_i32 rdalo, rdahi;
74
+
95
+
75
+ if (s->cpu->env.v7m.faultmask[secure]) {
96
+ if (!dc_isar_feature(aa32_mve, s)) {
97
+ return false;
98
+ }
99
+ /*
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
102
+ */
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
104
+ return false;
105
+ }
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
76
+ return true;
107
+ return true;
77
+ }
108
+ }
78
+
109
+
79
+ if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
110
+ /*
80
+ s->vectors[ARMV7M_EXCP_HARD].active) {
111
+ * This insn is subject to beat-wise execution. Partial execution
81
+ return true;
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
114
+ */
115
+ if (a->a || mve_skip_first_beat(s)) {
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
82
+ }
126
+ }
83
+
127
+
84
+ if (s->vectors[ARMV7M_EXCP_NMI].active &&
128
+ qm = mve_qreg_ptr(a->qm);
85
+ exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
129
+ if (a->u) {
86
+ return true;
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
87
+ }
133
+ }
134
+ tcg_temp_free_ptr(qm);
88
+
135
+
89
+ return false;
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
90
+}
145
+}
91
+
146
+
92
bool armv7m_nvic_can_take_pending_exception(void *opaque)
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
93
{
148
{
94
NVICState *s = opaque;
149
TCGv_ptr qd;
95
--
150
--
96
2.7.4
151
2.20.1
97
152
98
153
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/31] nvic: Make set_pending and clear_pending take a secure parameter
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()
1
The MVE extension to v8.1M includes some new shift instructions which
2
functions take a bool indicating whether to pend the secure
2
sit entirely within the non-coprocessor part of the encoding space
3
or non-secure version of a banked interrupt, and update the
3
and which operate only on general-purpose registers. They take up
4
callsites accordingly.
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
5
with Rm == 13 or 15.
6
In most callsites we can simply pass the correct security
6
7
state in; in a couple of cases we use TODO comments to indicate
7
Implement the long shifts by immediate, which perform shifts on a
8
that we will return the code in a subsequent commit.
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
an immediate shift count between 1 and 32.
10
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
9
23
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-10-git-send-email-peter.maydell@linaro.org
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
13
---
27
---
14
target/arm/cpu.h | 14 ++++++++++-
28
target/arm/helper-mve.h | 3 ++
15
hw/intc/armv7m_nvic.c | 64 ++++++++++++++++++++++++++++++++++++++-------------
29
target/arm/translate.h | 1 +
16
target/arm/helper.c | 24 +++++++++++--------
30
target/arm/t32.decode | 28 +++++++++++++
17
hw/intc/trace-events | 4 ++--
31
target/arm/mve_helper.c | 10 +++++
18
4 files changed, 77 insertions(+), 29 deletions(-)
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
19
33
5 files changed, 132 insertions(+)
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
21
index XXXXXXX..XXXXXXX 100644
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
22
--- a/target/arm/cpu.h
36
index XXXXXXX..XXXXXXX 100644
23
+++ b/target/arm/cpu.h
37
--- a/target/arm/helper-mve.h
24
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
38
+++ b/target/arm/helper-mve.h
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
43
+
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
49
+++ b/target/arm/translate.h
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@
63
&mcr !extern cp opc1 crn crm opc2 rt
64
&mcrr !extern cp opc1 crm rt rt2
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
83
{
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
25
return true;
133
return true;
26
}
134
}
27
#endif
135
28
-void armv7m_nvic_set_pending(void *opaque, int irq);
136
+/*
29
+/**
137
+ * v8.1M MVE wide-shifts
30
+ * armv7m_nvic_set_pending: mark the specified exception as pending
31
+ * @opaque: the NVIC
32
+ * @irq: the exception number to mark pending
33
+ * @secure: false for non-banked exceptions or for the nonsecure
34
+ * version of a banked exception, true for the secure version of a banked
35
+ * exception.
36
+ *
37
+ * Marks the specified exception as pending. Note that we will assert()
38
+ * if @secure is true and @irq does not specify one of the fixed set
39
+ * of architecturally banked exceptions.
40
+ */
138
+ */
41
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
42
void armv7m_nvic_acknowledge_irq(void *opaque);
140
+ WideShiftImmFn *fn)
43
/**
141
+{
44
* armv7m_nvic_complete_irq: complete specified interrupt or exception
142
+ TCGv_i64 rda;
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
143
+ TCGv_i32 rdalo, rdahi;
46
index XXXXXXX..XXXXXXX 100644
144
+
47
--- a/hw/intc/armv7m_nvic.c
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
48
+++ b/hw/intc/armv7m_nvic.c
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
49
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
147
+ return false;
50
qemu_set_irq(s->excpout, lvl);
148
+ }
51
}
149
+ if (a->rdahi == 15) {
52
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
53
-static void armv7m_nvic_clear_pending(void *opaque, int irq)
151
+ return false;
54
+/**
152
+ }
55
+ * armv7m_nvic_clear_pending: mark the specified exception as not pending
153
+ if (!dc_isar_feature(aa32_mve, s) ||
56
+ * @opaque: the NVIC
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
57
+ * @irq: the exception number to mark as not pending
155
+ a->rdahi == 13) {
58
+ * @secure: false for non-banked exceptions or for the nonsecure
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
59
+ * version of a banked exception, true for the secure version of a banked
157
+ unallocated_encoding(s);
60
+ * exception.
158
+ return true;
61
+ *
159
+ }
62
+ * Marks the specified exception as not pending. Note that we will assert()
160
+
63
+ * if @secure is true and @irq does not specify one of the fixed set
161
+ if (a->shim == 0) {
64
+ * of architecturally banked exceptions.
162
+ a->shim = 32;
65
+ */
163
+ }
66
+static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
164
+
67
{
165
+ rda = tcg_temp_new_i64();
68
NVICState *s = (NVICState *)opaque;
166
+ rdalo = load_reg(s, a->rdalo);
69
VecInfo *vec;
167
+ rdahi = load_reg(s, a->rdahi);
70
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
71
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
169
+
72
170
+ fn(rda, rda, a->shim);
73
- vec = &s->vectors[irq];
171
+
74
- trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
75
+ if (secure) {
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
76
+ assert(exc_is_banked(irq));
174
+ store_reg(s, a->rdalo, rdalo);
77
+ vec = &s->sec_vectors[irq];
175
+ store_reg(s, a->rdahi, rdahi);
78
+ } else {
176
+ tcg_temp_free_i64(rda);
79
+ vec = &s->vectors[irq];
177
+
80
+ }
178
+ return true;
81
+ trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
179
+}
82
if (vec->pending) {
180
+
83
vec->pending = 0;
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
84
nvic_irq_update(s);
182
+{
85
}
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
86
}
184
+}
87
185
+
88
-void armv7m_nvic_set_pending(void *opaque, int irq)
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
89
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
187
+{
90
{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
91
NVICState *s = (NVICState *)opaque;
189
+}
92
+ bool banked = exc_is_banked(irq);
190
+
93
VecInfo *vec;
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
94
192
+{
95
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
96
+ assert(!secure || banked);
194
+}
97
195
+
98
- vec = &s->vectors[irq];
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
99
- trace_nvic_set_pending(irq, vec->enabled, vec->prio);
197
+{
100
+ vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
101
199
+}
102
+ trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);
200
+
103
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
104
if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
202
+{
105
/* If a synchronous exception is pending then it may be
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
106
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq)
204
+}
107
"(current priority %d)\n", irq, running);
205
+
108
}
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
109
207
+{
110
- /* We can do the escalation, so we take HardFault instead */
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
111
+ /* We can do the escalation, so we take HardFault instead.
209
+}
112
+ * If BFHFNMINS is set then we escalate to the banked HF for
210
+
113
+ * the target security state of the original exception; otherwise
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
114
+ * we take a Secure HardFault.
212
+{
115
+ */
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
116
irq = ARMV7M_EXCP_HARD;
214
+}
117
- vec = &s->vectors[irq];
215
+
118
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
119
+ (secure ||
217
+{
120
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
121
+ vec = &s->sec_vectors[irq];
219
+}
122
+ } else {
220
+
123
+ vec = &s->vectors[irq];
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
124
+ }
222
+{
125
+ /* HF may be banked but there is only one shared HFSR */
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
126
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
224
+}
127
}
225
+
128
}
226
/*
129
@@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level)
227
* Multiply and multiply accumulate
130
if (level != vec->level) {
228
*/
131
vec->level = level;
132
if (level) {
133
- armv7m_nvic_set_pending(s, n);
134
+ armv7m_nvic_set_pending(s, n, false);
135
}
136
}
137
}
138
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
139
}
140
case 0xd04: /* Interrupt Control State. */
141
if (value & (1 << 31)) {
142
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
143
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
144
}
145
if (value & (1 << 28)) {
146
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
147
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
148
} else if (value & (1 << 27)) {
149
- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
150
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
151
}
152
if (value & (1 << 26)) {
153
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
154
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
155
} else if (value & (1 << 25)) {
156
- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
157
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
158
}
159
break;
160
case 0xd08: /* Vector Table Offset. */
161
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
162
{
163
int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
164
if (excnum < s->num_irq) {
165
- armv7m_nvic_set_pending(s, excnum);
166
+ armv7m_nvic_set_pending(s, excnum, false);
167
}
168
break;
169
}
170
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
171
/* SysTick just asked us to pend its exception.
172
* (This is different from an external interrupt line's
173
* behaviour.)
174
+ * TODO: when we implement the banked systicks we must make
175
+ * this pend the correct banked exception.
176
*/
177
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
178
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);
179
}
180
}
181
182
diff --git a/target/arm/helper.c b/target/arm/helper.c
183
index XXXXXXX..XXXXXXX 100644
184
--- a/target/arm/helper.c
185
+++ b/target/arm/helper.c
186
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
187
* stack, directly take a usage fault on the current stack.
188
*/
189
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
190
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
191
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
192
v7m_exception_taken(cpu, excret);
193
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
194
"stackframe: failed exception return integrity check\n");
195
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
196
* exception return excret specified then this is a UsageFault.
197
*/
198
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
199
- /* Take an INVPC UsageFault by pushing the stack again. */
200
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
201
+ /* Take an INVPC UsageFault by pushing the stack again.
202
+ * TODO: the v8M version of this code should target the
203
+ * background state for this exception.
204
+ */
205
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);
206
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
207
v7m_push_stack(cpu);
208
v7m_exception_taken(cpu, excret);
209
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
210
handle it. */
211
switch (cs->exception_index) {
212
case EXCP_UDEF:
213
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
214
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
215
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
216
break;
217
case EXCP_NOCP:
218
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
219
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
220
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
221
break;
222
case EXCP_INVSTATE:
223
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
224
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
225
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
226
break;
227
case EXCP_SWI:
228
/* The PC already points to the next instruction. */
229
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
230
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
231
break;
232
case EXCP_PREFETCH_ABORT:
233
case EXCP_DATA_ABORT:
234
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
235
env->v7m.bfar);
236
break;
237
}
238
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
239
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
240
break;
241
default:
242
/* All other FSR values are either MPU faults or "can't happen
243
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
244
env->v7m.mmfar[env->v7m.secure]);
245
break;
246
}
247
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
248
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,
249
+ env->v7m.secure);
250
break;
251
}
252
break;
253
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
254
return;
255
}
256
}
257
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
258
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
259
break;
260
case EXCP_IRQ:
261
break;
262
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
263
index XXXXXXX..XXXXXXX 100644
264
--- a/hw/intc/trace-events
265
+++ b/hw/intc/trace-events
266
@@ -XXX,XX +XXX,XX @@ nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
267
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
268
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
269
nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
270
-nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)"
271
-nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)"
272
+nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
273
+nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
274
nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
275
nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
276
nvic_complete_irq(int irq) "NVIC complete IRQ %d"
277
--
229
--
278
2.7.4
230
2.20.1
279
231
280
232
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/31] nvic: Implement NVIC_ITNS<n> registers
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
For v8M, the NVIC has a new set of registers per interrupt,
1
Implement the MVE long shifts by register, which perform shifts on a
2
NVIC_ITNS<n>. These determine whether the interrupt targets Secure
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
or Non-secure state. Implement the register read/write code for
3
the shift count in another general-purpose register, which might be
4
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
4
either positive or negative.
5
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
5
6
accesses to fields corresponding to interrupts which are
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
configured to target secure state.
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
8
11
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
12
---
15
---
13
include/hw/intc/armv7m_nvic.h | 3 ++
16
target/arm/helper-mve.h | 6 +++
14
hw/intc/armv7m_nvic.c | 74 +++++++++++++++++++++++++++++++++++++++----
17
target/arm/translate.h | 1 +
15
2 files changed, 70 insertions(+), 7 deletions(-)
18
target/arm/t32.decode | 16 +++++--
16
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
17
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
18
index XXXXXXX..XXXXXXX 100644
21
5 files changed, 182 insertions(+), 3 deletions(-)
19
--- a/include/hw/intc/armv7m_nvic.h
22
20
+++ b/include/hw/intc/armv7m_nvic.h
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
24
index XXXXXXX..XXXXXXX 100644
22
/* The PRIGROUP field in AIRCR is banked */
25
--- a/target/arm/helper-mve.h
23
uint32_t prigroup[M_REG_NUM_BANKS];
26
+++ b/target/arm/helper-mve.h
24
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+ /* v8M NVIC_ITNS state (stored as a bool per bit) */
28
26
+ bool itns[NVIC_MAX_VECTORS];
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
27
+
30
28
/* The following fields are all cached state that can be recalculated
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
29
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
30
* - vectpending
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
index XXXXXXX..XXXXXXX 100644
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
--- a/hw/intc/armv7m_nvic.c
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
+++ b/hw/intc/armv7m_nvic.c
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
36
switch (offset) {
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
37
case 4: /* Interrupt Control Type. */
40
index XXXXXXX..XXXXXXX 100644
38
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
41
--- a/target/arm/translate.h
39
+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
42
+++ b/target/arm/translate.h
40
+ {
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
41
+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
42
+ int i;
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
43
+
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
44
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
45
+ goto bad_offset;
48
46
+ }
49
/**
47
+ if (!attrs.secure) {
50
* arm_tbflags_from_tb:
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
54
+++ b/target/arm/t32.decode
55
@@ -XXX,XX +XXX,XX @@
56
&mcrr !extern cp opc1 crm rt rt2
57
58
&mve_shl_ri rdalo rdahi shim
59
+&mve_shl_rr rdalo rdahi rm
60
61
# rdahi: bits [3:1] from insn, bit 0 is 1
62
# rdalo: bits [3:1] from insn, bit 0 is 0
63
@@ -XXX,XX +XXX,XX @@
64
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
69
70
{
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
76
+
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
83
]
84
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
87
+
88
+ # v8.1M CSEL and friends
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
90
}
91
{
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
94
}
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
96
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
99
-
100
# Data-processing (register-shifted register)
101
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/mve_helper.c
106
+++ b/target/arm/mve_helper.c
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
108
return rdm;
109
}
110
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
112
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
114
+}
115
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
117
+{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
48
+ return 0;
146
+ return 0;
49
+ }
147
+ }
50
+ val = 0;
148
+ return src >> 63;
51
+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
149
+ } else if (shift < 0) {
52
+ if (s->itns[startvec + i]) {
150
+ if (round) {
53
+ val |= (1 << i);
151
+ src >>= -shift - 1;
54
+ }
152
+ return (src >> 1) + (src & 1);
55
+ }
153
+ }
56
+ return val;
154
+ return src >> -shift;
57
+ }
155
+ } else if (shift < 48) {
58
case 0xd00: /* CPUID Base. */
156
+ int64_t val = src << shift;
59
return cpu->midr;
157
+ int64_t extval = sextract64(val, 0, 48);
60
case 0xd04: /* Interrupt Control State. */
158
+ if (!sat || val == extval) {
61
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
159
+ return extval;
62
ARMCPU *cpu = s->cpu;
160
+ }
63
161
+ } else if (!sat || src == 0) {
64
switch (offset) {
162
+ return 0;
65
+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
163
+ }
66
+ {
164
+
67
+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
165
+ *sat = 1;
68
+ int i;
166
+ return (1ULL << 47) - (src >= 0);
69
+
167
+}
70
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
168
+
71
+ goto bad_offset;
169
+/* Operate on 64-bit values, but saturate at 48 bits */
72
+ }
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
73
+ if (!attrs.secure) {
171
+ bool round, uint32_t *sat)
74
+ break;
172
+{
75
+ }
173
+ uint64_t val, extval;
76
+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
174
+
77
+ s->itns[startvec + i] = (value >> i) & 1;
175
+ if (shift <= -(48 + round)) {
78
+ }
176
+ return 0;
79
+ nvic_irq_update(s);
177
+ } else if (shift < 0) {
80
+ break;
178
+ if (round) {
81
+ }
179
+ val = src >> (-shift - 1);
82
case 0xd04: /* Interrupt Control State. */
180
+ val = (val >> 1) + (val & 1);
83
if (value & (1 << 31)) {
181
+ } else {
84
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
182
+ val = src >> -shift;
85
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
183
+ }
86
startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
184
+ extval = extract64(val, 0, 48);
87
185
+ if (!sat || val == extval) {
88
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
186
+ return extval;
89
- if (s->vectors[startvec + i].enabled) {
187
+ }
90
+ if (s->vectors[startvec + i].enabled &&
188
+ } else if (shift < 48) {
91
+ (attrs.secure || s->itns[startvec + i])) {
189
+ uint64_t val = src << shift;
92
val |= (1 << i);
190
+ uint64_t extval = extract64(val, 0, 48);
93
}
191
+ if (!sat || val == extval) {
94
}
192
+ return extval;
95
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
193
+ }
96
val = 0;
194
+ } else if (!sat || src == 0) {
97
startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
195
+ return 0;
98
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
196
+ }
99
- if (s->vectors[startvec + i].pending) {
197
+
100
+ if (s->vectors[startvec + i].pending &&
198
+ *sat = 1;
101
+ (attrs.secure || s->itns[startvec + i])) {
199
+ return MAKE_64BIT_MASK(0, 48);
102
val |= (1 << i);
200
+}
103
}
201
+
104
}
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
105
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
203
+{
106
startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
107
205
+}
108
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
206
+
109
- if (s->vectors[startvec + i].active) {
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
110
+ if (s->vectors[startvec + i].active &&
208
+{
111
+ (attrs.secure || s->itns[startvec + i])) {
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
112
val |= (1 << i);
210
+}
113
}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
114
}
212
index XXXXXXX..XXXXXXX 100644
115
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
213
--- a/target/arm/translate.c
116
startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
214
+++ b/target/arm/translate.c
117
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
118
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
119
- val |= s->vectors[startvec + i].prio << (8 * i);
217
}
120
+ if (attrs.secure || s->itns[startvec + i]) {
218
121
+ val |= s->vectors[startvec + i].prio << (8 * i);
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
122
+ }
220
+{
123
}
221
+ TCGv_i64 rda;
124
break;
222
+ TCGv_i32 rdalo, rdahi;
125
case 0xd18 ... 0xd23: /* System Handler Priority. */
223
+
126
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
127
startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
128
226
+ return false;
129
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
227
+ }
130
- if (value & (1 << i)) {
228
+ if (a->rdahi == 15) {
131
+ if (value & (1 << i) &&
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
132
+ (attrs.secure || s->itns[startvec + i])) {
230
+ return false;
133
s->vectors[startvec + i].enabled = setval;
231
+ }
134
}
232
+ if (!dc_isar_feature(aa32_mve, s) ||
135
}
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
136
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
137
startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
138
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
139
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
237
+ unallocated_encoding(s);
140
- if (value & (1 << i)) {
238
+ return true;
141
+ if (value & (1 << i) &&
239
+ }
142
+ (attrs.secure || s->itns[startvec + i])) {
240
+
143
s->vectors[startvec + i].pending = setval;
241
+ rda = tcg_temp_new_i64();
144
}
242
+ rdalo = load_reg(s, a->rdalo);
145
}
243
+ rdahi = load_reg(s, a->rdahi);
146
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
147
startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
245
+
148
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
149
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
150
- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
248
+
151
+ if (attrs.secure || s->itns[startvec + i]) {
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
152
+ set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
153
+ }
251
+ store_reg(s, a->rdalo, rdalo);
154
}
252
+ store_reg(s, a->rdahi, rdahi);
155
nvic_irq_update(s);
253
+ tcg_temp_free_i64(rda);
156
return MEMTX_OK;
254
+
157
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
255
+ return true;
158
VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
256
+}
159
vmstate_VecInfo, VecInfo),
257
+
160
VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
161
+ VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),
259
+{
162
VMSTATE_END_OF_LIST()
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
163
}
261
+}
164
};
262
+
165
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
166
s->vectpending = 0;
264
+{
167
s->vectpending_is_s_banked = false;
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
168
s->vectpending_prio = NVIC_NOEXC_PRIO;
266
+}
169
+
267
+
170
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
171
+ memset(s->itns, 0, sizeof(s->itns));
269
+{
172
+ } else {
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
173
+ /* This state is constant and not guest accessible in a non-security
271
+}
174
+ * NVIC; we set the bits to true to avoid having to do a feature
272
+
175
+ * bit check in the NVIC enable/pend/etc register accessors.
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
176
+ */
274
+{
177
+ int i;
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
178
+
276
+}
179
+ for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {
277
+
180
+ s->itns[i] = true;
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
181
+ }
279
+{
182
+ }
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
183
}
281
+}
184
282
+
185
static void nvic_systick_trigger(void *opaque, int n, int level)
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
286
+}
287
+
288
/*
289
* Multiply and multiply accumulate
290
*/
186
--
291
--
187
2.7.4
292
2.20.1
188
293
189
294
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/31] nvic: Add cached vectpending_prio state
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
Instead of looking up the pending priority
1
Implement the MVE shifts by immediate, which perform shifts
2
in nvic_pending_prio(), cache it in a new state struct
2
on a single general-purpose register.
3
field. The calculation of the pending priority given
3
4
the interrupt number is more complicated in v8M with
4
These patterns overlap with the long-shift-by-immediates,
5
the security extension, so the caching will be worthwhile.
5
so we have to rearrange the grouping a little here.
6
7
This changes nvic_pending_prio() from returning a full
8
(group + subpriority) priority value to returning a group
9
priority. This doesn't require changes to its callsites
10
because we use it only in comparisons of the form
11
execution_prio > nvic_pending_prio()
12
and execution priority is always a group priority, so
13
a test (exec prio > full prio) is true if and only if
14
(execprio > group_prio).
15
16
(Architecturally the expected comparison is with the
17
group priority for this sort of "would we preempt" test;
18
we were only doing a test with a full priority as an
19
optimisation to avoid the mask, which is possible
20
precisely because the two comparisons always give the
21
same answer.)
22
6
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
26
---
10
---
27
include/hw/intc/armv7m_nvic.h | 2 ++
11
target/arm/helper-mve.h | 3 ++
28
hw/intc/armv7m_nvic.c | 23 +++++++++++++----------
12
target/arm/translate.h | 1 +
29
hw/intc/trace-events | 2 +-
13
target/arm/t32.decode | 31 ++++++++++++++-----
30
3 files changed, 16 insertions(+), 11 deletions(-)
14
target/arm/mve_helper.c | 10 ++++++
31
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
32
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
16
5 files changed, 104 insertions(+), 9 deletions(-)
33
index XXXXXXX..XXXXXXX 100644
17
34
--- a/include/hw/intc/armv7m_nvic.h
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
35
+++ b/include/hw/intc/armv7m_nvic.h
19
index XXXXXXX..XXXXXXX 100644
36
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
20
--- a/target/arm/helper-mve.h
37
* - vectpending
21
+++ b/target/arm/helper-mve.h
38
* - vectpending_is_secure
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
39
* - exception_prio
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
40
+ * - vectpending_prio
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
41
*/
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
42
unsigned int vectpending; /* highest prio pending enabled exception */
26
+
43
/* true if vectpending is a banked secure exception, ie it is in
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
44
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
45
*/
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
46
bool vectpending_is_s_banked;
30
index XXXXXXX..XXXXXXX 100644
47
int exception_prio; /* group prio of the highest prio active exception */
31
--- a/target/arm/translate.h
48
+ int vectpending_prio; /* group prio of the exeception in vectpending */
32
+++ b/target/arm/translate.h
49
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
50
MemoryRegion sysregmem;
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
51
MemoryRegion sysreg_ns_mem;
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
52
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
53
index XXXXXXX..XXXXXXX 100644
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
54
--- a/hw/intc/armv7m_nvic.c
38
55
+++ b/hw/intc/armv7m_nvic.c
39
/**
56
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
40
* arm_tbflags_from_tb:
57
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
58
static int nvic_pending_prio(NVICState *s)
42
index XXXXXXX..XXXXXXX 100644
59
{
43
--- a/target/arm/t32.decode
60
- /* return the priority of the current pending interrupt,
44
+++ b/target/arm/t32.decode
61
+ /* return the group priority of the current pending interrupt,
45
@@ -XXX,XX +XXX,XX @@
62
* or NVIC_NOEXC_PRIO if no interrupt is pending
46
63
*/
47
&mve_shl_ri rdalo rdahi shim
64
- return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
48
&mve_shl_rr rdalo rdahi rm
65
+ return s->vectpending_prio;
49
+&mve_sh_ri rda shim
50
51
# rdahi: bits [3:1] from insn, bit 0 is 1
52
# rdalo: bits [3:1] from insn, bit 0 is 0
53
@@ -XXX,XX +XXX,XX @@
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
58
+ &mve_sh_ri shim=%imm5_12_6
59
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
66
}
105
}
67
106
+
68
/* Return the value of the ISCR RETTOBASE bit:
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
69
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
108
+{
70
active_prio &= nvic_gprio_mask(s);
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
71
}
110
+}
72
111
+
73
+ if (pend_prio > 0) {
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
74
+ pend_prio &= nvic_gprio_mask(s);
113
+{
75
+ }
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
76
+
115
+}
77
s->vectpending = pend_irq;
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
78
+ s->vectpending_prio = pend_prio;
117
index XXXXXXX..XXXXXXX 100644
79
s->exception_prio = active_prio;
118
--- a/target/arm/translate.c
80
119
+++ b/target/arm/translate.c
81
- trace_nvic_recompute_state(s->vectpending, s->exception_prio);
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
82
+ trace_nvic_recompute_state(s->vectpending,
121
83
+ s->vectpending_prio,
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
84
+ s->exception_prio);
123
{
124
- TCGv_i32 t = tcg_temp_new_i32();
125
+ TCGv_i32 t;
126
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
128
+ if (sh == 32) {
129
+ tcg_gen_movi_i32(d, 0);
130
+ return;
131
+ }
132
+ t = tcg_temp_new_i32();
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
134
tcg_gen_sari_i32(d, a, sh);
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
85
}
154
}
86
155
87
/* Return the current execution priority of the CPU
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
88
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
157
+{
89
CPUARMState *env = &s->cpu->env;
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
90
const int pending = s->vectpending;
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
91
const int running = nvic_exec_prio(s);
160
+ return false;
92
- int pendgroupprio;
161
+ }
93
VecInfo *vec;
162
+ if (!dc_isar_feature(aa32_mve, s) ||
94
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
95
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
164
+ a->rda == 13 || a->rda == 15) {
96
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
97
assert(vec->enabled);
166
+ unallocated_encoding(s);
98
assert(vec->pending);
167
+ return true;
99
168
+ }
100
- pendgroupprio = vec->prio;
169
+
101
- if (pendgroupprio > 0) {
170
+ if (a->shim == 0) {
102
- pendgroupprio &= nvic_gprio_mask(s);
171
+ a->shim = 32;
103
- }
172
+ }
104
- assert(pendgroupprio < running);
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
105
+ assert(s->vectpending_prio < running);
174
+
106
175
+ return true;
107
- trace_nvic_acknowledge_irq(pending, vec->prio);
176
+}
108
+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
177
+
109
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
110
vec->active = 1;
179
+{
111
vec->pending = 0;
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
112
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
181
+}
113
s->exception_prio = NVIC_NOEXC_PRIO;
182
+
114
s->vectpending = 0;
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
115
s->vectpending_is_s_banked = false;
184
+{
116
+ s->vectpending_prio = NVIC_NOEXC_PRIO;
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
117
}
186
+}
118
187
+
119
static void nvic_systick_trigger(void *opaque, int n, int level)
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
120
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
189
+{
121
index XXXXXXX..XXXXXXX 100644
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
122
--- a/hw/intc/trace-events
191
+}
123
+++ b/hw/intc/trace-events
192
+
124
@@ -XXX,XX +XXX,XX @@ gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor 0x%x
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
125
gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending SGI %d"
194
+{
126
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
127
# hw/intc/armv7m_nvic.c
196
+}
128
-nvic_recompute_state(int vectpending, int exception_prio) "NVIC state recomputed: vectpending %d exception_prio %d"
197
+
129
+nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
130
nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
199
+{
131
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
132
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
133
--
211
--
134
2.7.4
212
2.20.1
135
213
136
214
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/31] nvic: Implement AIRCR changes for v8M
Deleted patch
1
The Application Interrupt and Reset Control Register has some changes
2
for v8M:
3
* new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
4
real state if the security extension is implemented and otherwise
5
are constant
6
* the PRIGROUP field is banked between security states
7
* non-secure code can be blocked from using the SYSRESET bit
8
to reset the system if SYSRESETREQS is set
9
1
10
Implement the new state and the changes to register read and write.
11
For the moment we ignore the effects of the secure PRIGROUP.
12
We will implement the effects of PRIS and BFHFNMIS later.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
17
---
18
include/hw/intc/armv7m_nvic.h | 3 ++-
19
target/arm/cpu.h | 12 +++++++++++
20
hw/intc/armv7m_nvic.c | 49 +++++++++++++++++++++++++++++++++----------
21
target/arm/cpu.c | 7 +++++++
22
4 files changed, 59 insertions(+), 12 deletions(-)
23
24
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/intc/armv7m_nvic.h
27
+++ b/include/hw/intc/armv7m_nvic.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
29
* Entries in sec_vectors[] for non-banked exception numbers are unused.
30
*/
31
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
32
- uint32_t prigroup;
33
+ /* The PRIGROUP field in AIRCR is banked */
34
+ uint32_t prigroup[M_REG_NUM_BANKS];
35
36
/* The following fields are all cached state that can be recalculated
37
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
38
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu.h
41
+++ b/target/arm/cpu.h
42
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
43
int exception;
44
uint32_t primask[M_REG_NUM_BANKS];
45
uint32_t faultmask[M_REG_NUM_BANKS];
46
+ uint32_t aircr; /* only holds r/w state if security extn implemented */
47
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
48
} v7m;
49
50
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1)
51
FIELD(V7M_CCR, DC, 16, 1)
52
FIELD(V7M_CCR, IC, 17, 1)
53
54
+/* V7M AIRCR bits */
55
+FIELD(V7M_AIRCR, VECTRESET, 0, 1)
56
+FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
57
+FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
58
+FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
59
+FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
60
+FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
61
+FIELD(V7M_AIRCR, PRIS, 14, 1)
62
+FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
63
+FIELD(V7M_AIRCR, VECTKEY, 16, 16)
64
+
65
/* V7M CFSR bits for MMFSR */
66
FIELD(V7M_CFSR, IACCVIOL, 0, 1)
67
FIELD(V7M_CFSR, DACCVIOL, 1, 1)
68
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/intc/armv7m_nvic.c
71
+++ b/hw/intc/armv7m_nvic.c
72
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
73
*/
74
static inline uint32_t nvic_gprio_mask(NVICState *s)
75
{
76
- return ~0U << (s->prigroup + 1);
77
+ return ~0U << (s->prigroup[M_REG_NS] + 1);
78
}
79
80
/* Recompute vectpending and exception_prio */
81
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
82
return val;
83
case 0xd08: /* Vector Table Offset. */
84
return cpu->env.v7m.vecbase[attrs.secure];
85
- case 0xd0c: /* Application Interrupt/Reset Control. */
86
- return 0xfa050000 | (s->prigroup << 8);
87
+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
88
+ val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);
89
+ if (attrs.secure) {
90
+ /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
91
+ val |= cpu->env.v7m.aircr;
92
+ } else {
93
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
94
+ /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
95
+ * security isn't supported then BFHFNMINS is RAO (and
96
+ * the bit in env.v7m.aircr is always set).
97
+ */
98
+ val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
99
+ }
100
+ }
101
+ return val;
102
case 0xd10: /* System Control. */
103
/* TODO: Implement SLEEPONEXIT. */
104
return 0;
105
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
106
case 0xd08: /* Vector Table Offset. */
107
cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
108
break;
109
- case 0xd0c: /* Application Interrupt/Reset Control. */
110
- if ((value >> 16) == 0x05fa) {
111
- if (value & 4) {
112
- qemu_irq_pulse(s->sysresetreq);
113
+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
114
+ if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
115
+ if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
116
+ if (attrs.secure ||
117
+ !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
118
+ qemu_irq_pulse(s->sysresetreq);
119
+ }
120
}
121
- if (value & 2) {
122
+ if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
123
qemu_log_mask(LOG_GUEST_ERROR,
124
"Setting VECTCLRACTIVE when not in DEBUG mode "
125
"is UNPREDICTABLE\n");
126
}
127
- if (value & 1) {
128
+ if (value & R_V7M_AIRCR_VECTRESET_MASK) {
129
+ /* NB: this bit is RES0 in v8M */
130
qemu_log_mask(LOG_GUEST_ERROR,
131
"Setting VECTRESET when not in DEBUG mode "
132
"is UNPREDICTABLE\n");
133
}
134
- s->prigroup = extract32(value, 8, 3);
135
+ s->prigroup[attrs.secure] = extract32(value,
136
+ R_V7M_AIRCR_PRIGROUP_SHIFT,
137
+ R_V7M_AIRCR_PRIGROUP_LENGTH);
138
+ if (attrs.secure) {
139
+ /* These bits are only writable by secure */
140
+ cpu->env.v7m.aircr = value &
141
+ (R_V7M_AIRCR_SYSRESETREQS_MASK |
142
+ R_V7M_AIRCR_BFHFNMINS_MASK |
143
+ R_V7M_AIRCR_PRIS_MASK);
144
+ }
145
nvic_irq_update(s);
146
}
147
break;
148
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
149
.fields = (VMStateField[]) {
150
VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
151
vmstate_VecInfo, VecInfo),
152
+ VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
153
VMSTATE_END_OF_LIST()
154
}
155
};
156
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
157
.fields = (VMStateField[]) {
158
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
159
vmstate_VecInfo, VecInfo),
160
- VMSTATE_UINT32(prigroup, NVICState),
161
+ VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),
162
VMSTATE_END_OF_LIST()
163
},
164
.subsections = (const VMStateDescription*[]) {
165
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
166
index XXXXXXX..XXXXXXX 100644
167
--- a/target/arm/cpu.c
168
+++ b/target/arm/cpu.c
169
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
170
171
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
172
env->v7m.secure = true;
173
+ } else {
174
+ /* This bit resets to 0 if security is supported, but 1 if
175
+ * it is not. The bit is not present in v7M, but we set it
176
+ * here so we can avoid having to make checks on it conditional
177
+ * on ARM_FEATURE_V8 (we don't let the guest see the bit).
178
+ */
179
+ env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
180
}
181
182
/* In v7M the reset value of this bit is IMPDEF, but ARM recommends
183
--
184
2.7.4
185
186
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/31] nvic: Make ICSR.RETTOBASE handle banked exceptions
Deleted patch
1
Update the code in nvic_rettobase() so that it checks the
2
sec_vectors[] array as well as the vectors[] array if needed.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505240046-11454-7-git-send-email-peter.maydell@linaro.org
7
---
8
hw/intc/armv7m_nvic.c | 5 ++++-
9
1 file changed, 4 insertions(+), 1 deletion(-)
10
11
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/armv7m_nvic.c
14
+++ b/hw/intc/armv7m_nvic.c
15
@@ -XXX,XX +XXX,XX @@ static int nvic_pending_prio(NVICState *s)
16
static bool nvic_rettobase(NVICState *s)
17
{
18
int irq, nhand = 0;
19
+ bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
20
21
for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
22
- if (s->vectors[irq].active) {
23
+ if (s->vectors[irq].active ||
24
+ (check_sec && irq < NVIC_INTERNAL_VECTORS &&
25
+ s->sec_vectors[irq].active)) {
26
nhand++;
27
if (nhand == 2) {
28
return 0;
29
--
30
2.7.4
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/31] nvic: Compare group priority for escalation to HF
Deleted patch
1
In armv7m_nvic_set_pending() we have to compare the
2
priority of an exception against the execution priority
3
to decide whether it needs to be escalated to HardFault.
4
In the specification this is a comparison against the
5
exception's group priority; for v7M we implemented it
6
as a comparison against the raw exception priority
7
because the two comparisons will always give the
8
same answer. For v8M the existence of AIRCR.PRIS and
9
the possibility of different PRIGROUP values for secure
10
and nonsecure exceptions means we need to explicitly
11
calculate the vector's group priority for this check.
12
1
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 1505240046-11454-12-git-send-email-peter.maydell@linaro.org
16
---
17
hw/intc/armv7m_nvic.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
23
+++ b/hw/intc/armv7m_nvic.c
24
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
25
int running = nvic_exec_prio(s);
26
bool escalate = false;
27
28
- if (vec->prio >= running) {
29
+ if (exc_group_prio(s, vec->prio, secure) >= running) {
30
trace_nvic_escalate_prio(irq, vec->prio, running);
31
escalate = true;
32
} else if (!vec->enabled) {
33
--
34
2.7.4
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/31] nvic: In escalation to HardFault, support HF not being priority -1
Deleted patch
1
When escalating to HardFault, we must go into Lockup if we
2
can't take the synchronous HardFault because the current
3
execution priority is already at or below the priority of
4
HardFault. In v7M HF is always priority -1 so a simple < 0
5
comparison sufficed; in v8M the priority of HardFault can
6
vary depending on whether it is a Secure or NonSecure
7
HardFault, so we must check against the priority of the
8
HardFault exception vector we're about to use.
9
1
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-13-git-send-email-peter.maydell@linaro.org
13
---
14
hw/intc/armv7m_nvic.c | 23 ++++++++++++-----------
15
1 file changed, 12 insertions(+), 11 deletions(-)
16
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
20
+++ b/hw/intc/armv7m_nvic.c
21
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
22
}
23
24
if (escalate) {
25
- if (running < 0) {
26
- /* We want to escalate to HardFault but we can't take a
27
- * synchronous HardFault at this point either. This is a
28
- * Lockup condition due to a guest bug. We don't model
29
- * Lockup, so report via cpu_abort() instead.
30
- */
31
- cpu_abort(&s->cpu->parent_obj,
32
- "Lockup: can't escalate %d to HardFault "
33
- "(current priority %d)\n", irq, running);
34
- }
35
36
- /* We can do the escalation, so we take HardFault instead.
37
+ /* We need to escalate this exception to a synchronous HardFault.
38
* If BFHFNMINS is set then we escalate to the banked HF for
39
* the target security state of the original exception; otherwise
40
* we take a Secure HardFault.
41
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
42
} else {
43
vec = &s->vectors[irq];
44
}
45
+ if (running <= vec->prio) {
46
+ /* We want to escalate to HardFault but we can't take the
47
+ * synchronous HardFault at this point either. This is a
48
+ * Lockup condition due to a guest bug. We don't model
49
+ * Lockup, so report via cpu_abort() instead.
50
+ */
51
+ cpu_abort(&s->cpu->parent_obj,
52
+ "Lockup: can't escalate %d to HardFault "
53
+ "(current priority %d)\n", irq, running);
54
+ }
55
+
56
/* HF may be banked but there is only one shared HFSR */
57
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
58
}
59
--
60
2.7.4
61
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions
Deleted patch
1
In v7M, the fixed-priority exceptions are:
2
Reset: -3
3
NMI: -2
4
HardFault: -1
5
1
6
In v8M, this changes because Secure HardFault may need
7
to be prioritised above NMI:
8
Reset: -4
9
Secure HardFault if AIRCR.BFHFNMINS == 1: -3
10
NMI: -2
11
Secure HardFault if AIRCR.BFHFNMINS == 0: -1
12
NonSecure HardFault: -1
13
14
Make these changes, including support for changing the
15
priority of Secure HardFault as AIRCR.BFHFNMINS changes.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 1505240046-11454-14-git-send-email-peter.maydell@linaro.org
20
---
21
hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++---
22
1 file changed, 19 insertions(+), 3 deletions(-)
23
24
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/intc/armv7m_nvic.c
27
+++ b/hw/intc/armv7m_nvic.c
28
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
29
(R_V7M_AIRCR_SYSRESETREQS_MASK |
30
R_V7M_AIRCR_BFHFNMINS_MASK |
31
R_V7M_AIRCR_PRIS_MASK);
32
+ /* BFHFNMINS changes the priority of Secure HardFault */
33
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
34
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
35
+ } else {
36
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
37
+ }
38
}
39
nvic_irq_update(s);
40
}
41
@@ -XXX,XX +XXX,XX @@ static int nvic_post_load(void *opaque, int version_id)
42
{
43
NVICState *s = opaque;
44
unsigned i;
45
+ int resetprio;
46
47
/* Check for out of range priority settings */
48
- if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
49
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
50
+
51
+ if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
52
s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
53
s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
54
return 1;
55
@@ -XXX,XX +XXX,XX @@ static int nvic_security_post_load(void *opaque, int version_id)
56
int i;
57
58
/* Check for out of range priority settings */
59
- if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
60
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
61
+ && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
62
+ /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
63
+ * if the CPU state has been migrated yet; a mismatch won't
64
+ * cause the emulation to blow up, though.
65
+ */
66
return 1;
67
}
68
for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
69
@@ -XXX,XX +XXX,XX @@ static Property props_nvic[] = {
70
71
static void armv7m_nvic_reset(DeviceState *dev)
72
{
73
+ int resetprio;
74
NVICState *s = NVIC(dev);
75
76
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
77
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
78
s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
79
s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
80
81
- s->vectors[ARMV7M_EXCP_RESET].prio = -3;
82
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
83
+ s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
84
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
85
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
86
87
--
88
2.7.4
89
90
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/31] nvic: Make ICSR banked for v8M
Deleted patch
1
The ICSR NVIC register is banked for v8M. This doesn't
2
require any new state, but it does mean that some bits
3
are controlled by BFHNFNMINS and some bits must work
4
with the correct banked exception. There is also a new
5
in v8M PENDNMICLR bit.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 1505240046-11454-18-git-send-email-peter.maydell@linaro.org
10
---
11
hw/intc/armv7m_nvic.c | 45 ++++++++++++++++++++++++++++++++-------------
12
1 file changed, 32 insertions(+), 13 deletions(-)
13
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
17
+++ b/hw/intc/armv7m_nvic.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
19
}
20
case 0xd00: /* CPUID Base. */
21
return cpu->midr;
22
- case 0xd04: /* Interrupt Control State. */
23
+ case 0xd04: /* Interrupt Control State (ICSR) */
24
/* VECTACTIVE */
25
val = cpu->env.v7m.exception;
26
/* VECTPENDING */
27
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
28
if (nvic_rettobase(s)) {
29
val |= (1 << 11);
30
}
31
- /* PENDSTSET */
32
- if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
33
- val |= (1 << 26);
34
- }
35
- /* PENDSVSET */
36
- if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
37
- val |= (1 << 28);
38
+ if (attrs.secure) {
39
+ /* PENDSTSET */
40
+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {
41
+ val |= (1 << 26);
42
+ }
43
+ /* PENDSVSET */
44
+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {
45
+ val |= (1 << 28);
46
+ }
47
+ } else {
48
+ /* PENDSTSET */
49
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
50
+ val |= (1 << 26);
51
+ }
52
+ /* PENDSVSET */
53
+ if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
54
+ val |= (1 << 28);
55
+ }
56
}
57
/* NMIPENDSET */
58
- if (s->vectors[ARMV7M_EXCP_NMI].pending) {
59
+ if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
60
+ s->vectors[ARMV7M_EXCP_NMI].pending) {
61
val |= (1 << 31);
62
}
63
- /* ISRPREEMPT not implemented */
64
+ /* ISRPREEMPT: RES0 when halting debug not implemented */
65
+ /* STTNS: RES0 for the Main Extension */
66
return val;
67
case 0xd08: /* Vector Table Offset. */
68
return cpu->env.v7m.vecbase[attrs.secure];
69
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
70
nvic_irq_update(s);
71
break;
72
}
73
- case 0xd04: /* Interrupt Control State. */
74
- if (value & (1 << 31)) {
75
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
76
+ case 0xd04: /* Interrupt Control State (ICSR) */
77
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
78
+ if (value & (1 << 31)) {
79
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
80
+ } else if (value & (1 << 30) &&
81
+ arm_feature(&cpu->env, ARM_FEATURE_V8)) {
82
+ /* PENDNMICLR didn't exist in v7M */
83
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false);
84
+ }
85
}
86
if (value & (1 << 28)) {
87
armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
88
--
89
2.7.4
90
91
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/31] msf2: Add Smartfusion2 System timer
[PULL 24/24] target/arm: Implement MVE shifts by register
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
Implement the MVE shifts by register, which perform
2
shifts on a single general-purpose register.
2
3
3
Modelled System Timer in Microsemi's Smartfusion2 Soc.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Timer has two 32bit down counters and two interrupts.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
7
---
8
target/arm/helper-mve.h | 2 ++
9
target/arm/translate.h | 1 +
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
5
14
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20170920201737.25723-2-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/timer/Makefile.objs | 1 +
14
include/hw/timer/mss-timer.h | 64 ++++++++++
15
hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++
16
3 files changed, 354 insertions(+)
17
create mode 100644 include/hw/timer/mss-timer.h
18
create mode 100644 hw/timer/mss-timer.c
19
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
17
--- a/target/arm/helper-mve.h
23
+++ b/hw/timer/Makefile.objs
18
+++ b/target/arm/helper-mve.h
24
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
20
26
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
27
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
28
+common-obj-$(CONFIG_MSF2) += mss-timer.o
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
29
diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
30
new file mode 100644
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
31
index XXXXXXX..XXXXXXX
26
index XXXXXXX..XXXXXXX 100644
32
--- /dev/null
27
--- a/target/arm/translate.h
33
+++ b/include/hw/timer/mss-timer.h
28
+++ b/target/arm/translate.h
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
34
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
35
+/*
42
&mve_shl_ri rdalo rdahi shim
36
+ * Microsemi SmartFusion2 Timer.
43
&mve_shl_rr rdalo rdahi rm
37
+ *
44
&mve_sh_ri rda shim
38
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
45
+&mve_sh_rr rda rm
39
+ *
46
40
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
47
# rdahi: bits [3:1] from insn, bit 0 is 1
41
+ * of this software and associated documentation files (the "Software"), to deal
48
# rdalo: bits [3:1] from insn, bit 0 is 0
42
+ * in the Software without restriction, including without limitation the rights
49
@@ -XXX,XX +XXX,XX @@
43
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
44
+ * copies of the Software, and to permit persons to whom the Software is
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
45
+ * furnished to do so, subject to the following conditions:
52
&mve_sh_ri shim=%imm5_12_6
46
+ *
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
47
+ * The above copyright notice and this permission notice shall be included in
54
48
+ * all copies or substantial portions of the Software.
55
{
49
+ *
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
50
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
51
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
52
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
59
}
53
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
60
54
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
55
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
56
+ * THE SOFTWARE.
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
57
+ */
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
65
+ {
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
69
+ }
58
+
70
+
59
+#ifndef HW_MSS_TIMER_H
71
+ {
60
+#define HW_MSS_TIMER_H
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
75
+ }
61
+
76
+
62
+#include "hw/sysbus.h"
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
63
+#include "hw/ptimer.h"
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
64
+
88
+
65
+#define TYPE_MSS_TIMER "mss-timer"
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
66
+#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \
67
+ (obj), TYPE_MSS_TIMER)
68
+
69
+/*
70
+ * There are two 32-bit down counting timers.
71
+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer
72
+ * that operates either in Periodic mode or in One-shot mode.
73
+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
74
+ * In 64-bit mode, writing to the 32-bit registers has no effect.
75
+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers
76
+ * has no effect. Only two 32-bit timers are supported currently.
77
+ */
78
+#define NUM_TIMERS 2
79
+
80
+#define R_TIM1_MAX 6
81
+
82
+struct Msf2Timer {
83
+ QEMUBH *bh;
84
+ ptimer_state *ptimer;
85
+
86
+ uint32_t regs[R_TIM1_MAX];
87
+ qemu_irq irq;
88
+};
89
+
90
+typedef struct MSSTimerState {
91
+ SysBusDevice parent_obj;
92
+
93
+ MemoryRegion mmio;
94
+ uint32_t freq_hz;
95
+ struct Msf2Timer timers[NUM_TIMERS];
96
+} MSSTimerState;
97
+
98
+#endif /* HW_MSS_TIMER_H */
99
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
100
new file mode 100644
101
index XXXXXXX..XXXXXXX
102
--- /dev/null
103
+++ b/hw/timer/mss-timer.c
104
@@ -XXX,XX +XXX,XX @@
105
+/*
106
+ * Block model of System timer present in
107
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
108
+ *
109
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
110
+ *
111
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
112
+ * of this software and associated documentation files (the "Software"), to deal
113
+ * in the Software without restriction, including without limitation the rights
114
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
115
+ * copies of the Software, and to permit persons to whom the Software is
116
+ * furnished to do so, subject to the following conditions:
117
+ *
118
+ * The above copyright notice and this permission notice shall be included in
119
+ * all copies or substantial portions of the Software.
120
+ *
121
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
122
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
123
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
124
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
125
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
126
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
127
+ * THE SOFTWARE.
128
+ */
129
+
130
+#include "qemu/osdep.h"
131
+#include "qemu/main-loop.h"
132
+#include "qemu/log.h"
133
+#include "hw/timer/mss-timer.h"
134
+
135
+#ifndef MSS_TIMER_ERR_DEBUG
136
+#define MSS_TIMER_ERR_DEBUG 0
137
+#endif
138
+
139
+#define DB_PRINT_L(lvl, fmt, args...) do { \
140
+ if (MSS_TIMER_ERR_DEBUG >= lvl) { \
141
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
142
+ } \
143
+} while (0);
144
+
145
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
146
+
147
+#define R_TIM_VAL 0
148
+#define R_TIM_LOADVAL 1
149
+#define R_TIM_BGLOADVAL 2
150
+#define R_TIM_CTRL 3
151
+#define R_TIM_RIS 4
152
+#define R_TIM_MIS 5
153
+
154
+#define TIMER_CTRL_ENBL (1 << 0)
155
+#define TIMER_CTRL_ONESHOT (1 << 1)
156
+#define TIMER_CTRL_INTR (1 << 2)
157
+#define TIMER_RIS_ACK (1 << 0)
158
+#define TIMER_RST_CLR (1 << 6)
159
+#define TIMER_MODE (1 << 0)
160
+
161
+static void timer_update_irq(struct Msf2Timer *st)
162
+{
90
+{
163
+ bool isr, ier;
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
164
+
165
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
166
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
167
+ qemu_set_irq(st->irq, (ier && isr));
168
+}
92
+}
169
+
93
+
170
+static void timer_update(struct Msf2Timer *st)
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
171
+{
95
+{
172
+ uint64_t count;
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
173
+
97
+}
174
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
175
+ ptimer_stop(st->ptimer);
99
index XXXXXXX..XXXXXXX 100644
176
+ return;
100
--- a/target/arm/translate.c
101
+++ b/target/arm/translate.c
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
104
}
105
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
177
+ }
119
+ }
178
+
120
+
179
+ count = st->regs[R_TIM_LOADVAL];
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
180
+ ptimer_set_limit(st->ptimer, count, 1);
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
181
+ ptimer_run(st->ptimer, 1);
123
+ return true;
182
+}
124
+}
183
+
125
+
184
+static uint64_t
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
185
+timer_read(void *opaque, hwaddr offset, unsigned int size)
186
+{
127
+{
187
+ MSSTimerState *t = opaque;
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
188
+ hwaddr addr;
189
+ struct Msf2Timer *st;
190
+ uint32_t ret = 0;
191
+ int timer = 0;
192
+ int isr;
193
+ int ier;
194
+
195
+ addr = offset >> 2;
196
+ /*
197
+ * Two independent timers has same base address.
198
+ * Based on address passed figure out which timer is being used.
199
+ */
200
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
201
+ timer = 1;
202
+ addr -= R_TIM1_MAX;
203
+ }
204
+
205
+ st = &t->timers[timer];
206
+
207
+ switch (addr) {
208
+ case R_TIM_VAL:
209
+ ret = ptimer_get_count(st->ptimer);
210
+ break;
211
+
212
+ case R_TIM_MIS:
213
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
214
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
215
+ ret = ier & isr;
216
+ break;
217
+
218
+ default:
219
+ if (addr < R_TIM1_MAX) {
220
+ ret = st->regs[addr];
221
+ } else {
222
+ qemu_log_mask(LOG_GUEST_ERROR,
223
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
224
+ return ret;
225
+ }
226
+ break;
227
+ }
228
+
229
+ DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset,
230
+ ret);
231
+ return ret;
232
+}
129
+}
233
+
130
+
234
+static void
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
235
+timer_write(void *opaque, hwaddr offset,
236
+ uint64_t val64, unsigned int size)
237
+{
132
+{
238
+ MSSTimerState *t = opaque;
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
239
+ hwaddr addr;
240
+ struct Msf2Timer *st;
241
+ int timer = 0;
242
+ uint32_t value = val64;
243
+
244
+ addr = offset >> 2;
245
+ /*
246
+ * Two independent timers has same base address.
247
+ * Based on addr passed figure out which timer is being used.
248
+ */
249
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
250
+ timer = 1;
251
+ addr -= R_TIM1_MAX;
252
+ }
253
+
254
+ st = &t->timers[timer];
255
+
256
+ DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
257
+ value, timer);
258
+
259
+ switch (addr) {
260
+ case R_TIM_CTRL:
261
+ st->regs[R_TIM_CTRL] = value;
262
+ timer_update(st);
263
+ break;
264
+
265
+ case R_TIM_RIS:
266
+ if (value & TIMER_RIS_ACK) {
267
+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
268
+ }
269
+ break;
270
+
271
+ case R_TIM_LOADVAL:
272
+ st->regs[R_TIM_LOADVAL] = value;
273
+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
274
+ timer_update(st);
275
+ }
276
+ break;
277
+
278
+ case R_TIM_BGLOADVAL:
279
+ st->regs[R_TIM_BGLOADVAL] = value;
280
+ st->regs[R_TIM_LOADVAL] = value;
281
+ break;
282
+
283
+ case R_TIM_VAL:
284
+ case R_TIM_MIS:
285
+ break;
286
+
287
+ default:
288
+ if (addr < R_TIM1_MAX) {
289
+ st->regs[addr] = value;
290
+ } else {
291
+ qemu_log_mask(LOG_GUEST_ERROR,
292
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
293
+ return;
294
+ }
295
+ break;
296
+ }
297
+ timer_update_irq(st);
298
+}
134
+}
299
+
135
+
300
+static const MemoryRegionOps timer_ops = {
136
/*
301
+ .read = timer_read,
137
* Multiply and multiply accumulate
302
+ .write = timer_write,
138
*/
303
+ .endianness = DEVICE_NATIVE_ENDIAN,
304
+ .valid = {
305
+ .min_access_size = 1,
306
+ .max_access_size = 4
307
+ }
308
+};
309
+
310
+static void timer_hit(void *opaque)
311
+{
312
+ struct Msf2Timer *st = opaque;
313
+
314
+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
315
+
316
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
317
+ timer_update(st);
318
+ }
319
+ timer_update_irq(st);
320
+}
321
+
322
+static void mss_timer_init(Object *obj)
323
+{
324
+ MSSTimerState *t = MSS_TIMER(obj);
325
+ int i;
326
+
327
+ /* Init all the ptimers. */
328
+ for (i = 0; i < NUM_TIMERS; i++) {
329
+ struct Msf2Timer *st = &t->timers[i];
330
+
331
+ st->bh = qemu_bh_new(timer_hit, st);
332
+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
333
+ ptimer_set_freq(st->ptimer, t->freq_hz);
334
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
335
+ }
336
+
337
+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
338
+ NUM_TIMERS * R_TIM1_MAX * 4);
339
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
340
+}
341
+
342
+static const VMStateDescription vmstate_timers = {
343
+ .name = "mss-timer-block",
344
+ .version_id = 1,
345
+ .minimum_version_id = 1,
346
+ .fields = (VMStateField[]) {
347
+ VMSTATE_PTIMER(ptimer, struct Msf2Timer),
348
+ VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),
349
+ VMSTATE_END_OF_LIST()
350
+ }
351
+};
352
+
353
+static const VMStateDescription vmstate_mss_timer = {
354
+ .name = TYPE_MSS_TIMER,
355
+ .version_id = 1,
356
+ .minimum_version_id = 1,
357
+ .fields = (VMStateField[]) {
358
+ VMSTATE_UINT32(freq_hz, MSSTimerState),
359
+ VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
360
+ vmstate_timers, struct Msf2Timer),
361
+ VMSTATE_END_OF_LIST()
362
+ }
363
+};
364
+
365
+static Property mss_timer_properties[] = {
366
+ /* Libero GUI shows 100Mhz as default for clocks */
367
+ DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
368
+ 100 * 1000000),
369
+ DEFINE_PROP_END_OF_LIST(),
370
+};
371
+
372
+static void mss_timer_class_init(ObjectClass *klass, void *data)
373
+{
374
+ DeviceClass *dc = DEVICE_CLASS(klass);
375
+
376
+ dc->props = mss_timer_properties;
377
+ dc->vmsd = &vmstate_mss_timer;
378
+}
379
+
380
+static const TypeInfo mss_timer_info = {
381
+ .name = TYPE_MSS_TIMER,
382
+ .parent = TYPE_SYS_BUS_DEVICE,
383
+ .instance_size = sizeof(MSSTimerState),
384
+ .instance_init = mss_timer_init,
385
+ .class_init = mss_timer_class_init,
386
+};
387
+
388
+static void mss_timer_register_types(void)
389
+{
390
+ type_register_static(&mss_timer_info);
391
+}
392
+
393
+type_init(mss_timer_register_types)
394
--
139
--
395
2.7.4
140
2.20.1
396
141
397
142
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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