1
ARM queue: mostly patches from me, but also the Smartfusion2 board.
1
target-arm queue: I have a lot more still in my to-review
2
queue, but my rule of thumb is when I get to 50 patches or
3
so to send out what I have.
2
4
3
thanks
5
thanks
4
-- PMM
6
-- PMM
5
7
6
The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:
8
The following changes since commit 9a7beaad3dbba982f7a461d676b55a5c3851d312:
7
9
8
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)
10
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging (2021-03-05 10:47:46 +0000)
9
11
10
are available in the git repository at:
12
are available in the Git repository at:
11
13
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210305
13
15
14
for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:
16
for you to fetch changes up to 2c669ff88ec6733420a000103a2b8b9e93df4945:
15
17
16
msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)
18
hw/arm/mps2: Update old infocenter.arm.com URLs (2021-03-05 15:17:38 +0000)
17
19
18
----------------------------------------------------------------
20
----------------------------------------------------------------
19
target-arm queue:
21
* sbsa-ref: remove cortex-a53 from list of supported cpus
20
* more preparatory work for v8M support
22
* sbsa-ref: add 'max' to list of allowed cpus
21
* convert some omap devices away from old_mmio
23
* target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
22
* remove out of date ARM ARM section references in comments
24
* npcm7xx: add EMC model
23
* add the Smartfusion2 board
25
* xlnx-zynqmp: Remove obsolete 'has_rpu' property
26
* target/arm: Speed up aarch64 TBL/TBX
27
* virtio-mmio: improve virtio-mmio get_dev_path alog
28
* target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
29
* target/arm: Restrict v8M IDAU to TCG
30
* target/arm/cpu: Update coding style to make checkpatch.pl happy
31
* musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB surfaces
32
* Add new board: mps3-an524
24
33
25
----------------------------------------------------------------
34
----------------------------------------------------------------
26
Peter Maydell (26):
35
Doug Evans (3):
27
target/arm: Implement MSR/MRS access to NS banked registers
36
hw/net: Add npcm7xx emc model
28
nvic: Add banked exception states
37
hw/arm: Add npcm7xx emc model
29
nvic: Add cached vectpending_is_s_banked state
38
tests/qtests: Add npcm7xx emc model test
30
nvic: Add cached vectpending_prio state
31
nvic: Implement AIRCR changes for v8M
32
nvic: Make ICSR.RETTOBASE handle banked exceptions
33
nvic: Implement NVIC_ITNS<n> registers
34
nvic: Handle banked exceptions in nvic_recompute_state()
35
nvic: Make set_pending and clear_pending take a secure parameter
36
nvic: Make SHPR registers banked
37
nvic: Compare group priority for escalation to HF
38
nvic: In escalation to HardFault, support HF not being priority -1
39
nvic: Implement v8M changes to fixed priority exceptions
40
nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
41
nvic: Handle v8M changes in nvic_exec_prio()
42
target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
43
nvic: Make ICSR banked for v8M
44
nvic: Make SHCSR banked for v8M
45
nvic: Support banked exceptions in acknowledge and complete
46
target/arm: Remove out of date ARM ARM section references in A64 decoder
47
hw/arm/palm.c: Don't use old_mmio for static_ops
48
hw/gpio/omap_gpio.c: Don't use old_mmio
49
hw/timer/omap_synctimer.c: Don't use old_mmio
50
hw/timer/omap_gptimer: Don't use old_mmio
51
hw/i2c/omap_i2c.c: Don't use old_mmio
52
hw/arm/omap2.c: Don't use old_mmio
53
39
54
Subbaraya Sundeep (5):
40
Marcin Juszkiewicz (2):
55
msf2: Add Smartfusion2 System timer
41
sbsa-ref: remove cortex-a53 from list of supported cpus
56
msf2: Microsemi Smartfusion2 System Register block
42
sbsa-ref: add 'max' to list of allowed cpus
57
msf2: Add Smartfusion2 SPI controller
58
msf2: Add Smartfusion2 SoC
59
msf2: Add Emcraft's Smartfusion2 SOM kit
60
43
61
hw/arm/Makefile.objs | 1 +
44
Peter Collingbourne (1):
62
hw/misc/Makefile.objs | 1 +
45
target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
63
hw/ssi/Makefile.objs | 1 +
64
hw/timer/Makefile.objs | 1 +
65
include/hw/arm/msf2-soc.h | 67 +++
66
include/hw/intc/armv7m_nvic.h | 33 +-
67
include/hw/misc/msf2-sysreg.h | 77 ++++
68
include/hw/ssi/mss-spi.h | 58 +++
69
include/hw/timer/mss-timer.h | 64 +++
70
target/arm/cpu.h | 62 ++-
71
hw/arm/msf2-soc.c | 238 +++++++++++
72
hw/arm/msf2-som.c | 105 +++++
73
hw/arm/omap2.c | 49 ++-
74
hw/arm/palm.c | 30 +-
75
hw/gpio/omap_gpio.c | 26 +-
76
hw/i2c/omap_i2c.c | 44 +-
77
hw/intc/armv7m_nvic.c | 913 ++++++++++++++++++++++++++++++++++------
78
hw/misc/msf2-sysreg.c | 160 +++++++
79
hw/ssi/mss-spi.c | 404 ++++++++++++++++++
80
hw/timer/mss-timer.c | 289 +++++++++++++
81
hw/timer/omap_gptimer.c | 49 ++-
82
hw/timer/omap_synctimer.c | 35 +-
83
target/arm/cpu.c | 7 +
84
target/arm/helper.c | 142 ++++++-
85
target/arm/translate-a64.c | 227 +++++-----
86
default-configs/arm-softmmu.mak | 1 +
87
hw/intc/trace-events | 13 +-
88
hw/misc/trace-events | 5 +
89
28 files changed, 2735 insertions(+), 367 deletions(-)
90
create mode 100644 include/hw/arm/msf2-soc.h
91
create mode 100644 include/hw/misc/msf2-sysreg.h
92
create mode 100644 include/hw/ssi/mss-spi.h
93
create mode 100644 include/hw/timer/mss-timer.h
94
create mode 100644 hw/arm/msf2-soc.c
95
create mode 100644 hw/arm/msf2-som.c
96
create mode 100644 hw/misc/msf2-sysreg.c
97
create mode 100644 hw/ssi/mss-spi.c
98
create mode 100644 hw/timer/mss-timer.c
99
46
47
Peter Maydell (34):
48
hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces
49
hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces
50
hw/display/tc6393xb: Expand out macros in template header
51
hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite
52
hw/display/omap_lcdc: Expand out macros in template header
53
hw/display/omap_lcdc: Drop broken bigendian ifdef
54
hw/display/omap_lcdc: Fix coding style issues in template header
55
hw/display/omap_lcdc: Inline template header into C file
56
hw/display/omap_lcdc: Delete unnecessary macro
57
hw/display/tcx: Drop unnecessary code for handling BGR format outputs
58
hw/arm/mps2-tz: Make SYSCLK frequency board-specific
59
hw/misc/mps2-scc: Support configurable number of OSCCLK values
60
hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511
61
hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board
62
hw/misc/mps2-fpgaio: Make number of LEDs configurable by board
63
hw/misc/mps2-fpgaio: Support SWITCH register
64
hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board
65
hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type
66
hw/arm/mps2-tz: Make number of IRQs board-specific
67
hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
68
hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI
69
hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts
70
hw/arm/mps2-tz: Move device IRQ info to data structures
71
hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs
72
hw/arm/mps2-tz: Allow boards to have different PPCInfo data
73
hw/arm/mps2-tz: Make RAM arrangement board-specific
74
hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data
75
hw/arm/mps2-tz: Support ROMs as well as RAMs
76
hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo
77
hw/arm/mps2-tz: Add new mps3-an524 board
78
hw/arm/mps2-tz: Stub out USB controller for mps3-an524
79
hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524
80
docs/system/arm/mps2.rst: Document the new mps3-an524 board
81
hw/arm/mps2: Update old infocenter.arm.com URLs
82
83
Philippe Mathieu-Daudé (4):
84
hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property
85
hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init()
86
target/arm: Restrict v8M IDAU to TCG
87
target/arm/cpu: Update coding style to make checkpatch.pl happy
88
89
Rebecca Cran (3):
90
target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
91
target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
92
target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU
93
94
Richard Henderson (1):
95
target/arm: Speed up aarch64 TBL/TBX
96
97
schspa (1):
98
virtio-mmio: improve virtio-mmio get_dev_path alog
99
100
docs/system/arm/mps2.rst | 24 +-
101
docs/system/arm/nuvoton.rst | 3 +-
102
hw/display/omap_lcd_template.h | 169 --------
103
hw/display/tc6393xb_template.h | 72 ----
104
include/hw/arm/armsse.h | 4 +-
105
include/hw/arm/npcm7xx.h | 2 +
106
include/hw/arm/xlnx-zynqmp.h | 2 -
107
include/hw/misc/armsse-cpuid.h | 2 +-
108
include/hw/misc/armsse-mhu.h | 2 +-
109
include/hw/misc/iotkit-secctl.h | 2 +-
110
include/hw/misc/iotkit-sysctl.h | 2 +-
111
include/hw/misc/iotkit-sysinfo.h | 2 +-
112
include/hw/misc/mps2-fpgaio.h | 8 +-
113
include/hw/misc/mps2-scc.h | 10 +-
114
include/hw/net/npcm7xx_emc.h | 286 +++++++++++++
115
include/ui/console.h | 10 -
116
target/arm/cpu.h | 15 +-
117
target/arm/helper-a64.h | 2 +-
118
target/arm/internals.h | 6 +
119
hw/arm/mps2-tz.c | 632 +++++++++++++++++++++++-----
120
hw/arm/mps2.c | 5 +
121
hw/arm/musicpal.c | 64 ++-
122
hw/arm/npcm7xx.c | 50 ++-
123
hw/arm/sbsa-ref.c | 2 +-
124
hw/arm/xlnx-zynqmp.c | 6 -
125
hw/display/omap_lcdc.c | 129 +++++-
126
hw/display/tc6393xb.c | 48 +--
127
hw/display/tcx.c | 31 +-
128
hw/i2c/npcm7xx_smbus.c | 1 -
129
hw/misc/armsse-cpuid.c | 2 +-
130
hw/misc/armsse-mhu.c | 2 +-
131
hw/misc/iotkit-sysctl.c | 2 +-
132
hw/misc/iotkit-sysinfo.c | 2 +-
133
hw/misc/mps2-fpgaio.c | 43 +-
134
hw/misc/mps2-scc.c | 93 ++++-
135
hw/net/npcm7xx_emc.c | 857 ++++++++++++++++++++++++++++++++++++++
136
hw/virtio/virtio-mmio.c | 13 +-
137
target/arm/cpu.c | 23 +-
138
target/arm/cpu64.c | 5 +
139
target/arm/cpu_tcg.c | 8 +
140
target/arm/helper-a64.c | 32 --
141
target/arm/helper.c | 39 +-
142
target/arm/mte_helper.c | 13 +-
143
target/arm/translate-a64.c | 70 +---
144
target/arm/vec_helper.c | 48 +++
145
tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++++++++
146
hw/net/meson.build | 1 +
147
hw/net/trace-events | 17 +
148
tests/qtest/meson.build | 3 +-
149
49 files changed, 3098 insertions(+), 628 deletions(-)
150
delete mode 100644 hw/display/omap_lcd_template.h
151
delete mode 100644 hw/display/tc6393xb_template.h
152
create mode 100644 include/hw/net/npcm7xx_emc.h
153
create mode 100644 hw/net/npcm7xx_emc.c
154
create mode 100644 tests/qtest/npcm7xx_emc-test.c
155
diff view generated by jsdifflib
New patch
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
1
2
3
Cortex-A53 supports 40bits of address space. sbsa-ref's memory starts
4
above this limit.
5
6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Acked-by: Leif Lindholm <leif@nuviainc.com>
9
Message-id: 20210216150122.3830863-2-marcin.juszkiewicz@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/sbsa-ref.c | 1 -
13
1 file changed, 1 deletion(-)
14
15
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/sbsa-ref.c
18
+++ b/hw/arm/sbsa-ref.c
19
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
20
};
21
22
static const char * const valid_cpus[] = {
23
- ARM_CPU_TYPE_NAME("cortex-a53"),
24
ARM_CPU_TYPE_NAME("cortex-a57"),
25
ARM_CPU_TYPE_NAME("cortex-a72"),
26
};
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
1
2
3
Let add 'max' cpu while work goes on adding newer CPU types than
4
Cortex-A72. This allows us to check SVE etc support.
5
6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
7
Acked-by: Leif Lindholm <leif@nuviainc.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210216150122.3830863-3-marcin.juszkiewicz@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/sbsa-ref.c | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/sbsa-ref.c
18
+++ b/hw/arm/sbsa-ref.c
19
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
20
static const char * const valid_cpus[] = {
21
ARM_CPU_TYPE_NAME("cortex-a57"),
22
ARM_CPU_TYPE_NAME("cortex-a72"),
23
+ ARM_CPU_TYPE_NAME("max"),
24
};
25
26
static bool cpu_type_valid(const char *cpu)
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Rebecca Cran <rebecca@nuviainc.com>
2
2
3
Modelled Microsemi's Smartfusion2 SPI controller.
3
Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
4
optional feature in ARMv8.0, and mandatory in ARMv8.5.
4
5
5
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210216224543.16142-2-rebecca@nuviainc.com
8
Message-id: 20170920201737.25723-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/ssi/Makefile.objs | 1 +
11
target/arm/cpu.h | 15 ++++++++++++++-
12
include/hw/ssi/mss-spi.h | 58 +++++++
12
target/arm/internals.h | 6 ++++++
13
hw/ssi/mss-spi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++
13
target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++
14
3 files changed, 463 insertions(+)
14
target/arm/translate-a64.c | 12 ++++++++++++
15
create mode 100644 include/hw/ssi/mss-spi.h
15
4 files changed, 69 insertions(+), 1 deletion(-)
16
create mode 100644 hw/ssi/mss-spi.c
17
16
18
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ssi/Makefile.objs
19
--- a/target/arm/cpu.h
21
+++ b/hw/ssi/Makefile.objs
20
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
21
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
23
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
22
#define SCTLR_TE (1U << 30) /* AArch32 only */
24
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
23
#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
25
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
24
#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
26
+common-obj-$(CONFIG_MSF2) += mss-spi.o
25
+#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
27
26
#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
28
obj-$(CONFIG_OMAP) += omap_spi.o
27
#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
29
obj-$(CONFIG_IMX) += imx_spi.o
28
#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
30
diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
29
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
31
new file mode 100644
30
#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
32
index XXXXXXX..XXXXXXX
31
#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
33
--- /dev/null
32
#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
34
+++ b/include/hw/ssi/mss-spi.h
33
-#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */
35
@@ -XXX,XX +XXX,XX @@
34
+#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
36
+/*
35
37
+ * Microsemi SmartFusion2 SPI
36
#define CPTR_TCPAC (1U << 31)
38
+ *
37
#define CPTR_TTA (1U << 20)
39
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
38
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
40
+ *
39
#define CPSR_IL (1U << 20)
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
40
#define CPSR_DIT (1U << 21)
42
+ * of this software and associated documentation files (the "Software"), to deal
41
#define CPSR_PAN (1U << 22)
43
+ * in the Software without restriction, including without limitation the rights
42
+#define CPSR_SSBS (1U << 23)
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
43
#define CPSR_J (1U << 24)
45
+ * copies of the Software, and to permit persons to whom the Software is
44
#define CPSR_IT_0_1 (3U << 25)
46
+ * furnished to do so, subject to the following conditions:
45
#define CPSR_Q (1U << 27)
47
+ *
46
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
48
+ * The above copyright notice and this permission notice shall be included in
47
#define PSTATE_A (1U << 8)
49
+ * all copies or substantial portions of the Software.
48
#define PSTATE_D (1U << 9)
50
+ *
49
#define PSTATE_BTYPE (3U << 10)
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
50
+#define PSTATE_SSBS (1U << 12)
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
51
#define PSTATE_IL (1U << 20)
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
52
#define PSTATE_SS (1U << 21)
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
53
#define PSTATE_PAN (1U << 22)
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
54
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
55
return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
57
+ * THE SOFTWARE.
56
}
58
+ */
57
59
+
58
+static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
60
+#ifndef HW_MSS_SPI_H
61
+#define HW_MSS_SPI_H
62
+
63
+#include "hw/sysbus.h"
64
+#include "hw/ssi/ssi.h"
65
+#include "qemu/fifo32.h"
66
+
67
+#define TYPE_MSS_SPI "mss-spi"
68
+#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
69
+
70
+#define R_SPI_MAX 16
71
+
72
+typedef struct MSSSpiState {
73
+ SysBusDevice parent_obj;
74
+
75
+ MemoryRegion mmio;
76
+
77
+ qemu_irq irq;
78
+
79
+ qemu_irq cs_line;
80
+
81
+ SSIBus *spi;
82
+
83
+ Fifo32 rx_fifo;
84
+ Fifo32 tx_fifo;
85
+
86
+ int fifo_depth;
87
+ uint32_t frame_count;
88
+ bool enabled;
89
+
90
+ uint32_t regs[R_SPI_MAX];
91
+} MSSSpiState;
92
+
93
+#endif /* HW_MSS_SPI_H */
94
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
95
new file mode 100644
96
index XXXXXXX..XXXXXXX
97
--- /dev/null
98
+++ b/hw/ssi/mss-spi.c
99
@@ -XXX,XX +XXX,XX @@
100
+/*
101
+ * Block model of SPI controller present in
102
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
103
+ *
104
+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
105
+ *
106
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
107
+ * of this software and associated documentation files (the "Software"), to deal
108
+ * in the Software without restriction, including without limitation the rights
109
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
110
+ * copies of the Software, and to permit persons to whom the Software is
111
+ * furnished to do so, subject to the following conditions:
112
+ *
113
+ * The above copyright notice and this permission notice shall be included in
114
+ * all copies or substantial portions of the Software.
115
+ *
116
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
117
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
118
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
119
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
120
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
121
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
122
+ * THE SOFTWARE.
123
+ */
124
+
125
+#include "qemu/osdep.h"
126
+#include "hw/ssi/mss-spi.h"
127
+#include "qemu/log.h"
128
+
129
+#ifndef MSS_SPI_ERR_DEBUG
130
+#define MSS_SPI_ERR_DEBUG 0
131
+#endif
132
+
133
+#define DB_PRINT_L(lvl, fmt, args...) do { \
134
+ if (MSS_SPI_ERR_DEBUG >= lvl) { \
135
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
136
+ } \
137
+} while (0);
138
+
139
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
140
+
141
+#define FIFO_CAPACITY 32
142
+
143
+#define R_SPI_CONTROL 0
144
+#define R_SPI_DFSIZE 1
145
+#define R_SPI_STATUS 2
146
+#define R_SPI_INTCLR 3
147
+#define R_SPI_RX 4
148
+#define R_SPI_TX 5
149
+#define R_SPI_CLKGEN 6
150
+#define R_SPI_SS 7
151
+#define R_SPI_MIS 8
152
+#define R_SPI_RIS 9
153
+
154
+#define S_TXDONE (1 << 0)
155
+#define S_RXRDY (1 << 1)
156
+#define S_RXCHOVRF (1 << 2)
157
+#define S_RXFIFOFUL (1 << 4)
158
+#define S_RXFIFOFULNXT (1 << 5)
159
+#define S_RXFIFOEMP (1 << 6)
160
+#define S_RXFIFOEMPNXT (1 << 7)
161
+#define S_TXFIFOFUL (1 << 8)
162
+#define S_TXFIFOFULNXT (1 << 9)
163
+#define S_TXFIFOEMP (1 << 10)
164
+#define S_TXFIFOEMPNXT (1 << 11)
165
+#define S_FRAMESTART (1 << 12)
166
+#define S_SSEL (1 << 13)
167
+#define S_ACTIVE (1 << 14)
168
+
169
+#define C_ENABLE (1 << 0)
170
+#define C_MODE (1 << 1)
171
+#define C_INTRXDATA (1 << 4)
172
+#define C_INTTXDATA (1 << 5)
173
+#define C_INTRXOVRFLO (1 << 6)
174
+#define C_SPS (1 << 26)
175
+#define C_BIGFIFO (1 << 29)
176
+#define C_RESET (1 << 31)
177
+
178
+#define FRAMESZ_MASK 0x1F
179
+#define FMCOUNT_MASK 0x00FFFF00
180
+#define FMCOUNT_SHIFT 8
181
+
182
+static void txfifo_reset(MSSSpiState *s)
183
+{
59
+{
184
+ fifo32_reset(&s->tx_fifo);
60
+ return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
185
+
186
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
187
+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
188
+}
61
+}
189
+
62
+
190
+static void rxfifo_reset(MSSSpiState *s)
63
/*
64
* 64-bit feature tests via id registers.
65
*/
66
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
67
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
68
}
69
70
+static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
191
+{
71
+{
192
+ fifo32_reset(&s->rx_fifo);
72
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
193
+
194
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
195
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
196
+}
73
+}
197
+
74
+
198
+static void set_fifodepth(MSSSpiState *s)
75
/*
76
* Feature tests for "does this exist in either 32-bit or 64-bit?"
77
*/
78
diff --git a/target/arm/internals.h b/target/arm/internals.h
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/arm/internals.h
81
+++ b/target/arm/internals.h
82
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
83
if (isar_feature_aa32_dit(id)) {
84
valid |= CPSR_DIT;
85
}
86
+ if (isar_feature_aa32_ssbs(id)) {
87
+ valid |= CPSR_SSBS;
88
+ }
89
90
return valid;
91
}
92
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
93
if (isar_feature_aa64_dit(id)) {
94
valid |= PSTATE_DIT;
95
}
96
+ if (isar_feature_aa64_ssbs(id)) {
97
+ valid |= PSTATE_SSBS;
98
+ }
99
if (isar_feature_aa64_mte(id)) {
100
valid |= PSTATE_TCO;
101
}
102
diff --git a/target/arm/helper.c b/target/arm/helper.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/helper.c
105
+++ b/target/arm/helper.c
106
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dit_reginfo = {
107
.readfn = aa64_dit_read, .writefn = aa64_dit_write
108
};
109
110
+static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri)
199
+{
111
+{
200
+ unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
112
+ return env->pstate & PSTATE_SSBS;
201
+
202
+ if (size <= 8) {
203
+ s->fifo_depth = 32;
204
+ } else if (size <= 16) {
205
+ s->fifo_depth = 16;
206
+ } else if (size <= 32) {
207
+ s->fifo_depth = 8;
208
+ } else {
209
+ s->fifo_depth = 4;
210
+ }
211
+}
113
+}
212
+
114
+
213
+static void update_mis(MSSSpiState *s)
115
+static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
116
+ uint64_t value)
214
+{
117
+{
215
+ uint32_t reg = s->regs[R_SPI_CONTROL];
118
+ env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS);
216
+ uint32_t tmp;
217
+
218
+ /*
219
+ * form the Control register interrupt enable bits
220
+ * same as RIS, MIS and Interrupt clear registers for simplicity
221
+ */
222
+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
223
+ ((reg & C_INTTXDATA) >> 5);
224
+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
225
+}
119
+}
226
+
120
+
227
+static void spi_update_irq(MSSSpiState *s)
121
+static const ARMCPRegInfo ssbs_reginfo = {
228
+{
122
+ .name = "SSBS", .state = ARM_CP_STATE_AA64,
229
+ int irq;
123
+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6,
124
+ .type = ARM_CP_NO_RAW, .access = PL0_RW,
125
+ .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write
126
+};
230
+
127
+
231
+ update_mis(s);
128
static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
232
+ irq = !!(s->regs[R_SPI_MIS]);
129
const ARMCPRegInfo *ri,
233
+
130
bool isread)
234
+ qemu_set_irq(s->irq, irq);
131
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
235
+}
132
if (cpu_isar_feature(aa64_dit, cpu)) {
236
+
133
define_one_arm_cp_reg(cpu, &dit_reginfo);
237
+static void mss_spi_reset(DeviceState *d)
134
}
238
+{
135
+ if (cpu_isar_feature(aa64_ssbs, cpu)) {
239
+ MSSSpiState *s = MSS_SPI(d);
136
+ define_one_arm_cp_reg(cpu, &ssbs_reginfo);
240
+
137
+ }
241
+ memset(s->regs, 0, sizeof s->regs);
138
242
+ s->regs[R_SPI_CONTROL] = 0x80000102;
139
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
243
+ s->regs[R_SPI_DFSIZE] = 0x4;
140
define_arm_cp_regs(cpu, vhe_reginfo);
244
+ s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
141
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
245
+ s->regs[R_SPI_CLKGEN] = 0x7;
142
env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
246
+ s->regs[R_SPI_RIS] = 0x0;
143
env->daif |= mask;
247
+
144
248
+ s->fifo_depth = 4;
145
+ if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
249
+ s->frame_count = 1;
146
+ if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
250
+ s->enabled = false;
147
+ env->uncached_cpsr |= CPSR_SSBS;
251
+
252
+ rxfifo_reset(s);
253
+ txfifo_reset(s);
254
+}
255
+
256
+static uint64_t
257
+spi_read(void *opaque, hwaddr addr, unsigned int size)
258
+{
259
+ MSSSpiState *s = opaque;
260
+ uint32_t ret = 0;
261
+
262
+ addr >>= 2;
263
+ switch (addr) {
264
+ case R_SPI_RX:
265
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
266
+ s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
267
+ ret = fifo32_pop(&s->rx_fifo);
268
+ if (fifo32_is_empty(&s->rx_fifo)) {
269
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
270
+ }
271
+ break;
272
+
273
+ case R_SPI_MIS:
274
+ update_mis(s);
275
+ ret = s->regs[R_SPI_MIS];
276
+ break;
277
+
278
+ default:
279
+ if (addr < ARRAY_SIZE(s->regs)) {
280
+ ret = s->regs[addr];
281
+ } else {
148
+ } else {
282
+ qemu_log_mask(LOG_GUEST_ERROR,
149
+ env->uncached_cpsr &= ~CPSR_SSBS;
283
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
284
+ addr * 4);
285
+ return ret;
286
+ }
287
+ break;
288
+ }
289
+
290
+ DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
291
+ spi_update_irq(s);
292
+ return ret;
293
+}
294
+
295
+static void assert_cs(MSSSpiState *s)
296
+{
297
+ qemu_set_irq(s->cs_line, 0);
298
+}
299
+
300
+static void deassert_cs(MSSSpiState *s)
301
+{
302
+ qemu_set_irq(s->cs_line, 1);
303
+}
304
+
305
+static void spi_flush_txfifo(MSSSpiState *s)
306
+{
307
+ uint32_t tx;
308
+ uint32_t rx;
309
+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
310
+
311
+ /*
312
+ * Chip Select(CS) is automatically controlled by this controller.
313
+ * If SPS bit is set in Control register then CS is asserted
314
+ * until all the frames set in frame count of Control register are
315
+ * transferred. If SPS is not set then CS pulses between frames.
316
+ * Note that Slave Select register specifies which of the CS line
317
+ * has to be controlled automatically by controller. Bits SS[7:1] are for
318
+ * masters in FPGA fabric since we model only Microcontroller subsystem
319
+ * of Smartfusion2 we control only one CS(SS[0]) line.
320
+ */
321
+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
322
+ assert_cs(s);
323
+
324
+ s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
325
+
326
+ tx = fifo32_pop(&s->tx_fifo);
327
+ DB_PRINT("data tx:0x%" PRIx32, tx);
328
+ rx = ssi_transfer(s->spi, tx);
329
+ DB_PRINT("data rx:0x%" PRIx32, rx);
330
+
331
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
332
+ s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
333
+ s->regs[R_SPI_RIS] |= S_RXCHOVRF;
334
+ } else {
335
+ fifo32_push(&s->rx_fifo, rx);
336
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
337
+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
338
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
339
+ } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
340
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
341
+ }
342
+ }
343
+ s->frame_count--;
344
+ if (!sps) {
345
+ deassert_cs(s);
346
+ }
150
+ }
347
+ }
151
+ }
348
+
152
+
349
+ if (!s->frame_count) {
153
if (new_mode == ARM_CPU_MODE_HYP) {
350
+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
154
env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
351
+ FMCOUNT_SHIFT;
155
env->elr_el[2] = env->regs[15];
352
+ deassert_cs(s);
156
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
353
+ s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
157
new_mode |= PSTATE_TCO;
354
+ s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
158
}
355
+ }
159
356
+}
160
+ if (cpu_isar_feature(aa64_ssbs, cpu)) {
161
+ if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) {
162
+ new_mode |= PSTATE_SSBS;
163
+ } else {
164
+ new_mode &= ~PSTATE_SSBS;
165
+ }
166
+ }
357
+
167
+
358
+static void spi_write(void *opaque, hwaddr addr,
168
pstate_write(env, PSTATE_DAIF | new_mode);
359
+ uint64_t val64, unsigned int size)
169
env->aarch64 = 1;
360
+{
170
aarch64_restore_sp(env, new_el);
361
+ MSSSpiState *s = opaque;
171
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
362
+ uint32_t value = val64;
172
index XXXXXXX..XXXXXXX 100644
363
+
173
--- a/target/arm/translate-a64.c
364
+ DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
174
+++ b/target/arm/translate-a64.c
365
+ addr >>= 2;
175
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
366
+
176
tcg_temp_free_i32(t1);
367
+ switch (addr) {
177
break;
368
+ case R_SPI_TX:
178
369
+ /* adding to already full FIFO */
179
+ case 0x19: /* SSBS */
370
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
180
+ if (!dc_isar_feature(aa64_ssbs, s)) {
371
+ break;
181
+ goto do_unallocated;
372
+ }
182
+ }
373
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
183
+ if (crm & 1) {
374
+ fifo32_push(&s->tx_fifo, value);
184
+ set_pstate_bits(PSTATE_SSBS);
375
+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
185
+ } else {
376
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
186
+ clear_pstate_bits(PSTATE_SSBS);
377
+ } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
378
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
379
+ }
187
+ }
380
+ if (s->enabled) {
188
+ /* Don't need to rebuild hflags since SSBS is a nop */
381
+ spi_flush_txfifo(s);
382
+ }
383
+ break;
189
+ break;
384
+
190
+
385
+ case R_SPI_CONTROL:
191
case 0x1a: /* DIT */
386
+ s->regs[R_SPI_CONTROL] = value;
192
if (!dc_isar_feature(aa64_dit, s)) {
387
+ if (value & C_BIGFIFO) {
193
goto do_unallocated;
388
+ set_fifodepth(s);
389
+ } else {
390
+ s->fifo_depth = 4;
391
+ }
392
+ s->enabled = value & C_ENABLE;
393
+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
394
+ if (value & C_RESET) {
395
+ mss_spi_reset(DEVICE(s));
396
+ }
397
+ break;
398
+
399
+ case R_SPI_DFSIZE:
400
+ if (s->enabled) {
401
+ break;
402
+ }
403
+ s->regs[R_SPI_DFSIZE] = value;
404
+ break;
405
+
406
+ case R_SPI_INTCLR:
407
+ s->regs[R_SPI_INTCLR] = value;
408
+ if (value & S_TXDONE) {
409
+ s->regs[R_SPI_RIS] &= ~S_TXDONE;
410
+ }
411
+ if (value & S_RXRDY) {
412
+ s->regs[R_SPI_RIS] &= ~S_RXRDY;
413
+ }
414
+ if (value & S_RXCHOVRF) {
415
+ s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
416
+ }
417
+ break;
418
+
419
+ case R_SPI_MIS:
420
+ case R_SPI_STATUS:
421
+ case R_SPI_RIS:
422
+ qemu_log_mask(LOG_GUEST_ERROR,
423
+ "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
424
+ __func__, addr * 4);
425
+ break;
426
+
427
+ default:
428
+ if (addr < ARRAY_SIZE(s->regs)) {
429
+ s->regs[addr] = value;
430
+ } else {
431
+ qemu_log_mask(LOG_GUEST_ERROR,
432
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
433
+ addr * 4);
434
+ }
435
+ break;
436
+ }
437
+
438
+ spi_update_irq(s);
439
+}
440
+
441
+static const MemoryRegionOps spi_ops = {
442
+ .read = spi_read,
443
+ .write = spi_write,
444
+ .endianness = DEVICE_NATIVE_ENDIAN,
445
+ .valid = {
446
+ .min_access_size = 1,
447
+ .max_access_size = 4
448
+ }
449
+};
450
+
451
+static void mss_spi_realize(DeviceState *dev, Error **errp)
452
+{
453
+ MSSSpiState *s = MSS_SPI(dev);
454
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
455
+
456
+ s->spi = ssi_create_bus(dev, "spi");
457
+
458
+ sysbus_init_irq(sbd, &s->irq);
459
+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
460
+ sysbus_init_irq(sbd, &s->cs_line);
461
+
462
+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
463
+ TYPE_MSS_SPI, R_SPI_MAX * 4);
464
+ sysbus_init_mmio(sbd, &s->mmio);
465
+
466
+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
467
+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
468
+}
469
+
470
+static const VMStateDescription vmstate_mss_spi = {
471
+ .name = TYPE_MSS_SPI,
472
+ .version_id = 1,
473
+ .minimum_version_id = 1,
474
+ .fields = (VMStateField[]) {
475
+ VMSTATE_FIFO32(tx_fifo, MSSSpiState),
476
+ VMSTATE_FIFO32(rx_fifo, MSSSpiState),
477
+ VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
478
+ VMSTATE_END_OF_LIST()
479
+ }
480
+};
481
+
482
+static void mss_spi_class_init(ObjectClass *klass, void *data)
483
+{
484
+ DeviceClass *dc = DEVICE_CLASS(klass);
485
+
486
+ dc->realize = mss_spi_realize;
487
+ dc->reset = mss_spi_reset;
488
+ dc->vmsd = &vmstate_mss_spi;
489
+}
490
+
491
+static const TypeInfo mss_spi_info = {
492
+ .name = TYPE_MSS_SPI,
493
+ .parent = TYPE_SYS_BUS_DEVICE,
494
+ .instance_size = sizeof(MSSSpiState),
495
+ .class_init = mss_spi_class_init,
496
+};
497
+
498
+static void mss_spi_register_types(void)
499
+{
500
+ type_register_static(&mss_spi_info);
501
+}
502
+
503
+type_init(mss_spi_register_types)
504
--
194
--
505
2.7.4
195
2.20.1
506
196
507
197
diff view generated by jsdifflib
New patch
1
From: Rebecca Cran <rebecca@nuviainc.com>
1
2
3
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.
4
5
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210216224543.16142-3-rebecca@nuviainc.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu64.c | 5 +++++
11
1 file changed, 5 insertions(+)
12
13
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu64.c
16
+++ b/target/arm/cpu64.c
17
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
18
19
t = cpu->isar.id_aa64pfr1;
20
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
21
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
22
/*
23
* Begin with full support for MTE. This will be downgraded to MTE=0
24
* during realize if the board provides no tag memory, much like
25
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
26
u = FIELD_DP32(u, ID_PFR0, DIT, 1);
27
cpu->isar.id_pfr0 = u;
28
29
+ u = cpu->isar.id_pfr2;
30
+ u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
31
+ cpu->isar.id_pfr2 = u;
32
+
33
u = cpu->isar.id_mmfr3;
34
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
35
cpu->isar.id_mmfr3 = u;
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
New patch
1
From: Rebecca Cran <rebecca@nuviainc.com>
1
2
3
Enable FEAT_SSBS for the "max" 32-bit CPU.
4
5
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210216224543.16142-4-rebecca@nuviainc.com
8
[PMM: fix typo causing compilation failure]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.c | 4 ++++
12
1 file changed, 4 insertions(+)
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
19
t = cpu->isar.id_pfr0;
20
t = FIELD_DP32(t, ID_PFR0, DIT, 1);
21
cpu->isar.id_pfr0 = t;
22
+
23
+ t = cpu->isar.id_pfr2;
24
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
25
+ cpu->isar.id_pfr2 = t;
26
}
27
#endif
28
}
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Doug Evans <dje@google.com>
2
2
3
Smartfusion2 SoC has hardened Microcontroller subsystem
3
This is a 10/100 ethernet device that has several features.
4
and flash based FPGA fabric. This patch adds support for
4
Only the ones needed by the Linux driver have been implemented.
5
Microcontroller subsystem in the SoC.
5
See npcm7xx_emc.c for a list of unimplemented features.
6
6
7
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Reviewed-by: Hao Wu <wuhaotsh@google.com>
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Doug Evans <dje@google.com>
10
Message-id: 20170920201737.25723-5-f4bug@amsat.org
10
Message-id: 20210218212453.831406-2-dje@google.com
11
[PMD: drop cpu_model to directly use cpu type, check m3clk non null]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
12
---
14
hw/arm/Makefile.objs | 1 +
13
include/hw/net/npcm7xx_emc.h | 286 ++++++++++++
15
include/hw/arm/msf2-soc.h | 67 +++++++++++
14
hw/net/npcm7xx_emc.c | 857 +++++++++++++++++++++++++++++++++++
16
hw/arm/msf2-soc.c | 238 ++++++++++++++++++++++++++++++++++++++++
15
hw/net/meson.build | 1 +
17
default-configs/arm-softmmu.mak | 1 +
16
hw/net/trace-events | 17 +
18
4 files changed, 307 insertions(+)
17
4 files changed, 1161 insertions(+)
19
create mode 100644 include/hw/arm/msf2-soc.h
18
create mode 100644 include/hw/net/npcm7xx_emc.h
20
create mode 100644 hw/arm/msf2-soc.c
19
create mode 100644 hw/net/npcm7xx_emc.c
21
20
22
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
21
diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/Makefile.objs
25
+++ b/hw/arm/Makefile.objs
26
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
27
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
28
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
29
obj-$(CONFIG_MPS2) += mps2.o
30
+obj-$(CONFIG_MSF2) += msf2-soc.o
31
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
32
new file mode 100644
22
new file mode 100644
33
index XXXXXXX..XXXXXXX
23
index XXXXXXX..XXXXXXX
34
--- /dev/null
24
--- /dev/null
35
+++ b/include/hw/arm/msf2-soc.h
25
+++ b/include/hw/net/npcm7xx_emc.h
36
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@
37
+/*
27
+/*
38
+ * Microsemi Smartfusion2 SoC
28
+ * Nuvoton NPCM7xx EMC Module
39
+ *
29
+ *
40
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
30
+ * Copyright 2020 Google LLC
41
+ *
31
+ *
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
32
+ * This program is free software; you can redistribute it and/or modify it
43
+ * of this software and associated documentation files (the "Software"), to deal
33
+ * under the terms of the GNU General Public License as published by the
44
+ * in the Software without restriction, including without limitation the rights
34
+ * Free Software Foundation; either version 2 of the License, or
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
35
+ * (at your option) any later version.
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
36
+ *
49
+ * The above copyright notice and this permission notice shall be included in
37
+ * This program is distributed in the hope that it will be useful, but WITHOUT
50
+ * all copies or substantial portions of the Software.
38
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
51
+ *
39
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
40
+ * for more details.
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
41
+ */
60
+
42
+
61
+#ifndef HW_ARM_MSF2_SOC_H
43
+#ifndef NPCM7XX_EMC_H
62
+#define HW_ARM_MSF2_SOC_H
44
+#define NPCM7XX_EMC_H
63
+
45
+
64
+#include "hw/arm/armv7m.h"
46
+#include "hw/irq.h"
65
+#include "hw/timer/mss-timer.h"
47
+#include "hw/sysbus.h"
66
+#include "hw/misc/msf2-sysreg.h"
48
+#include "net/net.h"
67
+#include "hw/ssi/mss-spi.h"
49
+
68
+
50
+/* 32-bit register indices. */
69
+#define TYPE_MSF2_SOC "msf2-soc"
51
+enum NPCM7xxPWMRegister {
70
+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
52
+ /* Control registers. */
71
+
53
+ REG_CAMCMR,
72
+#define MSF2_NUM_SPIS 2
54
+ REG_CAMEN,
73
+#define MSF2_NUM_UARTS 2
55
+
74
+
56
+ /* There are 16 CAMn[ML] registers. */
75
+/*
57
+ REG_CAMM_BASE,
76
+ * System timer consists of two programmable 32-bit
58
+ REG_CAML_BASE,
77
+ * decrementing counters that generate individual interrupts to
59
+ REG_CAMML_LAST = 0x21,
78
+ * the Cortex-M3 processor
60
+
79
+ */
61
+ REG_TXDLSA = 0x22,
80
+#define MSF2_NUM_TIMERS 2
62
+ REG_RXDLSA,
81
+
63
+ REG_MCMDR,
82
+typedef struct MSF2State {
64
+ REG_MIID,
65
+ REG_MIIDA,
66
+ REG_FFTCR,
67
+ REG_TSDR,
68
+ REG_RSDR,
69
+ REG_DMARFC,
70
+ REG_MIEN,
71
+
72
+ /* Status registers. */
73
+ REG_MISTA,
74
+ REG_MGSTA,
75
+ REG_MPCNT,
76
+ REG_MRPC,
77
+ REG_MRPCC,
78
+ REG_MREPC,
79
+ REG_DMARFS,
80
+ REG_CTXDSA,
81
+ REG_CTXBSA,
82
+ REG_CRXDSA,
83
+ REG_CRXBSA,
84
+
85
+ NPCM7XX_NUM_EMC_REGS,
86
+};
87
+
88
+/* REG_CAMCMR fields */
89
+/* Enable CAM Compare */
90
+#define REG_CAMCMR_ECMP (1 << 4)
91
+/* Complement CAM Compare */
92
+#define REG_CAMCMR_CCAM (1 << 3)
93
+/* Accept Broadcast Packet */
94
+#define REG_CAMCMR_ABP (1 << 2)
95
+/* Accept Multicast Packet */
96
+#define REG_CAMCMR_AMP (1 << 1)
97
+/* Accept Unicast Packet */
98
+#define REG_CAMCMR_AUP (1 << 0)
99
+
100
+/* REG_MCMDR fields */
101
+/* Software Reset */
102
+#define REG_MCMDR_SWR (1 << 24)
103
+/* Internal Loopback Select */
104
+#define REG_MCMDR_LBK (1 << 21)
105
+/* Operation Mode Select */
106
+#define REG_MCMDR_OPMOD (1 << 20)
107
+/* Enable MDC Clock Generation */
108
+#define REG_MCMDR_ENMDC (1 << 19)
109
+/* Full-Duplex Mode Select */
110
+#define REG_MCMDR_FDUP (1 << 18)
111
+/* Enable SQE Checking */
112
+#define REG_MCMDR_ENSEQ (1 << 17)
113
+/* Send PAUSE Frame */
114
+#define REG_MCMDR_SDPZ (1 << 16)
115
+/* No Defer */
116
+#define REG_MCMDR_NDEF (1 << 9)
117
+/* Frame Transmission On */
118
+#define REG_MCMDR_TXON (1 << 8)
119
+/* Strip CRC Checksum */
120
+#define REG_MCMDR_SPCRC (1 << 5)
121
+/* Accept CRC Error Packet */
122
+#define REG_MCMDR_AEP (1 << 4)
123
+/* Accept Control Packet */
124
+#define REG_MCMDR_ACP (1 << 3)
125
+/* Accept Runt Packet */
126
+#define REG_MCMDR_ARP (1 << 2)
127
+/* Accept Long Packet */
128
+#define REG_MCMDR_ALP (1 << 1)
129
+/* Frame Reception On */
130
+#define REG_MCMDR_RXON (1 << 0)
131
+
132
+/* REG_MIEN fields */
133
+/* Enable Transmit Descriptor Unavailable Interrupt */
134
+#define REG_MIEN_ENTDU (1 << 23)
135
+/* Enable Transmit Completion Interrupt */
136
+#define REG_MIEN_ENTXCP (1 << 18)
137
+/* Enable Transmit Interrupt */
138
+#define REG_MIEN_ENTXINTR (1 << 16)
139
+/* Enable Receive Descriptor Unavailable Interrupt */
140
+#define REG_MIEN_ENRDU (1 << 10)
141
+/* Enable Receive Good Interrupt */
142
+#define REG_MIEN_ENRXGD (1 << 4)
143
+/* Enable Receive Interrupt */
144
+#define REG_MIEN_ENRXINTR (1 << 0)
145
+
146
+/* REG_MISTA fields */
147
+/* TODO: Add error fields and support simulated errors? */
148
+/* Transmit Bus Error Interrupt */
149
+#define REG_MISTA_TXBERR (1 << 24)
150
+/* Transmit Descriptor Unavailable Interrupt */
151
+#define REG_MISTA_TDU (1 << 23)
152
+/* Transmit Completion Interrupt */
153
+#define REG_MISTA_TXCP (1 << 18)
154
+/* Transmit Interrupt */
155
+#define REG_MISTA_TXINTR (1 << 16)
156
+/* Receive Bus Error Interrupt */
157
+#define REG_MISTA_RXBERR (1 << 11)
158
+/* Receive Descriptor Unavailable Interrupt */
159
+#define REG_MISTA_RDU (1 << 10)
160
+/* DMA Early Notification Interrupt */
161
+#define REG_MISTA_DENI (1 << 9)
162
+/* Maximum Frame Length Interrupt */
163
+#define REG_MISTA_DFOI (1 << 8)
164
+/* Receive Good Interrupt */
165
+#define REG_MISTA_RXGD (1 << 4)
166
+/* Packet Too Long Interrupt */
167
+#define REG_MISTA_PTLE (1 << 3)
168
+/* Receive Interrupt */
169
+#define REG_MISTA_RXINTR (1 << 0)
170
+
171
+/* REG_MGSTA fields */
172
+/* Transmission Halted */
173
+#define REG_MGSTA_TXHA (1 << 11)
174
+/* Receive Halted */
175
+#define REG_MGSTA_RXHA (1 << 11)
176
+
177
+/* REG_DMARFC fields */
178
+/* Maximum Receive Frame Length */
179
+#define REG_DMARFC_RXMS(word) extract32((word), 0, 16)
180
+
181
+/* REG MIIDA fields */
182
+/* Busy Bit */
183
+#define REG_MIIDA_BUSY (1 << 17)
184
+
185
+/* Transmit and receive descriptors */
186
+typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc;
187
+typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc;
188
+
189
+struct NPCM7xxEMCTxDesc {
190
+ uint32_t flags;
191
+ uint32_t txbsa;
192
+ uint32_t status_and_length;
193
+ uint32_t ntxdsa;
194
+};
195
+
196
+struct NPCM7xxEMCRxDesc {
197
+ uint32_t status_and_length;
198
+ uint32_t rxbsa;
199
+ uint32_t reserved;
200
+ uint32_t nrxdsa;
201
+};
202
+
203
+/* NPCM7xxEMCTxDesc.flags values */
204
+/* Owner: 0 = cpu, 1 = emc */
205
+#define TX_DESC_FLAG_OWNER_MASK (1 << 31)
206
+/* Transmit interrupt enable */
207
+#define TX_DESC_FLAG_INTEN (1 << 2)
208
+/* CRC append */
209
+#define TX_DESC_FLAG_CRCAPP (1 << 1)
210
+/* Padding enable */
211
+#define TX_DESC_FLAG_PADEN (1 << 0)
212
+
213
+/* NPCM7xxEMCTxDesc.status_and_length values */
214
+/* Collision count */
215
+#define TX_DESC_STATUS_CCNT_SHIFT 28
216
+#define TX_DESC_STATUS_CCNT_BITSIZE 4
217
+/* SQE error */
218
+#define TX_DESC_STATUS_SQE (1 << 26)
219
+/* Transmission paused */
220
+#define TX_DESC_STATUS_PAU (1 << 25)
221
+/* P transmission halted */
222
+#define TX_DESC_STATUS_TXHA (1 << 24)
223
+/* Late collision */
224
+#define TX_DESC_STATUS_LC (1 << 23)
225
+/* Transmission abort */
226
+#define TX_DESC_STATUS_TXABT (1 << 22)
227
+/* No carrier sense */
228
+#define TX_DESC_STATUS_NCS (1 << 21)
229
+/* Defer exceed */
230
+#define TX_DESC_STATUS_EXDEF (1 << 20)
231
+/* Transmission complete */
232
+#define TX_DESC_STATUS_TXCP (1 << 19)
233
+/* Transmission deferred */
234
+#define TX_DESC_STATUS_DEF (1 << 17)
235
+/* Transmit interrupt */
236
+#define TX_DESC_STATUS_TXINTR (1 << 16)
237
+
238
+#define TX_DESC_PKT_LEN(word) extract32((word), 0, 16)
239
+
240
+/* Transmit buffer start address */
241
+#define TX_DESC_TXBSA(word) ((uint32_t) (word) & ~3u)
242
+
243
+/* Next transmit descriptor start address */
244
+#define TX_DESC_NTXDSA(word) ((uint32_t) (word) & ~3u)
245
+
246
+/* NPCM7xxEMCRxDesc.status_and_length values */
247
+/* Owner: 0b00 = cpu, 0b01 = undefined, 0b10 = emc, 0b11 = undefined */
248
+#define RX_DESC_STATUS_OWNER_SHIFT 30
249
+#define RX_DESC_STATUS_OWNER_BITSIZE 2
250
+#define RX_DESC_STATUS_OWNER_MASK (3 << RX_DESC_STATUS_OWNER_SHIFT)
251
+/* Runt packet */
252
+#define RX_DESC_STATUS_RP (1 << 22)
253
+/* Alignment error */
254
+#define RX_DESC_STATUS_ALIE (1 << 21)
255
+/* Frame reception complete */
256
+#define RX_DESC_STATUS_RXGD (1 << 20)
257
+/* Packet too long */
258
+#define RX_DESC_STATUS_PTLE (1 << 19)
259
+/* CRC error */
260
+#define RX_DESC_STATUS_CRCE (1 << 17)
261
+/* Receive interrupt */
262
+#define RX_DESC_STATUS_RXINTR (1 << 16)
263
+
264
+#define RX_DESC_PKT_LEN(word) extract32((word), 0, 16)
265
+
266
+/* Receive buffer start address */
267
+#define RX_DESC_RXBSA(word) ((uint32_t) (word) & ~3u)
268
+
269
+/* Next receive descriptor start address */
270
+#define RX_DESC_NRXDSA(word) ((uint32_t) (word) & ~3u)
271
+
272
+/* Minimum packet length, when TX_DESC_FLAG_PADEN is set. */
273
+#define MIN_PACKET_LENGTH 64
274
+
275
+struct NPCM7xxEMCState {
83
+ /*< private >*/
276
+ /*< private >*/
84
+ SysBusDevice parent_obj;
277
+ SysBusDevice parent;
85
+ /*< public >*/
278
+ /*< public >*/
86
+
279
+
87
+ ARMv7MState armv7m;
280
+ MemoryRegion iomem;
88
+
281
+
89
+ char *cpu_type;
282
+ qemu_irq tx_irq;
90
+ char *part_name;
283
+ qemu_irq rx_irq;
91
+ uint64_t envm_size;
284
+
92
+ uint64_t esram_size;
285
+ NICState *nic;
93
+
286
+ NICConf conf;
94
+ uint32_t m3clk;
287
+
95
+ uint8_t apb0div;
288
+ /* 0 or 1, for log messages */
96
+ uint8_t apb1div;
289
+ uint8_t emc_num;
97
+
290
+
98
+ MSF2SysregState sysreg;
291
+ uint32_t regs[NPCM7XX_NUM_EMC_REGS];
99
+ MSSTimerState timer;
292
+
100
+ MSSSpiState spi[MSF2_NUM_SPIS];
293
+ /*
101
+} MSF2State;
294
+ * tx is active. Set to true by TSDR and then switches off when out of
102
+
295
+ * descriptors. If the TXON bit in REG_MCMDR is off then this is off.
103
+#endif
296
+ */
104
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
297
+ bool tx_active;
298
+
299
+ /*
300
+ * rx is active. Set to true by RSDR and then switches off when out of
301
+ * descriptors. If the RXON bit in REG_MCMDR is off then this is off.
302
+ */
303
+ bool rx_active;
304
+};
305
+
306
+typedef struct NPCM7xxEMCState NPCM7xxEMCState;
307
+
308
+#define TYPE_NPCM7XX_EMC "npcm7xx-emc"
309
+#define NPCM7XX_EMC(obj) \
310
+ OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC)
311
+
312
+#endif /* NPCM7XX_EMC_H */
313
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
105
new file mode 100644
314
new file mode 100644
106
index XXXXXXX..XXXXXXX
315
index XXXXXXX..XXXXXXX
107
--- /dev/null
316
--- /dev/null
108
+++ b/hw/arm/msf2-soc.c
317
+++ b/hw/net/npcm7xx_emc.c
109
@@ -XXX,XX +XXX,XX @@
318
@@ -XXX,XX +XXX,XX @@
110
+/*
319
+/*
111
+ * SmartFusion2 SoC emulation.
320
+ * Nuvoton NPCM7xx EMC Module
112
+ *
321
+ *
113
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
322
+ * Copyright 2020 Google LLC
114
+ *
323
+ *
115
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
324
+ * This program is free software; you can redistribute it and/or modify it
116
+ * of this software and associated documentation files (the "Software"), to deal
325
+ * under the terms of the GNU General Public License as published by the
117
+ * in the Software without restriction, including without limitation the rights
326
+ * Free Software Foundation; either version 2 of the License, or
118
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
327
+ * (at your option) any later version.
119
+ * copies of the Software, and to permit persons to whom the Software is
120
+ * furnished to do so, subject to the following conditions:
121
+ *
328
+ *
122
+ * The above copyright notice and this permission notice shall be included in
329
+ * This program is distributed in the hope that it will be useful, but WITHOUT
123
+ * all copies or substantial portions of the Software.
330
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
331
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
332
+ * for more details.
124
+ *
333
+ *
125
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
334
+ * Unsupported/unimplemented features:
126
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
335
+ * - MCMDR.FDUP (full duplex) is ignored, half duplex is not supported
127
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
336
+ * - Only CAM0 is supported, CAM[1-15] are not
128
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
337
+ * - writes to CAMEN.[1-15] are ignored, these bits always read as zeroes
129
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
338
+ * - MII is not implemented, MIIDA.BUSY and MIID always return zero
130
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
339
+ * - MCMDR.LBK is not implemented
131
+ * THE SOFTWARE.
340
+ * - MCMDR.{OPMOD,ENSQE,AEP,ARP} are not supported
341
+ * - H/W FIFOs are not supported, MCMDR.FFTCR is ignored
342
+ * - MGSTA.SQE is not supported
343
+ * - pause and control frames are not implemented
344
+ * - MGSTA.CCNT is not supported
345
+ * - MPCNT, DMARFS are not implemented
132
+ */
346
+ */
133
+
347
+
134
+#include "qemu/osdep.h"
348
+#include "qemu/osdep.h"
135
+#include "qapi/error.h"
349
+
350
+/* For crc32 */
351
+#include <zlib.h>
352
+
136
+#include "qemu-common.h"
353
+#include "qemu-common.h"
137
+#include "hw/arm/arm.h"
354
+#include "hw/irq.h"
138
+#include "exec/address-spaces.h"
355
+#include "hw/qdev-clock.h"
139
+#include "hw/char/serial.h"
356
+#include "hw/qdev-properties.h"
140
+#include "hw/boards.h"
357
+#include "hw/net/npcm7xx_emc.h"
141
+#include "sysemu/block-backend.h"
358
+#include "net/eth.h"
142
+#include "qemu/cutils.h"
359
+#include "migration/vmstate.h"
143
+#include "hw/arm/msf2-soc.h"
360
+#include "qemu/bitops.h"
144
+#include "hw/misc/unimp.h"
361
+#include "qemu/error-report.h"
145
+
362
+#include "qemu/log.h"
146
+#define MSF2_TIMER_BASE 0x40004000
363
+#include "qemu/module.h"
147
+#define MSF2_SYSREG_BASE 0x40038000
364
+#include "qemu/units.h"
148
+
365
+#include "sysemu/dma.h"
149
+#define ENVM_BASE_ADDRESS 0x60000000
366
+#include "trace.h"
150
+
367
+
151
+#define SRAM_BASE_ADDRESS 0x20000000
368
+#define CRC_LENGTH 4
152
+
153
+#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
154
+
369
+
155
+/*
370
+/*
156
+ * eSRAM max size is 80k without SECDED(Single error correction and
371
+ * The maximum size of a (layer 2) ethernet frame as defined by 802.3.
157
+ * dual error detection) feature and 64k with SECDED.
372
+ * 1518 = 6(dest macaddr) + 6(src macaddr) + 2(proto) + 4(crc) + 1500(payload)
158
+ * We do not support SECDED now.
373
+ * This does not include an additional 4 for the vlan field (802.1q).
159
+ */
374
+ */
160
+#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
375
+#define MAX_ETH_FRAME_SIZE 1518
161
+
376
+
162
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
377
+static const char *emc_reg_name(int regno)
163
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
378
+{
164
+
379
+#define REG(name) case REG_ ## name: return #name;
165
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
380
+ switch (regno) {
166
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
381
+ REG(CAMCMR)
167
+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
382
+ REG(CAMEN)
168
+
383
+ REG(TXDLSA)
169
+static void m2sxxx_soc_initfn(Object *obj)
384
+ REG(RXDLSA)
170
+{
385
+ REG(MCMDR)
171
+ MSF2State *s = MSF2_SOC(obj);
386
+ REG(MIID)
172
+ int i;
387
+ REG(MIIDA)
173
+
388
+ REG(FFTCR)
174
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
389
+ REG(TSDR)
175
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
390
+ REG(RSDR)
176
+
391
+ REG(DMARFC)
177
+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
392
+ REG(MIEN)
178
+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
393
+ REG(MISTA)
179
+
394
+ REG(MGSTA)
180
+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
395
+ REG(MPCNT)
181
+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
396
+ REG(MRPC)
182
+
397
+ REG(MRPCC)
183
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
398
+ REG(MREPC)
184
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
399
+ REG(DMARFS)
185
+ TYPE_MSS_SPI);
400
+ REG(CTXDSA)
186
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
401
+ REG(CTXBSA)
187
+ }
402
+ REG(CRXDSA)
188
+}
403
+ REG(CRXBSA)
189
+
404
+ case REG_CAMM_BASE + 0: return "CAM0M";
190
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
405
+ case REG_CAML_BASE + 0: return "CAM0L";
191
+{
406
+ case REG_CAMM_BASE + 2 ... REG_CAMML_LAST:
192
+ MSF2State *s = MSF2_SOC(dev_soc);
407
+ /* Only CAM0 is supported, fold the others into something simple. */
193
+ DeviceState *dev, *armv7m;
408
+ if (regno & 1) {
194
+ SysBusDevice *busdev;
409
+ return "CAM<n>L";
195
+ Error *err = NULL;
410
+ } else {
196
+ int i;
411
+ return "CAM<n>M";
197
+
412
+ }
198
+ MemoryRegion *system_memory = get_system_memory();
413
+ default: return "UNKNOWN";
199
+ MemoryRegion *nvm = g_new(MemoryRegion, 1);
414
+ }
200
+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
415
+#undef REG
201
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
416
+}
202
+
417
+
203
+ memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
418
+static void emc_reset(NPCM7xxEMCState *emc)
204
+ &error_fatal);
419
+{
420
+ trace_npcm7xx_emc_reset(emc->emc_num);
421
+
422
+ memset(&emc->regs[0], 0, sizeof(emc->regs));
423
+
424
+ /* These regs have non-zero reset values. */
425
+ emc->regs[REG_TXDLSA] = 0xfffffffc;
426
+ emc->regs[REG_RXDLSA] = 0xfffffffc;
427
+ emc->regs[REG_MIIDA] = 0x00900000;
428
+ emc->regs[REG_FFTCR] = 0x0101;
429
+ emc->regs[REG_DMARFC] = 0x0800;
430
+ emc->regs[REG_MPCNT] = 0x7fff;
431
+
432
+ emc->tx_active = false;
433
+ emc->rx_active = false;
434
+}
435
+
436
+static void npcm7xx_emc_reset(DeviceState *dev)
437
+{
438
+ NPCM7xxEMCState *emc = NPCM7XX_EMC(dev);
439
+ emc_reset(emc);
440
+}
441
+
442
+static void emc_soft_reset(NPCM7xxEMCState *emc)
443
+{
205
+ /*
444
+ /*
206
+ * On power-on, the eNVM region 0x60000000 is automatically
445
+ * The docs say at least MCMDR.{LBK,OPMOD} bits are not changed during a
207
+ * remapped to the Cortex-M3 processor executable region
446
+ * soft reset, but does not go into further detail. For now, KISS.
208
+ * start address (0x0). We do not support remapping other eNVM,
209
+ * eSRAM and DDR regions by guest(via Sysreg) currently.
210
+ */
447
+ */
211
+ memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
448
+ uint32_t mcmdr = emc->regs[REG_MCMDR];
212
+ nvm, 0, s->envm_size);
449
+ emc_reset(emc);
213
+
450
+ emc->regs[REG_MCMDR] = mcmdr & (REG_MCMDR_LBK | REG_MCMDR_OPMOD);
214
+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
451
+
215
+ memory_region_add_subregion(system_memory, 0, nvm_alias);
452
+ qemu_set_irq(emc->tx_irq, 0);
216
+
453
+ qemu_set_irq(emc->rx_irq, 0);
217
+ memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
454
+}
218
+ &error_fatal);
455
+
219
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
456
+static void emc_set_link(NetClientState *nc)
220
+
457
+{
221
+ armv7m = DEVICE(&s->armv7m);
458
+ /* Nothing to do yet. */
222
+ qdev_prop_set_uint32(armv7m, "num-irq", 81);
459
+}
223
+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
460
+
224
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
461
+/* MISTA.TXINTR is the union of the individual bits with their enables. */
225
+ "memory", &error_abort);
462
+static void emc_update_mista_txintr(NPCM7xxEMCState *emc)
226
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
463
+{
227
+ if (err != NULL) {
464
+ /* Only look at the bits we support. */
228
+ error_propagate(errp, err);
465
+ uint32_t mask = (REG_MISTA_TXBERR |
466
+ REG_MISTA_TDU |
467
+ REG_MISTA_TXCP);
468
+ if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) {
469
+ emc->regs[REG_MISTA] |= REG_MISTA_TXINTR;
470
+ } else {
471
+ emc->regs[REG_MISTA] &= ~REG_MISTA_TXINTR;
472
+ }
473
+}
474
+
475
+/* MISTA.RXINTR is the union of the individual bits with their enables. */
476
+static void emc_update_mista_rxintr(NPCM7xxEMCState *emc)
477
+{
478
+ /* Only look at the bits we support. */
479
+ uint32_t mask = (REG_MISTA_RXBERR |
480
+ REG_MISTA_RDU |
481
+ REG_MISTA_RXGD);
482
+ if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) {
483
+ emc->regs[REG_MISTA] |= REG_MISTA_RXINTR;
484
+ } else {
485
+ emc->regs[REG_MISTA] &= ~REG_MISTA_RXINTR;
486
+ }
487
+}
488
+
489
+/* N.B. emc_update_mista_txintr must have already been called. */
490
+static void emc_update_tx_irq(NPCM7xxEMCState *emc)
491
+{
492
+ int level = !!(emc->regs[REG_MISTA] &
493
+ emc->regs[REG_MIEN] &
494
+ REG_MISTA_TXINTR);
495
+ trace_npcm7xx_emc_update_tx_irq(level);
496
+ qemu_set_irq(emc->tx_irq, level);
497
+}
498
+
499
+/* N.B. emc_update_mista_rxintr must have already been called. */
500
+static void emc_update_rx_irq(NPCM7xxEMCState *emc)
501
+{
502
+ int level = !!(emc->regs[REG_MISTA] &
503
+ emc->regs[REG_MIEN] &
504
+ REG_MISTA_RXINTR);
505
+ trace_npcm7xx_emc_update_rx_irq(level);
506
+ qemu_set_irq(emc->rx_irq, level);
507
+}
508
+
509
+/* Update IRQ states due to changes in MIEN,MISTA. */
510
+static void emc_update_irq_from_reg_change(NPCM7xxEMCState *emc)
511
+{
512
+ emc_update_mista_txintr(emc);
513
+ emc_update_tx_irq(emc);
514
+
515
+ emc_update_mista_rxintr(emc);
516
+ emc_update_rx_irq(emc);
517
+}
518
+
519
+static int emc_read_tx_desc(dma_addr_t addr, NPCM7xxEMCTxDesc *desc)
520
+{
521
+ if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) {
522
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%"
523
+ HWADDR_PRIx "\n", __func__, addr);
524
+ return -1;
525
+ }
526
+ desc->flags = le32_to_cpu(desc->flags);
527
+ desc->txbsa = le32_to_cpu(desc->txbsa);
528
+ desc->status_and_length = le32_to_cpu(desc->status_and_length);
529
+ desc->ntxdsa = le32_to_cpu(desc->ntxdsa);
530
+ return 0;
531
+}
532
+
533
+static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *desc, dma_addr_t addr)
534
+{
535
+ NPCM7xxEMCTxDesc le_desc;
536
+
537
+ le_desc.flags = cpu_to_le32(desc->flags);
538
+ le_desc.txbsa = cpu_to_le32(desc->txbsa);
539
+ le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
540
+ le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa);
541
+ if (dma_memory_write(&address_space_memory, addr, &le_desc,
542
+ sizeof(le_desc))) {
543
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%"
544
+ HWADDR_PRIx "\n", __func__, addr);
545
+ return -1;
546
+ }
547
+ return 0;
548
+}
549
+
550
+static int emc_read_rx_desc(dma_addr_t addr, NPCM7xxEMCRxDesc *desc)
551
+{
552
+ if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) {
553
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%"
554
+ HWADDR_PRIx "\n", __func__, addr);
555
+ return -1;
556
+ }
557
+ desc->status_and_length = le32_to_cpu(desc->status_and_length);
558
+ desc->rxbsa = le32_to_cpu(desc->rxbsa);
559
+ desc->reserved = le32_to_cpu(desc->reserved);
560
+ desc->nrxdsa = le32_to_cpu(desc->nrxdsa);
561
+ return 0;
562
+}
563
+
564
+static int emc_write_rx_desc(const NPCM7xxEMCRxDesc *desc, dma_addr_t addr)
565
+{
566
+ NPCM7xxEMCRxDesc le_desc;
567
+
568
+ le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
569
+ le_desc.rxbsa = cpu_to_le32(desc->rxbsa);
570
+ le_desc.reserved = cpu_to_le32(desc->reserved);
571
+ le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa);
572
+ if (dma_memory_write(&address_space_memory, addr, &le_desc,
573
+ sizeof(le_desc))) {
574
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%"
575
+ HWADDR_PRIx "\n", __func__, addr);
576
+ return -1;
577
+ }
578
+ return 0;
579
+}
580
+
581
+static void emc_set_mista(NPCM7xxEMCState *emc, uint32_t flags)
582
+{
583
+ trace_npcm7xx_emc_set_mista(flags);
584
+ emc->regs[REG_MISTA] |= flags;
585
+ if (extract32(flags, 16, 16)) {
586
+ emc_update_mista_txintr(emc);
587
+ }
588
+ if (extract32(flags, 0, 16)) {
589
+ emc_update_mista_rxintr(emc);
590
+ }
591
+}
592
+
593
+static void emc_halt_tx(NPCM7xxEMCState *emc, uint32_t mista_flag)
594
+{
595
+ emc->tx_active = false;
596
+ emc_set_mista(emc, mista_flag);
597
+}
598
+
599
+static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag)
600
+{
601
+ emc->rx_active = false;
602
+ emc_set_mista(emc, mista_flag);
603
+}
604
+
605
+static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc,
606
+ const NPCM7xxEMCTxDesc *tx_desc,
607
+ uint32_t desc_addr)
608
+{
609
+ /* Update the current descriptor, if only to reset the owner flag. */
610
+ if (emc_write_tx_desc(tx_desc, desc_addr)) {
611
+ /*
612
+ * We just read it so this shouldn't generally happen.
613
+ * Error already reported.
614
+ */
615
+ emc_set_mista(emc, REG_MISTA_TXBERR);
616
+ }
617
+ emc->regs[REG_CTXDSA] = TX_DESC_NTXDSA(tx_desc->ntxdsa);
618
+}
619
+
620
+static void emc_set_next_rx_descriptor(NPCM7xxEMCState *emc,
621
+ const NPCM7xxEMCRxDesc *rx_desc,
622
+ uint32_t desc_addr)
623
+{
624
+ /* Update the current descriptor, if only to reset the owner flag. */
625
+ if (emc_write_rx_desc(rx_desc, desc_addr)) {
626
+ /*
627
+ * We just read it so this shouldn't generally happen.
628
+ * Error already reported.
629
+ */
630
+ emc_set_mista(emc, REG_MISTA_RXBERR);
631
+ }
632
+ emc->regs[REG_CRXDSA] = RX_DESC_NRXDSA(rx_desc->nrxdsa);
633
+}
634
+
635
+static void emc_try_send_next_packet(NPCM7xxEMCState *emc)
636
+{
637
+ /* Working buffer for sending out packets. Most packets fit in this. */
638
+#define TX_BUFFER_SIZE 2048
639
+ uint8_t tx_send_buffer[TX_BUFFER_SIZE];
640
+ uint32_t desc_addr = TX_DESC_NTXDSA(emc->regs[REG_CTXDSA]);
641
+ NPCM7xxEMCTxDesc tx_desc;
642
+ uint32_t next_buf_addr, length;
643
+ uint8_t *buf;
644
+ g_autofree uint8_t *malloced_buf = NULL;
645
+
646
+ if (emc_read_tx_desc(desc_addr, &tx_desc)) {
647
+ /* Error reading descriptor, already reported. */
648
+ emc_halt_tx(emc, REG_MISTA_TXBERR);
649
+ emc_update_tx_irq(emc);
229
+ return;
650
+ return;
230
+ }
651
+ }
231
+
652
+
232
+ if (!s->m3clk) {
653
+ /* Nothing we can do if we don't own the descriptor. */
233
+ error_setg(errp, "Invalid m3clk value");
654
+ if (!(tx_desc.flags & TX_DESC_FLAG_OWNER_MASK)) {
234
+ error_append_hint(errp, "m3clk can not be zero\n");
655
+ trace_npcm7xx_emc_cpu_owned_desc(desc_addr);
656
+ emc_halt_tx(emc, REG_MISTA_TDU);
657
+ emc_update_tx_irq(emc);
235
+ return;
658
+ return;
236
+ }
659
+ }
237
+ system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
660
+
238
+
661
+ /* Give the descriptor back regardless of what happens. */
239
+ for (i = 0; i < MSF2_NUM_UARTS; i++) {
662
+ tx_desc.flags &= ~TX_DESC_FLAG_OWNER_MASK;
240
+ if (serial_hds[i]) {
663
+ tx_desc.status_and_length &= 0xffff;
241
+ serial_mm_init(get_system_memory(), uart_addr[i], 2,
664
+
242
+ qdev_get_gpio_in(armv7m, uart_irq[i]),
665
+ /*
243
+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
666
+ * Despite the h/w documentation saying the tx buffer is word aligned,
244
+ }
667
+ * the linux driver does not word align the buffer. There is value in not
245
+ }
668
+ * aligning the buffer: See the description of NET_IP_ALIGN in linux
246
+
669
+ * kernel sources.
247
+ dev = DEVICE(&s->timer);
670
+ */
248
+ /* APB0 clock is the timer input clock */
671
+ next_buf_addr = tx_desc.txbsa;
249
+ qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
672
+ emc->regs[REG_CTXBSA] = next_buf_addr;
250
+ object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
673
+ length = TX_DESC_PKT_LEN(tx_desc.status_and_length);
251
+ if (err != NULL) {
674
+ buf = &tx_send_buffer[0];
252
+ error_propagate(errp, err);
675
+
676
+ if (length > sizeof(tx_send_buffer)) {
677
+ malloced_buf = g_malloc(length);
678
+ buf = malloced_buf;
679
+ }
680
+
681
+ if (dma_memory_read(&address_space_memory, next_buf_addr, buf, length)) {
682
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x%x\n",
683
+ __func__, next_buf_addr);
684
+ emc_set_mista(emc, REG_MISTA_TXBERR);
685
+ emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr);
686
+ emc_update_tx_irq(emc);
687
+ trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]);
253
+ return;
688
+ return;
254
+ }
689
+ }
255
+ busdev = SYS_BUS_DEVICE(dev);
690
+
256
+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
691
+ if ((tx_desc.flags & TX_DESC_FLAG_PADEN) && (length < MIN_PACKET_LENGTH)) {
257
+ sysbus_connect_irq(busdev, 0,
692
+ memset(buf + length, 0, MIN_PACKET_LENGTH - length);
258
+ qdev_get_gpio_in(armv7m, timer_irq[0]));
693
+ length = MIN_PACKET_LENGTH;
259
+ sysbus_connect_irq(busdev, 1,
694
+ }
260
+ qdev_get_gpio_in(armv7m, timer_irq[1]));
695
+
261
+
696
+ /* N.B. emc_receive can get called here. */
262
+ dev = DEVICE(&s->sysreg);
697
+ qemu_send_packet(qemu_get_queue(emc->nic), buf, length);
263
+ qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
698
+ trace_npcm7xx_emc_sent_packet(length);
264
+ qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
699
+
265
+ object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
700
+ tx_desc.status_and_length |= TX_DESC_STATUS_TXCP;
266
+ if (err != NULL) {
701
+ if (tx_desc.flags & TX_DESC_FLAG_INTEN) {
267
+ error_propagate(errp, err);
702
+ emc_set_mista(emc, REG_MISTA_TXCP);
703
+ }
704
+ if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_TXINTR) {
705
+ tx_desc.status_and_length |= TX_DESC_STATUS_TXINTR;
706
+ }
707
+
708
+ emc_set_next_tx_descriptor(emc, &tx_desc, desc_addr);
709
+ emc_update_tx_irq(emc);
710
+ trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]);
711
+}
712
+
713
+static bool emc_can_receive(NetClientState *nc)
714
+{
715
+ NPCM7xxEMCState *emc = NPCM7XX_EMC(qemu_get_nic_opaque(nc));
716
+
717
+ bool can_receive = emc->rx_active;
718
+ trace_npcm7xx_emc_can_receive(can_receive);
719
+ return can_receive;
720
+}
721
+
722
+/* If result is false then *fail_reason contains the reason. */
723
+static bool emc_receive_filter1(NPCM7xxEMCState *emc, const uint8_t *buf,
724
+ size_t len, const char **fail_reason)
725
+{
726
+ eth_pkt_types_e pkt_type = get_eth_packet_type(PKT_GET_ETH_HDR(buf));
727
+
728
+ switch (pkt_type) {
729
+ case ETH_PKT_BCAST:
730
+ if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) {
731
+ return true;
732
+ } else {
733
+ *fail_reason = "Broadcast packet disabled";
734
+ return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_ABP);
735
+ }
736
+ case ETH_PKT_MCAST:
737
+ if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) {
738
+ return true;
739
+ } else {
740
+ *fail_reason = "Multicast packet disabled";
741
+ return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_AMP);
742
+ }
743
+ case ETH_PKT_UCAST: {
744
+ bool matches;
745
+ if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) {
746
+ return true;
747
+ }
748
+ matches = ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) &&
749
+ /* We only support one CAM register, CAM0. */
750
+ (emc->regs[REG_CAMEN] & (1 << 0)) &&
751
+ memcmp(buf, emc->conf.macaddr.a, ETH_ALEN) == 0);
752
+ if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) {
753
+ *fail_reason = "MACADDR matched, comparison complemented";
754
+ return !matches;
755
+ } else {
756
+ *fail_reason = "MACADDR didn't match";
757
+ return matches;
758
+ }
759
+ }
760
+ default:
761
+ g_assert_not_reached();
762
+ }
763
+}
764
+
765
+static bool emc_receive_filter(NPCM7xxEMCState *emc, const uint8_t *buf,
766
+ size_t len)
767
+{
768
+ const char *fail_reason = NULL;
769
+ bool ok = emc_receive_filter1(emc, buf, len, &fail_reason);
770
+ if (!ok) {
771
+ trace_npcm7xx_emc_packet_filtered_out(fail_reason);
772
+ }
773
+ return ok;
774
+}
775
+
776
+static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1)
777
+{
778
+ NPCM7xxEMCState *emc = NPCM7XX_EMC(qemu_get_nic_opaque(nc));
779
+ const uint32_t len = len1;
780
+ size_t max_frame_len;
781
+ bool long_frame;
782
+ uint32_t desc_addr;
783
+ NPCM7xxEMCRxDesc rx_desc;
784
+ uint32_t crc;
785
+ uint8_t *crc_ptr;
786
+ uint32_t buf_addr;
787
+
788
+ trace_npcm7xx_emc_receiving_packet(len);
789
+
790
+ if (!emc_can_receive(nc)) {
791
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__);
792
+ return -1;
793
+ }
794
+
795
+ if (len < ETH_HLEN ||
796
+ /* Defensive programming: drop unsupportable large packets. */
797
+ len > 0xffff - CRC_LENGTH) {
798
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Dropped frame of %u bytes\n",
799
+ __func__, len);
800
+ return len;
801
+ }
802
+
803
+ /*
804
+ * DENI is set if EMC received the Length/Type field of the incoming
805
+ * packet, so it will be set regardless of what happens next.
806
+ */
807
+ emc_set_mista(emc, REG_MISTA_DENI);
808
+
809
+ if (!emc_receive_filter(emc, buf, len)) {
810
+ emc_update_rx_irq(emc);
811
+ return len;
812
+ }
813
+
814
+ /* Huge frames (> DMARFC) are dropped. */
815
+ max_frame_len = REG_DMARFC_RXMS(emc->regs[REG_DMARFC]);
816
+ if (len + CRC_LENGTH > max_frame_len) {
817
+ trace_npcm7xx_emc_packet_dropped(len);
818
+ emc_set_mista(emc, REG_MISTA_DFOI);
819
+ emc_update_rx_irq(emc);
820
+ return len;
821
+ }
822
+
823
+ /*
824
+ * Long Frames (> MAX_ETH_FRAME_SIZE) are also dropped, unless MCMDR.ALP
825
+ * is set.
826
+ */
827
+ long_frame = false;
828
+ if (len + CRC_LENGTH > MAX_ETH_FRAME_SIZE) {
829
+ if (emc->regs[REG_MCMDR] & REG_MCMDR_ALP) {
830
+ long_frame = true;
831
+ } else {
832
+ trace_npcm7xx_emc_packet_dropped(len);
833
+ emc_set_mista(emc, REG_MISTA_PTLE);
834
+ emc_update_rx_irq(emc);
835
+ return len;
836
+ }
837
+ }
838
+
839
+ desc_addr = RX_DESC_NRXDSA(emc->regs[REG_CRXDSA]);
840
+ if (emc_read_rx_desc(desc_addr, &rx_desc)) {
841
+ /* Error reading descriptor, already reported. */
842
+ emc_halt_rx(emc, REG_MISTA_RXBERR);
843
+ emc_update_rx_irq(emc);
844
+ return len;
845
+ }
846
+
847
+ /* Nothing we can do if we don't own the descriptor. */
848
+ if (!(rx_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK)) {
849
+ trace_npcm7xx_emc_cpu_owned_desc(desc_addr);
850
+ emc_halt_rx(emc, REG_MISTA_RDU);
851
+ emc_update_rx_irq(emc);
852
+ return len;
853
+ }
854
+
855
+ crc = 0;
856
+ crc_ptr = (uint8_t *) &crc;
857
+ if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) {
858
+ crc = cpu_to_be32(crc32(~0, buf, len));
859
+ }
860
+
861
+ /* Give the descriptor back regardless of what happens. */
862
+ rx_desc.status_and_length &= ~RX_DESC_STATUS_OWNER_MASK;
863
+
864
+ buf_addr = rx_desc.rxbsa;
865
+ emc->regs[REG_CRXBSA] = buf_addr;
866
+ if (dma_memory_write(&address_space_memory, buf_addr, buf, len) ||
867
+ (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) &&
868
+ dma_memory_write(&address_space_memory, buf_addr + len, crc_ptr,
869
+ 4))) {
870
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bus error writing packet\n",
871
+ __func__);
872
+ emc_set_mista(emc, REG_MISTA_RXBERR);
873
+ emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr);
874
+ emc_update_rx_irq(emc);
875
+ trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]);
876
+ return len;
877
+ }
878
+
879
+ trace_npcm7xx_emc_received_packet(len);
880
+
881
+ /* Note: We've already verified len+4 <= 0xffff. */
882
+ rx_desc.status_and_length = len;
883
+ if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) {
884
+ rx_desc.status_and_length += 4;
885
+ }
886
+ rx_desc.status_and_length |= RX_DESC_STATUS_RXGD;
887
+ emc_set_mista(emc, REG_MISTA_RXGD);
888
+
889
+ if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_RXINTR) {
890
+ rx_desc.status_and_length |= RX_DESC_STATUS_RXINTR;
891
+ }
892
+ if (long_frame) {
893
+ rx_desc.status_and_length |= RX_DESC_STATUS_PTLE;
894
+ }
895
+
896
+ emc_set_next_rx_descriptor(emc, &rx_desc, desc_addr);
897
+ emc_update_rx_irq(emc);
898
+ trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]);
899
+ return len;
900
+}
901
+
902
+static void emc_try_receive_next_packet(NPCM7xxEMCState *emc)
903
+{
904
+ if (emc_can_receive(qemu_get_queue(emc->nic))) {
905
+ qemu_flush_queued_packets(qemu_get_queue(emc->nic));
906
+ }
907
+}
908
+
909
+static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size)
910
+{
911
+ NPCM7xxEMCState *emc = opaque;
912
+ uint32_t reg = offset / sizeof(uint32_t);
913
+ uint32_t result;
914
+
915
+ if (reg >= NPCM7XX_NUM_EMC_REGS) {
916
+ qemu_log_mask(LOG_GUEST_ERROR,
917
+ "%s: Invalid offset 0x%04" HWADDR_PRIx "\n",
918
+ __func__, offset);
919
+ return 0;
920
+ }
921
+
922
+ switch (reg) {
923
+ case REG_MIID:
924
+ /*
925
+ * We don't implement MII. For determinism, always return zero as
926
+ * writes record the last value written for debugging purposes.
927
+ */
928
+ qemu_log_mask(LOG_UNIMP, "%s: Read of MIID, returning 0\n", __func__);
929
+ result = 0;
930
+ break;
931
+ case REG_TSDR:
932
+ case REG_RSDR:
933
+ qemu_log_mask(LOG_GUEST_ERROR,
934
+ "%s: Read of write-only reg, %s/%d\n",
935
+ __func__, emc_reg_name(reg), reg);
936
+ return 0;
937
+ default:
938
+ result = emc->regs[reg];
939
+ break;
940
+ }
941
+
942
+ trace_npcm7xx_emc_reg_read(emc->emc_num, result, emc_reg_name(reg), reg);
943
+ return result;
944
+}
945
+
946
+static void npcm7xx_emc_write(void *opaque, hwaddr offset,
947
+ uint64_t v, unsigned size)
948
+{
949
+ NPCM7xxEMCState *emc = opaque;
950
+ uint32_t reg = offset / sizeof(uint32_t);
951
+ uint32_t value = v;
952
+
953
+ g_assert(size == sizeof(uint32_t));
954
+
955
+ if (reg >= NPCM7XX_NUM_EMC_REGS) {
956
+ qemu_log_mask(LOG_GUEST_ERROR,
957
+ "%s: Invalid offset 0x%04" HWADDR_PRIx "\n",
958
+ __func__, offset);
268
+ return;
959
+ return;
269
+ }
960
+ }
270
+ busdev = SYS_BUS_DEVICE(dev);
961
+
271
+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
962
+ trace_npcm7xx_emc_reg_write(emc->emc_num, emc_reg_name(reg), reg, value);
272
+
963
+
273
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
964
+ switch (reg) {
274
+ gchar *bus_name;
965
+ case REG_CAMCMR:
275
+
966
+ emc->regs[reg] = value;
276
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
967
+ break;
277
+ if (err != NULL) {
968
+ case REG_CAMEN:
278
+ error_propagate(errp, err);
969
+ /* Only CAM0 is supported, don't pretend otherwise. */
279
+ return;
970
+ if (value & ~1) {
280
+ }
971
+ qemu_log_mask(LOG_GUEST_ERROR,
281
+
972
+ "%s: Only CAM0 is supported, cannot enable others"
282
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
973
+ ": 0x%x\n",
283
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
974
+ __func__, value);
284
+ qdev_get_gpio_in(armv7m, spi_irq[i]));
975
+ }
285
+
976
+ emc->regs[reg] = value & 1;
286
+ /* Alias controller SPI bus to the SoC itself */
977
+ break;
287
+ bus_name = g_strdup_printf("spi%d", i);
978
+ case REG_CAMM_BASE + 0:
288
+ object_property_add_alias(OBJECT(s), bus_name,
979
+ emc->regs[reg] = value;
289
+ OBJECT(&s->spi[i]), "spi",
980
+ emc->conf.macaddr.a[0] = value >> 24;
290
+ &error_abort);
981
+ emc->conf.macaddr.a[1] = value >> 16;
291
+ g_free(bus_name);
982
+ emc->conf.macaddr.a[2] = value >> 8;
292
+ }
983
+ emc->conf.macaddr.a[3] = value >> 0;
293
+
984
+ break;
294
+ /* Below devices are not modelled yet. */
985
+ case REG_CAML_BASE + 0:
295
+ create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
986
+ emc->regs[reg] = value;
296
+ create_unimplemented_device("dma", 0x40003000, 0x1000);
987
+ emc->conf.macaddr.a[4] = value >> 24;
297
+ create_unimplemented_device("watchdog", 0x40005000, 0x1000);
988
+ emc->conf.macaddr.a[5] = value >> 16;
298
+ create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
989
+ break;
299
+ create_unimplemented_device("gpio", 0x40013000, 0x1000);
990
+ case REG_MCMDR: {
300
+ create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
991
+ uint32_t prev;
301
+ create_unimplemented_device("can", 0x40015000, 0x1000);
992
+ if (value & REG_MCMDR_SWR) {
302
+ create_unimplemented_device("rtc", 0x40017000, 0x1000);
993
+ emc_soft_reset(emc);
303
+ create_unimplemented_device("apb_config", 0x40020000, 0x10000);
994
+ /* On h/w the reset happens over multiple cycles. For now KISS. */
304
+ create_unimplemented_device("emac", 0x40041000, 0x1000);
995
+ break;
305
+ create_unimplemented_device("usb", 0x40043000, 0x1000);
996
+ }
306
+}
997
+ prev = emc->regs[reg];
307
+
998
+ emc->regs[reg] = value;
308
+static Property m2sxxx_soc_properties[] = {
999
+ /* Update tx state. */
309
+ /*
1000
+ if (!(prev & REG_MCMDR_TXON) &&
310
+ * part name specifies the type of SmartFusion2 device variant(this
1001
+ (value & REG_MCMDR_TXON)) {
311
+ * property is for information purpose only.
1002
+ emc->regs[REG_CTXDSA] = emc->regs[REG_TXDLSA];
312
+ */
1003
+ /*
313
+ DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
1004
+ * Linux kernel turns TX on with CPU still holding descriptor,
314
+ DEFINE_PROP_STRING("part-name", MSF2State, part_name),
1005
+ * which suggests we should wait for a write to TSDR before trying
315
+ DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
1006
+ * to send a packet: so we don't send one here.
316
+ DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
1007
+ */
317
+ MSF2_ESRAM_MAX_SIZE),
1008
+ } else if ((prev & REG_MCMDR_TXON) &&
318
+ /* Libero GUI shows 100Mhz as default for clocks */
1009
+ !(value & REG_MCMDR_TXON)) {
319
+ DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
1010
+ emc->regs[REG_MGSTA] |= REG_MGSTA_TXHA;
320
+ /* default divisors in Libero GUI */
1011
+ }
321
+ DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
1012
+ if (!(value & REG_MCMDR_TXON)) {
322
+ DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
1013
+ emc_halt_tx(emc, 0);
1014
+ }
1015
+ /* Update rx state. */
1016
+ if (!(prev & REG_MCMDR_RXON) &&
1017
+ (value & REG_MCMDR_RXON)) {
1018
+ emc->regs[REG_CRXDSA] = emc->regs[REG_RXDLSA];
1019
+ } else if ((prev & REG_MCMDR_RXON) &&
1020
+ !(value & REG_MCMDR_RXON)) {
1021
+ emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA;
1022
+ }
1023
+ if (!(value & REG_MCMDR_RXON)) {
1024
+ emc_halt_rx(emc, 0);
1025
+ }
1026
+ break;
1027
+ }
1028
+ case REG_TXDLSA:
1029
+ case REG_RXDLSA:
1030
+ case REG_DMARFC:
1031
+ case REG_MIID:
1032
+ emc->regs[reg] = value;
1033
+ break;
1034
+ case REG_MIEN:
1035
+ emc->regs[reg] = value;
1036
+ emc_update_irq_from_reg_change(emc);
1037
+ break;
1038
+ case REG_MISTA:
1039
+ /* Clear the bits that have 1 in "value". */
1040
+ emc->regs[reg] &= ~value;
1041
+ emc_update_irq_from_reg_change(emc);
1042
+ break;
1043
+ case REG_MGSTA:
1044
+ /* Clear the bits that have 1 in "value". */
1045
+ emc->regs[reg] &= ~value;
1046
+ break;
1047
+ case REG_TSDR:
1048
+ if (emc->regs[REG_MCMDR] & REG_MCMDR_TXON) {
1049
+ emc->tx_active = true;
1050
+ /* Keep trying to send packets until we run out. */
1051
+ while (emc->tx_active) {
1052
+ emc_try_send_next_packet(emc);
1053
+ }
1054
+ }
1055
+ break;
1056
+ case REG_RSDR:
1057
+ if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) {
1058
+ emc->rx_active = true;
1059
+ emc_try_receive_next_packet(emc);
1060
+ }
1061
+ break;
1062
+ case REG_MIIDA:
1063
+ emc->regs[reg] = value & ~REG_MIIDA_BUSY;
1064
+ break;
1065
+ case REG_MRPC:
1066
+ case REG_MRPCC:
1067
+ case REG_MREPC:
1068
+ case REG_CTXDSA:
1069
+ case REG_CTXBSA:
1070
+ case REG_CRXDSA:
1071
+ case REG_CRXBSA:
1072
+ qemu_log_mask(LOG_GUEST_ERROR,
1073
+ "%s: Write to read-only reg %s/%d\n",
1074
+ __func__, emc_reg_name(reg), reg);
1075
+ break;
1076
+ default:
1077
+ qemu_log_mask(LOG_UNIMP, "%s: Write to unimplemented reg %s/%d\n",
1078
+ __func__, emc_reg_name(reg), reg);
1079
+ break;
1080
+ }
1081
+}
1082
+
1083
+static const struct MemoryRegionOps npcm7xx_emc_ops = {
1084
+ .read = npcm7xx_emc_read,
1085
+ .write = npcm7xx_emc_write,
1086
+ .endianness = DEVICE_LITTLE_ENDIAN,
1087
+ .valid = {
1088
+ .min_access_size = 4,
1089
+ .max_access_size = 4,
1090
+ .unaligned = false,
1091
+ },
1092
+};
1093
+
1094
+static void emc_cleanup(NetClientState *nc)
1095
+{
1096
+ /* Nothing to do yet. */
1097
+}
1098
+
1099
+static NetClientInfo net_npcm7xx_emc_info = {
1100
+ .type = NET_CLIENT_DRIVER_NIC,
1101
+ .size = sizeof(NICState),
1102
+ .can_receive = emc_can_receive,
1103
+ .receive = emc_receive,
1104
+ .cleanup = emc_cleanup,
1105
+ .link_status_changed = emc_set_link,
1106
+};
1107
+
1108
+static void npcm7xx_emc_realize(DeviceState *dev, Error **errp)
1109
+{
1110
+ NPCM7xxEMCState *emc = NPCM7XX_EMC(dev);
1111
+ SysBusDevice *sbd = SYS_BUS_DEVICE(emc);
1112
+
1113
+ memory_region_init_io(&emc->iomem, OBJECT(emc), &npcm7xx_emc_ops, emc,
1114
+ TYPE_NPCM7XX_EMC, 4 * KiB);
1115
+ sysbus_init_mmio(sbd, &emc->iomem);
1116
+ sysbus_init_irq(sbd, &emc->tx_irq);
1117
+ sysbus_init_irq(sbd, &emc->rx_irq);
1118
+
1119
+ qemu_macaddr_default_if_unset(&emc->conf.macaddr);
1120
+ emc->nic = qemu_new_nic(&net_npcm7xx_emc_info, &emc->conf,
1121
+ object_get_typename(OBJECT(dev)), dev->id, emc);
1122
+ qemu_format_nic_info_str(qemu_get_queue(emc->nic), emc->conf.macaddr.a);
1123
+}
1124
+
1125
+static void npcm7xx_emc_unrealize(DeviceState *dev)
1126
+{
1127
+ NPCM7xxEMCState *emc = NPCM7XX_EMC(dev);
1128
+
1129
+ qemu_del_nic(emc->nic);
1130
+}
1131
+
1132
+static const VMStateDescription vmstate_npcm7xx_emc = {
1133
+ .name = TYPE_NPCM7XX_EMC,
1134
+ .version_id = 0,
1135
+ .minimum_version_id = 0,
1136
+ .fields = (VMStateField[]) {
1137
+ VMSTATE_UINT8(emc_num, NPCM7xxEMCState),
1138
+ VMSTATE_UINT32_ARRAY(regs, NPCM7xxEMCState, NPCM7XX_NUM_EMC_REGS),
1139
+ VMSTATE_BOOL(tx_active, NPCM7xxEMCState),
1140
+ VMSTATE_BOOL(rx_active, NPCM7xxEMCState),
1141
+ VMSTATE_END_OF_LIST(),
1142
+ },
1143
+};
1144
+
1145
+static Property npcm7xx_emc_properties[] = {
1146
+ DEFINE_NIC_PROPERTIES(NPCM7xxEMCState, conf),
323
+ DEFINE_PROP_END_OF_LIST(),
1147
+ DEFINE_PROP_END_OF_LIST(),
324
+};
1148
+};
325
+
1149
+
326
+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
1150
+static void npcm7xx_emc_class_init(ObjectClass *klass, void *data)
327
+{
1151
+{
328
+ DeviceClass *dc = DEVICE_CLASS(klass);
1152
+ DeviceClass *dc = DEVICE_CLASS(klass);
329
+
1153
+
330
+ dc->realize = m2sxxx_soc_realize;
1154
+ set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
331
+ dc->props = m2sxxx_soc_properties;
1155
+ dc->desc = "NPCM7xx EMC Controller";
332
+}
1156
+ dc->realize = npcm7xx_emc_realize;
333
+
1157
+ dc->unrealize = npcm7xx_emc_unrealize;
334
+static const TypeInfo m2sxxx_soc_info = {
1158
+ dc->reset = npcm7xx_emc_reset;
335
+ .name = TYPE_MSF2_SOC,
1159
+ dc->vmsd = &vmstate_npcm7xx_emc;
336
+ .parent = TYPE_SYS_BUS_DEVICE,
1160
+ device_class_set_props(dc, npcm7xx_emc_properties);
337
+ .instance_size = sizeof(MSF2State),
1161
+}
338
+ .instance_init = m2sxxx_soc_initfn,
1162
+
339
+ .class_init = m2sxxx_soc_class_init,
1163
+static const TypeInfo npcm7xx_emc_info = {
1164
+ .name = TYPE_NPCM7XX_EMC,
1165
+ .parent = TYPE_SYS_BUS_DEVICE,
1166
+ .instance_size = sizeof(NPCM7xxEMCState),
1167
+ .class_init = npcm7xx_emc_class_init,
340
+};
1168
+};
341
+
1169
+
342
+static void m2sxxx_soc_types(void)
1170
+static void npcm7xx_emc_register_type(void)
343
+{
1171
+{
344
+ type_register_static(&m2sxxx_soc_info);
1172
+ type_register_static(&npcm7xx_emc_info);
345
+}
1173
+}
346
+
1174
+
347
+type_init(m2sxxx_soc_types)
1175
+type_init(npcm7xx_emc_register_type)
348
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
1176
diff --git a/hw/net/meson.build b/hw/net/meson.build
349
index XXXXXXX..XXXXXXX 100644
1177
index XXXXXXX..XXXXXXX 100644
350
--- a/default-configs/arm-softmmu.mak
1178
--- a/hw/net/meson.build
351
+++ b/default-configs/arm-softmmu.mak
1179
+++ b/hw/net/meson.build
352
@@ -XXX,XX +XXX,XX @@ CONFIG_ACPI=y
1180
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_I82596_COMMON', if_true: files('i82596.c'))
353
CONFIG_SMBIOS=y
1181
softmmu_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c'))
354
CONFIG_ASPEED_SOC=y
1182
softmmu_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c'))
355
CONFIG_GPIO_KEY=y
1183
softmmu_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c'))
356
+CONFIG_MSF2=y
1184
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c'))
1185
1186
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_eth.c'))
1187
softmmu_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c'))
1188
diff --git a/hw/net/trace-events b/hw/net/trace-events
1189
index XXXXXXX..XXXXXXX 100644
1190
--- a/hw/net/trace-events
1191
+++ b/hw/net/trace-events
1192
@@ -XXX,XX +XXX,XX @@ imx_fec_receive_last(int last) "rx frame flags 0x%04x"
1193
imx_enet_receive(size_t size) "len %zu"
1194
imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d"
1195
imx_enet_receive_last(int last) "rx frame flags 0x%04x"
1196
+
1197
+# npcm7xx_emc.c
1198
+npcm7xx_emc_reset(int emc_num) "Resetting emc%d"
1199
+npcm7xx_emc_update_tx_irq(int level) "Setting tx irq to %d"
1200
+npcm7xx_emc_update_rx_irq(int level) "Setting rx irq to %d"
1201
+npcm7xx_emc_set_mista(uint32_t flags) "ORing 0x%x into MISTA"
1202
+npcm7xx_emc_cpu_owned_desc(uint32_t addr) "Can't process cpu-owned descriptor @0x%x"
1203
+npcm7xx_emc_sent_packet(uint32_t len) "Sent %u byte packet"
1204
+npcm7xx_emc_tx_done(uint32_t ctxdsa) "TX done, CTXDSA=0x%x"
1205
+npcm7xx_emc_can_receive(int can_receive) "Can receive: %d"
1206
+npcm7xx_emc_packet_filtered_out(const char* fail_reason) "Packet filtered out: %s"
1207
+npcm7xx_emc_packet_dropped(uint32_t len) "%u byte packet dropped"
1208
+npcm7xx_emc_receiving_packet(uint32_t len) "Receiving %u byte packet"
1209
+npcm7xx_emc_received_packet(uint32_t len) "Received %u byte packet"
1210
+npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=0x%x"
1211
+npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int regno) "emc%d: 0x%x = reg[%s/%d]"
1212
+npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t value) "emc%d: reg[%s/%d] = 0x%x"
357
--
1213
--
358
2.7.4
1214
2.20.1
359
1215
360
1216
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Doug Evans <dje@google.com>
2
2
3
Added Sytem register block of Smartfusion2.
3
This is a 10/100 ethernet device that has several features.
4
This block has PLL registers which are accessed by guest.
4
Only the ones needed by the Linux driver have been implemented.
5
See npcm7xx_emc.c for a list of unimplemented features.
5
6
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Reviewed-by: Hao Wu <wuhaotsh@google.com>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
8
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Signed-off-by: Doug Evans <dje@google.com>
10
Message-id: 20170920201737.25723-3-f4bug@amsat.org
11
Message-id: 20210218212453.831406-3-dje@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
---
13
hw/misc/Makefile.objs | 1 +
14
docs/system/arm/nuvoton.rst | 3 ++-
14
include/hw/misc/msf2-sysreg.h | 77 ++++++++++++++++++++
15
include/hw/arm/npcm7xx.h | 2 ++
15
hw/misc/msf2-sysreg.c | 160 ++++++++++++++++++++++++++++++++++++++++++
16
hw/arm/npcm7xx.c | 50 +++++++++++++++++++++++++++++++++++--
16
hw/misc/trace-events | 5 ++
17
3 files changed, 52 insertions(+), 3 deletions(-)
17
4 files changed, 243 insertions(+)
18
create mode 100644 include/hw/misc/msf2-sysreg.h
19
create mode 100644 hw/misc/msf2-sysreg.c
20
18
21
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
19
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
22
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/misc/Makefile.objs
21
--- a/docs/system/arm/nuvoton.rst
24
+++ b/hw/misc/Makefile.objs
22
+++ b/docs/system/arm/nuvoton.rst
25
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
23
@@ -XXX,XX +XXX,XX @@ Supported devices
26
obj-$(CONFIG_AUX) += auxbus.o
24
* Analog to Digital Converter (ADC)
27
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
25
* Pulse Width Modulation (PWM)
28
obj-y += mmio_interface.o
26
* SMBus controller (SMBF)
29
+obj-$(CONFIG_MSF2) += msf2-sysreg.o
27
+ * Ethernet controller (EMC)
30
diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
28
31
new file mode 100644
29
Missing devices
32
index XXXXXXX..XXXXXXX
30
---------------
33
--- /dev/null
31
@@ -XXX,XX +XXX,XX @@ Missing devices
34
+++ b/include/hw/misc/msf2-sysreg.h
32
* Shared memory (SHM)
33
* eSPI slave interface
34
35
- * Ethernet controllers (GMAC and EMC)
36
+ * Ethernet controller (GMAC)
37
* USB device (USBD)
38
* Peripheral SPI controller (PSPI)
39
* SD/MMC host
40
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/arm/npcm7xx.h
43
+++ b/include/hw/arm/npcm7xx.h
35
@@ -XXX,XX +XXX,XX @@
44
@@ -XXX,XX +XXX,XX @@
36
+/*
45
#include "hw/misc/npcm7xx_gcr.h"
37
+ * Microsemi SmartFusion2 SYSREG
46
#include "hw/misc/npcm7xx_pwm.h"
38
+ *
47
#include "hw/misc/npcm7xx_rng.h"
39
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
48
+#include "hw/net/npcm7xx_emc.h"
40
+ *
49
#include "hw/nvram/npcm7xx_otp.h"
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
50
#include "hw/timer/npcm7xx_timer.h"
42
+ * of this software and associated documentation files (the "Software"), to deal
51
#include "hw/ssi/npcm7xx_fiu.h"
43
+ * in the Software without restriction, including without limitation the rights
52
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
53
EHCISysBusState ehci;
45
+ * copies of the Software, and to permit persons to whom the Software is
54
OHCISysBusState ohci;
46
+ * furnished to do so, subject to the following conditions:
55
NPCM7xxFIUState fiu[2];
47
+ *
56
+ NPCM7xxEMCState emc[2];
48
+ * The above copyright notice and this permission notice shall be included in
57
} NPCM7xxState;
49
+ * all copies or substantial portions of the Software.
58
50
+ *
59
#define TYPE_NPCM7XX "npcm7xx"
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
60
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
61
index XXXXXXX..XXXXXXX 100644
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
62
--- a/hw/arm/npcm7xx.c
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
63
+++ b/hw/arm/npcm7xx.c
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
64
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
65
NPCM7XX_UART1_IRQ,
57
+ * THE SOFTWARE.
66
NPCM7XX_UART2_IRQ,
58
+ */
67
NPCM7XX_UART3_IRQ,
59
+
68
+ NPCM7XX_EMC1RX_IRQ = 15,
60
+#ifndef HW_MSF2_SYSREG_H
69
+ NPCM7XX_EMC1TX_IRQ,
61
+#define HW_MSF2_SYSREG_H
70
NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
62
+
71
NPCM7XX_TIMER1_IRQ,
63
+#include "hw/sysbus.h"
72
NPCM7XX_TIMER2_IRQ,
64
+
73
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
65
+enum {
74
NPCM7XX_SMBUS15_IRQ,
66
+ ESRAM_CR = 0x00 / 4,
75
NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
67
+ ESRAM_MAX_LAT,
76
NPCM7XX_PWM1_IRQ, /* PWM module 1 */
68
+ DDR_CR,
77
+ NPCM7XX_EMC2RX_IRQ = 114,
69
+ ENVM_CR,
78
+ NPCM7XX_EMC2TX_IRQ,
70
+ ENVM_REMAP_BASE_CR,
79
NPCM7XX_GPIO0_IRQ = 116,
71
+ ENVM_REMAP_FAB_CR,
80
NPCM7XX_GPIO1_IRQ,
72
+ CC_CR,
81
NPCM7XX_GPIO2_IRQ,
73
+ CC_REGION_CR,
82
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_smbus_addr[] = {
74
+ CC_LOCK_BASE_ADDR_CR,
83
0xf008f000,
75
+ CC_FLUSH_INDX_CR,
84
};
76
+ DDRB_BUF_TIMER_CR,
85
77
+ DDRB_NB_ADDR_CR,
86
+/* Register base address for each EMC Module */
78
+ DDRB_NB_SIZE_CR,
87
+static const hwaddr npcm7xx_emc_addr[] = {
79
+ DDRB_CR,
88
+ 0xf0825000,
80
+
89
+ 0xf0826000,
81
+ SOFT_RESET_CR = 0x48 / 4,
82
+ M3_CR,
83
+
84
+ GPIO_SYSRESET_SEL_CR = 0x58 / 4,
85
+
86
+ MDDR_CR = 0x60 / 4,
87
+
88
+ MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
89
+ MSSDDR_PLL_STATUS_HIGH_CR,
90
+ MSSDDR_FACC1_CR,
91
+ MSSDDR_FACC2_CR,
92
+
93
+ MSSDDR_PLL_STATUS = 0x150 / 4,
94
+};
90
+};
95
+
91
+
96
+#define MSF2_SYSREG_MMIO_SIZE 0x300
92
static const struct {
93
hwaddr regs_addr;
94
uint32_t unconnected_pins;
95
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
96
for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
97
object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
98
}
97
+
99
+
98
+#define TYPE_MSF2_SYSREG "msf2-sysreg"
100
+ for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
99
+#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
101
+ object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
100
+
102
+ }
101
+typedef struct MSF2SysregState {
103
}
102
+ SysBusDevice parent_obj;
104
103
+
105
static void npcm7xx_realize(DeviceState *dev, Error **errp)
104
+ MemoryRegion iomem;
106
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
105
+
107
sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
106
+ uint8_t apb0div;
108
}
107
+ uint8_t apb1div;
109
108
+
110
+ /*
109
+ uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
111
+ * EMC Modules. Cannot fail.
110
+} MSF2SysregState;
112
+ * The mapping of the device to its netdev backend works as follows:
111
+
113
+ * emc[i] = nd_table[i]
112
+#endif /* HW_MSF2_SYSREG_H */
114
+ * This works around the inability to specify the netdev property for the
113
diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
115
+ * emc device: it's not pluggable and thus the -device option can't be
114
new file mode 100644
116
+ * used.
115
index XXXXXXX..XXXXXXX
117
+ */
116
--- /dev/null
118
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) != ARRAY_SIZE(s->emc));
117
+++ b/hw/misc/msf2-sysreg.c
119
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) != 2);
118
@@ -XXX,XX +XXX,XX @@
120
+ for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
119
+/*
121
+ s->emc[i].emc_num = i;
120
+ * System Register block model of Microsemi SmartFusion2.
122
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->emc[i]);
121
+ *
123
+ if (nd_table[i].used) {
122
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
124
+ qemu_check_nic_model(&nd_table[i], TYPE_NPCM7XX_EMC);
123
+ *
125
+ qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]);
124
+ * This program is free software; you can redistribute it and/or
126
+ }
125
+ * modify it under the terms of the GNU General Public License
127
+ /*
126
+ * as published by the Free Software Foundation; either version
128
+ * The device exists regardless of whether it's connected to a QEMU
127
+ * 2 of the License, or (at your option) any later version.
129
+ * netdev backend. So always instantiate it even if there is no
128
+ *
130
+ * backend.
129
+ * You should have received a copy of the GNU General Public License along
131
+ */
130
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
132
+ sysbus_realize(sbd, &error_abort);
131
+ */
133
+ sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]);
132
+
134
+ int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ;
133
+#include "qemu/osdep.h"
135
+ int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ;
134
+#include "qapi/error.h"
136
+ /*
135
+#include "qemu/log.h"
137
+ * N.B. The values for the second argument sysbus_connect_irq are
136
+#include "hw/misc/msf2-sysreg.h"
138
+ * chosen to match the registration order in npcm7xx_emc_realize.
137
+#include "qemu/error-report.h"
139
+ */
138
+#include "trace.h"
140
+ sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq));
139
+
141
+ sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq));
140
+static inline int msf2_divbits(uint32_t div)
141
+{
142
+ int r = ctz32(div);
143
+
144
+ return (div < 8) ? r : r + 1;
145
+}
146
+
147
+static void msf2_sysreg_reset(DeviceState *d)
148
+{
149
+ MSF2SysregState *s = MSF2_SYSREG(d);
150
+
151
+ s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
152
+ s->regs[MSSDDR_PLL_STATUS] = 0x3;
153
+ s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
154
+ msf2_divbits(s->apb1div) << 2;
155
+}
156
+
157
+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
158
+ unsigned size)
159
+{
160
+ MSF2SysregState *s = opaque;
161
+ uint32_t ret = 0;
162
+
163
+ offset >>= 2;
164
+ if (offset < ARRAY_SIZE(s->regs)) {
165
+ ret = s->regs[offset];
166
+ trace_msf2_sysreg_read(offset << 2, ret);
167
+ } else {
168
+ qemu_log_mask(LOG_GUEST_ERROR,
169
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
170
+ offset << 2);
171
+ }
142
+ }
172
+
143
+
173
+ return ret;
144
/*
174
+}
145
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
175
+
146
* specified, but this is a programming error.
176
+static void msf2_sysreg_write(void *opaque, hwaddr offset,
147
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
177
+ uint64_t val, unsigned size)
148
create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
178
+{
149
create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
179
+ MSF2SysregState *s = opaque;
150
create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
180
+ uint32_t newval = val;
151
- create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB);
181
+
152
- create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB);
182
+ offset >>= 2;
153
create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB);
183
+
154
create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB);
184
+ switch (offset) {
155
create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB);
185
+ case MSSDDR_PLL_STATUS:
186
+ trace_msf2_sysreg_write_pll_status();
187
+ break;
188
+
189
+ case ESRAM_CR:
190
+ case DDR_CR:
191
+ case ENVM_REMAP_BASE_CR:
192
+ if (newval != s->regs[offset]) {
193
+ qemu_log_mask(LOG_UNIMP,
194
+ TYPE_MSF2_SYSREG": remapping not supported\n");
195
+ }
196
+ break;
197
+
198
+ default:
199
+ if (offset < ARRAY_SIZE(s->regs)) {
200
+ trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);
201
+ s->regs[offset] = newval;
202
+ } else {
203
+ qemu_log_mask(LOG_GUEST_ERROR,
204
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
205
+ offset << 2);
206
+ }
207
+ break;
208
+ }
209
+}
210
+
211
+static const MemoryRegionOps sysreg_ops = {
212
+ .read = msf2_sysreg_read,
213
+ .write = msf2_sysreg_write,
214
+ .endianness = DEVICE_NATIVE_ENDIAN,
215
+};
216
+
217
+static void msf2_sysreg_init(Object *obj)
218
+{
219
+ MSF2SysregState *s = MSF2_SYSREG(obj);
220
+
221
+ memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
222
+ MSF2_SYSREG_MMIO_SIZE);
223
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
224
+}
225
+
226
+static const VMStateDescription vmstate_msf2_sysreg = {
227
+ .name = TYPE_MSF2_SYSREG,
228
+ .version_id = 1,
229
+ .minimum_version_id = 1,
230
+ .fields = (VMStateField[]) {
231
+ VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
+static Property msf2_sysreg_properties[] = {
237
+ /* default divisors in Libero GUI */
238
+ DEFINE_PROP_UINT8("apb0divisor", MSF2SysregState, apb0div, 2),
239
+ DEFINE_PROP_UINT8("apb1divisor", MSF2SysregState, apb1div, 2),
240
+ DEFINE_PROP_END_OF_LIST(),
241
+};
242
+
243
+static void msf2_sysreg_realize(DeviceState *dev, Error **errp)
244
+{
245
+ MSF2SysregState *s = MSF2_SYSREG(dev);
246
+
247
+ if ((s->apb0div > 32 || !is_power_of_2(s->apb0div))
248
+ || (s->apb1div > 32 || !is_power_of_2(s->apb1div))) {
249
+ error_setg(errp, "Invalid apb divisor value");
250
+ error_append_hint(errp, "apb divisor must be a power of 2"
251
+ " and maximum value is 32\n");
252
+ }
253
+}
254
+
255
+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
256
+{
257
+ DeviceClass *dc = DEVICE_CLASS(klass);
258
+
259
+ dc->vmsd = &vmstate_msf2_sysreg;
260
+ dc->reset = msf2_sysreg_reset;
261
+ dc->props = msf2_sysreg_properties;
262
+ dc->realize = msf2_sysreg_realize;
263
+}
264
+
265
+static const TypeInfo msf2_sysreg_info = {
266
+ .name = TYPE_MSF2_SYSREG,
267
+ .parent = TYPE_SYS_BUS_DEVICE,
268
+ .class_init = msf2_sysreg_class_init,
269
+ .instance_size = sizeof(MSF2SysregState),
270
+ .instance_init = msf2_sysreg_init,
271
+};
272
+
273
+static void msf2_sysreg_register_types(void)
274
+{
275
+ type_register_static(&msf2_sysreg_info);
276
+}
277
+
278
+type_init(msf2_sysreg_register_types)
279
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
280
index XXXXXXX..XXXXXXX 100644
281
--- a/hw/misc/trace-events
282
+++ b/hw/misc/trace-events
283
@@ -XXX,XX +XXX,XX @@ mps2_scc_reset(void) "MPS2 SCC: reset"
284
mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) "MPS2 SCC LEDs: %c%c%c%c%c%c%c%c"
285
mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
286
mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
287
+
288
+# hw/misc/msf2-sysreg.c
289
+msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
290
+msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
291
+msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
292
--
156
--
293
2.7.4
157
2.20.1
294
158
295
159
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Doug Evans <dje@google.com>
2
2
3
Emulated Emcraft's Smartfusion2 System On Module starter
3
Reviewed-by: Hao Wu <wuhaotsh@google.com>
4
kit.
4
Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
5
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
Signed-off-by: Doug Evans <dje@google.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210218212453.831406-4-dje@google.com
8
Message-id: 20170920201737.25723-6-f4bug@amsat.org
9
[PMD: drop cpu_model to directly use cpu type]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
hw/arm/Makefile.objs | 2 +-
10
tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++
13
hw/arm/msf2-som.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++
11
tests/qtest/meson.build | 3 +-
14
2 files changed, 106 insertions(+), 1 deletion(-)
12
2 files changed, 864 insertions(+), 1 deletion(-)
15
create mode 100644 hw/arm/msf2-som.c
13
create mode 100644 tests/qtest/npcm7xx_emc-test.c
16
14
17
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
15
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/Makefile.objs
20
+++ b/hw/arm/Makefile.objs
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
22
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
23
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
24
obj-$(CONFIG_MPS2) += mps2.o
25
-obj-$(CONFIG_MSF2) += msf2-soc.o
26
+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
27
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
28
new file mode 100644
16
new file mode 100644
29
index XXXXXXX..XXXXXXX
17
index XXXXXXX..XXXXXXX
30
--- /dev/null
18
--- /dev/null
31
+++ b/hw/arm/msf2-som.c
19
+++ b/tests/qtest/npcm7xx_emc-test.c
32
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
33
+/*
21
+/*
34
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
22
+ * QTests for Nuvoton NPCM7xx EMC Modules.
35
+ *
23
+ *
36
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
24
+ * Copyright 2020 Google LLC
37
+ *
25
+ *
38
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
26
+ * This program is free software; you can redistribute it and/or modify it
39
+ * of this software and associated documentation files (the "Software"), to deal
27
+ * under the terms of the GNU General Public License as published by the
40
+ * in the Software without restriction, including without limitation the rights
28
+ * Free Software Foundation; either version 2 of the License, or
41
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
29
+ * (at your option) any later version.
42
+ * copies of the Software, and to permit persons to whom the Software is
43
+ * furnished to do so, subject to the following conditions:
44
+ *
30
+ *
45
+ * The above copyright notice and this permission notice shall be included in
31
+ * This program is distributed in the hope that it will be useful, but WITHOUT
46
+ * all copies or substantial portions of the Software.
32
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
47
+ *
33
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
48
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
34
+ * for more details.
49
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
50
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
51
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
52
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
53
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
54
+ * THE SOFTWARE.
55
+ */
35
+ */
56
+
36
+
57
+#include "qemu/osdep.h"
37
+#include "qemu/osdep.h"
58
+#include "qapi/error.h"
38
+#include "qemu-common.h"
59
+#include "qemu/error-report.h"
39
+#include "libqos/libqos.h"
60
+#include "hw/boards.h"
40
+#include "qapi/qmp/qdict.h"
61
+#include "hw/arm/arm.h"
41
+#include "qapi/qmp/qnum.h"
62
+#include "exec/address-spaces.h"
42
+#include "qemu/bitops.h"
63
+#include "qemu/cutils.h"
43
+#include "qemu/iov.h"
64
+#include "hw/arm/msf2-soc.h"
44
+
65
+#include "cpu.h"
45
+/* Name of the emc device. */
66
+
46
+#define TYPE_NPCM7XX_EMC "npcm7xx-emc"
67
+#define DDR_BASE_ADDRESS 0xA0000000
47
+
68
+#define DDR_SIZE (64 * M_BYTE)
48
+/* Timeout for various operations, in seconds. */
69
+
49
+#define TIMEOUT_SECONDS 10
70
+#define M2S010_ENVM_SIZE (256 * K_BYTE)
50
+
71
+#define M2S010_ESRAM_SIZE (64 * K_BYTE)
51
+/* Address in memory of the descriptor. */
72
+
52
+#define DESC_ADDR (1 << 20) /* 1 MiB */
73
+static void emcraft_sf2_s2s010_init(MachineState *machine)
53
+
74
+{
54
+/* Address in memory of the data packet. */
75
+ DeviceState *dev;
55
+#define DATA_ADDR (DESC_ADDR + 4096)
76
+ DeviceState *spi_flash;
56
+
77
+ MSF2State *soc;
57
+#define CRC_LENGTH 4
78
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
58
+
79
+ DriveInfo *dinfo = drive_get_next(IF_MTD);
59
+#define NUM_TX_DESCRIPTORS 3
80
+ qemu_irq cs_line;
60
+#define NUM_RX_DESCRIPTORS 2
81
+ SSIBus *spi_bus;
61
+
82
+ MemoryRegion *sysmem = get_system_memory();
62
+/* Size of tx,rx test buffers. */
83
+ MemoryRegion *ddr = g_new(MemoryRegion, 1);
63
+#define TX_DATA_LEN 64
84
+
64
+#define RX_DATA_LEN 64
85
+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
65
+
86
+ error_report("This board can only be used with CPU %s",
66
+#define TX_STEP_COUNT 10000
87
+ mc->default_cpu_type);
67
+#define RX_STEP_COUNT 10000
88
+ }
68
+
89
+
69
+/* 32-bit register indices. */
90
+ memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
70
+typedef enum NPCM7xxPWMRegister {
91
+ &error_fatal);
71
+ /* Control registers. */
92
+ memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
72
+ REG_CAMCMR,
93
+
73
+ REG_CAMEN,
94
+ dev = qdev_create(NULL, TYPE_MSF2_SOC);
74
+
95
+ qdev_prop_set_string(dev, "part-name", "M2S010");
75
+ /* There are 16 CAMn[ML] registers. */
96
+ qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
76
+ REG_CAMM_BASE,
97
+
77
+ REG_CAML_BASE,
98
+ qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
78
+
99
+ qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
79
+ REG_TXDLSA = 0x22,
80
+ REG_RXDLSA,
81
+ REG_MCMDR,
82
+ REG_MIID,
83
+ REG_MIIDA,
84
+ REG_FFTCR,
85
+ REG_TSDR,
86
+ REG_RSDR,
87
+ REG_DMARFC,
88
+ REG_MIEN,
89
+
90
+ /* Status registers. */
91
+ REG_MISTA,
92
+ REG_MGSTA,
93
+ REG_MPCNT,
94
+ REG_MRPC,
95
+ REG_MRPCC,
96
+ REG_MREPC,
97
+ REG_DMARFS,
98
+ REG_CTXDSA,
99
+ REG_CTXBSA,
100
+ REG_CRXDSA,
101
+ REG_CRXBSA,
102
+
103
+ NPCM7XX_NUM_EMC_REGS,
104
+} NPCM7xxPWMRegister;
105
+
106
+enum { NUM_CAMML_REGS = 16 };
107
+
108
+/* REG_CAMCMR fields */
109
+/* Enable CAM Compare */
110
+#define REG_CAMCMR_ECMP (1 << 4)
111
+/* Accept Unicast Packet */
112
+#define REG_CAMCMR_AUP (1 << 0)
113
+
114
+/* REG_MCMDR fields */
115
+/* Software Reset */
116
+#define REG_MCMDR_SWR (1 << 24)
117
+/* Frame Transmission On */
118
+#define REG_MCMDR_TXON (1 << 8)
119
+/* Accept Long Packet */
120
+#define REG_MCMDR_ALP (1 << 1)
121
+/* Frame Reception On */
122
+#define REG_MCMDR_RXON (1 << 0)
123
+
124
+/* REG_MIEN fields */
125
+/* Enable Transmit Completion Interrupt */
126
+#define REG_MIEN_ENTXCP (1 << 18)
127
+/* Enable Transmit Interrupt */
128
+#define REG_MIEN_ENTXINTR (1 << 16)
129
+/* Enable Receive Good Interrupt */
130
+#define REG_MIEN_ENRXGD (1 << 4)
131
+/* ENable Receive Interrupt */
132
+#define REG_MIEN_ENRXINTR (1 << 0)
133
+
134
+/* REG_MISTA fields */
135
+/* Transmit Bus Error Interrupt */
136
+#define REG_MISTA_TXBERR (1 << 24)
137
+/* Transmit Descriptor Unavailable Interrupt */
138
+#define REG_MISTA_TDU (1 << 23)
139
+/* Transmit Completion Interrupt */
140
+#define REG_MISTA_TXCP (1 << 18)
141
+/* Transmit Interrupt */
142
+#define REG_MISTA_TXINTR (1 << 16)
143
+/* Receive Bus Error Interrupt */
144
+#define REG_MISTA_RXBERR (1 << 11)
145
+/* Receive Descriptor Unavailable Interrupt */
146
+#define REG_MISTA_RDU (1 << 10)
147
+/* DMA Early Notification Interrupt */
148
+#define REG_MISTA_DENI (1 << 9)
149
+/* Maximum Frame Length Interrupt */
150
+#define REG_MISTA_DFOI (1 << 8)
151
+/* Receive Good Interrupt */
152
+#define REG_MISTA_RXGD (1 << 4)
153
+/* Packet Too Long Interrupt */
154
+#define REG_MISTA_PTLE (1 << 3)
155
+/* Receive Interrupt */
156
+#define REG_MISTA_RXINTR (1 << 0)
157
+
158
+typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc;
159
+typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc;
160
+
161
+struct NPCM7xxEMCTxDesc {
162
+ uint32_t flags;
163
+ uint32_t txbsa;
164
+ uint32_t status_and_length;
165
+ uint32_t ntxdsa;
166
+};
167
+
168
+struct NPCM7xxEMCRxDesc {
169
+ uint32_t status_and_length;
170
+ uint32_t rxbsa;
171
+ uint32_t reserved;
172
+ uint32_t nrxdsa;
173
+};
174
+
175
+/* NPCM7xxEMCTxDesc.flags values */
176
+/* Owner: 0 = cpu, 1 = emc */
177
+#define TX_DESC_FLAG_OWNER_MASK (1 << 31)
178
+/* Transmit interrupt enable */
179
+#define TX_DESC_FLAG_INTEN (1 << 2)
180
+
181
+/* NPCM7xxEMCTxDesc.status_and_length values */
182
+/* Transmission complete */
183
+#define TX_DESC_STATUS_TXCP (1 << 19)
184
+/* Transmit interrupt */
185
+#define TX_DESC_STATUS_TXINTR (1 << 16)
186
+
187
+/* NPCM7xxEMCRxDesc.status_and_length values */
188
+/* Owner: 0b00 = cpu, 0b10 = emc */
189
+#define RX_DESC_STATUS_OWNER_SHIFT 30
190
+#define RX_DESC_STATUS_OWNER_MASK 0xc0000000
191
+/* Frame Reception Complete */
192
+#define RX_DESC_STATUS_RXGD (1 << 20)
193
+/* Packet too long */
194
+#define RX_DESC_STATUS_PTLE (1 << 19)
195
+/* Receive Interrupt */
196
+#define RX_DESC_STATUS_RXINTR (1 << 16)
197
+
198
+#define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff)
199
+
200
+typedef struct EMCModule {
201
+ int rx_irq;
202
+ int tx_irq;
203
+ uint64_t base_addr;
204
+} EMCModule;
205
+
206
+typedef struct TestData {
207
+ const EMCModule *module;
208
+} TestData;
209
+
210
+static const EMCModule emc_module_list[] = {
211
+ {
212
+ .rx_irq = 15,
213
+ .tx_irq = 16,
214
+ .base_addr = 0xf0825000
215
+ },
216
+ {
217
+ .rx_irq = 114,
218
+ .tx_irq = 115,
219
+ .base_addr = 0xf0826000
220
+ }
221
+};
222
+
223
+/* Returns the index of the EMC module. */
224
+static int emc_module_index(const EMCModule *mod)
225
+{
226
+ ptrdiff_t diff = mod - emc_module_list;
227
+
228
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list));
229
+
230
+ return diff;
231
+}
232
+
233
+static void packet_test_clear(void *sockets)
234
+{
235
+ int *test_sockets = sockets;
236
+
237
+ close(test_sockets[0]);
238
+ g_free(test_sockets);
239
+}
240
+
241
+static int *packet_test_init(int module_num, GString *cmd_line)
242
+{
243
+ int *test_sockets = g_new(int, 2);
244
+ int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
245
+ g_assert_cmpint(ret, != , -1);
100
+
246
+
101
+ /*
247
+ /*
102
+ * CPU clock and peripheral clocks(APB0, APB1)are configurable
248
+ * KISS and use -nic. We specify two nics (both emc{0,1}) because there's
103
+ * in Libero. CPU clock is divided by APB0 and APB1 divisors for
249
+ * currently no way to specify only emc1: The driver implicitly relies on
104
+ * peripherals. Emcraft's SoM kit comes with these settings by default.
250
+ * emc[i] == nd_table[i].
105
+ */
251
+ */
106
+ qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
252
+ if (module_num == 0) {
107
+ qdev_prop_set_uint32(dev, "apb0div", 2);
253
+ g_string_append_printf(cmd_line,
108
+ qdev_prop_set_uint32(dev, "apb1div", 2);
254
+ " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " "
109
+
255
+ " -nic user,model=" TYPE_NPCM7XX_EMC " ",
110
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
256
+ test_sockets[1]);
111
+
257
+ } else {
112
+ soc = MSF2_SOC(dev);
258
+ g_string_append_printf(cmd_line,
113
+
259
+ " -nic user,model=" TYPE_NPCM7XX_EMC " "
114
+ /* Attach SPI flash to SPI0 controller */
260
+ " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " ",
115
+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
261
+ test_sockets[1]);
116
+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
262
+ }
117
+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
263
+
118
+ if (dinfo) {
264
+ g_test_queue_destroy(packet_test_clear, test_sockets);
119
+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
265
+ return test_sockets;
120
+ &error_fatal);
266
+}
121
+ }
267
+
122
+ qdev_init_nofail(spi_flash);
268
+static uint32_t emc_read(QTestState *qts, const EMCModule *mod,
123
+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
269
+ NPCM7xxPWMRegister regno)
124
+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
270
+{
125
+
271
+ return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t));
126
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
272
+}
127
+ soc->envm_size);
273
+
128
+}
274
+static void emc_write(QTestState *qts, const EMCModule *mod,
129
+
275
+ NPCM7xxPWMRegister regno, uint32_t value)
130
+static void emcraft_sf2_machine_init(MachineClass *mc)
276
+{
131
+{
277
+ qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value);
132
+ mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
278
+}
133
+ mc->init = emcraft_sf2_s2s010_init;
279
+
134
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
280
+static void emc_read_tx_desc(QTestState *qts, uint32_t addr,
135
+}
281
+ NPCM7xxEMCTxDesc *desc)
136
+
282
+{
137
+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
283
+ qtest_memread(qts, addr, desc, sizeof(*desc));
284
+ desc->flags = le32_to_cpu(desc->flags);
285
+ desc->txbsa = le32_to_cpu(desc->txbsa);
286
+ desc->status_and_length = le32_to_cpu(desc->status_and_length);
287
+ desc->ntxdsa = le32_to_cpu(desc->ntxdsa);
288
+}
289
+
290
+static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc,
291
+ uint32_t addr)
292
+{
293
+ NPCM7xxEMCTxDesc le_desc;
294
+
295
+ le_desc.flags = cpu_to_le32(desc->flags);
296
+ le_desc.txbsa = cpu_to_le32(desc->txbsa);
297
+ le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
298
+ le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa);
299
+ qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
300
+}
301
+
302
+static void emc_read_rx_desc(QTestState *qts, uint32_t addr,
303
+ NPCM7xxEMCRxDesc *desc)
304
+{
305
+ qtest_memread(qts, addr, desc, sizeof(*desc));
306
+ desc->status_and_length = le32_to_cpu(desc->status_and_length);
307
+ desc->rxbsa = le32_to_cpu(desc->rxbsa);
308
+ desc->reserved = le32_to_cpu(desc->reserved);
309
+ desc->nrxdsa = le32_to_cpu(desc->nrxdsa);
310
+}
311
+
312
+static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc,
313
+ uint32_t addr)
314
+{
315
+ NPCM7xxEMCRxDesc le_desc;
316
+
317
+ le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
318
+ le_desc.rxbsa = cpu_to_le32(desc->rxbsa);
319
+ le_desc.reserved = cpu_to_le32(desc->reserved);
320
+ le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa);
321
+ qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
322
+}
323
+
324
+/*
325
+ * Reset the EMC module.
326
+ * The module must be reset before, e.g., TXDLSA,RXDLSA are changed.
327
+ */
328
+static bool emc_soft_reset(QTestState *qts, const EMCModule *mod)
329
+{
330
+ uint32_t val;
331
+ uint64_t end_time;
332
+
333
+ emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR);
334
+
335
+ /*
336
+ * Wait for device to reset as the linux driver does.
337
+ * During reset the AHB reads 0 for all registers. So first wait for
338
+ * something that resets to non-zero, and then wait for SWR becoming 0.
339
+ */
340
+ end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
341
+
342
+ do {
343
+ qtest_clock_step(qts, 100);
344
+ val = emc_read(qts, mod, REG_FFTCR);
345
+ } while (val == 0 && g_get_monotonic_time() < end_time);
346
+ if (val != 0) {
347
+ do {
348
+ qtest_clock_step(qts, 100);
349
+ val = emc_read(qts, mod, REG_MCMDR);
350
+ if ((val & REG_MCMDR_SWR) == 0) {
351
+ /*
352
+ * N.B. The CAMs have been reset here, so macaddr matching of
353
+ * incoming packets will not work.
354
+ */
355
+ return true;
356
+ }
357
+ } while (g_get_monotonic_time() < end_time);
358
+ }
359
+
360
+ g_message("%s: Timeout expired", __func__);
361
+ return false;
362
+}
363
+
364
+/* Check emc registers are reset to default value. */
365
+static void test_init(gconstpointer test_data)
366
+{
367
+ const TestData *td = test_data;
368
+ const EMCModule *mod = td->module;
369
+ QTestState *qts = qtest_init("-machine quanta-gsj");
370
+ int i;
371
+
372
+#define CHECK_REG(regno, value) \
373
+ do { \
374
+ g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \
375
+ } while (0)
376
+
377
+ CHECK_REG(REG_CAMCMR, 0);
378
+ CHECK_REG(REG_CAMEN, 0);
379
+ CHECK_REG(REG_TXDLSA, 0xfffffffc);
380
+ CHECK_REG(REG_RXDLSA, 0xfffffffc);
381
+ CHECK_REG(REG_MCMDR, 0);
382
+ CHECK_REG(REG_MIID, 0);
383
+ CHECK_REG(REG_MIIDA, 0x00900000);
384
+ CHECK_REG(REG_FFTCR, 0x0101);
385
+ CHECK_REG(REG_DMARFC, 0x0800);
386
+ CHECK_REG(REG_MIEN, 0);
387
+ CHECK_REG(REG_MISTA, 0);
388
+ CHECK_REG(REG_MGSTA, 0);
389
+ CHECK_REG(REG_MPCNT, 0x7fff);
390
+ CHECK_REG(REG_MRPC, 0);
391
+ CHECK_REG(REG_MRPCC, 0);
392
+ CHECK_REG(REG_MREPC, 0);
393
+ CHECK_REG(REG_DMARFS, 0);
394
+ CHECK_REG(REG_CTXDSA, 0);
395
+ CHECK_REG(REG_CTXBSA, 0);
396
+ CHECK_REG(REG_CRXDSA, 0);
397
+ CHECK_REG(REG_CRXBSA, 0);
398
+
399
+#undef CHECK_REG
400
+
401
+ for (i = 0; i < NUM_CAMML_REGS; ++i) {
402
+ g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==,
403
+ 0);
404
+ g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==,
405
+ 0);
406
+ }
407
+
408
+ qtest_quit(qts);
409
+}
410
+
411
+static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step,
412
+ bool is_tx)
413
+{
414
+ uint64_t end_time =
415
+ g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
416
+
417
+ do {
418
+ if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) {
419
+ return true;
420
+ }
421
+ qtest_clock_step(qts, step);
422
+ } while (g_get_monotonic_time() < end_time);
423
+
424
+ g_message("%s: Timeout expired", __func__);
425
+ return false;
426
+}
427
+
428
+static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step,
429
+ uint32_t flag)
430
+{
431
+ uint64_t end_time =
432
+ g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
433
+
434
+ do {
435
+ uint32_t mista = emc_read(qts, mod, REG_MISTA);
436
+ if (mista & flag) {
437
+ return true;
438
+ }
439
+ qtest_clock_step(qts, step);
440
+ } while (g_get_monotonic_time() < end_time);
441
+
442
+ g_message("%s: Timeout expired", __func__);
443
+ return false;
444
+}
445
+
446
+static bool wait_socket_readable(int fd)
447
+{
448
+ fd_set read_fds;
449
+ struct timeval tv;
450
+ int rv;
451
+
452
+ FD_ZERO(&read_fds);
453
+ FD_SET(fd, &read_fds);
454
+ tv.tv_sec = TIMEOUT_SECONDS;
455
+ tv.tv_usec = 0;
456
+ rv = select(fd + 1, &read_fds, NULL, NULL, &tv);
457
+ if (rv == -1) {
458
+ perror("select");
459
+ } else if (rv == 0) {
460
+ g_message("%s: Timeout expired", __func__);
461
+ }
462
+ return rv == 1;
463
+}
464
+
465
+/* Initialize *desc (in host endian format). */
466
+static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count,
467
+ uint32_t desc_addr)
468
+{
469
+ g_assert(count >= 2);
470
+ memset(&desc[0], 0, sizeof(*desc) * count);
471
+ /* Leave the last one alone, owned by the cpu -> stops transmission. */
472
+ for (size_t i = 0; i < count - 1; ++i) {
473
+ desc[i].flags =
474
+ (TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */
475
+ TX_DESC_FLAG_INTEN |
476
+ 0 | /* crc append = 0 */
477
+ 0 /* padding enable = 0 */);
478
+ desc[i].status_and_length =
479
+ (0 | /* collision count = 0 */
480
+ 0 | /* SQE = 0 */
481
+ 0 | /* PAU = 0 */
482
+ 0 | /* TXHA = 0 */
483
+ 0 | /* LC = 0 */
484
+ 0 | /* TXABT = 0 */
485
+ 0 | /* NCS = 0 */
486
+ 0 | /* EXDEF = 0 */
487
+ 0 | /* TXCP = 0 */
488
+ 0 | /* DEF = 0 */
489
+ 0 | /* TXINTR = 0 */
490
+ 0 /* length filled in later */);
491
+ desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc);
492
+ }
493
+}
494
+
495
+static void enable_tx(QTestState *qts, const EMCModule *mod,
496
+ const NPCM7xxEMCTxDesc *desc, size_t count,
497
+ uint32_t desc_addr, uint32_t mien_flags)
498
+{
499
+ /* Write the descriptors to guest memory. */
500
+ for (size_t i = 0; i < count; ++i) {
501
+ emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
502
+ }
503
+
504
+ /* Trigger sending the packet. */
505
+ /* The module must be reset before changing TXDLSA. */
506
+ g_assert(emc_soft_reset(qts, mod));
507
+ emc_write(qts, mod, REG_TXDLSA, desc_addr);
508
+ emc_write(qts, mod, REG_CTXDSA, ~0);
509
+ emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags);
510
+ {
511
+ uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
512
+ mcmdr |= REG_MCMDR_TXON;
513
+ emc_write(qts, mod, REG_MCMDR, mcmdr);
514
+ }
515
+
516
+ /* Prod the device to send the packet. */
517
+ emc_write(qts, mod, REG_TSDR, 1);
518
+}
519
+
520
+static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd,
521
+ bool with_irq, uint32_t desc_addr,
522
+ uint32_t next_desc_addr,
523
+ const char *test_data, int test_size)
524
+{
525
+ NPCM7xxEMCTxDesc result_desc;
526
+ uint32_t expected_mask, expected_value, recv_len;
527
+ int ret;
528
+ char buffer[TX_DATA_LEN];
529
+
530
+ g_assert(wait_socket_readable(fd));
531
+
532
+ /* Read the descriptor back. */
533
+ emc_read_tx_desc(qts, desc_addr, &result_desc);
534
+ /* Descriptor should be owned by cpu now. */
535
+ g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0);
536
+ /* Test the status bits, ignoring the length field. */
537
+ expected_mask = 0xffff << 16;
538
+ expected_value = TX_DESC_STATUS_TXCP;
539
+ if (with_irq) {
540
+ expected_value |= TX_DESC_STATUS_TXINTR;
541
+ }
542
+ g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
543
+ expected_value);
544
+
545
+ /* Check data sent to the backend. */
546
+ recv_len = ~0;
547
+ ret = qemu_recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT);
548
+ g_assert_cmpint(ret, == , sizeof(recv_len));
549
+
550
+ g_assert(wait_socket_readable(fd));
551
+ memset(buffer, 0xff, sizeof(buffer));
552
+ ret = qemu_recv(fd, buffer, test_size, MSG_DONTWAIT);
553
+ g_assert_cmpmem(buffer, ret, test_data, test_size);
554
+}
555
+
556
+static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd,
557
+ bool with_irq)
558
+{
559
+ NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS];
560
+ uint32_t desc_addr = DESC_ADDR;
561
+ static const char test1_data[] = "TEST1";
562
+ static const char test2_data[] = "Testing 1 2 3 ...";
563
+ uint32_t data1_addr = DATA_ADDR;
564
+ uint32_t data2_addr = data1_addr + sizeof(test1_data);
565
+ bool got_tdu;
566
+ uint32_t end_desc_addr;
567
+
568
+ /* Prepare test data buffer. */
569
+ qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data));
570
+ qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data));
571
+
572
+ init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr);
573
+ desc[0].txbsa = data1_addr;
574
+ desc[0].status_and_length |= sizeof(test1_data);
575
+ desc[1].txbsa = data2_addr;
576
+ desc[1].status_and_length |= sizeof(test2_data);
577
+
578
+ enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr,
579
+ with_irq ? REG_MIEN_ENTXINTR : 0);
580
+
581
+ /*
582
+ * It's problematic to observe the interrupt for each packet.
583
+ * Instead just wait until all the packets go out.
584
+ */
585
+ got_tdu = false;
586
+ while (!got_tdu) {
587
+ if (with_irq) {
588
+ g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT,
589
+ /*is_tx=*/true));
590
+ } else {
591
+ g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT,
592
+ REG_MISTA_TXINTR));
593
+ }
594
+ got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU);
595
+ /* If we don't have TDU yet, reset the interrupt. */
596
+ if (!got_tdu) {
597
+ emc_write(qts, mod, REG_MISTA,
598
+ emc_read(qts, mod, REG_MISTA) & 0xffff0000);
599
+ }
600
+ }
601
+
602
+ end_desc_addr = desc_addr + 2 * sizeof(desc[0]);
603
+ g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr);
604
+ g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==,
605
+ REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU);
606
+
607
+ emc_send_verify1(qts, mod, fd, with_irq,
608
+ desc_addr, end_desc_addr,
609
+ test1_data, sizeof(test1_data));
610
+ emc_send_verify1(qts, mod, fd, with_irq,
611
+ desc_addr + sizeof(desc[0]), end_desc_addr,
612
+ test2_data, sizeof(test2_data));
613
+}
614
+
615
+/* Initialize *desc (in host endian format). */
616
+static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count,
617
+ uint32_t desc_addr, uint32_t data_addr)
618
+{
619
+ g_assert_true(count >= 2);
620
+ memset(desc, 0, sizeof(*desc) * count);
621
+ desc[0].rxbsa = data_addr;
622
+ desc[0].status_and_length =
623
+ (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */
624
+ 0 | /* RP = 0 */
625
+ 0 | /* ALIE = 0 */
626
+ 0 | /* RXGD = 0 */
627
+ 0 | /* PTLE = 0 */
628
+ 0 | /* CRCE = 0 */
629
+ 0 | /* RXINTR = 0 */
630
+ 0 /* length (filled in later) */);
631
+ /* Leave the last one alone, owned by the cpu -> stops transmission. */
632
+ desc[0].nrxdsa = desc_addr + sizeof(*desc);
633
+}
634
+
635
+static void enable_rx(QTestState *qts, const EMCModule *mod,
636
+ const NPCM7xxEMCRxDesc *desc, size_t count,
637
+ uint32_t desc_addr, uint32_t mien_flags,
638
+ uint32_t mcmdr_flags)
639
+{
640
+ /*
641
+ * Write the descriptor to guest memory.
642
+ * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC
643
+ * bytes.
644
+ */
645
+ for (size_t i = 0; i < count; ++i) {
646
+ emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
647
+ }
648
+
649
+ /* Trigger receiving the packet. */
650
+ /* The module must be reset before changing RXDLSA. */
651
+ g_assert(emc_soft_reset(qts, mod));
652
+ emc_write(qts, mod, REG_RXDLSA, desc_addr);
653
+ emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags);
654
+
655
+ /*
656
+ * We don't know what the device's macaddr is, so just accept all
657
+ * unicast packets (AUP).
658
+ */
659
+ emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP);
660
+ emc_write(qts, mod, REG_CAMEN, 1 << 0);
661
+ {
662
+ uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
663
+ mcmdr |= REG_MCMDR_RXON | mcmdr_flags;
664
+ emc_write(qts, mod, REG_MCMDR, mcmdr);
665
+ }
666
+
667
+ /* Prod the device to accept a packet. */
668
+ emc_write(qts, mod, REG_RSDR, 1);
669
+}
670
+
671
+static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd,
672
+ bool with_irq)
673
+{
674
+ NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
675
+ uint32_t desc_addr = DESC_ADDR;
676
+ uint32_t data_addr = DATA_ADDR;
677
+ int ret;
678
+ uint32_t expected_mask, expected_value;
679
+ NPCM7xxEMCRxDesc result_desc;
680
+
681
+ /* Prepare test data buffer. */
682
+ const char test[RX_DATA_LEN] = "TEST";
683
+ int len = htonl(sizeof(test));
684
+ const struct iovec iov[] = {
685
+ {
686
+ .iov_base = &len,
687
+ .iov_len = sizeof(len),
688
+ },{
689
+ .iov_base = (char *) test,
690
+ .iov_len = sizeof(test),
691
+ },
692
+ };
693
+
694
+ /*
695
+ * Reset the device BEFORE sending a test packet, otherwise the packet
696
+ * may get swallowed by an active device of an earlier test.
697
+ */
698
+ init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
699
+ enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
700
+ with_irq ? REG_MIEN_ENRXINTR : 0, 0);
701
+
702
+ /* Send test packet to device's socket. */
703
+ ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test));
704
+ g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
705
+
706
+ /* Wait for RX interrupt. */
707
+ if (with_irq) {
708
+ g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
709
+ } else {
710
+ g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD));
711
+ }
712
+
713
+ g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==,
714
+ desc_addr + sizeof(desc[0]));
715
+
716
+ expected_mask = 0xffff;
717
+ expected_value = (REG_MISTA_DENI |
718
+ REG_MISTA_RXGD |
719
+ REG_MISTA_RXINTR);
720
+ g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask),
721
+ ==, expected_value);
722
+
723
+ /* Read the descriptor back. */
724
+ emc_read_rx_desc(qts, desc_addr, &result_desc);
725
+ /* Descriptor should be owned by cpu now. */
726
+ g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
727
+ /* Test the status bits, ignoring the length field. */
728
+ expected_mask = 0xffff << 16;
729
+ expected_value = RX_DESC_STATUS_RXGD;
730
+ if (with_irq) {
731
+ expected_value |= RX_DESC_STATUS_RXINTR;
732
+ }
733
+ g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
734
+ expected_value);
735
+ g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
736
+ RX_DATA_LEN + CRC_LENGTH);
737
+
738
+ {
739
+ char buffer[RX_DATA_LEN];
740
+ qtest_memread(qts, data_addr, buffer, sizeof(buffer));
741
+ g_assert_cmpstr(buffer, == , "TEST");
742
+ }
743
+}
744
+
745
+static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd)
746
+{
747
+ NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
748
+ uint32_t desc_addr = DESC_ADDR;
749
+ uint32_t data_addr = DATA_ADDR;
750
+ int ret;
751
+ NPCM7xxEMCRxDesc result_desc;
752
+ uint32_t expected_mask, expected_value;
753
+
754
+ /* Prepare test data buffer. */
755
+#define PTLE_DATA_LEN 1600
756
+ char test_data[PTLE_DATA_LEN];
757
+ int len = htonl(sizeof(test_data));
758
+ const struct iovec iov[] = {
759
+ {
760
+ .iov_base = &len,
761
+ .iov_len = sizeof(len),
762
+ },{
763
+ .iov_base = (char *) test_data,
764
+ .iov_len = sizeof(test_data),
765
+ },
766
+ };
767
+ memset(test_data, 42, sizeof(test_data));
768
+
769
+ /*
770
+ * Reset the device BEFORE sending a test packet, otherwise the packet
771
+ * may get swallowed by an active device of an earlier test.
772
+ */
773
+ init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
774
+ enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
775
+ REG_MIEN_ENRXINTR, REG_MCMDR_ALP);
776
+
777
+ /* Send test packet to device's socket. */
778
+ ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data));
779
+ g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len));
780
+
781
+ /* Wait for RX interrupt. */
782
+ g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
783
+
784
+ /* Read the descriptor back. */
785
+ emc_read_rx_desc(qts, desc_addr, &result_desc);
786
+ /* Descriptor should be owned by cpu now. */
787
+ g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
788
+ /* Test the status bits, ignoring the length field. */
789
+ expected_mask = 0xffff << 16;
790
+ expected_value = (RX_DESC_STATUS_RXGD |
791
+ RX_DESC_STATUS_PTLE |
792
+ RX_DESC_STATUS_RXINTR);
793
+ g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
794
+ expected_value);
795
+ g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
796
+ PTLE_DATA_LEN + CRC_LENGTH);
797
+
798
+ {
799
+ char buffer[PTLE_DATA_LEN];
800
+ qtest_memread(qts, data_addr, buffer, sizeof(buffer));
801
+ g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0);
802
+ }
803
+}
804
+
805
+static void test_tx(gconstpointer test_data)
806
+{
807
+ const TestData *td = test_data;
808
+ GString *cmd_line = g_string_new("-machine quanta-gsj");
809
+ int *test_sockets = packet_test_init(emc_module_index(td->module),
810
+ cmd_line);
811
+ QTestState *qts = qtest_init(cmd_line->str);
812
+
813
+ /*
814
+ * TODO: For pedantic correctness test_sockets[0] should be closed after
815
+ * the fork and before the exec, but that will require some harness
816
+ * improvements.
817
+ */
818
+ close(test_sockets[1]);
819
+ /* Defensive programming */
820
+ test_sockets[1] = -1;
821
+
822
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
823
+
824
+ emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);
825
+ emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);
826
+
827
+ qtest_quit(qts);
828
+}
829
+
830
+static void test_rx(gconstpointer test_data)
831
+{
832
+ const TestData *td = test_data;
833
+ GString *cmd_line = g_string_new("-machine quanta-gsj");
834
+ int *test_sockets = packet_test_init(emc_module_index(td->module),
835
+ cmd_line);
836
+ QTestState *qts = qtest_init(cmd_line->str);
837
+
838
+ /*
839
+ * TODO: For pedantic correctness test_sockets[0] should be closed after
840
+ * the fork and before the exec, but that will require some harness
841
+ * improvements.
842
+ */
843
+ close(test_sockets[1]);
844
+ /* Defensive programming */
845
+ test_sockets[1] = -1;
846
+
847
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
848
+
849
+ emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);
850
+ emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);
851
+ emc_test_ptle(qts, td->module, test_sockets[0]);
852
+
853
+ qtest_quit(qts);
854
+}
855
+
856
+static void emc_add_test(const char *name, const TestData* td,
857
+ GTestDataFunc fn)
858
+{
859
+ g_autofree char *full_name = g_strdup_printf(
860
+ "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name);
861
+ qtest_add_data_func(full_name, td, fn);
862
+}
863
+#define add_test(name, td) emc_add_test(#name, td, test_##name)
864
+
865
+int main(int argc, char **argv)
866
+{
867
+ TestData test_data_list[ARRAY_SIZE(emc_module_list)];
868
+
869
+ g_test_init(&argc, &argv, NULL);
870
+
871
+ for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) {
872
+ TestData *td = &test_data_list[i];
873
+
874
+ td->module = &emc_module_list[i];
875
+
876
+ add_test(init, td);
877
+ add_test(tx, td);
878
+ add_test(rx, td);
879
+ }
880
+
881
+ return g_test_run();
882
+}
883
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
884
index XXXXXXX..XXXXXXX 100644
885
--- a/tests/qtest/meson.build
886
+++ b/tests/qtest/meson.build
887
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
888
'npcm7xx_rng-test',
889
'npcm7xx_smbus-test',
890
'npcm7xx_timer-test',
891
- 'npcm7xx_watchdog_timer-test']
892
+ 'npcm7xx_watchdog_timer-test'] + \
893
+ (slirp.found() ? ['npcm7xx_emc-test'] : [])
894
qtests_arm = \
895
(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
896
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
138
--
897
--
139
2.7.4
898
2.20.1
140
899
141
900
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
We hint the 'has_rpu' property is no longer required since commit
4
6908ec448b4 ("xlnx-zynqmp: Properly support the smp command line
5
option") which was released in QEMU v2.11.0.
6
7
Beside, this device is marked 'user_creatable = false', so the
8
only thing that could be setting the property is the board code
9
that creates the device.
10
11
Since the property is not user-facing, we can remove it without
12
going through the deprecation process.
13
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20210219144350.1979905-1-f4bug@amsat.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/arm/xlnx-zynqmp.h | 2 --
20
hw/arm/xlnx-zynqmp.c | 6 ------
21
2 files changed, 8 deletions(-)
22
23
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/arm/xlnx-zynqmp.h
26
+++ b/include/hw/arm/xlnx-zynqmp.h
27
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
28
bool secure;
29
/* Has the ARM Virtualization extensions? */
30
bool virt;
31
- /* Has the RPU subsystem? */
32
- bool has_rpu;
33
34
/* CAN bus. */
35
CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
36
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/xlnx-zynqmp.c
39
+++ b/hw/arm/xlnx-zynqmp.c
40
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
41
}
42
}
43
44
- if (s->has_rpu) {
45
- info_report("The 'has_rpu' property is no longer required, to use the "
46
- "RPUs just use -smp 6.");
47
- }
48
-
49
xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
50
if (err) {
51
error_propagate(errp, err);
52
@@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = {
53
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
54
DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
55
DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
56
- DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
57
DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
58
MemoryRegion *),
59
DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
New patch
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Always perform one call instead of two for 16-byte operands.
4
Use byte loads/stores directly into the vector register file
5
instead of extractions and deposits to a 64-bit local variable.
6
7
In order to easily receive pointers into the vector register file,
8
convert the helper to the gvec out-of-line signature. Move the
9
helper into vec_helper.c, where it can make use of H1 and clear_tail.
10
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Tested-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20210224230532.276878-1-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/helper-a64.h | 2 +-
18
target/arm/helper-a64.c | 32 ---------------------
19
target/arm/translate-a64.c | 58 +++++---------------------------------
20
target/arm/vec_helper.c | 48 +++++++++++++++++++++++++++++++
21
4 files changed, 56 insertions(+), 84 deletions(-)
22
23
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-a64.h
26
+++ b/target/arm/helper-a64.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
28
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
29
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
30
DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr)
31
-DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32)
32
+DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
34
DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
35
DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
36
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/helper-a64.c
39
+++ b/target/arm/helper-a64.c
40
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
41
return float64_mul(a, b, fpst);
42
}
43
44
-uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
45
- uint32_t rn, uint32_t numregs)
46
-{
47
- /* Helper function for SIMD TBL and TBX. We have to do the table
48
- * lookup part for the 64 bits worth of indices we're passed in.
49
- * result is the initial results vector (either zeroes for TBL
50
- * or some guest values for TBX), rn the register number where
51
- * the table starts, and numregs the number of registers in the table.
52
- * We return the results of the lookups.
53
- */
54
- int shift;
55
-
56
- for (shift = 0; shift < 64; shift += 8) {
57
- int index = extract64(indices, shift, 8);
58
- if (index < 16 * numregs) {
59
- /* Convert index (a byte offset into the virtual table
60
- * which is a series of 128-bit vectors concatenated)
61
- * into the correct register element plus a bit offset
62
- * into that element, bearing in mind that the table
63
- * can wrap around from V31 to V0.
64
- */
65
- int elt = (rn * 2 + (index >> 3)) % 64;
66
- int bitidx = (index & 7) * 8;
67
- uint64_t *q = aa64_vfp_qreg(env, elt >> 1);
68
- uint64_t val = extract64(q[elt & 1], bitidx, 8);
69
-
70
- result = deposit64(result, shift, 8, val);
71
- }
72
- }
73
- return result;
74
-}
75
-
76
/* 64bit/double versions of the neon float compare functions */
77
uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
78
{
79
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/arm/translate-a64.c
82
+++ b/target/arm/translate-a64.c
83
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
84
int rm = extract32(insn, 16, 5);
85
int rn = extract32(insn, 5, 5);
86
int rd = extract32(insn, 0, 5);
87
- int is_tblx = extract32(insn, 12, 1);
88
- int len = extract32(insn, 13, 2);
89
- TCGv_i64 tcg_resl, tcg_resh, tcg_idx;
90
- TCGv_i32 tcg_regno, tcg_numregs;
91
+ int is_tbx = extract32(insn, 12, 1);
92
+ int len = (extract32(insn, 13, 2) + 1) * 16;
93
94
if (op2 != 0) {
95
unallocated_encoding(s);
96
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
97
return;
98
}
99
100
- /* This does a table lookup: for every byte element in the input
101
- * we index into a table formed from up to four vector registers,
102
- * and then the output is the result of the lookups. Our helper
103
- * function does the lookup operation for a single 64 bit part of
104
- * the input.
105
- */
106
- tcg_resl = tcg_temp_new_i64();
107
- tcg_resh = NULL;
108
-
109
- if (is_tblx) {
110
- read_vec_element(s, tcg_resl, rd, 0, MO_64);
111
- } else {
112
- tcg_gen_movi_i64(tcg_resl, 0);
113
- }
114
-
115
- if (is_q) {
116
- tcg_resh = tcg_temp_new_i64();
117
- if (is_tblx) {
118
- read_vec_element(s, tcg_resh, rd, 1, MO_64);
119
- } else {
120
- tcg_gen_movi_i64(tcg_resh, 0);
121
- }
122
- }
123
-
124
- tcg_idx = tcg_temp_new_i64();
125
- tcg_regno = tcg_const_i32(rn);
126
- tcg_numregs = tcg_const_i32(len + 1);
127
- read_vec_element(s, tcg_idx, rm, 0, MO_64);
128
- gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,
129
- tcg_regno, tcg_numregs);
130
- if (is_q) {
131
- read_vec_element(s, tcg_idx, rm, 1, MO_64);
132
- gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,
133
- tcg_regno, tcg_numregs);
134
- }
135
- tcg_temp_free_i64(tcg_idx);
136
- tcg_temp_free_i32(tcg_regno);
137
- tcg_temp_free_i32(tcg_numregs);
138
-
139
- write_vec_element(s, tcg_resl, rd, 0, MO_64);
140
- tcg_temp_free_i64(tcg_resl);
141
-
142
- if (is_q) {
143
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
144
- tcg_temp_free_i64(tcg_resh);
145
- }
146
- clear_vec_high(s, is_q, rd);
147
+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
148
+ vec_full_reg_offset(s, rm), cpu_env,
149
+ is_q ? 16 : 8, vec_full_reg_size(s),
150
+ (len << 6) | (is_tbx << 5) | rn,
151
+ gen_helper_simd_tblx);
152
}
153
154
/* ZIP/UZP/TRN
155
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
156
index XXXXXXX..XXXXXXX 100644
157
--- a/target/arm/vec_helper.c
158
+++ b/target/arm/vec_helper.c
159
@@ -XXX,XX +XXX,XX @@ DO_VRINT_RMODE(gvec_vrint_rm_h, helper_rinth, uint16_t)
160
DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32_t)
161
162
#undef DO_VRINT_RMODE
163
+
164
+#ifdef TARGET_AARCH64
165
+void HELPER(simd_tblx)(void *vd, void *vm, void *venv, uint32_t desc)
166
+{
167
+ const uint8_t *indices = vm;
168
+ CPUARMState *env = venv;
169
+ size_t oprsz = simd_oprsz(desc);
170
+ uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5);
171
+ bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1);
172
+ uint32_t table_len = desc >> (SIMD_DATA_SHIFT + 6);
173
+ union {
174
+ uint8_t b[16];
175
+ uint64_t d[2];
176
+ } result;
177
+
178
+ /*
179
+ * We must construct the final result in a temp, lest the output
180
+ * overlaps the input table. For TBL, begin with zero; for TBX,
181
+ * begin with the original register contents. Note that we always
182
+ * copy 16 bytes here to avoid an extra branch; clearing the high
183
+ * bits of the register for oprsz == 8 is handled below.
184
+ */
185
+ if (is_tbx) {
186
+ memcpy(&result, vd, 16);
187
+ } else {
188
+ memset(&result, 0, 16);
189
+ }
190
+
191
+ for (size_t i = 0; i < oprsz; ++i) {
192
+ uint32_t index = indices[H1(i)];
193
+
194
+ if (index < table_len) {
195
+ /*
196
+ * Convert index (a byte offset into the virtual table
197
+ * which is a series of 128-bit vectors concatenated)
198
+ * into the correct register element, bearing in mind
199
+ * that the table can wrap around from V31 to V0.
200
+ */
201
+ const uint8_t *table = (const uint8_t *)
202
+ aa64_vfp_qreg(env, (rn + (index >> 4)) % 32);
203
+ result.b[H1(i)] = table[H1(index % 16)];
204
+ }
205
+ }
206
+
207
+ memcpy(vd, &result, 16);
208
+ clear_tail(vd, oprsz, simd_maxsz(desc));
209
+}
210
+#endif
211
--
212
2.20.1
213
214
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The STATUS register will be reset to IDLE in
4
cnpcm7xx_smbus_enter_reset(), no need to preset
5
it in instance_init().
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Hao Wu <wuhaotsh@google.com>
9
Message-id: 20210228224813.312532-1-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/i2c/npcm7xx_smbus.c | 1 -
13
1 file changed, 1 deletion(-)
14
15
diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/i2c/npcm7xx_smbus.c
18
+++ b/hw/i2c/npcm7xx_smbus.c
19
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_smbus_init(Object *obj)
20
sysbus_init_mmio(sbd, &s->iomem);
21
22
s->bus = i2c_init_bus(DEVICE(s), "i2c-bus");
23
- s->status = NPCM7XX_SMBUS_STATUS_IDLE;
24
}
25
26
static const VMStateDescription vmstate_npcm7xx_smbus = {
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
1
From: schspa <schspa@gmail.com>
1
2
3
At the moment the following QEMU command line triggers an assertion
4
failure On xlnx-versal SOC:
5
qemu-system-aarch64 \
6
-machine xlnx-versal-virt -nographic -smp 2 -m 128 \
7
-fsdev local,id=shareid,path=${HOME}/work,security_model=none \
8
-device virtio-9p-device,fsdev=shareid,mount_tag=share \
9
-fsdev local,id=shareid1,path=${HOME}/Music,security_model=none \
10
-device virtio-9p-device,fsdev=shareid1,mount_tag=share1
11
12
qemu-system-aarch64: ../migration/savevm.c:860:
13
vmstate_register_with_alias_id:
14
Assertion `!se->compat || se->instance_id == 0' failed.
15
16
This problem was fixed on arm virt platform in commit f58b39d2d5b
17
("virtio-mmio: format transport base address in BusClass.get_dev_path")
18
19
It works perfectly on arm virt platform. but there is still there on
20
xlnx-versal SOC.
21
22
The main difference between arm virt and xlnx-versal is they use
23
different way to create virtio-mmio qdev. on arm virt, it calls
24
sysbus_create_simple("virtio-mmio", base, pic[irq]); which will call
25
sysbus_mmio_map internally and assign base address to subsys device
26
mmio correctly. but xlnx-versal's implements won't do this.
27
28
However, xlnx-versal can't switch to sysbus_create_simple() to create
29
virtio-mmio device. It's because xlnx-versal's cpu use
30
VersalVirt.soc.fpd.apu.mr as it's memory. which is subregion of
31
system_memory. sysbus_create_simple will add virtio to system_memory,
32
which can't be accessed by cpu.
33
34
Besides, xlnx-versal can't add sysbus_mmio_map api call too, because
35
this will add memory region to system_memory, and it can't be added
36
to VersalVirt.soc.fpd.apu.mr again.
37
38
We can solve this by assign correct base address offset on dev_path.
39
40
This path was test on aarch64 virt & xlnx-versal platform.
41
42
Signed-off-by: schspa <schspa@gmail.com>
43
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
44
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
45
---
46
hw/virtio/virtio-mmio.c | 13 +++++++------
47
1 file changed, 7 insertions(+), 6 deletions(-)
48
49
diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/virtio/virtio-mmio.c
52
+++ b/hw/virtio/virtio-mmio.c
53
@@ -XXX,XX +XXX,XX @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev)
54
BusState *virtio_mmio_bus;
55
VirtIOMMIOProxy *virtio_mmio_proxy;
56
char *proxy_path;
57
- SysBusDevice *proxy_sbd;
58
char *path;
59
+ MemoryRegionSection section;
60
61
virtio_mmio_bus = qdev_get_parent_bus(dev);
62
virtio_mmio_proxy = VIRTIO_MMIO(virtio_mmio_bus->parent);
63
@@ -XXX,XX +XXX,XX @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev)
64
}
65
66
/* Otherwise, we append the base address of the transport. */
67
- proxy_sbd = SYS_BUS_DEVICE(virtio_mmio_proxy);
68
- assert(proxy_sbd->num_mmio == 1);
69
- assert(proxy_sbd->mmio[0].memory == &virtio_mmio_proxy->iomem);
70
+ section = memory_region_find(&virtio_mmio_proxy->iomem, 0, 0x200);
71
+ assert(section.mr);
72
73
if (proxy_path) {
74
path = g_strdup_printf("%s/virtio-mmio@" TARGET_FMT_plx, proxy_path,
75
- proxy_sbd->mmio[0].addr);
76
+ section.offset_within_address_space);
77
} else {
78
path = g_strdup_printf("virtio-mmio@" TARGET_FMT_plx,
79
- proxy_sbd->mmio[0].addr);
80
+ section.offset_within_address_space);
81
}
82
+ memory_region_unref(section.mr);
83
+
84
g_free(proxy_path);
85
return path;
86
}
87
--
88
2.20.1
89
90
diff view generated by jsdifflib
1
In v8M the MSR and MRS instructions have extra register value
1
From: Peter Collingbourne <pcc@google.com>
2
encodings to allow secure code to access the non-secure banked
3
version of various special registers.
4
2
5
(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because
3
Section D6.7 of the ARM ARM states:
6
we don't currently implement the stack limit registers at all.)
7
4
5
For the purpose of determining Tag Check Fault handling, unprivileged
6
load and store instructions are treated as if executed at EL0 when
7
executed at either:
8
- EL1, when the Effective value of PSTATE.UAO is 0.
9
- EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}
10
and the Effective value of PSTATE.UAO is 0.
11
12
ARM has confirmed a defect in the pseudocode function
13
AArch64.TagCheckFault that makes it inconsistent with the above
14
wording. The remedy is to adjust references to PSTATE.EL in that
15
function to instead refer to AArch64.AccessUsesEL(acctype), so
16
that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1.
17
The exception type for synchronous tag check faults remains unchanged.
18
19
This patch implements the described change by partially reverting
20
commits 50244cc76abc and cc97b0019bb5.
21
22
Signed-off-by: Peter Collingbourne <pcc@google.com>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Message-id: 20210219201820.2672077-1-pcc@google.com
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
11
---
27
---
12
target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++
28
target/arm/helper.c | 2 +-
13
1 file changed, 110 insertions(+)
29
target/arm/mte_helper.c | 13 +++++++++----
30
2 files changed, 10 insertions(+), 5 deletions(-)
14
31
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
34
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
35
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
36
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
20
break;
37
if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
21
case 20: /* CONTROL */
38
&& tbid
22
return env->v7m.control[env->v7m.secure];
39
&& !(env->pstate & PSTATE_TCO)
23
+ case 0x94: /* CONTROL_NS */
40
- && (sctlr & SCTLR_TCF)
24
+ /* We have to handle this here because unprivileged Secure code
41
+ && (sctlr & SCTLR_TCF0)
25
+ * can read the NS CONTROL register.
42
&& allocation_tag_access_enabled(env, 0, sctlr)) {
26
+ */
43
flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
27
+ if (!env->v7m.secure) {
44
}
28
+ return 0;
45
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
29
+ }
46
index XXXXXXX..XXXXXXX 100644
30
+ return env->v7m.control[M_REG_NS];
47
--- a/target/arm/mte_helper.c
48
+++ b/target/arm/mte_helper.c
49
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
50
reg_el = regime_el(env, arm_mmu_idx);
51
sctlr = env->cp15.sctlr_el[reg_el];
52
53
- el = arm_current_el(env);
54
- if (el == 0) {
55
+ switch (arm_mmu_idx) {
56
+ case ARMMMUIdx_E10_0:
57
+ case ARMMMUIdx_E20_0:
58
+ el = 0;
59
tcf = extract64(sctlr, 38, 2);
60
- } else {
61
+ break;
62
+ default:
63
+ el = reg_el;
64
tcf = extract64(sctlr, 40, 2);
31
}
65
}
32
66
33
if (el == 0) {
67
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
34
return 0; /* unprivileged reads others as zero */
68
env->exception.vaddress = dirty_ptr;
35
}
69
36
70
is_write = FIELD_EX32(desc, MTEDESC, WRITE);
37
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
71
- syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11);
38
+ switch (reg) {
72
+ syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0,
39
+ case 0x88: /* MSP_NS */
73
+ is_write, 0x11);
40
+ if (!env->v7m.secure) {
74
raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));
41
+ return 0;
75
/* noreturn, but fall through to the assert anyway */
42
+ }
76
43
+ return env->v7m.other_ss_msp;
44
+ case 0x89: /* PSP_NS */
45
+ if (!env->v7m.secure) {
46
+ return 0;
47
+ }
48
+ return env->v7m.other_ss_psp;
49
+ case 0x90: /* PRIMASK_NS */
50
+ if (!env->v7m.secure) {
51
+ return 0;
52
+ }
53
+ return env->v7m.primask[M_REG_NS];
54
+ case 0x91: /* BASEPRI_NS */
55
+ if (!env->v7m.secure) {
56
+ return 0;
57
+ }
58
+ return env->v7m.basepri[M_REG_NS];
59
+ case 0x93: /* FAULTMASK_NS */
60
+ if (!env->v7m.secure) {
61
+ return 0;
62
+ }
63
+ return env->v7m.faultmask[M_REG_NS];
64
+ case 0x98: /* SP_NS */
65
+ {
66
+ /* This gives the non-secure SP selected based on whether we're
67
+ * currently in handler mode or not, using the NS CONTROL.SPSEL.
68
+ */
69
+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
70
+
71
+ if (!env->v7m.secure) {
72
+ return 0;
73
+ }
74
+ if (!arm_v7m_is_handler_mode(env) && spsel) {
75
+ return env->v7m.other_ss_psp;
76
+ } else {
77
+ return env->v7m.other_ss_msp;
78
+ }
79
+ }
80
+ default:
81
+ break;
82
+ }
83
+ }
84
+
85
switch (reg) {
86
case 8: /* MSP */
87
return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
88
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
89
return;
90
}
91
92
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
93
+ switch (reg) {
94
+ case 0x88: /* MSP_NS */
95
+ if (!env->v7m.secure) {
96
+ return;
97
+ }
98
+ env->v7m.other_ss_msp = val;
99
+ return;
100
+ case 0x89: /* PSP_NS */
101
+ if (!env->v7m.secure) {
102
+ return;
103
+ }
104
+ env->v7m.other_ss_psp = val;
105
+ return;
106
+ case 0x90: /* PRIMASK_NS */
107
+ if (!env->v7m.secure) {
108
+ return;
109
+ }
110
+ env->v7m.primask[M_REG_NS] = val & 1;
111
+ return;
112
+ case 0x91: /* BASEPRI_NS */
113
+ if (!env->v7m.secure) {
114
+ return;
115
+ }
116
+ env->v7m.basepri[M_REG_NS] = val & 0xff;
117
+ return;
118
+ case 0x93: /* FAULTMASK_NS */
119
+ if (!env->v7m.secure) {
120
+ return;
121
+ }
122
+ env->v7m.faultmask[M_REG_NS] = val & 1;
123
+ return;
124
+ case 0x98: /* SP_NS */
125
+ {
126
+ /* This gives the non-secure SP selected based on whether we're
127
+ * currently in handler mode or not, using the NS CONTROL.SPSEL.
128
+ */
129
+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
130
+
131
+ if (!env->v7m.secure) {
132
+ return;
133
+ }
134
+ if (!arm_v7m_is_handler_mode(env) && spsel) {
135
+ env->v7m.other_ss_psp = val;
136
+ } else {
137
+ env->v7m.other_ss_msp = val;
138
+ }
139
+ return;
140
+ }
141
+ default:
142
+ break;
143
+ }
144
+ }
145
+
146
switch (reg) {
147
case 0 ... 7: /* xPSR sub-fields */
148
/* only APSR is actually writable */
149
--
77
--
150
2.7.4
78
2.20.1
151
79
152
80
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
IDAU is specific to M-profile. KVM only supports A-profile.
4
Restrict this interface to TCG, as it is pointless (and
5
confusing) on a KVM-only build.
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210221222617.2579610-2-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.c | 7 -------
14
target/arm/cpu_tcg.c | 8 ++++++++
15
2 files changed, 8 insertions(+), 7 deletions(-)
16
17
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.c
20
+++ b/target/arm/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static const TypeInfo arm_cpu_type_info = {
22
.class_init = arm_cpu_class_init,
23
};
24
25
-static const TypeInfo idau_interface_type_info = {
26
- .name = TYPE_IDAU_INTERFACE,
27
- .parent = TYPE_INTERFACE,
28
- .class_size = sizeof(IDAUInterfaceClass),
29
-};
30
-
31
static void arm_cpu_register_types(void)
32
{
33
const size_t cpu_count = ARRAY_SIZE(arm_cpus);
34
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)
35
if (cpu_count) {
36
size_t i;
37
38
- type_register_static(&idau_interface_type_info);
39
for (i = 0; i < cpu_count; ++i) {
40
arm_cpu_register(&arm_cpus[i]);
41
}
42
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/cpu_tcg.c
45
+++ b/target/arm/cpu_tcg.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "hw/core/tcg-cpu-ops.h"
48
#endif /* CONFIG_TCG */
49
#include "internals.h"
50
+#include "target/arm/idau.h"
51
52
/* CPU models. These are not needed for the AArch64 linux-user build. */
53
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
54
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
55
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
56
};
57
58
+static const TypeInfo idau_interface_type_info = {
59
+ .name = TYPE_IDAU_INTERFACE,
60
+ .parent = TYPE_INTERFACE,
61
+ .class_size = sizeof(IDAUInterfaceClass),
62
+};
63
+
64
static void arm_tcg_cpu_register_types(void)
65
{
66
size_t i;
67
68
+ type_register_static(&idau_interface_type_info);
69
for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
70
arm_cpu_register(&arm_tcg_cpus[i]);
71
}
72
--
73
2.20.1
74
75
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
We will move this code in the next commit. Clean it up
4
first to avoid checkpatch.pl errors.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210221222617.2579610-3-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.c | 12 ++++++++----
12
1 file changed, 8 insertions(+), 4 deletions(-)
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
19
}
20
21
static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
22
- /* power_control should be set to maximum latency. Again,
23
+ /*
24
+ * power_control should be set to maximum latency. Again,
25
* default to 0 and set by private hook
26
*/
27
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
28
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
29
set_feature(&cpu->env, ARM_FEATURE_NEON);
30
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
31
set_feature(&cpu->env, ARM_FEATURE_EL3);
32
- /* Note that A9 supports the MP extensions even for
33
+ /*
34
+ * Note that A9 supports the MP extensions even for
35
* A9UP and single-core A9MP (which are both different
36
* and valid configurations; we don't model A9UP).
37
*/
38
@@ -XXX,XX +XXX,XX @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
39
{
40
MachineState *ms = MACHINE(qdev_get_machine());
41
42
- /* Linux wants the number of processors from here.
43
+ /*
44
+ * Linux wants the number of processors from here.
45
* Might as well set the interrupt-controller bit too.
46
*/
47
return ((ms->smp.cpus - 1) << 24) | (1 << 23);
48
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
49
cpu->isar.id_mmfr1 = 0x40000000;
50
cpu->isar.id_mmfr2 = 0x01240000;
51
cpu->isar.id_mmfr3 = 0x02102211;
52
- /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
53
+ /*
54
+ * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
55
* table 4-41 gives 0x02101110, which includes the arm div insns.
56
*/
57
cpu->isar.id_isar0 = 0x02101110;
58
--
59
2.20.1
60
61
diff view generated by jsdifflib
1
Update nvic_exec_prio() to support the v8M changes:
1
For a long time now the UI layer has guaranteed that the console
2
* BASEPRI, FAULTMASK and PRIMASK are all banked
2
surface is always 32 bits per pixel RGB. Remove the legacy dead
3
* AIRCR.PRIS can affect NS priorities
3
code from the milkymist display device which was handling the
4
* AIRCR.BFHFNMINS affects FAULTMASK behaviour
4
possibility that the console surface was some other format.
5
6
These changes mean that it's no longer possible to
7
definitely say that if FAULTMASK is set it overrides
8
PRIMASK, and if PRIMASK is set it overrides BASEPRI
9
(since if PRIMASK_NS is set and AIRCR.PRIS is set then
10
whether that 0x80 priority should take effect or the
11
priority in BASEPRI_S depends on the value of BASEPRI_S,
12
for instance). So we switch to the same approach used
13
by the pseudocode of working through BASEPRI, PRIMASK
14
and FAULTMASK and overriding the previous values if
15
needed.
16
5
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 1505240046-11454-16-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210215103215.4944-2-peter.maydell@linaro.org
20
---
9
---
21
hw/intc/armv7m_nvic.c | 51 ++++++++++++++++++++++++++++++++++++++++++---------
10
hw/arm/musicpal.c | 64 ++++++++++++++++++-----------------------------
22
1 file changed, 42 insertions(+), 9 deletions(-)
11
1 file changed, 24 insertions(+), 40 deletions(-)
23
12
24
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
13
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/intc/armv7m_nvic.c
15
--- a/hw/arm/musicpal.c
27
+++ b/hw/intc/armv7m_nvic.c
16
+++ b/hw/arm/musicpal.c
28
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
17
@@ -XXX,XX +XXX,XX @@ static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
29
static inline int nvic_exec_prio(NVICState *s)
18
}
30
{
19
}
31
CPUARMState *env = &s->cpu->env;
20
32
- int running;
21
-#define SET_LCD_PIXEL(depth, type) \
33
+ int running = NVIC_NOEXC_PRIO;
22
-static inline void glue(set_lcd_pixel, depth) \
34
23
- (musicpal_lcd_state *s, int x, int y, type col) \
35
- if (env->v7m.faultmask[env->v7m.secure]) {
24
-{ \
36
- running = -1;
25
- int dx, dy; \
37
- } else if (env->v7m.primask[env->v7m.secure]) {
26
- DisplaySurface *surface = qemu_console_surface(s->con); \
38
+ if (env->v7m.basepri[M_REG_NS] > 0) {
27
- type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \
39
+ running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
28
-\
40
+ }
29
- for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
30
- for (dx = 0; dx < 3; dx++, pixel++) \
31
- *pixel = col; \
32
+static inline void set_lcd_pixel32(musicpal_lcd_state *s,
33
+ int x, int y, uint32_t col)
34
+{
35
+ int dx, dy;
36
+ DisplaySurface *surface = qemu_console_surface(s->con);
37
+ uint32_t *pixel =
38
+ &((uint32_t *) surface_data(surface))[(y * 128 * 3 + x) * 3];
41
+
39
+
42
+ if (env->v7m.basepri[M_REG_S] > 0) {
40
+ for (dy = 0; dy < 3; dy++, pixel += 127 * 3) {
43
+ int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
41
+ for (dx = 0; dx < 3; dx++, pixel++) {
44
+ if (running > basepri) {
42
+ *pixel = col;
45
+ running = basepri;
46
+ }
43
+ }
47
+ }
44
+ }
48
+
45
}
49
+ if (env->v7m.primask[M_REG_NS]) {
46
-SET_LCD_PIXEL(8, uint8_t)
50
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
47
-SET_LCD_PIXEL(16, uint16_t)
51
+ if (running > NVIC_NS_PRIO_LIMIT) {
48
-SET_LCD_PIXEL(32, uint32_t)
52
+ running = NVIC_NS_PRIO_LIMIT;
49
53
+ }
50
static void lcd_refresh(void *opaque)
54
+ } else {
51
{
55
+ running = 0;
52
musicpal_lcd_state *s = opaque;
56
+ }
53
- DisplaySurface *surface = qemu_console_surface(s->con);
57
+ }
54
int x, y, col;
58
+
55
59
+ if (env->v7m.primask[M_REG_S]) {
56
- switch (surface_bits_per_pixel(surface)) {
60
running = 0;
57
- case 0:
61
- } else if (env->v7m.basepri[env->v7m.secure] > 0) {
58
- return;
62
- running = env->v7m.basepri[env->v7m.secure] &
59
-#define LCD_REFRESH(depth, func) \
63
- nvic_gprio_mask(s, env->v7m.secure);
60
- case depth: \
64
- } else {
61
- col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
65
- running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
62
- scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
66
}
63
- scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
67
+
64
- for (x = 0; x < 128; x++) { \
68
+ if (env->v7m.faultmask[M_REG_NS]) {
65
- for (y = 0; y < 64; y++) { \
69
+ if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
66
- if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
70
+ running = -1;
67
- glue(set_lcd_pixel, depth)(s, x, y, col); \
71
+ } else {
68
- } else { \
72
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
69
- glue(set_lcd_pixel, depth)(s, x, y, 0); \
73
+ if (running > NVIC_NS_PRIO_LIMIT) {
70
- } \
74
+ running = NVIC_NS_PRIO_LIMIT;
71
- } \
75
+ }
72
- } \
73
- break;
74
- LCD_REFRESH(8, rgb_to_pixel8)
75
- LCD_REFRESH(16, rgb_to_pixel16)
76
- LCD_REFRESH(32, (is_surface_bgr(surface) ?
77
- rgb_to_pixel32bgr : rgb_to_pixel32))
78
- default:
79
- hw_error("unsupported colour depth %i\n",
80
- surface_bits_per_pixel(surface));
81
+ col = rgb_to_pixel32(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff),
82
+ scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff),
83
+ scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff));
84
+ for (x = 0; x < 128; x++) {
85
+ for (y = 0; y < 64; y++) {
86
+ if (s->video_ram[x + (y / 8) * 128] & (1 << (y % 8))) {
87
+ set_lcd_pixel32(s, x, y, col);
76
+ } else {
88
+ } else {
77
+ running = 0;
89
+ set_lcd_pixel32(s, x, y, 0);
78
+ }
90
+ }
79
+ }
91
+ }
80
+ }
92
}
81
+
93
82
+ if (env->v7m.faultmask[M_REG_S]) {
94
dpy_gfx_update(s->con, 0, 0, 128*3, 64*3);
83
+ running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
84
+ }
85
+
86
/* consider priority of active handler */
87
return MIN(running, s->exception_prio);
88
}
89
--
95
--
90
2.7.4
96
2.20.1
91
97
92
98
diff view generated by jsdifflib
1
Update the static_ops functions to use new-style mmio
1
For a long time now the UI layer has guaranteed that the console
2
rather than the legacy old_mmio functions.
2
surface is always 32 bits per pixel RGB. Remove the legacy dead
3
code from the tc6393xb display device which was handling the
4
possibility that the console surface was some other format.
3
5
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505580378-9044-2-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210215103215.4944-3-peter.maydell@linaro.org
7
---
9
---
8
hw/arm/palm.c | 30 ++++++++++--------------------
10
include/ui/console.h | 10 ----------
9
1 file changed, 10 insertions(+), 20 deletions(-)
11
hw/display/tc6393xb.c | 33 +--------------------------------
12
2 files changed, 1 insertion(+), 42 deletions(-)
10
13
11
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
14
diff --git a/include/ui/console.h b/include/ui/console.h
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/palm.c
16
--- a/include/ui/console.h
14
+++ b/hw/arm/palm.c
17
+++ b/include/ui/console.h
15
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ PixelFormat qemu_default_pixelformat(int bpp);
16
#include "exec/address-spaces.h"
19
DisplaySurface *qemu_create_displaysurface(int width, int height);
17
#include "cpu.h"
20
void qemu_free_displaysurface(DisplaySurface *surface);
18
21
19
-static uint32_t static_readb(void *opaque, hwaddr offset)
22
-static inline int is_surface_bgr(DisplaySurface *surface)
20
+static uint64_t static_read(void *opaque, hwaddr offset, unsigned size)
21
{
22
- uint32_t *val = (uint32_t *) opaque;
23
- return *val >> ((offset & 3) << 3);
24
-}
25
+ uint32_t *val = (uint32_t *)opaque;
26
+ uint32_t sizemask = 7 >> size;
27
28
-static uint32_t static_readh(void *opaque, hwaddr offset)
29
-{
23
-{
30
- uint32_t *val = (uint32_t *) opaque;
24
- if (PIXMAN_FORMAT_BPP(surface->format) == 32 &&
31
- return *val >> ((offset & 1) << 3);
25
- PIXMAN_FORMAT_TYPE(surface->format) == PIXMAN_TYPE_ABGR) {
26
- return 1;
27
- } else {
28
- return 0;
29
- }
32
-}
30
-}
33
-
31
-
34
-static uint32_t static_readw(void *opaque, hwaddr offset)
32
static inline int is_buffer_shared(DisplaySurface *surface)
35
-{
33
{
36
- uint32_t *val = (uint32_t *) opaque;
34
return !(surface->flags & QEMU_ALLOCATED_FLAG);
37
- return *val >> ((offset & 0) << 3);
35
diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c
38
+ return *val >> ((offset & sizemask) << 3);
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/display/tc6393xb.c
38
+++ b/hw/display/tc6393xb.c
39
@@ -XXX,XX +XXX,XX @@ static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
40
(uint32_t) addr, value & 0xff);
39
}
41
}
40
42
41
-static void static_write(void *opaque, hwaddr offset,
43
-#define BITS 8
42
- uint32_t value)
44
-#include "tc6393xb_template.h"
43
+static void static_write(void *opaque, hwaddr offset, uint64_t value,
45
-#define BITS 15
44
+ unsigned size)
46
-#include "tc6393xb_template.h"
47
-#define BITS 16
48
-#include "tc6393xb_template.h"
49
-#define BITS 24
50
-#include "tc6393xb_template.h"
51
#define BITS 32
52
#include "tc6393xb_template.h"
53
54
static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
45
{
55
{
46
#ifdef SPY
56
- DisplaySurface *surface = qemu_console_surface(s->con);
47
printf("%s: value %08lx written at " PA_FMT "\n",
57
-
48
@@ -XXX,XX +XXX,XX @@ static void static_write(void *opaque, hwaddr offset,
58
- switch (surface_bits_per_pixel(surface)) {
59
- case 8:
60
- tc6393xb_draw_graphic8(s);
61
- break;
62
- case 15:
63
- tc6393xb_draw_graphic15(s);
64
- break;
65
- case 16:
66
- tc6393xb_draw_graphic16(s);
67
- break;
68
- case 24:
69
- tc6393xb_draw_graphic24(s);
70
- break;
71
- case 32:
72
- tc6393xb_draw_graphic32(s);
73
- break;
74
- default:
75
- printf("tc6393xb: unknown depth %d\n",
76
- surface_bits_per_pixel(surface));
77
- return;
78
- }
79
-
80
+ tc6393xb_draw_graphic32(s);
81
dpy_gfx_update_full(s->con);
49
}
82
}
50
83
51
static const MemoryRegionOps static_ops = {
52
- .old_mmio = {
53
- .read = { static_readb, static_readh, static_readw, },
54
- .write = { static_write, static_write, static_write, },
55
- },
56
+ .read = static_read,
57
+ .write = static_write,
58
+ .valid.min_access_size = 1,
59
+ .valid.max_access_size = 4,
60
.endianness = DEVICE_NATIVE_ENDIAN,
61
};
62
63
--
84
--
64
2.7.4
85
2.20.1
65
86
66
87
diff view generated by jsdifflib
1
Handle banking of SHCSR: some register bits are banked between
1
Now the template header is included only for BITS==32, expand
2
Secure and Non-Secure, and some are only accessible to Secure.
2
out all the macros that depended on the BITS setting.
3
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505240046-11454-19-git-send-email-peter.maydell@linaro.org
6
Message-id: 20210215103215.4944-4-peter.maydell@linaro.org
7
---
7
---
8
hw/intc/armv7m_nvic.c | 221 ++++++++++++++++++++++++++++++++++++++------------
8
hw/display/tc6393xb_template.h | 35 ++++------------------------------
9
1 file changed, 169 insertions(+), 52 deletions(-)
9
1 file changed, 4 insertions(+), 31 deletions(-)
10
10
11
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
11
diff --git a/hw/display/tc6393xb_template.h b/hw/display/tc6393xb_template.h
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/armv7m_nvic.c
13
--- a/hw/display/tc6393xb_template.h
14
+++ b/hw/intc/armv7m_nvic.c
14
+++ b/hw/display/tc6393xb_template.h
15
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
15
@@ -XXX,XX +XXX,XX @@
16
val = cpu->env.v7m.ccr[attrs.secure];
16
* with this program; if not, see <http://www.gnu.org/licenses/>.
17
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
17
*/
18
return val;
18
19
- case 0xd24: /* System Handler Status. */
19
-#if BITS == 8
20
+ case 0xd24: /* System Handler Control and State (SHCSR) */
20
-# define SET_PIXEL(addr, color) (*(uint8_t *)addr = color)
21
val = 0;
21
-#elif BITS == 15 || BITS == 16
22
- if (s->vectors[ARMV7M_EXCP_MEM].active) {
22
-# define SET_PIXEL(addr, color) (*(uint16_t *)addr = color)
23
- val |= (1 << 0);
23
-#elif BITS == 24
24
- }
24
-# define SET_PIXEL(addr, color) \
25
- if (s->vectors[ARMV7M_EXCP_BUS].active) {
25
- do { \
26
- val |= (1 << 1);
26
- addr[0] = color; \
27
- }
27
- addr[1] = (color) >> 8; \
28
- if (s->vectors[ARMV7M_EXCP_USAGE].active) {
28
- addr[2] = (color) >> 16; \
29
- val |= (1 << 3);
29
- } while (0)
30
+ if (attrs.secure) {
30
-#elif BITS == 32
31
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
31
-# define SET_PIXEL(addr, color) (*(uint32_t *)addr = color)
32
+ val |= (1 << 0);
32
-#else
33
+ }
33
-# error unknown bit depth
34
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {
34
-#endif
35
+ val |= (1 << 2);
35
-
36
+ }
36
-
37
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {
37
-static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s)
38
+ val |= (1 << 3);
38
+static void tc6393xb_draw_graphic32(TC6393xbState *s)
39
+ }
39
{
40
+ if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {
40
DisplaySurface *surface = qemu_console_surface(s->con);
41
+ val |= (1 << 7);
41
int i;
42
+ }
42
@@ -XXX,XX +XXX,XX @@ static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s)
43
+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {
43
data_buffer = s->vram_ptr;
44
+ val |= (1 << 10);
44
data_display = surface_data(surface);
45
+ }
45
for(i = 0; i < s->scr_height; i++) {
46
+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {
46
-#if (BITS == 16)
47
+ val |= (1 << 11);
47
- memcpy(data_display, data_buffer, s->scr_width * 2);
48
+ }
48
- data_buffer += s->scr_width;
49
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {
49
- data_display += surface_stride(surface);
50
+ val |= (1 << 12);
50
-#else
51
+ }
51
int j;
52
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {
52
- for (j = 0; j < s->scr_width; j++, data_display += BITS / 8, data_buffer++) {
53
+ val |= (1 << 13);
53
+ for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) {
54
+ }
54
uint16_t color = *data_buffer;
55
+ if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {
55
- uint32_t dest_color = glue(rgb_to_pixel, BITS)(
56
+ val |= (1 << 15);
56
+ uint32_t dest_color = rgb_to_pixel32(
57
+ }
57
((color & 0xf800) * 0x108) >> 11,
58
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {
58
((color & 0x7e0) * 0x41) >> 9,
59
+ val |= (1 << 16);
59
((color & 0x1f) * 0x21) >> 2
60
+ }
60
);
61
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {
61
- SET_PIXEL(data_display, dest_color);
62
+ val |= (1 << 18);
62
+ *(uint32_t *)data_display = dest_color;
63
+ }
64
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {
65
+ val |= (1 << 21);
66
+ }
67
+ /* SecureFault is not banked but is always RAZ/WI to NS */
68
+ if (s->vectors[ARMV7M_EXCP_SECURE].active) {
69
+ val |= (1 << 4);
70
+ }
71
+ if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {
72
+ val |= (1 << 19);
73
+ }
74
+ if (s->vectors[ARMV7M_EXCP_SECURE].pending) {
75
+ val |= (1 << 20);
76
+ }
77
+ } else {
78
+ if (s->vectors[ARMV7M_EXCP_MEM].active) {
79
+ val |= (1 << 0);
80
+ }
81
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
82
+ /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
83
+ if (s->vectors[ARMV7M_EXCP_HARD].active) {
84
+ val |= (1 << 2);
85
+ }
86
+ if (s->vectors[ARMV7M_EXCP_HARD].pending) {
87
+ val |= (1 << 21);
88
+ }
89
+ }
90
+ if (s->vectors[ARMV7M_EXCP_USAGE].active) {
91
+ val |= (1 << 3);
92
+ }
93
+ if (s->vectors[ARMV7M_EXCP_SVC].active) {
94
+ val |= (1 << 7);
95
+ }
96
+ if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
97
+ val |= (1 << 10);
98
+ }
99
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
100
+ val |= (1 << 11);
101
+ }
102
+ if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
103
+ val |= (1 << 12);
104
+ }
105
+ if (s->vectors[ARMV7M_EXCP_MEM].pending) {
106
+ val |= (1 << 13);
107
+ }
108
+ if (s->vectors[ARMV7M_EXCP_SVC].pending) {
109
+ val |= (1 << 15);
110
+ }
111
+ if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
112
+ val |= (1 << 16);
113
+ }
114
+ if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
115
+ val |= (1 << 18);
116
+ }
117
}
63
}
118
- if (s->vectors[ARMV7M_EXCP_SVC].active) {
64
-#endif
119
- val |= (1 << 7);
65
}
120
+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
66
}
121
+ if (s->vectors[ARMV7M_EXCP_BUS].active) {
67
-
122
+ val |= (1 << 1);
68
-#undef BITS
123
+ }
69
-#undef SET_PIXEL
124
+ if (s->vectors[ARMV7M_EXCP_BUS].pending) {
125
+ val |= (1 << 14);
126
+ }
127
+ if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
128
+ val |= (1 << 17);
129
+ }
130
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
131
+ s->vectors[ARMV7M_EXCP_NMI].active) {
132
+ /* NMIACT is not present in v7M */
133
+ val |= (1 << 5);
134
+ }
135
}
136
+
137
+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
138
if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
139
val |= (1 << 8);
140
}
141
- if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
142
- val |= (1 << 10);
143
- }
144
- if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
145
- val |= (1 << 11);
146
- }
147
- if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
148
- val |= (1 << 12);
149
- }
150
- if (s->vectors[ARMV7M_EXCP_MEM].pending) {
151
- val |= (1 << 13);
152
- }
153
- if (s->vectors[ARMV7M_EXCP_BUS].pending) {
154
- val |= (1 << 14);
155
- }
156
- if (s->vectors[ARMV7M_EXCP_SVC].pending) {
157
- val |= (1 << 15);
158
- }
159
- if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
160
- val |= (1 << 16);
161
- }
162
- if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
163
- val |= (1 << 17);
164
- }
165
- if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
166
- val |= (1 << 18);
167
- }
168
return val;
169
case 0xd28: /* Configurable Fault Status. */
170
/* The BFSR bits [15:8] are shared between security states
171
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
172
173
cpu->env.v7m.ccr[attrs.secure] = value;
174
break;
175
- case 0xd24: /* System Handler Control. */
176
- s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
177
- s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
178
- s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
179
- s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
180
+ case 0xd24: /* System Handler Control and State (SHCSR) */
181
+ if (attrs.secure) {
182
+ s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
183
+ /* Secure HardFault active bit cannot be written */
184
+ s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
185
+ s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
186
+ s->sec_vectors[ARMV7M_EXCP_PENDSV].active =
187
+ (value & (1 << 10)) != 0;
188
+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =
189
+ (value & (1 << 11)) != 0;
190
+ s->sec_vectors[ARMV7M_EXCP_USAGE].pending =
191
+ (value & (1 << 12)) != 0;
192
+ s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
193
+ s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
194
+ s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
195
+ s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
196
+ s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
197
+ (value & (1 << 18)) != 0;
198
+ /* SecureFault not banked, but RAZ/WI to NS */
199
+ s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
200
+ s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
201
+ s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;
202
+ } else {
203
+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
204
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
205
+ /* HARDFAULTPENDED is not present in v7M */
206
+ s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
207
+ }
208
+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
209
+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
210
+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
211
+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
212
+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
213
+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
214
+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
215
+ s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
216
+ s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
217
+ }
218
+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
219
+ s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
220
+ s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
221
+ s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
222
+ }
223
+ /* NMIACT can only be written if the write is of a zero, with
224
+ * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
225
+ */
226
+ if (!attrs.secure && cpu->env.v7m.secure &&
227
+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
228
+ (value & (1 << 5)) == 0) {
229
+ s->vectors[ARMV7M_EXCP_NMI].active = 0;
230
+ }
231
+ /* HARDFAULTACT can only be written if the write is of a zero
232
+ * to the non-secure HardFault state by the CPU in secure state.
233
+ * The only case where we can be targeting the non-secure HF state
234
+ * when in secure state is if this is a write via the NS alias
235
+ * and BFHFNMINS is 1.
236
+ */
237
+ if (!attrs.secure && cpu->env.v7m.secure &&
238
+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
239
+ (value & (1 << 2)) == 0) {
240
+ s->vectors[ARMV7M_EXCP_HARD].active = 0;
241
+ }
242
+
243
+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
244
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
245
- s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
246
- s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
247
- s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
248
- s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
249
- s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
250
- s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
251
- s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
252
- s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
253
- s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
254
nvic_irq_update(s);
255
break;
256
case 0xd28: /* Configurable Fault Status. */
257
--
70
--
258
2.7.4
71
2.20.1
259
72
260
73
diff view generated by jsdifflib
1
Update the nvic_recompute_state() code to handle the security
1
The function tc6393xb_draw_graphic32() is called in exactly one place,
2
extension and its associated banked registers.
2
so just inline the function body at its callsite. This allows us to
3
drop the template header entirely.
3
4
4
Code that uses the resulting cached state (ie the irq
5
The code move includes a single added space after 'for' to fix
5
acknowledge and complete code) will be updated in a later
6
the coding style.
6
commit.
7
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20210215103215.4944-5-peter.maydell@linaro.org
11
---
12
---
12
hw/intc/armv7m_nvic.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++--
13
hw/display/tc6393xb_template.h | 45 ----------------------------------
13
hw/intc/trace-events | 1 +
14
hw/display/tc6393xb.c | 23 ++++++++++++++---
14
2 files changed, 147 insertions(+), 5 deletions(-)
15
2 files changed, 19 insertions(+), 49 deletions(-)
16
delete mode 100644 hw/display/tc6393xb_template.h
15
17
16
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
diff --git a/hw/display/tc6393xb_template.h b/hw/display/tc6393xb_template.h
19
deleted file mode 100644
20
index XXXXXXX..XXXXXXX
21
--- a/hw/display/tc6393xb_template.h
22
+++ /dev/null
23
@@ -XXX,XX +XXX,XX @@
24
-/*
25
- * Toshiba TC6393XB I/O Controller.
26
- * Found in Sharp Zaurus SL-6000 (tosa) or some
27
- * Toshiba e-Series PDAs.
28
- *
29
- * FB support code. Based on G364 fb emulator
30
- *
31
- * Copyright (c) 2007 Hervé Poussineau
32
- *
33
- * This program is free software; you can redistribute it and/or
34
- * modify it under the terms of the GNU General Public License as
35
- * published by the Free Software Foundation; either version 2 of
36
- * the License, or (at your option) any later version.
37
- *
38
- * This program is distributed in the hope that it will be useful,
39
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
40
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41
- * GNU General Public License for more details.
42
- *
43
- * You should have received a copy of the GNU General Public License along
44
- * with this program; if not, see <http://www.gnu.org/licenses/>.
45
- */
46
-
47
-static void tc6393xb_draw_graphic32(TC6393xbState *s)
48
-{
49
- DisplaySurface *surface = qemu_console_surface(s->con);
50
- int i;
51
- uint16_t *data_buffer;
52
- uint8_t *data_display;
53
-
54
- data_buffer = s->vram_ptr;
55
- data_display = surface_data(surface);
56
- for(i = 0; i < s->scr_height; i++) {
57
- int j;
58
- for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) {
59
- uint16_t color = *data_buffer;
60
- uint32_t dest_color = rgb_to_pixel32(
61
- ((color & 0xf800) * 0x108) >> 11,
62
- ((color & 0x7e0) * 0x41) >> 9,
63
- ((color & 0x1f) * 0x21) >> 2
64
- );
65
- *(uint32_t *)data_display = dest_color;
66
- }
67
- }
68
-}
69
diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c
17
index XXXXXXX..XXXXXXX 100644
70
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/armv7m_nvic.c
71
--- a/hw/display/tc6393xb.c
19
+++ b/hw/intc/armv7m_nvic.c
72
+++ b/hw/display/tc6393xb.c
20
@@ -XXX,XX +XXX,XX @@
73
@@ -XXX,XX +XXX,XX @@ static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
21
* (higher than the highest possible priority value)
74
(uint32_t) addr, value & 0xff);
22
*/
23
#define NVIC_NOEXC_PRIO 0x100
24
+/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
25
+#define NVIC_NS_PRIO_LIMIT 0x80
26
27
static const uint8_t nvic_id[] = {
28
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
29
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
30
return false;
31
}
75
}
32
76
33
+static bool exc_is_banked(int exc)
77
-#define BITS 32
34
+{
78
-#include "tc6393xb_template.h"
35
+ /* Return true if this is one of the limited set of exceptions which
79
-
36
+ * are banked (and thus have state in sec_vectors[])
80
static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
37
+ */
81
{
38
+ return exc == ARMV7M_EXCP_HARD ||
82
- tc6393xb_draw_graphic32(s);
39
+ exc == ARMV7M_EXCP_MEM ||
83
+ DisplaySurface *surface = qemu_console_surface(s->con);
40
+ exc == ARMV7M_EXCP_USAGE ||
84
+ int i;
41
+ exc == ARMV7M_EXCP_SVC ||
85
+ uint16_t *data_buffer;
42
+ exc == ARMV7M_EXCP_PENDSV ||
86
+ uint8_t *data_display;
43
+ exc == ARMV7M_EXCP_SYSTICK;
44
+}
45
+
87
+
46
/* Return a mask word which clears the subpriority bits from
88
+ data_buffer = s->vram_ptr;
47
* a priority value for an M-profile exception, leaving only
89
+ data_display = surface_data(surface);
48
* the group priority.
90
+ for (i = 0; i < s->scr_height; i++) {
49
*/
91
+ int j;
50
-static inline uint32_t nvic_gprio_mask(NVICState *s)
92
+ for (j = 0; j < s->scr_width; j++, data_display += 4, data_buffer++) {
51
+static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
93
+ uint16_t color = *data_buffer;
52
+{
94
+ uint32_t dest_color = rgb_to_pixel32(
53
+ return ~0U << (s->prigroup[secure] + 1);
95
+ ((color & 0xf800) * 0x108) >> 11,
54
+}
96
+ ((color & 0x7e0) * 0x41) >> 9,
55
+
97
+ ((color & 0x1f) * 0x21) >> 2
56
+static bool exc_targets_secure(NVICState *s, int exc)
98
+ );
57
+{
99
+ *(uint32_t *)data_display = dest_color;
58
+ /* Return true if this non-banked exception targets Secure state. */
59
+ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
60
+ return false;
61
+ }
62
+
63
+ if (exc >= NVIC_FIRST_IRQ) {
64
+ return !s->itns[exc];
65
+ }
66
+
67
+ /* Function shouldn't be called for banked exceptions. */
68
+ assert(!exc_is_banked(exc));
69
+
70
+ switch (exc) {
71
+ case ARMV7M_EXCP_NMI:
72
+ case ARMV7M_EXCP_BUS:
73
+ return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
74
+ case ARMV7M_EXCP_SECURE:
75
+ return true;
76
+ case ARMV7M_EXCP_DEBUG:
77
+ /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
78
+ return false;
79
+ default:
80
+ /* reset, and reserved (unused) low exception numbers.
81
+ * We'll get called by code that loops through all the exception
82
+ * numbers, but it doesn't matter what we return here as these
83
+ * non-existent exceptions will never be pended or active.
84
+ */
85
+ return true;
86
+ }
87
+}
88
+
89
+static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
90
+{
91
+ /* Return the group priority for this exception, given its raw
92
+ * (group-and-subgroup) priority value and whether it is targeting
93
+ * secure state or not.
94
+ */
95
+ if (rawprio < 0) {
96
+ return rawprio;
97
+ }
98
+ rawprio &= nvic_gprio_mask(s, targets_secure);
99
+ /* AIRCR.PRIS causes us to squash all NS priorities into the
100
+ * lower half of the total range
101
+ */
102
+ if (!targets_secure &&
103
+ (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
104
+ rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
105
+ }
106
+ return rawprio;
107
+}
108
+
109
+/* Recompute vectpending and exception_prio for a CPU which implements
110
+ * the Security extension
111
+ */
112
+static void nvic_recompute_state_secure(NVICState *s)
113
{
114
- return ~0U << (s->prigroup[M_REG_NS] + 1);
115
+ int i, bank;
116
+ int pend_prio = NVIC_NOEXC_PRIO;
117
+ int active_prio = NVIC_NOEXC_PRIO;
118
+ int pend_irq = 0;
119
+ bool pending_is_s_banked = false;
120
+
121
+ /* R_CQRV: precedence is by:
122
+ * - lowest group priority; if both the same then
123
+ * - lowest subpriority; if both the same then
124
+ * - lowest exception number; if both the same (ie banked) then
125
+ * - secure exception takes precedence
126
+ * Compare pseudocode RawExecutionPriority.
127
+ * Annoyingly, now we have two prigroup values (for S and NS)
128
+ * we can't do the loop comparison on raw priority values.
129
+ */
130
+ for (i = 1; i < s->num_irq; i++) {
131
+ for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
132
+ VecInfo *vec;
133
+ int prio;
134
+ bool targets_secure;
135
+
136
+ if (bank == M_REG_S) {
137
+ if (!exc_is_banked(i)) {
138
+ continue;
139
+ }
140
+ vec = &s->sec_vectors[i];
141
+ targets_secure = true;
142
+ } else {
143
+ vec = &s->vectors[i];
144
+ targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
145
+ }
146
+
147
+ prio = exc_group_prio(s, vec->prio, targets_secure);
148
+ if (vec->enabled && vec->pending && prio < pend_prio) {
149
+ pend_prio = prio;
150
+ pend_irq = i;
151
+ pending_is_s_banked = (bank == M_REG_S);
152
+ }
153
+ if (vec->active && prio < active_prio) {
154
+ active_prio = prio;
155
+ }
156
+ }
100
+ }
157
+ }
101
+ }
158
+
102
dpy_gfx_update_full(s->con);
159
+ s->vectpending_is_s_banked = pending_is_s_banked;
160
+ s->vectpending = pend_irq;
161
+ s->vectpending_prio = pend_prio;
162
+ s->exception_prio = active_prio;
163
+
164
+ trace_nvic_recompute_state_secure(s->vectpending,
165
+ s->vectpending_is_s_banked,
166
+ s->vectpending_prio,
167
+ s->exception_prio);
168
}
103
}
169
104
170
/* Recompute vectpending and exception_prio */
171
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
172
int active_prio = NVIC_NOEXC_PRIO;
173
int pend_irq = 0;
174
175
+ /* In theory we could write one function that handled both
176
+ * the "security extension present" and "not present"; however
177
+ * the security related changes significantly complicate the
178
+ * recomputation just by themselves and mixing both cases together
179
+ * would be even worse, so we retain a separate non-secure-only
180
+ * version for CPUs which don't implement the security extension.
181
+ */
182
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
183
+ nvic_recompute_state_secure(s);
184
+ return;
185
+ }
186
+
187
for (i = 1; i < s->num_irq; i++) {
188
VecInfo *vec = &s->vectors[i];
189
190
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
191
}
192
193
if (active_prio > 0) {
194
- active_prio &= nvic_gprio_mask(s);
195
+ active_prio &= nvic_gprio_mask(s, false);
196
}
197
198
if (pend_prio > 0) {
199
- pend_prio &= nvic_gprio_mask(s);
200
+ pend_prio &= nvic_gprio_mask(s, false);
201
}
202
203
s->vectpending = pend_irq;
204
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
205
} else if (env->v7m.primask[env->v7m.secure]) {
206
running = 0;
207
} else if (env->v7m.basepri[env->v7m.secure] > 0) {
208
- running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
209
+ running = env->v7m.basepri[env->v7m.secure] &
210
+ nvic_gprio_mask(s, env->v7m.secure);
211
} else {
212
running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
213
}
214
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/intc/trace-events
217
+++ b/hw/intc/trace-events
218
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
219
220
# hw/intc/armv7m_nvic.c
221
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
222
+nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
223
nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
224
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
225
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
226
--
105
--
227
2.7.4
106
2.20.1
228
107
229
108
diff view generated by jsdifflib
1
Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq()
1
The omap_lcdc template header is already only included once, for
2
to handle banked exceptions:
2
DEPTH==32, but it still has all the macro-driven parameterization
3
* acknowledge needs to use the correct vector, which may be
3
for other depths. Expand out all the macros in the header.
4
in sec_vectors[]
5
* acknowledge needs to return to its caller whether the
6
exception should be taken to secure or non-secure state
7
* complete needs its caller to tell it whether the exception
8
being completed is a secure one or not
9
4
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210215103215.4944-6-peter.maydell@linaro.org
13
---
9
---
14
target/arm/cpu.h | 15 +++++++++++++--
10
hw/display/omap_lcd_template.h | 67 ++++++++++++++--------------------
15
hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++++------
11
1 file changed, 28 insertions(+), 39 deletions(-)
16
target/arm/helper.c | 8 +++++---
17
hw/intc/trace-events | 4 ++--
18
4 files changed, 40 insertions(+), 13 deletions(-)
19
12
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h
21
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
15
--- a/hw/display/omap_lcd_template.h
23
+++ b/target/arm/cpu.h
16
+++ b/hw/display/omap_lcd_template.h
24
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
17
@@ -XXX,XX +XXX,XX @@
25
* of architecturally banked exceptions.
18
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
*/
19
*/
27
void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
20
28
-void armv7m_nvic_acknowledge_irq(void *opaque);
21
-#if DEPTH == 32
29
+/**
22
-# define BPP 4
30
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
23
-# define PIXEL_TYPE uint32_t
31
+ * @opaque: the NVIC
24
-#else
32
+ *
25
-# error unsupport depth
33
+ * Move the current highest priority pending exception from the pending
26
-#endif
34
+ * state to the active state, and update v7m.exception to indicate that
27
-
35
+ * it is the exception currently being handled.
28
/*
36
+ *
29
* 2-bit colour
37
+ * Returns: true if exception should be taken to Secure state, false for NS
38
+ */
39
+bool armv7m_nvic_acknowledge_irq(void *opaque);
40
/**
41
* armv7m_nvic_complete_irq: complete specified interrupt or exception
42
* @opaque: the NVIC
43
* @irq: the exception number to complete
44
+ * @secure: true if this exception was secure
45
*
46
* Returns: -1 if the irq was not active
47
* 1 if completing this irq brought us back to base (no active irqs)
48
* 0 if there is still an irq active after this one was completed
49
* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
50
*/
30
*/
51
-int armv7m_nvic_complete_irq(void *opaque, int irq);
31
-static void glue(draw_line2_, DEPTH)(void *opaque,
52
+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
32
- uint8_t *d, const uint8_t *s, int width, int deststep)
53
/**
33
+static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s,
54
* armv7m_nvic_raw_execution_priority: return the raw execution priority
34
+ int width, int deststep)
55
* @opaque: the NVIC
35
{
56
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
36
uint16_t *pal = opaque;
57
index XXXXXXX..XXXXXXX 100644
37
uint8_t v, r, g, b;
58
--- a/hw/intc/armv7m_nvic.c
38
@@ -XXX,XX +XXX,XX @@ static void glue(draw_line2_, DEPTH)(void *opaque,
59
+++ b/hw/intc/armv7m_nvic.c
39
r = (pal[v & 3] >> 4) & 0xf0;
60
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
40
g = pal[v & 3] & 0xf0;
41
b = (pal[v & 3] << 4) & 0xf0;
42
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
43
- d += BPP;
44
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
45
+ d += 4;
46
v >>= 2;
47
r = (pal[v & 3] >> 4) & 0xf0;
48
g = pal[v & 3] & 0xf0;
49
b = (pal[v & 3] << 4) & 0xf0;
50
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
51
- d += BPP;
52
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
53
+ d += 4;
54
v >>= 2;
55
r = (pal[v & 3] >> 4) & 0xf0;
56
g = pal[v & 3] & 0xf0;
57
b = (pal[v & 3] << 4) & 0xf0;
58
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
59
- d += BPP;
60
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
61
+ d += 4;
62
v >>= 2;
63
r = (pal[v & 3] >> 4) & 0xf0;
64
g = pal[v & 3] & 0xf0;
65
b = (pal[v & 3] << 4) & 0xf0;
66
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
67
- d += BPP;
68
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
69
+ d += 4;
70
s ++;
71
width -= 4;
72
} while (width > 0);
73
@@ -XXX,XX +XXX,XX @@ static void glue(draw_line2_, DEPTH)(void *opaque,
74
/*
75
* 4-bit colour
76
*/
77
-static void glue(draw_line4_, DEPTH)(void *opaque,
78
- uint8_t *d, const uint8_t *s, int width, int deststep)
79
+static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s,
80
+ int width, int deststep)
81
{
82
uint16_t *pal = opaque;
83
uint8_t v, r, g, b;
84
@@ -XXX,XX +XXX,XX @@ static void glue(draw_line4_, DEPTH)(void *opaque,
85
r = (pal[v & 0xf] >> 4) & 0xf0;
86
g = pal[v & 0xf] & 0xf0;
87
b = (pal[v & 0xf] << 4) & 0xf0;
88
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
89
- d += BPP;
90
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
91
+ d += 4;
92
v >>= 4;
93
r = (pal[v & 0xf] >> 4) & 0xf0;
94
g = pal[v & 0xf] & 0xf0;
95
b = (pal[v & 0xf] << 4) & 0xf0;
96
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
97
- d += BPP;
98
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
99
+ d += 4;
100
s ++;
101
width -= 2;
102
} while (width > 0);
103
@@ -XXX,XX +XXX,XX @@ static void glue(draw_line4_, DEPTH)(void *opaque,
104
/*
105
* 8-bit colour
106
*/
107
-static void glue(draw_line8_, DEPTH)(void *opaque,
108
- uint8_t *d, const uint8_t *s, int width, int deststep)
109
+static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s,
110
+ int width, int deststep)
111
{
112
uint16_t *pal = opaque;
113
uint8_t v, r, g, b;
114
@@ -XXX,XX +XXX,XX @@ static void glue(draw_line8_, DEPTH)(void *opaque,
115
r = (pal[v] >> 4) & 0xf0;
116
g = pal[v] & 0xf0;
117
b = (pal[v] << 4) & 0xf0;
118
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
119
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
120
s ++;
121
- d += BPP;
122
+ d += 4;
123
} while (-- width != 0);
61
}
124
}
62
125
63
/* Make pending IRQ active. */
126
/*
64
-void armv7m_nvic_acknowledge_irq(void *opaque)
127
* 12-bit colour
65
+bool armv7m_nvic_acknowledge_irq(void *opaque)
128
*/
129
-static void glue(draw_line12_, DEPTH)(void *opaque,
130
- uint8_t *d, const uint8_t *s, int width, int deststep)
131
+static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s,
132
+ int width, int deststep)
66
{
133
{
67
NVICState *s = (NVICState *)opaque;
134
uint16_t v;
68
CPUARMState *env = &s->cpu->env;
135
uint8_t r, g, b;
69
const int pending = s->vectpending;
136
@@ -XXX,XX +XXX,XX @@ static void glue(draw_line12_, DEPTH)(void *opaque,
70
const int running = nvic_exec_prio(s);
137
r = (v >> 4) & 0xf0;
71
VecInfo *vec;
138
g = v & 0xf0;
72
+ bool targets_secure;
139
b = (v << 4) & 0xf0;
73
140
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
74
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
141
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
75
142
s += 2;
76
- vec = &s->vectors[pending];
143
- d += BPP;
77
+ if (s->vectpending_is_s_banked) {
144
+ d += 4;
78
+ vec = &s->sec_vectors[pending];
145
} while (-- width != 0);
79
+ targets_secure = true;
80
+ } else {
81
+ vec = &s->vectors[pending];
82
+ targets_secure = !exc_is_banked(s->vectpending) &&
83
+ exc_targets_secure(s, s->vectpending);
84
+ }
85
86
assert(vec->enabled);
87
assert(vec->pending);
88
89
assert(s->vectpending_prio < running);
90
91
- trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
92
+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio, targets_secure);
93
94
vec->active = 1;
95
vec->pending = 0;
96
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
97
env->v7m.exception = s->vectpending;
98
99
nvic_irq_update(s);
100
+
101
+ return targets_secure;
102
}
146
}
103
147
104
-int armv7m_nvic_complete_irq(void *opaque, int irq)
148
/*
105
+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
149
* 16-bit colour
150
*/
151
-static void glue(draw_line16_, DEPTH)(void *opaque,
152
- uint8_t *d, const uint8_t *s, int width, int deststep)
153
+static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
154
+ int width, int deststep)
106
{
155
{
107
NVICState *s = (NVICState *)opaque;
156
#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
108
VecInfo *vec;
157
memcpy(d, s, width * 2);
109
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq)
158
@@ -XXX,XX +XXX,XX @@ static void glue(draw_line16_, DEPTH)(void *opaque,
110
159
r = (v >> 8) & 0xf8;
111
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
160
g = (v >> 3) & 0xfc;
112
161
b = (v << 3) & 0xf8;
113
- vec = &s->vectors[irq];
162
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
114
+ if (secure && exc_is_banked(irq)) {
163
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
115
+ vec = &s->sec_vectors[irq];
164
s += 2;
116
+ } else {
165
- d += BPP;
117
+ vec = &s->vectors[irq];
166
+ d += 4;
118
+ }
167
} while (-- width != 0);
119
168
#endif
120
- trace_nvic_complete_irq(irq);
169
}
121
+ trace_nvic_complete_irq(irq, secure);
170
-
122
171
-#undef DEPTH
123
if (!vec->active) {
172
-#undef BPP
124
/* Tell the caller this was an illegal exception return */
173
-#undef PIXEL_TYPE
125
diff --git a/target/arm/helper.c b/target/arm/helper.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/target/arm/helper.c
128
+++ b/target/arm/helper.c
129
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
130
bool return_to_sp_process = false;
131
bool return_to_handler = false;
132
bool rettobase = false;
133
+ bool exc_secure = false;
134
135
/* We can only get here from an EXCP_EXCEPTION_EXIT, and
136
* gen_bx_excret() enforces the architectural rule
137
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
138
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
139
*/
140
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
141
- int es = excret & R_V7M_EXCRET_ES_MASK;
142
+ exc_secure = excret & R_V7M_EXCRET_ES_MASK;
143
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
144
- env->v7m.faultmask[es] = 0;
145
+ env->v7m.faultmask[exc_secure] = 0;
146
}
147
} else {
148
env->v7m.faultmask[M_REG_NS] = 0;
149
}
150
}
151
152
- switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {
153
+ switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception,
154
+ exc_secure)) {
155
case -1:
156
/* attempt to exit an exception that isn't active */
157
ufault = true;
158
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
159
index XXXXXXX..XXXXXXX 100644
160
--- a/hw/intc/trace-events
161
+++ b/hw/intc/trace-events
162
@@ -XXX,XX +XXX,XX @@ nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
163
nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
164
nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
165
nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
166
-nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
167
-nvic_complete_irq(int irq) "NVIC complete IRQ %d"
168
+nvic_acknowledge_irq(int irq, int prio, bool targets_secure) "NVIC acknowledge IRQ: %d now active (prio %d targets_secure %d)"
169
+nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
170
nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
171
nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
172
nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
173
--
174
--
174
2.7.4
175
2.20.1
175
176
176
177
diff view generated by jsdifflib
New patch
1
The draw_line16_32() function in the omap_lcdc template header
2
includes an ifdef for the case where HOST_WORDS_BIGENDIAN matches
3
TARGET_WORDS_BIGENDIAN. This is trying to optimise for "source
4
bitmap and destination bitmap format match", but it is broken,
5
because in this function the formats don't match: the source is
6
16-bit colour and the destination is 32-bit colour, so a memcpy()
7
will produce corrupted graphics output. Drop the bogus ifdef.
1
8
9
This bug was introduced in commit ea644cf343129, when we dropped
10
support for DEPTH values other than 32 from the template header.
11
The old #if line was
12
#if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
13
and this was mistakenly changed to
14
#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
15
rather than deleting the #if as now having an always-false condition.
16
17
Fixes: ea644cf343129
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Message-id: 20210215103215.4944-7-peter.maydell@linaro.org
22
---
23
hw/display/omap_lcd_template.h | 4 ----
24
1 file changed, 4 deletions(-)
25
26
diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/display/omap_lcd_template.h
29
+++ b/hw/display/omap_lcd_template.h
30
@@ -XXX,XX +XXX,XX @@ static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s,
31
static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
32
int width, int deststep)
33
{
34
-#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
35
- memcpy(d, s, width * 2);
36
-#else
37
uint16_t v;
38
uint8_t r, g, b;
39
40
@@ -XXX,XX +XXX,XX @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
41
s += 2;
42
d += 4;
43
} while (-- width != 0);
44
-#endif
45
}
46
--
47
2.20.1
48
49
diff view generated by jsdifflib
1
The ICSR NVIC register is banked for v8M. This doesn't
1
Fix some minor coding style issues in the template header,
2
require any new state, but it does mean that some bits
2
so checkpatch doesn't complain when we move the code.
3
are controlled by BFHNFNMINS and some bits must work
4
with the correct banked exception. There is also a new
5
in v8M PENDNMICLR bit.
6
3
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 1505240046-11454-18-git-send-email-peter.maydell@linaro.org
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210215103215.4944-8-peter.maydell@linaro.org
10
---
8
---
11
hw/intc/armv7m_nvic.c | 45 ++++++++++++++++++++++++++++++++-------------
9
hw/display/omap_lcd_template.h | 6 +++---
12
1 file changed, 32 insertions(+), 13 deletions(-)
10
1 file changed, 3 insertions(+), 3 deletions(-)
13
11
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
12
diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
14
--- a/hw/display/omap_lcd_template.h
17
+++ b/hw/intc/armv7m_nvic.c
15
+++ b/hw/display/omap_lcd_template.h
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
16
@@ -XXX,XX +XXX,XX @@ static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s,
19
}
17
b = (pal[v & 3] << 4) & 0xf0;
20
case 0xd00: /* CPUID Base. */
18
((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
21
return cpu->midr;
19
d += 4;
22
- case 0xd04: /* Interrupt Control State. */
20
- s ++;
23
+ case 0xd04: /* Interrupt Control State (ICSR) */
21
+ s++;
24
/* VECTACTIVE */
22
width -= 4;
25
val = cpu->env.v7m.exception;
23
} while (width > 0);
26
/* VECTPENDING */
24
}
27
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
25
@@ -XXX,XX +XXX,XX @@ static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s,
28
if (nvic_rettobase(s)) {
26
b = (pal[v & 0xf] << 4) & 0xf0;
29
val |= (1 << 11);
27
((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
30
}
28
d += 4;
31
- /* PENDSTSET */
29
- s ++;
32
- if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
30
+ s++;
33
- val |= (1 << 26);
31
width -= 2;
34
- }
32
} while (width > 0);
35
- /* PENDSVSET */
33
}
36
- if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
34
@@ -XXX,XX +XXX,XX @@ static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s,
37
- val |= (1 << 28);
35
g = pal[v] & 0xf0;
38
+ if (attrs.secure) {
36
b = (pal[v] << 4) & 0xf0;
39
+ /* PENDSTSET */
37
((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
40
+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {
38
- s ++;
41
+ val |= (1 << 26);
39
+ s++;
42
+ }
40
d += 4;
43
+ /* PENDSVSET */
41
} while (-- width != 0);
44
+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {
42
}
45
+ val |= (1 << 28);
46
+ }
47
+ } else {
48
+ /* PENDSTSET */
49
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
50
+ val |= (1 << 26);
51
+ }
52
+ /* PENDSVSET */
53
+ if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
54
+ val |= (1 << 28);
55
+ }
56
}
57
/* NMIPENDSET */
58
- if (s->vectors[ARMV7M_EXCP_NMI].pending) {
59
+ if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
60
+ s->vectors[ARMV7M_EXCP_NMI].pending) {
61
val |= (1 << 31);
62
}
63
- /* ISRPREEMPT not implemented */
64
+ /* ISRPREEMPT: RES0 when halting debug not implemented */
65
+ /* STTNS: RES0 for the Main Extension */
66
return val;
67
case 0xd08: /* Vector Table Offset. */
68
return cpu->env.v7m.vecbase[attrs.secure];
69
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
70
nvic_irq_update(s);
71
break;
72
}
73
- case 0xd04: /* Interrupt Control State. */
74
- if (value & (1 << 31)) {
75
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
76
+ case 0xd04: /* Interrupt Control State (ICSR) */
77
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
78
+ if (value & (1 << 31)) {
79
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
80
+ } else if (value & (1 << 30) &&
81
+ arm_feature(&cpu->env, ARM_FEATURE_V8)) {
82
+ /* PENDNMICLR didn't exist in v7M */
83
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false);
84
+ }
85
}
86
if (value & (1 << 28)) {
87
armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
88
--
43
--
89
2.7.4
44
2.20.1
90
45
91
46
diff view generated by jsdifflib
1
Update the code in nvic_rettobase() so that it checks the
1
We only include the template header once, so just inline it into the
2
sec_vectors[] array as well as the vectors[] array if needed.
2
source file for the device.
3
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505240046-11454-7-git-send-email-peter.maydell@linaro.org
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210215103215.4944-9-peter.maydell@linaro.org
7
---
8
---
8
hw/intc/armv7m_nvic.c | 5 ++++-
9
hw/display/omap_lcd_template.h | 154 ---------------------------------
9
1 file changed, 4 insertions(+), 1 deletion(-)
10
hw/display/omap_lcdc.c | 127 ++++++++++++++++++++++++++-
11
2 files changed, 125 insertions(+), 156 deletions(-)
12
delete mode 100644 hw/display/omap_lcd_template.h
10
13
11
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
14
diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h
15
deleted file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- a/hw/display/omap_lcd_template.h
18
+++ /dev/null
19
@@ -XXX,XX +XXX,XX @@
20
-/*
21
- * QEMU OMAP LCD Emulator templates
22
- *
23
- * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
24
- *
25
- * Redistribution and use in source and binary forms, with or without
26
- * modification, are permitted provided that the following conditions
27
- * are met:
28
- *
29
- * 1. Redistributions of source code must retain the above copyright
30
- * notice, this list of conditions and the following disclaimer.
31
- * 2. Redistributions in binary form must reproduce the above copyright
32
- * notice, this list of conditions and the following disclaimer in
33
- * the documentation and/or other materials provided with the
34
- * distribution.
35
- *
36
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
37
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
38
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
39
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
40
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
41
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
42
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
43
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
44
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47
- */
48
-
49
-/*
50
- * 2-bit colour
51
- */
52
-static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s,
53
- int width, int deststep)
54
-{
55
- uint16_t *pal = opaque;
56
- uint8_t v, r, g, b;
57
-
58
- do {
59
- v = ldub_p((void *) s);
60
- r = (pal[v & 3] >> 4) & 0xf0;
61
- g = pal[v & 3] & 0xf0;
62
- b = (pal[v & 3] << 4) & 0xf0;
63
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
64
- d += 4;
65
- v >>= 2;
66
- r = (pal[v & 3] >> 4) & 0xf0;
67
- g = pal[v & 3] & 0xf0;
68
- b = (pal[v & 3] << 4) & 0xf0;
69
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
70
- d += 4;
71
- v >>= 2;
72
- r = (pal[v & 3] >> 4) & 0xf0;
73
- g = pal[v & 3] & 0xf0;
74
- b = (pal[v & 3] << 4) & 0xf0;
75
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
76
- d += 4;
77
- v >>= 2;
78
- r = (pal[v & 3] >> 4) & 0xf0;
79
- g = pal[v & 3] & 0xf0;
80
- b = (pal[v & 3] << 4) & 0xf0;
81
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
82
- d += 4;
83
- s++;
84
- width -= 4;
85
- } while (width > 0);
86
-}
87
-
88
-/*
89
- * 4-bit colour
90
- */
91
-static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s,
92
- int width, int deststep)
93
-{
94
- uint16_t *pal = opaque;
95
- uint8_t v, r, g, b;
96
-
97
- do {
98
- v = ldub_p((void *) s);
99
- r = (pal[v & 0xf] >> 4) & 0xf0;
100
- g = pal[v & 0xf] & 0xf0;
101
- b = (pal[v & 0xf] << 4) & 0xf0;
102
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
103
- d += 4;
104
- v >>= 4;
105
- r = (pal[v & 0xf] >> 4) & 0xf0;
106
- g = pal[v & 0xf] & 0xf0;
107
- b = (pal[v & 0xf] << 4) & 0xf0;
108
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
109
- d += 4;
110
- s++;
111
- width -= 2;
112
- } while (width > 0);
113
-}
114
-
115
-/*
116
- * 8-bit colour
117
- */
118
-static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s,
119
- int width, int deststep)
120
-{
121
- uint16_t *pal = opaque;
122
- uint8_t v, r, g, b;
123
-
124
- do {
125
- v = ldub_p((void *) s);
126
- r = (pal[v] >> 4) & 0xf0;
127
- g = pal[v] & 0xf0;
128
- b = (pal[v] << 4) & 0xf0;
129
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
130
- s++;
131
- d += 4;
132
- } while (-- width != 0);
133
-}
134
-
135
-/*
136
- * 12-bit colour
137
- */
138
-static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s,
139
- int width, int deststep)
140
-{
141
- uint16_t v;
142
- uint8_t r, g, b;
143
-
144
- do {
145
- v = lduw_le_p((void *) s);
146
- r = (v >> 4) & 0xf0;
147
- g = v & 0xf0;
148
- b = (v << 4) & 0xf0;
149
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
150
- s += 2;
151
- d += 4;
152
- } while (-- width != 0);
153
-}
154
-
155
-/*
156
- * 16-bit colour
157
- */
158
-static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
159
- int width, int deststep)
160
-{
161
- uint16_t v;
162
- uint8_t r, g, b;
163
-
164
- do {
165
- v = lduw_le_p((void *) s);
166
- r = (v >> 8) & 0xf8;
167
- g = (v >> 3) & 0xfc;
168
- b = (v << 3) & 0xf8;
169
- ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
170
- s += 2;
171
- d += 4;
172
- } while (-- width != 0);
173
-}
174
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
12
index XXXXXXX..XXXXXXX 100644
175
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/armv7m_nvic.c
176
--- a/hw/display/omap_lcdc.c
14
+++ b/hw/intc/armv7m_nvic.c
177
+++ b/hw/display/omap_lcdc.c
15
@@ -XXX,XX +XXX,XX @@ static int nvic_pending_prio(NVICState *s)
178
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
16
static bool nvic_rettobase(NVICState *s)
179
180
#define draw_line_func drawfn
181
182
-#define DEPTH 32
183
-#include "omap_lcd_template.h"
184
+/*
185
+ * 2-bit colour
186
+ */
187
+static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s,
188
+ int width, int deststep)
189
+{
190
+ uint16_t *pal = opaque;
191
+ uint8_t v, r, g, b;
192
+
193
+ do {
194
+ v = ldub_p((void *) s);
195
+ r = (pal[v & 3] >> 4) & 0xf0;
196
+ g = pal[v & 3] & 0xf0;
197
+ b = (pal[v & 3] << 4) & 0xf0;
198
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
199
+ d += 4;
200
+ v >>= 2;
201
+ r = (pal[v & 3] >> 4) & 0xf0;
202
+ g = pal[v & 3] & 0xf0;
203
+ b = (pal[v & 3] << 4) & 0xf0;
204
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
205
+ d += 4;
206
+ v >>= 2;
207
+ r = (pal[v & 3] >> 4) & 0xf0;
208
+ g = pal[v & 3] & 0xf0;
209
+ b = (pal[v & 3] << 4) & 0xf0;
210
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
211
+ d += 4;
212
+ v >>= 2;
213
+ r = (pal[v & 3] >> 4) & 0xf0;
214
+ g = pal[v & 3] & 0xf0;
215
+ b = (pal[v & 3] << 4) & 0xf0;
216
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
217
+ d += 4;
218
+ s++;
219
+ width -= 4;
220
+ } while (width > 0);
221
+}
222
+
223
+/*
224
+ * 4-bit colour
225
+ */
226
+static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s,
227
+ int width, int deststep)
228
+{
229
+ uint16_t *pal = opaque;
230
+ uint8_t v, r, g, b;
231
+
232
+ do {
233
+ v = ldub_p((void *) s);
234
+ r = (pal[v & 0xf] >> 4) & 0xf0;
235
+ g = pal[v & 0xf] & 0xf0;
236
+ b = (pal[v & 0xf] << 4) & 0xf0;
237
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
238
+ d += 4;
239
+ v >>= 4;
240
+ r = (pal[v & 0xf] >> 4) & 0xf0;
241
+ g = pal[v & 0xf] & 0xf0;
242
+ b = (pal[v & 0xf] << 4) & 0xf0;
243
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
244
+ d += 4;
245
+ s++;
246
+ width -= 2;
247
+ } while (width > 0);
248
+}
249
+
250
+/*
251
+ * 8-bit colour
252
+ */
253
+static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s,
254
+ int width, int deststep)
255
+{
256
+ uint16_t *pal = opaque;
257
+ uint8_t v, r, g, b;
258
+
259
+ do {
260
+ v = ldub_p((void *) s);
261
+ r = (pal[v] >> 4) & 0xf0;
262
+ g = pal[v] & 0xf0;
263
+ b = (pal[v] << 4) & 0xf0;
264
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
265
+ s++;
266
+ d += 4;
267
+ } while (-- width != 0);
268
+}
269
+
270
+/*
271
+ * 12-bit colour
272
+ */
273
+static void draw_line12_32(void *opaque, uint8_t *d, const uint8_t *s,
274
+ int width, int deststep)
275
+{
276
+ uint16_t v;
277
+ uint8_t r, g, b;
278
+
279
+ do {
280
+ v = lduw_le_p((void *) s);
281
+ r = (v >> 4) & 0xf0;
282
+ g = v & 0xf0;
283
+ b = (v << 4) & 0xf0;
284
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
285
+ s += 2;
286
+ d += 4;
287
+ } while (-- width != 0);
288
+}
289
+
290
+/*
291
+ * 16-bit colour
292
+ */
293
+static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
294
+ int width, int deststep)
295
+{
296
+ uint16_t v;
297
+ uint8_t r, g, b;
298
+
299
+ do {
300
+ v = lduw_le_p((void *) s);
301
+ r = (v >> 8) & 0xf8;
302
+ g = (v >> 3) & 0xfc;
303
+ b = (v << 3) & 0xf8;
304
+ ((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);
305
+ s += 2;
306
+ d += 4;
307
+ } while (-- width != 0);
308
+}
309
310
static void omap_update_display(void *opaque)
17
{
311
{
18
int irq, nhand = 0;
19
+ bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
20
21
for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
22
- if (s->vectors[irq].active) {
23
+ if (s->vectors[irq].active ||
24
+ (check_sec && irq < NVIC_INTERNAL_VECTORS &&
25
+ s->sec_vectors[irq].active)) {
26
nhand++;
27
if (nhand == 2) {
28
return 0;
29
--
312
--
30
2.7.4
313
2.20.1
31
314
32
315
diff view generated by jsdifflib
1
When escalating to HardFault, we must go into Lockup if we
1
The macro draw_line_func is used only once; just expand it.
2
can't take the synchronous HardFault because the current
3
execution priority is already at or below the priority of
4
HardFault. In v7M HF is always priority -1 so a simple < 0
5
comparison sufficed; in v8M the priority of HardFault can
6
vary depending on whether it is a Secure or NonSecure
7
HardFault, so we must check against the priority of the
8
HardFault exception vector we're about to use.
9
2
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-13-git-send-email-peter.maydell@linaro.org
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20210215103215.4944-10-peter.maydell@linaro.org
13
---
7
---
14
hw/intc/armv7m_nvic.c | 23 ++++++++++++-----------
8
hw/display/omap_lcdc.c | 4 +---
15
1 file changed, 12 insertions(+), 11 deletions(-)
9
1 file changed, 1 insertion(+), 3 deletions(-)
16
10
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
11
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
18
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
13
--- a/hw/display/omap_lcdc.c
20
+++ b/hw/intc/armv7m_nvic.c
14
+++ b/hw/display/omap_lcdc.c
21
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
15
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
22
}
16
qemu_irq_lower(s->irq);
23
17
}
24
if (escalate) {
18
25
- if (running < 0) {
19
-#define draw_line_func drawfn
26
- /* We want to escalate to HardFault but we can't take a
20
-
27
- * synchronous HardFault at this point either. This is a
21
/*
28
- * Lockup condition due to a guest bug. We don't model
22
* 2-bit colour
29
- * Lockup, so report via cpu_abort() instead.
23
*/
30
- */
24
@@ -XXX,XX +XXX,XX @@ static void omap_update_display(void *opaque)
31
- cpu_abort(&s->cpu->parent_obj,
25
{
32
- "Lockup: can't escalate %d to HardFault "
26
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
33
- "(current priority %d)\n", irq, running);
27
DisplaySurface *surface;
34
- }
28
- draw_line_func draw_line;
35
29
+ drawfn draw_line;
36
- /* We can do the escalation, so we take HardFault instead.
30
int size, height, first, last;
37
+ /* We need to escalate this exception to a synchronous HardFault.
31
int width, linesize, step, bpp, frame_offset;
38
* If BFHFNMINS is set then we escalate to the banked HF for
32
hwaddr frame_base;
39
* the target security state of the original exception; otherwise
40
* we take a Secure HardFault.
41
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
42
} else {
43
vec = &s->vectors[irq];
44
}
45
+ if (running <= vec->prio) {
46
+ /* We want to escalate to HardFault but we can't take the
47
+ * synchronous HardFault at this point either. This is a
48
+ * Lockup condition due to a guest bug. We don't model
49
+ * Lockup, so report via cpu_abort() instead.
50
+ */
51
+ cpu_abort(&s->cpu->parent_obj,
52
+ "Lockup: can't escalate %d to HardFault "
53
+ "(current priority %d)\n", irq, running);
54
+ }
55
+
56
/* HF may be banked but there is only one shared HFSR */
57
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
58
}
59
--
33
--
60
2.7.4
34
2.20.1
61
35
62
36
diff view generated by jsdifflib
New patch
1
For a long time now the UI layer has guaranteed that the console
2
surface is always 32 bits per pixel, RGB. The TCX code already
3
assumes 32bpp, but it still has some checks of is_surface_bgr()
4
in an attempt to support 32bpp BGR. is_surface_bgr() will always
5
return false for the qemu_console_surface(), unless the display
6
device itself has deliberately created an alternate-format
7
surface via a function like qemu_create_displaysurface_from().
1
8
9
Drop the never-used BGR-handling code, and assert that we have
10
a 32-bit surface rather than just doing nothing if it isn't.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20210215102149.20513-1-peter.maydell@linaro.org
16
---
17
hw/display/tcx.c | 31 ++++++++-----------------------
18
1 file changed, 8 insertions(+), 23 deletions(-)
19
20
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/display/tcx.c
23
+++ b/hw/display/tcx.c
24
@@ -XXX,XX +XXX,XX @@ static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap,
25
26
static void update_palette_entries(TCXState *s, int start, int end)
27
{
28
- DisplaySurface *surface = qemu_console_surface(s->con);
29
int i;
30
31
for (i = start; i < end; i++) {
32
- if (is_surface_bgr(surface)) {
33
- s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
34
- } else {
35
- s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
36
- }
37
+ s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
38
}
39
tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
40
}
41
@@ -XXX,XX +XXX,XX @@ static void tcx_draw_cursor32(TCXState *s1, uint8_t *d,
42
}
43
44
/*
45
- XXX Could be much more optimal:
46
- * detect if line/page/whole screen is in 24 bit mode
47
- * if destination is also BGR, use memcpy
48
- */
49
+ * XXX Could be much more optimal:
50
+ * detect if line/page/whole screen is in 24 bit mode
51
+ */
52
static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
53
const uint8_t *s, int width,
54
const uint32_t *cplane,
55
const uint32_t *s24)
56
{
57
- DisplaySurface *surface = qemu_console_surface(s1->con);
58
- int x, bgr, r, g, b;
59
+ int x, r, g, b;
60
uint8_t val, *p8;
61
uint32_t *p = (uint32_t *)d;
62
uint32_t dval;
63
- bgr = is_surface_bgr(surface);
64
for(x = 0; x < width; x++, s++, s24++) {
65
if (be32_to_cpu(*cplane) & 0x03000000) {
66
/* 24-bit direct, BGR order */
67
@@ -XXX,XX +XXX,XX @@ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
68
b = *p8++;
69
g = *p8++;
70
r = *p8;
71
- if (bgr)
72
- dval = rgb_to_pixel32bgr(r, g, b);
73
- else
74
- dval = rgb_to_pixel32(r, g, b);
75
+ dval = rgb_to_pixel32(r, g, b);
76
} else {
77
/* 8-bit pseudocolor */
78
val = *s;
79
@@ -XXX,XX +XXX,XX @@ static void tcx_update_display(void *opaque)
80
int y, y_start, dd, ds;
81
uint8_t *d, *s;
82
83
- if (surface_bits_per_pixel(surface) != 32) {
84
- return;
85
- }
86
+ assert(surface_bits_per_pixel(surface) == 32);
87
88
page = 0;
89
y_start = -1;
90
@@ -XXX,XX +XXX,XX @@ static void tcx24_update_display(void *opaque)
91
uint8_t *d, *s;
92
uint32_t *cptr, *s24;
93
94
- if (surface_bits_per_pixel(surface) != 32) {
95
- return;
96
- }
97
+ assert(surface_bits_per_pixel(surface) == 32);
98
99
page = 0;
100
y_start = -1;
101
--
102
2.20.1
103
104
diff view generated by jsdifflib
New patch
1
The AN524 has a different SYSCLK frequency from the AN505 and AN521;
2
make the SYSCLK frequency a field in the MPS2TZMachineClass rather
3
than a compile-time constant so we can support the AN524.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210215115138.20465-2-peter.maydell@linaro.org
9
---
10
hw/arm/mps2-tz.c | 10 ++++++----
11
1 file changed, 6 insertions(+), 4 deletions(-)
12
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/mps2-tz.c
16
+++ b/hw/arm/mps2-tz.c
17
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
18
MachineClass parent;
19
MPS2TZFPGAType fpga_type;
20
uint32_t scc_id;
21
+ uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
22
const char *armsse_type;
23
};
24
25
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
26
27
OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
28
29
-/* Main SYSCLK frequency in Hz */
30
-#define SYSCLK_FRQ 20000000
31
/* Slow 32Khz S32KCLK frequency in Hz */
32
#define S32KCLK_FRQ (32 * 1000)
33
34
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
35
static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
36
const char *name, hwaddr size)
37
{
38
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
39
CMSDKAPBUART *uart = opaque;
40
int i = uart - &mms->uart[0];
41
int rxirqno = i * 2;
42
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
43
44
object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART);
45
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
46
- qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
47
+ qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq);
48
sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
49
s = SYS_BUS_DEVICE(uart);
50
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno));
51
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
52
53
/* These clocks don't need migration because they are fixed-frequency */
54
mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
55
- clock_set_hz(mms->sysclk, SYSCLK_FRQ);
56
+ clock_set_hz(mms->sysclk, mmc->sysclk_frq);
57
mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
58
clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
59
60
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
61
mmc->fpga_type = FPGA_AN505;
62
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
63
mmc->scc_id = 0x41045050;
64
+ mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
65
mmc->armsse_type = TYPE_IOTKIT;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
69
mmc->fpga_type = FPGA_AN521;
70
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
71
mmc->scc_id = 0x41045210;
72
+ mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
73
mmc->armsse_type = TYPE_SSE200;
74
}
75
76
--
77
2.20.1
78
79
diff view generated by jsdifflib
1
The Application Interrupt and Reset Control Register has some changes
1
Currently the MPS2 SCC device implements a fixed number of OSCCLK
2
for v8M:
2
values (3). The variant of this device in the MPS3 AN524 board has 6
3
* new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
3
OSCCLK values. Switch to using a PROP_ARRAY, which allows board code
4
real state if the security extension is implemented and otherwise
4
to specify how large the OSCCLK array should be as well as its
5
are constant
5
values.
6
* the PRIGROUP field is banked between security states
7
* non-secure code can be blocked from using the SYSRESET bit
8
to reset the system if SYSRESETREQS is set
9
6
10
Implement the new state and the changes to register read and write.
7
With a variable-length property array, the SCC no longer specifies
11
For the moment we ignore the effects of the secure PRIGROUP.
8
default values for the OSCCLKs, so we must set them explicitly in the
12
We will implement the effects of PRIS and BFHFNMIS later.
9
board code. This defaults are actually incorrect for the an521 and
10
an505; we will correct this bug in a following patch.
11
12
This is a migration compatibility break for all the mps boards.
13
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
17
Message-id: 20210215115138.20465-3-peter.maydell@linaro.org
17
---
18
---
18
include/hw/intc/armv7m_nvic.h | 3 ++-
19
include/hw/misc/mps2-scc.h | 7 +++----
19
target/arm/cpu.h | 12 +++++++++++
20
hw/arm/mps2-tz.c | 5 +++++
20
hw/intc/armv7m_nvic.c | 49 +++++++++++++++++++++++++++++++++----------
21
hw/arm/mps2.c | 5 +++++
21
target/arm/cpu.c | 7 +++++++
22
hw/misc/mps2-scc.c | 24 +++++++++++++-----------
22
4 files changed, 59 insertions(+), 12 deletions(-)
23
4 files changed, 26 insertions(+), 15 deletions(-)
23
24
24
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
25
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
25
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/intc/armv7m_nvic.h
27
--- a/include/hw/misc/mps2-scc.h
27
+++ b/include/hw/intc/armv7m_nvic.h
28
+++ b/include/hw/misc/mps2-scc.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
29
@@ -XXX,XX +XXX,XX @@
29
* Entries in sec_vectors[] for non-banked exception numbers are unused.
30
#define TYPE_MPS2_SCC "mps2-scc"
30
*/
31
OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC)
31
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
32
32
- uint32_t prigroup;
33
-#define NUM_OSCCLK 3
33
+ /* The PRIGROUP field in AIRCR is banked */
34
-
34
+ uint32_t prigroup[M_REG_NUM_BANKS];
35
struct MPS2SCC {
35
36
/*< private >*/
36
/* The following fields are all cached state that can be recalculated
37
SysBusDevice parent_obj;
37
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
38
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
38
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
39
uint32_t dll;
40
uint32_t aid;
41
uint32_t id;
42
- uint32_t oscclk[NUM_OSCCLK];
43
- uint32_t oscclk_reset[NUM_OSCCLK];
44
+ uint32_t num_oscclk;
45
+ uint32_t *oscclk;
46
+ uint32_t *oscclk_reset;
47
};
48
49
#endif
50
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
39
index XXXXXXX..XXXXXXX 100644
51
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu.h
52
--- a/hw/arm/mps2-tz.c
41
+++ b/target/arm/cpu.h
53
+++ b/hw/arm/mps2-tz.c
42
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
54
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
43
int exception;
55
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
44
uint32_t primask[M_REG_NUM_BANKS];
56
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
45
uint32_t faultmask[M_REG_NUM_BANKS];
57
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
46
+ uint32_t aircr; /* only holds r/w state if security extn implemented */
58
+ /* This will need to be per-FPGA image eventually */
47
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
59
+ qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
48
} v7m;
60
+ qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000);
49
61
+ qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000);
50
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1)
62
+ qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
51
FIELD(V7M_CCR, DC, 16, 1)
63
sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
52
FIELD(V7M_CCR, IC, 17, 1)
64
return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
53
65
}
54
+/* V7M AIRCR bits */
66
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
55
+FIELD(V7M_AIRCR, VECTRESET, 0, 1)
67
index XXXXXXX..XXXXXXX 100644
56
+FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
68
--- a/hw/arm/mps2.c
57
+FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
69
+++ b/hw/arm/mps2.c
58
+FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
70
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
59
+FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
71
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
60
+FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
72
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
61
+FIELD(V7M_AIRCR, PRIS, 14, 1)
73
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
62
+FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
74
+ /* All these FPGA images have the same OSCCLK configuration */
63
+FIELD(V7M_AIRCR, VECTKEY, 16, 16)
75
+ qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
76
+ qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000);
77
+ qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000);
78
+ qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
79
sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
80
sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
81
object_initialize_child(OBJECT(mms), "fpgaio",
82
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/misc/mps2-scc.c
85
+++ b/hw/misc/mps2-scc.c
86
@@ -XXX,XX +XXX,XX @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function,
87
{
88
trace_mps2_scc_cfg_write(function, device, value);
89
90
- if (function != 1 || device >= NUM_OSCCLK) {
91
+ if (function != 1 || device >= s->num_oscclk) {
92
qemu_log_mask(LOG_GUEST_ERROR,
93
"MPS2 SCC config write: bad function %d device %d\n",
94
function, device);
95
@@ -XXX,XX +XXX,XX @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function,
96
static bool scc_cfg_read(MPS2SCC *s, unsigned function,
97
unsigned device, uint32_t *value)
98
{
99
- if (function != 1 || device >= NUM_OSCCLK) {
100
+ if (function != 1 || device >= s->num_oscclk) {
101
qemu_log_mask(LOG_GUEST_ERROR,
102
"MPS2 SCC config read: bad function %d device %d\n",
103
function, device);
104
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_reset(DeviceState *dev)
105
s->cfgctrl = 0x100000;
106
s->cfgstat = 0;
107
s->dll = 0xffff0001;
108
- for (i = 0; i < NUM_OSCCLK; i++) {
109
+ for (i = 0; i < s->num_oscclk; i++) {
110
s->oscclk[i] = s->oscclk_reset[i];
111
}
112
for (i = 0; i < ARRAY_SIZE(s->led); i++) {
113
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_realize(DeviceState *dev, Error **errp)
114
LED_COLOR_GREEN, name);
115
g_free(name);
116
}
64
+
117
+
65
/* V7M CFSR bits for MMFSR */
118
+ s->oscclk = g_new0(uint32_t, s->num_oscclk);
66
FIELD(V7M_CFSR, IACCVIOL, 0, 1)
67
FIELD(V7M_CFSR, DACCVIOL, 1, 1)
68
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/intc/armv7m_nvic.c
71
+++ b/hw/intc/armv7m_nvic.c
72
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
73
*/
74
static inline uint32_t nvic_gprio_mask(NVICState *s)
75
{
76
- return ~0U << (s->prigroup + 1);
77
+ return ~0U << (s->prigroup[M_REG_NS] + 1);
78
}
119
}
79
120
80
/* Recompute vectpending and exception_prio */
121
static const VMStateDescription mps2_scc_vmstate = {
81
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
122
.name = "mps2-scc",
82
return val;
123
- .version_id = 1,
83
case 0xd08: /* Vector Table Offset. */
124
- .minimum_version_id = 1,
84
return cpu->env.v7m.vecbase[attrs.secure];
125
+ .version_id = 2,
85
- case 0xd0c: /* Application Interrupt/Reset Control. */
126
+ .minimum_version_id = 2,
86
- return 0xfa050000 | (s->prigroup << 8);
87
+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
88
+ val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);
89
+ if (attrs.secure) {
90
+ /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
91
+ val |= cpu->env.v7m.aircr;
92
+ } else {
93
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
94
+ /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
95
+ * security isn't supported then BFHFNMINS is RAO (and
96
+ * the bit in env.v7m.aircr is always set).
97
+ */
98
+ val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
99
+ }
100
+ }
101
+ return val;
102
case 0xd10: /* System Control. */
103
/* TODO: Implement SLEEPONEXIT. */
104
return 0;
105
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
106
case 0xd08: /* Vector Table Offset. */
107
cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
108
break;
109
- case 0xd0c: /* Application Interrupt/Reset Control. */
110
- if ((value >> 16) == 0x05fa) {
111
- if (value & 4) {
112
- qemu_irq_pulse(s->sysresetreq);
113
+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
114
+ if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
115
+ if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
116
+ if (attrs.secure ||
117
+ !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
118
+ qemu_irq_pulse(s->sysresetreq);
119
+ }
120
}
121
- if (value & 2) {
122
+ if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
123
qemu_log_mask(LOG_GUEST_ERROR,
124
"Setting VECTCLRACTIVE when not in DEBUG mode "
125
"is UNPREDICTABLE\n");
126
}
127
- if (value & 1) {
128
+ if (value & R_V7M_AIRCR_VECTRESET_MASK) {
129
+ /* NB: this bit is RES0 in v8M */
130
qemu_log_mask(LOG_GUEST_ERROR,
131
"Setting VECTRESET when not in DEBUG mode "
132
"is UNPREDICTABLE\n");
133
}
134
- s->prigroup = extract32(value, 8, 3);
135
+ s->prigroup[attrs.secure] = extract32(value,
136
+ R_V7M_AIRCR_PRIGROUP_SHIFT,
137
+ R_V7M_AIRCR_PRIGROUP_LENGTH);
138
+ if (attrs.secure) {
139
+ /* These bits are only writable by secure */
140
+ cpu->env.v7m.aircr = value &
141
+ (R_V7M_AIRCR_SYSRESETREQS_MASK |
142
+ R_V7M_AIRCR_BFHFNMINS_MASK |
143
+ R_V7M_AIRCR_PRIS_MASK);
144
+ }
145
nvic_irq_update(s);
146
}
147
break;
148
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
149
.fields = (VMStateField[]) {
127
.fields = (VMStateField[]) {
150
VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
128
VMSTATE_UINT32(cfg0, MPS2SCC),
151
vmstate_VecInfo, VecInfo),
129
VMSTATE_UINT32(cfg1, MPS2SCC),
152
+ VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
130
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
131
VMSTATE_UINT32(cfgctrl, MPS2SCC),
132
VMSTATE_UINT32(cfgstat, MPS2SCC),
133
VMSTATE_UINT32(dll, MPS2SCC),
134
- VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK),
135
+ VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
136
+ 0, vmstate_info_uint32, uint32_t),
153
VMSTATE_END_OF_LIST()
137
VMSTATE_END_OF_LIST()
154
}
138
}
155
};
139
};
156
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
140
@@ -XXX,XX +XXX,XX @@ static Property mps2_scc_properties[] = {
157
.fields = (VMStateField[]) {
141
DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
158
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
142
DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
159
vmstate_VecInfo, VecInfo),
143
DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
160
- VMSTATE_UINT32(prigroup, NVICState),
144
- /* These are the initial settings for the source clocks on the board.
161
+ VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),
145
+ /*
162
VMSTATE_END_OF_LIST()
146
+ * These are the initial settings for the source clocks on the board.
163
},
147
* In hardware they can be configured via a config file read by the
164
.subsections = (const VMStateDescription*[]) {
148
* motherboard configuration controller to suit the FPGA image.
165
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
149
- * These default values are used by most of the standard FPGA images.
166
index XXXXXXX..XXXXXXX 100644
150
*/
167
--- a/target/arm/cpu.c
151
- DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000),
168
+++ b/target/arm/cpu.c
152
- DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000),
169
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
153
- DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000),
170
154
+ DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset,
171
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
155
+ qdev_prop_uint32, uint32_t),
172
env->v7m.secure = true;
156
DEFINE_PROP_END_OF_LIST(),
173
+ } else {
157
};
174
+ /* This bit resets to 0 if security is supported, but 1 if
158
175
+ * it is not. The bit is not present in v7M, but we set it
176
+ * here so we can avoid having to make checks on it conditional
177
+ * on ARM_FEATURE_V8 (we don't let the guest see the bit).
178
+ */
179
+ env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
180
}
181
182
/* In v7M the reset value of this bit is IMPDEF, but ARM recommends
183
--
159
--
184
2.7.4
160
2.20.1
185
161
186
162
diff view generated by jsdifflib
New patch
1
We were previously using the default OSCCLK settings, which are
2
correct for the older MPS2 boards (mps2-an385, mps2-an386,
3
mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511
4
implemented in mps2-tz.c. Now we're setting the values explicitly we
5
can fix them to be correct.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210215115138.20465-4-peter.maydell@linaro.org
11
---
12
hw/arm/mps2-tz.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/mps2-tz.c
18
+++ b/hw/arm/mps2-tz.c
19
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
20
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
21
/* This will need to be per-FPGA image eventually */
22
qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
23
- qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000);
24
- qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000);
25
+ qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000);
26
+ qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000);
27
qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
28
sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
29
return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
1
For the v8M security extension, some exceptions must be banked
1
The AN505 and AN511 happen to share the same OSCCLK values, but the
2
between security states. Add the new vecinfo array which holds
2
AN524 will have a different set (and more of them), so split the
3
the state for the banked exceptions and migrate it if the
3
settings out to be per-board.
4
CPU the NVIC is attached to implements the security extension.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210215115138.20465-5-peter.maydell@linaro.org
8
---
9
---
9
include/hw/intc/armv7m_nvic.h | 14 ++++++++++++
10
hw/arm/mps2-tz.c | 23 ++++++++++++++++++-----
10
hw/intc/armv7m_nvic.c | 53 ++++++++++++++++++++++++++++++++++++++++++-
11
1 file changed, 18 insertions(+), 5 deletions(-)
11
2 files changed, 66 insertions(+), 1 deletion(-)
12
12
13
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/armv7m_nvic.h
15
--- a/hw/arm/mps2-tz.c
16
+++ b/include/hw/intc/armv7m_nvic.h
16
+++ b/hw/arm/mps2-tz.c
17
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
18
18
MPS2TZFPGAType fpga_type;
19
/* Highest permitted number of exceptions (architectural limit) */
19
uint32_t scc_id;
20
#define NVIC_MAX_VECTORS 512
20
uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
21
+/* Number of internal exceptions */
21
+ uint32_t len_oscclk;
22
+#define NVIC_INTERNAL_VECTORS 16
22
+ const uint32_t *oscclk;
23
23
const char *armsse_type;
24
typedef struct VecInfo {
25
/* Exception priorities can range from -3 to 255; only the unmodifiable
26
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
27
ARMCPU *cpu;
28
29
VecInfo vectors[NVIC_MAX_VECTORS];
30
+ /* If the v8M security extension is implemented, some of the internal
31
+ * exceptions are banked between security states (ie there exists both
32
+ * a Secure and a NonSecure version of the exception and its state):
33
+ * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
34
+ * The rest (including all the external exceptions) are not banked, though
35
+ * they may be configurable to target either Secure or NonSecure state.
36
+ * We store the secure exception state in sec_vectors[] for the banked
37
+ * exceptions, and otherwise use only vectors[] (including for exceptions
38
+ * like SecureFault that unconditionally target Secure state).
39
+ * Entries in sec_vectors[] for non-banked exception numbers are unused.
40
+ */
41
+ VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
42
uint32_t prigroup;
43
44
/* vectpending and exception_prio are both cached state that can
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
49
@@ -XXX,XX +XXX,XX @@
50
* For historical reasons QEMU tends to use "interrupt" and
51
* "exception" more or less interchangeably.
52
*/
53
-#define NVIC_FIRST_IRQ 16
54
+#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
55
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
56
57
/* Effective running priority of the CPU when no exception is active
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
59
}
60
};
24
};
61
25
62
+static bool nvic_security_needed(void *opaque)
26
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
63
+{
27
/* Slow 32Khz S32KCLK frequency in Hz */
64
+ NVICState *s = opaque;
28
#define S32KCLK_FRQ (32 * 1000)
65
+
29
66
+ return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
30
+static const uint32_t an505_oscclk[] = {
67
+}
31
+ 40000000,
68
+
32
+ 24580000,
69
+static int nvic_security_post_load(void *opaque, int version_id)
33
+ 25000000,
70
+{
71
+ NVICState *s = opaque;
72
+ int i;
73
+
74
+ /* Check for out of range priority settings */
75
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
76
+ return 1;
77
+ }
78
+ for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
79
+ if (s->sec_vectors[i].prio & ~0xff) {
80
+ return 1;
81
+ }
82
+ }
83
+ return 0;
84
+}
85
+
86
+static const VMStateDescription vmstate_nvic_security = {
87
+ .name = "nvic/m-security",
88
+ .version_id = 1,
89
+ .minimum_version_id = 1,
90
+ .needed = nvic_security_needed,
91
+ .post_load = &nvic_security_post_load,
92
+ .fields = (VMStateField[]) {
93
+ VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
94
+ vmstate_VecInfo, VecInfo),
95
+ VMSTATE_END_OF_LIST()
96
+ }
97
+};
34
+};
98
+
35
+
99
static const VMStateDescription vmstate_nvic = {
36
/* Create an alias of an entire original MemoryRegion @orig
100
.name = "armv7m_nvic",
37
* located at @base in the memory map.
101
.version_id = 4,
38
*/
102
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
39
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
103
vmstate_VecInfo, VecInfo),
40
MPS2SCC *scc = opaque;
104
VMSTATE_UINT32(prigroup, NVICState),
41
DeviceState *sccdev;
105
VMSTATE_END_OF_LIST()
42
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
106
+ },
43
+ uint32_t i;
107
+ .subsections = (const VMStateDescription*[]) {
44
108
+ &vmstate_nvic_security,
45
object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
109
+ NULL
46
sccdev = DEVICE(scc);
110
}
47
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
111
};
48
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
112
49
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
113
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
50
- /* This will need to be per-FPGA image eventually */
114
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
51
- qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
115
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
52
- qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000);
116
53
- qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000);
117
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
54
- qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
118
+ s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;
55
+ qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk);
119
+ s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;
56
+ for (i = 0; i < mmc->len_oscclk; i++) {
120
+ s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
57
+ g_autofree char *propname = g_strdup_printf("oscclk[%u]", i);
121
+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
58
+ qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]);
122
+
123
+ /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
124
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
125
+ }
59
+ }
126
+
60
sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
127
/* Strictly speaking the reset handler should be enabled.
61
return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
128
* However, we don't simulate soft resets through the NVIC,
62
}
129
* and the reset vector should never be pended.
63
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
64
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
65
mmc->scc_id = 0x41045050;
66
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
67
+ mmc->oscclk = an505_oscclk;
68
+ mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
69
mmc->armsse_type = TYPE_IOTKIT;
70
}
71
72
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
73
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
74
mmc->scc_id = 0x41045210;
75
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
76
+ mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */
77
+ mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
78
mmc->armsse_type = TYPE_SSE200;
79
}
80
130
--
81
--
131
2.7.4
82
2.20.1
132
83
133
84
diff view generated by jsdifflib
1
Drop the use of old_mmio in the omap2_gpio memory ops.
1
The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The
2
FPGAIO device is similar on both sets of boards, but the LED0
3
register has correspondingly more bits that have an effect. Add a
4
device property for number of LEDs.
2
5
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-3-git-send-email-peter.maydell@linaro.org
9
Message-id: 20210215115138.20465-6-peter.maydell@linaro.org
6
---
10
---
7
hw/gpio/omap_gpio.c | 26 ++++++++++++--------------
11
include/hw/misc/mps2-fpgaio.h | 5 ++++-
8
1 file changed, 12 insertions(+), 14 deletions(-)
12
hw/misc/mps2-fpgaio.c | 31 +++++++++++++++++++++++--------
13
2 files changed, 27 insertions(+), 9 deletions(-)
9
14
10
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
15
diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h
11
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/gpio/omap_gpio.c
17
--- a/include/hw/misc/mps2-fpgaio.h
13
+++ b/hw/gpio/omap_gpio.c
18
+++ b/include/hw/misc/mps2-fpgaio.h
14
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_write(void *opaque, hwaddr addr,
19
@@ -XXX,XX +XXX,XX @@
20
#define TYPE_MPS2_FPGAIO "mps2-fpgaio"
21
OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO)
22
23
+#define MPS2FPGAIO_MAX_LEDS 32
24
+
25
struct MPS2FPGAIO {
26
/*< private >*/
27
SysBusDevice parent_obj;
28
29
/*< public >*/
30
MemoryRegion iomem;
31
- LEDState *led[2];
32
+ LEDState *led[MPS2FPGAIO_MAX_LEDS];
33
+ uint32_t num_leds;
34
35
uint32_t led0;
36
uint32_t prescale;
37
diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/misc/mps2-fpgaio.c
40
+++ b/hw/misc/mps2-fpgaio.c
41
@@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value,
42
43
switch (offset) {
44
case A_LED0:
45
- s->led0 = value & 0x3;
46
- led_set_state(s->led[0], value & 0x01);
47
- led_set_state(s->led[1], value & 0x02);
48
+ if (s->num_leds != 0) {
49
+ uint32_t i;
50
+
51
+ s->led0 = value & MAKE_64BIT_MASK(0, s->num_leds);
52
+ for (i = 0; i < s->num_leds; i++) {
53
+ led_set_state(s->led[i], value & (1 << i));
54
+ }
55
+ }
56
break;
57
case A_PRESCALE:
58
resync_counter(s);
59
@@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_reset(DeviceState *dev)
60
s->pscntr = 0;
61
s->pscntr_sync_ticks = now;
62
63
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
64
+ for (size_t i = 0; i < s->num_leds; i++) {
65
device_cold_reset(DEVICE(s->led[i]));
15
}
66
}
16
}
67
}
17
68
@@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_init(Object *obj)
18
-static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
69
static void mps2_fpgaio_realize(DeviceState *dev, Error **errp)
19
+static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
20
+ unsigned size)
21
{
70
{
22
return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
71
MPS2FPGAIO *s = MPS2_FPGAIO(dev);
23
}
72
+ uint32_t i;
24
73
25
static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
74
- s->led[0] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH,
26
- uint32_t value)
75
- LED_COLOR_GREEN, "USERLED0");
27
+ uint64_t value, unsigned size)
76
- s->led[1] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH,
28
{
77
- LED_COLOR_GREEN, "USERLED1");
29
uint32_t cur = 0;
78
+ if (s->num_leds > MPS2FPGAIO_MAX_LEDS) {
30
uint32_t mask = 0xffff;
79
+ error_setg(errp, "num-leds cannot be greater than %d",
31
80
+ MPS2FPGAIO_MAX_LEDS);
32
+ if (size == 4) {
33
+ omap2_gpio_module_write(opaque, addr, value);
34
+ return;
81
+ return;
35
+ }
82
+ }
36
+
83
+
37
switch (addr & ~3) {
84
+ for (i = 0; i < s->num_leds; i++) {
38
case 0x00:    /* GPIO_REVISION */
85
+ g_autofree char *ledname = g_strdup_printf("USERLED%d", i);
39
case 0x14:    /* GPIO_SYSSTATUS */
86
+ s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH,
40
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
87
+ LED_COLOR_GREEN, ledname);
88
+ }
41
}
89
}
42
90
43
static const MemoryRegionOps omap2_gpio_module_ops = {
91
static bool mps2_fpgaio_counters_needed(void *opaque)
44
- .old_mmio = {
92
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_fpgaio_vmstate = {
45
- .read = {
93
static Property mps2_fpgaio_properties[] = {
46
- omap2_gpio_module_readp,
94
/* Frequency of the prescale counter */
47
- omap2_gpio_module_readp,
95
DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000),
48
- omap2_gpio_module_read,
96
+ /* Number of LEDs controlled by LED0 register */
49
- },
97
+ DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2),
50
- .write = {
98
DEFINE_PROP_END_OF_LIST(),
51
- omap2_gpio_module_writep,
52
- omap2_gpio_module_writep,
53
- omap2_gpio_module_write,
54
- },
55
- },
56
+ .read = omap2_gpio_module_readp,
57
+ .write = omap2_gpio_module_writep,
58
+ .valid.min_access_size = 1,
59
+ .valid.max_access_size = 4,
60
.endianness = DEVICE_NATIVE_ENDIAN,
61
};
99
};
62
100
63
--
101
--
64
2.7.4
102
2.20.1
65
103
66
104
diff view generated by jsdifflib
New patch
1
MPS3 boards have an extra SWITCH register in the FPGAIO block which
2
reports the value of some switches. Implement this, governed by a
3
property the board code can use to specify whether whether it exists.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210215115138.20465-7-peter.maydell@linaro.org
9
---
10
include/hw/misc/mps2-fpgaio.h | 1 +
11
hw/misc/mps2-fpgaio.c | 10 ++++++++++
12
2 files changed, 11 insertions(+)
13
14
diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/misc/mps2-fpgaio.h
17
+++ b/include/hw/misc/mps2-fpgaio.h
18
@@ -XXX,XX +XXX,XX @@ struct MPS2FPGAIO {
19
MemoryRegion iomem;
20
LEDState *led[MPS2FPGAIO_MAX_LEDS];
21
uint32_t num_leds;
22
+ bool has_switches;
23
24
uint32_t led0;
25
uint32_t prescale;
26
diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/misc/mps2-fpgaio.c
29
+++ b/hw/misc/mps2-fpgaio.c
30
@@ -XXX,XX +XXX,XX @@ REG32(CLK100HZ, 0x14)
31
REG32(COUNTER, 0x18)
32
REG32(PRESCALE, 0x1c)
33
REG32(PSCNTR, 0x20)
34
+REG32(SWITCH, 0x28)
35
REG32(MISC, 0x4c)
36
37
static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq)
38
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size)
39
resync_counter(s);
40
r = s->pscntr;
41
break;
42
+ case A_SWITCH:
43
+ if (!s->has_switches) {
44
+ goto bad_offset;
45
+ }
46
+ /* User-togglable board switches. We don't model that, so report 0. */
47
+ r = 0;
48
+ break;
49
default:
50
+ bad_offset:
51
qemu_log_mask(LOG_GUEST_ERROR,
52
"MPS2 FPGAIO read: bad offset %x\n", (int) offset);
53
r = 0;
54
@@ -XXX,XX +XXX,XX @@ static Property mps2_fpgaio_properties[] = {
55
DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000),
56
/* Number of LEDs controlled by LED0 register */
57
DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2),
58
+ DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false),
59
DEFINE_PROP_END_OF_LIST(),
60
};
61
62
--
63
2.20.1
64
65
diff view generated by jsdifflib
1
In v7M, the fixed-priority exceptions are:
1
Set the FPGAIO num-leds and have-switches properties explicitly
2
Reset: -3
2
per-board, rather than relying on the defaults. The AN505 and AN521
3
NMI: -2
3
both have the same settings as the default values, but the AN524 will
4
HardFault: -1
4
be different.
5
6
In v8M, this changes because Secure HardFault may need
7
to be prioritised above NMI:
8
Reset: -4
9
Secure HardFault if AIRCR.BFHFNMINS == 1: -3
10
NMI: -2
11
Secure HardFault if AIRCR.BFHFNMINS == 0: -1
12
NonSecure HardFault: -1
13
14
Make these changes, including support for changing the
15
priority of Secure HardFault as AIRCR.BFHFNMINS changes.
16
5
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 1505240046-11454-14-git-send-email-peter.maydell@linaro.org
9
Message-id: 20210215115138.20465-8-peter.maydell@linaro.org
20
---
10
---
21
hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++---
11
hw/arm/mps2-tz.c | 9 +++++++++
22
1 file changed, 19 insertions(+), 3 deletions(-)
12
1 file changed, 9 insertions(+)
23
13
24
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
14
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/intc/armv7m_nvic.c
16
--- a/hw/arm/mps2-tz.c
27
+++ b/hw/intc/armv7m_nvic.c
17
+++ b/hw/arm/mps2-tz.c
28
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
18
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
29
(R_V7M_AIRCR_SYSRESETREQS_MASK |
19
uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
30
R_V7M_AIRCR_BFHFNMINS_MASK |
20
uint32_t len_oscclk;
31
R_V7M_AIRCR_PRIS_MASK);
21
const uint32_t *oscclk;
32
+ /* BFHFNMINS changes the priority of Secure HardFault */
22
+ uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */
33
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
23
+ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */
34
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
24
const char *armsse_type;
35
+ } else {
25
};
36
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
26
37
+ }
27
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
38
}
28
const char *name, hwaddr size)
39
nvic_irq_update(s);
40
}
41
@@ -XXX,XX +XXX,XX @@ static int nvic_post_load(void *opaque, int version_id)
42
{
29
{
43
NVICState *s = opaque;
30
MPS2FPGAIO *fpgaio = opaque;
44
unsigned i;
31
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
45
+ int resetprio;
32
46
33
object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO);
47
/* Check for out of range priority settings */
34
+ qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds);
48
- if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
35
+ qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches);
49
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
36
sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal);
50
+
37
return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
51
+ if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
38
}
52
s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
39
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
53
s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
40
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
54
return 1;
41
mmc->oscclk = an505_oscclk;
55
@@ -XXX,XX +XXX,XX @@ static int nvic_security_post_load(void *opaque, int version_id)
42
mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
56
int i;
43
+ mmc->fpgaio_num_leds = 2;
57
44
+ mmc->fpgaio_has_switches = false;
58
/* Check for out of range priority settings */
45
mmc->armsse_type = TYPE_IOTKIT;
59
- if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
46
}
60
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
47
61
+ && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
48
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
62
+ /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
49
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
63
+ * if the CPU state has been migrated yet; a mismatch won't
50
mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */
64
+ * cause the emulation to blow up, though.
51
mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
65
+ */
52
+ mmc->fpgaio_num_leds = 2;
66
return 1;
53
+ mmc->fpgaio_has_switches = false;
67
}
54
mmc->armsse_type = TYPE_SSE200;
68
for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
55
}
69
@@ -XXX,XX +XXX,XX @@ static Property props_nvic[] = {
70
71
static void armv7m_nvic_reset(DeviceState *dev)
72
{
73
+ int resetprio;
74
NVICState *s = NVIC(dev);
75
76
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
77
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
78
s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
79
s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
80
81
- s->vectors[ARMV7M_EXCP_RESET].prio = -3;
82
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
83
+ s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
84
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
85
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
86
56
87
--
57
--
88
2.7.4
58
2.20.1
89
59
90
60
diff view generated by jsdifflib
New patch
1
In the mps2-tz board code, we handle devices whose interrupt lines
2
must be wired to all CPUs by creating IRQ splitter devices for the
3
AN521, because it has 2 CPUs, but wiring the device IRQ directly to
4
the SSE/IoTKit input for the AN505, which has only 1 CPU.
1
5
6
We can avoid making an explicit check on the board type constant by
7
instead creating and using the IRQ splitters for any board with more
8
than 1 CPU. This avoids having to add extra cases to the
9
conditionals every time we add new boards.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210215115138.20465-9-peter.maydell@linaro.org
15
---
16
hw/arm/mps2-tz.c | 19 +++++++++----------
17
1 file changed, 9 insertions(+), 10 deletions(-)
18
19
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/mps2-tz.c
22
+++ b/hw/arm/mps2-tz.c
23
@@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name,
24
static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
25
{
26
/* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
27
- MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
28
+ MachineClass *mc = MACHINE_GET_CLASS(mms);
29
30
assert(irqno < MPS2TZ_NUMIRQ);
31
32
- switch (mmc->fpga_type) {
33
- case FPGA_AN505:
34
- return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno);
35
- case FPGA_AN521:
36
+ if (mc->max_cpus > 1) {
37
return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
38
- default:
39
- g_assert_not_reached();
40
+ } else {
41
+ return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno);
42
}
43
}
44
45
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
46
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
47
48
/*
49
- * The AN521 needs us to create splitters to feed the IRQ inputs
50
- * for each CPU in the SSE-200 from each device in the board.
51
+ * If this board has more than one CPU, then we need to create splitters
52
+ * to feed the IRQ inputs for each CPU in the SSE from each device in the
53
+ * board. If there is only one CPU, we can just wire the device IRQ
54
+ * directly to the SSE's IRQ input.
55
*/
56
- if (mmc->fpga_type == FPGA_AN521) {
57
+ if (mc->max_cpus > 1) {
58
for (i = 0; i < MPS2TZ_NUMIRQ; i++) {
59
char *name = g_strdup_printf("mps2-irq-splitter%d", i);
60
SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
61
--
62
2.20.1
63
64
diff view generated by jsdifflib
1
With banked exceptions, just the exception number in
1
The AN524 has more interrupt lines than the AN505 and AN521; make
2
s->vectpending is no longer sufficient to uniquely identify
2
numirq board-specific rather than a compile-time constant.
3
the pending exception. Add a vectpending_is_s_banked bool
3
4
which is true if the exception is using the sec_vectors[]
4
Since the difference is small (92 on the current boards and 95 on the
5
array.
5
new one) we don't dynamically allocate the cpu_irq_splitter[] array
6
but leave it as a fixed length array whose size is the maximum needed
7
for any of the boards.
6
8
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20210215115138.20465-10-peter.maydell@linaro.org
9
---
13
---
10
include/hw/intc/armv7m_nvic.h | 11 +++++++++--
14
hw/arm/mps2-tz.c | 15 ++++++++++-----
11
hw/intc/armv7m_nvic.c | 1 +
15
1 file changed, 10 insertions(+), 5 deletions(-)
12
2 files changed, 10 insertions(+), 2 deletions(-)
13
16
14
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
17
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/intc/armv7m_nvic.h
19
--- a/hw/arm/mps2-tz.c
17
+++ b/include/hw/intc/armv7m_nvic.h
20
+++ b/hw/arm/mps2-tz.c
18
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
21
@@ -XXX,XX +XXX,XX @@
19
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
22
#include "hw/qdev-clock.h"
20
uint32_t prigroup;
23
#include "qom/object.h"
21
24
22
- /* vectpending and exception_prio are both cached state that can
25
-#define MPS2TZ_NUMIRQ 92
23
- * be recalculated from the vectors[] array and the prigroup field.
26
+#define MPS2TZ_NUMIRQ_MAX 92
24
+ /* The following fields are all cached state that can be recalculated
27
25
+ * from the vectors[] and sec_vectors[] arrays and the prigroup field:
28
typedef enum MPS2TZFPGAType {
26
+ * - vectpending
29
FPGA_AN505,
27
+ * - vectpending_is_secure
30
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
28
+ * - exception_prio
31
const uint32_t *oscclk;
32
uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */
33
bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */
34
+ int numirq; /* Number of external interrupts */
35
const char *armsse_type;
36
};
37
38
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
39
SplitIRQ sec_resp_splitter;
40
qemu_or_irq uart_irq_orgate;
41
DeviceState *lan9118;
42
- SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ];
43
+ SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX];
44
Clock *sysclk;
45
Clock *s32kclk;
46
};
47
@@ -XXX,XX +XXX,XX @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
48
{
49
/* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
50
MachineClass *mc = MACHINE_GET_CLASS(mms);
51
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
52
53
- assert(irqno < MPS2TZ_NUMIRQ);
54
+ assert(irqno < mmc->numirq);
55
56
if (mc->max_cpus > 1) {
57
return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
58
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
59
iotkitdev = DEVICE(&mms->iotkit);
60
object_property_set_link(OBJECT(&mms->iotkit), "memory",
61
OBJECT(system_memory), &error_abort);
62
- qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
63
+ qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
64
qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
65
qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
66
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
67
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
68
* board. If there is only one CPU, we can just wire the device IRQ
69
* directly to the SSE's IRQ input.
29
*/
70
*/
30
unsigned int vectpending; /* highest prio pending enabled exception */
71
+ assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX);
31
+ /* true if vectpending is a banked secure exception, ie it is in
72
if (mc->max_cpus > 1) {
32
+ * sec_vectors[] rather than vectors[]
73
- for (i = 0; i < MPS2TZ_NUMIRQ; i++) {
33
+ */
74
+ for (i = 0; i < mmc->numirq; i++) {
34
+ bool vectpending_is_s_banked;
75
char *name = g_strdup_printf("mps2-irq-splitter%d", i);
35
int exception_prio; /* group prio of the highest prio active exception */
76
SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
36
77
37
MemoryRegion sysregmem;
78
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
38
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
79
mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
39
index XXXXXXX..XXXXXXX 100644
80
mmc->fpgaio_num_leds = 2;
40
--- a/hw/intc/armv7m_nvic.c
81
mmc->fpgaio_has_switches = false;
41
+++ b/hw/intc/armv7m_nvic.c
82
+ mmc->numirq = 92;
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
83
mmc->armsse_type = TYPE_IOTKIT;
43
44
s->exception_prio = NVIC_NOEXC_PRIO;
45
s->vectpending = 0;
46
+ s->vectpending_is_s_banked = false;
47
}
84
}
48
85
49
static void nvic_systick_trigger(void *opaque, int n, int level)
86
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
87
mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
88
mmc->fpgaio_num_leds = 2;
89
mmc->fpgaio_has_switches = false;
90
+ mmc->numirq = 92;
91
mmc->armsse_type = TYPE_SSE200;
92
}
93
50
--
94
--
51
2.7.4
95
2.20.1
52
96
53
97
diff view generated by jsdifflib
1
For v8M, the NVIC has a new set of registers per interrupt,
1
The AN524 version of the SCC interface has different behaviour for
2
NVIC_ITNS<n>. These determine whether the interrupt targets Secure
2
some of the CFG registers; implement it.
3
or Non-secure state. Implement the register read/write code for
3
4
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
4
Each board in this family can have minor differences in the meaning
5
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
5
of the CFG registers, so rather than trying to specify all the
6
accesses to fields corresponding to interrupts which are
6
possible semantics via individual device properties, we make the
7
configured to target secure state.
7
behaviour conditional on the part-number field of the SCC_ID register
8
which the board code already passes us.
9
10
For the AN524, the differences are:
11
* CFG3 is reserved rather than being board switches
12
* CFG5 is a new register ("ACLK Frequency in Hz")
13
* CFG6 is a new register ("Clock divider for BRAM")
14
15
We implement both of the new registers as reads-as-written.
8
16
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
19
Message-id: 20210215115138.20465-11-peter.maydell@linaro.org
12
---
20
---
13
include/hw/intc/armv7m_nvic.h | 3 ++
21
include/hw/misc/mps2-scc.h | 3 ++
14
hw/intc/armv7m_nvic.c | 74 +++++++++++++++++++++++++++++++++++++++----
22
hw/misc/mps2-scc.c | 71 ++++++++++++++++++++++++++++++++++++--
15
2 files changed, 70 insertions(+), 7 deletions(-)
23
2 files changed, 72 insertions(+), 2 deletions(-)
16
24
17
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
25
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
18
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/intc/armv7m_nvic.h
27
--- a/include/hw/misc/mps2-scc.h
20
+++ b/include/hw/intc/armv7m_nvic.h
28
+++ b/include/hw/misc/mps2-scc.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
29
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
22
/* The PRIGROUP field in AIRCR is banked */
30
23
uint32_t prigroup[M_REG_NUM_BANKS];
31
uint32_t cfg0;
24
32
uint32_t cfg1;
25
+ /* v8M NVIC_ITNS state (stored as a bool per bit) */
33
+ uint32_t cfg2;
26
+ bool itns[NVIC_MAX_VECTORS];
34
uint32_t cfg4;
35
+ uint32_t cfg5;
36
+ uint32_t cfg6;
37
uint32_t cfgdata_rtn;
38
uint32_t cfgdata_out;
39
uint32_t cfgctrl;
40
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/misc/mps2-scc.c
43
+++ b/hw/misc/mps2-scc.c
44
@@ -XXX,XX +XXX,XX @@
45
46
REG32(CFG0, 0)
47
REG32(CFG1, 4)
48
+REG32(CFG2, 8)
49
REG32(CFG3, 0xc)
50
REG32(CFG4, 0x10)
51
+REG32(CFG5, 0x14)
52
+REG32(CFG6, 0x18)
53
REG32(CFGDATA_RTN, 0xa0)
54
REG32(CFGDATA_OUT, 0xa4)
55
REG32(CFGCTRL, 0xa8)
56
@@ -XXX,XX +XXX,XX @@ REG32(DLL, 0x100)
57
REG32(AID, 0xFF8)
58
REG32(ID, 0xFFC)
59
60
+static int scc_partno(MPS2SCC *s)
61
+{
62
+ /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */
63
+ return extract32(s->id, 4, 8);
64
+}
27
+
65
+
28
/* The following fields are all cached state that can be recalculated
66
/* Handle a write via the SYS_CFG channel to the specified function/device.
29
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
67
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
30
* - vectpending
68
*/
31
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
69
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
32
index XXXXXXX..XXXXXXX 100644
70
case A_CFG1:
33
--- a/hw/intc/armv7m_nvic.c
71
r = s->cfg1;
34
+++ b/hw/intc/armv7m_nvic.c
72
break;
35
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
73
+ case A_CFG2:
36
switch (offset) {
74
+ if (scc_partno(s) != 0x524) {
37
case 4: /* Interrupt Control Type. */
75
+ /* CFG2 reserved on other boards */
38
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
39
+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
40
+ {
41
+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
42
+ int i;
43
+
44
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
45
+ goto bad_offset;
76
+ goto bad_offset;
46
+ }
77
+ }
47
+ if (!attrs.secure) {
78
+ r = s->cfg2;
48
+ return 0;
79
+ break;
49
+ }
80
case A_CFG3:
50
+ val = 0;
81
+ if (scc_partno(s) == 0x524) {
51
+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
82
+ /* CFG3 reserved on AN524 */
52
+ if (s->itns[startvec + i]) {
53
+ val |= (1 << i);
54
+ }
55
+ }
56
+ return val;
57
+ }
58
case 0xd00: /* CPUID Base. */
59
return cpu->midr;
60
case 0xd04: /* Interrupt Control State. */
61
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
62
ARMCPU *cpu = s->cpu;
63
64
switch (offset) {
65
+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
66
+ {
67
+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
68
+ int i;
69
+
70
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
71
+ goto bad_offset;
83
+ goto bad_offset;
72
+ }
84
+ }
73
+ if (!attrs.secure) {
85
/* These are user-settable DIP switches on the board. We don't
74
+ break;
86
* model that, so just return zeroes.
87
*/
88
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
89
case A_CFG4:
90
r = s->cfg4;
91
break;
92
+ case A_CFG5:
93
+ if (scc_partno(s) != 0x524) {
94
+ /* CFG5 reserved on other boards */
95
+ goto bad_offset;
75
+ }
96
+ }
76
+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
97
+ r = s->cfg5;
77
+ s->itns[startvec + i] = (value >> i) & 1;
98
+ break;
99
+ case A_CFG6:
100
+ if (scc_partno(s) != 0x524) {
101
+ /* CFG6 reserved on other boards */
102
+ goto bad_offset;
78
+ }
103
+ }
79
+ nvic_irq_update(s);
104
+ r = s->cfg6;
80
+ break;
105
+ break;
81
+ }
106
case A_CFGDATA_RTN:
82
case 0xd04: /* Interrupt Control State. */
107
r = s->cfgdata_rtn;
83
if (value & (1 << 31)) {
108
break;
84
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
109
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
85
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
110
r = s->id;
86
startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
111
break;
87
112
default:
88
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
113
+ bad_offset:
89
- if (s->vectors[startvec + i].enabled) {
114
qemu_log_mask(LOG_GUEST_ERROR,
90
+ if (s->vectors[startvec + i].enabled &&
115
"MPS2 SCC read: bad offset %x\n", (int) offset);
91
+ (attrs.secure || s->itns[startvec + i])) {
116
r = 0;
92
val |= (1 << i);
117
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
93
}
118
led_set_state(s->led[i], extract32(value, i, 1));
94
}
95
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
96
val = 0;
97
startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
98
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
99
- if (s->vectors[startvec + i].pending) {
100
+ if (s->vectors[startvec + i].pending &&
101
+ (attrs.secure || s->itns[startvec + i])) {
102
val |= (1 << i);
103
}
104
}
105
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
106
startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
107
108
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
109
- if (s->vectors[startvec + i].active) {
110
+ if (s->vectors[startvec + i].active &&
111
+ (attrs.secure || s->itns[startvec + i])) {
112
val |= (1 << i);
113
}
114
}
115
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
116
startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
117
118
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
119
- val |= s->vectors[startvec + i].prio << (8 * i);
120
+ if (attrs.secure || s->itns[startvec + i]) {
121
+ val |= s->vectors[startvec + i].prio << (8 * i);
122
+ }
123
}
119
}
124
break;
120
break;
125
case 0xd18 ... 0xd23: /* System Handler Priority. */
121
+ case A_CFG2:
126
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
122
+ if (scc_partno(s) != 0x524) {
127
startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
123
+ /* CFG2 reserved on other boards */
128
124
+ goto bad_offset;
129
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
130
- if (value & (1 << i)) {
131
+ if (value & (1 << i) &&
132
+ (attrs.secure || s->itns[startvec + i])) {
133
s->vectors[startvec + i].enabled = setval;
134
}
135
}
136
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
137
startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
138
139
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
140
- if (value & (1 << i)) {
141
+ if (value & (1 << i) &&
142
+ (attrs.secure || s->itns[startvec + i])) {
143
s->vectors[startvec + i].pending = setval;
144
}
145
}
146
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
147
startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
148
149
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
150
- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
151
+ if (attrs.secure || s->itns[startvec + i]) {
152
+ set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
153
+ }
154
}
155
nvic_irq_update(s);
156
return MEMTX_OK;
157
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
158
VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
159
vmstate_VecInfo, VecInfo),
160
VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
161
+ VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),
162
VMSTATE_END_OF_LIST()
163
}
164
};
165
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
166
s->vectpending = 0;
167
s->vectpending_is_s_banked = false;
168
s->vectpending_prio = NVIC_NOEXC_PRIO;
169
+
170
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
171
+ memset(s->itns, 0, sizeof(s->itns));
172
+ } else {
173
+ /* This state is constant and not guest accessible in a non-security
174
+ * NVIC; we set the bits to true to avoid having to do a feature
175
+ * bit check in the NVIC enable/pend/etc register accessors.
176
+ */
177
+ int i;
178
+
179
+ for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {
180
+ s->itns[i] = true;
181
+ }
125
+ }
182
+ }
126
+ /* AN524: QSPI Select signal */
183
}
127
+ s->cfg2 = value;
184
128
+ break;
185
static void nvic_systick_trigger(void *opaque, int n, int level)
129
+ case A_CFG5:
130
+ if (scc_partno(s) != 0x524) {
131
+ /* CFG5 reserved on other boards */
132
+ goto bad_offset;
133
+ }
134
+ /* AN524: ACLK frequency in Hz */
135
+ s->cfg5 = value;
136
+ break;
137
+ case A_CFG6:
138
+ if (scc_partno(s) != 0x524) {
139
+ /* CFG6 reserved on other boards */
140
+ goto bad_offset;
141
+ }
142
+ /* AN524: Clock divider for BRAM */
143
+ s->cfg6 = value;
144
+ break;
145
case A_CFGDATA_OUT:
146
s->cfgdata_out = value;
147
break;
148
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
149
s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8));
150
break;
151
default:
152
+ bad_offset:
153
qemu_log_mask(LOG_GUEST_ERROR,
154
"MPS2 SCC write: bad offset 0x%x\n", (int) offset);
155
break;
156
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_reset(DeviceState *dev)
157
trace_mps2_scc_reset();
158
s->cfg0 = 0;
159
s->cfg1 = 0;
160
+ s->cfg2 = 0;
161
+ s->cfg5 = 0;
162
+ s->cfg6 = 0;
163
s->cfgdata_rtn = 0;
164
s->cfgdata_out = 0;
165
s->cfgctrl = 0x100000;
166
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_realize(DeviceState *dev, Error **errp)
167
168
static const VMStateDescription mps2_scc_vmstate = {
169
.name = "mps2-scc",
170
- .version_id = 2,
171
- .minimum_version_id = 2,
172
+ .version_id = 3,
173
+ .minimum_version_id = 3,
174
.fields = (VMStateField[]) {
175
VMSTATE_UINT32(cfg0, MPS2SCC),
176
VMSTATE_UINT32(cfg1, MPS2SCC),
177
+ VMSTATE_UINT32(cfg2, MPS2SCC),
178
+ /* cfg3, cfg4 are read-only so need not be migrated */
179
+ VMSTATE_UINT32(cfg5, MPS2SCC),
180
+ VMSTATE_UINT32(cfg6, MPS2SCC),
181
VMSTATE_UINT32(cfgdata_rtn, MPS2SCC),
182
VMSTATE_UINT32(cfgdata_out, MPS2SCC),
183
VMSTATE_UINT32(cfgctrl, MPS2SCC),
186
--
184
--
187
2.7.4
185
2.20.1
188
186
189
187
diff view generated by jsdifflib
1
Now that we have a banked FAULTMASK register and banked exceptions,
1
On the MPS2 boards, the first 32 interrupt lines are entirely
2
we can implement the correct check in cpu_mmu_index() for whether
2
internal to the SSE; interrupt lines for devices outside the SSE
3
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
3
start at 32. In the application notes that document each FPGA image,
4
handlers which have requested a negative execution priority to run
4
the interrupt wiring is documented from the point of view of the CPU,
5
with the MPU disabled. In v8M the test has to check this for the
5
so '0' is the first of the SSE's interrupts and the devices in the
6
current security state and so takes account of banking.
6
FPGA image itself are '32' and up: so the UART 0 Receive interrupt is
7
32, the SPI #0 interrupt is 51, and so on.
8
9
Within our implementation, because the external interrupts must be
10
connected to the EXP_IRQ[0...n] lines of the SSE object, we made the
11
get_sse_irq_in() function take an irqno whose values start at 0 for
12
the first FPGA device interrupt. In this numbering scheme the UART 0
13
Receive interrupt is 0, the SPI #0 interrupt is 19, and so on.
14
15
The result of these two different numbering schemes has been that
16
half of the devices were wired up to the wrong IRQs: the UART IRQs
17
are wired up correctly, but the DMA and SPI devices were passing
18
start-at-32 values to get_sse_irq_in() and so being mis-connected.
19
20
Fix the bug by making get_sse_irq_in() take values specified with the
21
same scheme that the hardware manuals use, to avoid confusion.
7
22
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
25
Message-id: 20210215115138.20465-12-peter.maydell@linaro.org
11
---
26
---
12
target/arm/cpu.h | 21 ++++++++++++++++-----
27
hw/arm/mps2-tz.c | 24 +++++++++++++++++-------
13
hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++
28
1 file changed, 17 insertions(+), 7 deletions(-)
14
2 files changed, 45 insertions(+), 5 deletions(-)
15
29
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
30
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
17
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
32
--- a/hw/arm/mps2-tz.c
19
+++ b/target/arm/cpu.h
33
+++ b/hw/arm/mps2-tz.c
20
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq);
34
@@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name,
21
* (v8M ARM ARM I_PKLD.)
35
22
*/
36
static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
23
int armv7m_nvic_raw_execution_priority(void *opaque);
37
{
24
+/**
38
- /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
25
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
39
+ /*
26
+ * priority is negative for the specified security state.
40
+ * Return a qemu_irq which will signal IRQ n to all CPUs in the
27
+ * @opaque: the NVIC
41
+ * SSE. The irqno should be as the CPU sees it, so the first
28
+ * @secure: the security state to test
42
+ * external-to-the-SSE interrupt is 32.
29
+ * This corresponds to the pseudocode IsReqExecPriNeg().
43
+ */
30
+ */
44
MachineClass *mc = MACHINE_GET_CLASS(mms);
31
+#ifndef CONFIG_USER_ONLY
45
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
32
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
46
33
+#else
47
- assert(irqno < mmc->numirq);
34
+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
48
+ assert(irqno >= 32 && irqno < (mmc->numirq + 32));
35
+{
49
+
36
+ return false;
50
+ /*
37
+}
51
+ * Convert from "CPU irq number" (as listed in the FPGA image
38
+#endif
52
+ * documentation) to the SSE external-interrupt number.
39
53
+ */
40
/* Interface for defining coprocessor registers.
54
+ irqno -= 32;
41
* Registers are defined in tables of arm_cp_reginfo structs
55
42
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
56
if (mc->max_cpus > 1) {
43
if (arm_feature(env, ARM_FEATURE_M)) {
57
return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
44
ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
58
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
45
59
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
46
- /* Execution priority is negative if FAULTMASK is set or
60
CMSDKAPBUART *uart = opaque;
47
- * we're in a HardFault or NMI handler.
61
int i = uart - &mms->uart[0];
48
- */
62
- int rxirqno = i * 2;
49
- if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
63
- int txirqno = i * 2 + 1;
50
- || env->v7m.faultmask[env->v7m.secure]) {
64
- int combirqno = i + 10;
51
+ if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
65
+ int rxirqno = i * 2 + 32;
52
mmu_idx = ARMMMUIdx_MNegPri;
66
+ int txirqno = i * 2 + 33;
53
}
67
+ int combirqno = i + 42;
54
68
SysBusDevice *s;
55
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
69
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
56
index XXXXXXX..XXXXXXX 100644
70
57
--- a/hw/intc/armv7m_nvic.c
71
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
58
+++ b/hw/intc/armv7m_nvic.c
72
59
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
73
s = SYS_BUS_DEVICE(mms->lan9118);
60
return MIN(running, s->exception_prio);
74
sysbus_realize_and_unref(s, &error_fatal);
75
- sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));
76
+ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48));
77
return sysbus_mmio_get_region(s, 0);
61
}
78
}
62
79
63
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
80
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
64
+{
81
&error_fatal);
65
+ /* Return true if the requested execution priority is negative
82
qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
66
+ * for the specified security state, ie that security state
83
qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
67
+ * has an active NMI or HardFault or has set its FAULTMASK.
84
- get_sse_irq_in(mms, 15));
68
+ * Note that this is not the same as whether the execution
85
+ get_sse_irq_in(mms, 47));
69
+ * priority is actually negative (for instance AIRCR.PRIS may
86
70
+ * mean we don't allow FAULTMASK_NS to actually make the execution
87
/* Most of the devices in the FPGA are behind Peripheral Protection
71
+ * priority negative). Compare pseudocode IsReqExcPriNeg().
88
* Controllers. The required order for initializing things is:
72
+ */
73
+ NVICState *s = opaque;
74
+
75
+ if (s->cpu->env.v7m.faultmask[secure]) {
76
+ return true;
77
+ }
78
+
79
+ if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
80
+ s->vectors[ARMV7M_EXCP_HARD].active) {
81
+ return true;
82
+ }
83
+
84
+ if (s->vectors[ARMV7M_EXCP_NMI].active &&
85
+ exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
86
+ return true;
87
+ }
88
+
89
+ return false;
90
+}
91
+
92
bool armv7m_nvic_can_take_pending_exception(void *opaque)
93
{
94
NVICState *s = opaque;
95
--
89
--
96
2.7.4
90
2.20.1
97
91
98
92
diff view generated by jsdifflib
1
In the A64 decoder, we have a lot of references to section numbers
1
The mps2-tz code uses PPCPortInfo data structures to define what
2
from version A.a of the v8A ARM ARM (DDI0487). This version of the
2
devices are present and how they are wired up. Currently we use
3
document is now long obsolete (we are currently on revision B.a),
3
these to specify device types and addresses, but hard-code the
4
and various intervening versions renumbered all the sections.
4
interrupt line wiring in each make_* helper function. This works for
5
the two boards we have at the moment, but the AN524 has some devices
6
with different interrupt assignments.
5
7
6
The most recent B.a version of the document doesn't assign
8
This commit adds the framework to allow PPCPortInfo structures to
7
section numbers at all to the individual instruction classes
9
specify interrupt numbers. We add an array of interrupt numbers to
8
in the way that the various A.x versions did. The simplest thing
10
the PPCPortInfo struct, and pass it through to the make_* helpers.
9
to do is just to delete all the out of date C.x.x references.
11
The following commit will change the make_* helpers over to using the
12
framework.
10
13
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20170915150849.23557-1-peter.maydell@linaro.org
16
Message-id: 20210215115138.20465-13-peter.maydell@linaro.org
14
---
17
---
15
target/arm/translate-a64.c | 227 +++++++++++++++++++++++----------------------
18
hw/arm/mps2-tz.c | 36 ++++++++++++++++++++++++------------
16
1 file changed, 114 insertions(+), 113 deletions(-)
19
1 file changed, 24 insertions(+), 12 deletions(-)
17
20
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
19
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
23
--- a/hw/arm/mps2-tz.c
21
+++ b/target/arm/translate-a64.c
24
+++ b/hw/arm/mps2-tz.c
22
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
25
@@ -XXX,XX +XXX,XX @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
26
* needs to be plugged into the downstream end of the PPC port.
27
*/
28
typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,
29
- const char *name, hwaddr size);
30
+ const char *name, hwaddr size,
31
+ const int *irqs);
32
33
typedef struct PPCPortInfo {
34
const char *name;
35
@@ -XXX,XX +XXX,XX @@ typedef struct PPCPortInfo {
36
void *opaque;
37
hwaddr addr;
38
hwaddr size;
39
+ int irqs[3]; /* currently no device needs more IRQ lines than this */
40
} PPCPortInfo;
41
42
typedef struct PPCInfo {
43
@@ -XXX,XX +XXX,XX @@ typedef struct PPCInfo {
44
} PPCInfo;
45
46
static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
47
- void *opaque,
48
- const char *name, hwaddr size)
49
+ void *opaque,
50
+ const char *name, hwaddr size,
51
+ const int *irqs)
52
{
53
/* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
54
* and return a pointer to its MemoryRegion.
55
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
23
}
56
}
24
57
25
/*
58
static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
26
- * the instruction disassembly implemented here matches
59
- const char *name, hwaddr size)
27
- * the instruction encoding classifications in chapter 3 (C3)
60
+ const char *name, hwaddr size,
28
- * of the ARM Architecture Reference Manual (DDI0487A_a)
61
+ const int *irqs)
29
+ * The instruction disassembly implemented here matches
62
{
30
+ * the instruction encoding classifications in chapter C4
63
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
31
+ * of the ARM Architecture Reference Manual (DDI0487B_a);
64
CMSDKAPBUART *uart = opaque;
32
+ * classification names and decode diagrams here should generally
65
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
33
+ * match up with those in the manual.
34
*/
35
36
-/* C3.2.7 Unconditional branch (immediate)
37
+/* Unconditional branch (immediate)
38
* 31 30 26 25 0
39
* +----+-----------+-------------------------------------+
40
* | op | 0 0 1 0 1 | imm26 |
41
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
42
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
43
44
if (insn & (1U << 31)) {
45
- /* C5.6.26 BL Branch with link */
46
+ /* BL Branch with link */
47
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
48
}
49
50
- /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
51
+ /* B Branch / BL Branch with link */
52
gen_goto_tb(s, 0, addr);
53
}
66
}
54
67
55
-/* C3.2.1 Compare & branch (immediate)
68
static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
56
+/* Compare and branch (immediate)
69
- const char *name, hwaddr size)
57
* 31 30 25 24 23 5 4 0
70
+ const char *name, hwaddr size,
58
* +----+-------------+----+---------------------+--------+
71
+ const int *irqs)
59
* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
72
{
60
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
73
MPS2SCC *scc = opaque;
61
gen_goto_tb(s, 1, addr);
74
DeviceState *sccdev;
75
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
62
}
76
}
63
77
64
-/* C3.2.5 Test & branch (immediate)
78
static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
65
+/* Test and branch (immediate)
79
- const char *name, hwaddr size)
66
* 31 30 25 24 23 19 18 5 4 0
80
+ const char *name, hwaddr size,
67
* +----+-------------+----+-------+-------------+------+
81
+ const int *irqs)
68
* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
82
{
69
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
83
MPS2FPGAIO *fpgaio = opaque;
70
gen_goto_tb(s, 1, addr);
84
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
85
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
71
}
86
}
72
87
73
-/* C3.2.2 / C5.6.19 Conditional branch (immediate)
88
static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
74
+/* Conditional branch (immediate)
89
- const char *name, hwaddr size)
75
* 31 25 24 23 5 4 3 0
90
+ const char *name, hwaddr size,
76
* +---------------+----+---------------------+----+------+
91
+ const int *irqs)
77
* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
92
{
78
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
93
SysBusDevice *s;
79
}
94
NICInfo *nd = &nd_table[0];
95
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
80
}
96
}
81
97
82
-/* C5.6.68 HINT */
98
static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
83
+/* HINT instruction group, including various allocated HINTs */
99
- const char *name, hwaddr size)
84
static void handle_hint(DisasContext *s, uint32_t insn,
100
+ const char *name, hwaddr size,
85
unsigned int op1, unsigned int op2, unsigned int crm)
101
+ const int *irqs)
86
{
102
{
87
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
103
TZMPC *mpc = opaque;
88
}
104
int i = mpc - &mms->ssram_mpc[0];
105
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
89
}
106
}
90
107
91
-/* C5.6.130 MSR (immediate) - move immediate to processor state field */
108
static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
92
+/* MSR (immediate) - move immediate to processor state field */
109
- const char *name, hwaddr size)
93
static void handle_msr_i(DisasContext *s, uint32_t insn,
110
+ const char *name, hwaddr size,
94
unsigned int op1, unsigned int op2, unsigned int crm)
111
+ const int *irqs)
95
{
112
{
96
@@ -XXX,XX +XXX,XX @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
113
PL080State *dma = opaque;
97
tcg_temp_free_i32(nzcv);
114
int i = dma - &mms->dma[0];
115
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
98
}
116
}
99
117
100
-/* C5.6.129 MRS - move from system register
118
static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
101
- * C5.6.131 MSR (register) - move to system register
119
- const char *name, hwaddr size)
102
- * C5.6.204 SYS
120
+ const char *name, hwaddr size,
103
- * C5.6.205 SYSL
121
+ const int *irqs)
104
+/* MRS - move from system register
122
{
105
+ * MSR (register) - move to system register
123
/*
106
+ * SYS
124
* The AN505 has five PL022 SPI controllers.
107
+ * SYSL
125
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
108
* These are all essentially the same insn in 'read' and 'write'
109
* versions, with varying op0 fields.
110
*/
111
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
112
}
113
}
126
}
114
127
115
-/* C3.2.4 System
128
static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
116
+/* System
129
- const char *name, hwaddr size)
117
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
130
+ const char *name, hwaddr size,
118
* +---------------------+---+-----+-----+-------+-------+-----+------+
131
+ const int *irqs)
119
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
120
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
121
return;
122
}
123
switch (crn) {
124
- case 2: /* C5.6.68 HINT */
125
+ case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
126
handle_hint(s, insn, op1, op2, crm);
127
break;
128
case 3: /* CLREX, DSB, DMB, ISB */
129
handle_sync(s, insn, op1, op2, crm);
130
break;
131
- case 4: /* C5.6.130 MSR (immediate) */
132
+ case 4: /* MSR (immediate) */
133
handle_msr_i(s, insn, op1, op2, crm);
134
break;
135
default:
136
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
137
handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
138
}
139
140
-/* C3.2.3 Exception generation
141
+/* Exception generation
142
*
143
* 31 24 23 21 20 5 4 2 1 0
144
* +-----------------+-----+------------------------+-----+----+
145
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
146
}
147
}
148
149
-/* C3.2.7 Unconditional branch (register)
150
+/* Unconditional branch (register)
151
* 31 25 24 21 20 16 15 10 9 5 4 0
152
* +---------------+-------+-------+-------+------+-------+
153
* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
154
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
155
s->base.is_jmp = DISAS_JUMP;
156
}
157
158
-/* C3.2 Branches, exception generating and system instructions */
159
+/* Branches, exception generating and system instructions */
160
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
161
{
132
{
162
switch (extract32(insn, 25, 7)) {
133
ArmSbconI2CState *i2c = opaque;
163
@@ -XXX,XX +XXX,XX @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
134
SysBusDevice *s;
164
return regsize == 64;
135
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
165
}
136
continue;
166
137
}
167
-/* C3.3.6 Load/store exclusive
138
168
+/* Load/store exclusive
139
- mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
169
*
140
+ mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size,
170
* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
141
+ pinfo->irqs);
171
* +-----+-------------+----+---+----+------+----+-------+------+------+
142
portname = g_strdup_printf("port[%d]", port);
172
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
143
object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
173
}
144
&error_fatal);
174
175
/*
176
- * C3.3.5 Load register (literal)
177
+ * Load register (literal)
178
*
179
* 31 30 29 27 26 25 24 23 5 4 0
180
* +-----+-------+---+-----+-------------------+-------+
181
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
182
}
183
184
/*
185
- * C5.6.80 LDNP (Load Pair - non-temporal hint)
186
- * C5.6.81 LDP (Load Pair - non vector)
187
- * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
188
- * C5.6.176 STNP (Store Pair - non-temporal hint)
189
- * C5.6.177 STP (Store Pair - non vector)
190
- * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
191
- * C6.3.165 LDP (Load Pair of SIMD&FP)
192
- * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
193
- * C6.3.284 STP (Store Pair of SIMD&FP)
194
+ * LDNP (Load Pair - non-temporal hint)
195
+ * LDP (Load Pair - non vector)
196
+ * LDPSW (Load Pair Signed Word - non vector)
197
+ * STNP (Store Pair - non-temporal hint)
198
+ * STP (Store Pair - non vector)
199
+ * LDNP (Load Pair of SIMD&FP - non-temporal hint)
200
+ * LDP (Load Pair of SIMD&FP)
201
+ * STNP (Store Pair of SIMD&FP - non-temporal hint)
202
+ * STP (Store Pair of SIMD&FP)
203
*
204
* 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
205
* +-----+-------+---+---+-------+---+-----------------------------+
206
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
207
}
208
209
/*
210
- * C3.3.8 Load/store (immediate post-indexed)
211
- * C3.3.9 Load/store (immediate pre-indexed)
212
- * C3.3.12 Load/store (unscaled immediate)
213
+ * Load/store (immediate post-indexed)
214
+ * Load/store (immediate pre-indexed)
215
+ * Load/store (unscaled immediate)
216
*
217
* 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
218
* +----+-------+---+-----+-----+---+--------+-----+------+------+
219
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
220
}
221
222
/*
223
- * C3.3.10 Load/store (register offset)
224
+ * Load/store (register offset)
225
*
226
* 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
227
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
228
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
229
}
230
231
/*
232
- * C3.3.13 Load/store (unsigned immediate)
233
+ * Load/store (unsigned immediate)
234
*
235
* 31 30 29 27 26 25 24 23 22 21 10 9 5
236
* +----+-------+---+-----+-----+------------+-------+------+
237
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
238
}
239
}
240
241
-/* C3.3.1 AdvSIMD load/store multiple structures
242
+/* AdvSIMD load/store multiple structures
243
*
244
* 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
245
* +---+---+---------------+---+-------------+--------+------+------+------+
246
* | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
247
* +---+---+---------------+---+-------------+--------+------+------+------+
248
*
249
- * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
250
+ * AdvSIMD load/store multiple structures (post-indexed)
251
*
252
* 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
253
* +---+---+---------------+---+---+---------+--------+------+------+------+
254
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
255
tcg_temp_free_i64(tcg_addr);
256
}
257
258
-/* C3.3.3 AdvSIMD load/store single structure
259
+/* AdvSIMD load/store single structure
260
*
261
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
262
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
263
* | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
264
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
265
*
266
- * C3.3.4 AdvSIMD load/store single structure (post-indexed)
267
+ * AdvSIMD load/store single structure (post-indexed)
268
*
269
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
270
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
271
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
272
tcg_temp_free_i64(tcg_addr);
273
}
274
275
-/* C3.3 Loads and stores */
276
+/* Loads and stores */
277
static void disas_ldst(DisasContext *s, uint32_t insn)
278
{
279
switch (extract32(insn, 24, 6)) {
280
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
281
}
282
}
283
284
-/* C3.4.6 PC-rel. addressing
285
+/* PC-rel. addressing
286
* 31 30 29 28 24 23 5 4 0
287
* +----+-------+-----------+-------------------+------+
288
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
289
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
290
}
291
292
/*
293
- * C3.4.1 Add/subtract (immediate)
294
+ * Add/subtract (immediate)
295
*
296
* 31 30 29 28 24 23 22 21 10 9 5 4 0
297
* +--+--+--+-----------+-----+-------------+-----+-----+
298
@@ -XXX,XX +XXX,XX @@ static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
299
return true;
300
}
301
302
-/* C3.4.4 Logical (immediate)
303
+/* Logical (immediate)
304
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
305
* +----+-----+-------------+---+------+------+------+------+
306
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
307
@@ -XXX,XX +XXX,XX @@ static void disas_logic_imm(DisasContext *s, uint32_t insn)
308
}
309
310
/*
311
- * C3.4.5 Move wide (immediate)
312
+ * Move wide (immediate)
313
*
314
* 31 30 29 28 23 22 21 20 5 4 0
315
* +--+-----+-------------+-----+----------------+------+
316
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
317
}
318
}
319
320
-/* C3.4.2 Bitfield
321
+/* Bitfield
322
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
323
* +----+-----+-------------+---+------+------+------+------+
324
* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
325
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
326
}
327
}
328
329
-/* C3.4.3 Extract
330
+/* Extract
331
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
332
* +----+------+-------------+---+----+------+--------+------+------+
333
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
334
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
335
}
336
}
337
338
-/* C3.4 Data processing - immediate */
339
+/* Data processing - immediate */
340
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
341
{
342
switch (extract32(insn, 23, 6)) {
343
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
344
}
345
}
346
347
-/* C3.5.10 Logical (shifted register)
348
+/* Logical (shifted register)
349
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
350
* +----+-----+-----------+-------+---+------+--------+------+------+
351
* | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
352
@@ -XXX,XX +XXX,XX @@ static void disas_logic_reg(DisasContext *s, uint32_t insn)
353
}
354
355
/*
356
- * C3.5.1 Add/subtract (extended register)
357
+ * Add/subtract (extended register)
358
*
359
* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
360
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
361
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
362
}
363
364
/*
365
- * C3.5.2 Add/subtract (shifted register)
366
+ * Add/subtract (shifted register)
367
*
368
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
369
* +--+--+--+-----------+-----+--+-------+---------+------+------+
370
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
371
tcg_temp_free_i64(tcg_result);
372
}
373
374
-/* C3.5.9 Data-processing (3 source)
375
-
376
- 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
377
- +--+------+-----------+------+------+----+------+------+------+
378
- |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
379
- +--+------+-----------+------+------+----+------+------+------+
380
-
381
+/* Data-processing (3 source)
382
+ *
383
+ * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
384
+ * +--+------+-----------+------+------+----+------+------+------+
385
+ * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
386
+ * +--+------+-----------+------+------+----+------+------+------+
387
*/
388
static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
389
{
390
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
391
tcg_temp_free_i64(tcg_tmp);
392
}
393
394
-/* C3.5.3 - Add/subtract (with carry)
395
+/* Add/subtract (with carry)
396
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
397
* +--+--+--+------------------------+------+---------+------+-----+
398
* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
399
@@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
400
}
401
}
402
403
-/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
404
+/* Conditional compare (immediate / register)
405
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
406
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
407
* |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
408
@@ -XXX,XX +XXX,XX @@ static void disas_cc(DisasContext *s, uint32_t insn)
409
tcg_temp_free_i32(tcg_t2);
410
}
411
412
-/* C3.5.6 Conditional select
413
+/* Conditional select
414
* 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
415
* +----+----+---+-----------------+------+------+-----+------+------+
416
* | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
417
@@ -XXX,XX +XXX,XX @@ static void handle_rbit(DisasContext *s, unsigned int sf,
418
}
419
}
420
421
-/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
422
+/* REV with sf==1, opcode==3 ("REV64") */
423
static void handle_rev64(DisasContext *s, unsigned int sf,
424
unsigned int rn, unsigned int rd)
425
{
426
@@ -XXX,XX +XXX,XX @@ static void handle_rev64(DisasContext *s, unsigned int sf,
427
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
428
}
429
430
-/* C5.6.149 REV with sf==0, opcode==2
431
- * C5.6.151 REV32 (sf==1, opcode==2)
432
+/* REV with sf==0, opcode==2
433
+ * REV32 (sf==1, opcode==2)
434
*/
435
static void handle_rev32(DisasContext *s, unsigned int sf,
436
unsigned int rn, unsigned int rd)
437
@@ -XXX,XX +XXX,XX @@ static void handle_rev32(DisasContext *s, unsigned int sf,
438
}
439
}
440
441
-/* C5.6.150 REV16 (opcode==1) */
442
+/* REV16 (opcode==1) */
443
static void handle_rev16(DisasContext *s, unsigned int sf,
444
unsigned int rn, unsigned int rd)
445
{
446
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
447
tcg_temp_free_i64(tcg_tmp);
448
}
449
450
-/* C3.5.7 Data-processing (1 source)
451
+/* Data-processing (1 source)
452
* 31 30 29 28 21 20 16 15 10 9 5 4 0
453
* +----+---+---+-----------------+---------+--------+------+------+
454
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
455
@@ -XXX,XX +XXX,XX @@ static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
456
}
457
}
458
459
-/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
460
+/* LSLV, LSRV, ASRV, RORV */
461
static void handle_shift_reg(DisasContext *s,
462
enum a64_shift_type shift_type, unsigned int sf,
463
unsigned int rm, unsigned int rn, unsigned int rd)
464
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
465
tcg_temp_free_i32(tcg_bytes);
466
}
467
468
-/* C3.5.8 Data-processing (2 source)
469
+/* Data-processing (2 source)
470
* 31 30 29 28 21 20 16 15 10 9 5 4 0
471
* +----+---+---+-----------------+------+--------+------+------+
472
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
473
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
474
}
475
}
476
477
-/* C3.5 Data processing - register */
478
+/* Data processing - register */
479
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
480
{
481
switch (extract32(insn, 24, 5)) {
482
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
483
tcg_temp_free_i64(tcg_flags);
484
}
485
486
-/* C3.6.22 Floating point compare
487
+/* Floating point compare
488
* 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
489
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
490
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
491
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
492
handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
493
}
494
495
-/* C3.6.23 Floating point conditional compare
496
+/* Floating point conditional compare
497
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
498
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
499
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
500
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
501
}
502
}
503
504
-/* C3.6.24 Floating point conditional select
505
+/* Floating point conditional select
506
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
507
* +---+---+---+-----------+------+---+------+------+-----+------+------+
508
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
509
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
510
tcg_temp_free_i64(t_true);
511
}
512
513
-/* C3.6.25 Floating-point data-processing (1 source) - single precision */
514
+/* Floating-point data-processing (1 source) - single precision */
515
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
516
{
517
TCGv_ptr fpst;
518
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
519
tcg_temp_free_i32(tcg_res);
520
}
521
522
-/* C3.6.25 Floating-point data-processing (1 source) - double precision */
523
+/* Floating-point data-processing (1 source) - double precision */
524
static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
525
{
526
TCGv_ptr fpst;
527
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
528
}
529
}
530
531
-/* C3.6.25 Floating point data-processing (1 source)
532
+/* Floating point data-processing (1 source)
533
* 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
534
* +---+---+---+-----------+------+---+--------+-----------+------+------+
535
* | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
536
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
537
}
538
}
539
540
-/* C3.6.26 Floating-point data-processing (2 source) - single precision */
541
+/* Floating-point data-processing (2 source) - single precision */
542
static void handle_fp_2src_single(DisasContext *s, int opcode,
543
int rd, int rn, int rm)
544
{
545
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
546
tcg_temp_free_i32(tcg_res);
547
}
548
549
-/* C3.6.26 Floating-point data-processing (2 source) - double precision */
550
+/* Floating-point data-processing (2 source) - double precision */
551
static void handle_fp_2src_double(DisasContext *s, int opcode,
552
int rd, int rn, int rm)
553
{
554
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
555
tcg_temp_free_i64(tcg_res);
556
}
557
558
-/* C3.6.26 Floating point data-processing (2 source)
559
+/* Floating point data-processing (2 source)
560
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
561
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
562
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
563
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
564
}
565
}
566
567
-/* C3.6.27 Floating-point data-processing (3 source) - single precision */
568
+/* Floating-point data-processing (3 source) - single precision */
569
static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
570
int rd, int rn, int rm, int ra)
571
{
572
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
573
tcg_temp_free_i32(tcg_res);
574
}
575
576
-/* C3.6.27 Floating-point data-processing (3 source) - double precision */
577
+/* Floating-point data-processing (3 source) - double precision */
578
static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
579
int rd, int rn, int rm, int ra)
580
{
581
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
582
tcg_temp_free_i64(tcg_res);
583
}
584
585
-/* C3.6.27 Floating point data-processing (3 source)
586
+/* Floating point data-processing (3 source)
587
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
588
* +---+---+---+-----------+------+----+------+----+------+------+------+
589
* | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
590
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
591
}
592
}
593
594
-/* C3.6.28 Floating point immediate
595
+/* Floating point immediate
596
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
597
* +---+---+---+-----------+------+---+------------+-------+------+------+
598
* | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
599
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
600
tcg_temp_free_i32(tcg_shift);
601
}
602
603
-/* C3.6.29 Floating point <-> fixed point conversions
604
+/* Floating point <-> fixed point conversions
605
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
606
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
607
* | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
608
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
609
}
610
}
611
612
-/* C3.6.30 Floating point <-> integer conversions
613
+/* Floating point <-> integer conversions
614
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
615
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
616
* | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
617
@@ -XXX,XX +XXX,XX @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
618
tcg_temp_free_i64(tcg_tmp);
619
}
620
621
-/* C3.6.1 EXT
622
+/* EXT
623
* 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
624
* +---+---+-------------+-----+---+------+---+------+---+------+------+
625
* | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
626
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
627
tcg_temp_free_i64(tcg_resh);
628
}
629
630
-/* C3.6.2 TBL/TBX
631
+/* TBL/TBX
632
* 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
633
* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
634
* | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
635
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
636
tcg_temp_free_i64(tcg_resh);
637
}
638
639
-/* C3.6.3 ZIP/UZP/TRN
640
+/* ZIP/UZP/TRN
641
* 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
642
* +---+---+-------------+------+---+------+---+------------------+------+
643
* | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
644
@@ -XXX,XX +XXX,XX @@ static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
645
}
646
}
647
648
-/* C3.6.4 AdvSIMD across lanes
649
+/* AdvSIMD across lanes
650
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
651
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
652
* | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
653
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
654
tcg_temp_free_i64(tcg_res);
655
}
656
657
-/* C6.3.31 DUP (Element, Vector)
658
+/* DUP (Element, Vector)
659
*
660
* 31 30 29 21 20 16 15 10 9 5 4 0
661
* +---+---+-------------------+--------+-------------+------+------+
662
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
663
tcg_temp_free_i64(tmp);
664
}
665
666
-/* C6.3.31 DUP (element, scalar)
667
+/* DUP (element, scalar)
668
* 31 21 20 16 15 10 9 5 4 0
669
* +-----------------------+--------+-------------+------+------+
670
* | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
671
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupes(DisasContext *s, int rd, int rn,
672
tcg_temp_free_i64(tmp);
673
}
674
675
-/* C6.3.32 DUP (General)
676
+/* DUP (General)
677
*
678
* 31 30 29 21 20 16 15 10 9 5 4 0
679
* +---+---+-------------------+--------+-------------+------+------+
680
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
681
}
682
}
683
684
-/* C6.3.150 INS (Element)
685
+/* INS (Element)
686
*
687
* 31 21 20 16 15 14 11 10 9 5 4 0
688
* +-----------------------+--------+------------+---+------+------+
689
@@ -XXX,XX +XXX,XX @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
690
}
691
692
693
-/* C6.3.151 INS (General)
694
+/* INS (General)
695
*
696
* 31 21 20 16 15 10 9 5 4 0
697
* +-----------------------+--------+-------------+------+------+
698
@@ -XXX,XX +XXX,XX @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
699
}
700
701
/*
702
- * C6.3.321 UMOV (General)
703
- * C6.3.237 SMOV (General)
704
+ * UMOV (General)
705
+ * SMOV (General)
706
*
707
* 31 30 29 21 20 16 15 12 10 9 5 4 0
708
* +---+---+-------------------+--------+-------------+------+------+
709
@@ -XXX,XX +XXX,XX @@ static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
710
}
711
}
712
713
-/* C3.6.5 AdvSIMD copy
714
+/* AdvSIMD copy
715
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
716
* +---+---+----+-----------------+------+---+------+---+------+------+
717
* | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
718
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
719
}
720
}
721
722
-/* C3.6.6 AdvSIMD modified immediate
723
+/* AdvSIMD modified immediate
724
* 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
725
* +---+---+----+---------------------+-----+-------+----+---+-------+------+
726
* | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
727
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
728
tcg_temp_free_i64(tcg_imm);
729
}
730
731
-/* C3.6.7 AdvSIMD scalar copy
732
+/* AdvSIMD scalar copy
733
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
734
* +-----+----+-----------------+------+---+------+---+------+------+
735
* | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
736
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
737
handle_simd_dupes(s, rd, rn, imm5);
738
}
739
740
-/* C3.6.8 AdvSIMD scalar pairwise
741
+/* AdvSIMD scalar pairwise
742
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
743
* +-----+---+-----------+------+-----------+--------+-----+------+------+
744
* | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
745
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
746
tcg_temp_free_i32(tcg_rmode);
747
}
748
749
-/* C3.6.9 AdvSIMD scalar shift by immediate
750
+/* AdvSIMD scalar shift by immediate
751
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
752
* +-----+---+-------------+------+------+--------+---+------+------+
753
* | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
754
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
755
}
756
}
757
758
-/* C3.6.10 AdvSIMD scalar three different
759
+/* AdvSIMD scalar three different
760
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
761
* +-----+---+-----------+------+---+------+--------+-----+------+------+
762
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
763
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
764
}
765
}
766
767
-/* C3.6.11 AdvSIMD scalar three same
768
+/* AdvSIMD scalar three same
769
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
770
* +-----+---+-----------+------+---+------+--------+---+------+------+
771
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
772
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
773
}
774
}
775
776
-/* C3.6.12 AdvSIMD scalar two reg misc
777
+/* AdvSIMD scalar two reg misc
778
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
779
* +-----+---+-----------+------+-----------+--------+-----+------+------+
780
* | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
781
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
782
}
783
784
785
-/* C3.6.14 AdvSIMD shift by immediate
786
+/* AdvSIMD shift by immediate
787
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
788
* +---+---+---+-------------+------+------+--------+---+------+------+
789
* | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
790
@@ -XXX,XX +XXX,XX @@ static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
791
tcg_temp_free_i64(tcg_res);
792
}
793
794
-/* C3.6.15 AdvSIMD three different
795
+/* AdvSIMD three different
796
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
797
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
798
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
799
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
800
}
801
}
802
803
-/* C3.6.16 AdvSIMD three same
804
+/* AdvSIMD three same
805
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
806
* +---+---+---+-----------+------+---+------+--------+---+------+------+
807
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
808
@@ -XXX,XX +XXX,XX @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
809
}
810
}
811
812
-/* C3.6.17 AdvSIMD two reg misc
813
+/* AdvSIMD two reg misc
814
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
815
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
816
* | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
817
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
818
}
819
}
820
821
-/* C3.6.13 AdvSIMD scalar x indexed element
822
+/* AdvSIMD scalar x indexed element
823
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
824
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
825
* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
826
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
827
- * C3.6.18 AdvSIMD vector x indexed element
828
+ * AdvSIMD vector x indexed element
829
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
830
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
831
* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
832
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
833
}
834
}
835
836
-/* C3.6.19 Crypto AES
837
+/* Crypto AES
838
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
839
* +-----------------+------+-----------+--------+-----+------+------+
840
* | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
841
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
842
tcg_temp_free_i32(tcg_decrypt);
843
}
844
845
-/* C3.6.20 Crypto three-reg SHA
846
+/* Crypto three-reg SHA
847
* 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
848
* +-----------------+------+---+------+---+--------+-----+------+------+
849
* | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
850
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
851
tcg_temp_free_i32(tcg_rm_regno);
852
}
853
854
-/* C3.6.21 Crypto two-reg SHA
855
+/* Crypto two-reg SHA
856
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
857
* +-----------------+------+-----------+--------+-----+------+------+
858
* | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
859
--
145
--
860
2.7.4
146
2.20.1
861
147
862
148
diff view generated by jsdifflib
1
Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()
1
Move the specification of the IRQ information for the uart, ethernet,
2
functions take a bool indicating whether to pend the secure
2
dma and spi devices to the data structures. (The other devices
3
or non-secure version of a banked interrupt, and update the
3
handled by the PPCPortInfo structures don't have any interrupt lines
4
callsites accordingly.
4
we need to wire up.)
5
6
In most callsites we can simply pass the correct security
7
state in; in a couple of cases we use TODO comments to indicate
8
that we will return the code in a subsequent commit.
9
5
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-10-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210215115138.20465-14-peter.maydell@linaro.org
13
---
9
---
14
target/arm/cpu.h | 14 ++++++++++-
10
hw/arm/mps2-tz.c | 52 +++++++++++++++++++++++-------------------------
15
hw/intc/armv7m_nvic.c | 64 ++++++++++++++++++++++++++++++++++++++-------------
11
1 file changed, 25 insertions(+), 27 deletions(-)
16
target/arm/helper.c | 24 +++++++++++--------
17
hw/intc/trace-events | 4 ++--
18
4 files changed, 77 insertions(+), 29 deletions(-)
19
12
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
21
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
15
--- a/hw/arm/mps2-tz.c
23
+++ b/target/arm/cpu.h
16
+++ b/hw/arm/mps2-tz.c
24
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
17
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
25
return true;
18
const char *name, hwaddr size,
19
const int *irqs)
20
{
21
+ /* The irq[] array is tx, rx, combined, in that order */
22
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
23
CMSDKAPBUART *uart = opaque;
24
int i = uart - &mms->uart[0];
25
- int rxirqno = i * 2 + 32;
26
- int txirqno = i * 2 + 33;
27
- int combirqno = i + 42;
28
SysBusDevice *s;
29
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
30
31
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
32
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq);
33
sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
34
s = SYS_BUS_DEVICE(uart);
35
- sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno));
36
- sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno));
37
+ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
38
+ sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1]));
39
sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
40
sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
41
- sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno));
42
+ sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2]));
43
return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
26
}
44
}
27
#endif
45
28
-void armv7m_nvic_set_pending(void *opaque, int irq);
46
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
29
+/**
47
30
+ * armv7m_nvic_set_pending: mark the specified exception as pending
48
s = SYS_BUS_DEVICE(mms->lan9118);
31
+ * @opaque: the NVIC
49
sysbus_realize_and_unref(s, &error_fatal);
32
+ * @irq: the exception number to mark pending
50
- sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48));
33
+ * @secure: false for non-banked exceptions or for the nonsecure
51
+ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
34
+ * version of a banked exception, true for the secure version of a banked
52
return sysbus_mmio_get_region(s, 0);
35
+ * exception.
36
+ *
37
+ * Marks the specified exception as pending. Note that we will assert()
38
+ * if @secure is true and @irq does not specify one of the fixed set
39
+ * of architecturally banked exceptions.
40
+ */
41
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
42
void armv7m_nvic_acknowledge_irq(void *opaque);
43
/**
44
* armv7m_nvic_complete_irq: complete specified interrupt or exception
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
49
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
50
qemu_set_irq(s->excpout, lvl);
51
}
53
}
52
54
53
-static void armv7m_nvic_clear_pending(void *opaque, int irq)
55
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
54
+/**
56
const char *name, hwaddr size,
55
+ * armv7m_nvic_clear_pending: mark the specified exception as not pending
57
const int *irqs)
56
+ * @opaque: the NVIC
57
+ * @irq: the exception number to mark as not pending
58
+ * @secure: false for non-banked exceptions or for the nonsecure
59
+ * version of a banked exception, true for the secure version of a banked
60
+ * exception.
61
+ *
62
+ * Marks the specified exception as not pending. Note that we will assert()
63
+ * if @secure is true and @irq does not specify one of the fixed set
64
+ * of architecturally banked exceptions.
65
+ */
66
+static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
67
{
58
{
68
NVICState *s = (NVICState *)opaque;
59
+ /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */
69
VecInfo *vec;
60
PL080State *dma = opaque;
70
61
int i = dma - &mms->dma[0];
71
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
62
SysBusDevice *s;
72
63
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
73
- vec = &s->vectors[irq];
64
74
- trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
65
s = SYS_BUS_DEVICE(dma);
75
+ if (secure) {
66
/* Wire up DMACINTR, DMACINTERR, DMACINTTC */
76
+ assert(exc_is_banked(irq));
67
- sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3));
77
+ vec = &s->sec_vectors[irq];
68
- sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3));
78
+ } else {
69
- sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3));
79
+ vec = &s->vectors[irq];
70
+ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
80
+ }
71
+ sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1]));
81
+ trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
72
+ sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2]));
82
if (vec->pending) {
73
83
vec->pending = 0;
74
g_free(mscname);
84
nvic_irq_update(s);
75
return sysbus_mmio_get_region(s, 0);
85
}
76
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque,
77
* lines are set via the "MISC" register in the MPS2 FPGAIO device.
78
*/
79
PL022State *spi = opaque;
80
- int i = spi - &mms->spi[0];
81
SysBusDevice *s;
82
83
object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022);
84
sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal);
85
s = SYS_BUS_DEVICE(spi);
86
- sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i));
87
+ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
88
return sysbus_mmio_get_region(s, 0);
86
}
89
}
87
90
88
-void armv7m_nvic_set_pending(void *opaque, int irq)
91
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
89
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
92
}, {
90
{
93
.name = "apb_ppcexp1",
91
NVICState *s = (NVICState *)opaque;
94
.ports = {
92
+ bool banked = exc_is_banked(irq);
95
- { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 },
93
VecInfo *vec;
96
- { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 },
94
97
- { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 },
95
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
98
- { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 },
96
+ assert(!secure || banked);
99
- { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 },
97
100
- { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 },
98
- vec = &s->vectors[irq];
101
- { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 },
99
- trace_nvic_set_pending(irq, vec->enabled, vec->prio);
102
- { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
100
+ vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
103
- { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
101
104
- { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
102
+ trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);
105
+ { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } },
103
106
+ { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } },
104
if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
107
+ { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } },
105
/* If a synchronous exception is pending then it may be
108
+ { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } },
106
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq)
109
+ { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } },
107
"(current priority %d)\n", irq, running);
110
+ { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } },
108
}
111
+ { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } },
109
112
+ { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } },
110
- /* We can do the escalation, so we take HardFault instead */
113
+ { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } },
111
+ /* We can do the escalation, so we take HardFault instead.
114
+ { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } },
112
+ * If BFHFNMINS is set then we escalate to the banked HF for
115
{ "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 },
113
+ * the target security state of the original exception; otherwise
116
{ "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 },
114
+ * we take a Secure HardFault.
117
{ "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 },
115
+ */
118
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
116
irq = ARMV7M_EXCP_HARD;
119
{ "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },
117
- vec = &s->vectors[irq];
120
{ "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },
118
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
121
{ "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },
119
+ (secure ||
122
- { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 },
120
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
123
+ { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } },
121
+ vec = &s->sec_vectors[irq];
124
},
122
+ } else {
125
}, {
123
+ vec = &s->vectors[irq];
126
.name = "ahb_ppcexp1",
124
+ }
127
.ports = {
125
+ /* HF may be banked but there is only one shared HFSR */
128
- { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 },
126
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
129
- { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 },
127
}
130
- { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 },
128
}
131
- { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 },
129
@@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level)
132
+ { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } },
130
if (level != vec->level) {
133
+ { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } },
131
vec->level = level;
134
+ { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } },
132
if (level) {
135
+ { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } },
133
- armv7m_nvic_set_pending(s, n);
136
},
134
+ armv7m_nvic_set_pending(s, n, false);
137
},
135
}
138
};
136
}
137
}
138
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
139
}
140
case 0xd04: /* Interrupt Control State. */
141
if (value & (1 << 31)) {
142
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
143
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
144
}
145
if (value & (1 << 28)) {
146
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
147
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
148
} else if (value & (1 << 27)) {
149
- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
150
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
151
}
152
if (value & (1 << 26)) {
153
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
154
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
155
} else if (value & (1 << 25)) {
156
- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
157
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
158
}
159
break;
160
case 0xd08: /* Vector Table Offset. */
161
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
162
{
163
int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
164
if (excnum < s->num_irq) {
165
- armv7m_nvic_set_pending(s, excnum);
166
+ armv7m_nvic_set_pending(s, excnum, false);
167
}
168
break;
169
}
170
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
171
/* SysTick just asked us to pend its exception.
172
* (This is different from an external interrupt line's
173
* behaviour.)
174
+ * TODO: when we implement the banked systicks we must make
175
+ * this pend the correct banked exception.
176
*/
177
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
178
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);
179
}
180
}
181
182
diff --git a/target/arm/helper.c b/target/arm/helper.c
183
index XXXXXXX..XXXXXXX 100644
184
--- a/target/arm/helper.c
185
+++ b/target/arm/helper.c
186
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
187
* stack, directly take a usage fault on the current stack.
188
*/
189
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
190
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
191
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
192
v7m_exception_taken(cpu, excret);
193
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
194
"stackframe: failed exception return integrity check\n");
195
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
196
* exception return excret specified then this is a UsageFault.
197
*/
198
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
199
- /* Take an INVPC UsageFault by pushing the stack again. */
200
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
201
+ /* Take an INVPC UsageFault by pushing the stack again.
202
+ * TODO: the v8M version of this code should target the
203
+ * background state for this exception.
204
+ */
205
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);
206
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
207
v7m_push_stack(cpu);
208
v7m_exception_taken(cpu, excret);
209
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
210
handle it. */
211
switch (cs->exception_index) {
212
case EXCP_UDEF:
213
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
214
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
215
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
216
break;
217
case EXCP_NOCP:
218
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
219
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
220
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
221
break;
222
case EXCP_INVSTATE:
223
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
224
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
225
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
226
break;
227
case EXCP_SWI:
228
/* The PC already points to the next instruction. */
229
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
230
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
231
break;
232
case EXCP_PREFETCH_ABORT:
233
case EXCP_DATA_ABORT:
234
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
235
env->v7m.bfar);
236
break;
237
}
238
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
239
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
240
break;
241
default:
242
/* All other FSR values are either MPU faults or "can't happen
243
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
244
env->v7m.mmfar[env->v7m.secure]);
245
break;
246
}
247
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
248
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,
249
+ env->v7m.secure);
250
break;
251
}
252
break;
253
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
254
return;
255
}
256
}
257
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
258
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
259
break;
260
case EXCP_IRQ:
261
break;
262
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
263
index XXXXXXX..XXXXXXX 100644
264
--- a/hw/intc/trace-events
265
+++ b/hw/intc/trace-events
266
@@ -XXX,XX +XXX,XX @@ nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
267
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
268
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
269
nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
270
-nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)"
271
-nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)"
272
+nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
273
+nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
274
nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
275
nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
276
nvic_complete_irq(int irq) "NVIC complete IRQ %d"
277
--
139
--
278
2.7.4
140
2.20.1
279
141
280
142
diff view generated by jsdifflib
1
In armv7m_nvic_set_pending() we have to compare the
1
We create an OR gate to wire together the overflow IRQs for all the
2
priority of an exception against the execution priority
2
UARTs on the board; this has to have twice the number of inputs as
3
to decide whether it needs to be escalated to HardFault.
3
there are UARTs, since each UART feeds it a TX overflow and an RX
4
In the specification this is a comparison against the
4
overflow interrupt line. Replace the hardcoded '10' with a
5
exception's group priority; for v7M we implemented it
5
calculation based on the size of the uart[] array in the
6
as a comparison against the raw exception priority
6
MPS2TZMachineState. (We rely on OR gate inputs that are never wired
7
because the two comparisons will always give the
7
up or asserted being treated as always-zero.)
8
same answer. For v8M the existence of AIRCR.PRIS and
9
the possibility of different PRIGROUP values for secure
10
and nonsecure exceptions means we need to explicitly
11
calculate the vector's group priority for this check.
12
8
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 1505240046-11454-12-git-send-email-peter.maydell@linaro.org
11
Message-id: 20210215115138.20465-15-peter.maydell@linaro.org
16
---
12
---
17
hw/intc/armv7m_nvic.c | 2 +-
13
hw/arm/mps2-tz.c | 11 ++++++++---
18
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 8 insertions(+), 3 deletions(-)
19
15
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
16
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
18
--- a/hw/arm/mps2-tz.c
23
+++ b/hw/intc/armv7m_nvic.c
19
+++ b/hw/arm/mps2-tz.c
24
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
20
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
25
int running = nvic_exec_prio(s);
21
*/
26
bool escalate = false;
22
memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
27
23
28
- if (vec->prio >= running) {
24
- /* The overflow IRQs for all UARTs are ORed together.
29
+ if (exc_group_prio(s, vec->prio, secure) >= running) {
25
+ /*
30
trace_nvic_escalate_prio(irq, vec->prio, running);
26
+ * The overflow IRQs for all UARTs are ORed together.
31
escalate = true;
27
* Tx, Rx and "combined" IRQs are sent to the NVIC separately.
32
} else if (!vec->enabled) {
28
- * Create the OR gate for this.
29
+ * Create the OR gate for this: it has one input for the TX overflow
30
+ * and one for the RX overflow for each UART we might have.
31
+ * (If the board has fewer than the maximum possible number of UARTs
32
+ * those inputs are never wired up and are treated as always-zero.)
33
*/
34
object_initialize_child(OBJECT(mms), "uart-irq-orgate",
35
&mms->uart_irq_orgate, TYPE_OR_IRQ);
36
- object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10,
37
+ object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines",
38
+ 2 * ARRAY_SIZE(mms->uart),
39
&error_fatal);
40
qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
41
qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
33
--
42
--
34
2.7.4
43
2.20.1
35
44
36
45
diff view generated by jsdifflib
1
Don't use old_mmio in the memory region ops struct.
1
The AN505 and AN521 have the same device layout, but the AN524 is
2
somewhat different. Allow for more than one PPCInfo array, which can
3
be selected based on the board type.
2
4
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-7-git-send-email-peter.maydell@linaro.org
7
Message-id: 20210215115138.20465-16-peter.maydell@linaro.org
6
---
8
---
7
hw/arm/omap2.c | 49 +++++++++++++++++++++++++++++++++++++------------
9
hw/arm/mps2-tz.c | 16 ++++++++++++++--
8
1 file changed, 37 insertions(+), 12 deletions(-)
10
1 file changed, 14 insertions(+), 2 deletions(-)
9
11
10
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
12
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
11
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/arm/omap2.c
14
--- a/hw/arm/mps2-tz.c
13
+++ b/hw/arm/omap2.c
15
+++ b/hw/arm/mps2-tz.c
14
@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write(void *opaque, hwaddr addr,
16
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
15
}
17
MemoryRegion *system_memory = get_system_memory();
16
}
18
DeviceState *iotkitdev;
17
19
DeviceState *dev_splitter;
18
+static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
20
+ const PPCInfo *ppcs;
19
+ unsigned size)
21
+ int num_ppcs;
20
+{
22
int i;
21
+ switch (size) {
23
22
+ case 1:
24
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
23
+ return omap_sysctl_read8(opaque, addr);
25
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
24
+ case 2:
26
* + wire up the PPC's control lines to the IoTKit object
25
+ return omap_badwidth_read32(opaque, addr); /* TODO */
27
*/
26
+ case 4:
28
27
+ return omap_sysctl_read(opaque, addr);
29
- const PPCInfo ppcs[] = { {
28
+ default:
30
+ const PPCInfo an505_ppcs[] = { {
29
+ g_assert_not_reached();
31
.name = "apb_ppcexp0",
30
+ }
32
.ports = {
31
+}
33
{ "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },
32
+
34
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
33
+static void omap_sysctl_writefn(void *opaque, hwaddr addr,
35
},
34
+ uint64_t value, unsigned size)
36
};
35
+{
37
36
+ switch (size) {
38
- for (i = 0; i < ARRAY_SIZE(ppcs); i++) {
37
+ case 1:
39
+ switch (mmc->fpga_type) {
38
+ omap_sysctl_write8(opaque, addr, value);
40
+ case FPGA_AN505:
39
+ break;
41
+ case FPGA_AN521:
40
+ case 2:
42
+ ppcs = an505_ppcs;
41
+ omap_badwidth_write32(opaque, addr, value); /* TODO */
43
+ num_ppcs = ARRAY_SIZE(an505_ppcs);
42
+ break;
43
+ case 4:
44
+ omap_sysctl_write(opaque, addr, value);
45
+ break;
44
+ break;
46
+ default:
45
+ default:
47
+ g_assert_not_reached();
46
+ g_assert_not_reached();
48
+ }
47
+ }
49
+}
50
+
48
+
51
static const MemoryRegionOps omap_sysctl_ops = {
49
+ for (i = 0; i < num_ppcs; i++) {
52
- .old_mmio = {
50
const PPCInfo *ppcinfo = &ppcs[i];
53
- .read = {
51
TZPPC *ppc = &mms->ppc[i];
54
- omap_sysctl_read8,
52
DeviceState *ppcdev;
55
- omap_badwidth_read32,    /* TODO */
56
- omap_sysctl_read,
57
- },
58
- .write = {
59
- omap_sysctl_write8,
60
- omap_badwidth_write32,    /* TODO */
61
- omap_sysctl_write,
62
- },
63
- },
64
+ .read = omap_sysctl_readfn,
65
+ .write = omap_sysctl_writefn,
66
+ .valid.min_access_size = 1,
67
+ .valid.max_access_size = 4,
68
.endianness = DEVICE_NATIVE_ENDIAN,
69
};
70
71
--
53
--
72
2.7.4
54
2.20.1
73
55
74
56
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
The AN505 and AN521 have the same layout of RAM; the AN524 does not.
2
2
Replace the current hard-coding of where the RAM is and which parts
3
Modelled System Timer in Microsemi's Smartfusion2 Soc.
3
of it are behind which MPCs with a data-driven approach.
4
Timer has two 32bit down counters and two interrupts.
4
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20170920201737.25723-2-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210215115138.20465-17-peter.maydell@linaro.org
12
---
8
---
13
hw/timer/Makefile.objs | 1 +
9
hw/arm/mps2-tz.c | 175 +++++++++++++++++++++++++++++++++++++----------
14
include/hw/timer/mss-timer.h | 64 ++++++++++
10
1 file changed, 138 insertions(+), 37 deletions(-)
15
hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++
11
16
3 files changed, 354 insertions(+)
12
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
17
create mode 100644 include/hw/timer/mss-timer.h
18
create mode 100644 hw/timer/mss-timer.c
19
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
14
--- a/hw/arm/mps2-tz.c
23
+++ b/hw/timer/Makefile.objs
15
+++ b/hw/arm/mps2-tz.c
24
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
25
26
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
27
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
28
+common-obj-$(CONFIG_MSF2) += mss-timer.o
29
diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
30
new file mode 100644
31
index XXXXXXX..XXXXXXX
32
--- /dev/null
33
+++ b/include/hw/timer/mss-timer.h
34
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@
17
#include "qom/object.h"
18
19
#define MPS2TZ_NUMIRQ_MAX 92
20
+#define MPS2TZ_RAM_MAX 4
21
22
typedef enum MPS2TZFPGAType {
23
FPGA_AN505,
24
FPGA_AN521,
25
} MPS2TZFPGAType;
26
35
+/*
27
+/*
36
+ * Microsemi SmartFusion2 Timer.
28
+ * Define the layout of RAM in a board, including which parts are
37
+ *
29
+ * behind which MPCs.
38
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
30
+ * mrindex specifies the index into mms->ram[] to use for the backing RAM;
39
+ *
31
+ * -1 means "use the system RAM".
40
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
41
+ * of this software and associated documentation files (the "Software"), to deal
42
+ * in the Software without restriction, including without limitation the rights
43
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
44
+ * copies of the Software, and to permit persons to whom the Software is
45
+ * furnished to do so, subject to the following conditions:
46
+ *
47
+ * The above copyright notice and this permission notice shall be included in
48
+ * all copies or substantial portions of the Software.
49
+ *
50
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
51
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
52
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
53
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
54
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
55
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
56
+ * THE SOFTWARE.
57
+ */
32
+ */
58
+
33
+typedef struct RAMInfo {
59
+#ifndef HW_MSS_TIMER_H
34
+ const char *name;
60
+#define HW_MSS_TIMER_H
35
+ uint32_t base;
61
+
36
+ uint32_t size;
62
+#include "hw/sysbus.h"
37
+ int mpc; /* MPC number, -1 for "not behind an MPC" */
63
+#include "hw/ptimer.h"
38
+ int mrindex;
64
+
39
+ int flags;
65
+#define TYPE_MSS_TIMER "mss-timer"
40
+} RAMInfo;
66
+#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \
67
+ (obj), TYPE_MSS_TIMER)
68
+
41
+
69
+/*
42
+/*
70
+ * There are two 32-bit down counting timers.
43
+ * Flag values:
71
+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer
44
+ * IS_ALIAS: this RAM area is an alias to the upstream end of the
72
+ * that operates either in Periodic mode or in One-shot mode.
45
+ * MPC specified by its .mpc value
73
+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
74
+ * In 64-bit mode, writing to the 32-bit registers has no effect.
75
+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers
76
+ * has no effect. Only two 32-bit timers are supported currently.
77
+ */
46
+ */
78
+#define NUM_TIMERS 2
47
+#define IS_ALIAS 1
79
+
48
+
80
+#define R_TIM1_MAX 6
49
struct MPS2TZMachineClass {
81
+
50
MachineClass parent;
82
+struct Msf2Timer {
51
MPS2TZFPGAType fpga_type;
83
+ QEMUBH *bh;
52
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
84
+ ptimer_state *ptimer;
53
uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */
85
+
54
bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */
86
+ uint32_t regs[R_TIM1_MAX];
55
int numirq; /* Number of external interrupts */
87
+ qemu_irq irq;
56
+ const RAMInfo *raminfo;
57
const char *armsse_type;
58
};
59
60
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
61
MachineState parent;
62
63
ARMSSE iotkit;
64
- MemoryRegion ssram[3];
65
- MemoryRegion ssram1_m;
66
+ MemoryRegion ram[MPS2TZ_RAM_MAX];
67
MPS2SCC scc;
68
MPS2FPGAIO fpgaio;
69
TZPPC ppc[5];
70
- TZMPC ssram_mpc[3];
71
+ TZMPC mpc[3];
72
PL022State spi[5];
73
ArmSbconI2CState i2c[4];
74
UnimplementedDeviceState i2s_audio;
75
@@ -XXX,XX +XXX,XX @@ static const uint32_t an505_oscclk[] = {
76
25000000,
77
};
78
79
+static const RAMInfo an505_raminfo[] = { {
80
+ .name = "ssram-0",
81
+ .base = 0x00000000,
82
+ .size = 0x00400000,
83
+ .mpc = 0,
84
+ .mrindex = 0,
85
+ }, {
86
+ .name = "ssram-1",
87
+ .base = 0x28000000,
88
+ .size = 0x00200000,
89
+ .mpc = 1,
90
+ .mrindex = 1,
91
+ }, {
92
+ .name = "ssram-2",
93
+ .base = 0x28200000,
94
+ .size = 0x00200000,
95
+ .mpc = 2,
96
+ .mrindex = 2,
97
+ }, {
98
+ .name = "ssram-0-alias",
99
+ .base = 0x00400000,
100
+ .size = 0x00400000,
101
+ .mpc = 0,
102
+ .mrindex = 3,
103
+ .flags = IS_ALIAS,
104
+ }, {
105
+ /* Use the largest bit of contiguous RAM as our "system memory" */
106
+ .name = "mps.ram",
107
+ .base = 0x80000000,
108
+ .size = 16 * MiB,
109
+ .mpc = -1,
110
+ .mrindex = -1,
111
+ }, {
112
+ .name = NULL,
113
+ },
88
+};
114
+};
89
+
115
+
90
+typedef struct MSSTimerState {
116
+static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)
91
+ SysBusDevice parent_obj;
92
+
93
+ MemoryRegion mmio;
94
+ uint32_t freq_hz;
95
+ struct Msf2Timer timers[NUM_TIMERS];
96
+} MSSTimerState;
97
+
98
+#endif /* HW_MSS_TIMER_H */
99
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
100
new file mode 100644
101
index XXXXXXX..XXXXXXX
102
--- /dev/null
103
+++ b/hw/timer/mss-timer.c
104
@@ -XXX,XX +XXX,XX @@
105
+/*
106
+ * Block model of System timer present in
107
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
108
+ *
109
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
110
+ *
111
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
112
+ * of this software and associated documentation files (the "Software"), to deal
113
+ * in the Software without restriction, including without limitation the rights
114
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
115
+ * copies of the Software, and to permit persons to whom the Software is
116
+ * furnished to do so, subject to the following conditions:
117
+ *
118
+ * The above copyright notice and this permission notice shall be included in
119
+ * all copies or substantial portions of the Software.
120
+ *
121
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
122
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
123
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
124
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
125
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
126
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
127
+ * THE SOFTWARE.
128
+ */
129
+
130
+#include "qemu/osdep.h"
131
+#include "qemu/main-loop.h"
132
+#include "qemu/log.h"
133
+#include "hw/timer/mss-timer.h"
134
+
135
+#ifndef MSS_TIMER_ERR_DEBUG
136
+#define MSS_TIMER_ERR_DEBUG 0
137
+#endif
138
+
139
+#define DB_PRINT_L(lvl, fmt, args...) do { \
140
+ if (MSS_TIMER_ERR_DEBUG >= lvl) { \
141
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
142
+ } \
143
+} while (0);
144
+
145
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
146
+
147
+#define R_TIM_VAL 0
148
+#define R_TIM_LOADVAL 1
149
+#define R_TIM_BGLOADVAL 2
150
+#define R_TIM_CTRL 3
151
+#define R_TIM_RIS 4
152
+#define R_TIM_MIS 5
153
+
154
+#define TIMER_CTRL_ENBL (1 << 0)
155
+#define TIMER_CTRL_ONESHOT (1 << 1)
156
+#define TIMER_CTRL_INTR (1 << 2)
157
+#define TIMER_RIS_ACK (1 << 0)
158
+#define TIMER_RST_CLR (1 << 6)
159
+#define TIMER_MODE (1 << 0)
160
+
161
+static void timer_update_irq(struct Msf2Timer *st)
162
+{
117
+{
163
+ bool isr, ier;
118
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
164
+
119
+ const RAMInfo *p;
165
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
120
+
166
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
121
+ for (p = mmc->raminfo; p->name; p++) {
167
+ qemu_set_irq(st->irq, (ier && isr));
122
+ if (p->mpc == mpc && !(p->flags & IS_ALIAS)) {
123
+ return p;
124
+ }
125
+ }
126
+ /* if raminfo array doesn't have an entry for each MPC this is a bug */
127
+ g_assert_not_reached();
168
+}
128
+}
169
+
129
+
170
+static void timer_update(struct Msf2Timer *st)
130
+static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,
131
+ const RAMInfo *raminfo)
171
+{
132
+{
172
+ uint64_t count;
133
+ /* Return an initialized MemoryRegion for the RAMInfo. */
173
+
134
+ MemoryRegion *ram;
174
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
135
+
175
+ ptimer_stop(st->ptimer);
136
+ if (raminfo->mrindex < 0) {
176
+ return;
137
+ /* Means this RAMInfo is for QEMU's "system memory" */
138
+ MachineState *machine = MACHINE(mms);
139
+ return machine->ram;
177
+ }
140
+ }
178
+
141
+
179
+ count = st->regs[R_TIM_LOADVAL];
142
+ assert(raminfo->mrindex < MPS2TZ_RAM_MAX);
180
+ ptimer_set_limit(st->ptimer, count, 1);
143
+ ram = &mms->ram[raminfo->mrindex];
181
+ ptimer_run(st->ptimer, 1);
144
+
145
+ memory_region_init_ram(ram, NULL, raminfo->name,
146
+ raminfo->size, &error_fatal);
147
+ return ram;
182
+}
148
+}
183
+
149
+
184
+static uint64_t
150
/* Create an alias of an entire original MemoryRegion @orig
185
+timer_read(void *opaque, hwaddr offset, unsigned int size)
151
* located at @base in the memory map.
152
*/
153
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
154
const int *irqs)
155
{
156
TZMPC *mpc = opaque;
157
- int i = mpc - &mms->ssram_mpc[0];
158
- MemoryRegion *ssram = &mms->ssram[i];
159
+ int i = mpc - &mms->mpc[0];
160
MemoryRegion *upstream;
161
- char *mpcname = g_strdup_printf("%s-mpc", name);
162
- static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 };
163
- static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 };
164
+ const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i);
165
+ MemoryRegion *ram = mr_for_raminfo(mms, raminfo);
166
167
- memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
168
-
169
- object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
170
- object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram),
171
+ object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC);
172
+ object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram),
173
&error_fatal);
174
sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
175
/* Map the upstream end of the MPC into system memory */
176
upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
177
- memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
178
+ memory_region_add_subregion(get_system_memory(), raminfo->base, upstream);
179
/* and connect its interrupt to the IoTKit */
180
qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
181
qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
182
"mpcexp_status", i));
183
184
- /* The first SSRAM is a special case as it has an alias; accesses to
185
- * the alias region at 0x00400000 must also go to the MPC upstream.
186
- */
187
- if (i == 0) {
188
- make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000);
189
- }
190
-
191
- g_free(mpcname);
192
/* Return the register interface MR for our caller to map behind the PPC */
193
return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
194
}
195
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
196
return sysbus_mmio_get_region(s, 0);
197
}
198
199
+static void create_non_mpc_ram(MPS2TZMachineState *mms)
186
+{
200
+{
187
+ MSSTimerState *t = opaque;
188
+ hwaddr addr;
189
+ struct Msf2Timer *st;
190
+ uint32_t ret = 0;
191
+ int timer = 0;
192
+ int isr;
193
+ int ier;
194
+
195
+ addr = offset >> 2;
196
+ /*
201
+ /*
197
+ * Two independent timers has same base address.
202
+ * Handle the RAMs which are either not behind MPCs or which are
198
+ * Based on address passed figure out which timer is being used.
203
+ * aliases to another MPC.
199
+ */
204
+ */
200
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
205
+ const RAMInfo *p;
201
+ timer = 1;
206
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
202
+ addr -= R_TIM1_MAX;
207
+
208
+ for (p = mmc->raminfo; p->name; p++) {
209
+ if (p->flags & IS_ALIAS) {
210
+ SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]);
211
+ MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1);
212
+ make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base);
213
+ } else if (p->mpc == -1) {
214
+ /* RAM not behind an MPC */
215
+ MemoryRegion *mr = mr_for_raminfo(mms, p);
216
+ memory_region_add_subregion(get_system_memory(), p->base, mr);
217
+ }
203
+ }
218
+ }
204
+
205
+ st = &t->timers[timer];
206
+
207
+ switch (addr) {
208
+ case R_TIM_VAL:
209
+ ret = ptimer_get_count(st->ptimer);
210
+ break;
211
+
212
+ case R_TIM_MIS:
213
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
214
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
215
+ ret = ier & isr;
216
+ break;
217
+
218
+ default:
219
+ if (addr < R_TIM1_MAX) {
220
+ ret = st->regs[addr];
221
+ } else {
222
+ qemu_log_mask(LOG_GUEST_ERROR,
223
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
224
+ return ret;
225
+ }
226
+ break;
227
+ }
228
+
229
+ DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset,
230
+ ret);
231
+ return ret;
232
+}
219
+}
233
+
220
+
234
+static void
221
static void mps2tz_common_init(MachineState *machine)
235
+timer_write(void *opaque, hwaddr offset,
222
{
236
+ uint64_t val64, unsigned int size)
223
MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
237
+{
224
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
238
+ MSSTimerState *t = opaque;
225
qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
239
+ hwaddr addr;
226
qdev_get_gpio_in(dev_splitter, 0));
240
+ struct Msf2Timer *st;
227
241
+ int timer = 0;
228
- /* The IoTKit sets up much of the memory layout, including
242
+ uint32_t value = val64;
243
+
244
+ addr = offset >> 2;
245
+ /*
229
+ /*
246
+ * Two independent timers has same base address.
230
+ * The IoTKit sets up much of the memory layout, including
247
+ * Based on addr passed figure out which timer is being used.
231
* the aliases between secure and non-secure regions in the
248
+ */
232
- * address space. The FPGA itself contains:
249
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
233
- *
250
+ timer = 1;
234
- * 0x00000000..0x003fffff SSRAM1
251
+ addr -= R_TIM1_MAX;
235
- * 0x00400000..0x007fffff alias of SSRAM1
252
+ }
236
- * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3
253
+
237
- * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices
254
+ st = &t->timers[timer];
238
- * 0x80000000..0x80ffffff 16MB PSRAM
255
+
239
- */
256
+ DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
240
-
257
+ value, timer);
241
- /* The FPGA images have an odd combination of different RAMs,
258
+
242
+ * address space, and also most of the devices in the system.
259
+ switch (addr) {
243
+ * The FPGA itself contains various RAMs and some additional devices.
260
+ case R_TIM_CTRL:
244
+ * The FPGA images have an odd combination of different RAMs,
261
+ st->regs[R_TIM_CTRL] = value;
245
* because in hardware they are different implementations and
262
+ timer_update(st);
246
* connected to different buses, giving varying performance/size
263
+ break;
247
* tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
264
+
248
- * call the 16MB our "system memory", as it's the largest lump.
265
+ case R_TIM_RIS:
249
+ * call the largest lump our "system memory".
266
+ if (value & TIMER_RIS_ACK) {
250
*/
267
+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
251
- memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
268
+ }
252
269
+ break;
253
/*
270
+
254
* The overflow IRQs for all UARTs are ORed together.
271
+ case R_TIM_LOADVAL:
255
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
272
+ st->regs[R_TIM_LOADVAL] = value;
256
const PPCInfo an505_ppcs[] = { {
273
+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
257
.name = "apb_ppcexp0",
274
+ timer_update(st);
258
.ports = {
275
+ }
259
- { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },
276
+ break;
260
- { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 },
277
+
261
- { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 },
278
+ case R_TIM_BGLOADVAL:
262
+ { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 },
279
+ st->regs[R_TIM_BGLOADVAL] = value;
263
+ { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 },
280
+ st->regs[R_TIM_LOADVAL] = value;
264
+ { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 },
281
+ break;
265
},
282
+
266
}, {
283
+ case R_TIM_VAL:
267
.name = "apb_ppcexp1",
284
+ case R_TIM_MIS:
268
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
285
+ break;
269
286
+
270
create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
287
+ default:
271
288
+ if (addr < R_TIM1_MAX) {
272
+ create_non_mpc_ram(mms);
289
+ st->regs[addr] = value;
273
+
290
+ } else {
274
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);
291
+ qemu_log_mask(LOG_GUEST_ERROR,
275
}
292
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
276
293
+ return;
277
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
294
+ }
278
mmc->fpgaio_num_leds = 2;
295
+ break;
279
mmc->fpgaio_has_switches = false;
296
+ }
280
mmc->numirq = 92;
297
+ timer_update_irq(st);
281
+ mmc->raminfo = an505_raminfo;
298
+}
282
mmc->armsse_type = TYPE_IOTKIT;
299
+
283
}
300
+static const MemoryRegionOps timer_ops = {
284
301
+ .read = timer_read,
285
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
302
+ .write = timer_write,
286
mmc->fpgaio_num_leds = 2;
303
+ .endianness = DEVICE_NATIVE_ENDIAN,
287
mmc->fpgaio_has_switches = false;
304
+ .valid = {
288
mmc->numirq = 92;
305
+ .min_access_size = 1,
289
+ mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */
306
+ .max_access_size = 4
290
mmc->armsse_type = TYPE_SSE200;
307
+ }
291
}
308
+};
292
309
+
310
+static void timer_hit(void *opaque)
311
+{
312
+ struct Msf2Timer *st = opaque;
313
+
314
+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
315
+
316
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
317
+ timer_update(st);
318
+ }
319
+ timer_update_irq(st);
320
+}
321
+
322
+static void mss_timer_init(Object *obj)
323
+{
324
+ MSSTimerState *t = MSS_TIMER(obj);
325
+ int i;
326
+
327
+ /* Init all the ptimers. */
328
+ for (i = 0; i < NUM_TIMERS; i++) {
329
+ struct Msf2Timer *st = &t->timers[i];
330
+
331
+ st->bh = qemu_bh_new(timer_hit, st);
332
+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
333
+ ptimer_set_freq(st->ptimer, t->freq_hz);
334
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
335
+ }
336
+
337
+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
338
+ NUM_TIMERS * R_TIM1_MAX * 4);
339
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
340
+}
341
+
342
+static const VMStateDescription vmstate_timers = {
343
+ .name = "mss-timer-block",
344
+ .version_id = 1,
345
+ .minimum_version_id = 1,
346
+ .fields = (VMStateField[]) {
347
+ VMSTATE_PTIMER(ptimer, struct Msf2Timer),
348
+ VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),
349
+ VMSTATE_END_OF_LIST()
350
+ }
351
+};
352
+
353
+static const VMStateDescription vmstate_mss_timer = {
354
+ .name = TYPE_MSS_TIMER,
355
+ .version_id = 1,
356
+ .minimum_version_id = 1,
357
+ .fields = (VMStateField[]) {
358
+ VMSTATE_UINT32(freq_hz, MSSTimerState),
359
+ VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
360
+ vmstate_timers, struct Msf2Timer),
361
+ VMSTATE_END_OF_LIST()
362
+ }
363
+};
364
+
365
+static Property mss_timer_properties[] = {
366
+ /* Libero GUI shows 100Mhz as default for clocks */
367
+ DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
368
+ 100 * 1000000),
369
+ DEFINE_PROP_END_OF_LIST(),
370
+};
371
+
372
+static void mss_timer_class_init(ObjectClass *klass, void *data)
373
+{
374
+ DeviceClass *dc = DEVICE_CLASS(klass);
375
+
376
+ dc->props = mss_timer_properties;
377
+ dc->vmsd = &vmstate_mss_timer;
378
+}
379
+
380
+static const TypeInfo mss_timer_info = {
381
+ .name = TYPE_MSS_TIMER,
382
+ .parent = TYPE_SYS_BUS_DEVICE,
383
+ .instance_size = sizeof(MSSTimerState),
384
+ .instance_init = mss_timer_init,
385
+ .class_init = mss_timer_class_init,
386
+};
387
+
388
+static void mss_timer_register_types(void)
389
+{
390
+ type_register_static(&mss_timer_info);
391
+}
392
+
393
+type_init(mss_timer_register_types)
394
--
293
--
395
2.7.4
294
2.20.1
396
295
397
296
diff view generated by jsdifflib
1
Instead of looking up the pending priority
1
Instead of hardcoding the MachineClass default_ram_size and
2
in nvic_pending_prio(), cache it in a new state struct
2
default_ram_id fields, set them on class creation by finding the
3
field. The calculation of the pending priority given
3
entry in the RAMInfo array which is marked as being the QEMU system
4
the interrupt number is more complicated in v8M with
4
RAM.
5
the security extension, so the caching will be worthwhile.
6
7
This changes nvic_pending_prio() from returning a full
8
(group + subpriority) priority value to returning a group
9
priority. This doesn't require changes to its callsites
10
because we use it only in comparisons of the form
11
execution_prio > nvic_pending_prio()
12
and execution priority is always a group priority, so
13
a test (exec prio > full prio) is true if and only if
14
(execprio > group_prio).
15
16
(Architecturally the expected comparison is with the
17
group priority for this sort of "would we preempt" test;
18
we were only doing a test with a full priority as an
19
optimisation to avoid the mask, which is possible
20
precisely because the two comparisons always give the
21
same answer.)
22
5
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210215115138.20465-18-peter.maydell@linaro.org
26
---
9
---
27
include/hw/intc/armv7m_nvic.h | 2 ++
10
hw/arm/mps2-tz.c | 24 ++++++++++++++++++++++--
28
hw/intc/armv7m_nvic.c | 23 +++++++++++++----------
11
1 file changed, 22 insertions(+), 2 deletions(-)
29
hw/intc/trace-events | 2 +-
30
3 files changed, 16 insertions(+), 11 deletions(-)
31
12
32
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
33
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/intc/armv7m_nvic.h
15
--- a/hw/arm/mps2-tz.c
35
+++ b/include/hw/intc/armv7m_nvic.h
16
+++ b/hw/arm/mps2-tz.c
36
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
17
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
37
* - vectpending
18
38
* - vectpending_is_secure
19
mc->init = mps2tz_common_init;
39
* - exception_prio
20
iic->check = mps2_tz_idau_check;
40
+ * - vectpending_prio
21
- mc->default_ram_size = 16 * MiB;
41
*/
22
- mc->default_ram_id = "mps.ram";
42
unsigned int vectpending; /* highest prio pending enabled exception */
23
+}
43
/* true if vectpending is a banked secure exception, ie it is in
24
+
44
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
25
+static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
45
*/
26
+{
46
bool vectpending_is_s_banked;
27
+ /*
47
int exception_prio; /* group prio of the highest prio active exception */
28
+ * Set mc->default_ram_size and default_ram_id from the
48
+ int vectpending_prio; /* group prio of the exeception in vectpending */
29
+ * information in mmc->raminfo.
49
30
+ */
50
MemoryRegion sysregmem;
31
+ MachineClass *mc = MACHINE_CLASS(mmc);
51
MemoryRegion sysreg_ns_mem;
32
+ const RAMInfo *p;
52
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
33
+
53
index XXXXXXX..XXXXXXX 100644
34
+ for (p = mmc->raminfo; p->name; p++) {
54
--- a/hw/intc/armv7m_nvic.c
35
+ if (p->mrindex < 0) {
55
+++ b/hw/intc/armv7m_nvic.c
36
+ /* Found the entry for "system memory" */
56
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
37
+ mc->default_ram_size = p->size;
57
38
+ mc->default_ram_id = p->name;
58
static int nvic_pending_prio(NVICState *s)
39
+ return;
59
{
40
+ }
60
- /* return the priority of the current pending interrupt,
41
+ }
61
+ /* return the group priority of the current pending interrupt,
42
+ g_assert_not_reached();
62
* or NVIC_NOEXC_PRIO if no interrupt is pending
63
*/
64
- return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
65
+ return s->vectpending_prio;
66
}
43
}
67
44
68
/* Return the value of the ISCR RETTOBASE bit:
45
static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
69
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
46
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
70
active_prio &= nvic_gprio_mask(s);
47
mmc->numirq = 92;
71
}
48
mmc->raminfo = an505_raminfo;
72
49
mmc->armsse_type = TYPE_IOTKIT;
73
+ if (pend_prio > 0) {
50
+ mps2tz_set_default_ram_info(mmc);
74
+ pend_prio &= nvic_gprio_mask(s);
75
+ }
76
+
77
s->vectpending = pend_irq;
78
+ s->vectpending_prio = pend_prio;
79
s->exception_prio = active_prio;
80
81
- trace_nvic_recompute_state(s->vectpending, s->exception_prio);
82
+ trace_nvic_recompute_state(s->vectpending,
83
+ s->vectpending_prio,
84
+ s->exception_prio);
85
}
51
}
86
52
87
/* Return the current execution priority of the CPU
53
static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
88
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
54
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
89
CPUARMState *env = &s->cpu->env;
55
mmc->numirq = 92;
90
const int pending = s->vectpending;
56
mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */
91
const int running = nvic_exec_prio(s);
57
mmc->armsse_type = TYPE_SSE200;
92
- int pendgroupprio;
58
+ mps2tz_set_default_ram_info(mmc);
93
VecInfo *vec;
94
95
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
96
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
97
assert(vec->enabled);
98
assert(vec->pending);
99
100
- pendgroupprio = vec->prio;
101
- if (pendgroupprio > 0) {
102
- pendgroupprio &= nvic_gprio_mask(s);
103
- }
104
- assert(pendgroupprio < running);
105
+ assert(s->vectpending_prio < running);
106
107
- trace_nvic_acknowledge_irq(pending, vec->prio);
108
+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
109
110
vec->active = 1;
111
vec->pending = 0;
112
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
113
s->exception_prio = NVIC_NOEXC_PRIO;
114
s->vectpending = 0;
115
s->vectpending_is_s_banked = false;
116
+ s->vectpending_prio = NVIC_NOEXC_PRIO;
117
}
59
}
118
60
119
static void nvic_systick_trigger(void *opaque, int n, int level)
61
static const TypeInfo mps2tz_info = {
120
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
121
index XXXXXXX..XXXXXXX 100644
122
--- a/hw/intc/trace-events
123
+++ b/hw/intc/trace-events
124
@@ -XXX,XX +XXX,XX @@ gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor 0x%x
125
gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending SGI %d"
126
127
# hw/intc/armv7m_nvic.c
128
-nvic_recompute_state(int vectpending, int exception_prio) "NVIC state recomputed: vectpending %d exception_prio %d"
129
+nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
130
nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
131
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
132
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
133
--
62
--
134
2.7.4
63
2.20.1
135
64
136
65
diff view generated by jsdifflib
1
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
1
The AN505 and AN521 don't have any read-only memory, but the AN524
2
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
2
does; add a flag to ROMInfo to mark a region as ROM.
3
preempt execution. The simple way to achieve this is to clear the
4
enable bit for it, since the enable bit isn't guest visible.
5
3
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org
6
Message-id: 20210215115138.20465-19-peter.maydell@linaro.org
9
---
7
---
10
hw/intc/armv7m_nvic.c | 12 ++++++++++--
8
hw/arm/mps2-tz.c | 6 ++++++
11
1 file changed, 10 insertions(+), 2 deletions(-)
9
1 file changed, 6 insertions(+)
12
10
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
11
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/armv7m_nvic.c
13
--- a/hw/arm/mps2-tz.c
16
+++ b/hw/intc/armv7m_nvic.c
14
+++ b/hw/arm/mps2-tz.c
17
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
15
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
18
(R_V7M_AIRCR_SYSRESETREQS_MASK |
16
* Flag values:
19
R_V7M_AIRCR_BFHFNMINS_MASK |
17
* IS_ALIAS: this RAM area is an alias to the upstream end of the
20
R_V7M_AIRCR_PRIS_MASK);
18
* MPC specified by its .mpc value
21
- /* BFHFNMINS changes the priority of Secure HardFault */
19
+ * IS_ROM: this RAM area is read-only
22
+ /* BFHFNMINS changes the priority of Secure HardFault, and
20
*/
23
+ * allows a pending Non-secure HardFault to preempt (which
21
#define IS_ALIAS 1
24
+ * we implement by marking it enabled).
22
+#define IS_ROM 2
25
+ */
23
26
if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
24
struct MPS2TZMachineClass {
27
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
25
MachineClass parent;
28
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
26
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,
29
} else {
27
if (raminfo->mrindex < 0) {
30
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
28
/* Means this RAMInfo is for QEMU's "system memory" */
31
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
29
MachineState *machine = MACHINE(mms);
32
}
30
+ assert(!(raminfo->flags & IS_ROM));
33
}
31
return machine->ram;
34
nvic_irq_update(s);
35
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
36
NVICState *s = NVIC(dev);
37
38
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
39
- s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
40
/* MEM, BUS, and USAGE are enabled through
41
* the System Handler Control register
42
*/
43
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
44
45
/* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
46
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
47
+ /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
48
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
49
+ } else {
50
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
51
}
32
}
52
33
53
/* Strictly speaking the reset handler should be enabled.
34
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,
35
36
memory_region_init_ram(ram, NULL, raminfo->name,
37
raminfo->size, &error_fatal);
38
+ if (raminfo->flags & IS_ROM) {
39
+ memory_region_set_readonly(ram, true);
40
+ }
41
return ram;
42
}
43
54
--
44
--
55
2.7.4
45
2.20.1
56
46
57
47
diff view generated by jsdifflib
1
Don't use the old_mmio in the memory region ops struct.
1
The armv7m_load_kernel() function takes a mem_size argument which it
2
expects to be the size of the memory region at guest address 0. (It
3
uses this argument only as a limit on how large a raw image file it
4
can load at address zero).
5
6
Instead of hardcoding this value, find the RAMInfo corresponding to
7
the 0 address and extract its size.
2
8
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-4-git-send-email-peter.maydell@linaro.org
12
Message-id: 20210215115138.20465-20-peter.maydell@linaro.org
6
---
13
---
7
hw/timer/omap_synctimer.c | 35 +++++++++++++++++++++--------------
14
hw/arm/mps2-tz.c | 17 ++++++++++++++++-
8
1 file changed, 21 insertions(+), 14 deletions(-)
15
1 file changed, 16 insertions(+), 1 deletion(-)
9
16
10
diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
17
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
11
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/timer/omap_synctimer.c
19
--- a/hw/arm/mps2-tz.c
13
+++ b/hw/timer/omap_synctimer.c
20
+++ b/hw/arm/mps2-tz.c
14
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
21
@@ -XXX,XX +XXX,XX @@ static void create_non_mpc_ram(MPS2TZMachineState *mms)
15
}
22
}
16
}
23
}
17
24
18
-static void omap_synctimer_write(void *opaque, hwaddr addr,
25
+static uint32_t boot_ram_size(MPS2TZMachineState *mms)
19
- uint32_t value)
20
+static uint64_t omap_synctimer_readfn(void *opaque, hwaddr addr,
21
+ unsigned size)
22
+{
26
+{
23
+ switch (size) {
27
+ /* Return the size of the RAM block at guest address zero */
24
+ case 1:
28
+ const RAMInfo *p;
25
+ return omap_badwidth_read32(opaque, addr);
29
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
26
+ case 2:
30
+
27
+ return omap_synctimer_readh(opaque, addr);
31
+ for (p = mmc->raminfo; p->name; p++) {
28
+ case 4:
32
+ if (p->base == 0) {
29
+ return omap_synctimer_readw(opaque, addr);
33
+ return p->size;
30
+ default:
34
+ }
31
+ g_assert_not_reached();
32
+ }
35
+ }
36
+ g_assert_not_reached();
33
+}
37
+}
34
+
38
+
35
+static void omap_synctimer_writefn(void *opaque, hwaddr addr,
39
static void mps2tz_common_init(MachineState *machine)
36
+ uint64_t value, unsigned size)
37
{
40
{
38
OMAP_BAD_REG(addr);
41
MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
42
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
43
44
create_non_mpc_ram(mms);
45
46
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);
47
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
48
+ boot_ram_size(mms));
39
}
49
}
40
50
41
static const MemoryRegionOps omap_synctimer_ops = {
51
static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
42
- .old_mmio = {
43
- .read = {
44
- omap_badwidth_read32,
45
- omap_synctimer_readh,
46
- omap_synctimer_readw,
47
- },
48
- .write = {
49
- omap_badwidth_write32,
50
- omap_synctimer_write,
51
- omap_synctimer_write,
52
- },
53
- },
54
+ .read = omap_synctimer_readfn,
55
+ .write = omap_synctimer_writefn,
56
+ .valid.min_access_size = 1,
57
+ .valid.max_access_size = 4,
58
.endianness = DEVICE_NATIVE_ENDIAN,
59
};
60
61
--
52
--
62
2.7.4
53
2.20.1
63
54
64
55
diff view generated by jsdifflib
1
Don't use old_mmio in the memory region ops struct.
1
Add support for the mps3-an524 board; this is an SSE-200 based FPGA
2
image, like the existing mps2-an521. It has a usefully larger amount
3
of RAM, and a PL031 RTC, as well as some more minor differences.
4
5
In real hardware this image runs on a newer generation of the FPGA
6
board, the MPS3 rather than the older MPS2. Architecturally the two
7
boards are similar, so we implement the MPS3 boards in the mps2-tz.c
8
file as variations of the existing MPS2 boards.
2
9
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-6-git-send-email-peter.maydell@linaro.org
12
Message-id: 20210215115138.20465-21-peter.maydell@linaro.org
6
---
13
---
7
hw/i2c/omap_i2c.c | 44 ++++++++++++++++++++++++++++++++------------
14
hw/arm/mps2-tz.c | 139 +++++++++++++++++++++++++++++++++++++++++++++--
8
1 file changed, 32 insertions(+), 12 deletions(-)
15
1 file changed, 135 insertions(+), 4 deletions(-)
9
16
10
diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
17
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
11
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/i2c/omap_i2c.c
19
--- a/hw/arm/mps2-tz.c
13
+++ b/hw/i2c/omap_i2c.c
20
+++ b/hw/arm/mps2-tz.c
14
@@ -XXX,XX +XXX,XX @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
21
@@ -XXX,XX +XXX,XX @@
22
* This source file covers the following FPGA images, for TrustZone cores:
23
* "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
24
* "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
25
+ * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
26
*
27
* Links to the TRM for the board itself and to the various Application
28
* Notes which document the FPGA images can be found here:
29
@@ -XXX,XX +XXX,XX @@
30
* http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
31
* Application Note AN521:
32
* http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html
33
+ * Application Note AN524:
34
+ * https://developer.arm.com/documentation/dai0524/latest/
35
*
36
* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
37
* (ARM ECM0601256) for the details of some of the device layout:
38
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
39
- * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines
40
+ * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
41
* most of the device layout:
42
* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
43
*
44
@@ -XXX,XX +XXX,XX @@
45
#include "hw/qdev-clock.h"
46
#include "qom/object.h"
47
48
-#define MPS2TZ_NUMIRQ_MAX 92
49
+#define MPS2TZ_NUMIRQ_MAX 95
50
#define MPS2TZ_RAM_MAX 4
51
52
typedef enum MPS2TZFPGAType {
53
FPGA_AN505,
54
FPGA_AN521,
55
+ FPGA_AN524,
56
} MPS2TZFPGAType;
57
58
/*
59
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
60
TZPPC ppc[5];
61
TZMPC mpc[3];
62
PL022State spi[5];
63
- ArmSbconI2CState i2c[4];
64
+ ArmSbconI2CState i2c[5];
65
UnimplementedDeviceState i2s_audio;
66
UnimplementedDeviceState gpio[4];
67
UnimplementedDeviceState gfx;
68
+ UnimplementedDeviceState cldc;
69
+ UnimplementedDeviceState rtc;
70
PL080State dma[4];
71
TZMSC msc[4];
72
- CMSDKAPBUART uart[5];
73
+ CMSDKAPBUART uart[6];
74
SplitIRQ sec_resp_splitter;
75
qemu_or_irq uart_irq_orgate;
76
DeviceState *lan9118;
77
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
78
#define TYPE_MPS2TZ_MACHINE "mps2tz"
79
#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
80
#define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
81
+#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
82
83
OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
84
85
@@ -XXX,XX +XXX,XX @@ static const uint32_t an505_oscclk[] = {
86
25000000,
87
};
88
89
+static const uint32_t an524_oscclk[] = {
90
+ 24000000,
91
+ 32000000,
92
+ 50000000,
93
+ 50000000,
94
+ 24576000,
95
+ 23750000,
96
+};
97
+
98
static const RAMInfo an505_raminfo[] = { {
99
.name = "ssram-0",
100
.base = 0x00000000,
101
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an505_raminfo[] = { {
102
},
103
};
104
105
+static const RAMInfo an524_raminfo[] = { {
106
+ .name = "bram",
107
+ .base = 0x00000000,
108
+ .size = 512 * KiB,
109
+ .mpc = 0,
110
+ .mrindex = 0,
111
+ }, {
112
+ .name = "sram",
113
+ .base = 0x20000000,
114
+ .size = 32 * 4 * KiB,
115
+ .mpc = 1,
116
+ .mrindex = 1,
117
+ }, {
118
+ /* We don't model QSPI flash yet; for now expose it as simple ROM */
119
+ .name = "QSPI",
120
+ .base = 0x28000000,
121
+ .size = 8 * MiB,
122
+ .mpc = 1,
123
+ .mrindex = 2,
124
+ .flags = IS_ROM,
125
+ }, {
126
+ .name = "DDR",
127
+ .base = 0x60000000,
128
+ .size = 2 * GiB,
129
+ .mpc = 2,
130
+ .mrindex = -1,
131
+ }, {
132
+ .name = NULL,
133
+ },
134
+};
135
+
136
static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)
137
{
138
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
139
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
140
},
141
};
142
143
+ const PPCInfo an524_ppcs[] = { {
144
+ .name = "apb_ppcexp0",
145
+ .ports = {
146
+ { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 },
147
+ { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 },
148
+ { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 },
149
+ },
150
+ }, {
151
+ .name = "apb_ppcexp1",
152
+ .ports = {
153
+ { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 },
154
+ { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 },
155
+ { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } },
156
+ { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } },
157
+ { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } },
158
+ { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 },
159
+ { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 },
160
+ { /* port 7 reserved */ },
161
+ { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 },
162
+ },
163
+ }, {
164
+ .name = "apb_ppcexp2",
165
+ .ports = {
166
+ { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 },
167
+ { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
168
+ 0x41301000, 0x1000 },
169
+ { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 },
170
+ { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } },
171
+ { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } },
172
+ { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } },
173
+ { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } },
174
+ { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } },
175
+ { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } },
176
+
177
+ { /* port 9 reserved */ },
178
+ { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 },
179
+ { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 },
180
+ },
181
+ }, {
182
+ .name = "ahb_ppcexp0",
183
+ .ports = {
184
+ { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 },
185
+ { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
186
+ { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
187
+ { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
188
+ { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } },
189
+ },
190
+ },
191
+ };
192
+
193
switch (mmc->fpga_type) {
194
case FPGA_AN505:
195
case FPGA_AN521:
196
ppcs = an505_ppcs;
197
num_ppcs = ARRAY_SIZE(an505_ppcs);
198
break;
199
+ case FPGA_AN524:
200
+ ppcs = an524_ppcs;
201
+ num_ppcs = ARRAY_SIZE(an524_ppcs);
202
+ break;
203
default:
204
g_assert_not_reached();
15
}
205
}
206
@@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
207
mps2tz_set_default_ram_info(mmc);
16
}
208
}
17
209
18
+static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
210
+static void mps3tz_an524_class_init(ObjectClass *oc, void *data)
19
+ unsigned size)
20
+{
211
+{
21
+ switch (size) {
212
+ MachineClass *mc = MACHINE_CLASS(oc);
22
+ case 2:
213
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
23
+ return omap_i2c_read(opaque, addr);
214
+
24
+ default:
215
+ mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
25
+ return omap_badwidth_read16(opaque, addr);
216
+ mc->default_cpus = 2;
26
+ }
217
+ mc->min_cpus = mc->default_cpus;
218
+ mc->max_cpus = mc->default_cpus;
219
+ mmc->fpga_type = FPGA_AN524;
220
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
221
+ mmc->scc_id = 0x41045240;
222
+ mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
223
+ mmc->oscclk = an524_oscclk;
224
+ mmc->len_oscclk = ARRAY_SIZE(an524_oscclk);
225
+ mmc->fpgaio_num_leds = 10;
226
+ mmc->fpgaio_has_switches = true;
227
+ mmc->numirq = 95;
228
+ mmc->raminfo = an524_raminfo;
229
+ mmc->armsse_type = TYPE_SSE200;
230
+ mps2tz_set_default_ram_info(mmc);
27
+}
231
+}
28
+
232
+
29
+static void omap_i2c_writefn(void *opaque, hwaddr addr,
233
static const TypeInfo mps2tz_info = {
30
+ uint64_t value, unsigned size)
234
.name = TYPE_MPS2TZ_MACHINE,
31
+{
235
.parent = TYPE_MACHINE,
32
+ switch (size) {
236
@@ -XXX,XX +XXX,XX @@ static const TypeInfo mps2tz_an521_info = {
33
+ case 1:
237
.class_init = mps2tz_an521_class_init,
34
+ /* Only the last fifo write can be 8 bit. */
35
+ omap_i2c_writeb(opaque, addr, value);
36
+ break;
37
+ case 2:
38
+ omap_i2c_write(opaque, addr, value);
39
+ break;
40
+ default:
41
+ omap_badwidth_write16(opaque, addr, value);
42
+ break;
43
+ }
44
+}
45
+
46
static const MemoryRegionOps omap_i2c_ops = {
47
- .old_mmio = {
48
- .read = {
49
- omap_badwidth_read16,
50
- omap_i2c_read,
51
- omap_badwidth_read16,
52
- },
53
- .write = {
54
- omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
55
- omap_i2c_write,
56
- omap_badwidth_write16,
57
- },
58
- },
59
+ .read = omap_i2c_readfn,
60
+ .write = omap_i2c_writefn,
61
+ .valid.min_access_size = 1,
62
+ .valid.max_access_size = 4,
63
.endianness = DEVICE_NATIVE_ENDIAN,
64
};
238
};
65
239
240
+static const TypeInfo mps3tz_an524_info = {
241
+ .name = TYPE_MPS3TZ_AN524_MACHINE,
242
+ .parent = TYPE_MPS2TZ_MACHINE,
243
+ .class_init = mps3tz_an524_class_init,
244
+};
245
+
246
static void mps2tz_machine_init(void)
247
{
248
type_register_static(&mps2tz_info);
249
type_register_static(&mps2tz_an505_info);
250
type_register_static(&mps2tz_an521_info);
251
+ type_register_static(&mps3tz_an524_info);
252
}
253
254
type_init(mps2tz_machine_init);
66
--
255
--
67
2.7.4
256
2.20.1
68
257
69
258
diff view generated by jsdifflib
1
Don't use the old_mmio struct in memory region ops.
1
The AN524 has a USB controller (an ISP1763); we don't have a model of
2
it but we should provide a stub "unimplemented-device" for it. This
3
is slightly complicated because the USB controller shares a PPC port
4
with the ethernet controller.
5
6
Implement a make_* function which provides creates a container
7
MemoryRegion with both the ethernet controller and an
8
unimplemented-device stub for the USB controller.
2
9
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
13
Message-id: 20210215115138.20465-22-peter.maydell@linaro.org
6
---
14
---
7
hw/timer/omap_gptimer.c | 49 +++++++++++++++++++++++++++++++++++++------------
15
hw/arm/mps2-tz.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++-
8
1 file changed, 37 insertions(+), 12 deletions(-)
16
1 file changed, 47 insertions(+), 1 deletion(-)
9
17
10
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
18
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
11
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/timer/omap_gptimer.c
20
--- a/hw/arm/mps2-tz.c
13
+++ b/hw/timer/omap_gptimer.c
21
+++ b/hw/arm/mps2-tz.c
14
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
22
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
15
s->writeh = (uint16_t) value;
23
24
ARMSSE iotkit;
25
MemoryRegion ram[MPS2TZ_RAM_MAX];
26
+ MemoryRegion eth_usb_container;
27
+
28
MPS2SCC scc;
29
MPS2FPGAIO fpgaio;
30
TZPPC ppc[5];
31
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
32
UnimplementedDeviceState gfx;
33
UnimplementedDeviceState cldc;
34
UnimplementedDeviceState rtc;
35
+ UnimplementedDeviceState usb;
36
PL080State dma[4];
37
TZMSC msc[4];
38
CMSDKAPBUART uart[6];
39
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
40
return sysbus_mmio_get_region(s, 0);
16
}
41
}
17
42
18
+static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,
43
+static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque,
19
+ unsigned size)
44
+ const char *name, hwaddr size,
45
+ const int *irqs)
20
+{
46
+{
21
+ switch (size) {
47
+ /*
22
+ case 1:
48
+ * The AN524 makes the ethernet and USB share a PPC port.
23
+ return omap_badwidth_read32(opaque, addr);
49
+ * irqs[] is the ethernet IRQ.
24
+ case 2:
50
+ */
25
+ return omap_gp_timer_readh(opaque, addr);
51
+ SysBusDevice *s;
26
+ case 4:
52
+ NICInfo *nd = &nd_table[0];
27
+ return omap_gp_timer_readw(opaque, addr);
53
+
28
+ default:
54
+ memory_region_init(&mms->eth_usb_container, OBJECT(mms),
29
+ g_assert_not_reached();
55
+ "mps2-tz-eth-usb-container", 0x200000);
30
+ }
56
+
57
+ /*
58
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
59
+ * except that it doesn't support the checksum-offload feature.
60
+ */
61
+ qemu_check_nic_model(nd, "lan9118");
62
+ mms->lan9118 = qdev_new(TYPE_LAN9118);
63
+ qdev_set_nic_properties(mms->lan9118, nd);
64
+
65
+ s = SYS_BUS_DEVICE(mms->lan9118);
66
+ sysbus_realize_and_unref(s, &error_fatal);
67
+ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
68
+
69
+ memory_region_add_subregion(&mms->eth_usb_container,
70
+ 0, sysbus_mmio_get_region(s, 0));
71
+
72
+ /* The USB OTG controller is an ISP1763; we don't have a model of it. */
73
+ object_initialize_child(OBJECT(mms), "usb-otg",
74
+ &mms->usb, TYPE_UNIMPLEMENTED_DEVICE);
75
+ qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg");
76
+ qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000);
77
+ s = SYS_BUS_DEVICE(&mms->usb);
78
+ sysbus_realize(s, &error_fatal);
79
+
80
+ memory_region_add_subregion(&mms->eth_usb_container,
81
+ 0x100000, sysbus_mmio_get_region(s, 0));
82
+
83
+ return &mms->eth_usb_container;
31
+}
84
+}
32
+
85
+
33
+static void omap_gp_timer_writefn(void *opaque, hwaddr addr,
86
static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
34
+ uint64_t value, unsigned size)
87
const char *name, hwaddr size,
35
+{
88
const int *irqs)
36
+ switch (size) {
89
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
37
+ case 1:
90
{ "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
38
+ omap_badwidth_write32(opaque, addr, value);
91
{ "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
39
+ break;
92
{ "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
40
+ case 2:
93
- { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } },
41
+ omap_gp_timer_writeh(opaque, addr, value);
94
+ { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } },
42
+ break;
95
},
43
+ case 4:
96
},
44
+ omap_gp_timer_write(opaque, addr, value);
97
};
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
+}
50
+
51
static const MemoryRegionOps omap_gp_timer_ops = {
52
- .old_mmio = {
53
- .read = {
54
- omap_badwidth_read32,
55
- omap_gp_timer_readh,
56
- omap_gp_timer_readw,
57
- },
58
- .write = {
59
- omap_badwidth_write32,
60
- omap_gp_timer_writeh,
61
- omap_gp_timer_write,
62
- },
63
- },
64
+ .read = omap_gp_timer_readfn,
65
+ .write = omap_gp_timer_writefn,
66
+ .valid.min_access_size = 1,
67
+ .valid.max_access_size = 4,
68
.endianness = DEVICE_NATIVE_ENDIAN,
69
};
70
71
--
98
--
72
2.7.4
99
2.20.1
73
100
74
101
diff view generated by jsdifflib
1
Make the set_prio() function take a bool indicating
1
The AN524 has a PL031 RTC, which we have a model of; provide it
2
whether to pend the secure or non-secure version of a banked
2
rather than an unimplemented-device stub.
3
interrupt, and use this to implement the correct banking
4
semantics for the SHPR registers.
5
3
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
7
Message-id: 20210215115138.20465-23-peter.maydell@linaro.org
9
---
8
---
10
hw/intc/armv7m_nvic.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-----
9
hw/arm/mps2-tz.c | 22 ++++++++++++++++++++--
11
hw/intc/trace-events | 2 +-
10
1 file changed, 20 insertions(+), 2 deletions(-)
12
2 files changed, 88 insertions(+), 10 deletions(-)
13
11
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
12
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
14
--- a/hw/arm/mps2-tz.c
17
+++ b/hw/intc/armv7m_nvic.c
15
+++ b/hw/arm/mps2-tz.c
18
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_raw_execution_priority(void *opaque)
16
@@ -XXX,XX +XXX,XX @@
19
return s->exception_prio;
17
#include "hw/misc/tz-msc.h"
18
#include "hw/arm/armsse.h"
19
#include "hw/dma/pl080.h"
20
+#include "hw/rtc/pl031.h"
21
#include "hw/ssi/pl022.h"
22
#include "hw/i2c/arm_sbcon_i2c.h"
23
#include "hw/net/lan9118.h"
24
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
25
UnimplementedDeviceState gpio[4];
26
UnimplementedDeviceState gfx;
27
UnimplementedDeviceState cldc;
28
- UnimplementedDeviceState rtc;
29
UnimplementedDeviceState usb;
30
+ PL031State rtc;
31
PL080State dma[4];
32
TZMSC msc[4];
33
CMSDKAPBUART uart[6];
34
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,
35
return sysbus_mmio_get_region(s, 0);
20
}
36
}
21
37
22
-/* caller must call nvic_irq_update() after this */
38
+static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque,
23
-static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
39
+ const char *name, hwaddr size,
24
+/* caller must call nvic_irq_update() after this.
40
+ const int *irqs)
25
+ * secure indicates the bank to use for banked exceptions (we assert if
41
+{
26
+ * we are passed secure=true for a non-banked exception).
42
+ PL031State *pl031 = opaque;
27
+ */
43
+ SysBusDevice *s;
28
+static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
29
{
30
assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
31
assert(irq < s->num_irq);
32
33
- s->vectors[irq].prio = prio;
34
+ if (secure) {
35
+ assert(exc_is_banked(irq));
36
+ s->sec_vectors[irq].prio = prio;
37
+ } else {
38
+ s->vectors[irq].prio = prio;
39
+ }
40
+
44
+
41
+ trace_nvic_set_prio(irq, secure, prio);
45
+ object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031);
46
+ s = SYS_BUS_DEVICE(pl031);
47
+ sysbus_realize(s, &error_fatal);
48
+ /*
49
+ * The board docs don't give an IRQ number for the PL031, so
50
+ * presumably it is not connected.
51
+ */
52
+ return sysbus_mmio_get_region(s, 0);
42
+}
53
+}
43
+
54
+
44
+/* Return the current raw priority register value.
55
static void create_non_mpc_ram(MPS2TZMachineState *mms)
45
+ * secure indicates the bank to use for banked exceptions (we assert if
56
{
46
+ * we are passed secure=true for a non-banked exception).
57
/*
47
+ */
58
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
48
+static int get_prio(NVICState *s, unsigned irq, bool secure)
59
49
+{
60
{ /* port 9 reserved */ },
50
+ assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
61
{ "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 },
51
+ assert(irq < s->num_irq);
62
- { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 },
52
63
+ { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 },
53
- trace_nvic_set_prio(irq, prio);
64
},
54
+ if (secure) {
65
}, {
55
+ assert(exc_is_banked(irq));
66
.name = "ahb_ppcexp0",
56
+ return s->sec_vectors[irq].prio;
57
+ } else {
58
+ return s->vectors[irq].prio;
59
+ }
60
}
61
62
/* Recompute state and assert irq line accordingly.
63
@@ -XXX,XX +XXX,XX @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
64
}
65
}
66
67
+static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
68
+{
69
+ /* Behaviour for the SHPR register field for this exception:
70
+ * return M_REG_NS to use the nonsecure vector (including for
71
+ * non-banked exceptions), M_REG_S for the secure version of
72
+ * a banked exception, and -1 if this field should RAZ/WI.
73
+ */
74
+ switch (exc) {
75
+ case ARMV7M_EXCP_MEM:
76
+ case ARMV7M_EXCP_USAGE:
77
+ case ARMV7M_EXCP_SVC:
78
+ case ARMV7M_EXCP_PENDSV:
79
+ case ARMV7M_EXCP_SYSTICK:
80
+ /* Banked exceptions */
81
+ return attrs.secure;
82
+ case ARMV7M_EXCP_BUS:
83
+ /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
84
+ if (!attrs.secure &&
85
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
86
+ return -1;
87
+ }
88
+ return M_REG_NS;
89
+ case ARMV7M_EXCP_SECURE:
90
+ /* Not banked, RAZ/WI from nonsecure */
91
+ if (!attrs.secure) {
92
+ return -1;
93
+ }
94
+ return M_REG_NS;
95
+ case ARMV7M_EXCP_DEBUG:
96
+ /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
97
+ return M_REG_NS;
98
+ case 8 ... 10:
99
+ case 13:
100
+ /* RES0 */
101
+ return -1;
102
+ default:
103
+ /* Not reachable due to decode of SHPR register addresses */
104
+ g_assert_not_reached();
105
+ }
106
+}
107
+
108
static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
109
uint64_t *data, unsigned size,
110
MemTxAttrs attrs)
111
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
112
}
113
}
114
break;
115
- case 0xd18 ... 0xd23: /* System Handler Priority. */
116
+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
117
val = 0;
118
for (i = 0; i < size; i++) {
119
- val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
120
+ unsigned hdlidx = (offset - 0xd14) + i;
121
+ int sbank = shpr_bank(s, hdlidx, attrs);
122
+
123
+ if (sbank < 0) {
124
+ continue;
125
+ }
126
+ val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
127
}
128
break;
129
case 0xfe0 ... 0xfff: /* ID. */
130
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
131
132
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
133
if (attrs.secure || s->itns[startvec + i]) {
134
- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
135
+ set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
136
}
137
}
138
nvic_irq_update(s);
139
return MEMTX_OK;
140
- case 0xd18 ... 0xd23: /* System Handler Priority. */
141
+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
142
for (i = 0; i < size; i++) {
143
unsigned hdlidx = (offset - 0xd14) + i;
144
- set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
145
+ int newprio = extract32(value, i * 8, 8);
146
+ int sbank = shpr_bank(s, hdlidx, attrs);
147
+
148
+ if (sbank < 0) {
149
+ continue;
150
+ }
151
+ set_prio(s, hdlidx, sbank, newprio);
152
}
153
nvic_irq_update(s);
154
return MEMTX_OK;
155
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
156
index XXXXXXX..XXXXXXX 100644
157
--- a/hw/intc/trace-events
158
+++ b/hw/intc/trace-events
159
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
160
# hw/intc/armv7m_nvic.c
161
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
162
nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
163
-nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
164
+nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
165
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
166
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
167
nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
168
--
67
--
169
2.7.4
68
2.20.1
170
69
171
70
diff view generated by jsdifflib
New patch
1
Add brief documentation of the new mps3-an524 board.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210215115138.20465-24-peter.maydell@linaro.org
7
---
8
docs/system/arm/mps2.rst | 24 ++++++++++++++++++------
9
1 file changed, 18 insertions(+), 6 deletions(-)
10
11
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
12
index XXXXXXX..XXXXXXX 100644
13
--- a/docs/system/arm/mps2.rst
14
+++ b/docs/system/arm/mps2.rst
15
@@ -XXX,XX +XXX,XX @@
16
-Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
17
-================================================================================================================
18
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``)
19
+=========================================================================================================================================
20
21
These board models all use Arm M-profile CPUs.
22
23
-The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
24
-FPGA but is otherwise the same as the 2). Since the CPU itself
25
-and most of the devices are in the FPGA, the details of the board
26
-as seen by the guest depend significantly on the FPGA image.
27
+The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
28
+bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
29
+FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
30
+
31
+Since the CPU itself and most of the devices are in the FPGA, the
32
+details of the board as seen by the guest depend significantly on the
33
+FPGA image.
34
35
QEMU models the following FPGA images:
36
37
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
38
Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
39
``mps2-an521``
40
Dual Cortex-M33 as documented in Arm Application Note AN521
41
+``mps3-an524``
42
+ Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524
43
44
Differences between QEMU and real hardware:
45
46
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
47
block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
48
if zbt_boot_ctrl is always zero)
49
+- AN524 remapping of low memory to either BRAM or to QSPI flash is
50
+ unimplemented (QEMU always maps this to BRAM, ignoring the
51
+ SCC CFG_REG0 memory-remap bit)
52
- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
53
visible difference is that the LAN9118 doesn't support checksum
54
offloading
55
+- QEMU does not model the QSPI flash in MPS3 boards as real QSPI
56
+ flash, but only as simple ROM, so attempting to rewrite the flash
57
+ from the guest will fail
58
+- QEMU does not model the USB controller in MPS3 boards
59
--
60
2.20.1
61
62
diff view generated by jsdifflib
New patch
1
1
Update old infocenter.arm.com URLs to the equivalent developer.arm.com
2
ones (the old URLs should redirect, but we might as well avoid the
3
redirection notice, and the new URLs are pleasantly shorter).
4
5
This commit covers the links to the MPS2 board TRM, the various
6
Application Notes, the IoTKit and SSE-200 documents.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210215115138.20465-25-peter.maydell@linaro.org
11
---
12
include/hw/arm/armsse.h | 4 ++--
13
include/hw/misc/armsse-cpuid.h | 2 +-
14
include/hw/misc/armsse-mhu.h | 2 +-
15
include/hw/misc/iotkit-secctl.h | 2 +-
16
include/hw/misc/iotkit-sysctl.h | 2 +-
17
include/hw/misc/iotkit-sysinfo.h | 2 +-
18
include/hw/misc/mps2-fpgaio.h | 2 +-
19
hw/arm/mps2-tz.c | 11 +++++------
20
hw/misc/armsse-cpuid.c | 2 +-
21
hw/misc/armsse-mhu.c | 2 +-
22
hw/misc/iotkit-sysctl.c | 2 +-
23
hw/misc/iotkit-sysinfo.c | 2 +-
24
hw/misc/mps2-fpgaio.c | 2 +-
25
hw/misc/mps2-scc.c | 2 +-
26
14 files changed, 19 insertions(+), 20 deletions(-)
27
28
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/armsse.h
31
+++ b/include/hw/arm/armsse.h
32
@@ -XXX,XX +XXX,XX @@
33
* hardware, which include the IoT Kit and the SSE-050, SSE-100 and
34
* SSE-200. Currently we model:
35
* - the Arm IoT Kit which is documented in
36
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
37
+ * https://developer.arm.com/documentation/ecm0601256/latest
38
* - the SSE-200 which is documented in
39
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
40
+ * https://developer.arm.com/documentation/101104/latest/
41
*
42
* The IoTKit contains:
43
* a Cortex-M33
44
diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/misc/armsse-cpuid.h
47
+++ b/include/hw/misc/armsse-cpuid.h
48
@@ -XXX,XX +XXX,XX @@
49
/*
50
* This is a model of the "CPU_IDENTITY" register block which is part of the
51
* Arm SSE-200 and documented in
52
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
53
+ * https://developer.arm.com/documentation/101104/latest/
54
*
55
* QEMU interface:
56
* + QOM property "CPUID": the value to use for the CPUID register
57
diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/hw/misc/armsse-mhu.h
60
+++ b/include/hw/misc/armsse-mhu.h
61
@@ -XXX,XX +XXX,XX @@
62
/*
63
* This is a model of the Message Handling Unit (MHU) which is part of the
64
* Arm SSE-200 and documented in
65
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
66
+ * https://developer.arm.com/documentation/101104/latest/
67
*
68
* QEMU interface:
69
* + sysbus MMIO region 0: the system information register bank
70
diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/hw/misc/iotkit-secctl.h
73
+++ b/include/hw/misc/iotkit-secctl.h
74
@@ -XXX,XX +XXX,XX @@
75
76
/* This is a model of the security controller which is part of the
77
* Arm IoT Kit and documented in
78
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
79
+ * https://developer.arm.com/documentation/ecm0601256/latest
80
*
81
* QEMU interface:
82
* + sysbus MMIO region 0 is the "secure privilege control block" registers
83
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
84
index XXXXXXX..XXXXXXX 100644
85
--- a/include/hw/misc/iotkit-sysctl.h
86
+++ b/include/hw/misc/iotkit-sysctl.h
87
@@ -XXX,XX +XXX,XX @@
88
/*
89
* This is a model of the "system control element" which is part of the
90
* Arm IoTKit and documented in
91
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
92
+ * https://developer.arm.com/documentation/ecm0601256/latest
93
* Specifically, it implements the "system information block" and
94
* "system control register" blocks.
95
*
96
diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysinfo.h
97
index XXXXXXX..XXXXXXX 100644
98
--- a/include/hw/misc/iotkit-sysinfo.h
99
+++ b/include/hw/misc/iotkit-sysinfo.h
100
@@ -XXX,XX +XXX,XX @@
101
/*
102
* This is a model of the "system information block" which is part of the
103
* Arm IoTKit and documented in
104
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
105
+ * https://developer.arm.com/documentation/ecm0601256/latest
106
* QEMU interface:
107
* + QOM property "SYS_VERSION": value to use for SYS_VERSION register
108
* + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register
109
diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/include/hw/misc/mps2-fpgaio.h
112
+++ b/include/hw/misc/mps2-fpgaio.h
113
@@ -XXX,XX +XXX,XX @@
114
/* This is a model of the FPGAIO register block in the AN505
115
* FPGA image for the MPS2 dev board; it is documented in the
116
* application note:
117
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
118
+ * https://developer.arm.com/documentation/dai0505/latest/
119
*
120
* QEMU interface:
121
* + sysbus MMIO region 0: the register bank
122
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
123
index XXXXXXX..XXXXXXX 100644
124
--- a/hw/arm/mps2-tz.c
125
+++ b/hw/arm/mps2-tz.c
126
@@ -XXX,XX +XXX,XX @@
127
* https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
128
*
129
* Board TRM:
130
- * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
131
+ * https://developer.arm.com/documentation/100112/latest/
132
* Application Note AN505:
133
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
134
+ * https://developer.arm.com/documentation/dai0505/latest/
135
* Application Note AN521:
136
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html
137
+ * https://developer.arm.com/documentation/dai0521/latest/
138
* Application Note AN524:
139
* https://developer.arm.com/documentation/dai0524/latest/
140
*
141
* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
142
* (ARM ECM0601256) for the details of some of the device layout:
143
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
144
+ * https://developer.arm.com/documentation/ecm0601256/latest
145
* Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
146
* most of the device layout:
147
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
148
- *
149
+ * https://developer.arm.com/documentation/101104/latest/
150
*/
151
152
#include "qemu/osdep.h"
153
diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c
154
index XXXXXXX..XXXXXXX 100644
155
--- a/hw/misc/armsse-cpuid.c
156
+++ b/hw/misc/armsse-cpuid.c
157
@@ -XXX,XX +XXX,XX @@
158
/*
159
* This is a model of the "CPU_IDENTITY" register block which is part of the
160
* Arm SSE-200 and documented in
161
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
162
+ * https://developer.arm.com/documentation/101104/latest/
163
*
164
* It consists of one read-only CPUID register (set by QOM property), plus the
165
* usual ID registers.
166
diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/hw/misc/armsse-mhu.c
169
+++ b/hw/misc/armsse-mhu.c
170
@@ -XXX,XX +XXX,XX @@
171
/*
172
* This is a model of the Message Handling Unit (MHU) which is part of the
173
* Arm SSE-200 and documented in
174
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
175
+ * https://developer.arm.com/documentation/101104/latest/
176
*/
177
178
#include "qemu/osdep.h"
179
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
180
index XXXXXXX..XXXXXXX 100644
181
--- a/hw/misc/iotkit-sysctl.c
182
+++ b/hw/misc/iotkit-sysctl.c
183
@@ -XXX,XX +XXX,XX @@
184
/*
185
* This is a model of the "system control element" which is part of the
186
* Arm IoTKit and documented in
187
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
188
+ * https://developer.arm.com/documentation/ecm0601256/latest
189
* Specifically, it implements the "system control register" blocks.
190
*/
191
192
diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c
193
index XXXXXXX..XXXXXXX 100644
194
--- a/hw/misc/iotkit-sysinfo.c
195
+++ b/hw/misc/iotkit-sysinfo.c
196
@@ -XXX,XX +XXX,XX @@
197
/*
198
* This is a model of the "system information block" which is part of the
199
* Arm IoTKit and documented in
200
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
201
+ * https://developer.arm.com/documentation/ecm0601256/latest
202
* It consists of 2 read-only version/config registers, plus the
203
* usual ID registers.
204
*/
205
diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c
206
index XXXXXXX..XXXXXXX 100644
207
--- a/hw/misc/mps2-fpgaio.c
208
+++ b/hw/misc/mps2-fpgaio.c
209
@@ -XXX,XX +XXX,XX @@
210
/* This is a model of the "FPGA system control and I/O" block found
211
* in the AN505 FPGA image for the MPS2 devboard.
212
* It is documented in AN505:
213
- * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
214
+ * https://developer.arm.com/documentation/dai0505/latest/
215
*/
216
217
#include "qemu/osdep.h"
218
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
219
index XXXXXXX..XXXXXXX 100644
220
--- a/hw/misc/mps2-scc.c
221
+++ b/hw/misc/mps2-scc.c
222
@@ -XXX,XX +XXX,XX @@
223
* found in the FPGA images of MPS2 development boards.
224
*
225
* Documentation of it can be found in the MPS2 TRM:
226
- * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html
227
+ * https://developer.arm.com/documentation/100112/latest/
228
* and also in the Application Notes documenting individual FPGA images.
229
*/
230
231
--
232
2.20.1
233
234
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