ARM queue: mostly patches from me, but also the Smartfusion2 board.

The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:

Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921

for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:

msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)

* more preparatory work for v8M support

* convert some omap devices away from old_mmio

* remove out of date ARM ARM section references in comments

* add the Smartfusion2 board

Peter Maydell (26):

target/arm: Implement MSR/MRS access to NS banked registers

nvic: Add banked exception states

nvic: Add cached vectpending_is_s_banked state

nvic: Add cached vectpending_prio state

nvic: Implement AIRCR changes for v8M

nvic: Make ICSR.RETTOBASE handle banked exceptions

nvic: Implement NVIC_ITNS<n> registers

nvic: Handle banked exceptions in nvic_recompute_state()

nvic: Make set_pending and clear_pending take a secure parameter

nvic: Make SHPR registers banked

nvic: Compare group priority for escalation to HF

nvic: In escalation to HardFault, support HF not being priority -1

nvic: Implement v8M changes to fixed priority exceptions

nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear

nvic: Handle v8M changes in nvic_exec_prio()

target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()

nvic: Make ICSR banked for v8M

nvic: Make SHCSR banked for v8M

nvic: Support banked exceptions in acknowledge and complete

target/arm: Remove out of date ARM ARM section references in A64 decoder

hw/arm/palm.c: Don't use old_mmio for static_ops

hw/gpio/omap_gpio.c: Don't use old_mmio

hw/timer/omap_synctimer.c: Don't use old_mmio

hw/timer/omap_gptimer: Don't use old_mmio

hw/i2c/omap_i2c.c: Don't use old_mmio

hw/arm/omap2.c: Don't use old_mmio

Subbaraya Sundeep (5):

msf2: Add Smartfusion2 System timer

msf2: Microsemi Smartfusion2 System Register block

msf2: Add Smartfusion2 SPI controller

msf2: Add Smartfusion2 SoC

msf2: Add Emcraft's Smartfusion2 SOM kit

hw/arm/Makefile.objs | 1 +

hw/misc/Makefile.objs | 1 +

hw/ssi/Makefile.objs | 1 +

hw/timer/Makefile.objs | 1 +

include/hw/arm/msf2-soc.h | 67 +++

include/hw/intc/armv7m_nvic.h | 33 +-

include/hw/misc/msf2-sysreg.h | 77 ++++

include/hw/ssi/mss-spi.h | 58 +++

include/hw/timer/mss-timer.h | 64 +++

target/arm/cpu.h | 62 ++-

hw/arm/msf2-soc.c | 238 +++++++++++

hw/arm/msf2-som.c | 105 +++++

hw/arm/omap2.c | 49 ++-

hw/arm/palm.c | 30 +-

hw/gpio/omap_gpio.c | 26 +-

hw/i2c/omap_i2c.c | 44 +-

hw/intc/armv7m_nvic.c | 913 ++++++++++++++++++++++++++++++++++------

hw/misc/msf2-sysreg.c | 160 +++++++

hw/ssi/mss-spi.c | 404 ++++++++++++++++++

hw/timer/mss-timer.c | 289 +++++++++++++

hw/timer/omap_gptimer.c | 49 ++-

hw/timer/omap_synctimer.c | 35 +-

target/arm/cpu.c | 7 +

target/arm/helper.c | 142 ++++++-

target/arm/translate-a64.c | 227 +++++-----

default-configs/arm-softmmu.mak | 1 +

hw/intc/trace-events | 13 +-

hw/misc/trace-events | 5 +

28 files changed, 2735 insertions(+), 367 deletions(-)

create mode 100644 include/hw/arm/msf2-soc.h

create mode 100644 include/hw/misc/msf2-sysreg.h

create mode 100644 include/hw/ssi/mss-spi.h

create mode 100644 include/hw/timer/mss-timer.h

create mode 100644 hw/arm/msf2-soc.c

create mode 100644 hw/arm/msf2-som.c

create mode 100644 hw/misc/msf2-sysreg.c

create mode 100644 hw/ssi/mss-spi.c

create mode 100644 hw/timer/mss-timer.c

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Emulated Emcraft's Smartfusion2 System On Module starter

kit.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20170920201737.25723-6-f4bug@amsat.org

[PMD: drop cpu_model to directly use cpu type]

hw/arm/Makefile.objs | 2 +-

hw/arm/msf2-som.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 106 insertions(+), 1 deletion(-)

create mode 100644 hw/arm/msf2-som.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

--- a/hw/arm/Makefile.objs

+++ b/hw/arm/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o

obj-$(CONFIG_MPS2) += mps2.o

-obj-$(CONFIG_MSF2) += msf2-soc.o

+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o

diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/msf2-som.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.

+ *

+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "qemu/error-report.h"

+#include "hw/boards.h"

+#include "hw/arm/arm.h"

+#include "exec/address-spaces.h"

+#include "qemu/cutils.h"

+#include "hw/arm/msf2-soc.h"

+#include "cpu.h"

+

+#define DDR_BASE_ADDRESS 0xA0000000

+#define DDR_SIZE (64 * M_BYTE)

+

+#define M2S010_ENVM_SIZE (256 * K_BYTE)

+#define M2S010_ESRAM_SIZE (64 * K_BYTE)

+

+static void emcraft_sf2_s2s010_init(MachineState *machine)

+{

+ DeviceState *dev;

+ DeviceState *spi_flash;

+ MSF2State *soc;

+ MachineClass *mc = MACHINE_GET_CLASS(machine);

+ DriveInfo *dinfo = drive_get_next(IF_MTD);

+ qemu_irq cs_line;

+ SSIBus *spi_bus;

+ MemoryRegion *sysmem = get_system_memory();

+ MemoryRegion *ddr = g_new(MemoryRegion, 1);

+

+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {

+ error_report("This board can only be used with CPU %s",

+ mc->default_cpu_type);

+ }

+

+ memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,

+ &error_fatal);

+ memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);

+

+ dev = qdev_create(NULL, TYPE_MSF2_SOC);

+ qdev_prop_set_string(dev, "part-name", "M2S010");

+ qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);

+

+ qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);

+ qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);

+

+ /*

+ * CPU clock and peripheral clocks(APB0, APB1)are configurable

+ * in Libero. CPU clock is divided by APB0 and APB1 divisors for

+ * peripherals. Emcraft's SoM kit comes with these settings by default.

+ */

+ qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);

+ qdev_prop_set_uint32(dev, "apb0div", 2);

+ qdev_prop_set_uint32(dev, "apb1div", 2);

+

+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);

+

+ soc = MSF2_SOC(dev);

+

+ /* Attach SPI flash to SPI0 controller */

+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");

+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");

+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);

+ if (dinfo) {

+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),

+ &error_fatal);

+ }

+ qdev_init_nofail(spi_flash);

+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);

+

+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+ soc->envm_size);

+}

+

+static void emcraft_sf2_machine_init(MachineClass *mc)

+{

+ mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";

+ mc->init = emcraft_sf2_s2s010_init;

+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");

+}

+

+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)

2.7.4

Don't use old_mmio in the memory region ops struct.

hw/arm/omap2.c | 49 +++++++++++++++++++++++++++++++++++++------------

1 file changed, 37 insertions(+), 12 deletions(-)

diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c

--- a/hw/arm/omap2.c

+++ b/hw/arm/omap2.c

@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write(void *opaque, hwaddr addr,

+static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,

+ unsigned size)

+{

+ switch (size) {

+ case 1:

+ return omap_sysctl_read8(opaque, addr);

+ case 2:

+ return omap_badwidth_read32(opaque, addr); /* TODO */

+ case 4:

+ return omap_sysctl_read(opaque, addr);

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static void omap_sysctl_writefn(void *opaque, hwaddr addr,

+ uint64_t value, unsigned size)

+{

+ switch (size) {

+ case 1:

+ omap_sysctl_write8(opaque, addr, value);

+ break;

+ case 2:

+ omap_badwidth_write32(opaque, addr, value); /* TODO */

+ break;

+ case 4:

+ omap_sysctl_write(opaque, addr, value);

+ break;

+ default:

+ g_assert_not_reached();

+ }

+}

+

static const MemoryRegionOps omap_sysctl_ops = {

- .old_mmio = {

- .read = {

- omap_sysctl_read8,

- omap_badwidth_read32,    /* TODO */

- omap_sysctl_read,

- },

- .write = {

- omap_sysctl_write8,

- omap_badwidth_write32,    /* TODO */

- omap_sysctl_write,

- },

- },

+ .read = omap_sysctl_readfn,

+ .write = omap_sysctl_writefn,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 4,

.endianness = DEVICE_NATIVE_ENDIAN,

};

2.7.4

Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()

functions take a bool indicating whether to pend the secure

or non-secure version of a banked interrupt, and update the

callsites accordingly.

In most callsites we can simply pass the correct security

state in; in a couple of cases we use TODO comments to indicate

that we will return the code in a subsequent commit.

target/arm/cpu.h | 14 ++++++++++-

hw/intc/armv7m_nvic.c | 64 ++++++++++++++++++++++++++++++++++++++-------------

target/arm/helper.c | 24 +++++++++++--------

hw/intc/trace-events | 4 ++--

4 files changed, 77 insertions(+), 29 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)

return true;

}

#endif

-void armv7m_nvic_set_pending(void *opaque, int irq);

+/**

+ * armv7m_nvic_set_pending: mark the specified exception as pending

+ * @opaque: the NVIC

+ * @irq: the exception number to mark pending

+ * @secure: false for non-banked exceptions or for the nonsecure

+ * version of a banked exception, true for the secure version of a banked

+ * exception.

+ *

+ * Marks the specified exception as pending. Note that we will assert()

+ * if @secure is true and @irq does not specify one of the fixed set

+ * of architecturally banked exceptions.

+ */

+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);

void armv7m_nvic_acknowledge_irq(void *opaque);

/**

* armv7m_nvic_complete_irq: complete specified interrupt or exception

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)

qemu_set_irq(s->excpout, lvl);

}

-static void armv7m_nvic_clear_pending(void *opaque, int irq)

+/**

+ * armv7m_nvic_clear_pending: mark the specified exception as not pending

+ * @opaque: the NVIC

+ * @irq: the exception number to mark as not pending

+ * @secure: false for non-banked exceptions or for the nonsecure

+ * version of a banked exception, true for the secure version of a banked

+ * exception.

+ *

+ * Marks the specified exception as not pending. Note that we will assert()

+ * if @secure is true and @irq does not specify one of the fixed set

+ * of architecturally banked exceptions.

+ */

+static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)

{

NVICState *s = (NVICState *)opaque;

VecInfo *vec;

assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);

- vec = &s->vectors[irq];

- trace_nvic_clear_pending(irq, vec->enabled, vec->prio);

+ if (secure) {

+ assert(exc_is_banked(irq));

+ vec = &s->sec_vectors[irq];

+ } else {

+ vec = &s->vectors[irq];

+ }

+ trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);

if (vec->pending) {

vec->pending = 0;

nvic_irq_update(s);

}

-void armv7m_nvic_set_pending(void *opaque, int irq)

+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)

{

NVICState *s = (NVICState *)opaque;

+ bool banked = exc_is_banked(irq);

VecInfo *vec;

assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);

+ assert(!secure || banked);

- vec = &s->vectors[irq];

- trace_nvic_set_pending(irq, vec->enabled, vec->prio);

+ vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];

+ trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);

if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {

/* If a synchronous exception is pending then it may be

@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq)

"(current priority %d)\n", irq, running);

}

- /* We can do the escalation, so we take HardFault instead */

+ /* We can do the escalation, so we take HardFault instead.

+ * If BFHFNMINS is set then we escalate to the banked HF for

+ * the target security state of the original exception; otherwise

+ * we take a Secure HardFault.

+ */

irq = ARMV7M_EXCP_HARD;

- vec = &s->vectors[irq];

+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&

+ (secure ||

+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {

+ vec = &s->sec_vectors[irq];

+ } else {

+ vec = &s->vectors[irq];

+ }

+ /* HF may be banked but there is only one shared HFSR */

s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;

@@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level)

if (level != vec->level) {

vec->level = level;

if (level) {

- armv7m_nvic_set_pending(s, n);

+ armv7m_nvic_set_pending(s, n, false);

}

}

}

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

}

case 0xd04: /* Interrupt Control State. */

if (value & (1 << 31)) {

- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);

+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);

}

if (value & (1 << 28)) {

- armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);

+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);

} else if (value & (1 << 27)) {

- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);

+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);

}

if (value & (1 << 26)) {

- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);

+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);

} else if (value & (1 << 25)) {

- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);

+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);

}

break;

case 0xd08: /* Vector Table Offset. */

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

{

int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;

if (excnum < s->num_irq) {

- armv7m_nvic_set_pending(s, excnum);

+ armv7m_nvic_set_pending(s, excnum, false);

}

break;

}

@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)

/* SysTick just asked us to pend its exception.

* (This is different from an external interrupt line's

* behaviour.)

+ * TODO: when we implement the banked systicks we must make

+ * this pend the correct banked exception.

*/

- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);

+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);

}

}

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

* stack, directly take a usage fault on the current stack.

*/

env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);

v7m_exception_taken(cpu, excret);

qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "

"stackframe: failed exception return integrity check\n");

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

* exception return excret specified then this is a UsageFault.

*/

if (return_to_handler != arm_v7m_is_handler_mode(env)) {

- /* Take an INVPC UsageFault by pushing the stack again. */

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

+ /* Take an INVPC UsageFault by pushing the stack again.

+ * TODO: the v8M version of this code should target the

+ * background state for this exception.

+ */

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);

env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;

v7m_push_stack(cpu);

v7m_exception_taken(cpu, excret);

@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)

handle it. */

switch (cs->exception_index) {

case EXCP_UDEF:

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);

env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;

break;

case EXCP_NOCP:

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);

env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;

break;

case EXCP_INVSTATE:

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);

env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;

break;

case EXCP_SWI:

/* The PC already points to the next instruction. */

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);

break;

case EXCP_PREFETCH_ABORT:

case EXCP_DATA_ABORT:

@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)

env->v7m.bfar);

break;

}

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);

break;

default:

/* All other FSR values are either MPU faults or "can't happen

@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)

env->v7m.mmfar[env->v7m.secure]);

break;

}

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,

+ env->v7m.secure);

break;

}

break;

@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)

return;

}

}

- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);

break;

case EXCP_IRQ:

break;

diff --git a/hw/intc/trace-events b/hw/intc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/trace-events

+++ b/hw/intc/trace-events

@@ -XXX,XX +XXX,XX @@ nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"

nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"

nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"

nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"

-nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)"

-nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)"

+nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"

+nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"

nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"

nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"

nvic_complete_irq(int irq) "NVIC complete IRQ %d"

2.7.4

In the A64 decoder, we have a lot of references to section numbers

from version A.a of the v8A ARM ARM (DDI0487). This version of the

document is now long obsolete (we are currently on revision B.a),

and various intervening versions renumbered all the sections.

The most recent B.a version of the document doesn't assign

section numbers at all to the individual instruction classes

in the way that the various A.x versions did. The simplest thing

to do is just to delete all the out of date C.x.x references.

target/arm/translate-a64.c | 227 +++++++++++++++++++++++----------------------

1 file changed, 114 insertions(+), 113 deletions(-)

@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,

}

/*

- * the instruction disassembly implemented here matches

- * the instruction encoding classifications in chapter 3 (C3)

- * of the ARM Architecture Reference Manual (DDI0487A_a)

+ * The instruction disassembly implemented here matches

+ * the instruction encoding classifications in chapter C4

+ * of the ARM Architecture Reference Manual (DDI0487B_a);

+ * classification names and decode diagrams here should generally

+ * match up with those in the manual.

*/

-/* C3.2.7 Unconditional branch (immediate)

+/* Unconditional branch (immediate)

* 31 30 26 25 0

* +----+-----------+-------------------------------------+

* | op | 0 0 1 0 1 | imm26 |

@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)

uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;

if (insn & (1U << 31)) {

- /* C5.6.26 BL Branch with link */

+ /* BL Branch with link */

tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);