1
ARM queue: mostly patches from me, but also the Smartfusion2 board.
1
Arm queue; some of the simpler stuff, things other have reviewed (thanks!), etc.
2
2
3
thanks
4
-- PMM
3
-- PMM
5
4
6
The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:
5
The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a:
7
6
8
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)
7
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 13:53:05 +0100)
9
8
10
are available in the git repository at:
9
are available in the Git repository at:
11
10
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200605
13
12
14
for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:
13
for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812:
15
14
16
msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)
15
target/arm: Convert Neon one-register-and-immediate insns to decodetree (2020-06-05 17:23:10 +0100)
17
16
18
----------------------------------------------------------------
17
----------------------------------------------------------------
19
target-arm queue:
18
target-arm queue:
20
* more preparatory work for v8M support
19
hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly
21
* convert some omap devices away from old_mmio
20
hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
22
* remove out of date ARM ARM section references in comments
21
hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
23
* add the Smartfusion2 board
22
target/arm: Convert crypto insns to gvec
23
hw/adc/stm32f2xx_adc: Correct memory region size and access size
24
tests/acceptance: Add a boot test for the xlnx-versal-virt machine
25
docs/system: Document Aspeed boards
26
raspi: Add model of the USB controller
27
target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree
24
28
25
----------------------------------------------------------------
29
----------------------------------------------------------------
26
Peter Maydell (26):
30
Cédric Le Goater (1):
27
target/arm: Implement MSR/MRS access to NS banked registers
31
docs/system: Document Aspeed boards
28
nvic: Add banked exception states
29
nvic: Add cached vectpending_is_s_banked state
30
nvic: Add cached vectpending_prio state
31
nvic: Implement AIRCR changes for v8M
32
nvic: Make ICSR.RETTOBASE handle banked exceptions
33
nvic: Implement NVIC_ITNS<n> registers
34
nvic: Handle banked exceptions in nvic_recompute_state()
35
nvic: Make set_pending and clear_pending take a secure parameter
36
nvic: Make SHPR registers banked
37
nvic: Compare group priority for escalation to HF
38
nvic: In escalation to HardFault, support HF not being priority -1
39
nvic: Implement v8M changes to fixed priority exceptions
40
nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
41
nvic: Handle v8M changes in nvic_exec_prio()
42
target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
43
nvic: Make ICSR banked for v8M
44
nvic: Make SHCSR banked for v8M
45
nvic: Support banked exceptions in acknowledge and complete
46
target/arm: Remove out of date ARM ARM section references in A64 decoder
47
hw/arm/palm.c: Don't use old_mmio for static_ops
48
hw/gpio/omap_gpio.c: Don't use old_mmio
49
hw/timer/omap_synctimer.c: Don't use old_mmio
50
hw/timer/omap_gptimer: Don't use old_mmio
51
hw/i2c/omap_i2c.c: Don't use old_mmio
52
hw/arm/omap2.c: Don't use old_mmio
53
32
54
Subbaraya Sundeep (5):
33
Eden Mikitas (2):
55
msf2: Add Smartfusion2 System timer
34
hw/ssi/imx_spi: changed while statement to prevent underflow
56
msf2: Microsemi Smartfusion2 System Register block
35
hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave
57
msf2: Add Smartfusion2 SPI controller
58
msf2: Add Smartfusion2 SoC
59
msf2: Add Emcraft's Smartfusion2 SOM kit
60
36
61
hw/arm/Makefile.objs | 1 +
37
Paul Zimmerman (7):
62
hw/misc/Makefile.objs | 1 +
38
raspi: add BCM2835 SOC MPHI emulation
63
hw/ssi/Makefile.objs | 1 +
39
dwc-hsotg (dwc2) USB host controller register definitions
64
hw/timer/Makefile.objs | 1 +
40
dwc-hsotg (dwc2) USB host controller state definitions
65
include/hw/arm/msf2-soc.h | 67 +++
41
dwc-hsotg (dwc2) USB host controller emulation
66
include/hw/intc/armv7m_nvic.h | 33 +-
42
usb: add short-packet handling to usb-storage driver
67
include/hw/misc/msf2-sysreg.h | 77 ++++
43
wire in the dwc-hsotg (dwc2) USB host controller emulation
68
include/hw/ssi/mss-spi.h | 58 +++
44
raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
69
include/hw/timer/mss-timer.h | 64 +++
70
target/arm/cpu.h | 62 ++-
71
hw/arm/msf2-soc.c | 238 +++++++++++
72
hw/arm/msf2-som.c | 105 +++++
73
hw/arm/omap2.c | 49 ++-
74
hw/arm/palm.c | 30 +-
75
hw/gpio/omap_gpio.c | 26 +-
76
hw/i2c/omap_i2c.c | 44 +-
77
hw/intc/armv7m_nvic.c | 913 ++++++++++++++++++++++++++++++++++------
78
hw/misc/msf2-sysreg.c | 160 +++++++
79
hw/ssi/mss-spi.c | 404 ++++++++++++++++++
80
hw/timer/mss-timer.c | 289 +++++++++++++
81
hw/timer/omap_gptimer.c | 49 ++-
82
hw/timer/omap_synctimer.c | 35 +-
83
target/arm/cpu.c | 7 +
84
target/arm/helper.c | 142 ++++++-
85
target/arm/translate-a64.c | 227 +++++-----
86
default-configs/arm-softmmu.mak | 1 +
87
hw/intc/trace-events | 13 +-
88
hw/misc/trace-events | 5 +
89
28 files changed, 2735 insertions(+), 367 deletions(-)
90
create mode 100644 include/hw/arm/msf2-soc.h
91
create mode 100644 include/hw/misc/msf2-sysreg.h
92
create mode 100644 include/hw/ssi/mss-spi.h
93
create mode 100644 include/hw/timer/mss-timer.h
94
create mode 100644 hw/arm/msf2-soc.c
95
create mode 100644 hw/arm/msf2-som.c
96
create mode 100644 hw/misc/msf2-sysreg.c
97
create mode 100644 hw/ssi/mss-spi.c
98
create mode 100644 hw/timer/mss-timer.c
99
45
46
Peter Maydell (9):
47
target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
48
target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
49
target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree
50
target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
51
target/arm: Convert Neon narrowing shifts with op==8 to decodetree
52
target/arm: Convert Neon narrowing shifts with op==9 to decodetree
53
target/arm: Convert Neon VSHLL, VMOVL to decodetree
54
target/arm: Convert VCVT fixed-point ops to decodetree
55
target/arm: Convert Neon one-register-and-immediate insns to decodetree
56
57
Philippe Mathieu-Daudé (3):
58
hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
59
hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
60
hw/adc/stm32f2xx_adc: Correct memory region size and access size
61
62
Richard Henderson (6):
63
target/arm: Convert aes and sm4 to gvec helpers
64
target/arm: Convert rax1 to gvec helpers
65
target/arm: Convert sha512 and sm3 to gvec helpers
66
target/arm: Convert sha1 and sha256 to gvec helpers
67
target/arm: Split helper_crypto_sha1_3reg
68
target/arm: Split helper_crypto_sm3tt
69
70
Thomas Huth (1):
71
tests/acceptance: Add a boot test for the xlnx-versal-virt machine
72
73
docs/system/arm/aspeed.rst | 85 ++
74
docs/system/target-arm.rst | 1 +
75
hw/usb/hcd-dwc2.h | 190 +++++
76
include/hw/arm/bcm2835_peripherals.h | 5 +-
77
include/hw/misc/bcm2835_mphi.h | 44 +
78
include/hw/usb/dwc2-regs.h | 899 ++++++++++++++++++++
79
target/arm/helper.h | 45 +-
80
target/arm/translate-a64.h | 3 +
81
target/arm/vec_internal.h | 33 +
82
target/arm/neon-dp.decode | 214 ++++-
83
hw/adc/stm32f2xx_adc.c | 4 +-
84
hw/arm/bcm2835_peripherals.c | 38 +-
85
hw/arm/pxa2xx.c | 66 +-
86
hw/input/pxa2xx_keypad.c | 10 +-
87
hw/misc/bcm2835_mphi.c | 191 +++++
88
hw/ssi/imx_spi.c | 4 +-
89
hw/usb/dev-storage.c | 15 +-
90
hw/usb/hcd-dwc2.c | 1417 ++++++++++++++++++++++++++++++++
91
target/arm/crypto_helper.c | 267 ++++--
92
target/arm/translate-a64.c | 198 ++---
93
target/arm/translate-neon.inc.c | 796 ++++++++++++++----
94
target/arm/translate.c | 539 +-----------
95
target/arm/vec_helper.c | 12 +-
96
hw/misc/Makefile.objs | 1 +
97
hw/usb/Kconfig | 5 +
98
hw/usb/Makefile.objs | 1 +
99
hw/usb/trace-events | 50 ++
100
tests/acceptance/boot_linux_console.py | 35 +-
101
28 files changed, 4258 insertions(+), 910 deletions(-)
102
create mode 100644 docs/system/arm/aspeed.rst
103
create mode 100644 hw/usb/hcd-dwc2.h
104
create mode 100644 include/hw/misc/bcm2835_mphi.h
105
create mode 100644 include/hw/usb/dwc2-regs.h
106
create mode 100644 target/arm/vec_internal.h
107
create mode 100644 hw/misc/bcm2835_mphi.c
108
create mode 100644 hw/usb/hcd-dwc2.c
109
diff view generated by jsdifflib
1
In armv7m_nvic_set_pending() we have to compare the
1
From: Eden Mikitas <e.mikitas@gmail.com>
2
priority of an exception against the execution priority
3
to decide whether it needs to be escalated to HardFault.
4
In the specification this is a comparison against the
5
exception's group priority; for v7M we implemented it
6
as a comparison against the raw exception priority
7
because the two comparisons will always give the
8
same answer. For v8M the existence of AIRCR.PRIS and
9
the possibility of different PRIGROUP values for secure
10
and nonsecure exceptions means we need to explicitly
11
calculate the vector's group priority for this check.
12
2
3
The while statement in question only checked if tx_burst is not 0.
4
tx_burst is a signed int, which is assigned the value put by the
5
guest driver in ECSPI_CONREG. The burst length can be anywhere
6
between 1 and 4096, and since tx_burst is always decremented by 8
7
it could possibly underflow, causing an infinite loop.
8
9
Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 1505240046-11454-12-git-send-email-peter.maydell@linaro.org
16
---
12
---
17
hw/intc/armv7m_nvic.c | 2 +-
13
hw/ssi/imx_spi.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
19
15
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
18
--- a/hw/ssi/imx_spi.c
23
+++ b/hw/intc/armv7m_nvic.c
19
+++ b/hw/ssi/imx_spi.c
24
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
20
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
25
int running = nvic_exec_prio(s);
21
26
bool escalate = false;
22
rx = 0;
27
23
28
- if (vec->prio >= running) {
24
- while (tx_burst) {
29
+ if (exc_group_prio(s, vec->prio, secure) >= running) {
25
+ while (tx_burst > 0) {
30
trace_nvic_escalate_prio(irq, vec->prio, running);
26
uint8_t byte = tx & 0xff;
31
escalate = true;
27
32
} else if (!vec->enabled) {
28
DPRINTF("writing 0x%02x\n", (uint32_t)byte);
33
--
29
--
34
2.7.4
30
2.20.1
35
31
36
32
diff view generated by jsdifflib
1
When escalating to HardFault, we must go into Lockup if we
1
From: Eden Mikitas <e.mikitas@gmail.com>
2
can't take the synchronous HardFault because the current
3
execution priority is already at or below the priority of
4
HardFault. In v7M HF is always priority -1 so a simple < 0
5
comparison sufficed; in v8M the priority of HardFault can
6
vary depending on whether it is a Secure or NonSecure
7
HardFault, so we must check against the priority of the
8
HardFault exception vector we're about to use.
9
2
3
When inserting the value retrieved (rx) from the spi slave, rx is pushed to
4
rx_fifo after being cast to uint8_t. rx_fifo is a fifo32, and the rx
5
register the driver uses is also 32 bit. This zeroes the 24 most
6
significant bits of rx. This proved problematic with devices that expect to
7
use the whole 32 bits of the rx register.
8
9
Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-13-git-send-email-peter.maydell@linaro.org
13
---
12
---
14
hw/intc/armv7m_nvic.c | 23 ++++++++++++-----------
13
hw/ssi/imx_spi.c | 2 +-
15
1 file changed, 12 insertions(+), 11 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
16
15
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
18
--- a/hw/ssi/imx_spi.c
20
+++ b/hw/intc/armv7m_nvic.c
19
+++ b/hw/ssi/imx_spi.c
21
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
20
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
21
if (fifo32_is_full(&s->rx_fifo)) {
22
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
23
} else {
24
- fifo32_push(&s->rx_fifo, (uint8_t)rx);
25
+ fifo32_push(&s->rx_fifo, rx);
22
}
26
}
23
27
24
if (escalate) {
28
if (s->burst_length <= 0) {
25
- if (running < 0) {
26
- /* We want to escalate to HardFault but we can't take a
27
- * synchronous HardFault at this point either. This is a
28
- * Lockup condition due to a guest bug. We don't model
29
- * Lockup, so report via cpu_abort() instead.
30
- */
31
- cpu_abort(&s->cpu->parent_obj,
32
- "Lockup: can't escalate %d to HardFault "
33
- "(current priority %d)\n", irq, running);
34
- }
35
36
- /* We can do the escalation, so we take HardFault instead.
37
+ /* We need to escalate this exception to a synchronous HardFault.
38
* If BFHFNMINS is set then we escalate to the banked HF for
39
* the target security state of the original exception; otherwise
40
* we take a Secure HardFault.
41
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
42
} else {
43
vec = &s->vectors[irq];
44
}
45
+ if (running <= vec->prio) {
46
+ /* We want to escalate to HardFault but we can't take the
47
+ * synchronous HardFault at this point either. This is a
48
+ * Lockup condition due to a guest bug. We don't model
49
+ * Lockup, so report via cpu_abort() instead.
50
+ */
51
+ cpu_abort(&s->cpu->parent_obj,
52
+ "Lockup: can't escalate %d to HardFault "
53
+ "(current priority %d)\n", irq, running);
54
+ }
55
+
56
/* HF may be banked but there is only one shared HFSR */
57
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
58
}
59
--
29
--
60
2.7.4
30
2.20.1
61
31
62
32
diff view generated by jsdifflib
1
Don't use the old_mmio in the memory region ops struct.
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
hw_error() calls exit(). This a bit overkill when we can log
4
the accesses as unimplemented or guest error.
5
6
When fuzzing the devices, we don't want the whole process to
7
exit. Replace some hw_error() calls by qemu_log_mask()
8
(missed in commit 5a0001ec7e).
9
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20200525114123.21317-2-f4bug@amsat.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-4-git-send-email-peter.maydell@linaro.org
6
---
14
---
7
hw/timer/omap_synctimer.c | 35 +++++++++++++++++++++--------------
15
hw/input/pxa2xx_keypad.c | 10 +++++++---
8
1 file changed, 21 insertions(+), 14 deletions(-)
16
1 file changed, 7 insertions(+), 3 deletions(-)
9
17
10
diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
18
diff --git a/hw/input/pxa2xx_keypad.c b/hw/input/pxa2xx_keypad.c
11
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/timer/omap_synctimer.c
20
--- a/hw/input/pxa2xx_keypad.c
13
+++ b/hw/timer/omap_synctimer.c
21
+++ b/hw/input/pxa2xx_keypad.c
14
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
22
@@ -XXX,XX +XXX,XX @@
23
*/
24
25
#include "qemu/osdep.h"
26
-#include "hw/hw.h"
27
+#include "qemu/log.h"
28
#include "hw/irq.h"
29
#include "migration/vmstate.h"
30
#include "hw/arm/pxa.h"
31
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
32
return s->kpkdi;
33
break;
34
default:
35
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
36
+ qemu_log_mask(LOG_GUEST_ERROR,
37
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
38
+ __func__, offset);
39
}
40
41
return 0;
42
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
43
break;
44
45
default:
46
- hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
47
+ qemu_log_mask(LOG_GUEST_ERROR,
48
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
49
+ __func__, offset);
15
}
50
}
16
}
51
}
17
52
18
-static void omap_synctimer_write(void *opaque, hwaddr addr,
19
- uint32_t value)
20
+static uint64_t omap_synctimer_readfn(void *opaque, hwaddr addr,
21
+ unsigned size)
22
+{
23
+ switch (size) {
24
+ case 1:
25
+ return omap_badwidth_read32(opaque, addr);
26
+ case 2:
27
+ return omap_synctimer_readh(opaque, addr);
28
+ case 4:
29
+ return omap_synctimer_readw(opaque, addr);
30
+ default:
31
+ g_assert_not_reached();
32
+ }
33
+}
34
+
35
+static void omap_synctimer_writefn(void *opaque, hwaddr addr,
36
+ uint64_t value, unsigned size)
37
{
38
OMAP_BAD_REG(addr);
39
}
40
41
static const MemoryRegionOps omap_synctimer_ops = {
42
- .old_mmio = {
43
- .read = {
44
- omap_badwidth_read32,
45
- omap_synctimer_readh,
46
- omap_synctimer_readw,
47
- },
48
- .write = {
49
- omap_badwidth_write32,
50
- omap_synctimer_write,
51
- omap_synctimer_write,
52
- },
53
- },
54
+ .read = omap_synctimer_readfn,
55
+ .write = omap_synctimer_writefn,
56
+ .valid.min_access_size = 1,
57
+ .valid.max_access_size = 4,
58
.endianness = DEVICE_NATIVE_ENDIAN,
59
};
60
61
--
53
--
62
2.7.4
54
2.20.1
63
55
64
56
diff view generated by jsdifflib
1
Update the static_ops functions to use new-style mmio
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
rather than the legacy old_mmio functions.
2
3
3
Replace printf() calls by qemu_log_mask(), which is disabled
4
by default. This avoid flooding the terminal when fuzzing the
5
device.
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200525114123.21317-3-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505580378-9044-2-git-send-email-peter.maydell@linaro.org
7
---
11
---
8
hw/arm/palm.c | 30 ++++++++++--------------------
12
hw/arm/pxa2xx.c | 66 ++++++++++++++++++++++++++++++++++++-------------
9
1 file changed, 10 insertions(+), 20 deletions(-)
13
1 file changed, 49 insertions(+), 17 deletions(-)
10
14
11
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
15
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/palm.c
17
--- a/hw/arm/pxa2xx.c
14
+++ b/hw/arm/palm.c
18
+++ b/hw/arm/pxa2xx.c
15
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
16
#include "exec/address-spaces.h"
20
#include "sysemu/blockdev.h"
17
#include "cpu.h"
21
#include "sysemu/qtest.h"
18
22
#include "qemu/cutils.h"
19
-static uint32_t static_readb(void *opaque, hwaddr offset)
23
+#include "qemu/log.h"
20
+static uint64_t static_read(void *opaque, hwaddr offset, unsigned size)
24
21
{
25
static struct {
22
- uint32_t *val = (uint32_t *) opaque;
26
hwaddr io_base;
23
- return *val >> ((offset & 3) << 3);
27
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
24
-}
28
return s->pm_regs[addr >> 2];
25
+ uint32_t *val = (uint32_t *)opaque;
29
default:
26
+ uint32_t sizemask = 7 >> size;
30
fail:
27
31
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
28
-static uint32_t static_readh(void *opaque, hwaddr offset)
32
+ qemu_log_mask(LOG_GUEST_ERROR,
29
-{
33
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
30
- uint32_t *val = (uint32_t *) opaque;
34
+ __func__, addr);
31
- return *val >> ((offset & 1) << 3);
35
break;
32
-}
36
}
37
return 0;
38
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr,
39
s->pm_regs[addr >> 2] = value;
40
break;
41
}
33
-
42
-
34
-static uint32_t static_readw(void *opaque, hwaddr offset)
43
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
35
-{
44
+ qemu_log_mask(LOG_GUEST_ERROR,
36
- uint32_t *val = (uint32_t *) opaque;
45
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
37
- return *val >> ((offset & 0) << 3);
46
+ __func__, addr);
38
+ return *val >> ((offset & sizemask) << 3);
47
break;
39
}
48
}
40
49
}
41
-static void static_write(void *opaque, hwaddr offset,
50
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
42
- uint32_t value)
51
return s->cm_regs[CCCR >> 2] | (3 << 28);
43
+static void static_write(void *opaque, hwaddr offset, uint64_t value,
52
44
+ unsigned size)
53
default:
45
{
54
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
46
#ifdef SPY
55
+ qemu_log_mask(LOG_GUEST_ERROR,
47
printf("%s: value %08lx written at " PA_FMT "\n",
56
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
48
@@ -XXX,XX +XXX,XX @@ static void static_write(void *opaque, hwaddr offset,
57
+ __func__, addr);
49
}
58
break;
50
59
}
51
static const MemoryRegionOps static_ops = {
60
return 0;
52
- .old_mmio = {
61
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr,
53
- .read = { static_readb, static_readh, static_readw, },
62
break;
54
- .write = { static_write, static_write, static_write, },
63
55
- },
64
default:
56
+ .read = static_read,
65
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
57
+ .write = static_write,
66
+ qemu_log_mask(LOG_GUEST_ERROR,
58
+ .valid.min_access_size = 1,
67
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
59
+ .valid.max_access_size = 4,
68
+ __func__, addr);
60
.endianness = DEVICE_NATIVE_ENDIAN,
69
break;
61
};
70
}
71
}
72
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
73
return s->mm_regs[addr >> 2];
74
/* fall through */
75
default:
76
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
77
+ qemu_log_mask(LOG_GUEST_ERROR,
78
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
79
+ __func__, addr);
80
break;
81
}
82
return 0;
83
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr,
84
}
85
86
default:
87
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
88
+ qemu_log_mask(LOG_GUEST_ERROR,
89
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
90
+ __func__, addr);
91
break;
92
}
93
}
94
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
95
case SSACD:
96
return s->ssacd;
97
default:
98
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
99
+ qemu_log_mask(LOG_GUEST_ERROR,
100
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
101
+ __func__, addr);
102
break;
103
}
104
return 0;
105
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
106
break;
107
108
default:
109
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
110
+ qemu_log_mask(LOG_GUEST_ERROR,
111
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
112
+ __func__, addr);
113
break;
114
}
115
}
116
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
117
else
118
return s->last_swcr;
119
default:
120
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
121
+ qemu_log_mask(LOG_GUEST_ERROR,
122
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
123
+ __func__, addr);
124
break;
125
}
126
return 0;
127
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
128
break;
129
130
default:
131
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
132
+ qemu_log_mask(LOG_GUEST_ERROR,
133
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
134
+ __func__, addr);
135
}
136
}
137
138
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
139
s->ibmr = 0;
140
return s->ibmr;
141
default:
142
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
143
+ qemu_log_mask(LOG_GUEST_ERROR,
144
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
145
+ __func__, addr);
146
break;
147
}
148
return 0;
149
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
150
break;
151
152
default:
153
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
154
+ qemu_log_mask(LOG_GUEST_ERROR,
155
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
156
+ __func__, addr);
157
}
158
}
159
160
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
161
}
162
return 0;
163
default:
164
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
165
+ qemu_log_mask(LOG_GUEST_ERROR,
166
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
167
+ __func__, addr);
168
break;
169
}
170
return 0;
171
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
172
}
173
break;
174
default:
175
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
176
+ qemu_log_mask(LOG_GUEST_ERROR,
177
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
178
+ __func__, addr);
179
}
180
}
181
182
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
183
case ICFOR:
184
return s->rx_len;
185
default:
186
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
187
+ qemu_log_mask(LOG_GUEST_ERROR,
188
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
189
+ __func__, addr);
190
break;
191
}
192
return 0;
193
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
194
case ICFOR:
195
break;
196
default:
197
- printf("%s: Bad register " REG_FMT "\n", __func__, addr);
198
+ qemu_log_mask(LOG_GUEST_ERROR,
199
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
200
+ __func__, addr);
201
}
202
}
62
203
63
--
204
--
64
2.7.4
205
2.20.1
65
206
66
207
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Smartfusion2 SoC has hardened Microcontroller subsystem
3
With this conversion, we will be able to use the same helpers
4
and flash based FPGA fabric. This patch adds support for
4
with sve. In particular, pass 3 vector parameters for the
5
Microcontroller subsystem in the SoC.
5
3-operand operations; for advsimd the destination register
6
6
is also an input.
7
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
7
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
This also fixes a bug in which we failed to clear the high bits
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
of the SVE register after an AdvSIMD operation.
10
Message-id: 20170920201737.25723-5-f4bug@amsat.org
10
11
[PMD: drop cpu_model to directly use cpu type, check m3clk non null]
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200514212831.31248-2-richard.henderson@linaro.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
15
---
14
hw/arm/Makefile.objs | 1 +
16
target/arm/helper.h | 6 ++--
15
include/hw/arm/msf2-soc.h | 67 +++++++++++
17
target/arm/vec_internal.h | 33 +++++++++++++++++
16
hw/arm/msf2-soc.c | 238 ++++++++++++++++++++++++++++++++++++++++
18
target/arm/crypto_helper.c | 72 +++++++++++++++++++++++++++-----------
17
default-configs/arm-softmmu.mak | 1 +
19
target/arm/translate-a64.c | 55 ++++++++++++++++++-----------
18
4 files changed, 307 insertions(+)
20
target/arm/translate.c | 27 +++++++-------
19
create mode 100644 include/hw/arm/msf2-soc.h
21
target/arm/vec_helper.c | 12 +------
20
create mode 100644 hw/arm/msf2-soc.c
22
6 files changed, 138 insertions(+), 67 deletions(-)
21
23
create mode 100644 target/arm/vec_internal.h
22
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
24
25
diff --git a/target/arm/helper.h b/target/arm/helper.h
23
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/Makefile.objs
27
--- a/target/arm/helper.h
25
+++ b/hw/arm/Makefile.objs
28
+++ b/target/arm/helper.h
26
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
29
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr)
27
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
30
DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr)
28
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
31
DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
29
obj-$(CONFIG_MPS2) += mps2.o
32
30
+obj-$(CONFIG_MSF2) += msf2-soc.o
33
-DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
31
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
34
+DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
36
37
DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
38
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
39
DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
40
DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
41
42
-DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr)
43
-DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
44
+DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
45
+DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
46
47
DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
48
DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
49
diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h
32
new file mode 100644
50
new file mode 100644
33
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
34
--- /dev/null
52
--- /dev/null
35
+++ b/include/hw/arm/msf2-soc.h
53
+++ b/target/arm/vec_internal.h
36
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
37
+/*
55
+/*
38
+ * Microsemi Smartfusion2 SoC
56
+ * ARM AdvSIMD / SVE Vector Helpers
39
+ *
57
+ *
40
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
58
+ * Copyright (c) 2020 Linaro
41
+ *
59
+ *
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
60
+ * This library is free software; you can redistribute it and/or
43
+ * of this software and associated documentation files (the "Software"), to deal
61
+ * modify it under the terms of the GNU Lesser General Public
44
+ * in the Software without restriction, including without limitation the rights
62
+ * License as published by the Free Software Foundation; either
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
63
+ * version 2 of the License, or (at your option) any later version.
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
64
+ *
49
+ * The above copyright notice and this permission notice shall be included in
65
+ * This library is distributed in the hope that it will be useful,
50
+ * all copies or substantial portions of the Software.
66
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
67
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
68
+ * Lesser General Public License for more details.
51
+ *
69
+ *
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
70
+ * You should have received a copy of the GNU Lesser General Public
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
71
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
72
+ */
60
+
73
+
61
+#ifndef HW_ARM_MSF2_SOC_H
74
+#ifndef TARGET_ARM_VEC_INTERNALS_H
62
+#define HW_ARM_MSF2_SOC_H
75
+#define TARGET_ARM_VEC_INTERNALS_H
63
+
76
+
64
+#include "hw/arm/armv7m.h"
77
+static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
65
+#include "hw/timer/mss-timer.h"
78
+{
66
+#include "hw/misc/msf2-sysreg.h"
79
+ uint64_t *d = vd + opr_sz;
67
+#include "hw/ssi/mss-spi.h"
80
+ uintptr_t i;
68
+
81
+
69
+#define TYPE_MSF2_SOC "msf2-soc"
82
+ for (i = opr_sz; i < max_sz; i += 8) {
70
+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
83
+ *d++ = 0;
71
+
84
+ }
72
+#define MSF2_NUM_SPIS 2
85
+}
73
+#define MSF2_NUM_UARTS 2
86
+
74
+
87
+#endif /* TARGET_ARM_VEC_INTERNALS_H */
75
+/*
88
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
76
+ * System timer consists of two programmable 32-bit
89
index XXXXXXX..XXXXXXX 100644
77
+ * decrementing counters that generate individual interrupts to
90
--- a/target/arm/crypto_helper.c
78
+ * the Cortex-M3 processor
91
+++ b/target/arm/crypto_helper.c
79
+ */
80
+#define MSF2_NUM_TIMERS 2
81
+
82
+typedef struct MSF2State {
83
+ /*< private >*/
84
+ SysBusDevice parent_obj;
85
+ /*< public >*/
86
+
87
+ ARMv7MState armv7m;
88
+
89
+ char *cpu_type;
90
+ char *part_name;
91
+ uint64_t envm_size;
92
+ uint64_t esram_size;
93
+
94
+ uint32_t m3clk;
95
+ uint8_t apb0div;
96
+ uint8_t apb1div;
97
+
98
+ MSF2SysregState sysreg;
99
+ MSSTimerState timer;
100
+ MSSSpiState spi[MSF2_NUM_SPIS];
101
+} MSF2State;
102
+
103
+#endif
104
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
105
new file mode 100644
106
index XXXXXXX..XXXXXXX
107
--- /dev/null
108
+++ b/hw/arm/msf2-soc.c
109
@@ -XXX,XX +XXX,XX @@
92
@@ -XXX,XX +XXX,XX @@
110
+/*
93
111
+ * SmartFusion2 SoC emulation.
94
#include "cpu.h"
112
+ *
95
#include "exec/helper-proto.h"
113
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
96
+#include "tcg/tcg-gvec-desc.h"
114
+ *
97
#include "crypto/aes.h"
115
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
98
+#include "vec_internal.h"
116
+ * of this software and associated documentation files (the "Software"), to deal
99
117
+ * in the Software without restriction, including without limitation the rights
100
union CRYPTO_STATE {
118
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
101
uint8_t bytes[16];
119
+ * copies of the Software, and to permit persons to whom the Software is
102
@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
120
+ * furnished to do so, subject to the following conditions:
103
#define CR_ST_WORD(state, i) (state.words[i])
121
+ *
104
#endif
122
+ * The above copyright notice and this permission notice shall be included in
105
123
+ * all copies or substantial portions of the Software.
106
-void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
124
+ *
107
+static void do_crypto_aese(uint64_t *rd, uint64_t *rn,
125
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
108
+ uint64_t *rm, bool decrypt)
126
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
109
{
127
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
110
static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
128
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
111
static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
129
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
112
- uint64_t *rd = vd;
130
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
113
- uint64_t *rm = vm;
131
+ * THE SOFTWARE.
114
union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } };
132
+ */
115
- union CRYPTO_STATE st = { .l = { rd[0], rd[1] } };
133
+
116
+ union CRYPTO_STATE st = { .l = { rn[0], rn[1] } };
134
+#include "qemu/osdep.h"
117
int i;
135
+#include "qapi/error.h"
118
136
+#include "qemu-common.h"
119
- assert(decrypt < 2);
137
+#include "hw/arm/arm.h"
120
-
138
+#include "exec/address-spaces.h"
121
/* xor state vector with round key */
139
+#include "hw/char/serial.h"
122
rk.l[0] ^= st.l[0];
140
+#include "hw/boards.h"
123
rk.l[1] ^= st.l[1];
141
+#include "sysemu/block-backend.h"
124
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
142
+#include "qemu/cutils.h"
125
rd[1] = st.l[1];
143
+#include "hw/arm/msf2-soc.h"
126
}
144
+#include "hw/misc/unimp.h"
127
145
+
128
-void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
146
+#define MSF2_TIMER_BASE 0x40004000
129
+void HELPER(crypto_aese)(void *vd, void *vn, void *vm, uint32_t desc)
147
+#define MSF2_SYSREG_BASE 0x40038000
130
+{
148
+
131
+ intptr_t i, opr_sz = simd_oprsz(desc);
149
+#define ENVM_BASE_ADDRESS 0x60000000
132
+ bool decrypt = simd_data(desc);
150
+
133
+
151
+#define SRAM_BASE_ADDRESS 0x20000000
134
+ for (i = 0; i < opr_sz; i += 16) {
152
+
135
+ do_crypto_aese(vd + i, vn + i, vm + i, decrypt);
153
+#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
136
+ }
154
+
137
+ clear_tail(vd, opr_sz, simd_maxsz(desc));
155
+/*
138
+}
156
+ * eSRAM max size is 80k without SECDED(Single error correction and
139
+
157
+ * dual error detection) feature and 64k with SECDED.
140
+static void do_crypto_aesmc(uint64_t *rd, uint64_t *rm, bool decrypt)
158
+ * We do not support SECDED now.
141
{
159
+ */
142
static uint32_t const mc[][256] = { {
160
+#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
143
/* MixColumns lookup table */
161
+
144
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
162
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
145
0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,
163
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
146
} };
164
+
147
165
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
148
- uint64_t *rd = vd;
166
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
149
- uint64_t *rm = vm;
167
+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
150
union CRYPTO_STATE st = { .l = { rm[0], rm[1] } };
168
+
151
int i;
169
+static void m2sxxx_soc_initfn(Object *obj)
152
170
+{
153
- assert(decrypt < 2);
171
+ MSF2State *s = MSF2_SOC(obj);
154
-
172
+ int i;
155
for (i = 0; i < 16; i += 4) {
173
+
156
CR_ST_WORD(st, i >> 2) =
174
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
157
mc[decrypt][CR_ST_BYTE(st, i)] ^
175
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
158
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
176
+
159
rd[1] = st.l[1];
177
+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
160
}
178
+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
161
179
+
162
+void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc)
180
+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
163
+{
181
+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
164
+ intptr_t i, opr_sz = simd_oprsz(desc);
182
+
165
+ bool decrypt = simd_data(desc);
183
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
166
+
184
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
167
+ for (i = 0; i < opr_sz; i += 16) {
185
+ TYPE_MSS_SPI);
168
+ do_crypto_aesmc(vd + i, vm + i, decrypt);
186
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
169
+ }
187
+ }
170
+ clear_tail(vd, opr_sz, simd_maxsz(desc));
188
+}
171
+}
189
+
172
+
190
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
173
/*
191
+{
174
* SHA-1 logical functions
192
+ MSF2State *s = MSF2_SOC(dev_soc);
175
*/
193
+ DeviceState *dev, *armv7m;
176
@@ -XXX,XX +XXX,XX @@ static uint8_t const sm4_sbox[] = {
194
+ SysBusDevice *busdev;
177
0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
195
+ Error *err = NULL;
178
};
196
+ int i;
179
197
+
180
-void HELPER(crypto_sm4e)(void *vd, void *vn)
198
+ MemoryRegion *system_memory = get_system_memory();
181
+static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
199
+ MemoryRegion *nvm = g_new(MemoryRegion, 1);
182
{
200
+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
183
- uint64_t *rd = vd;
201
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
184
- uint64_t *rn = vn;
202
+
185
- union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
203
+ memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
186
- union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
204
+ &error_fatal);
187
+ union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
205
+ /*
188
+ union CRYPTO_STATE n = { .l = { rm[0], rm[1] } };
206
+ * On power-on, the eNVM region 0x60000000 is automatically
189
uint32_t t, i;
207
+ * remapped to the Cortex-M3 processor executable region
190
208
+ * start address (0x0). We do not support remapping other eNVM,
191
for (i = 0; i < 4; i++) {
209
+ * eSRAM and DDR regions by guest(via Sysreg) currently.
192
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4e)(void *vd, void *vn)
210
+ */
193
rd[1] = d.l[1];
211
+ memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
194
}
212
+ nvm, 0, s->envm_size);
195
213
+
196
-void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
214
+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
197
+void HELPER(crypto_sm4e)(void *vd, void *vn, void *vm, uint32_t desc)
215
+ memory_region_add_subregion(system_memory, 0, nvm_alias);
198
+{
216
+
199
+ intptr_t i, opr_sz = simd_oprsz(desc);
217
+ memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
200
+
218
+ &error_fatal);
201
+ for (i = 0; i < opr_sz; i += 16) {
219
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
202
+ do_crypto_sm4e(vd + i, vn + i, vm + i);
220
+
203
+ }
221
+ armv7m = DEVICE(&s->armv7m);
204
+ clear_tail(vd, opr_sz, simd_maxsz(desc));
222
+ qdev_prop_set_uint32(armv7m, "num-irq", 81);
205
+}
223
+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
206
+
224
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
207
+static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm)
225
+ "memory", &error_abort);
208
{
226
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
209
- uint64_t *rd = vd;
227
+ if (err != NULL) {
210
- uint64_t *rn = vn;
228
+ error_propagate(errp, err);
211
- uint64_t *rm = vm;
212
union CRYPTO_STATE d;
213
union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
214
union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
215
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
216
rd[0] = d.l[0];
217
rd[1] = d.l[1];
218
}
219
+
220
+void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)
221
+{
222
+ intptr_t i, opr_sz = simd_oprsz(desc);
223
+
224
+ for (i = 0; i < opr_sz; i += 16) {
225
+ do_crypto_sm4ekey(vd + i, vn + i, vm + i);
226
+ }
227
+ clear_tail(vd, opr_sz, simd_maxsz(desc));
228
+}
229
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
230
index XXXXXXX..XXXXXXX 100644
231
--- a/target/arm/translate-a64.c
232
+++ b/target/arm/translate-a64.c
233
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
234
is_q ? 16 : 8, vec_full_reg_size(s));
235
}
236
237
+/* Expand a 2-operand operation using an out-of-line helper. */
238
+static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd,
239
+ int rn, int data, gen_helper_gvec_2 *fn)
240
+{
241
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
242
+ vec_full_reg_offset(s, rn),
243
+ is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
244
+}
245
+
246
/* Expand a 3-operand operation using an out-of-line helper. */
247
static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,
248
int rn, int rm, int data, gen_helper_gvec_3 *fn)
249
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
250
int rn = extract32(insn, 5, 5);
251
int rd = extract32(insn, 0, 5);
252
int decrypt;
253
- TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
254
- TCGv_i32 tcg_decrypt;
255
- CryptoThreeOpIntFn *genfn;
256
+ gen_helper_gvec_2 *genfn2 = NULL;
257
+ gen_helper_gvec_3 *genfn3 = NULL;
258
259
if (!dc_isar_feature(aa64_aes, s) || size != 0) {
260
unallocated_encoding(s);
261
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
262
switch (opcode) {
263
case 0x4: /* AESE */
264
decrypt = 0;
265
- genfn = gen_helper_crypto_aese;
266
+ genfn3 = gen_helper_crypto_aese;
267
break;
268
case 0x6: /* AESMC */
269
decrypt = 0;
270
- genfn = gen_helper_crypto_aesmc;
271
+ genfn2 = gen_helper_crypto_aesmc;
272
break;
273
case 0x5: /* AESD */
274
decrypt = 1;
275
- genfn = gen_helper_crypto_aese;
276
+ genfn3 = gen_helper_crypto_aese;
277
break;
278
case 0x7: /* AESIMC */
279
decrypt = 1;
280
- genfn = gen_helper_crypto_aesmc;
281
+ genfn2 = gen_helper_crypto_aesmc;
282
break;
283
default:
284
unallocated_encoding(s);
285
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
286
if (!fp_access_check(s)) {
287
return;
288
}
289
-
290
- tcg_rd_ptr = vec_full_reg_ptr(s, rd);
291
- tcg_rn_ptr = vec_full_reg_ptr(s, rn);
292
- tcg_decrypt = tcg_const_i32(decrypt);
293
-
294
- genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt);
295
-
296
- tcg_temp_free_ptr(tcg_rd_ptr);
297
- tcg_temp_free_ptr(tcg_rn_ptr);
298
- tcg_temp_free_i32(tcg_decrypt);
299
+ if (genfn2) {
300
+ gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2);
301
+ } else {
302
+ gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3);
303
+ }
304
}
305
306
/* Crypto three-reg SHA
307
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
308
int rn = extract32(insn, 5, 5);
309
int rd = extract32(insn, 0, 5);
310
bool feature;
311
- CryptoThreeOpFn *genfn;
312
+ CryptoThreeOpFn *genfn = NULL;
313
+ gen_helper_gvec_3 *oolfn = NULL;
314
315
if (o == 0) {
316
switch (opcode) {
317
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
318
break;
319
case 2: /* SM4EKEY */
320
feature = dc_isar_feature(aa64_sm4, s);
321
- genfn = gen_helper_crypto_sm4ekey;
322
+ oolfn = gen_helper_crypto_sm4ekey;
323
break;
324
default:
325
unallocated_encoding(s);
326
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
327
return;
328
}
329
330
+ if (oolfn) {
331
+ gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
229
+ return;
332
+ return;
230
+ }
333
+ }
231
+
334
+
232
+ if (!s->m3clk) {
335
if (genfn) {
233
+ error_setg(errp, "Invalid m3clk value");
336
TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
234
+ error_append_hint(errp, "m3clk can not be zero\n");
337
338
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
339
TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
340
bool feature;
341
CryptoTwoOpFn *genfn;
342
+ gen_helper_gvec_3 *oolfn = NULL;
343
344
switch (opcode) {
345
case 0: /* SHA512SU0 */
346
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
347
break;
348
case 1: /* SM4E */
349
feature = dc_isar_feature(aa64_sm4, s);
350
- genfn = gen_helper_crypto_sm4e;
351
+ oolfn = gen_helper_crypto_sm4e;
352
break;
353
default:
354
unallocated_encoding(s);
355
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
356
return;
357
}
358
359
+ if (oolfn) {
360
+ gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);
235
+ return;
361
+ return;
236
+ }
362
+ }
237
+ system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
363
+
238
+
364
tcg_rd_ptr = vec_full_reg_ptr(s, rd);
239
+ for (i = 0; i < MSF2_NUM_UARTS; i++) {
365
tcg_rn_ptr = vec_full_reg_ptr(s, rn);
240
+ if (serial_hds[i]) {
366
241
+ serial_mm_init(get_system_memory(), uart_addr[i], 2,
367
diff --git a/target/arm/translate.c b/target/arm/translate.c
242
+ qdev_get_gpio_in(armv7m, uart_irq[i]),
243
+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
244
+ }
245
+ }
246
+
247
+ dev = DEVICE(&s->timer);
248
+ /* APB0 clock is the timer input clock */
249
+ qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
250
+ object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
251
+ if (err != NULL) {
252
+ error_propagate(errp, err);
253
+ return;
254
+ }
255
+ busdev = SYS_BUS_DEVICE(dev);
256
+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
257
+ sysbus_connect_irq(busdev, 0,
258
+ qdev_get_gpio_in(armv7m, timer_irq[0]));
259
+ sysbus_connect_irq(busdev, 1,
260
+ qdev_get_gpio_in(armv7m, timer_irq[1]));
261
+
262
+ dev = DEVICE(&s->sysreg);
263
+ qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
264
+ qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
265
+ object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
266
+ if (err != NULL) {
267
+ error_propagate(errp, err);
268
+ return;
269
+ }
270
+ busdev = SYS_BUS_DEVICE(dev);
271
+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
272
+
273
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
274
+ gchar *bus_name;
275
+
276
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
277
+ if (err != NULL) {
278
+ error_propagate(errp, err);
279
+ return;
280
+ }
281
+
282
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
283
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
284
+ qdev_get_gpio_in(armv7m, spi_irq[i]));
285
+
286
+ /* Alias controller SPI bus to the SoC itself */
287
+ bus_name = g_strdup_printf("spi%d", i);
288
+ object_property_add_alias(OBJECT(s), bus_name,
289
+ OBJECT(&s->spi[i]), "spi",
290
+ &error_abort);
291
+ g_free(bus_name);
292
+ }
293
+
294
+ /* Below devices are not modelled yet. */
295
+ create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
296
+ create_unimplemented_device("dma", 0x40003000, 0x1000);
297
+ create_unimplemented_device("watchdog", 0x40005000, 0x1000);
298
+ create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
299
+ create_unimplemented_device("gpio", 0x40013000, 0x1000);
300
+ create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
301
+ create_unimplemented_device("can", 0x40015000, 0x1000);
302
+ create_unimplemented_device("rtc", 0x40017000, 0x1000);
303
+ create_unimplemented_device("apb_config", 0x40020000, 0x10000);
304
+ create_unimplemented_device("emac", 0x40041000, 0x1000);
305
+ create_unimplemented_device("usb", 0x40043000, 0x1000);
306
+}
307
+
308
+static Property m2sxxx_soc_properties[] = {
309
+ /*
310
+ * part name specifies the type of SmartFusion2 device variant(this
311
+ * property is for information purpose only.
312
+ */
313
+ DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
314
+ DEFINE_PROP_STRING("part-name", MSF2State, part_name),
315
+ DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
316
+ DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
317
+ MSF2_ESRAM_MAX_SIZE),
318
+ /* Libero GUI shows 100Mhz as default for clocks */
319
+ DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
320
+ /* default divisors in Libero GUI */
321
+ DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
322
+ DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
323
+ DEFINE_PROP_END_OF_LIST(),
324
+};
325
+
326
+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
327
+{
328
+ DeviceClass *dc = DEVICE_CLASS(klass);
329
+
330
+ dc->realize = m2sxxx_soc_realize;
331
+ dc->props = m2sxxx_soc_properties;
332
+}
333
+
334
+static const TypeInfo m2sxxx_soc_info = {
335
+ .name = TYPE_MSF2_SOC,
336
+ .parent = TYPE_SYS_BUS_DEVICE,
337
+ .instance_size = sizeof(MSF2State),
338
+ .instance_init = m2sxxx_soc_initfn,
339
+ .class_init = m2sxxx_soc_class_init,
340
+};
341
+
342
+static void m2sxxx_soc_types(void)
343
+{
344
+ type_register_static(&m2sxxx_soc_info);
345
+}
346
+
347
+type_init(m2sxxx_soc_types)
348
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
349
index XXXXXXX..XXXXXXX 100644
368
index XXXXXXX..XXXXXXX 100644
350
--- a/default-configs/arm-softmmu.mak
369
--- a/target/arm/translate.c
351
+++ b/default-configs/arm-softmmu.mak
370
+++ b/target/arm/translate.c
352
@@ -XXX,XX +XXX,XX @@ CONFIG_ACPI=y
371
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
353
CONFIG_SMBIOS=y
372
if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
354
CONFIG_ASPEED_SOC=y
373
return 1;
355
CONFIG_GPIO_KEY=y
374
}
356
+CONFIG_MSF2=y
375
- ptr1 = vfp_reg_ptr(true, rd);
376
- ptr2 = vfp_reg_ptr(true, rm);
377
-
378
- /* Bit 6 is the lowest opcode bit; it distinguishes between
379
- * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
380
- */
381
- tmp3 = tcg_const_i32(extract32(insn, 6, 1));
382
-
383
+ /*
384
+ * Bit 6 is the lowest opcode bit; it distinguishes
385
+ * between encryption (AESE/AESMC) and decryption
386
+ * (AESD/AESIMC).
387
+ */
388
if (op == NEON_2RM_AESE) {
389
- gen_helper_crypto_aese(ptr1, ptr2, tmp3);
390
+ tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd),
391
+ vfp_reg_offset(true, rd),
392
+ vfp_reg_offset(true, rm),
393
+ 16, 16, extract32(insn, 6, 1),
394
+ gen_helper_crypto_aese);
395
} else {
396
- gen_helper_crypto_aesmc(ptr1, ptr2, tmp3);
397
+ tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd),
398
+ vfp_reg_offset(true, rm),
399
+ 16, 16, extract32(insn, 6, 1),
400
+ gen_helper_crypto_aesmc);
401
}
402
- tcg_temp_free_ptr(ptr1);
403
- tcg_temp_free_ptr(ptr2);
404
- tcg_temp_free_i32(tmp3);
405
break;
406
case NEON_2RM_SHA1H:
407
if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
408
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
409
index XXXXXXX..XXXXXXX 100644
410
--- a/target/arm/vec_helper.c
411
+++ b/target/arm/vec_helper.c
412
@@ -XXX,XX +XXX,XX @@
413
#include "exec/helper-proto.h"
414
#include "tcg/tcg-gvec-desc.h"
415
#include "fpu/softfloat.h"
416
-
417
+#include "vec_internal.h"
418
419
/* Note that vector data is stored in host-endian 64-bit chunks,
420
so addressing units smaller than that needs a host-endian fixup. */
421
@@ -XXX,XX +XXX,XX @@
422
#define H4(x) (x)
423
#endif
424
425
-static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
426
-{
427
- uint64_t *d = vd + opr_sz;
428
- uintptr_t i;
429
-
430
- for (i = opr_sz; i < max_sz; i += 8) {
431
- *d++ = 0;
432
- }
433
-}
434
-
435
/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
436
static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
437
int16_t src3, uint32_t *sat)
357
--
438
--
358
2.7.4
439
2.20.1
359
440
360
441
diff view generated by jsdifflib
1
In the A64 decoder, we have a lot of references to section numbers
1
From: Richard Henderson <richard.henderson@linaro.org>
2
from version A.a of the v8A ARM ARM (DDI0487). This version of the
3
document is now long obsolete (we are currently on revision B.a),
4
and various intervening versions renumbered all the sections.
5
2
6
The most recent B.a version of the document doesn't assign
3
With this conversion, we will be able to use the same helpers
7
section numbers at all to the individual instruction classes
4
with sve. This also fixes a bug in which we failed to clear
8
in the way that the various A.x versions did. The simplest thing
5
the high bits of the SVE register after an AdvSIMD operation.
9
to do is just to delete all the out of date C.x.x references.
10
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200514212831.31248-3-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20170915150849.23557-1-peter.maydell@linaro.org
14
---
11
---
15
target/arm/translate-a64.c | 227 +++++++++++++++++++++++----------------------
12
target/arm/helper.h | 2 ++
16
1 file changed, 114 insertions(+), 113 deletions(-)
13
target/arm/translate-a64.h | 3 ++
14
target/arm/crypto_helper.c | 11 +++++++
15
target/arm/translate-a64.c | 59 ++++++++++++++++++++------------------
16
4 files changed, 47 insertions(+), 28 deletions(-)
17
17
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
21
+++ b/target/arm/helper.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
23
DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
24
DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
25
26
+DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
27
+
28
DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
29
DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
30
31
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/translate-a64.h
34
+++ b/target/arm/translate-a64.h
35
@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
36
37
bool disas_sve(DisasContext *, uint32_t);
38
39
+void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
40
+ uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
41
+
42
#endif /* TARGET_ARM_TRANSLATE_A64_H */
43
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/crypto_helper.c
46
+++ b/target/arm/crypto_helper.c
47
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc)
48
}
49
clear_tail(vd, opr_sz, simd_maxsz(desc));
50
}
51
+
52
+void HELPER(crypto_rax1)(void *vd, void *vn, void *vm, uint32_t desc)
53
+{
54
+ intptr_t i, opr_sz = simd_oprsz(desc);
55
+ uint64_t *d = vd, *n = vn, *m = vm;
56
+
57
+ for (i = 0; i < opr_sz / 8; ++i) {
58
+ d[i] = n[i] ^ rol64(m[i], 1);
59
+ }
60
+ clear_tail(vd, opr_sz, simd_maxsz(desc));
61
+}
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
62
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
64
--- a/target/arm/translate-a64.c
21
+++ b/target/arm/translate-a64.c
65
+++ b/target/arm/translate-a64.c
22
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
66
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
67
tcg_temp_free_ptr(tcg_rn_ptr);
23
}
68
}
24
69
25
/*
70
+static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
26
- * the instruction disassembly implemented here matches
71
+{
27
- * the instruction encoding classifications in chapter 3 (C3)
72
+ tcg_gen_rotli_i64(d, m, 1);
28
- * of the ARM Architecture Reference Manual (DDI0487A_a)
73
+ tcg_gen_xor_i64(d, d, n);
29
+ * The instruction disassembly implemented here matches
74
+}
30
+ * the instruction encoding classifications in chapter C4
75
+
31
+ * of the ARM Architecture Reference Manual (DDI0487B_a);
76
+static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m)
32
+ * classification names and decode diagrams here should generally
77
+{
33
+ * match up with those in the manual.
78
+ tcg_gen_rotli_vec(vece, d, m, 1);
34
*/
79
+ tcg_gen_xor_vec(vece, d, d, n);
35
80
+}
36
-/* C3.2.7 Unconditional branch (immediate)
81
+
37
+/* Unconditional branch (immediate)
82
+void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
38
* 31 30 26 25 0
83
+ uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
39
* +----+-----------+-------------------------------------+
84
+{
40
* | op | 0 0 1 0 1 | imm26 |
85
+ static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 };
41
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
86
+ static const GVecGen3 op = {
42
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
87
+ .fni8 = gen_rax1_i64,
43
88
+ .fniv = gen_rax1_vec,
44
if (insn & (1U << 31)) {
89
+ .opt_opc = vecop_list,
45
- /* C5.6.26 BL Branch with link */
90
+ .fno = gen_helper_crypto_rax1,
46
+ /* BL Branch with link */
91
+ .vece = MO_64,
47
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
92
+ };
48
}
93
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op);
49
94
+}
50
- /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
95
+
51
+ /* B Branch / BL Branch with link */
96
/* Crypto three-reg SHA512
52
gen_goto_tb(s, 0, addr);
97
* 31 21 20 16 15 14 13 12 11 10 9 5 4 0
53
}
98
* +-----------------------+------+---+---+-----+--------+------+------+
54
99
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
55
-/* C3.2.1 Compare & branch (immediate)
100
bool feature;
56
+/* Compare and branch (immediate)
101
CryptoThreeOpFn *genfn = NULL;
57
* 31 30 25 24 23 5 4 0
102
gen_helper_gvec_3 *oolfn = NULL;
58
* +----+-------------+----+---------------------+--------+
103
+ GVecGen3Fn *gvecfn = NULL;
59
* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
104
60
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
105
if (o == 0) {
61
gen_goto_tb(s, 1, addr);
106
switch (opcode) {
62
}
107
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
63
108
break;
64
-/* C3.2.5 Test & branch (immediate)
109
case 3: /* RAX1 */
65
+/* Test and branch (immediate)
110
feature = dc_isar_feature(aa64_sha3, s);
66
* 31 30 25 24 23 19 18 5 4 0
111
- genfn = NULL;
67
* +----+-------------+----+-------+-------------+------+
112
+ gvecfn = gen_gvec_rax1;
68
* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
113
break;
69
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
114
default:
70
gen_goto_tb(s, 1, addr);
115
g_assert_not_reached();
71
}
116
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
72
117
73
-/* C3.2.2 / C5.6.19 Conditional branch (immediate)
118
if (oolfn) {
74
+/* Conditional branch (immediate)
119
gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
75
* 31 25 24 23 5 4 3 0
120
- return;
76
* +---------------+----+---------------------+----+------+
121
- }
77
* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
122
-
78
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
123
- if (genfn) {
124
+ } else if (gvecfn) {
125
+ gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
126
+ } else {
127
TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
128
129
tcg_rd_ptr = vec_full_reg_ptr(s, rd);
130
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
131
tcg_temp_free_ptr(tcg_rd_ptr);
132
tcg_temp_free_ptr(tcg_rn_ptr);
133
tcg_temp_free_ptr(tcg_rm_ptr);
134
- } else {
135
- TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
136
- int pass;
137
-
138
- tcg_op1 = tcg_temp_new_i64();
139
- tcg_op2 = tcg_temp_new_i64();
140
- tcg_res[0] = tcg_temp_new_i64();
141
- tcg_res[1] = tcg_temp_new_i64();
142
-
143
- for (pass = 0; pass < 2; pass++) {
144
- read_vec_element(s, tcg_op1, rn, pass, MO_64);
145
- read_vec_element(s, tcg_op2, rm, pass, MO_64);
146
-
147
- tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1);
148
- tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
149
- }
150
- write_vec_element(s, tcg_res[0], rd, 0, MO_64);
151
- write_vec_element(s, tcg_res[1], rd, 1, MO_64);
152
-
153
- tcg_temp_free_i64(tcg_op1);
154
- tcg_temp_free_i64(tcg_op2);
155
- tcg_temp_free_i64(tcg_res[0]);
156
- tcg_temp_free_i64(tcg_res[1]);
79
}
157
}
80
}
158
}
81
159
82
-/* C5.6.68 HINT */
83
+/* HINT instruction group, including various allocated HINTs */
84
static void handle_hint(DisasContext *s, uint32_t insn,
85
unsigned int op1, unsigned int op2, unsigned int crm)
86
{
87
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
88
}
89
}
90
91
-/* C5.6.130 MSR (immediate) - move immediate to processor state field */
92
+/* MSR (immediate) - move immediate to processor state field */
93
static void handle_msr_i(DisasContext *s, uint32_t insn,
94
unsigned int op1, unsigned int op2, unsigned int crm)
95
{
96
@@ -XXX,XX +XXX,XX @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
97
tcg_temp_free_i32(nzcv);
98
}
99
100
-/* C5.6.129 MRS - move from system register
101
- * C5.6.131 MSR (register) - move to system register
102
- * C5.6.204 SYS
103
- * C5.6.205 SYSL
104
+/* MRS - move from system register
105
+ * MSR (register) - move to system register
106
+ * SYS
107
+ * SYSL
108
* These are all essentially the same insn in 'read' and 'write'
109
* versions, with varying op0 fields.
110
*/
111
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
112
}
113
}
114
115
-/* C3.2.4 System
116
+/* System
117
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
118
* +---------------------+---+-----+-----+-------+-------+-----+------+
119
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
120
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
121
return;
122
}
123
switch (crn) {
124
- case 2: /* C5.6.68 HINT */
125
+ case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
126
handle_hint(s, insn, op1, op2, crm);
127
break;
128
case 3: /* CLREX, DSB, DMB, ISB */
129
handle_sync(s, insn, op1, op2, crm);
130
break;
131
- case 4: /* C5.6.130 MSR (immediate) */
132
+ case 4: /* MSR (immediate) */
133
handle_msr_i(s, insn, op1, op2, crm);
134
break;
135
default:
136
@@ -XXX,XX +XXX,XX @@ static void disas_system(DisasContext *s, uint32_t insn)
137
handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
138
}
139
140
-/* C3.2.3 Exception generation
141
+/* Exception generation
142
*
143
* 31 24 23 21 20 5 4 2 1 0
144
* +-----------------+-----+------------------------+-----+----+
145
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
146
}
147
}
148
149
-/* C3.2.7 Unconditional branch (register)
150
+/* Unconditional branch (register)
151
* 31 25 24 21 20 16 15 10 9 5 4 0
152
* +---------------+-------+-------+-------+------+-------+
153
* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
154
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
155
s->base.is_jmp = DISAS_JUMP;
156
}
157
158
-/* C3.2 Branches, exception generating and system instructions */
159
+/* Branches, exception generating and system instructions */
160
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
161
{
162
switch (extract32(insn, 25, 7)) {
163
@@ -XXX,XX +XXX,XX @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
164
return regsize == 64;
165
}
166
167
-/* C3.3.6 Load/store exclusive
168
+/* Load/store exclusive
169
*
170
* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
171
* +-----+-------------+----+---+----+------+----+-------+------+------+
172
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
173
}
174
175
/*
176
- * C3.3.5 Load register (literal)
177
+ * Load register (literal)
178
*
179
* 31 30 29 27 26 25 24 23 5 4 0
180
* +-----+-------+---+-----+-------------------+-------+
181
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
182
}
183
184
/*
185
- * C5.6.80 LDNP (Load Pair - non-temporal hint)
186
- * C5.6.81 LDP (Load Pair - non vector)
187
- * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
188
- * C5.6.176 STNP (Store Pair - non-temporal hint)
189
- * C5.6.177 STP (Store Pair - non vector)
190
- * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
191
- * C6.3.165 LDP (Load Pair of SIMD&FP)
192
- * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
193
- * C6.3.284 STP (Store Pair of SIMD&FP)
194
+ * LDNP (Load Pair - non-temporal hint)
195
+ * LDP (Load Pair - non vector)
196
+ * LDPSW (Load Pair Signed Word - non vector)
197
+ * STNP (Store Pair - non-temporal hint)
198
+ * STP (Store Pair - non vector)
199
+ * LDNP (Load Pair of SIMD&FP - non-temporal hint)
200
+ * LDP (Load Pair of SIMD&FP)
201
+ * STNP (Store Pair of SIMD&FP - non-temporal hint)
202
+ * STP (Store Pair of SIMD&FP)
203
*
204
* 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
205
* +-----+-------+---+---+-------+---+-----------------------------+
206
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
207
}
208
209
/*
210
- * C3.3.8 Load/store (immediate post-indexed)
211
- * C3.3.9 Load/store (immediate pre-indexed)
212
- * C3.3.12 Load/store (unscaled immediate)
213
+ * Load/store (immediate post-indexed)
214
+ * Load/store (immediate pre-indexed)
215
+ * Load/store (unscaled immediate)
216
*
217
* 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
218
* +----+-------+---+-----+-----+---+--------+-----+------+------+
219
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
220
}
221
222
/*
223
- * C3.3.10 Load/store (register offset)
224
+ * Load/store (register offset)
225
*
226
* 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
227
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
228
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
229
}
230
231
/*
232
- * C3.3.13 Load/store (unsigned immediate)
233
+ * Load/store (unsigned immediate)
234
*
235
* 31 30 29 27 26 25 24 23 22 21 10 9 5
236
* +----+-------+---+-----+-----+------------+-------+------+
237
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
238
}
239
}
240
241
-/* C3.3.1 AdvSIMD load/store multiple structures
242
+/* AdvSIMD load/store multiple structures
243
*
244
* 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
245
* +---+---+---------------+---+-------------+--------+------+------+------+
246
* | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
247
* +---+---+---------------+---+-------------+--------+------+------+------+
248
*
249
- * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
250
+ * AdvSIMD load/store multiple structures (post-indexed)
251
*
252
* 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
253
* +---+---+---------------+---+---+---------+--------+------+------+------+
254
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
255
tcg_temp_free_i64(tcg_addr);
256
}
257
258
-/* C3.3.3 AdvSIMD load/store single structure
259
+/* AdvSIMD load/store single structure
260
*
261
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
262
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
263
* | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
264
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
265
*
266
- * C3.3.4 AdvSIMD load/store single structure (post-indexed)
267
+ * AdvSIMD load/store single structure (post-indexed)
268
*
269
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
270
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
271
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
272
tcg_temp_free_i64(tcg_addr);
273
}
274
275
-/* C3.3 Loads and stores */
276
+/* Loads and stores */
277
static void disas_ldst(DisasContext *s, uint32_t insn)
278
{
279
switch (extract32(insn, 24, 6)) {
280
@@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn)
281
}
282
}
283
284
-/* C3.4.6 PC-rel. addressing
285
+/* PC-rel. addressing
286
* 31 30 29 28 24 23 5 4 0
287
* +----+-------+-----------+-------------------+------+
288
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
289
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
290
}
291
292
/*
293
- * C3.4.1 Add/subtract (immediate)
294
+ * Add/subtract (immediate)
295
*
296
* 31 30 29 28 24 23 22 21 10 9 5 4 0
297
* +--+--+--+-----------+-----+-------------+-----+-----+
298
@@ -XXX,XX +XXX,XX @@ static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
299
return true;
300
}
301
302
-/* C3.4.4 Logical (immediate)
303
+/* Logical (immediate)
304
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
305
* +----+-----+-------------+---+------+------+------+------+
306
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
307
@@ -XXX,XX +XXX,XX @@ static void disas_logic_imm(DisasContext *s, uint32_t insn)
308
}
309
310
/*
311
- * C3.4.5 Move wide (immediate)
312
+ * Move wide (immediate)
313
*
314
* 31 30 29 28 23 22 21 20 5 4 0
315
* +--+-----+-------------+-----+----------------+------+
316
@@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
317
}
318
}
319
320
-/* C3.4.2 Bitfield
321
+/* Bitfield
322
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
323
* +----+-----+-------------+---+------+------+------+------+
324
* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
325
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
326
}
327
}
328
329
-/* C3.4.3 Extract
330
+/* Extract
331
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
332
* +----+------+-------------+---+----+------+--------+------+------+
333
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
334
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
335
}
336
}
337
338
-/* C3.4 Data processing - immediate */
339
+/* Data processing - immediate */
340
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
341
{
342
switch (extract32(insn, 23, 6)) {
343
@@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
344
}
345
}
346
347
-/* C3.5.10 Logical (shifted register)
348
+/* Logical (shifted register)
349
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
350
* +----+-----+-----------+-------+---+------+--------+------+------+
351
* | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
352
@@ -XXX,XX +XXX,XX @@ static void disas_logic_reg(DisasContext *s, uint32_t insn)
353
}
354
355
/*
356
- * C3.5.1 Add/subtract (extended register)
357
+ * Add/subtract (extended register)
358
*
359
* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
360
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
361
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
362
}
363
364
/*
365
- * C3.5.2 Add/subtract (shifted register)
366
+ * Add/subtract (shifted register)
367
*
368
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
369
* +--+--+--+-----------+-----+--+-------+---------+------+------+
370
@@ -XXX,XX +XXX,XX @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
371
tcg_temp_free_i64(tcg_result);
372
}
373
374
-/* C3.5.9 Data-processing (3 source)
375
-
376
- 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
377
- +--+------+-----------+------+------+----+------+------+------+
378
- |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
379
- +--+------+-----------+------+------+----+------+------+------+
380
-
381
+/* Data-processing (3 source)
382
+ *
383
+ * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
384
+ * +--+------+-----------+------+------+----+------+------+------+
385
+ * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
386
+ * +--+------+-----------+------+------+----+------+------+------+
387
*/
388
static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
389
{
390
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
391
tcg_temp_free_i64(tcg_tmp);
392
}
393
394
-/* C3.5.3 - Add/subtract (with carry)
395
+/* Add/subtract (with carry)
396
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
397
* +--+--+--+------------------------+------+---------+------+-----+
398
* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
399
@@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
400
}
401
}
402
403
-/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
404
+/* Conditional compare (immediate / register)
405
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
406
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
407
* |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
408
@@ -XXX,XX +XXX,XX @@ static void disas_cc(DisasContext *s, uint32_t insn)
409
tcg_temp_free_i32(tcg_t2);
410
}
411
412
-/* C3.5.6 Conditional select
413
+/* Conditional select
414
* 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
415
* +----+----+---+-----------------+------+------+-----+------+------+
416
* | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
417
@@ -XXX,XX +XXX,XX @@ static void handle_rbit(DisasContext *s, unsigned int sf,
418
}
419
}
420
421
-/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
422
+/* REV with sf==1, opcode==3 ("REV64") */
423
static void handle_rev64(DisasContext *s, unsigned int sf,
424
unsigned int rn, unsigned int rd)
425
{
426
@@ -XXX,XX +XXX,XX @@ static void handle_rev64(DisasContext *s, unsigned int sf,
427
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
428
}
429
430
-/* C5.6.149 REV with sf==0, opcode==2
431
- * C5.6.151 REV32 (sf==1, opcode==2)
432
+/* REV with sf==0, opcode==2
433
+ * REV32 (sf==1, opcode==2)
434
*/
435
static void handle_rev32(DisasContext *s, unsigned int sf,
436
unsigned int rn, unsigned int rd)
437
@@ -XXX,XX +XXX,XX @@ static void handle_rev32(DisasContext *s, unsigned int sf,
438
}
439
}
440
441
-/* C5.6.150 REV16 (opcode==1) */
442
+/* REV16 (opcode==1) */
443
static void handle_rev16(DisasContext *s, unsigned int sf,
444
unsigned int rn, unsigned int rd)
445
{
446
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
447
tcg_temp_free_i64(tcg_tmp);
448
}
449
450
-/* C3.5.7 Data-processing (1 source)
451
+/* Data-processing (1 source)
452
* 31 30 29 28 21 20 16 15 10 9 5 4 0
453
* +----+---+---+-----------------+---------+--------+------+------+
454
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
455
@@ -XXX,XX +XXX,XX @@ static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
456
}
457
}
458
459
-/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
460
+/* LSLV, LSRV, ASRV, RORV */
461
static void handle_shift_reg(DisasContext *s,
462
enum a64_shift_type shift_type, unsigned int sf,
463
unsigned int rm, unsigned int rn, unsigned int rd)
464
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
465
tcg_temp_free_i32(tcg_bytes);
466
}
467
468
-/* C3.5.8 Data-processing (2 source)
469
+/* Data-processing (2 source)
470
* 31 30 29 28 21 20 16 15 10 9 5 4 0
471
* +----+---+---+-----------------+------+--------+------+------+
472
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
473
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
474
}
475
}
476
477
-/* C3.5 Data processing - register */
478
+/* Data processing - register */
479
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
480
{
481
switch (extract32(insn, 24, 5)) {
482
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
483
tcg_temp_free_i64(tcg_flags);
484
}
485
486
-/* C3.6.22 Floating point compare
487
+/* Floating point compare
488
* 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
489
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
490
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
491
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
492
handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
493
}
494
495
-/* C3.6.23 Floating point conditional compare
496
+/* Floating point conditional compare
497
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
498
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
499
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
500
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
501
}
502
}
503
504
-/* C3.6.24 Floating point conditional select
505
+/* Floating point conditional select
506
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
507
* +---+---+---+-----------+------+---+------+------+-----+------+------+
508
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
509
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
510
tcg_temp_free_i64(t_true);
511
}
512
513
-/* C3.6.25 Floating-point data-processing (1 source) - single precision */
514
+/* Floating-point data-processing (1 source) - single precision */
515
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
516
{
517
TCGv_ptr fpst;
518
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
519
tcg_temp_free_i32(tcg_res);
520
}
521
522
-/* C3.6.25 Floating-point data-processing (1 source) - double precision */
523
+/* Floating-point data-processing (1 source) - double precision */
524
static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
525
{
526
TCGv_ptr fpst;
527
@@ -XXX,XX +XXX,XX @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
528
}
529
}
530
531
-/* C3.6.25 Floating point data-processing (1 source)
532
+/* Floating point data-processing (1 source)
533
* 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
534
* +---+---+---+-----------+------+---+--------+-----------+------+------+
535
* | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
536
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
537
}
538
}
539
540
-/* C3.6.26 Floating-point data-processing (2 source) - single precision */
541
+/* Floating-point data-processing (2 source) - single precision */
542
static void handle_fp_2src_single(DisasContext *s, int opcode,
543
int rd, int rn, int rm)
544
{
545
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
546
tcg_temp_free_i32(tcg_res);
547
}
548
549
-/* C3.6.26 Floating-point data-processing (2 source) - double precision */
550
+/* Floating-point data-processing (2 source) - double precision */
551
static void handle_fp_2src_double(DisasContext *s, int opcode,
552
int rd, int rn, int rm)
553
{
554
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
555
tcg_temp_free_i64(tcg_res);
556
}
557
558
-/* C3.6.26 Floating point data-processing (2 source)
559
+/* Floating point data-processing (2 source)
560
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
561
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
562
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
563
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
564
}
565
}
566
567
-/* C3.6.27 Floating-point data-processing (3 source) - single precision */
568
+/* Floating-point data-processing (3 source) - single precision */
569
static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
570
int rd, int rn, int rm, int ra)
571
{
572
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
573
tcg_temp_free_i32(tcg_res);
574
}
575
576
-/* C3.6.27 Floating-point data-processing (3 source) - double precision */
577
+/* Floating-point data-processing (3 source) - double precision */
578
static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
579
int rd, int rn, int rm, int ra)
580
{
581
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
582
tcg_temp_free_i64(tcg_res);
583
}
584
585
-/* C3.6.27 Floating point data-processing (3 source)
586
+/* Floating point data-processing (3 source)
587
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
588
* +---+---+---+-----------+------+----+------+----+------+------+------+
589
* | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
590
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
591
}
592
}
593
594
-/* C3.6.28 Floating point immediate
595
+/* Floating point immediate
596
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
597
* +---+---+---+-----------+------+---+------------+-------+------+------+
598
* | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
599
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
600
tcg_temp_free_i32(tcg_shift);
601
}
602
603
-/* C3.6.29 Floating point <-> fixed point conversions
604
+/* Floating point <-> fixed point conversions
605
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
606
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
607
* | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
608
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
609
}
610
}
611
612
-/* C3.6.30 Floating point <-> integer conversions
613
+/* Floating point <-> integer conversions
614
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
615
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
616
* | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
617
@@ -XXX,XX +XXX,XX @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
618
tcg_temp_free_i64(tcg_tmp);
619
}
620
621
-/* C3.6.1 EXT
622
+/* EXT
623
* 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
624
* +---+---+-------------+-----+---+------+---+------+---+------+------+
625
* | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
626
@@ -XXX,XX +XXX,XX @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
627
tcg_temp_free_i64(tcg_resh);
628
}
629
630
-/* C3.6.2 TBL/TBX
631
+/* TBL/TBX
632
* 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
633
* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
634
* | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
635
@@ -XXX,XX +XXX,XX @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
636
tcg_temp_free_i64(tcg_resh);
637
}
638
639
-/* C3.6.3 ZIP/UZP/TRN
640
+/* ZIP/UZP/TRN
641
* 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
642
* +---+---+-------------+------+---+------+---+------------------+------+
643
* | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
644
@@ -XXX,XX +XXX,XX @@ static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
645
}
646
}
647
648
-/* C3.6.4 AdvSIMD across lanes
649
+/* AdvSIMD across lanes
650
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
651
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
652
* | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
653
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
654
tcg_temp_free_i64(tcg_res);
655
}
656
657
-/* C6.3.31 DUP (Element, Vector)
658
+/* DUP (Element, Vector)
659
*
660
* 31 30 29 21 20 16 15 10 9 5 4 0
661
* +---+---+-------------------+--------+-------------+------+------+
662
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
663
tcg_temp_free_i64(tmp);
664
}
665
666
-/* C6.3.31 DUP (element, scalar)
667
+/* DUP (element, scalar)
668
* 31 21 20 16 15 10 9 5 4 0
669
* +-----------------------+--------+-------------+------+------+
670
* | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
671
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupes(DisasContext *s, int rd, int rn,
672
tcg_temp_free_i64(tmp);
673
}
674
675
-/* C6.3.32 DUP (General)
676
+/* DUP (General)
677
*
678
* 31 30 29 21 20 16 15 10 9 5 4 0
679
* +---+---+-------------------+--------+-------------+------+------+
680
@@ -XXX,XX +XXX,XX @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
681
}
682
}
683
684
-/* C6.3.150 INS (Element)
685
+/* INS (Element)
686
*
687
* 31 21 20 16 15 14 11 10 9 5 4 0
688
* +-----------------------+--------+------------+---+------+------+
689
@@ -XXX,XX +XXX,XX @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
690
}
691
692
693
-/* C6.3.151 INS (General)
694
+/* INS (General)
695
*
696
* 31 21 20 16 15 10 9 5 4 0
697
* +-----------------------+--------+-------------+------+------+
698
@@ -XXX,XX +XXX,XX @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
699
}
700
701
/*
702
- * C6.3.321 UMOV (General)
703
- * C6.3.237 SMOV (General)
704
+ * UMOV (General)
705
+ * SMOV (General)
706
*
707
* 31 30 29 21 20 16 15 12 10 9 5 4 0
708
* +---+---+-------------------+--------+-------------+------+------+
709
@@ -XXX,XX +XXX,XX @@ static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
710
}
711
}
712
713
-/* C3.6.5 AdvSIMD copy
714
+/* AdvSIMD copy
715
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
716
* +---+---+----+-----------------+------+---+------+---+------+------+
717
* | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
718
@@ -XXX,XX +XXX,XX @@ static void disas_simd_copy(DisasContext *s, uint32_t insn)
719
}
720
}
721
722
-/* C3.6.6 AdvSIMD modified immediate
723
+/* AdvSIMD modified immediate
724
* 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
725
* +---+---+----+---------------------+-----+-------+----+---+-------+------+
726
* | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
727
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
728
tcg_temp_free_i64(tcg_imm);
729
}
730
731
-/* C3.6.7 AdvSIMD scalar copy
732
+/* AdvSIMD scalar copy
733
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
734
* +-----+----+-----------------+------+---+------+---+------+------+
735
* | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
736
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
737
handle_simd_dupes(s, rd, rn, imm5);
738
}
739
740
-/* C3.6.8 AdvSIMD scalar pairwise
741
+/* AdvSIMD scalar pairwise
742
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
743
* +-----+---+-----------+------+-----------+--------+-----+------+------+
744
* | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
745
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
746
tcg_temp_free_i32(tcg_rmode);
747
}
748
749
-/* C3.6.9 AdvSIMD scalar shift by immediate
750
+/* AdvSIMD scalar shift by immediate
751
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
752
* +-----+---+-------------+------+------+--------+---+------+------+
753
* | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
754
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
755
}
756
}
757
758
-/* C3.6.10 AdvSIMD scalar three different
759
+/* AdvSIMD scalar three different
760
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
761
* +-----+---+-----------+------+---+------+--------+-----+------+------+
762
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
763
@@ -XXX,XX +XXX,XX @@ static void handle_3same_float(DisasContext *s, int size, int elements,
764
}
765
}
766
767
-/* C3.6.11 AdvSIMD scalar three same
768
+/* AdvSIMD scalar three same
769
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
770
* +-----+---+-----------+------+---+------+--------+---+------+------+
771
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
772
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
773
}
774
}
775
776
-/* C3.6.12 AdvSIMD scalar two reg misc
777
+/* AdvSIMD scalar two reg misc
778
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
779
* +-----+---+-----------+------+-----------+--------+-----+------+------+
780
* | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
781
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
782
}
783
784
785
-/* C3.6.14 AdvSIMD shift by immediate
786
+/* AdvSIMD shift by immediate
787
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
788
* +---+---+---+-------------+------+------+--------+---+------+------+
789
* | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
790
@@ -XXX,XX +XXX,XX @@ static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
791
tcg_temp_free_i64(tcg_res);
792
}
793
794
-/* C3.6.15 AdvSIMD three different
795
+/* AdvSIMD three different
796
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
797
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
798
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
799
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
800
}
801
}
802
803
-/* C3.6.16 AdvSIMD three same
804
+/* AdvSIMD three same
805
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
806
* +---+---+---+-----------+------+---+------+--------+---+------+------+
807
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
808
@@ -XXX,XX +XXX,XX @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
809
}
810
}
811
812
-/* C3.6.17 AdvSIMD two reg misc
813
+/* AdvSIMD two reg misc
814
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
815
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
816
* | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
817
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
818
}
819
}
820
821
-/* C3.6.13 AdvSIMD scalar x indexed element
822
+/* AdvSIMD scalar x indexed element
823
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
824
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
825
* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
826
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
827
- * C3.6.18 AdvSIMD vector x indexed element
828
+ * AdvSIMD vector x indexed element
829
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
830
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
831
* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
832
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
833
}
834
}
835
836
-/* C3.6.19 Crypto AES
837
+/* Crypto AES
838
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
839
* +-----------------+------+-----------+--------+-----+------+------+
840
* | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
841
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
842
tcg_temp_free_i32(tcg_decrypt);
843
}
844
845
-/* C3.6.20 Crypto three-reg SHA
846
+/* Crypto three-reg SHA
847
* 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
848
* +-----------------+------+---+------+---+--------+-----+------+------+
849
* | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
850
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
851
tcg_temp_free_i32(tcg_rm_regno);
852
}
853
854
-/* C3.6.21 Crypto two-reg SHA
855
+/* Crypto two-reg SHA
856
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
857
* +-----------------+------+-----------+--------+-----+------+------+
858
* | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
859
--
160
--
860
2.7.4
161
2.20.1
861
162
862
163
diff view generated by jsdifflib
1
Don't use old_mmio in the memory region ops struct.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Do not yet convert the helpers to loop over opr_sz, but the
4
descriptor allows the vector tail to be cleared. Which fixes
5
an existing bug vs SVE.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200514212831.31248-4-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-7-git-send-email-peter.maydell@linaro.org
6
---
11
---
7
hw/arm/omap2.c | 49 +++++++++++++++++++++++++++++++++++++------------
12
target/arm/helper.h | 15 +++++++-----
8
1 file changed, 37 insertions(+), 12 deletions(-)
13
target/arm/crypto_helper.c | 37 +++++++++++++++++++++++-----
9
14
target/arm/translate-a64.c | 50 ++++++++++++--------------------------
10
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
15
3 files changed, 55 insertions(+), 47 deletions(-)
16
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
11
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/arm/omap2.c
19
--- a/target/arm/helper.h
13
+++ b/hw/arm/omap2.c
20
+++ b/target/arm/helper.h
14
@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write(void *opaque, hwaddr addr,
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
22
DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)
23
DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
24
25
-DEF_HELPER_FLAGS_3(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
26
-DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
27
-DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr)
28
-DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
29
+DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG,
33
+ void, ptr, ptr, ptr, i32)
34
35
DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
36
-DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
37
-DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
38
+DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG,
39
+ void, ptr, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG,
41
+ void, ptr, ptr, ptr, i32)
42
43
DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
44
DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
45
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/crypto_helper.c
48
+++ b/target/arm/crypto_helper.c
49
@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
50
#define CR_ST_WORD(state, i) (state.words[i])
51
#endif
52
53
+/*
54
+ * The caller has not been converted to full gvec, and so only
55
+ * modifies the low 16 bytes of the vector register.
56
+ */
57
+static void clear_tail_16(void *vd, uint32_t desc)
58
+{
59
+ int opr_sz = simd_oprsz(desc);
60
+ int max_sz = simd_maxsz(desc);
61
+
62
+ assert(opr_sz == 16);
63
+ clear_tail(vd, opr_sz, max_sz);
64
+}
65
+
66
static void do_crypto_aese(uint64_t *rd, uint64_t *rn,
67
uint64_t *rm, bool decrypt)
68
{
69
@@ -XXX,XX +XXX,XX @@ static uint64_t s1_512(uint64_t x)
70
return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6);
71
}
72
73
-void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm)
74
+void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm, uint32_t desc)
75
{
76
uint64_t *rd = vd;
77
uint64_t *rn = vn;
78
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm)
79
80
rd[0] = d0;
81
rd[1] = d1;
82
+
83
+ clear_tail_16(vd, desc);
84
}
85
86
-void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm)
87
+void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm, uint32_t desc)
88
{
89
uint64_t *rd = vd;
90
uint64_t *rn = vn;
91
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm)
92
93
rd[0] = d0;
94
rd[1] = d1;
95
+
96
+ clear_tail_16(vd, desc);
97
}
98
99
-void HELPER(crypto_sha512su0)(void *vd, void *vn)
100
+void HELPER(crypto_sha512su0)(void *vd, void *vn, uint32_t desc)
101
{
102
uint64_t *rd = vd;
103
uint64_t *rn = vn;
104
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su0)(void *vd, void *vn)
105
106
rd[0] = d0;
107
rd[1] = d1;
108
+
109
+ clear_tail_16(vd, desc);
110
}
111
112
-void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm)
113
+void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm, uint32_t desc)
114
{
115
uint64_t *rd = vd;
116
uint64_t *rn = vn;
117
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm)
118
119
rd[0] += s1_512(rn[0]) + rm[0];
120
rd[1] += s1_512(rn[1]) + rm[1];
121
+
122
+ clear_tail_16(vd, desc);
123
}
124
125
-void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm)
126
+void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm, uint32_t desc)
127
{
128
uint64_t *rd = vd;
129
uint64_t *rn = vn;
130
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm)
131
132
rd[0] = d.l[0];
133
rd[1] = d.l[1];
134
+
135
+ clear_tail_16(vd, desc);
136
}
137
138
-void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm)
139
+void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm, uint32_t desc)
140
{
141
uint64_t *rd = vd;
142
uint64_t *rn = vn;
143
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm)
144
145
rd[0] = d.l[0];
146
rd[1] = d.l[1];
147
+
148
+ clear_tail_16(vd, desc);
149
}
150
151
void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
152
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/target/arm/translate-a64.c
155
+++ b/target/arm/translate-a64.c
156
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
157
int rn = extract32(insn, 5, 5);
158
int rd = extract32(insn, 0, 5);
159
bool feature;
160
- CryptoThreeOpFn *genfn = NULL;
161
gen_helper_gvec_3 *oolfn = NULL;
162
GVecGen3Fn *gvecfn = NULL;
163
164
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
165
switch (opcode) {
166
case 0: /* SHA512H */
167
feature = dc_isar_feature(aa64_sha512, s);
168
- genfn = gen_helper_crypto_sha512h;
169
+ oolfn = gen_helper_crypto_sha512h;
170
break;
171
case 1: /* SHA512H2 */
172
feature = dc_isar_feature(aa64_sha512, s);
173
- genfn = gen_helper_crypto_sha512h2;
174
+ oolfn = gen_helper_crypto_sha512h2;
175
break;
176
case 2: /* SHA512SU1 */
177
feature = dc_isar_feature(aa64_sha512, s);
178
- genfn = gen_helper_crypto_sha512su1;
179
+ oolfn = gen_helper_crypto_sha512su1;
180
break;
181
case 3: /* RAX1 */
182
feature = dc_isar_feature(aa64_sha3, s);
183
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
184
switch (opcode) {
185
case 0: /* SM3PARTW1 */
186
feature = dc_isar_feature(aa64_sm3, s);
187
- genfn = gen_helper_crypto_sm3partw1;
188
+ oolfn = gen_helper_crypto_sm3partw1;
189
break;
190
case 1: /* SM3PARTW2 */
191
feature = dc_isar_feature(aa64_sm3, s);
192
- genfn = gen_helper_crypto_sm3partw2;
193
+ oolfn = gen_helper_crypto_sm3partw2;
194
break;
195
case 2: /* SM4EKEY */
196
feature = dc_isar_feature(aa64_sm4, s);
197
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
198
199
if (oolfn) {
200
gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn);
201
- } else if (gvecfn) {
202
- gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
203
} else {
204
- TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
205
-
206
- tcg_rd_ptr = vec_full_reg_ptr(s, rd);
207
- tcg_rn_ptr = vec_full_reg_ptr(s, rn);
208
- tcg_rm_ptr = vec_full_reg_ptr(s, rm);
209
-
210
- genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
211
-
212
- tcg_temp_free_ptr(tcg_rd_ptr);
213
- tcg_temp_free_ptr(tcg_rn_ptr);
214
- tcg_temp_free_ptr(tcg_rm_ptr);
215
+ gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64);
15
}
216
}
16
}
217
}
17
218
18
+static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
219
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
19
+ unsigned size)
220
int opcode = extract32(insn, 10, 2);
20
+{
221
int rn = extract32(insn, 5, 5);
21
+ switch (size) {
222
int rd = extract32(insn, 0, 5);
22
+ case 1:
223
- TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
23
+ return omap_sysctl_read8(opaque, addr);
224
bool feature;
24
+ case 2:
225
- CryptoTwoOpFn *genfn;
25
+ return omap_badwidth_read32(opaque, addr); /* TODO */
226
- gen_helper_gvec_3 *oolfn = NULL;
26
+ case 4:
227
27
+ return omap_sysctl_read(opaque, addr);
228
switch (opcode) {
28
+ default:
229
case 0: /* SHA512SU0 */
29
+ g_assert_not_reached();
230
feature = dc_isar_feature(aa64_sha512, s);
30
+ }
231
- genfn = gen_helper_crypto_sha512su0;
31
+}
232
break;
32
+
233
case 1: /* SM4E */
33
+static void omap_sysctl_writefn(void *opaque, hwaddr addr,
234
feature = dc_isar_feature(aa64_sm4, s);
34
+ uint64_t value, unsigned size)
235
- oolfn = gen_helper_crypto_sm4e;
35
+{
236
break;
36
+ switch (size) {
237
default:
37
+ case 1:
238
unallocated_encoding(s);
38
+ omap_sysctl_write8(opaque, addr, value);
239
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
240
return;
241
}
242
243
- if (oolfn) {
244
- gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn);
245
- return;
246
+ switch (opcode) {
247
+ case 0: /* SHA512SU0 */
248
+ gen_gvec_op2_ool(s, true, rd, rn, 0, gen_helper_crypto_sha512su0);
39
+ break;
249
+ break;
40
+ case 2:
250
+ case 1: /* SM4E */
41
+ omap_badwidth_write32(opaque, addr, value); /* TODO */
251
+ gen_gvec_op3_ool(s, true, rd, rd, rn, 0, gen_helper_crypto_sm4e);
42
+ break;
43
+ case 4:
44
+ omap_sysctl_write(opaque, addr, value);
45
+ break;
252
+ break;
46
+ default:
253
+ default:
47
+ g_assert_not_reached();
254
+ g_assert_not_reached();
48
+ }
255
}
49
+}
256
-
50
+
257
- tcg_rd_ptr = vec_full_reg_ptr(s, rd);
51
static const MemoryRegionOps omap_sysctl_ops = {
258
- tcg_rn_ptr = vec_full_reg_ptr(s, rn);
52
- .old_mmio = {
259
-
53
- .read = {
260
- genfn(tcg_rd_ptr, tcg_rn_ptr);
54
- omap_sysctl_read8,
261
-
55
- omap_badwidth_read32,    /* TODO */
262
- tcg_temp_free_ptr(tcg_rd_ptr);
56
- omap_sysctl_read,
263
- tcg_temp_free_ptr(tcg_rn_ptr);
57
- },
264
}
58
- .write = {
265
59
- omap_sysctl_write8,
266
/* Crypto four-register
60
- omap_badwidth_write32,    /* TODO */
61
- omap_sysctl_write,
62
- },
63
- },
64
+ .read = omap_sysctl_readfn,
65
+ .write = omap_sysctl_writefn,
66
+ .valid.min_access_size = 1,
67
+ .valid.max_access_size = 4,
68
.endianness = DEVICE_NATIVE_ENDIAN,
69
};
70
71
--
267
--
72
2.7.4
268
2.20.1
73
269
74
270
diff view generated by jsdifflib
1
In v8M the MSR and MRS instructions have extra register value
1
From: Richard Henderson <richard.henderson@linaro.org>
2
encodings to allow secure code to access the non-secure banked
3
version of various special registers.
4
2
5
(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because
3
Do not yet convert the helpers to loop over opr_sz, but the
6
we don't currently implement the stack limit registers at all.)
4
descriptor allows the vector tail to be cleared. Which fixes
5
an existing bug vs SVE.
7
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200514212831.31248-5-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
11
---
11
---
12
target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++
12
target/arm/helper.h | 12 ++--
13
1 file changed, 110 insertions(+)
13
target/arm/neon-dp.decode | 12 ++--
14
target/arm/crypto_helper.c | 24 +++++--
15
target/arm/translate-a64.c | 34 ++++-----
16
target/arm/translate-neon.inc.c | 124 +++++---------------------------
17
target/arm/translate.c | 24 ++-----
18
6 files changed, 67 insertions(+), 163 deletions(-)
14
19
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
22
--- a/target/arm/helper.h
18
+++ b/target/arm/helper.c
23
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
24
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
20
break;
25
DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
21
case 20: /* CONTROL */
26
22
return env->v7m.control[env->v7m.secure];
27
DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
23
+ case 0x94: /* CONTROL_NS */
28
-DEF_HELPER_FLAGS_2(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr)
24
+ /* We have to handle this here because unprivileged Secure code
29
-DEF_HELPER_FLAGS_2(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr)
25
+ * can read the NS CONTROL register.
30
+DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
26
+ */
31
+DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
27
+ if (!env->v7m.secure) {
32
28
+ return 0;
33
-DEF_HELPER_FLAGS_3(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
29
+ }
34
-DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
30
+ return env->v7m.control[M_REG_NS];
35
-DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr)
31
}
36
-DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
32
37
+DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
if (el == 0) {
38
+DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
34
return 0; /* unprivileged reads others as zero */
39
+DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
35
}
40
+DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
36
41
37
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
42
DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
38
+ switch (reg) {
43
DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
39
+ case 0x88: /* MSP_NS */
44
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
40
+ if (!env->v7m.secure) {
45
index XXXXXXX..XXXXXXX 100644
41
+ return 0;
46
--- a/target/arm/neon-dp.decode
42
+ }
47
+++ b/target/arm/neon-dp.decode
43
+ return env->v7m.other_ss_msp;
48
@@ -XXX,XX +XXX,XX @@ VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
44
+ case 0x89: /* PSP_NS */
49
45
+ if (!env->v7m.secure) {
50
VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
46
+ return 0;
51
47
+ }
52
+@3same_crypto .... .... .... .... .... .... .... .... \
48
+ return env->v7m.other_ss_psp;
53
+ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
49
+ case 0x90: /* PRIMASK_NS */
54
+
50
+ if (!env->v7m.secure) {
55
SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
51
+ return 0;
56
vm=%vm_dp vn=%vn_dp vd=%vd_dp
52
+ }
57
-SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \
53
+ return env->v7m.primask[M_REG_NS];
58
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
54
+ case 0x91: /* BASEPRI_NS */
59
-SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \
55
+ if (!env->v7m.secure) {
60
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
56
+ return 0;
61
-SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
57
+ }
62
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
58
+ return env->v7m.basepri[M_REG_NS];
63
+SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
59
+ case 0x93: /* FAULTMASK_NS */
64
+SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
60
+ if (!env->v7m.secure) {
65
+SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
61
+ return 0;
66
62
+ }
67
VFMA_fp_3s 1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
63
+ return env->v7m.faultmask[M_REG_NS];
68
VFMS_fp_3s 1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
64
+ case 0x98: /* SP_NS */
69
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
65
+ {
70
index XXXXXXX..XXXXXXX 100644
66
+ /* This gives the non-secure SP selected based on whether we're
71
--- a/target/arm/crypto_helper.c
67
+ * currently in handler mode or not, using the NS CONTROL.SPSEL.
72
+++ b/target/arm/crypto_helper.c
68
+ */
73
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
69
+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
74
rd[1] = d.l[1];
70
+
75
}
71
+ if (!env->v7m.secure) {
76
72
+ return 0;
77
-void HELPER(crypto_sha1h)(void *vd, void *vm)
73
+ }
78
+void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)
74
+ if (!arm_v7m_is_handler_mode(env) && spsel) {
79
{
75
+ return env->v7m.other_ss_psp;
80
uint64_t *rd = vd;
76
+ } else {
81
uint64_t *rm = vm;
77
+ return env->v7m.other_ss_msp;
82
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1h)(void *vd, void *vm)
78
+ }
83
79
+ }
84
rd[0] = m.l[0];
80
+ default:
85
rd[1] = m.l[1];
81
+ break;
86
+
82
+ }
87
+ clear_tail_16(vd, desc);
83
+ }
88
}
84
+
89
85
switch (reg) {
90
-void HELPER(crypto_sha1su1)(void *vd, void *vm)
86
case 8: /* MSP */
91
+void HELPER(crypto_sha1su1)(void *vd, void *vm, uint32_t desc)
87
return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
92
{
88
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
93
uint64_t *rd = vd;
94
uint64_t *rm = vm;
95
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1su1)(void *vd, void *vm)
96
97
rd[0] = d.l[0];
98
rd[1] = d.l[1];
99
+
100
+ clear_tail_16(vd, desc);
101
}
102
103
/*
104
@@ -XXX,XX +XXX,XX @@ static uint32_t s1(uint32_t x)
105
return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
106
}
107
108
-void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
109
+void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm, uint32_t desc)
110
{
111
uint64_t *rd = vd;
112
uint64_t *rn = vn;
113
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
114
115
rd[0] = d.l[0];
116
rd[1] = d.l[1];
117
+
118
+ clear_tail_16(vd, desc);
119
}
120
121
-void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
122
+void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm, uint32_t desc)
123
{
124
uint64_t *rd = vd;
125
uint64_t *rn = vn;
126
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm)
127
128
rd[0] = d.l[0];
129
rd[1] = d.l[1];
130
+
131
+ clear_tail_16(vd, desc);
132
}
133
134
-void HELPER(crypto_sha256su0)(void *vd, void *vm)
135
+void HELPER(crypto_sha256su0)(void *vd, void *vm, uint32_t desc)
136
{
137
uint64_t *rd = vd;
138
uint64_t *rm = vm;
139
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su0)(void *vd, void *vm)
140
141
rd[0] = d.l[0];
142
rd[1] = d.l[1];
143
+
144
+ clear_tail_16(vd, desc);
145
}
146
147
-void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
148
+void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm, uint32_t desc)
149
{
150
uint64_t *rd = vd;
151
uint64_t *rn = vn;
152
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm)
153
154
rd[0] = d.l[0];
155
rd[1] = d.l[1];
156
+
157
+ clear_tail_16(vd, desc);
158
}
159
160
/*
161
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
162
index XXXXXXX..XXXXXXX 100644
163
--- a/target/arm/translate-a64.c
164
+++ b/target/arm/translate-a64.c
165
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
166
int rm = extract32(insn, 16, 5);
167
int rn = extract32(insn, 5, 5);
168
int rd = extract32(insn, 0, 5);
169
- CryptoThreeOpFn *genfn;
170
- TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
171
+ gen_helper_gvec_3 *genfn;
172
bool feature;
173
174
if (size != 0) {
175
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
89
return;
176
return;
90
}
177
}
91
178
92
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
179
- tcg_rd_ptr = vec_full_reg_ptr(s, rd);
93
+ switch (reg) {
180
- tcg_rn_ptr = vec_full_reg_ptr(s, rn);
94
+ case 0x88: /* MSP_NS */
181
- tcg_rm_ptr = vec_full_reg_ptr(s, rm);
95
+ if (!env->v7m.secure) {
182
-
96
+ return;
183
if (genfn) {
97
+ }
184
- genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
98
+ env->v7m.other_ss_msp = val;
185
+ gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
99
+ return;
186
} else {
100
+ case 0x89: /* PSP_NS */
187
TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
101
+ if (!env->v7m.secure) {
188
+ TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
102
+ return;
189
+ TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
103
+ }
190
+ TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
104
+ env->v7m.other_ss_psp = val;
191
105
+ return;
192
gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
106
+ case 0x90: /* PRIMASK_NS */
193
tcg_rm_ptr, tcg_opcode);
107
+ if (!env->v7m.secure) {
194
- tcg_temp_free_i32(tcg_opcode);
108
+ return;
195
- }
109
+ }
196
110
+ env->v7m.primask[M_REG_NS] = val & 1;
197
- tcg_temp_free_ptr(tcg_rd_ptr);
111
+ return;
198
- tcg_temp_free_ptr(tcg_rn_ptr);
112
+ case 0x91: /* BASEPRI_NS */
199
- tcg_temp_free_ptr(tcg_rm_ptr);
113
+ if (!env->v7m.secure) {
200
+ tcg_temp_free_i32(tcg_opcode);
114
+ return;
201
+ tcg_temp_free_ptr(tcg_rd_ptr);
115
+ }
202
+ tcg_temp_free_ptr(tcg_rn_ptr);
116
+ env->v7m.basepri[M_REG_NS] = val & 0xff;
203
+ tcg_temp_free_ptr(tcg_rm_ptr);
117
+ return;
118
+ case 0x93: /* FAULTMASK_NS */
119
+ if (!env->v7m.secure) {
120
+ return;
121
+ }
122
+ env->v7m.faultmask[M_REG_NS] = val & 1;
123
+ return;
124
+ case 0x98: /* SP_NS */
125
+ {
126
+ /* This gives the non-secure SP selected based on whether we're
127
+ * currently in handler mode or not, using the NS CONTROL.SPSEL.
128
+ */
129
+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
130
+
131
+ if (!env->v7m.secure) {
132
+ return;
133
+ }
134
+ if (!arm_v7m_is_handler_mode(env) && spsel) {
135
+ env->v7m.other_ss_psp = val;
136
+ } else {
137
+ env->v7m.other_ss_msp = val;
138
+ }
139
+ return;
140
+ }
141
+ default:
142
+ break;
143
+ }
144
+ }
204
+ }
145
+
205
}
146
switch (reg) {
206
147
case 0 ... 7: /* xPSR sub-fields */
207
/* Crypto two-reg SHA
148
/* only APSR is actually writable */
208
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
209
int opcode = extract32(insn, 12, 5);
210
int rn = extract32(insn, 5, 5);
211
int rd = extract32(insn, 0, 5);
212
- CryptoTwoOpFn *genfn;
213
+ gen_helper_gvec_2 *genfn;
214
bool feature;
215
- TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
216
217
if (size != 0) {
218
unallocated_encoding(s);
219
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
220
if (!fp_access_check(s)) {
221
return;
222
}
223
-
224
- tcg_rd_ptr = vec_full_reg_ptr(s, rd);
225
- tcg_rn_ptr = vec_full_reg_ptr(s, rn);
226
-
227
- genfn(tcg_rd_ptr, tcg_rn_ptr);
228
-
229
- tcg_temp_free_ptr(tcg_rd_ptr);
230
- tcg_temp_free_ptr(tcg_rn_ptr);
231
+ gen_gvec_op2_ool(s, true, rd, rn, 0, genfn);
232
}
233
234
static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
235
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
236
index XXXXXXX..XXXXXXX 100644
237
--- a/target/arm/translate-neon.inc.c
238
+++ b/target/arm/translate-neon.inc.c
239
@@ -XXX,XX +XXX,XX @@ DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
240
DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
241
DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
242
243
-static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
244
- uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
245
-{
246
- tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
247
- 0, gen_helper_gvec_pmul_b);
248
-}
249
+#define WRAP_OOL_FN(WRAPNAME, FUNC) \
250
+ static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, \
251
+ uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) \
252
+ { \
253
+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \
254
+ }
255
+
256
+WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b)
257
258
static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
259
{
260
@@ -XXX,XX +XXX,XX @@ static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
261
return true;
262
}
263
264
-static bool trans_SHA256H_3s(DisasContext *s, arg_SHA256H_3s *a)
265
-{
266
- TCGv_ptr ptr1, ptr2, ptr3;
267
-
268
- if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
269
- !dc_isar_feature(aa32_sha2, s)) {
270
- return false;
271
+#define DO_SHA2(NAME, FUNC) \
272
+ WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \
273
+ static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \
274
+ { \
275
+ if (!dc_isar_feature(aa32_sha2, s)) { \
276
+ return false; \
277
+ } \
278
+ return do_3same(s, a, gen_##NAME##_3s); \
279
}
280
281
- /* UNDEF accesses to D16-D31 if they don't exist. */
282
- if (!dc_isar_feature(aa32_simd_r32, s) &&
283
- ((a->vd | a->vn | a->vm) & 0x10)) {
284
- return false;
285
- }
286
-
287
- if ((a->vn | a->vm | a->vd) & 1) {
288
- return false;
289
- }
290
-
291
- if (!vfp_access_check(s)) {
292
- return true;
293
- }
294
-
295
- ptr1 = vfp_reg_ptr(true, a->vd);
296
- ptr2 = vfp_reg_ptr(true, a->vn);
297
- ptr3 = vfp_reg_ptr(true, a->vm);
298
- gen_helper_crypto_sha256h(ptr1, ptr2, ptr3);
299
- tcg_temp_free_ptr(ptr1);
300
- tcg_temp_free_ptr(ptr2);
301
- tcg_temp_free_ptr(ptr3);
302
-
303
- return true;
304
-}
305
-
306
-static bool trans_SHA256H2_3s(DisasContext *s, arg_SHA256H2_3s *a)
307
-{
308
- TCGv_ptr ptr1, ptr2, ptr3;
309
-
310
- if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
311
- !dc_isar_feature(aa32_sha2, s)) {
312
- return false;
313
- }
314
-
315
- /* UNDEF accesses to D16-D31 if they don't exist. */
316
- if (!dc_isar_feature(aa32_simd_r32, s) &&
317
- ((a->vd | a->vn | a->vm) & 0x10)) {
318
- return false;
319
- }
320
-
321
- if ((a->vn | a->vm | a->vd) & 1) {
322
- return false;
323
- }
324
-
325
- if (!vfp_access_check(s)) {
326
- return true;
327
- }
328
-
329
- ptr1 = vfp_reg_ptr(true, a->vd);
330
- ptr2 = vfp_reg_ptr(true, a->vn);
331
- ptr3 = vfp_reg_ptr(true, a->vm);
332
- gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3);
333
- tcg_temp_free_ptr(ptr1);
334
- tcg_temp_free_ptr(ptr2);
335
- tcg_temp_free_ptr(ptr3);
336
-
337
- return true;
338
-}
339
-
340
-static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a)
341
-{
342
- TCGv_ptr ptr1, ptr2, ptr3;
343
-
344
- if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
345
- !dc_isar_feature(aa32_sha2, s)) {
346
- return false;
347
- }
348
-
349
- /* UNDEF accesses to D16-D31 if they don't exist. */
350
- if (!dc_isar_feature(aa32_simd_r32, s) &&
351
- ((a->vd | a->vn | a->vm) & 0x10)) {
352
- return false;
353
- }
354
-
355
- if ((a->vn | a->vm | a->vd) & 1) {
356
- return false;
357
- }
358
-
359
- if (!vfp_access_check(s)) {
360
- return true;
361
- }
362
-
363
- ptr1 = vfp_reg_ptr(true, a->vd);
364
- ptr2 = vfp_reg_ptr(true, a->vn);
365
- ptr3 = vfp_reg_ptr(true, a->vm);
366
- gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3);
367
- tcg_temp_free_ptr(ptr1);
368
- tcg_temp_free_ptr(ptr2);
369
- tcg_temp_free_ptr(ptr3);
370
-
371
- return true;
372
-}
373
+DO_SHA2(SHA256H, gen_helper_crypto_sha256h)
374
+DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2)
375
+DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
376
377
#define DO_3SAME_64(INSN, FUNC) \
378
static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
379
diff --git a/target/arm/translate.c b/target/arm/translate.c
380
index XXXXXXX..XXXXXXX 100644
381
--- a/target/arm/translate.c
382
+++ b/target/arm/translate.c
383
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
384
int vec_size;
385
uint32_t imm;
386
TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
387
- TCGv_ptr ptr1, ptr2;
388
+ TCGv_ptr ptr1;
389
TCGv_i64 tmp64;
390
391
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
392
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
393
if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
394
return 1;
395
}
396
- ptr1 = vfp_reg_ptr(true, rd);
397
- ptr2 = vfp_reg_ptr(true, rm);
398
-
399
- gen_helper_crypto_sha1h(ptr1, ptr2);
400
-
401
- tcg_temp_free_ptr(ptr1);
402
- tcg_temp_free_ptr(ptr2);
403
+ tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
404
+ gen_helper_crypto_sha1h);
405
break;
406
case NEON_2RM_SHA1SU1:
407
if ((rm | rd) & 1) {
408
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
409
} else if (!dc_isar_feature(aa32_sha1, s)) {
410
return 1;
411
}
412
- ptr1 = vfp_reg_ptr(true, rd);
413
- ptr2 = vfp_reg_ptr(true, rm);
414
- if (q) {
415
- gen_helper_crypto_sha256su0(ptr1, ptr2);
416
- } else {
417
- gen_helper_crypto_sha1su1(ptr1, ptr2);
418
- }
419
- tcg_temp_free_ptr(ptr1);
420
- tcg_temp_free_ptr(ptr2);
421
+ tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0,
422
+ q ? gen_helper_crypto_sha256su0
423
+ : gen_helper_crypto_sha1su1);
424
break;
425
-
426
case NEON_2RM_VMVN:
427
tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size);
428
break;
149
--
429
--
150
2.7.4
430
2.20.1
151
431
152
432
diff view generated by jsdifflib
Deleted patch
1
For the v8M security extension, some exceptions must be banked
2
between security states. Add the new vecinfo array which holds
3
the state for the banked exceptions and migrate it if the
4
CPU the NVIC is attached to implements the security extension.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/hw/intc/armv7m_nvic.h | 14 ++++++++++++
10
hw/intc/armv7m_nvic.c | 53 ++++++++++++++++++++++++++++++++++++++++++-
11
2 files changed, 66 insertions(+), 1 deletion(-)
12
13
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/armv7m_nvic.h
16
+++ b/include/hw/intc/armv7m_nvic.h
17
@@ -XXX,XX +XXX,XX @@
18
19
/* Highest permitted number of exceptions (architectural limit) */
20
#define NVIC_MAX_VECTORS 512
21
+/* Number of internal exceptions */
22
+#define NVIC_INTERNAL_VECTORS 16
23
24
typedef struct VecInfo {
25
/* Exception priorities can range from -3 to 255; only the unmodifiable
26
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
27
ARMCPU *cpu;
28
29
VecInfo vectors[NVIC_MAX_VECTORS];
30
+ /* If the v8M security extension is implemented, some of the internal
31
+ * exceptions are banked between security states (ie there exists both
32
+ * a Secure and a NonSecure version of the exception and its state):
33
+ * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
34
+ * The rest (including all the external exceptions) are not banked, though
35
+ * they may be configurable to target either Secure or NonSecure state.
36
+ * We store the secure exception state in sec_vectors[] for the banked
37
+ * exceptions, and otherwise use only vectors[] (including for exceptions
38
+ * like SecureFault that unconditionally target Secure state).
39
+ * Entries in sec_vectors[] for non-banked exception numbers are unused.
40
+ */
41
+ VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
42
uint32_t prigroup;
43
44
/* vectpending and exception_prio are both cached state that can
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
49
@@ -XXX,XX +XXX,XX @@
50
* For historical reasons QEMU tends to use "interrupt" and
51
* "exception" more or less interchangeably.
52
*/
53
-#define NVIC_FIRST_IRQ 16
54
+#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
55
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
56
57
/* Effective running priority of the CPU when no exception is active
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
59
}
60
};
61
62
+static bool nvic_security_needed(void *opaque)
63
+{
64
+ NVICState *s = opaque;
65
+
66
+ return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
67
+}
68
+
69
+static int nvic_security_post_load(void *opaque, int version_id)
70
+{
71
+ NVICState *s = opaque;
72
+ int i;
73
+
74
+ /* Check for out of range priority settings */
75
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
76
+ return 1;
77
+ }
78
+ for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
79
+ if (s->sec_vectors[i].prio & ~0xff) {
80
+ return 1;
81
+ }
82
+ }
83
+ return 0;
84
+}
85
+
86
+static const VMStateDescription vmstate_nvic_security = {
87
+ .name = "nvic/m-security",
88
+ .version_id = 1,
89
+ .minimum_version_id = 1,
90
+ .needed = nvic_security_needed,
91
+ .post_load = &nvic_security_post_load,
92
+ .fields = (VMStateField[]) {
93
+ VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
94
+ vmstate_VecInfo, VecInfo),
95
+ VMSTATE_END_OF_LIST()
96
+ }
97
+};
98
+
99
static const VMStateDescription vmstate_nvic = {
100
.name = "armv7m_nvic",
101
.version_id = 4,
102
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
103
vmstate_VecInfo, VecInfo),
104
VMSTATE_UINT32(prigroup, NVICState),
105
VMSTATE_END_OF_LIST()
106
+ },
107
+ .subsections = (const VMStateDescription*[]) {
108
+ &vmstate_nvic_security,
109
+ NULL
110
}
111
};
112
113
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
114
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
115
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
116
117
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
118
+ s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;
119
+ s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;
120
+ s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
121
+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
122
+
123
+ /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
124
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
125
+ }
126
+
127
/* Strictly speaking the reset handler should be enabled.
128
* However, we don't simulate soft resets through the NVIC,
129
* and the reset vector should never be pended.
130
--
131
2.7.4
132
133
diff view generated by jsdifflib
Deleted patch
1
With banked exceptions, just the exception number in
2
s->vectpending is no longer sufficient to uniquely identify
3
the pending exception. Add a vectpending_is_s_banked bool
4
which is true if the exception is using the sec_vectors[]
5
array.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
9
---
10
include/hw/intc/armv7m_nvic.h | 11 +++++++++--
11
hw/intc/armv7m_nvic.c | 1 +
12
2 files changed, 10 insertions(+), 2 deletions(-)
13
14
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/intc/armv7m_nvic.h
17
+++ b/include/hw/intc/armv7m_nvic.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
19
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
20
uint32_t prigroup;
21
22
- /* vectpending and exception_prio are both cached state that can
23
- * be recalculated from the vectors[] array and the prigroup field.
24
+ /* The following fields are all cached state that can be recalculated
25
+ * from the vectors[] and sec_vectors[] arrays and the prigroup field:
26
+ * - vectpending
27
+ * - vectpending_is_secure
28
+ * - exception_prio
29
*/
30
unsigned int vectpending; /* highest prio pending enabled exception */
31
+ /* true if vectpending is a banked secure exception, ie it is in
32
+ * sec_vectors[] rather than vectors[]
33
+ */
34
+ bool vectpending_is_s_banked;
35
int exception_prio; /* group prio of the highest prio active exception */
36
37
MemoryRegion sysregmem;
38
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/intc/armv7m_nvic.c
41
+++ b/hw/intc/armv7m_nvic.c
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
43
44
s->exception_prio = NVIC_NOEXC_PRIO;
45
s->vectpending = 0;
46
+ s->vectpending_is_s_banked = false;
47
}
48
49
static void nvic_systick_trigger(void *opaque, int n, int level)
50
--
51
2.7.4
52
53
diff view generated by jsdifflib
1
Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq()
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to handle banked exceptions:
2
3
* acknowledge needs to use the correct vector, which may be
3
Rather than passing an opcode to a helper, fully decode the
4
in sec_vectors[]
4
operation at translate time. Use clear_tail_16 to zap the
5
* acknowledge needs to return to its caller whether the
5
balance of the SVE register with the AdvSIMD write.
6
exception should be taken to secure or non-secure state
6
7
* complete needs its caller to tell it whether the exception
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
being completed is a secure one or not
8
Message-id: 20200514212831.31248-6-richard.henderson@linaro.org
9
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
13
---
11
---
14
target/arm/cpu.h | 15 +++++++++++++--
12
target/arm/helper.h | 5 +-
15
hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++++------
13
target/arm/neon-dp.decode | 6 +-
16
target/arm/helper.c | 8 +++++---
14
target/arm/crypto_helper.c | 99 +++++++++++++++++++++------------
17
hw/intc/trace-events | 4 ++--
15
target/arm/translate-a64.c | 29 ++++------
18
4 files changed, 40 insertions(+), 13 deletions(-)
16
target/arm/translate-neon.inc.c | 46 ++++-----------
19
17
5 files changed, 93 insertions(+), 92 deletions(-)
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
21
index XXXXXXX..XXXXXXX 100644
19
diff --git a/target/arm/helper.h b/target/arm/helper.h
22
--- a/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
23
+++ b/target/arm/cpu.h
21
--- a/target/arm/helper.h
24
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
22
+++ b/target/arm/helper.h
25
* of architecturally banked exceptions.
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
26
*/
24
DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
27
void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
25
DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
28
-void armv7m_nvic_acknowledge_irq(void *opaque);
26
29
+/**
27
-DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
30
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
28
+DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
31
+ * @opaque: the NVIC
29
+DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
32
+ *
30
+DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
+ * Move the current highest priority pending exception from the pending
31
+DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
34
+ * state to the active state, and update v7m.exception to indicate that
32
DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
35
+ * it is the exception currently being handled.
33
DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
36
+ *
34
37
+ * Returns: true if exception should be taken to Secure state, false for NS
35
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
38
+ */
36
index XXXXXXX..XXXXXXX 100644
39
+bool armv7m_nvic_acknowledge_irq(void *opaque);
37
--- a/target/arm/neon-dp.decode
40
/**
38
+++ b/target/arm/neon-dp.decode
41
* armv7m_nvic_complete_irq: complete specified interrupt or exception
39
@@ -XXX,XX +XXX,XX @@ VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
42
* @opaque: the NVIC
40
@3same_crypto .... .... .... .... .... .... .... .... \
43
* @irq: the exception number to complete
41
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
44
+ * @secure: true if this exception was secure
42
45
*
43
-SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
46
* Returns: -1 if the irq was not active
44
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
47
* 1 if completing this irq brought us back to base (no active irqs)
45
+SHA1C_3s 1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
48
* 0 if there is still an irq active after this one was completed
46
+SHA1P_3s 1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
49
* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
47
+SHA1M_3s 1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
50
*/
48
+SHA1SU0_3s 1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
51
-int armv7m_nvic_complete_irq(void *opaque, int irq);
49
SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
52
+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
50
SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
53
/**
51
SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
54
* armv7m_nvic_raw_execution_priority: return the raw execution priority
52
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
55
* @opaque: the NVIC
53
index XXXXXXX..XXXXXXX 100644
56
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
54
--- a/target/arm/crypto_helper.c
57
index XXXXXXX..XXXXXXX 100644
55
+++ b/target/arm/crypto_helper.c
58
--- a/hw/intc/armv7m_nvic.c
56
@@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE {
59
+++ b/hw/intc/armv7m_nvic.c
57
};
60
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
58
59
#ifdef HOST_WORDS_BIGENDIAN
60
-#define CR_ST_BYTE(state, i) (state.bytes[(15 - (i)) ^ 8])
61
-#define CR_ST_WORD(state, i) (state.words[(3 - (i)) ^ 2])
62
+#define CR_ST_BYTE(state, i) ((state).bytes[(15 - (i)) ^ 8])
63
+#define CR_ST_WORD(state, i) ((state).words[(3 - (i)) ^ 2])
64
#else
65
-#define CR_ST_BYTE(state, i) (state.bytes[i])
66
-#define CR_ST_WORD(state, i) (state.words[i])
67
+#define CR_ST_BYTE(state, i) ((state).bytes[i])
68
+#define CR_ST_WORD(state, i) ((state).words[i])
69
#endif
70
71
/*
72
@@ -XXX,XX +XXX,XX @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t z)
73
return (x & y) | ((x | y) & z);
61
}
74
}
62
75
63
/* Make pending IRQ active. */
76
-void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
64
-void armv7m_nvic_acknowledge_irq(void *opaque)
77
+void HELPER(crypto_sha1su0)(void *vd, void *vn, void *vm, uint32_t desc)
65
+bool armv7m_nvic_acknowledge_irq(void *opaque)
78
+{
79
+ uint64_t *d = vd, *n = vn, *m = vm;
80
+ uint64_t d0, d1;
81
+
82
+ d0 = d[1] ^ d[0] ^ m[0];
83
+ d1 = n[0] ^ d[1] ^ m[1];
84
+ d[0] = d0;
85
+ d[1] = d1;
86
+
87
+ clear_tail_16(vd, desc);
88
+}
89
+
90
+static inline void crypto_sha1_3reg(uint64_t *rd, uint64_t *rn,
91
+ uint64_t *rm, uint32_t desc,
92
+ uint32_t (*fn)(union CRYPTO_STATE *d))
66
{
93
{
67
NVICState *s = (NVICState *)opaque;
94
- uint64_t *rd = vd;
68
CPUARMState *env = &s->cpu->env;
95
- uint64_t *rn = vn;
69
const int pending = s->vectpending;
96
- uint64_t *rm = vm;
70
const int running = nvic_exec_prio(s);
97
union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
71
VecInfo *vec;
98
union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
72
+ bool targets_secure;
99
union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
73
100
+ int i;
74
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
101
75
102
- if (op == 3) { /* sha1su0 */
76
- vec = &s->vectors[pending];
103
- d.l[0] ^= d.l[1] ^ m.l[0];
77
+ if (s->vectpending_is_s_banked) {
104
- d.l[1] ^= n.l[0] ^ m.l[1];
78
+ vec = &s->sec_vectors[pending];
105
- } else {
79
+ targets_secure = true;
106
- int i;
80
+ } else {
107
+ for (i = 0; i < 4; i++) {
81
+ vec = &s->vectors[pending];
108
+ uint32_t t = fn(&d);
82
+ targets_secure = !exc_is_banked(s->vectpending) &&
109
83
+ exc_targets_secure(s, s->vectpending);
110
- for (i = 0; i < 4; i++) {
84
+ }
111
- uint32_t t;
85
112
+ t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0)
86
assert(vec->enabled);
113
+ + CR_ST_WORD(m, i);
87
assert(vec->pending);
114
88
115
- switch (op) {
89
assert(s->vectpending_prio < running);
116
- case 0: /* sha1c */
90
117
- t = cho(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
91
- trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
118
- break;
92
+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio, targets_secure);
119
- case 1: /* sha1p */
93
120
- t = par(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
94
vec->active = 1;
121
- break;
95
vec->pending = 0;
122
- case 2: /* sha1m */
96
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
123
- t = maj(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
97
env->v7m.exception = s->vectpending;
124
- break;
98
125
- default:
99
nvic_irq_update(s);
126
- g_assert_not_reached();
100
+
127
- }
101
+ return targets_secure;
128
- t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0)
129
- + CR_ST_WORD(m, i);
130
-
131
- CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3);
132
- CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2);
133
- CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2);
134
- CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0);
135
- CR_ST_WORD(d, 0) = t;
136
- }
137
+ CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3);
138
+ CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2);
139
+ CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2);
140
+ CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0);
141
+ CR_ST_WORD(d, 0) = t;
142
}
143
rd[0] = d.l[0];
144
rd[1] = d.l[1];
145
+
146
+ clear_tail_16(rd, desc);
147
+}
148
+
149
+static uint32_t do_sha1c(union CRYPTO_STATE *d)
150
+{
151
+ return cho(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
152
+}
153
+
154
+void HELPER(crypto_sha1c)(void *vd, void *vn, void *vm, uint32_t desc)
155
+{
156
+ crypto_sha1_3reg(vd, vn, vm, desc, do_sha1c);
157
+}
158
+
159
+static uint32_t do_sha1p(union CRYPTO_STATE *d)
160
+{
161
+ return par(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
162
+}
163
+
164
+void HELPER(crypto_sha1p)(void *vd, void *vn, void *vm, uint32_t desc)
165
+{
166
+ crypto_sha1_3reg(vd, vn, vm, desc, do_sha1p);
167
+}
168
+
169
+static uint32_t do_sha1m(union CRYPTO_STATE *d)
170
+{
171
+ return maj(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
172
+}
173
+
174
+void HELPER(crypto_sha1m)(void *vd, void *vn, void *vm, uint32_t desc)
175
+{
176
+ crypto_sha1_3reg(vd, vn, vm, desc, do_sha1m);
102
}
177
}
103
178
104
-int armv7m_nvic_complete_irq(void *opaque, int irq)
179
void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)
105
+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
180
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
106
{
181
index XXXXXXX..XXXXXXX 100644
107
NVICState *s = (NVICState *)opaque;
182
--- a/target/arm/translate-a64.c
108
VecInfo *vec;
183
+++ b/target/arm/translate-a64.c
109
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq)
184
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
110
185
111
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
186
switch (opcode) {
112
187
case 0: /* SHA1C */
113
- vec = &s->vectors[irq];
188
+ genfn = gen_helper_crypto_sha1c;
114
+ if (secure && exc_is_banked(irq)) {
189
+ feature = dc_isar_feature(aa64_sha1, s);
115
+ vec = &s->sec_vectors[irq];
190
+ break;
116
+ } else {
191
case 1: /* SHA1P */
117
+ vec = &s->vectors[irq];
192
+ genfn = gen_helper_crypto_sha1p;
118
+ }
193
+ feature = dc_isar_feature(aa64_sha1, s);
119
194
+ break;
120
- trace_nvic_complete_irq(irq);
195
case 2: /* SHA1M */
121
+ trace_nvic_complete_irq(irq, secure);
196
+ genfn = gen_helper_crypto_sha1m;
122
197
+ feature = dc_isar_feature(aa64_sha1, s);
123
if (!vec->active) {
198
+ break;
124
/* Tell the caller this was an illegal exception return */
199
case 3: /* SHA1SU0 */
125
diff --git a/target/arm/helper.c b/target/arm/helper.c
200
- genfn = NULL;
126
index XXXXXXX..XXXXXXX 100644
201
+ genfn = gen_helper_crypto_sha1su0;
127
--- a/target/arm/helper.c
202
feature = dc_isar_feature(aa64_sha1, s);
128
+++ b/target/arm/helper.c
203
break;
129
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
204
case 4: /* SHA256H */
130
bool return_to_sp_process = false;
205
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
131
bool return_to_handler = false;
206
if (!fp_access_check(s)) {
132
bool rettobase = false;
207
return;
133
+ bool exc_secure = false;
134
135
/* We can only get here from an EXCP_EXCEPTION_EXIT, and
136
* gen_bx_excret() enforces the architectural rule
137
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
138
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
139
*/
140
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
141
- int es = excret & R_V7M_EXCRET_ES_MASK;
142
+ exc_secure = excret & R_V7M_EXCRET_ES_MASK;
143
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
144
- env->v7m.faultmask[es] = 0;
145
+ env->v7m.faultmask[exc_secure] = 0;
146
}
147
} else {
148
env->v7m.faultmask[M_REG_NS] = 0;
149
}
150
}
208
}
151
209
-
152
- switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {
210
- if (genfn) {
153
+ switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception,
211
- gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
154
+ exc_secure)) {
212
- } else {
155
case -1:
213
- TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
156
/* attempt to exit an exception that isn't active */
214
- TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
157
ufault = true;
215
- TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
158
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
216
- TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
159
index XXXXXXX..XXXXXXX 100644
217
-
160
--- a/hw/intc/trace-events
218
- gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
161
+++ b/hw/intc/trace-events
219
- tcg_rm_ptr, tcg_opcode);
162
@@ -XXX,XX +XXX,XX @@ nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
220
-
163
nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
221
- tcg_temp_free_i32(tcg_opcode);
164
nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
222
- tcg_temp_free_ptr(tcg_rd_ptr);
165
nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
223
- tcg_temp_free_ptr(tcg_rn_ptr);
166
-nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
224
- tcg_temp_free_ptr(tcg_rm_ptr);
167
-nvic_complete_irq(int irq) "NVIC complete IRQ %d"
225
- }
168
+nvic_acknowledge_irq(int irq, int prio, bool targets_secure) "NVIC acknowledge IRQ: %d now active (prio %d targets_secure %d)"
226
+ gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
169
+nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
227
}
170
nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
228
171
nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
229
/* Crypto two-reg SHA
172
nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
230
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
231
index XXXXXXX..XXXXXXX 100644
232
--- a/target/arm/translate-neon.inc.c
233
+++ b/target/arm/translate-neon.inc.c
234
@@ -XXX,XX +XXX,XX @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
235
DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc)
236
DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc)
237
238
-static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
239
-{
240
- TCGv_ptr ptr1, ptr2, ptr3;
241
- TCGv_i32 tmp;
242
-
243
- if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
244
- !dc_isar_feature(aa32_sha1, s)) {
245
- return false;
246
+#define DO_SHA1(NAME, FUNC) \
247
+ WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \
248
+ static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \
249
+ { \
250
+ if (!dc_isar_feature(aa32_sha1, s)) { \
251
+ return false; \
252
+ } \
253
+ return do_3same(s, a, gen_##NAME##_3s); \
254
}
255
256
- /* UNDEF accesses to D16-D31 if they don't exist. */
257
- if (!dc_isar_feature(aa32_simd_r32, s) &&
258
- ((a->vd | a->vn | a->vm) & 0x10)) {
259
- return false;
260
- }
261
-
262
- if ((a->vn | a->vm | a->vd) & 1) {
263
- return false;
264
- }
265
-
266
- if (!vfp_access_check(s)) {
267
- return true;
268
- }
269
-
270
- ptr1 = vfp_reg_ptr(true, a->vd);
271
- ptr2 = vfp_reg_ptr(true, a->vn);
272
- ptr3 = vfp_reg_ptr(true, a->vm);
273
- tmp = tcg_const_i32(a->optype);
274
- gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp);
275
- tcg_temp_free_i32(tmp);
276
- tcg_temp_free_ptr(ptr1);
277
- tcg_temp_free_ptr(ptr2);
278
- tcg_temp_free_ptr(ptr3);
279
-
280
- return true;
281
-}
282
+DO_SHA1(SHA1C, gen_helper_crypto_sha1c)
283
+DO_SHA1(SHA1P, gen_helper_crypto_sha1p)
284
+DO_SHA1(SHA1M, gen_helper_crypto_sha1m)
285
+DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0)
286
287
#define DO_SHA2(NAME, FUNC) \
288
WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \
173
--
289
--
174
2.7.4
290
2.20.1
175
291
176
292
diff view generated by jsdifflib
1
Instead of looking up the pending priority
1
From: Richard Henderson <richard.henderson@linaro.org>
2
in nvic_pending_prio(), cache it in a new state struct
3
field. The calculation of the pending priority given
4
the interrupt number is more complicated in v8M with
5
the security extension, so the caching will be worthwhile.
6
2
7
This changes nvic_pending_prio() from returning a full
3
Rather than passing an opcode to a helper, fully decode the
8
(group + subpriority) priority value to returning a group
4
operation at translate time. Use clear_tail_16 to zap the
9
priority. This doesn't require changes to its callsites
5
balance of the SVE register with the AdvSIMD write.
10
because we use it only in comparisons of the form
11
execution_prio > nvic_pending_prio()
12
and execution priority is always a group priority, so
13
a test (exec prio > full prio) is true if and only if
14
(execprio > group_prio).
15
6
16
(Architecturally the expected comparison is with the
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
group priority for this sort of "would we preempt" test;
8
Message-id: 20200514212831.31248-7-richard.henderson@linaro.org
18
we were only doing a test with a full priority as an
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
optimisation to avoid the mask, which is possible
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
precisely because the two comparisons always give the
11
---
21
same answer.)
12
target/arm/helper.h | 5 ++++-
13
target/arm/crypto_helper.c | 24 ++++++++++++++++++------
14
target/arm/translate-a64.c | 21 +++++----------------
15
3 files changed, 27 insertions(+), 23 deletions(-)
22
16
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
26
---
27
include/hw/intc/armv7m_nvic.h | 2 ++
28
hw/intc/armv7m_nvic.c | 23 +++++++++++++----------
29
hw/intc/trace-events | 2 +-
30
3 files changed, 16 insertions(+), 11 deletions(-)
31
32
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
33
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/intc/armv7m_nvic.h
19
--- a/target/arm/helper.h
35
+++ b/include/hw/intc/armv7m_nvic.h
20
+++ b/target/arm/helper.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
37
* - vectpending
22
DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG,
38
* - vectpending_is_secure
23
void, ptr, ptr, ptr, i32)
39
* - exception_prio
24
40
+ * - vectpending_prio
25
-DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)
41
*/
26
+DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
42
unsigned int vectpending; /* highest prio pending enabled exception */
27
+DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
43
/* true if vectpending is a banked secure exception, ie it is in
28
+DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
44
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
29
+DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
45
*/
30
DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG,
46
bool vectpending_is_s_banked;
31
void, ptr, ptr, ptr, i32)
47
int exception_prio; /* group prio of the highest prio active exception */
32
DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG,
48
+ int vectpending_prio; /* group prio of the exeception in vectpending */
33
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
49
50
MemoryRegion sysregmem;
51
MemoryRegion sysreg_ns_mem;
52
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
53
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/intc/armv7m_nvic.c
35
--- a/target/arm/crypto_helper.c
55
+++ b/hw/intc/armv7m_nvic.c
36
+++ b/target/arm/crypto_helper.c
56
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
37
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm, uint32_t desc)
57
38
clear_tail_16(vd, desc);
58
static int nvic_pending_prio(NVICState *s)
39
}
40
41
-void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
42
- uint32_t opcode)
43
+static inline void QEMU_ALWAYS_INLINE
44
+crypto_sm3tt(uint64_t *rd, uint64_t *rn, uint64_t *rm,
45
+ uint32_t desc, uint32_t opcode)
59
{
46
{
60
- /* return the priority of the current pending interrupt,
47
- uint64_t *rd = vd;
61
+ /* return the group priority of the current pending interrupt,
48
- uint64_t *rn = vn;
62
* or NVIC_NOEXC_PRIO if no interrupt is pending
49
- uint64_t *rm = vm;
63
*/
50
union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
64
- return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
51
union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
65
+ return s->vectpending_prio;
52
union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
53
+ uint32_t imm2 = simd_data(desc);
54
uint32_t t;
55
56
assert(imm2 < 4);
57
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
58
/* SM3TT2B */
59
t = cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1));
60
} else {
61
- g_assert_not_reached();
62
+ qemu_build_not_reached();
63
}
64
65
t += CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2);
66
@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
67
68
rd[0] = d.l[0];
69
rd[1] = d.l[1];
70
+
71
+ clear_tail_16(rd, desc);
66
}
72
}
67
73
68
/* Return the value of the ISCR RETTOBASE bit:
74
+#define DO_SM3TT(NAME, OPCODE) \
69
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
75
+ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
70
active_prio &= nvic_gprio_mask(s);
76
+ { crypto_sm3tt(vd, vn, vm, desc, OPCODE); }
77
+
78
+DO_SM3TT(crypto_sm3tt1a, 0)
79
+DO_SM3TT(crypto_sm3tt1b, 1)
80
+DO_SM3TT(crypto_sm3tt2a, 2)
81
+DO_SM3TT(crypto_sm3tt2b, 3)
82
+
83
+#undef DO_SM3TT
84
+
85
static uint8_t const sm4_sbox[] = {
86
0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
87
0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
88
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/translate-a64.c
91
+++ b/target/arm/translate-a64.c
92
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn)
93
*/
94
static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
95
{
96
+ static gen_helper_gvec_3 * const fns[4] = {
97
+ gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b,
98
+ gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b,
99
+ };
100
int opcode = extract32(insn, 10, 2);
101
int imm2 = extract32(insn, 12, 2);
102
int rm = extract32(insn, 16, 5);
103
int rn = extract32(insn, 5, 5);
104
int rd = extract32(insn, 0, 5);
105
- TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
106
- TCGv_i32 tcg_imm2, tcg_opcode;
107
108
if (!dc_isar_feature(aa64_sm3, s)) {
109
unallocated_encoding(s);
110
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
111
return;
71
}
112
}
72
113
73
+ if (pend_prio > 0) {
114
- tcg_rd_ptr = vec_full_reg_ptr(s, rd);
74
+ pend_prio &= nvic_gprio_mask(s);
115
- tcg_rn_ptr = vec_full_reg_ptr(s, rn);
75
+ }
116
- tcg_rm_ptr = vec_full_reg_ptr(s, rm);
76
+
117
- tcg_imm2 = tcg_const_i32(imm2);
77
s->vectpending = pend_irq;
118
- tcg_opcode = tcg_const_i32(opcode);
78
+ s->vectpending_prio = pend_prio;
119
-
79
s->exception_prio = active_prio;
120
- gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2,
80
121
- tcg_opcode);
81
- trace_nvic_recompute_state(s->vectpending, s->exception_prio);
122
-
82
+ trace_nvic_recompute_state(s->vectpending,
123
- tcg_temp_free_ptr(tcg_rd_ptr);
83
+ s->vectpending_prio,
124
- tcg_temp_free_ptr(tcg_rn_ptr);
84
+ s->exception_prio);
125
- tcg_temp_free_ptr(tcg_rm_ptr);
126
- tcg_temp_free_i32(tcg_imm2);
127
- tcg_temp_free_i32(tcg_opcode);
128
+ gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]);
85
}
129
}
86
130
87
/* Return the current execution priority of the CPU
131
/* C3.6 Data processing - SIMD, inc Crypto
88
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
89
CPUARMState *env = &s->cpu->env;
90
const int pending = s->vectpending;
91
const int running = nvic_exec_prio(s);
92
- int pendgroupprio;
93
VecInfo *vec;
94
95
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
96
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
97
assert(vec->enabled);
98
assert(vec->pending);
99
100
- pendgroupprio = vec->prio;
101
- if (pendgroupprio > 0) {
102
- pendgroupprio &= nvic_gprio_mask(s);
103
- }
104
- assert(pendgroupprio < running);
105
+ assert(s->vectpending_prio < running);
106
107
- trace_nvic_acknowledge_irq(pending, vec->prio);
108
+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
109
110
vec->active = 1;
111
vec->pending = 0;
112
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
113
s->exception_prio = NVIC_NOEXC_PRIO;
114
s->vectpending = 0;
115
s->vectpending_is_s_banked = false;
116
+ s->vectpending_prio = NVIC_NOEXC_PRIO;
117
}
118
119
static void nvic_systick_trigger(void *opaque, int n, int level)
120
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
121
index XXXXXXX..XXXXXXX 100644
122
--- a/hw/intc/trace-events
123
+++ b/hw/intc/trace-events
124
@@ -XXX,XX +XXX,XX @@ gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor 0x%x
125
gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending SGI %d"
126
127
# hw/intc/armv7m_nvic.c
128
-nvic_recompute_state(int vectpending, int exception_prio) "NVIC state recomputed: vectpending %d exception_prio %d"
129
+nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
130
nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
131
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
132
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
133
--
132
--
134
2.7.4
133
2.20.1
135
134
136
135
diff view generated by jsdifflib
1
In v7M, the fixed-priority exceptions are:
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Reset: -3
3
NMI: -2
4
HardFault: -1
5
2
6
In v8M, this changes because Secure HardFault may need
3
The ADC region size is 256B, split as:
7
to be prioritised above NMI:
4
- [0x00 - 0x4f] defined
8
Reset: -4
5
- [0x50 - 0xff] reserved
9
Secure HardFault if AIRCR.BFHFNMINS == 1: -3
10
NMI: -2
11
Secure HardFault if AIRCR.BFHFNMINS == 0: -1
12
NonSecure HardFault: -1
13
6
14
Make these changes, including support for changing the
7
All registers are 32-bit (thus when the datasheet mentions the
15
priority of Secure HardFault as AIRCR.BFHFNMINS changes.
8
last defined register is 0x4c, it means its address range is
9
0x4c .. 0x4f.
16
10
11
This model implementation is also 32-bit. Set MemoryRegionOps
12
'impl' fields.
13
14
See:
15
'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
16
17
Reported-by: Seth Kintigh <skintigh@gmail.com>
18
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20200603055915.17678-1-f4bug@amsat.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 1505240046-11454-14-git-send-email-peter.maydell@linaro.org
20
---
22
---
21
hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++---
23
hw/adc/stm32f2xx_adc.c | 4 +++-
22
1 file changed, 19 insertions(+), 3 deletions(-)
24
1 file changed, 3 insertions(+), 1 deletion(-)
23
25
24
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
26
diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
25
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/intc/armv7m_nvic.c
28
--- a/hw/adc/stm32f2xx_adc.c
27
+++ b/hw/intc/armv7m_nvic.c
29
+++ b/hw/adc/stm32f2xx_adc.c
28
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
30
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps stm32f2xx_adc_ops = {
29
(R_V7M_AIRCR_SYSRESETREQS_MASK |
31
.read = stm32f2xx_adc_read,
30
R_V7M_AIRCR_BFHFNMINS_MASK |
32
.write = stm32f2xx_adc_write,
31
R_V7M_AIRCR_PRIS_MASK);
33
.endianness = DEVICE_NATIVE_ENDIAN,
32
+ /* BFHFNMINS changes the priority of Secure HardFault */
34
+ .impl.min_access_size = 4,
33
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
35
+ .impl.max_access_size = 4,
34
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
36
};
35
+ } else {
37
36
+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
38
static const VMStateDescription vmstate_stm32f2xx_adc = {
37
+ }
39
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_adc_init(Object *obj)
38
}
40
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
39
nvic_irq_update(s);
41
40
}
42
memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
41
@@ -XXX,XX +XXX,XX @@ static int nvic_post_load(void *opaque, int version_id)
43
- TYPE_STM32F2XX_ADC, 0xFF);
42
{
44
+ TYPE_STM32F2XX_ADC, 0x100);
43
NVICState *s = opaque;
45
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
44
unsigned i;
46
}
45
+ int resetprio;
46
47
/* Check for out of range priority settings */
48
- if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
49
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
50
+
51
+ if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio ||
52
s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
53
s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
54
return 1;
55
@@ -XXX,XX +XXX,XX @@ static int nvic_security_post_load(void *opaque, int version_id)
56
int i;
57
58
/* Check for out of range priority settings */
59
- if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {
60
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1
61
+ && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) {
62
+ /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
63
+ * if the CPU state has been migrated yet; a mismatch won't
64
+ * cause the emulation to blow up, though.
65
+ */
66
return 1;
67
}
68
for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {
69
@@ -XXX,XX +XXX,XX @@ static Property props_nvic[] = {
70
71
static void armv7m_nvic_reset(DeviceState *dev)
72
{
73
+ int resetprio;
74
NVICState *s = NVIC(dev);
75
76
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
77
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
78
s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
79
s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
80
81
- s->vectors[ARMV7M_EXCP_RESET].prio = -3;
82
+ resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
83
+ s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
84
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
85
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
86
47
87
--
48
--
88
2.7.4
49
2.20.1
89
50
90
51
diff view generated by jsdifflib
1
The ICSR NVIC register is banked for v8M. This doesn't
1
From: Thomas Huth <thuth@redhat.com>
2
require any new state, but it does mean that some bits
3
are controlled by BFHNFNMINS and some bits must work
4
with the correct banked exception. There is also a new
5
in v8M PENDNMICLR bit.
6
2
3
As described by Edgar here:
4
5
https://www.mail-archive.com/qemu-devel@nongnu.org/msg605124.html
6
7
we can use the Ubuntu kernel for testing the xlnx-versal-virt machine.
8
So let's add a boot test for this now.
9
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Signed-off-by: Thomas Huth <thuth@redhat.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
15
Message-id: 20200525141237.15243-1-thuth@redhat.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 1505240046-11454-18-git-send-email-peter.maydell@linaro.org
10
---
17
---
11
hw/intc/armv7m_nvic.c | 45 ++++++++++++++++++++++++++++++++-------------
18
tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++
12
1 file changed, 32 insertions(+), 13 deletions(-)
19
1 file changed, 26 insertions(+)
13
20
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
21
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
23
--- a/tests/acceptance/boot_linux_console.py
17
+++ b/hw/intc/armv7m_nvic.c
24
+++ b/tests/acceptance/boot_linux_console.py
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
25
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
19
}
26
console_pattern = 'Kernel command line: %s' % kernel_command_line
20
case 0xd00: /* CPUID Base. */
27
self.wait_for_console_pattern(console_pattern)
21
return cpu->midr;
28
22
- case 0xd04: /* Interrupt Control State. */
29
+ def test_aarch64_xlnx_versal_virt(self):
23
+ case 0xd04: /* Interrupt Control State (ICSR) */
30
+ """
24
/* VECTACTIVE */
31
+ :avocado: tags=arch:aarch64
25
val = cpu->env.v7m.exception;
32
+ :avocado: tags=machine:xlnx-versal-virt
26
/* VECTPENDING */
33
+ :avocado: tags=device:pl011
27
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
34
+ :avocado: tags=device:arm_gicv3
28
if (nvic_rettobase(s)) {
35
+ """
29
val |= (1 << 11);
36
+ kernel_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'
30
}
37
+ 'bionic-updates/main/installer-arm64/current/images/'
31
- /* PENDSTSET */
38
+ 'netboot/ubuntu-installer/arm64/linux')
32
- if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
39
+ kernel_hash = '5bfc54cf7ed8157d93f6e5b0241e727b6dc22c50'
33
- val |= (1 << 26);
40
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
34
- }
41
+
35
- /* PENDSVSET */
42
+ initrd_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/'
36
- if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
43
+ 'bionic-updates/main/installer-arm64/current/images/'
37
- val |= (1 << 28);
44
+ 'netboot/ubuntu-installer/arm64/initrd.gz')
38
+ if (attrs.secure) {
45
+ initrd_hash = 'd385d3e88d53e2004c5d43cbe668b458a094f772'
39
+ /* PENDSTSET */
46
+ initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
40
+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {
47
+
41
+ val |= (1 << 26);
48
+ self.vm.set_console()
42
+ }
49
+ self.vm.add_args('-m', '2G',
43
+ /* PENDSVSET */
50
+ '-kernel', kernel_path,
44
+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {
51
+ '-initrd', initrd_path)
45
+ val |= (1 << 28);
52
+ self.vm.launch()
46
+ }
53
+ self.wait_for_console_pattern('Checked W+X mappings: passed')
47
+ } else {
54
+
48
+ /* PENDSTSET */
55
def test_arm_virt(self):
49
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
56
"""
50
+ val |= (1 << 26);
57
:avocado: tags=arch:arm
51
+ }
52
+ /* PENDSVSET */
53
+ if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
54
+ val |= (1 << 28);
55
+ }
56
}
57
/* NMIPENDSET */
58
- if (s->vectors[ARMV7M_EXCP_NMI].pending) {
59
+ if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
60
+ s->vectors[ARMV7M_EXCP_NMI].pending) {
61
val |= (1 << 31);
62
}
63
- /* ISRPREEMPT not implemented */
64
+ /* ISRPREEMPT: RES0 when halting debug not implemented */
65
+ /* STTNS: RES0 for the Main Extension */
66
return val;
67
case 0xd08: /* Vector Table Offset. */
68
return cpu->env.v7m.vecbase[attrs.secure];
69
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
70
nvic_irq_update(s);
71
break;
72
}
73
- case 0xd04: /* Interrupt Control State. */
74
- if (value & (1 << 31)) {
75
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
76
+ case 0xd04: /* Interrupt Control State (ICSR) */
77
+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
78
+ if (value & (1 << 31)) {
79
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
80
+ } else if (value & (1 << 30) &&
81
+ arm_feature(&cpu->env, ARM_FEATURE_V8)) {
82
+ /* PENDNMICLR didn't exist in v7M */
83
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false);
84
+ }
85
}
86
if (value & (1 << 28)) {
87
armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
88
--
58
--
89
2.7.4
59
2.20.1
90
60
91
61
diff view generated by jsdifflib
1
For v8M, the NVIC has a new set of registers per interrupt,
1
From: Cédric Le Goater <clg@kaod.org>
2
NVIC_ITNS<n>. These determine whether the interrupt targets Secure
3
or Non-secure state. Implement the register read/write code for
4
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
5
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
6
accesses to fields corresponding to interrupts which are
7
configured to target secure state.
8
2
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20200602135050.593692-1-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
12
---
7
---
13
include/hw/intc/armv7m_nvic.h | 3 ++
8
docs/system/arm/aspeed.rst | 85 ++++++++++++++++++++++++++++++++++++++
14
hw/intc/armv7m_nvic.c | 74 +++++++++++++++++++++++++++++++++++++++----
9
docs/system/target-arm.rst | 1 +
15
2 files changed, 70 insertions(+), 7 deletions(-)
10
2 files changed, 86 insertions(+)
11
create mode 100644 docs/system/arm/aspeed.rst
16
12
17
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
13
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
14
new file mode 100644
15
index XXXXXXX..XXXXXXX
16
--- /dev/null
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@
19
+Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``)
20
+==================================================================
21
+
22
+The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
23
+Aspeed evaluation boards. They are based on different releases of the
24
+Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
25
+AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600
26
+with dual cores ARM Cortex A7 CPUs (1.2GHz).
27
+
28
+The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
29
+etc.
30
+
31
+AST2400 SoC based machines :
32
+
33
+- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
34
+
35
+AST2500 SoC based machines :
36
+
37
+- ``ast2500-evb`` Aspeed AST2500 Evaluation board
38
+- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
39
+- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
40
+- ``sonorapass-bmc`` OCP SonoraPass BMC
41
+- ``swift-bmc`` OpenPOWER Swift BMC POWER9
42
+
43
+AST2600 SoC based machines :
44
+
45
+- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex A7)
46
+- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC
47
+
48
+Supported devices
49
+-----------------
50
+
51
+ * SMP (for the AST2600 Cortex-A7)
52
+ * Interrupt Controller (VIC)
53
+ * Timer Controller
54
+ * RTC Controller
55
+ * I2C Controller
56
+ * System Control Unit (SCU)
57
+ * SRAM mapping
58
+ * X-DMA Controller (basic interface)
59
+ * Static Memory Controller (SMC or FMC) - Only SPI Flash support
60
+ * SPI Memory Controller
61
+ * USB 2.0 Controller
62
+ * SD/MMC storage controllers
63
+ * SDRAM controller (dummy interface for basic settings and training)
64
+ * Watchdog Controller
65
+ * GPIO Controller (Master only)
66
+ * UART
67
+ * Ethernet controllers
68
+
69
+
70
+Missing devices
71
+---------------
72
+
73
+ * Coprocessor support
74
+ * ADC (out of tree implementation)
75
+ * PWM and Fan Controller
76
+ * LPC Bus Controller
77
+ * Slave GPIO Controller
78
+ * Super I/O Controller
79
+ * Hash/Crypto Engine
80
+ * PCI-Express 1 Controller
81
+ * Graphic Display Controller
82
+ * PECI Controller
83
+ * MCTP Controller
84
+ * Mailbox Controller
85
+ * Virtual UART
86
+ * eSPI Controller
87
+ * I3C Controller
88
+
89
+Boot options
90
+------------
91
+
92
+The Aspeed machines can be started using the -kernel option to load a
93
+Linux kernel or from a firmare image which can be downloaded from the
94
+OpenPOWER jenkins :
95
+
96
+ https://openpower.xyz/
97
+
98
+The image should be attached as an MTD drive. Run :
99
+
100
+.. code-block:: bash
101
+
102
+ $ qemu-system-arm -M romulus-bmc -nic user \
103
+    -drive file=flash-romulus,format=raw,if=mtd -nographic
104
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
18
index XXXXXXX..XXXXXXX 100644
105
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/intc/armv7m_nvic.h
106
--- a/docs/system/target-arm.rst
20
+++ b/include/hw/intc/armv7m_nvic.h
107
+++ b/docs/system/target-arm.rst
21
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
108
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
22
/* The PRIGROUP field in AIRCR is banked */
109
arm/realview
23
uint32_t prigroup[M_REG_NUM_BANKS];
110
arm/versatile
24
111
arm/vexpress
25
+ /* v8M NVIC_ITNS state (stored as a bool per bit) */
112
+ arm/aspeed
26
+ bool itns[NVIC_MAX_VECTORS];
113
arm/musicpal
27
+
114
arm/nseries
28
/* The following fields are all cached state that can be recalculated
115
arm/orangepi
29
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
30
* - vectpending
31
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/intc/armv7m_nvic.c
34
+++ b/hw/intc/armv7m_nvic.c
35
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
36
switch (offset) {
37
case 4: /* Interrupt Control Type. */
38
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
39
+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
40
+ {
41
+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
42
+ int i;
43
+
44
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
45
+ goto bad_offset;
46
+ }
47
+ if (!attrs.secure) {
48
+ return 0;
49
+ }
50
+ val = 0;
51
+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
52
+ if (s->itns[startvec + i]) {
53
+ val |= (1 << i);
54
+ }
55
+ }
56
+ return val;
57
+ }
58
case 0xd00: /* CPUID Base. */
59
return cpu->midr;
60
case 0xd04: /* Interrupt Control State. */
61
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
62
ARMCPU *cpu = s->cpu;
63
64
switch (offset) {
65
+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
66
+ {
67
+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;
68
+ int i;
69
+
70
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
71
+ goto bad_offset;
72
+ }
73
+ if (!attrs.secure) {
74
+ break;
75
+ }
76
+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {
77
+ s->itns[startvec + i] = (value >> i) & 1;
78
+ }
79
+ nvic_irq_update(s);
80
+ break;
81
+ }
82
case 0xd04: /* Interrupt Control State. */
83
if (value & (1 << 31)) {
84
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
85
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
86
startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
87
88
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
89
- if (s->vectors[startvec + i].enabled) {
90
+ if (s->vectors[startvec + i].enabled &&
91
+ (attrs.secure || s->itns[startvec + i])) {
92
val |= (1 << i);
93
}
94
}
95
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
96
val = 0;
97
startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
98
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
99
- if (s->vectors[startvec + i].pending) {
100
+ if (s->vectors[startvec + i].pending &&
101
+ (attrs.secure || s->itns[startvec + i])) {
102
val |= (1 << i);
103
}
104
}
105
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
106
startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
107
108
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
109
- if (s->vectors[startvec + i].active) {
110
+ if (s->vectors[startvec + i].active &&
111
+ (attrs.secure || s->itns[startvec + i])) {
112
val |= (1 << i);
113
}
114
}
115
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
116
startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
117
118
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
119
- val |= s->vectors[startvec + i].prio << (8 * i);
120
+ if (attrs.secure || s->itns[startvec + i]) {
121
+ val |= s->vectors[startvec + i].prio << (8 * i);
122
+ }
123
}
124
break;
125
case 0xd18 ... 0xd23: /* System Handler Priority. */
126
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
127
startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
128
129
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
130
- if (value & (1 << i)) {
131
+ if (value & (1 << i) &&
132
+ (attrs.secure || s->itns[startvec + i])) {
133
s->vectors[startvec + i].enabled = setval;
134
}
135
}
136
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
137
startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
138
139
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
140
- if (value & (1 << i)) {
141
+ if (value & (1 << i) &&
142
+ (attrs.secure || s->itns[startvec + i])) {
143
s->vectors[startvec + i].pending = setval;
144
}
145
}
146
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
147
startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
148
149
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
150
- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
151
+ if (attrs.secure || s->itns[startvec + i]) {
152
+ set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
153
+ }
154
}
155
nvic_irq_update(s);
156
return MEMTX_OK;
157
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
158
VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
159
vmstate_VecInfo, VecInfo),
160
VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
161
+ VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),
162
VMSTATE_END_OF_LIST()
163
}
164
};
165
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
166
s->vectpending = 0;
167
s->vectpending_is_s_banked = false;
168
s->vectpending_prio = NVIC_NOEXC_PRIO;
169
+
170
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
171
+ memset(s->itns, 0, sizeof(s->itns));
172
+ } else {
173
+ /* This state is constant and not guest accessible in a non-security
174
+ * NVIC; we set the bits to true to avoid having to do a feature
175
+ * bit check in the NVIC enable/pend/etc register accessors.
176
+ */
177
+ int i;
178
+
179
+ for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {
180
+ s->itns[i] = true;
181
+ }
182
+ }
183
}
184
185
static void nvic_systick_trigger(void *opaque, int n, int level)
186
--
116
--
187
2.7.4
117
2.20.1
188
118
189
119
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Paul Zimmerman <pauldzim@gmail.com>
2
2
3
Modelled Microsemi's Smartfusion2 SPI controller.
3
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
4
4
emulation. It is very basic, only providing the FIQ interrupt
5
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
5
needed to allow the dwc-otg USB host controller driver in the
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
6
Raspbian kernel to function.
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
8
Message-id: 20170920201737.25723-4-f4bug@amsat.org
8
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
9
Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200520235349.21215-2-pauldzim@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
hw/ssi/Makefile.objs | 1 +
14
include/hw/arm/bcm2835_peripherals.h | 2 +
12
include/hw/ssi/mss-spi.h | 58 +++++++
15
include/hw/misc/bcm2835_mphi.h | 44 ++++++
13
hw/ssi/mss-spi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++
16
hw/arm/bcm2835_peripherals.c | 17 +++
14
3 files changed, 463 insertions(+)
17
hw/misc/bcm2835_mphi.c | 191 +++++++++++++++++++++++++++
15
create mode 100644 include/hw/ssi/mss-spi.h
18
hw/misc/Makefile.objs | 1 +
16
create mode 100644 hw/ssi/mss-spi.c
19
5 files changed, 255 insertions(+)
17
20
create mode 100644 include/hw/misc/bcm2835_mphi.h
18
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
21
create mode 100644 hw/misc/bcm2835_mphi.c
22
23
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
19
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ssi/Makefile.objs
25
--- a/include/hw/arm/bcm2835_peripherals.h
21
+++ b/hw/ssi/Makefile.objs
26
+++ b/include/hw/arm/bcm2835_peripherals.h
22
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
27
@@ -XXX,XX +XXX,XX @@
23
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
28
#include "hw/misc/bcm2835_property.h"
24
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
29
#include "hw/misc/bcm2835_rng.h"
25
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
30
#include "hw/misc/bcm2835_mbox.h"
26
+common-obj-$(CONFIG_MSF2) += mss-spi.o
31
+#include "hw/misc/bcm2835_mphi.h"
27
32
#include "hw/misc/bcm2835_thermal.h"
28
obj-$(CONFIG_OMAP) += omap_spi.o
33
#include "hw/sd/sdhci.h"
29
obj-$(CONFIG_IMX) += imx_spi.o
34
#include "hw/sd/bcm2835_sdhost.h"
30
diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
35
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
36
qemu_irq irq, fiq;
37
38
BCM2835SystemTimerState systmr;
39
+ BCM2835MphiState mphi;
40
UnimplementedDeviceState armtmr;
41
UnimplementedDeviceState cprman;
42
UnimplementedDeviceState a2w;
43
diff --git a/include/hw/misc/bcm2835_mphi.h b/include/hw/misc/bcm2835_mphi.h
31
new file mode 100644
44
new file mode 100644
32
index XXXXXXX..XXXXXXX
45
index XXXXXXX..XXXXXXX
33
--- /dev/null
46
--- /dev/null
34
+++ b/include/hw/ssi/mss-spi.h
47
+++ b/include/hw/misc/bcm2835_mphi.h
35
@@ -XXX,XX +XXX,XX @@
48
@@ -XXX,XX +XXX,XX @@
36
+/*
49
+/*
37
+ * Microsemi SmartFusion2 SPI
50
+ * BCM2835 SOC MPHI state definitions
38
+ *
51
+ *
39
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
52
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
40
+ *
53
+ *
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
54
+ * This program is free software; you can redistribute it and/or modify
42
+ * of this software and associated documentation files (the "Software"), to deal
55
+ * it under the terms of the GNU General Public License as published by
43
+ * in the Software without restriction, including without limitation the rights
56
+ * the Free Software Foundation; either version 2 of the License, or
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
57
+ * (at your option) any later version.
45
+ * copies of the Software, and to permit persons to whom the Software is
58
+ *
46
+ * furnished to do so, subject to the following conditions:
59
+ * This program is distributed in the hope that it will be useful,
47
+ *
60
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
48
+ * The above copyright notice and this permission notice shall be included in
61
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
49
+ * all copies or substantial portions of the Software.
62
+ * GNU General Public License for more details.
50
+ *
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
57
+ * THE SOFTWARE.
58
+ */
63
+ */
59
+
64
+
60
+#ifndef HW_MSS_SPI_H
65
+#ifndef HW_MISC_BCM2835_MPHI_H
61
+#define HW_MSS_SPI_H
66
+#define HW_MISC_BCM2835_MPHI_H
62
+
67
+
68
+#include "hw/irq.h"
63
+#include "hw/sysbus.h"
69
+#include "hw/sysbus.h"
64
+#include "hw/ssi/ssi.h"
70
+
65
+#include "qemu/fifo32.h"
71
+#define MPHI_MMIO_SIZE 0x1000
66
+
72
+
67
+#define TYPE_MSS_SPI "mss-spi"
73
+typedef struct BCM2835MphiState BCM2835MphiState;
68
+#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
74
+
69
+
75
+struct BCM2835MphiState {
70
+#define R_SPI_MAX 16
71
+
72
+typedef struct MSSSpiState {
73
+ SysBusDevice parent_obj;
76
+ SysBusDevice parent_obj;
74
+
75
+ MemoryRegion mmio;
76
+
77
+ qemu_irq irq;
77
+ qemu_irq irq;
78
+
78
+ MemoryRegion iomem;
79
+ qemu_irq cs_line;
79
+
80
+
80
+ uint32_t outdda;
81
+ SSIBus *spi;
81
+ uint32_t outddb;
82
+
82
+ uint32_t ctrl;
83
+ Fifo32 rx_fifo;
83
+ uint32_t intstat;
84
+ Fifo32 tx_fifo;
84
+ uint32_t swirq;
85
+
85
+};
86
+ int fifo_depth;
86
+
87
+ uint32_t frame_count;
87
+#define TYPE_BCM2835_MPHI "bcm2835-mphi"
88
+ bool enabled;
88
+
89
+
89
+#define BCM2835_MPHI(obj) \
90
+ uint32_t regs[R_SPI_MAX];
90
+ OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI)
91
+} MSSSpiState;
91
+
92
+
92
+#endif
93
+#endif /* HW_MSS_SPI_H */
93
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
94
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/hw/arm/bcm2835_peripherals.c
96
+++ b/hw/arm/bcm2835_peripherals.c
97
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
98
OBJECT(&s->sdhci.sdbus));
99
object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
100
OBJECT(&s->sdhost.sdbus));
101
+
102
+ /* Mphi */
103
+ sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
104
+ TYPE_BCM2835_MPHI);
105
}
106
107
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
108
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
109
110
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
111
112
+ /* Mphi */
113
+ object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
114
+ if (err) {
115
+ error_propagate(errp, err);
116
+ return;
117
+ }
118
+
119
+ memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,
120
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));
121
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
122
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
123
+ INTERRUPT_HOSTPORT));
124
+
125
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
126
create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
127
create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
128
diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c
95
new file mode 100644
129
new file mode 100644
96
index XXXXXXX..XXXXXXX
130
index XXXXXXX..XXXXXXX
97
--- /dev/null
131
--- /dev/null
98
+++ b/hw/ssi/mss-spi.c
132
+++ b/hw/misc/bcm2835_mphi.c
99
@@ -XXX,XX +XXX,XX @@
133
@@ -XXX,XX +XXX,XX @@
100
+/*
134
+/*
101
+ * Block model of SPI controller present in
135
+ * BCM2835 SOC MPHI emulation
102
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
136
+ *
103
+ *
137
+ * Very basic emulation, only providing the FIQ interrupt needed to
104
+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
138
+ * allow the dwc-otg USB host controller driver in the Raspbian kernel
105
+ *
139
+ * to function.
106
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
140
+ *
107
+ * of this software and associated documentation files (the "Software"), to deal
141
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
108
+ * in the Software without restriction, including without limitation the rights
142
+ *
109
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
143
+ * This program is free software; you can redistribute it and/or modify
110
+ * copies of the Software, and to permit persons to whom the Software is
144
+ * it under the terms of the GNU General Public License as published by
111
+ * furnished to do so, subject to the following conditions:
145
+ * the Free Software Foundation; either version 2 of the License, or
112
+ *
146
+ * (at your option) any later version.
113
+ * The above copyright notice and this permission notice shall be included in
147
+ *
114
+ * all copies or substantial portions of the Software.
148
+ * This program is distributed in the hope that it will be useful,
115
+ *
149
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
116
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
150
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
117
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
151
+ * GNU General Public License for more details.
118
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
119
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
120
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
121
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
122
+ * THE SOFTWARE.
123
+ */
152
+ */
124
+
153
+
125
+#include "qemu/osdep.h"
154
+#include "qemu/osdep.h"
126
+#include "hw/ssi/mss-spi.h"
155
+#include "qapi/error.h"
156
+#include "hw/misc/bcm2835_mphi.h"
157
+#include "migration/vmstate.h"
158
+#include "qemu/error-report.h"
127
+#include "qemu/log.h"
159
+#include "qemu/log.h"
128
+
160
+#include "qemu/main-loop.h"
129
+#ifndef MSS_SPI_ERR_DEBUG
161
+
130
+#define MSS_SPI_ERR_DEBUG 0
162
+static inline void mphi_raise_irq(BCM2835MphiState *s)
131
+#endif
163
+{
132
+
164
+ qemu_set_irq(s->irq, 1);
133
+#define DB_PRINT_L(lvl, fmt, args...) do { \
165
+}
134
+ if (MSS_SPI_ERR_DEBUG >= lvl) { \
166
+
135
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
167
+static inline void mphi_lower_irq(BCM2835MphiState *s)
136
+ } \
168
+{
137
+} while (0);
169
+ qemu_set_irq(s->irq, 0);
138
+
170
+}
139
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
171
+
140
+
172
+static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size)
141
+#define FIFO_CAPACITY 32
173
+{
142
+
174
+ BCM2835MphiState *s = ptr;
143
+#define R_SPI_CONTROL 0
175
+ uint32_t val = 0;
144
+#define R_SPI_DFSIZE 1
176
+
145
+#define R_SPI_STATUS 2
146
+#define R_SPI_INTCLR 3
147
+#define R_SPI_RX 4
148
+#define R_SPI_TX 5
149
+#define R_SPI_CLKGEN 6
150
+#define R_SPI_SS 7
151
+#define R_SPI_MIS 8
152
+#define R_SPI_RIS 9
153
+
154
+#define S_TXDONE (1 << 0)
155
+#define S_RXRDY (1 << 1)
156
+#define S_RXCHOVRF (1 << 2)
157
+#define S_RXFIFOFUL (1 << 4)
158
+#define S_RXFIFOFULNXT (1 << 5)
159
+#define S_RXFIFOEMP (1 << 6)
160
+#define S_RXFIFOEMPNXT (1 << 7)
161
+#define S_TXFIFOFUL (1 << 8)
162
+#define S_TXFIFOFULNXT (1 << 9)
163
+#define S_TXFIFOEMP (1 << 10)
164
+#define S_TXFIFOEMPNXT (1 << 11)
165
+#define S_FRAMESTART (1 << 12)
166
+#define S_SSEL (1 << 13)
167
+#define S_ACTIVE (1 << 14)
168
+
169
+#define C_ENABLE (1 << 0)
170
+#define C_MODE (1 << 1)
171
+#define C_INTRXDATA (1 << 4)
172
+#define C_INTTXDATA (1 << 5)
173
+#define C_INTRXOVRFLO (1 << 6)
174
+#define C_SPS (1 << 26)
175
+#define C_BIGFIFO (1 << 29)
176
+#define C_RESET (1 << 31)
177
+
178
+#define FRAMESZ_MASK 0x1F
179
+#define FMCOUNT_MASK 0x00FFFF00
180
+#define FMCOUNT_SHIFT 8
181
+
182
+static void txfifo_reset(MSSSpiState *s)
183
+{
184
+ fifo32_reset(&s->tx_fifo);
185
+
186
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
187
+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
188
+}
189
+
190
+static void rxfifo_reset(MSSSpiState *s)
191
+{
192
+ fifo32_reset(&s->rx_fifo);
193
+
194
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
195
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
196
+}
197
+
198
+static void set_fifodepth(MSSSpiState *s)
199
+{
200
+ unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
201
+
202
+ if (size <= 8) {
203
+ s->fifo_depth = 32;
204
+ } else if (size <= 16) {
205
+ s->fifo_depth = 16;
206
+ } else if (size <= 32) {
207
+ s->fifo_depth = 8;
208
+ } else {
209
+ s->fifo_depth = 4;
210
+ }
211
+}
212
+
213
+static void update_mis(MSSSpiState *s)
214
+{
215
+ uint32_t reg = s->regs[R_SPI_CONTROL];
216
+ uint32_t tmp;
217
+
218
+ /*
219
+ * form the Control register interrupt enable bits
220
+ * same as RIS, MIS and Interrupt clear registers for simplicity
221
+ */
222
+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
223
+ ((reg & C_INTTXDATA) >> 5);
224
+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
225
+}
226
+
227
+static void spi_update_irq(MSSSpiState *s)
228
+{
229
+ int irq;
230
+
231
+ update_mis(s);
232
+ irq = !!(s->regs[R_SPI_MIS]);
233
+
234
+ qemu_set_irq(s->irq, irq);
235
+}
236
+
237
+static void mss_spi_reset(DeviceState *d)
238
+{
239
+ MSSSpiState *s = MSS_SPI(d);
240
+
241
+ memset(s->regs, 0, sizeof s->regs);
242
+ s->regs[R_SPI_CONTROL] = 0x80000102;
243
+ s->regs[R_SPI_DFSIZE] = 0x4;
244
+ s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
245
+ s->regs[R_SPI_CLKGEN] = 0x7;
246
+ s->regs[R_SPI_RIS] = 0x0;
247
+
248
+ s->fifo_depth = 4;
249
+ s->frame_count = 1;
250
+ s->enabled = false;
251
+
252
+ rxfifo_reset(s);
253
+ txfifo_reset(s);
254
+}
255
+
256
+static uint64_t
257
+spi_read(void *opaque, hwaddr addr, unsigned int size)
258
+{
259
+ MSSSpiState *s = opaque;
260
+ uint32_t ret = 0;
261
+
262
+ addr >>= 2;
263
+ switch (addr) {
177
+ switch (addr) {
264
+ case R_SPI_RX:
178
+ case 0x28: /* outdda */
265
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
179
+ val = s->outdda;
266
+ s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
180
+ break;
267
+ ret = fifo32_pop(&s->rx_fifo);
181
+ case 0x2c: /* outddb */
268
+ if (fifo32_is_empty(&s->rx_fifo)) {
182
+ val = s->outddb;
269
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
183
+ break;
184
+ case 0x4c: /* ctrl */
185
+ val = s->ctrl;
186
+ val |= 1 << 17;
187
+ break;
188
+ case 0x50: /* intstat */
189
+ val = s->intstat;
190
+ break;
191
+ case 0x1f0: /* swirq_set */
192
+ val = s->swirq;
193
+ break;
194
+ case 0x1f4: /* swirq_clr */
195
+ val = s->swirq;
196
+ break;
197
+ default:
198
+ qemu_log_mask(LOG_UNIMP, "read from unknown register");
199
+ break;
200
+ }
201
+
202
+ return val;
203
+}
204
+
205
+static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size)
206
+{
207
+ BCM2835MphiState *s = ptr;
208
+ int do_irq = 0;
209
+
210
+ switch (addr) {
211
+ case 0x28: /* outdda */
212
+ s->outdda = val;
213
+ break;
214
+ case 0x2c: /* outddb */
215
+ s->outddb = val;
216
+ if (val & (1 << 29)) {
217
+ do_irq = 1;
270
+ }
218
+ }
271
+ break;
219
+ break;
272
+
220
+ case 0x4c: /* ctrl */
273
+ case R_SPI_MIS:
221
+ s->ctrl = val;
274
+ update_mis(s);
222
+ if (val & (1 << 16)) {
275
+ ret = s->regs[R_SPI_MIS];
223
+ do_irq = -1;
276
+ break;
224
+ }
277
+
225
+ break;
226
+ case 0x50: /* intstat */
227
+ s->intstat = val;
228
+ if (val & ((1 << 16) | (1 << 29))) {
229
+ do_irq = -1;
230
+ }
231
+ break;
232
+ case 0x1f0: /* swirq_set */
233
+ s->swirq |= val;
234
+ do_irq = 1;
235
+ break;
236
+ case 0x1f4: /* swirq_clr */
237
+ s->swirq &= ~val;
238
+ do_irq = -1;
239
+ break;
278
+ default:
240
+ default:
279
+ if (addr < ARRAY_SIZE(s->regs)) {
241
+ qemu_log_mask(LOG_UNIMP, "write to unknown register");
280
+ ret = s->regs[addr];
242
+ return;
281
+ } else {
243
+ }
282
+ qemu_log_mask(LOG_GUEST_ERROR,
244
+
283
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
245
+ if (do_irq > 0) {
284
+ addr * 4);
246
+ mphi_raise_irq(s);
285
+ return ret;
247
+ } else if (do_irq < 0) {
286
+ }
248
+ mphi_lower_irq(s);
287
+ break;
249
+ }
288
+ }
250
+}
289
+
251
+
290
+ DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
252
+static const MemoryRegionOps mphi_mmio_ops = {
291
+ spi_update_irq(s);
253
+ .read = mphi_reg_read,
292
+ return ret;
254
+ .write = mphi_reg_write,
293
+}
255
+ .impl.min_access_size = 4,
294
+
256
+ .impl.max_access_size = 4,
295
+static void assert_cs(MSSSpiState *s)
257
+ .endianness = DEVICE_LITTLE_ENDIAN,
296
+{
297
+ qemu_set_irq(s->cs_line, 0);
298
+}
299
+
300
+static void deassert_cs(MSSSpiState *s)
301
+{
302
+ qemu_set_irq(s->cs_line, 1);
303
+}
304
+
305
+static void spi_flush_txfifo(MSSSpiState *s)
306
+{
307
+ uint32_t tx;
308
+ uint32_t rx;
309
+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
310
+
311
+ /*
312
+ * Chip Select(CS) is automatically controlled by this controller.
313
+ * If SPS bit is set in Control register then CS is asserted
314
+ * until all the frames set in frame count of Control register are
315
+ * transferred. If SPS is not set then CS pulses between frames.
316
+ * Note that Slave Select register specifies which of the CS line
317
+ * has to be controlled automatically by controller. Bits SS[7:1] are for
318
+ * masters in FPGA fabric since we model only Microcontroller subsystem
319
+ * of Smartfusion2 we control only one CS(SS[0]) line.
320
+ */
321
+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
322
+ assert_cs(s);
323
+
324
+ s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
325
+
326
+ tx = fifo32_pop(&s->tx_fifo);
327
+ DB_PRINT("data tx:0x%" PRIx32, tx);
328
+ rx = ssi_transfer(s->spi, tx);
329
+ DB_PRINT("data rx:0x%" PRIx32, rx);
330
+
331
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
332
+ s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
333
+ s->regs[R_SPI_RIS] |= S_RXCHOVRF;
334
+ } else {
335
+ fifo32_push(&s->rx_fifo, rx);
336
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
337
+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
338
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
339
+ } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
340
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
341
+ }
342
+ }
343
+ s->frame_count--;
344
+ if (!sps) {
345
+ deassert_cs(s);
346
+ }
347
+ }
348
+
349
+ if (!s->frame_count) {
350
+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
351
+ FMCOUNT_SHIFT;
352
+ deassert_cs(s);
353
+ s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
354
+ s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
355
+ }
356
+}
357
+
358
+static void spi_write(void *opaque, hwaddr addr,
359
+ uint64_t val64, unsigned int size)
360
+{
361
+ MSSSpiState *s = opaque;
362
+ uint32_t value = val64;
363
+
364
+ DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
365
+ addr >>= 2;
366
+
367
+ switch (addr) {
368
+ case R_SPI_TX:
369
+ /* adding to already full FIFO */
370
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
371
+ break;
372
+ }
373
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
374
+ fifo32_push(&s->tx_fifo, value);
375
+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
376
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
377
+ } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
378
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
379
+ }
380
+ if (s->enabled) {
381
+ spi_flush_txfifo(s);
382
+ }
383
+ break;
384
+
385
+ case R_SPI_CONTROL:
386
+ s->regs[R_SPI_CONTROL] = value;
387
+ if (value & C_BIGFIFO) {
388
+ set_fifodepth(s);
389
+ } else {
390
+ s->fifo_depth = 4;
391
+ }
392
+ s->enabled = value & C_ENABLE;
393
+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
394
+ if (value & C_RESET) {
395
+ mss_spi_reset(DEVICE(s));
396
+ }
397
+ break;
398
+
399
+ case R_SPI_DFSIZE:
400
+ if (s->enabled) {
401
+ break;
402
+ }
403
+ s->regs[R_SPI_DFSIZE] = value;
404
+ break;
405
+
406
+ case R_SPI_INTCLR:
407
+ s->regs[R_SPI_INTCLR] = value;
408
+ if (value & S_TXDONE) {
409
+ s->regs[R_SPI_RIS] &= ~S_TXDONE;
410
+ }
411
+ if (value & S_RXRDY) {
412
+ s->regs[R_SPI_RIS] &= ~S_RXRDY;
413
+ }
414
+ if (value & S_RXCHOVRF) {
415
+ s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
416
+ }
417
+ break;
418
+
419
+ case R_SPI_MIS:
420
+ case R_SPI_STATUS:
421
+ case R_SPI_RIS:
422
+ qemu_log_mask(LOG_GUEST_ERROR,
423
+ "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
424
+ __func__, addr * 4);
425
+ break;
426
+
427
+ default:
428
+ if (addr < ARRAY_SIZE(s->regs)) {
429
+ s->regs[addr] = value;
430
+ } else {
431
+ qemu_log_mask(LOG_GUEST_ERROR,
432
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
433
+ addr * 4);
434
+ }
435
+ break;
436
+ }
437
+
438
+ spi_update_irq(s);
439
+}
440
+
441
+static const MemoryRegionOps spi_ops = {
442
+ .read = spi_read,
443
+ .write = spi_write,
444
+ .endianness = DEVICE_NATIVE_ENDIAN,
445
+ .valid = {
446
+ .min_access_size = 1,
447
+ .max_access_size = 4
448
+ }
449
+};
258
+};
450
+
259
+
451
+static void mss_spi_realize(DeviceState *dev, Error **errp)
260
+static void mphi_reset(DeviceState *dev)
452
+{
261
+{
453
+ MSSSpiState *s = MSS_SPI(dev);
262
+ BCM2835MphiState *s = BCM2835_MPHI(dev);
263
+
264
+ s->outdda = 0;
265
+ s->outddb = 0;
266
+ s->ctrl = 0;
267
+ s->intstat = 0;
268
+ s->swirq = 0;
269
+}
270
+
271
+static void mphi_realize(DeviceState *dev, Error **errp)
272
+{
454
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
273
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
455
+
274
+ BCM2835MphiState *s = BCM2835_MPHI(dev);
456
+ s->spi = ssi_create_bus(dev, "spi");
457
+
275
+
458
+ sysbus_init_irq(sbd, &s->irq);
276
+ sysbus_init_irq(sbd, &s->irq);
459
+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
277
+}
460
+ sysbus_init_irq(sbd, &s->cs_line);
278
+
461
+
279
+static void mphi_init(Object *obj)
462
+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
280
+{
463
+ TYPE_MSS_SPI, R_SPI_MAX * 4);
281
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
464
+ sysbus_init_mmio(sbd, &s->mmio);
282
+ BCM2835MphiState *s = BCM2835_MPHI(obj);
465
+
283
+
466
+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
284
+ memory_region_init_io(&s->iomem, obj, &mphi_mmio_ops, s, "mphi", MPHI_MMIO_SIZE);
467
+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
285
+ sysbus_init_mmio(sbd, &s->iomem);
468
+}
286
+}
469
+
287
+
470
+static const VMStateDescription vmstate_mss_spi = {
288
+const VMStateDescription vmstate_mphi_state = {
471
+ .name = TYPE_MSS_SPI,
289
+ .name = "mphi",
472
+ .version_id = 1,
290
+ .version_id = 1,
473
+ .minimum_version_id = 1,
291
+ .minimum_version_id = 1,
474
+ .fields = (VMStateField[]) {
292
+ .fields = (VMStateField[]) {
475
+ VMSTATE_FIFO32(tx_fifo, MSSSpiState),
293
+ VMSTATE_UINT32(outdda, BCM2835MphiState),
476
+ VMSTATE_FIFO32(rx_fifo, MSSSpiState),
294
+ VMSTATE_UINT32(outddb, BCM2835MphiState),
477
+ VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
295
+ VMSTATE_UINT32(ctrl, BCM2835MphiState),
296
+ VMSTATE_UINT32(intstat, BCM2835MphiState),
297
+ VMSTATE_UINT32(swirq, BCM2835MphiState),
478
+ VMSTATE_END_OF_LIST()
298
+ VMSTATE_END_OF_LIST()
479
+ }
299
+ }
480
+};
300
+};
481
+
301
+
482
+static void mss_spi_class_init(ObjectClass *klass, void *data)
302
+static void mphi_class_init(ObjectClass *klass, void *data)
483
+{
303
+{
484
+ DeviceClass *dc = DEVICE_CLASS(klass);
304
+ DeviceClass *dc = DEVICE_CLASS(klass);
485
+
305
+
486
+ dc->realize = mss_spi_realize;
306
+ dc->realize = mphi_realize;
487
+ dc->reset = mss_spi_reset;
307
+ dc->reset = mphi_reset;
488
+ dc->vmsd = &vmstate_mss_spi;
308
+ dc->vmsd = &vmstate_mphi_state;
489
+}
309
+}
490
+
310
+
491
+static const TypeInfo mss_spi_info = {
311
+static const TypeInfo bcm2835_mphi_type_info = {
492
+ .name = TYPE_MSS_SPI,
312
+ .name = TYPE_BCM2835_MPHI,
493
+ .parent = TYPE_SYS_BUS_DEVICE,
313
+ .parent = TYPE_SYS_BUS_DEVICE,
494
+ .instance_size = sizeof(MSSSpiState),
314
+ .instance_size = sizeof(BCM2835MphiState),
495
+ .class_init = mss_spi_class_init,
315
+ .instance_init = mphi_init,
316
+ .class_init = mphi_class_init,
496
+};
317
+};
497
+
318
+
498
+static void mss_spi_register_types(void)
319
+static void bcm2835_mphi_register_types(void)
499
+{
320
+{
500
+ type_register_static(&mss_spi_info);
321
+ type_register_static(&bcm2835_mphi_type_info);
501
+}
322
+}
502
+
323
+
503
+type_init(mss_spi_register_types)
324
+type_init(bcm2835_mphi_register_types)
325
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
326
index XXXXXXX..XXXXXXX 100644
327
--- a/hw/misc/Makefile.objs
328
+++ b/hw/misc/Makefile.objs
329
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_OMAP) += omap_l4.o
330
common-obj-$(CONFIG_OMAP) += omap_sdrc.o
331
common-obj-$(CONFIG_OMAP) += omap_tap.o
332
common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o
333
+common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o
334
common-obj-$(CONFIG_RASPI) += bcm2835_property.o
335
common-obj-$(CONFIG_RASPI) += bcm2835_rng.o
336
common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o
504
--
337
--
505
2.7.4
338
2.20.1
506
339
507
340
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Paul Zimmerman <pauldzim@gmail.com>
2
2
3
Emulated Emcraft's Smartfusion2 System On Module starter
3
Import the dwc-hsotg (dwc2) register definitions file from the
4
kit.
4
Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
5
mainline Linux kernel, the only changes being to the header, and
6
two instances of 'u32' changed to 'uint32_t' to allow it to
7
compile. Checkpatch throws a boatload of errors due to the tab
8
indentation, but I would rather import it as-is than reformat it.
5
9
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
10
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20200520235349.21215-3-pauldzim@gmail.com
8
Message-id: 20170920201737.25723-6-f4bug@amsat.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
[PMD: drop cpu_model to directly use cpu type]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
hw/arm/Makefile.objs | 2 +-
15
include/hw/usb/dwc2-regs.h | 899 +++++++++++++++++++++++++++++++++++++
13
hw/arm/msf2-som.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++
16
1 file changed, 899 insertions(+)
14
2 files changed, 106 insertions(+), 1 deletion(-)
17
create mode 100644 include/hw/usb/dwc2-regs.h
15
create mode 100644 hw/arm/msf2-som.c
16
18
17
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
19
diff --git a/include/hw/usb/dwc2-regs.h b/include/hw/usb/dwc2-regs.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/Makefile.objs
20
+++ b/hw/arm/Makefile.objs
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
22
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
23
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
24
obj-$(CONFIG_MPS2) += mps2.o
25
-obj-$(CONFIG_MSF2) += msf2-soc.o
26
+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
27
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
28
new file mode 100644
20
new file mode 100644
29
index XXXXXXX..XXXXXXX
21
index XXXXXXX..XXXXXXX
30
--- /dev/null
22
--- /dev/null
31
+++ b/hw/arm/msf2-som.c
23
+++ b/include/hw/usb/dwc2-regs.h
32
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
25
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
33
+/*
26
+/*
34
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
27
+ * Imported from the Linux kernel file drivers/usb/dwc2/hw.h, commit
28
+ * a89bae709b3492b478480a2c9734e7e9393b279c ("usb: dwc2: Move
29
+ * UTMI_PHY_DATA defines closer")
35
+ *
30
+ *
36
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
31
+ * hw.h - DesignWare HS OTG Controller hardware definitions
37
+ *
32
+ *
38
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
33
+ * Copyright 2004-2013 Synopsys, Inc.
39
+ * of this software and associated documentation files (the "Software"), to deal
40
+ * in the Software without restriction, including without limitation the rights
41
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
42
+ * copies of the Software, and to permit persons to whom the Software is
43
+ * furnished to do so, subject to the following conditions:
44
+ *
34
+ *
45
+ * The above copyright notice and this permission notice shall be included in
35
+ * Redistribution and use in source and binary forms, with or without
46
+ * all copies or substantial portions of the Software.
36
+ * modification, are permitted provided that the following conditions
37
+ * are met:
38
+ * 1. Redistributions of source code must retain the above copyright
39
+ * notice, this list of conditions, and the following disclaimer,
40
+ * without modification.
41
+ * 2. Redistributions in binary form must reproduce the above copyright
42
+ * notice, this list of conditions and the following disclaimer in the
43
+ * documentation and/or other materials provided with the distribution.
44
+ * 3. The names of the above-listed copyright holders may not be used
45
+ * to endorse or promote products derived from this software without
46
+ * specific prior written permission.
47
+ *
47
+ *
48
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
48
+ * ALTERNATIVELY, this software may be distributed under the terms of the
49
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
49
+ * GNU General Public License ("GPL") as published by the Free Software
50
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
50
+ * Foundation; either version 2 of the License, or (at your option) any
51
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
51
+ * later version.
52
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
52
+ *
53
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
53
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
54
+ * THE SOFTWARE.
54
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
55
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
56
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
57
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
58
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
59
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
60
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
61
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
62
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
63
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55
+ */
64
+ */
56
+
65
+
57
+#include "qemu/osdep.h"
66
+#ifndef __DWC2_HW_H__
58
+#include "qapi/error.h"
67
+#define __DWC2_HW_H__
59
+#include "qemu/error-report.h"
68
+
60
+#include "hw/boards.h"
69
+#define HSOTG_REG(x)    (x)
61
+#include "hw/arm/arm.h"
70
+
62
+#include "exec/address-spaces.h"
71
+#define GOTGCTL                HSOTG_REG(0x000)
63
+#include "qemu/cutils.h"
72
+#define GOTGCTL_CHIRPEN            BIT(27)
64
+#include "hw/arm/msf2-soc.h"
73
+#define GOTGCTL_MULT_VALID_BC_MASK    (0x1f << 22)
65
+#include "cpu.h"
74
+#define GOTGCTL_MULT_VALID_BC_SHIFT    22
66
+
75
+#define GOTGCTL_OTGVER            BIT(20)
67
+#define DDR_BASE_ADDRESS 0xA0000000
76
+#define GOTGCTL_BSESVLD            BIT(19)
68
+#define DDR_SIZE (64 * M_BYTE)
77
+#define GOTGCTL_ASESVLD            BIT(18)
69
+
78
+#define GOTGCTL_DBNC_SHORT        BIT(17)
70
+#define M2S010_ENVM_SIZE (256 * K_BYTE)
79
+#define GOTGCTL_CONID_B            BIT(16)
71
+#define M2S010_ESRAM_SIZE (64 * K_BYTE)
80
+#define GOTGCTL_DBNCE_FLTR_BYPASS    BIT(15)
72
+
81
+#define GOTGCTL_DEVHNPEN        BIT(11)
73
+static void emcraft_sf2_s2s010_init(MachineState *machine)
82
+#define GOTGCTL_HSTSETHNPEN        BIT(10)
74
+{
83
+#define GOTGCTL_HNPREQ            BIT(9)
75
+ DeviceState *dev;
84
+#define GOTGCTL_HSTNEGSCS        BIT(8)
76
+ DeviceState *spi_flash;
85
+#define GOTGCTL_SESREQ            BIT(1)
77
+ MSF2State *soc;
86
+#define GOTGCTL_SESREQSCS        BIT(0)
78
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
87
+
79
+ DriveInfo *dinfo = drive_get_next(IF_MTD);
88
+#define GOTGINT                HSOTG_REG(0x004)
80
+ qemu_irq cs_line;
89
+#define GOTGINT_DBNCE_DONE        BIT(19)
81
+ SSIBus *spi_bus;
90
+#define GOTGINT_A_DEV_TOUT_CHG        BIT(18)
82
+ MemoryRegion *sysmem = get_system_memory();
91
+#define GOTGINT_HST_NEG_DET        BIT(17)
83
+ MemoryRegion *ddr = g_new(MemoryRegion, 1);
92
+#define GOTGINT_HST_NEG_SUC_STS_CHNG    BIT(9)
84
+
93
+#define GOTGINT_SES_REQ_SUC_STS_CHNG    BIT(8)
85
+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
94
+#define GOTGINT_SES_END_DET        BIT(2)
86
+ error_report("This board can only be used with CPU %s",
95
+
87
+ mc->default_cpu_type);
96
+#define GAHBCFG                HSOTG_REG(0x008)
88
+ }
97
+#define GAHBCFG_AHB_SINGLE        BIT(23)
89
+
98
+#define GAHBCFG_NOTI_ALL_DMA_WRIT    BIT(22)
90
+ memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
99
+#define GAHBCFG_REM_MEM_SUPP        BIT(21)
91
+ &error_fatal);
100
+#define GAHBCFG_P_TXF_EMP_LVL        BIT(8)
92
+ memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
101
+#define GAHBCFG_NP_TXF_EMP_LVL        BIT(7)
93
+
102
+#define GAHBCFG_DMA_EN            BIT(5)
94
+ dev = qdev_create(NULL, TYPE_MSF2_SOC);
103
+#define GAHBCFG_HBSTLEN_MASK        (0xf << 1)
95
+ qdev_prop_set_string(dev, "part-name", "M2S010");
104
+#define GAHBCFG_HBSTLEN_SHIFT        1
96
+ qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
105
+#define GAHBCFG_HBSTLEN_SINGLE        0
97
+
106
+#define GAHBCFG_HBSTLEN_INCR        1
98
+ qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
107
+#define GAHBCFG_HBSTLEN_INCR4        3
99
+ qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
108
+#define GAHBCFG_HBSTLEN_INCR8        5
100
+
109
+#define GAHBCFG_HBSTLEN_INCR16        7
101
+ /*
110
+#define GAHBCFG_GLBL_INTR_EN        BIT(0)
102
+ * CPU clock and peripheral clocks(APB0, APB1)are configurable
111
+#define GAHBCFG_CTRL_MASK        (GAHBCFG_P_TXF_EMP_LVL | \
103
+ * in Libero. CPU clock is divided by APB0 and APB1 divisors for
112
+                     GAHBCFG_NP_TXF_EMP_LVL | \
104
+ * peripherals. Emcraft's SoM kit comes with these settings by default.
113
+                     GAHBCFG_DMA_EN | \
105
+ */
114
+                     GAHBCFG_GLBL_INTR_EN)
106
+ qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
115
+
107
+ qdev_prop_set_uint32(dev, "apb0div", 2);
116
+#define GUSBCFG                HSOTG_REG(0x00C)
108
+ qdev_prop_set_uint32(dev, "apb1div", 2);
117
+#define GUSBCFG_FORCEDEVMODE        BIT(30)
109
+
118
+#define GUSBCFG_FORCEHOSTMODE        BIT(29)
110
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
119
+#define GUSBCFG_TXENDDELAY        BIT(28)
111
+
120
+#define GUSBCFG_ICTRAFFICPULLREMOVE    BIT(27)
112
+ soc = MSF2_SOC(dev);
121
+#define GUSBCFG_ICUSBCAP        BIT(26)
113
+
122
+#define GUSBCFG_ULPI_INT_PROT_DIS    BIT(25)
114
+ /* Attach SPI flash to SPI0 controller */
123
+#define GUSBCFG_INDICATORPASSTHROUGH    BIT(24)
115
+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
124
+#define GUSBCFG_INDICATORCOMPLEMENT    BIT(23)
116
+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
125
+#define GUSBCFG_TERMSELDLPULSE        BIT(22)
117
+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
126
+#define GUSBCFG_ULPI_INT_VBUS_IND    BIT(21)
118
+ if (dinfo) {
127
+#define GUSBCFG_ULPI_EXT_VBUS_DRV    BIT(20)
119
+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
128
+#define GUSBCFG_ULPI_CLK_SUSP_M        BIT(19)
120
+ &error_fatal);
129
+#define GUSBCFG_ULPI_AUTO_RES        BIT(18)
121
+ }
130
+#define GUSBCFG_ULPI_FS_LS        BIT(17)
122
+ qdev_init_nofail(spi_flash);
131
+#define GUSBCFG_OTG_UTMI_FS_SEL        BIT(16)
123
+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
132
+#define GUSBCFG_PHY_LP_CLK_SEL        BIT(15)
124
+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
133
+#define GUSBCFG_USBTRDTIM_MASK        (0xf << 10)
125
+
134
+#define GUSBCFG_USBTRDTIM_SHIFT        10
126
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
135
+#define GUSBCFG_HNPCAP            BIT(9)
127
+ soc->envm_size);
136
+#define GUSBCFG_SRPCAP            BIT(8)
128
+}
137
+#define GUSBCFG_DDRSEL            BIT(7)
129
+
138
+#define GUSBCFG_PHYSEL            BIT(6)
130
+static void emcraft_sf2_machine_init(MachineClass *mc)
139
+#define GUSBCFG_FSINTF            BIT(5)
131
+{
140
+#define GUSBCFG_ULPI_UTMI_SEL        BIT(4)
132
+ mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
141
+#define GUSBCFG_PHYIF16            BIT(3)
133
+ mc->init = emcraft_sf2_s2s010_init;
142
+#define GUSBCFG_PHYIF8            (0 << 3)
134
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
143
+#define GUSBCFG_TOUTCAL_MASK        (0x7 << 0)
135
+}
144
+#define GUSBCFG_TOUTCAL_SHIFT        0
136
+
145
+#define GUSBCFG_TOUTCAL_LIMIT        0x7
137
+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
146
+#define GUSBCFG_TOUTCAL(_x)        ((_x) << 0)
147
+
148
+#define GRSTCTL                HSOTG_REG(0x010)
149
+#define GRSTCTL_AHBIDLE            BIT(31)
150
+#define GRSTCTL_DMAREQ            BIT(30)
151
+#define GRSTCTL_TXFNUM_MASK        (0x1f << 6)
152
+#define GRSTCTL_TXFNUM_SHIFT        6
153
+#define GRSTCTL_TXFNUM_LIMIT        0x1f
154
+#define GRSTCTL_TXFNUM(_x)        ((_x) << 6)
155
+#define GRSTCTL_TXFFLSH            BIT(5)
156
+#define GRSTCTL_RXFFLSH            BIT(4)
157
+#define GRSTCTL_IN_TKNQ_FLSH        BIT(3)
158
+#define GRSTCTL_FRMCNTRRST        BIT(2)
159
+#define GRSTCTL_HSFTRST            BIT(1)
160
+#define GRSTCTL_CSFTRST            BIT(0)
161
+
162
+#define GINTSTS                HSOTG_REG(0x014)
163
+#define GINTMSK                HSOTG_REG(0x018)
164
+#define GINTSTS_WKUPINT            BIT(31)
165
+#define GINTSTS_SESSREQINT        BIT(30)
166
+#define GINTSTS_DISCONNINT        BIT(29)
167
+#define GINTSTS_CONIDSTSCHNG        BIT(28)
168
+#define GINTSTS_LPMTRANRCVD        BIT(27)
169
+#define GINTSTS_PTXFEMP            BIT(26)
170
+#define GINTSTS_HCHINT            BIT(25)
171
+#define GINTSTS_PRTINT            BIT(24)
172
+#define GINTSTS_RESETDET        BIT(23)
173
+#define GINTSTS_FET_SUSP        BIT(22)
174
+#define GINTSTS_INCOMPL_IP        BIT(21)
175
+#define GINTSTS_INCOMPL_SOOUT        BIT(21)
176
+#define GINTSTS_INCOMPL_SOIN        BIT(20)
177
+#define GINTSTS_OEPINT            BIT(19)
178
+#define GINTSTS_IEPINT            BIT(18)
179
+#define GINTSTS_EPMIS            BIT(17)
180
+#define GINTSTS_RESTOREDONE        BIT(16)
181
+#define GINTSTS_EOPF            BIT(15)
182
+#define GINTSTS_ISOUTDROP        BIT(14)
183
+#define GINTSTS_ENUMDONE        BIT(13)
184
+#define GINTSTS_USBRST            BIT(12)
185
+#define GINTSTS_USBSUSP            BIT(11)
186
+#define GINTSTS_ERLYSUSP        BIT(10)
187
+#define GINTSTS_I2CINT            BIT(9)
188
+#define GINTSTS_ULPI_CK_INT        BIT(8)
189
+#define GINTSTS_GOUTNAKEFF        BIT(7)
190
+#define GINTSTS_GINNAKEFF        BIT(6)
191
+#define GINTSTS_NPTXFEMP        BIT(5)
192
+#define GINTSTS_RXFLVL            BIT(4)
193
+#define GINTSTS_SOF            BIT(3)
194
+#define GINTSTS_OTGINT            BIT(2)
195
+#define GINTSTS_MODEMIS            BIT(1)
196
+#define GINTSTS_CURMODE_HOST        BIT(0)
197
+
198
+#define GRXSTSR                HSOTG_REG(0x01C)
199
+#define GRXSTSP                HSOTG_REG(0x020)
200
+#define GRXSTS_FN_MASK            (0x7f << 25)
201
+#define GRXSTS_FN_SHIFT            25
202
+#define GRXSTS_PKTSTS_MASK        (0xf << 17)
203
+#define GRXSTS_PKTSTS_SHIFT        17
204
+#define GRXSTS_PKTSTS_GLOBALOUTNAK    1
205
+#define GRXSTS_PKTSTS_OUTRX        2
206
+#define GRXSTS_PKTSTS_HCHIN        2
207
+#define GRXSTS_PKTSTS_OUTDONE        3
208
+#define GRXSTS_PKTSTS_HCHIN_XFER_COMP    3
209
+#define GRXSTS_PKTSTS_SETUPDONE        4
210
+#define GRXSTS_PKTSTS_DATATOGGLEERR    5
211
+#define GRXSTS_PKTSTS_SETUPRX        6
212
+#define GRXSTS_PKTSTS_HCHHALTED        7
213
+#define GRXSTS_HCHNUM_MASK        (0xf << 0)
214
+#define GRXSTS_HCHNUM_SHIFT        0
215
+#define GRXSTS_DPID_MASK        (0x3 << 15)
216
+#define GRXSTS_DPID_SHIFT        15
217
+#define GRXSTS_BYTECNT_MASK        (0x7ff << 4)
218
+#define GRXSTS_BYTECNT_SHIFT        4
219
+#define GRXSTS_EPNUM_MASK        (0xf << 0)
220
+#define GRXSTS_EPNUM_SHIFT        0
221
+
222
+#define GRXFSIZ                HSOTG_REG(0x024)
223
+#define GRXFSIZ_DEPTH_MASK        (0xffff << 0)
224
+#define GRXFSIZ_DEPTH_SHIFT        0
225
+
226
+#define GNPTXFSIZ            HSOTG_REG(0x028)
227
+/* Use FIFOSIZE_* constants to access this register */
228
+
229
+#define GNPTXSTS            HSOTG_REG(0x02C)
230
+#define GNPTXSTS_NP_TXQ_TOP_MASK        (0x7f << 24)
231
+#define GNPTXSTS_NP_TXQ_TOP_SHIFT        24
232
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK        (0xff << 16)
233
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT        16
234
+#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)    (((_v) >> 16) & 0xff)
235
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK        (0xffff << 0)
236
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT        0
237
+#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)    (((_v) >> 0) & 0xffff)
238
+
239
+#define GI2CCTL                HSOTG_REG(0x0030)
240
+#define GI2CCTL_BSYDNE            BIT(31)
241
+#define GI2CCTL_RW            BIT(30)
242
+#define GI2CCTL_I2CDATSE0        BIT(28)
243
+#define GI2CCTL_I2CDEVADDR_MASK        (0x3 << 26)
244
+#define GI2CCTL_I2CDEVADDR_SHIFT    26
245
+#define GI2CCTL_I2CSUSPCTL        BIT(25)
246
+#define GI2CCTL_ACK            BIT(24)
247
+#define GI2CCTL_I2CEN            BIT(23)
248
+#define GI2CCTL_ADDR_MASK        (0x7f << 16)
249
+#define GI2CCTL_ADDR_SHIFT        16
250
+#define GI2CCTL_REGADDR_MASK        (0xff << 8)
251
+#define GI2CCTL_REGADDR_SHIFT        8
252
+#define GI2CCTL_RWDATA_MASK        (0xff << 0)
253
+#define GI2CCTL_RWDATA_SHIFT        0
254
+
255
+#define GPVNDCTL            HSOTG_REG(0x0034)
256
+#define GGPIO                HSOTG_REG(0x0038)
257
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN    BIT(16)
258
+
259
+#define GUID                HSOTG_REG(0x003c)
260
+#define GSNPSID                HSOTG_REG(0x0040)
261
+#define GHWCFG1                HSOTG_REG(0x0044)
262
+#define GSNPSID_ID_MASK            GENMASK(31, 16)
263
+
264
+#define GHWCFG2                HSOTG_REG(0x0048)
265
+#define GHWCFG2_OTG_ENABLE_IC_USB        BIT(31)
266
+#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK        (0x1f << 26)
267
+#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT        26
268
+#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK    (0x3 << 24)
269
+#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT    24
270
+#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK    (0x3 << 22)
271
+#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT    22
272
+#define GHWCFG2_MULTI_PROC_INT            BIT(20)
273
+#define GHWCFG2_DYNAMIC_FIFO            BIT(19)
274
+#define GHWCFG2_PERIO_EP_SUPPORTED        BIT(18)
275
+#define GHWCFG2_NUM_HOST_CHAN_MASK        (0xf << 14)
276
+#define GHWCFG2_NUM_HOST_CHAN_SHIFT        14
277
+#define GHWCFG2_NUM_DEV_EP_MASK            (0xf << 10)
278
+#define GHWCFG2_NUM_DEV_EP_SHIFT        10
279
+#define GHWCFG2_FS_PHY_TYPE_MASK        (0x3 << 8)
280
+#define GHWCFG2_FS_PHY_TYPE_SHIFT        8
281
+#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED    0
282
+#define GHWCFG2_FS_PHY_TYPE_DEDICATED        1
283
+#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI        2
284
+#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI        3
285
+#define GHWCFG2_HS_PHY_TYPE_MASK        (0x3 << 6)
286
+#define GHWCFG2_HS_PHY_TYPE_SHIFT        6
287
+#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED    0
288
+#define GHWCFG2_HS_PHY_TYPE_UTMI        1
289
+#define GHWCFG2_HS_PHY_TYPE_ULPI        2
290
+#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI        3
291
+#define GHWCFG2_POINT2POINT            BIT(5)
292
+#define GHWCFG2_ARCHITECTURE_MASK        (0x3 << 3)
293
+#define GHWCFG2_ARCHITECTURE_SHIFT        3
294
+#define GHWCFG2_SLAVE_ONLY_ARCH            0
295
+#define GHWCFG2_EXT_DMA_ARCH            1
296
+#define GHWCFG2_INT_DMA_ARCH            2
297
+#define GHWCFG2_OP_MODE_MASK            (0x7 << 0)
298
+#define GHWCFG2_OP_MODE_SHIFT            0
299
+#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE        0
300
+#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE    1
301
+#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE    2
302
+#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE    3
303
+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE    4
304
+#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST    5
305
+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST    6
306
+#define GHWCFG2_OP_MODE_UNDEFINED        7
307
+
308
+#define GHWCFG3                HSOTG_REG(0x004c)
309
+#define GHWCFG3_DFIFO_DEPTH_MASK        (0xffff << 16)
310
+#define GHWCFG3_DFIFO_DEPTH_SHIFT        16
311
+#define GHWCFG3_OTG_LPM_EN            BIT(15)
312
+#define GHWCFG3_BC_SUPPORT            BIT(14)
313
+#define GHWCFG3_OTG_ENABLE_HSIC            BIT(13)
314
+#define GHWCFG3_ADP_SUPP            BIT(12)
315
+#define GHWCFG3_SYNCH_RESET_TYPE        BIT(11)
316
+#define GHWCFG3_OPTIONAL_FEATURES        BIT(10)
317
+#define GHWCFG3_VENDOR_CTRL_IF            BIT(9)
318
+#define GHWCFG3_I2C                BIT(8)
319
+#define GHWCFG3_OTG_FUNC            BIT(7)
320
+#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK    (0x7 << 4)
321
+#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT    4
322
+#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK    (0xf << 0)
323
+#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT    0
324
+
325
+#define GHWCFG4                HSOTG_REG(0x0050)
326
+#define GHWCFG4_DESC_DMA_DYN            BIT(31)
327
+#define GHWCFG4_DESC_DMA            BIT(30)
328
+#define GHWCFG4_NUM_IN_EPS_MASK            (0xf << 26)
329
+#define GHWCFG4_NUM_IN_EPS_SHIFT        26
330
+#define GHWCFG4_DED_FIFO_EN            BIT(25)
331
+#define GHWCFG4_DED_FIFO_SHIFT        25
332
+#define GHWCFG4_SESSION_END_FILT_EN        BIT(24)
333
+#define GHWCFG4_B_VALID_FILT_EN            BIT(23)
334
+#define GHWCFG4_A_VALID_FILT_EN            BIT(22)
335
+#define GHWCFG4_VBUS_VALID_FILT_EN        BIT(21)
336
+#define GHWCFG4_IDDIG_FILT_EN            BIT(20)
337
+#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK    (0xf << 16)
338
+#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT    16
339
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK    (0x3 << 14)
340
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT    14
341
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8        0
342
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16        1
343
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16    2
344
+#define GHWCFG4_ACG_SUPPORTED            BIT(12)
345
+#define GHWCFG4_IPG_ISOC_SUPPORTED        BIT(11)
346
+#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10)
347
+#define GHWCFG4_XHIBER                BIT(7)
348
+#define GHWCFG4_HIBER                BIT(6)
349
+#define GHWCFG4_MIN_AHB_FREQ            BIT(5)
350
+#define GHWCFG4_POWER_OPTIMIZ            BIT(4)
351
+#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK    (0xf << 0)
352
+#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT    0
353
+
354
+#define GLPMCFG                HSOTG_REG(0x0054)
355
+#define GLPMCFG_INVSELHSIC        BIT(31)
356
+#define GLPMCFG_HSICCON            BIT(30)
357
+#define GLPMCFG_RSTRSLPSTS        BIT(29)
358
+#define GLPMCFG_ENBESL            BIT(28)
359
+#define GLPMCFG_LPM_RETRYCNT_STS_MASK    (0x7 << 25)
360
+#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT    25
361
+#define GLPMCFG_SNDLPM            BIT(24)
362
+#define GLPMCFG_RETRY_CNT_MASK        (0x7 << 21)
363
+#define GLPMCFG_RETRY_CNT_SHIFT        21
364
+#define GLPMCFG_LPM_REJECT_CTRL_CONTROL    BIT(21)
365
+#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC    BIT(22)
366
+#define GLPMCFG_LPM_CHNL_INDX_MASK    (0xf << 17)
367
+#define GLPMCFG_LPM_CHNL_INDX_SHIFT    17
368
+#define GLPMCFG_L1RESUMEOK        BIT(16)
369
+#define GLPMCFG_SLPSTS            BIT(15)
370
+#define GLPMCFG_COREL1RES_MASK        (0x3 << 13)
371
+#define GLPMCFG_COREL1RES_SHIFT        13
372
+#define GLPMCFG_HIRD_THRES_MASK        (0x1f << 8)
373
+#define GLPMCFG_HIRD_THRES_SHIFT    8
374
+#define GLPMCFG_HIRD_THRES_EN        (0x10 << 8)
375
+#define GLPMCFG_ENBLSLPM        BIT(7)
376
+#define GLPMCFG_BREMOTEWAKE        BIT(6)
377
+#define GLPMCFG_HIRD_MASK        (0xf << 2)
378
+#define GLPMCFG_HIRD_SHIFT        2
379
+#define GLPMCFG_APPL1RES        BIT(1)
380
+#define GLPMCFG_LPMCAP            BIT(0)
381
+
382
+#define GPWRDN                HSOTG_REG(0x0058)
383
+#define GPWRDN_MULT_VAL_ID_BC_MASK    (0x1f << 24)
384
+#define GPWRDN_MULT_VAL_ID_BC_SHIFT    24
385
+#define GPWRDN_ADP_INT            BIT(23)
386
+#define GPWRDN_BSESSVLD            BIT(22)
387
+#define GPWRDN_IDSTS            BIT(21)
388
+#define GPWRDN_LINESTATE_MASK        (0x3 << 19)
389
+#define GPWRDN_LINESTATE_SHIFT        19
390
+#define GPWRDN_STS_CHGINT_MSK        BIT(18)
391
+#define GPWRDN_STS_CHGINT        BIT(17)
392
+#define GPWRDN_SRP_DET_MSK        BIT(16)
393
+#define GPWRDN_SRP_DET            BIT(15)
394
+#define GPWRDN_CONNECT_DET_MSK        BIT(14)
395
+#define GPWRDN_CONNECT_DET        BIT(13)
396
+#define GPWRDN_DISCONN_DET_MSK        BIT(12)
397
+#define GPWRDN_DISCONN_DET        BIT(11)
398
+#define GPWRDN_RST_DET_MSK        BIT(10)
399
+#define GPWRDN_RST_DET            BIT(9)
400
+#define GPWRDN_LNSTSCHG_MSK        BIT(8)
401
+#define GPWRDN_LNSTSCHG            BIT(7)
402
+#define GPWRDN_DIS_VBUS            BIT(6)
403
+#define GPWRDN_PWRDNSWTCH        BIT(5)
404
+#define GPWRDN_PWRDNRSTN        BIT(4)
405
+#define GPWRDN_PWRDNCLMP        BIT(3)
406
+#define GPWRDN_RESTORE            BIT(2)
407
+#define GPWRDN_PMUACTV            BIT(1)
408
+#define GPWRDN_PMUINTSEL        BIT(0)
409
+
410
+#define GDFIFOCFG            HSOTG_REG(0x005c)
411
+#define GDFIFOCFG_EPINFOBASE_MASK    (0xffff << 16)
412
+#define GDFIFOCFG_EPINFOBASE_SHIFT    16
413
+#define GDFIFOCFG_GDFIFOCFG_MASK    (0xffff << 0)
414
+#define GDFIFOCFG_GDFIFOCFG_SHIFT    0
415
+
416
+#define ADPCTL                HSOTG_REG(0x0060)
417
+#define ADPCTL_AR_MASK            (0x3 << 27)
418
+#define ADPCTL_AR_SHIFT            27
419
+#define ADPCTL_ADP_TMOUT_INT_MSK    BIT(26)
420
+#define ADPCTL_ADP_SNS_INT_MSK        BIT(25)
421
+#define ADPCTL_ADP_PRB_INT_MSK        BIT(24)
422
+#define ADPCTL_ADP_TMOUT_INT        BIT(23)
423
+#define ADPCTL_ADP_SNS_INT        BIT(22)
424
+#define ADPCTL_ADP_PRB_INT        BIT(21)
425
+#define ADPCTL_ADPENA            BIT(20)
426
+#define ADPCTL_ADPRES            BIT(19)
427
+#define ADPCTL_ENASNS            BIT(18)
428
+#define ADPCTL_ENAPRB            BIT(17)
429
+#define ADPCTL_RTIM_MASK        (0x7ff << 6)
430
+#define ADPCTL_RTIM_SHIFT        6
431
+#define ADPCTL_PRB_PER_MASK        (0x3 << 4)
432
+#define ADPCTL_PRB_PER_SHIFT        4
433
+#define ADPCTL_PRB_DELTA_MASK        (0x3 << 2)
434
+#define ADPCTL_PRB_DELTA_SHIFT        2
435
+#define ADPCTL_PRB_DSCHRG_MASK        (0x3 << 0)
436
+#define ADPCTL_PRB_DSCHRG_SHIFT        0
437
+
438
+#define GREFCLK                 HSOTG_REG(0x0064)
439
+#define GREFCLK_REFCLKPER_MASK         (0x1ffff << 15)
440
+#define GREFCLK_REFCLKPER_SHIFT         15
441
+#define GREFCLK_REF_CLK_MODE         BIT(14)
442
+#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK     (0x3ff)
443
+#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0
444
+
445
+#define GINTMSK2            HSOTG_REG(0x0068)
446
+#define GINTMSK2_WKUP_ALERT_INT_MSK    BIT(0)
447
+
448
+#define GINTSTS2            HSOTG_REG(0x006c)
449
+#define GINTSTS2_WKUP_ALERT_INT        BIT(0)
450
+
451
+#define HPTXFSIZ            HSOTG_REG(0x100)
452
+/* Use FIFOSIZE_* constants to access this register */
453
+
454
+#define DPTXFSIZN(_a)            HSOTG_REG(0x104 + (((_a) - 1) * 4))
455
+/* Use FIFOSIZE_* constants to access this register */
456
+
457
+/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
458
+#define FIFOSIZE_DEPTH_MASK        (0xffff << 16)
459
+#define FIFOSIZE_DEPTH_SHIFT        16
460
+#define FIFOSIZE_STARTADDR_MASK        (0xffff << 0)
461
+#define FIFOSIZE_STARTADDR_SHIFT    0
462
+#define FIFOSIZE_DEPTH_GET(_x)        (((_x) >> 16) & 0xffff)
463
+
464
+/* Device mode registers */
465
+
466
+#define DCFG                HSOTG_REG(0x800)
467
+#define DCFG_DESCDMA_EN            BIT(23)
468
+#define DCFG_EPMISCNT_MASK        (0x1f << 18)
469
+#define DCFG_EPMISCNT_SHIFT        18
470
+#define DCFG_EPMISCNT_LIMIT        0x1f
471
+#define DCFG_EPMISCNT(_x)        ((_x) << 18)
472
+#define DCFG_IPG_ISOC_SUPPORDED        BIT(17)
473
+#define DCFG_PERFRINT_MASK        (0x3 << 11)
474
+#define DCFG_PERFRINT_SHIFT        11
475
+#define DCFG_PERFRINT_LIMIT        0x3
476
+#define DCFG_PERFRINT(_x)        ((_x) << 11)
477
+#define DCFG_DEVADDR_MASK        (0x7f << 4)
478
+#define DCFG_DEVADDR_SHIFT        4
479
+#define DCFG_DEVADDR_LIMIT        0x7f
480
+#define DCFG_DEVADDR(_x)        ((_x) << 4)
481
+#define DCFG_NZ_STS_OUT_HSHK        BIT(2)
482
+#define DCFG_DEVSPD_MASK        (0x3 << 0)
483
+#define DCFG_DEVSPD_SHIFT        0
484
+#define DCFG_DEVSPD_HS            0
485
+#define DCFG_DEVSPD_FS            1
486
+#define DCFG_DEVSPD_LS            2
487
+#define DCFG_DEVSPD_FS48        3
488
+
489
+#define DCTL                HSOTG_REG(0x804)
490
+#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
491
+#define DCTL_PWRONPRGDONE        BIT(11)
492
+#define DCTL_CGOUTNAK            BIT(10)
493
+#define DCTL_SGOUTNAK            BIT(9)
494
+#define DCTL_CGNPINNAK            BIT(8)
495
+#define DCTL_SGNPINNAK            BIT(7)
496
+#define DCTL_TSTCTL_MASK        (0x7 << 4)
497
+#define DCTL_TSTCTL_SHIFT        4
498
+#define DCTL_GOUTNAKSTS            BIT(3)
499
+#define DCTL_GNPINNAKSTS        BIT(2)
500
+#define DCTL_SFTDISCON            BIT(1)
501
+#define DCTL_RMTWKUPSIG            BIT(0)
502
+
503
+#define DSTS                HSOTG_REG(0x808)
504
+#define DSTS_SOFFN_MASK            (0x3fff << 8)
505
+#define DSTS_SOFFN_SHIFT        8
506
+#define DSTS_SOFFN_LIMIT        0x3fff
507
+#define DSTS_SOFFN(_x)            ((_x) << 8)
508
+#define DSTS_ERRATICERR            BIT(3)
509
+#define DSTS_ENUMSPD_MASK        (0x3 << 1)
510
+#define DSTS_ENUMSPD_SHIFT        1
511
+#define DSTS_ENUMSPD_HS            0
512
+#define DSTS_ENUMSPD_FS            1
513
+#define DSTS_ENUMSPD_LS            2
514
+#define DSTS_ENUMSPD_FS48        3
515
+#define DSTS_SUSPSTS            BIT(0)
516
+
517
+#define DIEPMSK                HSOTG_REG(0x810)
518
+#define DIEPMSK_NAKMSK            BIT(13)
519
+#define DIEPMSK_BNAININTRMSK        BIT(9)
520
+#define DIEPMSK_TXFIFOUNDRNMSK        BIT(8)
521
+#define DIEPMSK_TXFIFOEMPTY        BIT(7)
522
+#define DIEPMSK_INEPNAKEFFMSK        BIT(6)
523
+#define DIEPMSK_INTKNEPMISMSK        BIT(5)
524
+#define DIEPMSK_INTKNTXFEMPMSK        BIT(4)
525
+#define DIEPMSK_TIMEOUTMSK        BIT(3)
526
+#define DIEPMSK_AHBERRMSK        BIT(2)
527
+#define DIEPMSK_EPDISBLDMSK        BIT(1)
528
+#define DIEPMSK_XFERCOMPLMSK        BIT(0)
529
+
530
+#define DOEPMSK                HSOTG_REG(0x814)
531
+#define DOEPMSK_BNAMSK            BIT(9)
532
+#define DOEPMSK_BACK2BACKSETUP        BIT(6)
533
+#define DOEPMSK_STSPHSERCVDMSK        BIT(5)
534
+#define DOEPMSK_OUTTKNEPDISMSK        BIT(4)
535
+#define DOEPMSK_SETUPMSK        BIT(3)
536
+#define DOEPMSK_AHBERRMSK        BIT(2)
537
+#define DOEPMSK_EPDISBLDMSK        BIT(1)
538
+#define DOEPMSK_XFERCOMPLMSK        BIT(0)
539
+
540
+#define DAINT                HSOTG_REG(0x818)
541
+#define DAINTMSK            HSOTG_REG(0x81C)
542
+#define DAINT_OUTEP_SHIFT        16
543
+#define DAINT_OUTEP(_x)            (1 << ((_x) + 16))
544
+#define DAINT_INEP(_x)            (1 << (_x))
545
+
546
+#define DTKNQR1                HSOTG_REG(0x820)
547
+#define DTKNQR2                HSOTG_REG(0x824)
548
+#define DTKNQR3                HSOTG_REG(0x830)
549
+#define DTKNQR4                HSOTG_REG(0x834)
550
+#define DIEPEMPMSK            HSOTG_REG(0x834)
551
+
552
+#define DVBUSDIS            HSOTG_REG(0x828)
553
+#define DVBUSPULSE            HSOTG_REG(0x82C)
554
+
555
+#define DIEPCTL0            HSOTG_REG(0x900)
556
+#define DIEPCTL(_a)            HSOTG_REG(0x900 + ((_a) * 0x20))
557
+
558
+#define DOEPCTL0            HSOTG_REG(0xB00)
559
+#define DOEPCTL(_a)            HSOTG_REG(0xB00 + ((_a) * 0x20))
560
+
561
+/* EP0 specialness:
562
+ * bits[29..28] - reserved (no SetD0PID, SetD1PID)
563
+ * bits[25..22] - should always be zero, this isn't a periodic endpoint
564
+ * bits[10..0] - MPS setting different for EP0
565
+ */
566
+#define D0EPCTL_MPS_MASK        (0x3 << 0)
567
+#define D0EPCTL_MPS_SHIFT        0
568
+#define D0EPCTL_MPS_64            0
569
+#define D0EPCTL_MPS_32            1
570
+#define D0EPCTL_MPS_16            2
571
+#define D0EPCTL_MPS_8            3
572
+
573
+#define DXEPCTL_EPENA            BIT(31)
574
+#define DXEPCTL_EPDIS            BIT(30)
575
+#define DXEPCTL_SETD1PID        BIT(29)
576
+#define DXEPCTL_SETODDFR        BIT(29)
577
+#define DXEPCTL_SETD0PID        BIT(28)
578
+#define DXEPCTL_SETEVENFR        BIT(28)
579
+#define DXEPCTL_SNAK            BIT(27)
580
+#define DXEPCTL_CNAK            BIT(26)
581
+#define DXEPCTL_TXFNUM_MASK        (0xf << 22)
582
+#define DXEPCTL_TXFNUM_SHIFT        22
583
+#define DXEPCTL_TXFNUM_LIMIT        0xf
584
+#define DXEPCTL_TXFNUM(_x)        ((_x) << 22)
585
+#define DXEPCTL_STALL            BIT(21)
586
+#define DXEPCTL_SNP            BIT(20)
587
+#define DXEPCTL_EPTYPE_MASK        (0x3 << 18)
588
+#define DXEPCTL_EPTYPE_CONTROL        (0x0 << 18)
589
+#define DXEPCTL_EPTYPE_ISO        (0x1 << 18)
590
+#define DXEPCTL_EPTYPE_BULK        (0x2 << 18)
591
+#define DXEPCTL_EPTYPE_INTERRUPT    (0x3 << 18)
592
+
593
+#define DXEPCTL_NAKSTS            BIT(17)
594
+#define DXEPCTL_DPID            BIT(16)
595
+#define DXEPCTL_EOFRNUM            BIT(16)
596
+#define DXEPCTL_USBACTEP        BIT(15)
597
+#define DXEPCTL_NEXTEP_MASK        (0xf << 11)
598
+#define DXEPCTL_NEXTEP_SHIFT        11
599
+#define DXEPCTL_NEXTEP_LIMIT        0xf
600
+#define DXEPCTL_NEXTEP(_x)        ((_x) << 11)
601
+#define DXEPCTL_MPS_MASK        (0x7ff << 0)
602
+#define DXEPCTL_MPS_SHIFT        0
603
+#define DXEPCTL_MPS_LIMIT        0x7ff
604
+#define DXEPCTL_MPS(_x)            ((_x) << 0)
605
+
606
+#define DIEPINT(_a)            HSOTG_REG(0x908 + ((_a) * 0x20))
607
+#define DOEPINT(_a)            HSOTG_REG(0xB08 + ((_a) * 0x20))
608
+#define DXEPINT_SETUP_RCVD        BIT(15)
609
+#define DXEPINT_NYETINTRPT        BIT(14)
610
+#define DXEPINT_NAKINTRPT        BIT(13)
611
+#define DXEPINT_BBLEERRINTRPT        BIT(12)
612
+#define DXEPINT_PKTDRPSTS        BIT(11)
613
+#define DXEPINT_BNAINTR            BIT(9)
614
+#define DXEPINT_TXFIFOUNDRN        BIT(8)
615
+#define DXEPINT_OUTPKTERR        BIT(8)
616
+#define DXEPINT_TXFEMP            BIT(7)
617
+#define DXEPINT_INEPNAKEFF        BIT(6)
618
+#define DXEPINT_BACK2BACKSETUP        BIT(6)
619
+#define DXEPINT_INTKNEPMIS        BIT(5)
620
+#define DXEPINT_STSPHSERCVD        BIT(5)
621
+#define DXEPINT_INTKNTXFEMP        BIT(4)
622
+#define DXEPINT_OUTTKNEPDIS        BIT(4)
623
+#define DXEPINT_TIMEOUT            BIT(3)
624
+#define DXEPINT_SETUP            BIT(3)
625
+#define DXEPINT_AHBERR            BIT(2)
626
+#define DXEPINT_EPDISBLD        BIT(1)
627
+#define DXEPINT_XFERCOMPL        BIT(0)
628
+
629
+#define DIEPTSIZ0            HSOTG_REG(0x910)
630
+#define DIEPTSIZ0_PKTCNT_MASK        (0x3 << 19)
631
+#define DIEPTSIZ0_PKTCNT_SHIFT        19
632
+#define DIEPTSIZ0_PKTCNT_LIMIT        0x3
633
+#define DIEPTSIZ0_PKTCNT(_x)        ((_x) << 19)
634
+#define DIEPTSIZ0_XFERSIZE_MASK        (0x7f << 0)
635
+#define DIEPTSIZ0_XFERSIZE_SHIFT    0
636
+#define DIEPTSIZ0_XFERSIZE_LIMIT    0x7f
637
+#define DIEPTSIZ0_XFERSIZE(_x)        ((_x) << 0)
638
+
639
+#define DOEPTSIZ0            HSOTG_REG(0xB10)
640
+#define DOEPTSIZ0_SUPCNT_MASK        (0x3 << 29)
641
+#define DOEPTSIZ0_SUPCNT_SHIFT        29
642
+#define DOEPTSIZ0_SUPCNT_LIMIT        0x3
643
+#define DOEPTSIZ0_SUPCNT(_x)        ((_x) << 29)
644
+#define DOEPTSIZ0_PKTCNT        BIT(19)
645
+#define DOEPTSIZ0_XFERSIZE_MASK        (0x7f << 0)
646
+#define DOEPTSIZ0_XFERSIZE_SHIFT    0
647
+
648
+#define DIEPTSIZ(_a)            HSOTG_REG(0x910 + ((_a) * 0x20))
649
+#define DOEPTSIZ(_a)            HSOTG_REG(0xB10 + ((_a) * 0x20))
650
+#define DXEPTSIZ_MC_MASK        (0x3 << 29)
651
+#define DXEPTSIZ_MC_SHIFT        29
652
+#define DXEPTSIZ_MC_LIMIT        0x3
653
+#define DXEPTSIZ_MC(_x)            ((_x) << 29)
654
+#define DXEPTSIZ_PKTCNT_MASK        (0x3ff << 19)
655
+#define DXEPTSIZ_PKTCNT_SHIFT        19
656
+#define DXEPTSIZ_PKTCNT_LIMIT        0x3ff
657
+#define DXEPTSIZ_PKTCNT_GET(_v)        (((_v) >> 19) & 0x3ff)
658
+#define DXEPTSIZ_PKTCNT(_x)        ((_x) << 19)
659
+#define DXEPTSIZ_XFERSIZE_MASK        (0x7ffff << 0)
660
+#define DXEPTSIZ_XFERSIZE_SHIFT        0
661
+#define DXEPTSIZ_XFERSIZE_LIMIT        0x7ffff
662
+#define DXEPTSIZ_XFERSIZE_GET(_v)    (((_v) >> 0) & 0x7ffff)
663
+#define DXEPTSIZ_XFERSIZE(_x)        ((_x) << 0)
664
+
665
+#define DIEPDMA(_a)            HSOTG_REG(0x914 + ((_a) * 0x20))
666
+#define DOEPDMA(_a)            HSOTG_REG(0xB14 + ((_a) * 0x20))
667
+
668
+#define DTXFSTS(_a)            HSOTG_REG(0x918 + ((_a) * 0x20))
669
+
670
+#define PCGCTL                HSOTG_REG(0x0e00)
671
+#define PCGCTL_IF_DEV_MODE        BIT(31)
672
+#define PCGCTL_P2HD_PRT_SPD_MASK    (0x3 << 29)
673
+#define PCGCTL_P2HD_PRT_SPD_SHIFT    29
674
+#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK    (0x3 << 27)
675
+#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT    27
676
+#define PCGCTL_MAC_DEV_ADDR_MASK    (0x7f << 20)
677
+#define PCGCTL_MAC_DEV_ADDR_SHIFT    20
678
+#define PCGCTL_MAX_TERMSEL        BIT(19)
679
+#define PCGCTL_MAX_XCVRSELECT_MASK    (0x3 << 17)
680
+#define PCGCTL_MAX_XCVRSELECT_SHIFT    17
681
+#define PCGCTL_PORT_POWER        BIT(16)
682
+#define PCGCTL_PRT_CLK_SEL_MASK        (0x3 << 14)
683
+#define PCGCTL_PRT_CLK_SEL_SHIFT    14
684
+#define PCGCTL_ESS_REG_RESTORED        BIT(13)
685
+#define PCGCTL_EXTND_HIBER_SWITCH    BIT(12)
686
+#define PCGCTL_EXTND_HIBER_PWRCLMP    BIT(11)
687
+#define PCGCTL_ENBL_EXTND_HIBER        BIT(10)
688
+#define PCGCTL_RESTOREMODE        BIT(9)
689
+#define PCGCTL_RESETAFTSUSP        BIT(8)
690
+#define PCGCTL_DEEP_SLEEP        BIT(7)
691
+#define PCGCTL_PHY_IN_SLEEP        BIT(6)
692
+#define PCGCTL_ENBL_SLEEP_GATING    BIT(5)
693
+#define PCGCTL_RSTPDWNMODULE        BIT(3)
694
+#define PCGCTL_PWRCLMP            BIT(2)
695
+#define PCGCTL_GATEHCLK            BIT(1)
696
+#define PCGCTL_STOPPCLK            BIT(0)
697
+
698
+#define PCGCCTL1 HSOTG_REG(0xe04)
699
+#define PCGCCTL1_TIMER (0x3 << 1)
700
+#define PCGCCTL1_GATEEN BIT(0)
701
+
702
+#define EPFIFO(_a)            HSOTG_REG(0x1000 + ((_a) * 0x1000))
703
+
704
+/* Host Mode Registers */
705
+
706
+#define HCFG                HSOTG_REG(0x0400)
707
+#define HCFG_MODECHTIMEN        BIT(31)
708
+#define HCFG_PERSCHEDENA        BIT(26)
709
+#define HCFG_FRLISTEN_MASK        (0x3 << 24)
710
+#define HCFG_FRLISTEN_SHIFT        24
711
+#define HCFG_FRLISTEN_8                (0 << 24)
712
+#define FRLISTEN_8_SIZE                8
713
+#define HCFG_FRLISTEN_16            BIT(24)
714
+#define FRLISTEN_16_SIZE            16
715
+#define HCFG_FRLISTEN_32            (2 << 24)
716
+#define FRLISTEN_32_SIZE            32
717
+#define HCFG_FRLISTEN_64            (3 << 24)
718
+#define FRLISTEN_64_SIZE            64
719
+#define HCFG_DESCDMA            BIT(23)
720
+#define HCFG_RESVALID_MASK        (0xff << 8)
721
+#define HCFG_RESVALID_SHIFT        8
722
+#define HCFG_ENA32KHZ            BIT(7)
723
+#define HCFG_FSLSSUPP            BIT(2)
724
+#define HCFG_FSLSPCLKSEL_MASK        (0x3 << 0)
725
+#define HCFG_FSLSPCLKSEL_SHIFT        0
726
+#define HCFG_FSLSPCLKSEL_30_60_MHZ    0
727
+#define HCFG_FSLSPCLKSEL_48_MHZ        1
728
+#define HCFG_FSLSPCLKSEL_6_MHZ        2
729
+
730
+#define HFIR                HSOTG_REG(0x0404)
731
+#define HFIR_FRINT_MASK            (0xffff << 0)
732
+#define HFIR_FRINT_SHIFT        0
733
+#define HFIR_RLDCTRL            BIT(16)
734
+
735
+#define HFNUM                HSOTG_REG(0x0408)
736
+#define HFNUM_FRREM_MASK        (0xffff << 16)
737
+#define HFNUM_FRREM_SHIFT        16
738
+#define HFNUM_FRNUM_MASK        (0xffff << 0)
739
+#define HFNUM_FRNUM_SHIFT        0
740
+#define HFNUM_MAX_FRNUM            0x3fff
741
+
742
+#define HPTXSTS                HSOTG_REG(0x0410)
743
+#define TXSTS_QTOP_ODD            BIT(31)
744
+#define TXSTS_QTOP_CHNEP_MASK        (0xf << 27)
745
+#define TXSTS_QTOP_CHNEP_SHIFT        27
746
+#define TXSTS_QTOP_TOKEN_MASK        (0x3 << 25)
747
+#define TXSTS_QTOP_TOKEN_SHIFT        25
748
+#define TXSTS_QTOP_TERMINATE        BIT(24)
749
+#define TXSTS_QSPCAVAIL_MASK        (0xff << 16)
750
+#define TXSTS_QSPCAVAIL_SHIFT        16
751
+#define TXSTS_FSPCAVAIL_MASK        (0xffff << 0)
752
+#define TXSTS_FSPCAVAIL_SHIFT        0
753
+
754
+#define HAINT                HSOTG_REG(0x0414)
755
+#define HAINTMSK            HSOTG_REG(0x0418)
756
+#define HFLBADDR            HSOTG_REG(0x041c)
757
+
758
+#define HPRT0                HSOTG_REG(0x0440)
759
+#define HPRT0_SPD_MASK            (0x3 << 17)
760
+#define HPRT0_SPD_SHIFT            17
761
+#define HPRT0_SPD_HIGH_SPEED        0
762
+#define HPRT0_SPD_FULL_SPEED        1
763
+#define HPRT0_SPD_LOW_SPEED        2
764
+#define HPRT0_TSTCTL_MASK        (0xf << 13)
765
+#define HPRT0_TSTCTL_SHIFT        13
766
+#define HPRT0_PWR            BIT(12)
767
+#define HPRT0_LNSTS_MASK        (0x3 << 10)
768
+#define HPRT0_LNSTS_SHIFT        10
769
+#define HPRT0_RST            BIT(8)
770
+#define HPRT0_SUSP            BIT(7)
771
+#define HPRT0_RES            BIT(6)
772
+#define HPRT0_OVRCURRCHG        BIT(5)
773
+#define HPRT0_OVRCURRACT        BIT(4)
774
+#define HPRT0_ENACHG            BIT(3)
775
+#define HPRT0_ENA            BIT(2)
776
+#define HPRT0_CONNDET            BIT(1)
777
+#define HPRT0_CONNSTS            BIT(0)
778
+
779
+#define HCCHAR(_ch)            HSOTG_REG(0x0500 + 0x20 * (_ch))
780
+#define HCCHAR_CHENA            BIT(31)
781
+#define HCCHAR_CHDIS            BIT(30)
782
+#define HCCHAR_ODDFRM            BIT(29)
783
+#define HCCHAR_DEVADDR_MASK        (0x7f << 22)
784
+#define HCCHAR_DEVADDR_SHIFT        22
785
+#define HCCHAR_MULTICNT_MASK        (0x3 << 20)
786
+#define HCCHAR_MULTICNT_SHIFT        20
787
+#define HCCHAR_EPTYPE_MASK        (0x3 << 18)
788
+#define HCCHAR_EPTYPE_SHIFT        18
789
+#define HCCHAR_LSPDDEV            BIT(17)
790
+#define HCCHAR_EPDIR            BIT(15)
791
+#define HCCHAR_EPNUM_MASK        (0xf << 11)
792
+#define HCCHAR_EPNUM_SHIFT        11
793
+#define HCCHAR_MPS_MASK            (0x7ff << 0)
794
+#define HCCHAR_MPS_SHIFT        0
795
+
796
+#define HCSPLT(_ch)            HSOTG_REG(0x0504 + 0x20 * (_ch))
797
+#define HCSPLT_SPLTENA            BIT(31)
798
+#define HCSPLT_COMPSPLT            BIT(16)
799
+#define HCSPLT_XACTPOS_MASK        (0x3 << 14)
800
+#define HCSPLT_XACTPOS_SHIFT        14
801
+#define HCSPLT_XACTPOS_MID        0
802
+#define HCSPLT_XACTPOS_END        1
803
+#define HCSPLT_XACTPOS_BEGIN        2
804
+#define HCSPLT_XACTPOS_ALL        3
805
+#define HCSPLT_HUBADDR_MASK        (0x7f << 7)
806
+#define HCSPLT_HUBADDR_SHIFT        7
807
+#define HCSPLT_PRTADDR_MASK        (0x7f << 0)
808
+#define HCSPLT_PRTADDR_SHIFT        0
809
+
810
+#define HCINT(_ch)            HSOTG_REG(0x0508 + 0x20 * (_ch))
811
+#define HCINTMSK(_ch)            HSOTG_REG(0x050c + 0x20 * (_ch))
812
+#define HCINTMSK_RESERVED14_31        (0x3ffff << 14)
813
+#define HCINTMSK_FRM_LIST_ROLL        BIT(13)
814
+#define HCINTMSK_XCS_XACT        BIT(12)
815
+#define HCINTMSK_BNA            BIT(11)
816
+#define HCINTMSK_DATATGLERR        BIT(10)
817
+#define HCINTMSK_FRMOVRUN        BIT(9)
818
+#define HCINTMSK_BBLERR            BIT(8)
819
+#define HCINTMSK_XACTERR        BIT(7)
820
+#define HCINTMSK_NYET            BIT(6)
821
+#define HCINTMSK_ACK            BIT(5)
822
+#define HCINTMSK_NAK            BIT(4)
823
+#define HCINTMSK_STALL            BIT(3)
824
+#define HCINTMSK_AHBERR            BIT(2)
825
+#define HCINTMSK_CHHLTD            BIT(1)
826
+#define HCINTMSK_XFERCOMPL        BIT(0)
827
+
828
+#define HCTSIZ(_ch)            HSOTG_REG(0x0510 + 0x20 * (_ch))
829
+#define TSIZ_DOPNG            BIT(31)
830
+#define TSIZ_SC_MC_PID_MASK        (0x3 << 29)
831
+#define TSIZ_SC_MC_PID_SHIFT        29
832
+#define TSIZ_SC_MC_PID_DATA0        0
833
+#define TSIZ_SC_MC_PID_DATA2        1
834
+#define TSIZ_SC_MC_PID_DATA1        2
835
+#define TSIZ_SC_MC_PID_MDATA        3
836
+#define TSIZ_SC_MC_PID_SETUP        3
837
+#define TSIZ_PKTCNT_MASK        (0x3ff << 19)
838
+#define TSIZ_PKTCNT_SHIFT        19
839
+#define TSIZ_NTD_MASK            (0xff << 8)
840
+#define TSIZ_NTD_SHIFT            8
841
+#define TSIZ_SCHINFO_MASK        (0xff << 0)
842
+#define TSIZ_SCHINFO_SHIFT        0
843
+#define TSIZ_XFERSIZE_MASK        (0x7ffff << 0)
844
+#define TSIZ_XFERSIZE_SHIFT        0
845
+
846
+#define HCDMA(_ch)            HSOTG_REG(0x0514 + 0x20 * (_ch))
847
+
848
+#define HCDMAB(_ch)            HSOTG_REG(0x051c + 0x20 * (_ch))
849
+
850
+#define HCFIFO(_ch)            HSOTG_REG(0x1000 + 0x1000 * (_ch))
851
+
852
+/**
853
+ * struct dwc2_dma_desc - DMA descriptor structure,
854
+ * used for both host and gadget modes
855
+ *
856
+ * @status: DMA descriptor status quadlet
857
+ * @buf: DMA descriptor data buffer pointer
858
+ *
859
+ * DMA Descriptor structure contains two quadlets:
860
+ * Status quadlet and Data buffer pointer.
861
+ */
862
+struct dwc2_dma_desc {
863
+    uint32_t status;
864
+    uint32_t buf;
865
+} __packed;
866
+
867
+/* Host Mode DMA descriptor status quadlet */
868
+
869
+#define HOST_DMA_A            BIT(31)
870
+#define HOST_DMA_STS_MASK        (0x3 << 28)
871
+#define HOST_DMA_STS_SHIFT        28
872
+#define HOST_DMA_STS_PKTERR        BIT(28)
873
+#define HOST_DMA_EOL            BIT(26)
874
+#define HOST_DMA_IOC            BIT(25)
875
+#define HOST_DMA_SUP            BIT(24)
876
+#define HOST_DMA_ALT_QTD        BIT(23)
877
+#define HOST_DMA_QTD_OFFSET_MASK    (0x3f << 17)
878
+#define HOST_DMA_QTD_OFFSET_SHIFT    17
879
+#define HOST_DMA_ISOC_NBYTES_MASK    (0xfff << 0)
880
+#define HOST_DMA_ISOC_NBYTES_SHIFT    0
881
+#define HOST_DMA_NBYTES_MASK        (0x1ffff << 0)
882
+#define HOST_DMA_NBYTES_SHIFT        0
883
+#define HOST_DMA_NBYTES_LIMIT        131071
884
+
885
+/* Device Mode DMA descriptor status quadlet */
886
+
887
+#define DEV_DMA_BUFF_STS_MASK        (0x3 << 30)
888
+#define DEV_DMA_BUFF_STS_SHIFT        30
889
+#define DEV_DMA_BUFF_STS_HREADY        0
890
+#define DEV_DMA_BUFF_STS_DMABUSY    1
891
+#define DEV_DMA_BUFF_STS_DMADONE    2
892
+#define DEV_DMA_BUFF_STS_HBUSY        3
893
+#define DEV_DMA_STS_MASK        (0x3 << 28)
894
+#define DEV_DMA_STS_SHIFT        28
895
+#define DEV_DMA_STS_SUCC        0
896
+#define DEV_DMA_STS_BUFF_FLUSH        1
897
+#define DEV_DMA_STS_BUFF_ERR        3
898
+#define DEV_DMA_L            BIT(27)
899
+#define DEV_DMA_SHORT            BIT(26)
900
+#define DEV_DMA_IOC            BIT(25)
901
+#define DEV_DMA_SR            BIT(24)
902
+#define DEV_DMA_MTRF            BIT(23)
903
+#define DEV_DMA_ISOC_PID_MASK        (0x3 << 23)
904
+#define DEV_DMA_ISOC_PID_SHIFT        23
905
+#define DEV_DMA_ISOC_PID_DATA0        0
906
+#define DEV_DMA_ISOC_PID_DATA2        1
907
+#define DEV_DMA_ISOC_PID_DATA1        2
908
+#define DEV_DMA_ISOC_PID_MDATA        3
909
+#define DEV_DMA_ISOC_FRNUM_MASK        (0x7ff << 12)
910
+#define DEV_DMA_ISOC_FRNUM_SHIFT    12
911
+#define DEV_DMA_ISOC_TX_NBYTES_MASK    (0xfff << 0)
912
+#define DEV_DMA_ISOC_TX_NBYTES_LIMIT    0xfff
913
+#define DEV_DMA_ISOC_RX_NBYTES_MASK    (0x7ff << 0)
914
+#define DEV_DMA_ISOC_RX_NBYTES_LIMIT    0x7ff
915
+#define DEV_DMA_ISOC_NBYTES_SHIFT    0
916
+#define DEV_DMA_NBYTES_MASK        (0xffff << 0)
917
+#define DEV_DMA_NBYTES_SHIFT        0
918
+#define DEV_DMA_NBYTES_LIMIT        0xffff
919
+
920
+#define MAX_DMA_DESC_NUM_GENERIC    64
921
+#define MAX_DMA_DESC_NUM_HS_ISOC    256
922
+
923
+#endif /* __DWC2_HW_H__ */
138
--
924
--
139
2.7.4
925
2.20.1
140
926
141
927
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Paul Zimmerman <pauldzim@gmail.com>
2
2
3
Added Sytem register block of Smartfusion2.
3
Add the dwc-hsotg (dwc2) USB host controller state definitions.
4
This block has PLL registers which are accessed by guest.
4
Mostly based on hw/usb/hcd-ehci.h.
5
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20200520235349.21215-4-pauldzim@gmail.com
8
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20170920201737.25723-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
hw/misc/Makefile.objs | 1 +
11
hw/usb/hcd-dwc2.h | 190 ++++++++++++++++++++++++++++++++++++++++++++++
14
include/hw/misc/msf2-sysreg.h | 77 ++++++++++++++++++++
12
1 file changed, 190 insertions(+)
15
hw/misc/msf2-sysreg.c | 160 ++++++++++++++++++++++++++++++++++++++++++
13
create mode 100644 hw/usb/hcd-dwc2.h
16
hw/misc/trace-events | 5 ++
14
17
4 files changed, 243 insertions(+)
15
diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h
18
create mode 100644 include/hw/misc/msf2-sysreg.h
19
create mode 100644 hw/misc/msf2-sysreg.c
20
21
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/misc/Makefile.objs
24
+++ b/hw/misc/Makefile.objs
25
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
26
obj-$(CONFIG_AUX) += auxbus.o
27
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
28
obj-y += mmio_interface.o
29
+obj-$(CONFIG_MSF2) += msf2-sysreg.o
30
diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
31
new file mode 100644
16
new file mode 100644
32
index XXXXXXX..XXXXXXX
17
index XXXXXXX..XXXXXXX
33
--- /dev/null
18
--- /dev/null
34
+++ b/include/hw/misc/msf2-sysreg.h
19
+++ b/hw/usb/hcd-dwc2.h
35
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
36
+/*
21
+/*
37
+ * Microsemi SmartFusion2 SYSREG
22
+ * dwc-hsotg (dwc2) USB host controller state definitions
38
+ *
23
+ *
39
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
24
+ * Based on hw/usb/hcd-ehci.h
40
+ *
25
+ *
41
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
26
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
42
+ * of this software and associated documentation files (the "Software"), to deal
27
+ *
43
+ * in the Software without restriction, including without limitation the rights
28
+ * This program is free software; you can redistribute it and/or modify
44
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
29
+ * it under the terms of the GNU General Public License as published by
45
+ * copies of the Software, and to permit persons to whom the Software is
30
+ * the Free Software Foundation; either version 2 of the License, or
46
+ * furnished to do so, subject to the following conditions:
31
+ * (at your option) any later version.
47
+ *
32
+ *
48
+ * The above copyright notice and this permission notice shall be included in
33
+ * This program is distributed in the hope that it will be useful,
49
+ * all copies or substantial portions of the Software.
34
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
50
+ *
35
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
51
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
36
+ * GNU General Public License for more details.
52
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
53
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
54
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
55
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
56
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
57
+ * THE SOFTWARE.
58
+ */
37
+ */
59
+
38
+
60
+#ifndef HW_MSF2_SYSREG_H
39
+#ifndef HW_USB_DWC2_H
61
+#define HW_MSF2_SYSREG_H
40
+#define HW_USB_DWC2_H
62
+
41
+
42
+#include "qemu/timer.h"
43
+#include "hw/irq.h"
63
+#include "hw/sysbus.h"
44
+#include "hw/sysbus.h"
64
+
45
+#include "hw/usb.h"
65
+enum {
46
+#include "sysemu/dma.h"
66
+ ESRAM_CR = 0x00 / 4,
47
+
67
+ ESRAM_MAX_LAT,
48
+#define DWC2_MMIO_SIZE 0x11000
68
+ DDR_CR,
49
+
69
+ ENVM_CR,
50
+#define DWC2_NB_CHAN 8 /* Number of host channels */
70
+ ENVM_REMAP_BASE_CR,
51
+#define DWC2_MAX_XFER_SIZE 65536 /* Max transfer size expected in HCTSIZ */
71
+ ENVM_REMAP_FAB_CR,
52
+
72
+ CC_CR,
53
+typedef struct DWC2Packet DWC2Packet;
73
+ CC_REGION_CR,
54
+typedef struct DWC2State DWC2State;
74
+ CC_LOCK_BASE_ADDR_CR,
55
+typedef struct DWC2Class DWC2Class;
75
+ CC_FLUSH_INDX_CR,
56
+
76
+ DDRB_BUF_TIMER_CR,
57
+enum async_state {
77
+ DDRB_NB_ADDR_CR,
58
+ DWC2_ASYNC_NONE = 0,
78
+ DDRB_NB_SIZE_CR,
59
+ DWC2_ASYNC_INITIALIZED,
79
+ DDRB_CR,
60
+ DWC2_ASYNC_INFLIGHT,
80
+
61
+ DWC2_ASYNC_FINISHED,
81
+ SOFT_RESET_CR = 0x48 / 4,
62
+};
82
+ M3_CR,
63
+
83
+
64
+struct DWC2Packet {
84
+ GPIO_SYSRESET_SEL_CR = 0x58 / 4,
65
+ USBPacket packet;
85
+
66
+ uint32_t devadr;
86
+ MDDR_CR = 0x60 / 4,
67
+ uint32_t epnum;
87
+
68
+ uint32_t epdir;
88
+ MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
69
+ uint32_t mps;
89
+ MSSDDR_PLL_STATUS_HIGH_CR,
70
+ uint32_t pid;
90
+ MSSDDR_FACC1_CR,
71
+ uint32_t index;
91
+ MSSDDR_FACC2_CR,
72
+ uint32_t pcnt;
92
+
73
+ uint32_t len;
93
+ MSSDDR_PLL_STATUS = 0x150 / 4,
74
+ int32_t async;
94
+};
75
+ bool small;
95
+
76
+ bool needs_service;
96
+#define MSF2_SYSREG_MMIO_SIZE 0x300
77
+};
97
+
78
+
98
+#define TYPE_MSF2_SYSREG "msf2-sysreg"
79
+struct DWC2State {
99
+#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
80
+ /*< private >*/
100
+
101
+typedef struct MSF2SysregState {
102
+ SysBusDevice parent_obj;
81
+ SysBusDevice parent_obj;
103
+
82
+
104
+ MemoryRegion iomem;
83
+ /*< public >*/
105
+
84
+ USBBus bus;
106
+ uint8_t apb0div;
85
+ qemu_irq irq;
107
+ uint8_t apb1div;
86
+ MemoryRegion *dma_mr;
108
+
87
+ AddressSpace dma_as;
109
+ uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
88
+ MemoryRegion container;
110
+} MSF2SysregState;
89
+ MemoryRegion hsotg;
111
+
90
+ MemoryRegion fifos;
112
+#endif /* HW_MSF2_SYSREG_H */
91
+
113
diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
92
+ union {
114
new file mode 100644
93
+#define DWC2_GLBREG_SIZE 0x70
115
index XXXXXXX..XXXXXXX
94
+ uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)];
116
--- /dev/null
95
+ struct {
117
+++ b/hw/misc/msf2-sysreg.c
96
+ uint32_t gotgctl; /* 00 */
118
@@ -XXX,XX +XXX,XX @@
97
+ uint32_t gotgint; /* 04 */
119
+/*
98
+ uint32_t gahbcfg; /* 08 */
120
+ * System Register block model of Microsemi SmartFusion2.
99
+ uint32_t gusbcfg; /* 0c */
121
+ *
100
+ uint32_t grstctl; /* 10 */
122
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
101
+ uint32_t gintsts; /* 14 */
123
+ *
102
+ uint32_t gintmsk; /* 18 */
124
+ * This program is free software; you can redistribute it and/or
103
+ uint32_t grxstsr; /* 1c */
125
+ * modify it under the terms of the GNU General Public License
104
+ uint32_t grxstsp; /* 20 */
126
+ * as published by the Free Software Foundation; either version
105
+ uint32_t grxfsiz; /* 24 */
127
+ * 2 of the License, or (at your option) any later version.
106
+ uint32_t gnptxfsiz; /* 28 */
128
+ *
107
+ uint32_t gnptxsts; /* 2c */
129
+ * You should have received a copy of the GNU General Public License along
108
+ uint32_t gi2cctl; /* 30 */
130
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
109
+ uint32_t gpvndctl; /* 34 */
131
+ */
110
+ uint32_t ggpio; /* 38 */
132
+
111
+ uint32_t guid; /* 3c */
133
+#include "qemu/osdep.h"
112
+ uint32_t gsnpsid; /* 40 */
134
+#include "qapi/error.h"
113
+ uint32_t ghwcfg1; /* 44 */
135
+#include "qemu/log.h"
114
+ uint32_t ghwcfg2; /* 48 */
136
+#include "hw/misc/msf2-sysreg.h"
115
+ uint32_t ghwcfg3; /* 4c */
137
+#include "qemu/error-report.h"
116
+ uint32_t ghwcfg4; /* 50 */
138
+#include "trace.h"
117
+ uint32_t glpmcfg; /* 54 */
139
+
118
+ uint32_t gpwrdn; /* 58 */
140
+static inline int msf2_divbits(uint32_t div)
119
+ uint32_t gdfifocfg; /* 5c */
141
+{
120
+ uint32_t gadpctl; /* 60 */
142
+ int r = ctz32(div);
121
+ uint32_t grefclk; /* 64 */
143
+
122
+ uint32_t gintmsk2; /* 68 */
144
+ return (div < 8) ? r : r + 1;
123
+ uint32_t gintsts2; /* 6c */
145
+}
124
+ };
146
+
125
+ };
147
+static void msf2_sysreg_reset(DeviceState *d)
126
+
148
+{
127
+ union {
149
+ MSF2SysregState *s = MSF2_SYSREG(d);
128
+#define DWC2_FSZREG_SIZE 0x04
150
+
129
+ uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)];
151
+ s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
130
+ struct {
152
+ s->regs[MSSDDR_PLL_STATUS] = 0x3;
131
+ uint32_t hptxfsiz; /* 100 */
153
+ s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
132
+ };
154
+ msf2_divbits(s->apb1div) << 2;
133
+ };
155
+}
134
+
156
+
135
+ union {
157
+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
136
+#define DWC2_HREG0_SIZE 0x44
158
+ unsigned size)
137
+ uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)];
159
+{
138
+ struct {
160
+ MSF2SysregState *s = opaque;
139
+ uint32_t hcfg; /* 400 */
161
+ uint32_t ret = 0;
140
+ uint32_t hfir; /* 404 */
162
+
141
+ uint32_t hfnum; /* 408 */
163
+ offset >>= 2;
142
+ uint32_t rsvd0; /* 40c */
164
+ if (offset < ARRAY_SIZE(s->regs)) {
143
+ uint32_t hptxsts; /* 410 */
165
+ ret = s->regs[offset];
144
+ uint32_t haint; /* 414 */
166
+ trace_msf2_sysreg_read(offset << 2, ret);
145
+ uint32_t haintmsk; /* 418 */
167
+ } else {
146
+ uint32_t hflbaddr; /* 41c */
168
+ qemu_log_mask(LOG_GUEST_ERROR,
147
+ uint32_t rsvd1[8]; /* 420-43c */
169
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
148
+ uint32_t hprt0; /* 440 */
170
+ offset << 2);
149
+ };
171
+ }
150
+ };
172
+
151
+
173
+ return ret;
152
+#define DWC2_HREG1_SIZE (0x20 * DWC2_NB_CHAN)
174
+}
153
+ uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)];
175
+
154
+
176
+static void msf2_sysreg_write(void *opaque, hwaddr offset,
155
+#define hcchar(_ch) hreg1[((_ch) << 3) + 0] /* 500, 520, ... */
177
+ uint64_t val, unsigned size)
156
+#define hcsplt(_ch) hreg1[((_ch) << 3) + 1] /* 504, 524, ... */
178
+{
157
+#define hcint(_ch) hreg1[((_ch) << 3) + 2] /* 508, 528, ... */
179
+ MSF2SysregState *s = opaque;
158
+#define hcintmsk(_ch) hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */
180
+ uint32_t newval = val;
159
+#define hctsiz(_ch) hreg1[((_ch) << 3) + 4] /* 510, 530, ... */
181
+
160
+#define hcdma(_ch) hreg1[((_ch) << 3) + 5] /* 514, 534, ... */
182
+ offset >>= 2;
161
+#define hcdmab(_ch) hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */
183
+
162
+
184
+ switch (offset) {
163
+ union {
185
+ case MSSDDR_PLL_STATUS:
164
+#define DWC2_PCGREG_SIZE 0x08
186
+ trace_msf2_sysreg_write_pll_status();
165
+ uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)];
187
+ break;
166
+ struct {
188
+
167
+ uint32_t pcgctl; /* e00 */
189
+ case ESRAM_CR:
168
+ uint32_t pcgcctl1; /* e04 */
190
+ case DDR_CR:
169
+ };
191
+ case ENVM_REMAP_BASE_CR:
170
+ };
192
+ if (newval != s->regs[offset]) {
171
+
193
+ qemu_log_mask(LOG_UNIMP,
172
+ /* TODO - implement FIFO registers for slave mode */
194
+ TYPE_MSF2_SYSREG": remapping not supported\n");
173
+#define DWC2_HFIFO_SIZE (0x1000 * DWC2_NB_CHAN)
195
+ }
174
+
196
+ break;
175
+ /*
197
+
176
+ * Internal state
198
+ default:
177
+ */
199
+ if (offset < ARRAY_SIZE(s->regs)) {
178
+ QEMUTimer *eof_timer;
200
+ trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);
179
+ QEMUTimer *frame_timer;
201
+ s->regs[offset] = newval;
180
+ QEMUBH *async_bh;
202
+ } else {
181
+ int64_t sof_time;
203
+ qemu_log_mask(LOG_GUEST_ERROR,
182
+ int64_t usb_frame_time;
204
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
183
+ int64_t usb_bit_time;
205
+ offset << 2);
184
+ uint32_t usb_version;
206
+ }
185
+ uint16_t frame_number;
207
+ break;
186
+ uint16_t fi;
208
+ }
187
+ uint16_t next_chan;
209
+}
188
+ bool working;
210
+
189
+ USBPort uport;
211
+static const MemoryRegionOps sysreg_ops = {
190
+ DWC2Packet packet[DWC2_NB_CHAN]; /* one packet per chan */
212
+ .read = msf2_sysreg_read,
191
+ uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */
213
+ .write = msf2_sysreg_write,
192
+};
214
+ .endianness = DEVICE_NATIVE_ENDIAN,
193
+
215
+};
194
+struct DWC2Class {
216
+
195
+ /*< private >*/
217
+static void msf2_sysreg_init(Object *obj)
196
+ SysBusDeviceClass parent_class;
218
+{
197
+ ResettablePhases parent_phases;
219
+ MSF2SysregState *s = MSF2_SYSREG(obj);
198
+
220
+
199
+ /*< public >*/
221
+ memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
200
+};
222
+ MSF2_SYSREG_MMIO_SIZE);
201
+
223
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
202
+#define TYPE_DWC2_USB "dwc2-usb"
224
+}
203
+#define DWC2_USB(obj) \
225
+
204
+ OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
226
+static const VMStateDescription vmstate_msf2_sysreg = {
205
+#define DWC2_CLASS(klass) \
227
+ .name = TYPE_MSF2_SYSREG,
206
+ OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
228
+ .version_id = 1,
207
+#define DWC2_GET_CLASS(obj) \
229
+ .minimum_version_id = 1,
208
+ OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
230
+ .fields = (VMStateField[]) {
209
+
231
+ VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),
210
+#endif
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
+static Property msf2_sysreg_properties[] = {
237
+ /* default divisors in Libero GUI */
238
+ DEFINE_PROP_UINT8("apb0divisor", MSF2SysregState, apb0div, 2),
239
+ DEFINE_PROP_UINT8("apb1divisor", MSF2SysregState, apb1div, 2),
240
+ DEFINE_PROP_END_OF_LIST(),
241
+};
242
+
243
+static void msf2_sysreg_realize(DeviceState *dev, Error **errp)
244
+{
245
+ MSF2SysregState *s = MSF2_SYSREG(dev);
246
+
247
+ if ((s->apb0div > 32 || !is_power_of_2(s->apb0div))
248
+ || (s->apb1div > 32 || !is_power_of_2(s->apb1div))) {
249
+ error_setg(errp, "Invalid apb divisor value");
250
+ error_append_hint(errp, "apb divisor must be a power of 2"
251
+ " and maximum value is 32\n");
252
+ }
253
+}
254
+
255
+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
256
+{
257
+ DeviceClass *dc = DEVICE_CLASS(klass);
258
+
259
+ dc->vmsd = &vmstate_msf2_sysreg;
260
+ dc->reset = msf2_sysreg_reset;
261
+ dc->props = msf2_sysreg_properties;
262
+ dc->realize = msf2_sysreg_realize;
263
+}
264
+
265
+static const TypeInfo msf2_sysreg_info = {
266
+ .name = TYPE_MSF2_SYSREG,
267
+ .parent = TYPE_SYS_BUS_DEVICE,
268
+ .class_init = msf2_sysreg_class_init,
269
+ .instance_size = sizeof(MSF2SysregState),
270
+ .instance_init = msf2_sysreg_init,
271
+};
272
+
273
+static void msf2_sysreg_register_types(void)
274
+{
275
+ type_register_static(&msf2_sysreg_info);
276
+}
277
+
278
+type_init(msf2_sysreg_register_types)
279
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
280
index XXXXXXX..XXXXXXX 100644
281
--- a/hw/misc/trace-events
282
+++ b/hw/misc/trace-events
283
@@ -XXX,XX +XXX,XX @@ mps2_scc_reset(void) "MPS2 SCC: reset"
284
mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) "MPS2 SCC LEDs: %c%c%c%c%c%c%c%c"
285
mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
286
mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
287
+
288
+# hw/misc/msf2-sysreg.c
289
+msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
290
+msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
291
+msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
292
--
211
--
293
2.7.4
212
2.20.1
294
213
295
214
diff view generated by jsdifflib
1
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
1
From: Paul Zimmerman <pauldzim@gmail.com>
2
2
3
Modelled System Timer in Microsemi's Smartfusion2 Soc.
3
Add the dwc-hsotg (dwc2) USB host controller emulation code.
4
Timer has two 32bit down counters and two interrupts.
4
Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.
5
5
6
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
6
Note that to use this with the dwc-otg driver in the Raspbian
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on
8
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
the kernel command line.
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
10
Message-id: 20170920201737.25723-2-f4bug@amsat.org
10
Emulation of slave mode and of descriptor-DMA mode has not been
11
implemented yet. These modes are seldom used.
12
13
I have used some on-line sources of information while developing
14
this emulation, including:
15
16
http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
17
which has a pretty complete description of the controller starting
18
on page 370.
19
20
https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
21
which has a description of the controller registers starting on
22
page 130.
23
24
Thanks to Felippe Mathieu-Daude for providing a cleaner method
25
of implementing the memory regions for the controller registers.
26
27
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
28
Message-id: 20200520235349.21215-5-pauldzim@gmail.com
29
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
31
---
13
hw/timer/Makefile.objs | 1 +
32
hw/usb/hcd-dwc2.c | 1417 ++++++++++++++++++++++++++++++++++++++++++
14
include/hw/timer/mss-timer.h | 64 ++++++++++
33
hw/usb/Kconfig | 5 +
15
hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++
34
hw/usb/Makefile.objs | 1 +
16
3 files changed, 354 insertions(+)
35
hw/usb/trace-events | 50 ++
17
create mode 100644 include/hw/timer/mss-timer.h
36
4 files changed, 1473 insertions(+)
18
create mode 100644 hw/timer/mss-timer.c
37
create mode 100644 hw/usb/hcd-dwc2.c
19
38
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
39
diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
23
+++ b/hw/timer/Makefile.objs
24
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
25
26
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
27
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
28
+common-obj-$(CONFIG_MSF2) += mss-timer.o
29
diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
30
new file mode 100644
40
new file mode 100644
31
index XXXXXXX..XXXXXXX
41
index XXXXXXX..XXXXXXX
32
--- /dev/null
42
--- /dev/null
33
+++ b/include/hw/timer/mss-timer.h
43
+++ b/hw/usb/hcd-dwc2.c
34
@@ -XXX,XX +XXX,XX @@
44
@@ -XXX,XX +XXX,XX @@
35
+/*
45
+/*
36
+ * Microsemi SmartFusion2 Timer.
46
+ * dwc-hsotg (dwc2) USB host controller emulation
37
+ *
47
+ *
38
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
48
+ * Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c
39
+ *
49
+ *
40
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
50
+ * Note that to use this emulation with the dwc-otg driver in the
41
+ * of this software and associated documentation files (the "Software"), to deal
51
+ * Raspbian kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0"
42
+ * in the Software without restriction, including without limitation the rights
52
+ * on the kernel command line.
43
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
44
+ * copies of the Software, and to permit persons to whom the Software is
45
+ * furnished to do so, subject to the following conditions:
46
+ *
53
+ *
47
+ * The above copyright notice and this permission notice shall be included in
54
+ * Some useful documentation used to develop this emulation can be
48
+ * all copies or substantial portions of the Software.
55
+ * found online (as of April 2020) at:
49
+ *
56
+ *
50
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
57
+ * http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
51
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
58
+ * which has a pretty complete description of the controller starting
52
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
59
+ * on page 370.
53
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
60
+ *
54
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
61
+ * https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
55
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
62
+ * which has a description of the controller registers starting on
56
+ * THE SOFTWARE.
63
+ * page 130.
64
+ *
65
+ * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
66
+ *
67
+ * This program is free software; you can redistribute it and/or modify
68
+ * it under the terms of the GNU General Public License as published by
69
+ * the Free Software Foundation; either version 2 of the License, or
70
+ * (at your option) any later version.
71
+ *
72
+ * This program is distributed in the hope that it will be useful,
73
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
74
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
75
+ * GNU General Public License for more details.
57
+ */
76
+ */
58
+
77
+
59
+#ifndef HW_MSS_TIMER_H
60
+#define HW_MSS_TIMER_H
61
+
62
+#include "hw/sysbus.h"
63
+#include "hw/ptimer.h"
64
+
65
+#define TYPE_MSS_TIMER "mss-timer"
66
+#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \
67
+ (obj), TYPE_MSS_TIMER)
68
+
69
+/*
70
+ * There are two 32-bit down counting timers.
71
+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer
72
+ * that operates either in Periodic mode or in One-shot mode.
73
+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
74
+ * In 64-bit mode, writing to the 32-bit registers has no effect.
75
+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers
76
+ * has no effect. Only two 32-bit timers are supported currently.
77
+ */
78
+#define NUM_TIMERS 2
79
+
80
+#define R_TIM1_MAX 6
81
+
82
+struct Msf2Timer {
83
+ QEMUBH *bh;
84
+ ptimer_state *ptimer;
85
+
86
+ uint32_t regs[R_TIM1_MAX];
87
+ qemu_irq irq;
88
+};
89
+
90
+typedef struct MSSTimerState {
91
+ SysBusDevice parent_obj;
92
+
93
+ MemoryRegion mmio;
94
+ uint32_t freq_hz;
95
+ struct Msf2Timer timers[NUM_TIMERS];
96
+} MSSTimerState;
97
+
98
+#endif /* HW_MSS_TIMER_H */
99
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
100
new file mode 100644
101
index XXXXXXX..XXXXXXX
102
--- /dev/null
103
+++ b/hw/timer/mss-timer.c
104
@@ -XXX,XX +XXX,XX @@
105
+/*
106
+ * Block model of System timer present in
107
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
108
+ *
109
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
110
+ *
111
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
112
+ * of this software and associated documentation files (the "Software"), to deal
113
+ * in the Software without restriction, including without limitation the rights
114
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
115
+ * copies of the Software, and to permit persons to whom the Software is
116
+ * furnished to do so, subject to the following conditions:
117
+ *
118
+ * The above copyright notice and this permission notice shall be included in
119
+ * all copies or substantial portions of the Software.
120
+ *
121
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
122
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
123
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
124
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
125
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
126
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
127
+ * THE SOFTWARE.
128
+ */
129
+
130
+#include "qemu/osdep.h"
78
+#include "qemu/osdep.h"
79
+#include "qemu/units.h"
80
+#include "qapi/error.h"
81
+#include "hw/usb/dwc2-regs.h"
82
+#include "hw/usb/hcd-dwc2.h"
83
+#include "migration/vmstate.h"
84
+#include "trace.h"
85
+#include "qemu/log.h"
86
+#include "qemu/error-report.h"
131
+#include "qemu/main-loop.h"
87
+#include "qemu/main-loop.h"
132
+#include "qemu/log.h"
88
+#include "hw/qdev-properties.h"
133
+#include "hw/timer/mss-timer.h"
89
+
134
+
90
+#define USB_HZ_FS 12000000
135
+#ifndef MSS_TIMER_ERR_DEBUG
91
+#define USB_HZ_HS 96000000
136
+#define MSS_TIMER_ERR_DEBUG 0
92
+#define USB_FRMINTVL 12000
137
+#endif
93
+
138
+
94
+/* nifty macros from Arnon's EHCI version */
139
+#define DB_PRINT_L(lvl, fmt, args...) do { \
95
+#define get_field(data, field) \
140
+ if (MSS_TIMER_ERR_DEBUG >= lvl) { \
96
+ (((data) & field##_MASK) >> field##_SHIFT)
141
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
97
+
142
+ } \
98
+#define set_field(data, newval, field) do { \
143
+} while (0);
99
+ uint32_t val = *(data); \
144
+
100
+ val &= ~field##_MASK; \
145
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
101
+ val |= ((newval) << field##_SHIFT) & field##_MASK; \
146
+
102
+ *(data) = val; \
147
+#define R_TIM_VAL 0
103
+} while (0)
148
+#define R_TIM_LOADVAL 1
104
+
149
+#define R_TIM_BGLOADVAL 2
105
+#define get_bit(data, bitmask) \
150
+#define R_TIM_CTRL 3
106
+ (!!((data) & (bitmask)))
151
+#define R_TIM_RIS 4
107
+
152
+#define R_TIM_MIS 5
108
+/* update irq line */
153
+
109
+static inline void dwc2_update_irq(DWC2State *s)
154
+#define TIMER_CTRL_ENBL (1 << 0)
110
+{
155
+#define TIMER_CTRL_ONESHOT (1 << 1)
111
+ static int oldlevel;
156
+#define TIMER_CTRL_INTR (1 << 2)
112
+ int level = 0;
157
+#define TIMER_RIS_ACK (1 << 0)
113
+
158
+#define TIMER_RST_CLR (1 << 6)
114
+ if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) {
159
+#define TIMER_MODE (1 << 0)
115
+ level = 1;
160
+
116
+ }
161
+static void timer_update_irq(struct Msf2Timer *st)
117
+ if (level != oldlevel) {
162
+{
118
+ oldlevel = level;
163
+ bool isr, ier;
119
+ trace_usb_dwc2_update_irq(level);
164
+
120
+ qemu_set_irq(s->irq, level);
165
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
121
+ }
166
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
122
+}
167
+ qemu_set_irq(st->irq, (ier && isr));
123
+
168
+}
124
+/* flag interrupt condition */
169
+
125
+static inline void dwc2_raise_global_irq(DWC2State *s, uint32_t intr)
170
+static void timer_update(struct Msf2Timer *st)
126
+{
171
+{
127
+ if (!(s->gintsts & intr)) {
172
+ uint64_t count;
128
+ s->gintsts |= intr;
173
+
129
+ trace_usb_dwc2_raise_global_irq(intr);
174
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
130
+ dwc2_update_irq(s);
175
+ ptimer_stop(st->ptimer);
131
+ }
132
+}
133
+
134
+static inline void dwc2_lower_global_irq(DWC2State *s, uint32_t intr)
135
+{
136
+ if (s->gintsts & intr) {
137
+ s->gintsts &= ~intr;
138
+ trace_usb_dwc2_lower_global_irq(intr);
139
+ dwc2_update_irq(s);
140
+ }
141
+}
142
+
143
+static inline void dwc2_raise_host_irq(DWC2State *s, uint32_t host_intr)
144
+{
145
+ if (!(s->haint & host_intr)) {
146
+ s->haint |= host_intr;
147
+ s->haint &= 0xffff;
148
+ trace_usb_dwc2_raise_host_irq(host_intr);
149
+ if (s->haint & s->haintmsk) {
150
+ dwc2_raise_global_irq(s, GINTSTS_HCHINT);
151
+ }
152
+ }
153
+}
154
+
155
+static inline void dwc2_lower_host_irq(DWC2State *s, uint32_t host_intr)
156
+{
157
+ if (s->haint & host_intr) {
158
+ s->haint &= ~host_intr;
159
+ trace_usb_dwc2_lower_host_irq(host_intr);
160
+ if (!(s->haint & s->haintmsk)) {
161
+ dwc2_lower_global_irq(s, GINTSTS_HCHINT);
162
+ }
163
+ }
164
+}
165
+
166
+static inline void dwc2_update_hc_irq(DWC2State *s, int index)
167
+{
168
+ uint32_t host_intr = 1 << (index >> 3);
169
+
170
+ if (s->hreg1[index + 2] & s->hreg1[index + 3]) {
171
+ dwc2_raise_host_irq(s, host_intr);
172
+ } else {
173
+ dwc2_lower_host_irq(s, host_intr);
174
+ }
175
+}
176
+
177
+/* set a timer for EOF */
178
+static void dwc2_eof_timer(DWC2State *s)
179
+{
180
+ timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time);
181
+}
182
+
183
+/* Set a timer for EOF and generate SOF event */
184
+static void dwc2_sof(DWC2State *s)
185
+{
186
+ s->sof_time += s->usb_frame_time;
187
+ trace_usb_dwc2_sof(s->sof_time);
188
+ dwc2_eof_timer(s);
189
+ dwc2_raise_global_irq(s, GINTSTS_SOF);
190
+}
191
+
192
+/* Do frame processing on frame boundary */
193
+static void dwc2_frame_boundary(void *opaque)
194
+{
195
+ DWC2State *s = opaque;
196
+ int64_t now;
197
+ uint16_t frcnt;
198
+
199
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
200
+
201
+ /* Frame boundary, so do EOF stuff here */
202
+
203
+ /* Increment frame number */
204
+ frcnt = (uint16_t)((now - s->sof_time) / s->fi);
205
+ s->frame_number = (s->frame_number + frcnt) & 0xffff;
206
+ s->hfnum = s->frame_number & HFNUM_MAX_FRNUM;
207
+
208
+ /* Do SOF stuff here */
209
+ dwc2_sof(s);
210
+}
211
+
212
+/* Start sending SOF tokens on the USB bus */
213
+static void dwc2_bus_start(DWC2State *s)
214
+{
215
+ trace_usb_dwc2_bus_start();
216
+ s->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
217
+ dwc2_eof_timer(s);
218
+}
219
+
220
+/* Stop sending SOF tokens on the USB bus */
221
+static void dwc2_bus_stop(DWC2State *s)
222
+{
223
+ trace_usb_dwc2_bus_stop();
224
+ timer_del(s->eof_timer);
225
+}
226
+
227
+static USBDevice *dwc2_find_device(DWC2State *s, uint8_t addr)
228
+{
229
+ USBDevice *dev;
230
+
231
+ trace_usb_dwc2_find_device(addr);
232
+
233
+ if (!(s->hprt0 & HPRT0_ENA)) {
234
+ trace_usb_dwc2_port_disabled(0);
235
+ } else {
236
+ dev = usb_find_device(&s->uport, addr);
237
+ if (dev != NULL) {
238
+ trace_usb_dwc2_device_found(0);
239
+ return dev;
240
+ }
241
+ }
242
+
243
+ trace_usb_dwc2_device_not_found();
244
+ return NULL;
245
+}
246
+
247
+static const char *pstatus[] = {
248
+ "USB_RET_SUCCESS", "USB_RET_NODEV", "USB_RET_NAK", "USB_RET_STALL",
249
+ "USB_RET_BABBLE", "USB_RET_IOERROR", "USB_RET_ASYNC",
250
+ "USB_RET_ADD_TO_QUEUE", "USB_RET_REMOVE_FROM_QUEUE"
251
+};
252
+
253
+static uint32_t pintr[] = {
254
+ HCINTMSK_XFERCOMPL, HCINTMSK_XACTERR, HCINTMSK_NAK, HCINTMSK_STALL,
255
+ HCINTMSK_BBLERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR,
256
+ HCINTMSK_XACTERR
257
+};
258
+
259
+static const char *types[] = {
260
+ "Ctrl", "Isoc", "Bulk", "Intr"
261
+};
262
+
263
+static const char *dirs[] = {
264
+ "Out", "In"
265
+};
266
+
267
+static void dwc2_handle_packet(DWC2State *s, uint32_t devadr, USBDevice *dev,
268
+ USBEndpoint *ep, uint32_t index, bool send)
269
+{
270
+ DWC2Packet *p;
271
+ uint32_t hcchar = s->hreg1[index];
272
+ uint32_t hctsiz = s->hreg1[index + 4];
273
+ uint32_t hcdma = s->hreg1[index + 5];
274
+ uint32_t chan, epnum, epdir, eptype, mps, pid, pcnt, len, tlen, intr = 0;
275
+ uint32_t tpcnt, stsidx, actual = 0;
276
+ bool do_intr = false, done = false;
277
+
278
+ epnum = get_field(hcchar, HCCHAR_EPNUM);
279
+ epdir = get_bit(hcchar, HCCHAR_EPDIR);
280
+ eptype = get_field(hcchar, HCCHAR_EPTYPE);
281
+ mps = get_field(hcchar, HCCHAR_MPS);
282
+ pid = get_field(hctsiz, TSIZ_SC_MC_PID);
283
+ pcnt = get_field(hctsiz, TSIZ_PKTCNT);
284
+ len = get_field(hctsiz, TSIZ_XFERSIZE);
285
+ assert(len <= DWC2_MAX_XFER_SIZE);
286
+ chan = index >> 3;
287
+ p = &s->packet[chan];
288
+
289
+ trace_usb_dwc2_handle_packet(chan, dev, &p->packet, epnum, types[eptype],
290
+ dirs[epdir], mps, len, pcnt);
291
+
292
+ if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
293
+ pid = USB_TOKEN_SETUP;
294
+ } else {
295
+ pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
296
+ }
297
+
298
+ if (send) {
299
+ tlen = len;
300
+ if (p->small) {
301
+ if (tlen > mps) {
302
+ tlen = mps;
303
+ }
304
+ }
305
+
306
+ if (pid != USB_TOKEN_IN) {
307
+ trace_usb_dwc2_memory_read(hcdma, tlen);
308
+ if (dma_memory_read(&s->dma_as, hcdma,
309
+ s->usb_buf[chan], tlen) != MEMTX_OK) {
310
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_read failed\n",
311
+ __func__);
312
+ }
313
+ }
314
+
315
+ usb_packet_init(&p->packet);
316
+ usb_packet_setup(&p->packet, pid, ep, 0, hcdma,
317
+ pid != USB_TOKEN_IN, true);
318
+ usb_packet_addbuf(&p->packet, s->usb_buf[chan], tlen);
319
+ p->async = DWC2_ASYNC_NONE;
320
+ usb_handle_packet(dev, &p->packet);
321
+ } else {
322
+ tlen = p->len;
323
+ }
324
+
325
+ stsidx = -p->packet.status;
326
+ assert(stsidx < sizeof(pstatus) / sizeof(*pstatus));
327
+ actual = p->packet.actual_length;
328
+ trace_usb_dwc2_packet_status(pstatus[stsidx], actual);
329
+
330
+babble:
331
+ if (p->packet.status != USB_RET_SUCCESS &&
332
+ p->packet.status != USB_RET_NAK &&
333
+ p->packet.status != USB_RET_STALL &&
334
+ p->packet.status != USB_RET_ASYNC) {
335
+ trace_usb_dwc2_packet_error(pstatus[stsidx]);
336
+ }
337
+
338
+ if (p->packet.status == USB_RET_ASYNC) {
339
+ trace_usb_dwc2_async_packet(&p->packet, chan, dev, epnum,
340
+ dirs[epdir], tlen);
341
+ usb_device_flush_ep_queue(dev, ep);
342
+ assert(p->async != DWC2_ASYNC_INFLIGHT);
343
+ p->devadr = devadr;
344
+ p->epnum = epnum;
345
+ p->epdir = epdir;
346
+ p->mps = mps;
347
+ p->pid = pid;
348
+ p->index = index;
349
+ p->pcnt = pcnt;
350
+ p->len = tlen;
351
+ p->async = DWC2_ASYNC_INFLIGHT;
352
+ p->needs_service = false;
176
+ return;
353
+ return;
177
+ }
354
+ }
178
+
355
+
179
+ count = st->regs[R_TIM_LOADVAL];
356
+ if (p->packet.status == USB_RET_SUCCESS) {
180
+ ptimer_set_limit(st->ptimer, count, 1);
357
+ if (actual > tlen) {
181
+ ptimer_run(st->ptimer, 1);
358
+ p->packet.status = USB_RET_BABBLE;
182
+}
359
+ goto babble;
183
+
360
+ }
184
+static uint64_t
361
+
185
+timer_read(void *opaque, hwaddr offset, unsigned int size)
362
+ if (pid == USB_TOKEN_IN) {
186
+{
363
+ trace_usb_dwc2_memory_write(hcdma, actual);
187
+ MSSTimerState *t = opaque;
364
+ if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan],
188
+ hwaddr addr;
365
+ actual) != MEMTX_OK) {
189
+ struct Msf2Timer *st;
366
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_write failed\n",
190
+ uint32_t ret = 0;
367
+ __func__);
191
+ int timer = 0;
368
+ }
192
+ int isr;
369
+ }
193
+ int ier;
370
+
194
+
371
+ tpcnt = actual / mps;
195
+ addr = offset >> 2;
372
+ if (actual % mps) {
373
+ tpcnt++;
374
+ if (pid == USB_TOKEN_IN) {
375
+ done = true;
376
+ }
377
+ }
378
+
379
+ pcnt -= tpcnt < pcnt ? tpcnt : pcnt;
380
+ set_field(&hctsiz, pcnt, TSIZ_PKTCNT);
381
+ len -= actual < len ? actual : len;
382
+ set_field(&hctsiz, len, TSIZ_XFERSIZE);
383
+ s->hreg1[index + 4] = hctsiz;
384
+ hcdma += actual;
385
+ s->hreg1[index + 5] = hcdma;
386
+
387
+ if (!pcnt || len == 0 || actual == 0) {
388
+ done = true;
389
+ }
390
+ } else {
391
+ intr |= pintr[stsidx];
392
+ if (p->packet.status == USB_RET_NAK &&
393
+ (eptype == USB_ENDPOINT_XFER_CONTROL ||
394
+ eptype == USB_ENDPOINT_XFER_BULK)) {
395
+ /*
396
+ * for ctrl/bulk, automatically retry on NAK,
397
+ * but send the interrupt anyway
398
+ */
399
+ intr &= ~HCINTMSK_RESERVED14_31;
400
+ s->hreg1[index + 2] |= intr;
401
+ do_intr = true;
402
+ } else {
403
+ intr |= HCINTMSK_CHHLTD;
404
+ done = true;
405
+ }
406
+ }
407
+
408
+ usb_packet_cleanup(&p->packet);
409
+
410
+ if (done) {
411
+ hcchar &= ~HCCHAR_CHENA;
412
+ s->hreg1[index] = hcchar;
413
+ if (!(intr & HCINTMSK_CHHLTD)) {
414
+ intr |= HCINTMSK_CHHLTD | HCINTMSK_XFERCOMPL;
415
+ }
416
+ intr &= ~HCINTMSK_RESERVED14_31;
417
+ s->hreg1[index + 2] |= intr;
418
+ p->needs_service = false;
419
+ trace_usb_dwc2_packet_done(pstatus[stsidx], actual, len, pcnt);
420
+ dwc2_update_hc_irq(s, index);
421
+ return;
422
+ }
423
+
424
+ p->devadr = devadr;
425
+ p->epnum = epnum;
426
+ p->epdir = epdir;
427
+ p->mps = mps;
428
+ p->pid = pid;
429
+ p->index = index;
430
+ p->pcnt = pcnt;
431
+ p->len = len;
432
+ p->needs_service = true;
433
+ trace_usb_dwc2_packet_next(pstatus[stsidx], len, pcnt);
434
+ if (do_intr) {
435
+ dwc2_update_hc_irq(s, index);
436
+ }
437
+}
438
+
439
+/* Attach or detach a device on root hub */
440
+
441
+static const char *speeds[] = {
442
+ "low", "full", "high"
443
+};
444
+
445
+static void dwc2_attach(USBPort *port)
446
+{
447
+ DWC2State *s = port->opaque;
448
+ int hispd = 0;
449
+
450
+ trace_usb_dwc2_attach(port);
451
+ assert(port->index == 0);
452
+
453
+ if (!port->dev || !port->dev->attached) {
454
+ return;
455
+ }
456
+
457
+ assert(port->dev->speed <= USB_SPEED_HIGH);
458
+ trace_usb_dwc2_attach_speed(speeds[port->dev->speed]);
459
+ s->hprt0 &= ~HPRT0_SPD_MASK;
460
+
461
+ switch (port->dev->speed) {
462
+ case USB_SPEED_LOW:
463
+ s->hprt0 |= HPRT0_SPD_LOW_SPEED << HPRT0_SPD_SHIFT;
464
+ break;
465
+ case USB_SPEED_FULL:
466
+ s->hprt0 |= HPRT0_SPD_FULL_SPEED << HPRT0_SPD_SHIFT;
467
+ break;
468
+ case USB_SPEED_HIGH:
469
+ s->hprt0 |= HPRT0_SPD_HIGH_SPEED << HPRT0_SPD_SHIFT;
470
+ hispd = 1;
471
+ break;
472
+ }
473
+
474
+ if (hispd) {
475
+ s->usb_frame_time = NANOSECONDS_PER_SECOND / 8000; /* 125000 */
476
+ if (NANOSECONDS_PER_SECOND >= USB_HZ_HS) {
477
+ s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_HS; /* 10.4 */
478
+ } else {
479
+ s->usb_bit_time = 1;
480
+ }
481
+ } else {
482
+ s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000; /* 1000000 */
483
+ if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
484
+ s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 */
485
+ } else {
486
+ s->usb_bit_time = 1;
487
+ }
488
+ }
489
+
490
+ s->fi = USB_FRMINTVL - 1;
491
+ s->hprt0 |= HPRT0_CONNDET | HPRT0_CONNSTS;
492
+
493
+ dwc2_bus_start(s);
494
+ dwc2_raise_global_irq(s, GINTSTS_PRTINT);
495
+}
496
+
497
+static void dwc2_detach(USBPort *port)
498
+{
499
+ DWC2State *s = port->opaque;
500
+
501
+ trace_usb_dwc2_detach(port);
502
+ assert(port->index == 0);
503
+
504
+ dwc2_bus_stop(s);
505
+
506
+ s->hprt0 &= ~(HPRT0_SPD_MASK | HPRT0_SUSP | HPRT0_ENA | HPRT0_CONNSTS);
507
+ s->hprt0 |= HPRT0_CONNDET | HPRT0_ENACHG;
508
+
509
+ dwc2_raise_global_irq(s, GINTSTS_PRTINT);
510
+}
511
+
512
+static void dwc2_child_detach(USBPort *port, USBDevice *child)
513
+{
514
+ trace_usb_dwc2_child_detach(port, child);
515
+ assert(port->index == 0);
516
+}
517
+
518
+static void dwc2_wakeup(USBPort *port)
519
+{
520
+ DWC2State *s = port->opaque;
521
+
522
+ trace_usb_dwc2_wakeup(port);
523
+ assert(port->index == 0);
524
+
525
+ if (s->hprt0 & HPRT0_SUSP) {
526
+ s->hprt0 |= HPRT0_RES;
527
+ dwc2_raise_global_irq(s, GINTSTS_PRTINT);
528
+ }
529
+
530
+ qemu_bh_schedule(s->async_bh);
531
+}
532
+
533
+static void dwc2_async_packet_complete(USBPort *port, USBPacket *packet)
534
+{
535
+ DWC2State *s = port->opaque;
536
+ DWC2Packet *p;
537
+ USBDevice *dev;
538
+ USBEndpoint *ep;
539
+
540
+ assert(port->index == 0);
541
+ p = container_of(packet, DWC2Packet, packet);
542
+ dev = dwc2_find_device(s, p->devadr);
543
+ ep = usb_ep_get(dev, p->pid, p->epnum);
544
+ trace_usb_dwc2_async_packet_complete(port, packet, p->index >> 3, dev,
545
+ p->epnum, dirs[p->epdir], p->len);
546
+ assert(p->async == DWC2_ASYNC_INFLIGHT);
547
+
548
+ if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
549
+ usb_cancel_packet(packet);
550
+ usb_packet_cleanup(packet);
551
+ return;
552
+ }
553
+
554
+ dwc2_handle_packet(s, p->devadr, dev, ep, p->index, false);
555
+
556
+ p->async = DWC2_ASYNC_FINISHED;
557
+ qemu_bh_schedule(s->async_bh);
558
+}
559
+
560
+static USBPortOps dwc2_port_ops = {
561
+ .attach = dwc2_attach,
562
+ .detach = dwc2_detach,
563
+ .child_detach = dwc2_child_detach,
564
+ .wakeup = dwc2_wakeup,
565
+ .complete = dwc2_async_packet_complete,
566
+};
567
+
568
+static uint32_t dwc2_get_frame_remaining(DWC2State *s)
569
+{
570
+ uint32_t fr = 0;
571
+ int64_t tks;
572
+
573
+ tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->sof_time;
574
+ if (tks < 0) {
575
+ tks = 0;
576
+ }
577
+
578
+ /* avoid muldiv if possible */
579
+ if (tks >= s->usb_frame_time) {
580
+ goto out;
581
+ }
582
+ if (tks < s->usb_bit_time) {
583
+ fr = s->fi;
584
+ goto out;
585
+ }
586
+
587
+ /* tks = number of ns since SOF, divided by 83 (fs) or 10 (hs) */
588
+ tks = tks / s->usb_bit_time;
589
+ if (tks >= (int64_t)s->fi) {
590
+ goto out;
591
+ }
592
+
593
+ /* remaining = frame interval minus tks */
594
+ fr = (uint32_t)((int64_t)s->fi - tks);
595
+
596
+out:
597
+ return fr;
598
+}
599
+
600
+static void dwc2_work_bh(void *opaque)
601
+{
602
+ DWC2State *s = opaque;
603
+ DWC2Packet *p;
604
+ USBDevice *dev;
605
+ USBEndpoint *ep;
606
+ int64_t t_now, expire_time;
607
+ int chan;
608
+ bool found = false;
609
+
610
+ trace_usb_dwc2_work_bh();
611
+ if (s->working) {
612
+ return;
613
+ }
614
+ s->working = true;
615
+
616
+ t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
617
+ chan = s->next_chan;
618
+
619
+ do {
620
+ p = &s->packet[chan];
621
+ if (p->needs_service) {
622
+ dev = dwc2_find_device(s, p->devadr);
623
+ ep = usb_ep_get(dev, p->pid, p->epnum);
624
+ trace_usb_dwc2_work_bh_service(s->next_chan, chan, dev, p->epnum);
625
+ dwc2_handle_packet(s, p->devadr, dev, ep, p->index, true);
626
+ found = true;
627
+ }
628
+ if (++chan == DWC2_NB_CHAN) {
629
+ chan = 0;
630
+ }
631
+ if (found) {
632
+ s->next_chan = chan;
633
+ trace_usb_dwc2_work_bh_next(chan);
634
+ }
635
+ } while (chan != s->next_chan);
636
+
637
+ if (found) {
638
+ expire_time = t_now + NANOSECONDS_PER_SECOND / 4000;
639
+ timer_mod(s->frame_timer, expire_time);
640
+ }
641
+ s->working = false;
642
+}
643
+
644
+static void dwc2_enable_chan(DWC2State *s, uint32_t index)
645
+{
646
+ USBDevice *dev;
647
+ USBEndpoint *ep;
648
+ uint32_t hcchar;
649
+ uint32_t hctsiz;
650
+ uint32_t devadr, epnum, epdir, eptype, pid, len;
651
+ DWC2Packet *p;
652
+
653
+ assert((index >> 3) < DWC2_NB_CHAN);
654
+ p = &s->packet[index >> 3];
655
+ hcchar = s->hreg1[index];
656
+ hctsiz = s->hreg1[index + 4];
657
+ devadr = get_field(hcchar, HCCHAR_DEVADDR);
658
+ epnum = get_field(hcchar, HCCHAR_EPNUM);
659
+ epdir = get_bit(hcchar, HCCHAR_EPDIR);
660
+ eptype = get_field(hcchar, HCCHAR_EPTYPE);
661
+ pid = get_field(hctsiz, TSIZ_SC_MC_PID);
662
+ len = get_field(hctsiz, TSIZ_XFERSIZE);
663
+
664
+ dev = dwc2_find_device(s, devadr);
665
+
666
+ trace_usb_dwc2_enable_chan(index >> 3, dev, &p->packet, epnum);
667
+ if (dev == NULL) {
668
+ return;
669
+ }
670
+
671
+ if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) {
672
+ pid = USB_TOKEN_SETUP;
673
+ } else {
674
+ pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT;
675
+ }
676
+
677
+ ep = usb_ep_get(dev, pid, epnum);
678
+
196
+ /*
679
+ /*
197
+ * Two independent timers has same base address.
680
+ * Hack: Networking doesn't like us delivering large transfers, it kind
198
+ * Based on address passed figure out which timer is being used.
681
+ * of works but the latency is horrible. So if the transfer is <= the mtu
682
+ * size, we take that as a hint that this might be a network transfer,
683
+ * and do the transfer packet-by-packet.
199
+ */
684
+ */
200
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
685
+ if (len > 1536) {
201
+ timer = 1;
686
+ p->small = false;
202
+ addr -= R_TIM1_MAX;
687
+ } else {
203
+ }
688
+ p->small = true;
204
+
689
+ }
205
+ st = &t->timers[timer];
690
+
691
+ dwc2_handle_packet(s, devadr, dev, ep, index, true);
692
+ qemu_bh_schedule(s->async_bh);
693
+}
694
+
695
+static const char *glbregnm[] = {
696
+ "GOTGCTL ", "GOTGINT ", "GAHBCFG ", "GUSBCFG ", "GRSTCTL ",
697
+ "GINTSTS ", "GINTMSK ", "GRXSTSR ", "GRXSTSP ", "GRXFSIZ ",
698
+ "GNPTXFSIZ", "GNPTXSTS ", "GI2CCTL ", "GPVNDCTL ", "GGPIO ",
699
+ "GUID ", "GSNPSID ", "GHWCFG1 ", "GHWCFG2 ", "GHWCFG3 ",
700
+ "GHWCFG4 ", "GLPMCFG ", "GPWRDN ", "GDFIFOCFG", "GADPCTL ",
701
+ "GREFCLK ", "GINTMSK2 ", "GINTSTS2 "
702
+};
703
+
704
+static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, int index,
705
+ unsigned size)
706
+{
707
+ DWC2State *s = ptr;
708
+ uint32_t val;
709
+
710
+ assert(addr <= GINTSTS2);
711
+ val = s->glbreg[index];
206
+
712
+
207
+ switch (addr) {
713
+ switch (addr) {
208
+ case R_TIM_VAL:
714
+ case GRSTCTL:
209
+ ret = ptimer_get_count(st->ptimer);
715
+ /* clear any self-clearing bits that were set */
210
+ break;
716
+ val &= ~(GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | GRSTCTL_IN_TKNQ_FLSH |
211
+
717
+ GRSTCTL_FRMCNTRRST | GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
212
+ case R_TIM_MIS:
718
+ s->glbreg[index] = val;
213
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
719
+ break;
214
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
215
+ ret = ier & isr;
216
+ break;
217
+
218
+ default:
720
+ default:
219
+ if (addr < R_TIM1_MAX) {
721
+ break;
220
+ ret = st->regs[addr];
722
+ }
723
+
724
+ trace_usb_dwc2_glbreg_read(addr, glbregnm[index], val);
725
+ return val;
726
+}
727
+
728
+static void dwc2_glbreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
729
+ unsigned size)
730
+{
731
+ DWC2State *s = ptr;
732
+ uint64_t orig = val;
733
+ uint32_t *mmio;
734
+ uint32_t old;
735
+ int iflg = 0;
736
+
737
+ assert(addr <= GINTSTS2);
738
+ mmio = &s->glbreg[index];
739
+ old = *mmio;
740
+
741
+ switch (addr) {
742
+ case GOTGCTL:
743
+ /* don't allow setting of read-only bits */
744
+ val &= ~(GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
745
+ GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
746
+ GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
747
+ /* don't allow clearing of read-only bits */
748
+ val |= old & (GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD |
749
+ GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B |
750
+ GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS);
751
+ break;
752
+ case GAHBCFG:
753
+ if ((val & GAHBCFG_GLBL_INTR_EN) && !(old & GAHBCFG_GLBL_INTR_EN)) {
754
+ iflg = 1;
755
+ }
756
+ break;
757
+ case GRSTCTL:
758
+ val |= GRSTCTL_AHBIDLE;
759
+ val &= ~GRSTCTL_DMAREQ;
760
+ if (!(old & GRSTCTL_TXFFLSH) && (val & GRSTCTL_TXFFLSH)) {
761
+ /* TODO - TX fifo flush */
762
+ qemu_log_mask(LOG_UNIMP, "Tx FIFO flush not implemented\n");
763
+ }
764
+ if (!(old & GRSTCTL_RXFFLSH) && (val & GRSTCTL_RXFFLSH)) {
765
+ /* TODO - RX fifo flush */
766
+ qemu_log_mask(LOG_UNIMP, "Rx FIFO flush not implemented\n");
767
+ }
768
+ if (!(old & GRSTCTL_IN_TKNQ_FLSH) && (val & GRSTCTL_IN_TKNQ_FLSH)) {
769
+ /* TODO - device IN token queue flush */
770
+ qemu_log_mask(LOG_UNIMP, "Token queue flush not implemented\n");
771
+ }
772
+ if (!(old & GRSTCTL_FRMCNTRRST) && (val & GRSTCTL_FRMCNTRRST)) {
773
+ /* TODO - host frame counter reset */
774
+ qemu_log_mask(LOG_UNIMP, "Frame counter reset not implemented\n");
775
+ }
776
+ if (!(old & GRSTCTL_HSFTRST) && (val & GRSTCTL_HSFTRST)) {
777
+ /* TODO - host soft reset */
778
+ qemu_log_mask(LOG_UNIMP, "Host soft reset not implemented\n");
779
+ }
780
+ if (!(old & GRSTCTL_CSFTRST) && (val & GRSTCTL_CSFTRST)) {
781
+ /* TODO - core soft reset */
782
+ qemu_log_mask(LOG_UNIMP, "Core soft reset not implemented\n");
783
+ }
784
+ /* don't allow clearing of self-clearing bits */
785
+ val |= old & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH |
786
+ GRSTCTL_IN_TKNQ_FLSH | GRSTCTL_FRMCNTRRST |
787
+ GRSTCTL_HSFTRST | GRSTCTL_CSFTRST);
788
+ break;
789
+ case GINTSTS:
790
+ /* clear the write-1-to-clear bits */
791
+ val |= ~old;
792
+ val = ~val;
793
+ /* don't allow clearing of read-only bits */
794
+ val |= old & (GINTSTS_PTXFEMP | GINTSTS_HCHINT | GINTSTS_PRTINT |
795
+ GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_GOUTNAKEFF |
796
+ GINTSTS_GINNAKEFF | GINTSTS_NPTXFEMP | GINTSTS_RXFLVL |
797
+ GINTSTS_OTGINT | GINTSTS_CURMODE_HOST);
798
+ iflg = 1;
799
+ break;
800
+ case GINTMSK:
801
+ iflg = 1;
802
+ break;
803
+ default:
804
+ break;
805
+ }
806
+
807
+ trace_usb_dwc2_glbreg_write(addr, glbregnm[index], orig, old, val);
808
+ *mmio = val;
809
+
810
+ if (iflg) {
811
+ dwc2_update_irq(s);
812
+ }
813
+}
814
+
815
+static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, int index,
816
+ unsigned size)
817
+{
818
+ DWC2State *s = ptr;
819
+ uint32_t val;
820
+
821
+ assert(addr == HPTXFSIZ);
822
+ val = s->fszreg[index];
823
+
824
+ trace_usb_dwc2_fszreg_read(addr, val);
825
+ return val;
826
+}
827
+
828
+static void dwc2_fszreg_write(void *ptr, hwaddr addr, int index, uint64_t val,
829
+ unsigned size)
830
+{
831
+ DWC2State *s = ptr;
832
+ uint64_t orig = val;
833
+ uint32_t *mmio;
834
+ uint32_t old;
835
+
836
+ assert(addr == HPTXFSIZ);
837
+ mmio = &s->fszreg[index];
838
+ old = *mmio;
839
+
840
+ trace_usb_dwc2_fszreg_write(addr, orig, old, val);
841
+ *mmio = val;
842
+}
843
+
844
+static const char *hreg0nm[] = {
845
+ "HCFG ", "HFIR ", "HFNUM ", "<rsvd> ", "HPTXSTS ",
846
+ "HAINT ", "HAINTMSK ", "HFLBADDR ", "<rsvd> ", "<rsvd> ",
847
+ "<rsvd> ", "<rsvd> ", "<rsvd> ", "<rsvd> ", "<rsvd> ",
848
+ "<rsvd> ", "HPRT0 "
849
+};
850
+
851
+static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, int index,
852
+ unsigned size)
853
+{
854
+ DWC2State *s = ptr;
855
+ uint32_t val;
856
+
857
+ assert(addr >= HCFG && addr <= HPRT0);
858
+ val = s->hreg0[index];
859
+
860
+ switch (addr) {
861
+ case HFNUM:
862
+ val = (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) |
863
+ (s->hfnum << HFNUM_FRNUM_SHIFT);
864
+ break;
865
+ default:
866
+ break;
867
+ }
868
+
869
+ trace_usb_dwc2_hreg0_read(addr, hreg0nm[index], val);
870
+ return val;
871
+}
872
+
873
+static void dwc2_hreg0_write(void *ptr, hwaddr addr, int index, uint64_t val,
874
+ unsigned size)
875
+{
876
+ DWC2State *s = ptr;
877
+ USBDevice *dev = s->uport.dev;
878
+ uint64_t orig = val;
879
+ uint32_t *mmio;
880
+ uint32_t tval, told, old;
881
+ int prst = 0;
882
+ int iflg = 0;
883
+
884
+ assert(addr >= HCFG && addr <= HPRT0);
885
+ mmio = &s->hreg0[index];
886
+ old = *mmio;
887
+
888
+ switch (addr) {
889
+ case HFIR:
890
+ break;
891
+ case HFNUM:
892
+ case HPTXSTS:
893
+ case HAINT:
894
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
895
+ __func__);
896
+ return;
897
+ case HAINTMSK:
898
+ val &= 0xffff;
899
+ break;
900
+ case HPRT0:
901
+ /* don't allow clearing of read-only bits */
902
+ val |= old & (HPRT0_SPD_MASK | HPRT0_LNSTS_MASK | HPRT0_OVRCURRACT |
903
+ HPRT0_CONNSTS);
904
+ /* don't allow clearing of self-clearing bits */
905
+ val |= old & (HPRT0_SUSP | HPRT0_RES);
906
+ /* don't allow setting of self-setting bits */
907
+ if (!(old & HPRT0_ENA) && (val & HPRT0_ENA)) {
908
+ val &= ~HPRT0_ENA;
909
+ }
910
+ /* clear the write-1-to-clear bits */
911
+ tval = val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
912
+ HPRT0_CONNDET);
913
+ told = old & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
914
+ HPRT0_CONNDET);
915
+ tval |= ~told;
916
+ tval = ~tval;
917
+ tval &= (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
918
+ HPRT0_CONNDET);
919
+ val &= ~(HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA |
920
+ HPRT0_CONNDET);
921
+ val |= tval;
922
+ if (!(val & HPRT0_RST) && (old & HPRT0_RST)) {
923
+ if (dev && dev->attached) {
924
+ val |= HPRT0_ENA | HPRT0_ENACHG;
925
+ prst = 1;
926
+ }
927
+ }
928
+ if (val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_CONNDET)) {
929
+ iflg = 1;
221
+ } else {
930
+ } else {
222
+ qemu_log_mask(LOG_GUEST_ERROR,
931
+ iflg = -1;
223
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
932
+ }
224
+ return ret;
933
+ break;
225
+ }
934
+ default:
226
+ break;
935
+ break;
227
+ }
936
+ }
228
+
937
+
229
+ DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset,
938
+ if (prst) {
230
+ ret);
939
+ trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old,
231
+ return ret;
940
+ val & ~HPRT0_CONNDET);
232
+}
941
+ trace_usb_dwc2_hreg0_action("call usb_port_reset");
233
+
942
+ usb_port_reset(&s->uport);
234
+static void
943
+ val &= ~HPRT0_CONNDET;
235
+timer_write(void *opaque, hwaddr offset,
944
+ } else {
236
+ uint64_t val64, unsigned int size)
945
+ trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, val);
237
+{
946
+ }
238
+ MSSTimerState *t = opaque;
947
+
239
+ hwaddr addr;
948
+ *mmio = val;
240
+ struct Msf2Timer *st;
949
+
241
+ int timer = 0;
950
+ if (iflg > 0) {
242
+ uint32_t value = val64;
951
+ trace_usb_dwc2_hreg0_action("enable PRTINT");
243
+
952
+ dwc2_raise_global_irq(s, GINTSTS_PRTINT);
244
+ addr = offset >> 2;
953
+ } else if (iflg < 0) {
245
+ /*
954
+ trace_usb_dwc2_hreg0_action("disable PRTINT");
246
+ * Two independent timers has same base address.
955
+ dwc2_lower_global_irq(s, GINTSTS_PRTINT);
247
+ * Based on addr passed figure out which timer is being used.
956
+ }
248
+ */
957
+}
249
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
958
+
250
+ timer = 1;
959
+static const char *hreg1nm[] = {
251
+ addr -= R_TIM1_MAX;
960
+ "HCCHAR ", "HCSPLT ", "HCINT ", "HCINTMSK", "HCTSIZ ", "HCDMA ",
252
+ }
961
+ "<rsvd> ", "HCDMAB "
253
+
962
+};
254
+ st = &t->timers[timer];
963
+
255
+
964
+static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, int index,
256
+ DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
965
+ unsigned size)
257
+ value, timer);
966
+{
967
+ DWC2State *s = ptr;
968
+ uint32_t val;
969
+
970
+ assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
971
+ val = s->hreg1[index];
972
+
973
+ trace_usb_dwc2_hreg1_read(addr, hreg1nm[index & 7], addr >> 5, val);
974
+ return val;
975
+}
976
+
977
+static void dwc2_hreg1_write(void *ptr, hwaddr addr, int index, uint64_t val,
978
+ unsigned size)
979
+{
980
+ DWC2State *s = ptr;
981
+ uint64_t orig = val;
982
+ uint32_t *mmio;
983
+ uint32_t old;
984
+ int iflg = 0;
985
+ int enflg = 0;
986
+ int disflg = 0;
987
+
988
+ assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1));
989
+ mmio = &s->hreg1[index];
990
+ old = *mmio;
991
+
992
+ switch (HSOTG_REG(0x500) + (addr & 0x1c)) {
993
+ case HCCHAR(0):
994
+ if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) {
995
+ val &= ~(HCCHAR_CHENA | HCCHAR_CHDIS);
996
+ disflg = 1;
997
+ } else {
998
+ val |= old & HCCHAR_CHDIS;
999
+ if ((val & HCCHAR_CHENA) && !(old & HCCHAR_CHENA)) {
1000
+ val &= ~HCCHAR_CHDIS;
1001
+ enflg = 1;
1002
+ } else {
1003
+ val |= old & HCCHAR_CHENA;
1004
+ }
1005
+ }
1006
+ break;
1007
+ case HCINT(0):
1008
+ /* clear the write-1-to-clear bits */
1009
+ val |= ~old;
1010
+ val = ~val;
1011
+ val &= ~HCINTMSK_RESERVED14_31;
1012
+ iflg = 1;
1013
+ break;
1014
+ case HCINTMSK(0):
1015
+ val &= ~HCINTMSK_RESERVED14_31;
1016
+ iflg = 1;
1017
+ break;
1018
+ case HCDMAB(0):
1019
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n",
1020
+ __func__);
1021
+ return;
1022
+ default:
1023
+ break;
1024
+ }
1025
+
1026
+ trace_usb_dwc2_hreg1_write(addr, hreg1nm[index & 7], index >> 3, orig,
1027
+ old, val);
1028
+ *mmio = val;
1029
+
1030
+ if (disflg) {
1031
+ /* set ChHltd in HCINT */
1032
+ s->hreg1[(index & ~7) + 2] |= HCINTMSK_CHHLTD;
1033
+ iflg = 1;
1034
+ }
1035
+
1036
+ if (enflg) {
1037
+ dwc2_enable_chan(s, index & ~7);
1038
+ }
1039
+
1040
+ if (iflg) {
1041
+ dwc2_update_hc_irq(s, index & ~7);
1042
+ }
1043
+}
1044
+
1045
+static const char *pcgregnm[] = {
1046
+ "PCGCTL ", "PCGCCTL1 "
1047
+};
1048
+
1049
+static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, int index,
1050
+ unsigned size)
1051
+{
1052
+ DWC2State *s = ptr;
1053
+ uint32_t val;
1054
+
1055
+ assert(addr >= PCGCTL && addr <= PCGCCTL1);
1056
+ val = s->pcgreg[index];
1057
+
1058
+ trace_usb_dwc2_pcgreg_read(addr, pcgregnm[index], val);
1059
+ return val;
1060
+}
1061
+
1062
+static void dwc2_pcgreg_write(void *ptr, hwaddr addr, int index,
1063
+ uint64_t val, unsigned size)
1064
+{
1065
+ DWC2State *s = ptr;
1066
+ uint64_t orig = val;
1067
+ uint32_t *mmio;
1068
+ uint32_t old;
1069
+
1070
+ assert(addr >= PCGCTL && addr <= PCGCCTL1);
1071
+ mmio = &s->pcgreg[index];
1072
+ old = *mmio;
1073
+
1074
+ trace_usb_dwc2_pcgreg_write(addr, pcgregnm[index], orig, old, val);
1075
+ *mmio = val;
1076
+}
1077
+
1078
+static uint64_t dwc2_hsotg_read(void *ptr, hwaddr addr, unsigned size)
1079
+{
1080
+ uint64_t val;
258
+
1081
+
259
+ switch (addr) {
1082
+ switch (addr) {
260
+ case R_TIM_CTRL:
1083
+ case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
261
+ st->regs[R_TIM_CTRL] = value;
1084
+ val = dwc2_glbreg_read(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, size);
262
+ timer_update(st);
1085
+ break;
263
+ break;
1086
+ case HSOTG_REG(0x100):
264
+
1087
+ val = dwc2_fszreg_read(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, size);
265
+ case R_TIM_RIS:
1088
+ break;
266
+ if (value & TIMER_RIS_ACK) {
1089
+ case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
267
+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
1090
+ /* Gadget-mode registers, just return 0 for now */
268
+ }
1091
+ val = 0;
269
+ break;
1092
+ break;
270
+
1093
+ case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
271
+ case R_TIM_LOADVAL:
1094
+ val = dwc2_hreg0_read(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, size);
272
+ st->regs[R_TIM_LOADVAL] = value;
1095
+ break;
273
+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
1096
+ case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
274
+ timer_update(st);
1097
+ val = dwc2_hreg1_read(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, size);
275
+ }
1098
+ break;
276
+ break;
1099
+ case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
277
+
1100
+ /* Gadget-mode registers, just return 0 for now */
278
+ case R_TIM_BGLOADVAL:
1101
+ val = 0;
279
+ st->regs[R_TIM_BGLOADVAL] = value;
1102
+ break;
280
+ st->regs[R_TIM_LOADVAL] = value;
1103
+ case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
281
+ break;
1104
+ val = dwc2_pcgreg_read(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, size);
282
+
1105
+ break;
283
+ case R_TIM_VAL:
284
+ case R_TIM_MIS:
285
+ break;
286
+
287
+ default:
1106
+ default:
288
+ if (addr < R_TIM1_MAX) {
1107
+ g_assert_not_reached();
289
+ st->regs[addr] = value;
1108
+ }
290
+ } else {
1109
+
291
+ qemu_log_mask(LOG_GUEST_ERROR,
1110
+ return val;
292
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
1111
+}
293
+ return;
1112
+
294
+ }
1113
+static void dwc2_hsotg_write(void *ptr, hwaddr addr, uint64_t val,
295
+ break;
1114
+ unsigned size)
296
+ }
1115
+{
297
+ timer_update_irq(st);
1116
+ switch (addr) {
298
+}
1117
+ case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc):
299
+
1118
+ dwc2_glbreg_write(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, val, size);
300
+static const MemoryRegionOps timer_ops = {
1119
+ break;
301
+ .read = timer_read,
1120
+ case HSOTG_REG(0x100):
302
+ .write = timer_write,
1121
+ dwc2_fszreg_write(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, val, size);
303
+ .endianness = DEVICE_NATIVE_ENDIAN,
1122
+ break;
304
+ .valid = {
1123
+ case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc):
305
+ .min_access_size = 1,
1124
+ /* Gadget-mode registers, do nothing for now */
306
+ .max_access_size = 4
1125
+ break;
307
+ }
1126
+ case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc):
308
+};
1127
+ dwc2_hreg0_write(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, val, size);
309
+
1128
+ break;
310
+static void timer_hit(void *opaque)
1129
+ case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc):
311
+{
1130
+ dwc2_hreg1_write(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, val, size);
312
+ struct Msf2Timer *st = opaque;
1131
+ break;
313
+
1132
+ case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc):
314
+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
1133
+ /* Gadget-mode registers, do nothing for now */
315
+
1134
+ break;
316
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
1135
+ case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc):
317
+ timer_update(st);
1136
+ dwc2_pcgreg_write(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, val, size);
318
+ }
1137
+ break;
319
+ timer_update_irq(st);
1138
+ default:
320
+}
1139
+ g_assert_not_reached();
321
+
1140
+ }
322
+static void mss_timer_init(Object *obj)
1141
+}
323
+{
1142
+
324
+ MSSTimerState *t = MSS_TIMER(obj);
1143
+static const MemoryRegionOps dwc2_mmio_hsotg_ops = {
1144
+ .read = dwc2_hsotg_read,
1145
+ .write = dwc2_hsotg_write,
1146
+ .impl.min_access_size = 4,
1147
+ .impl.max_access_size = 4,
1148
+ .endianness = DEVICE_LITTLE_ENDIAN,
1149
+};
1150
+
1151
+static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size)
1152
+{
1153
+ /* TODO - implement FIFOs to support slave mode */
1154
+ trace_usb_dwc2_hreg2_read(addr, addr >> 12, 0);
1155
+ qemu_log_mask(LOG_UNIMP, "FIFO read not implemented\n");
1156
+ return 0;
1157
+}
1158
+
1159
+static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val,
1160
+ unsigned size)
1161
+{
1162
+ uint64_t orig = val;
1163
+
1164
+ /* TODO - implement FIFOs to support slave mode */
1165
+ trace_usb_dwc2_hreg2_write(addr, addr >> 12, orig, 0, val);
1166
+ qemu_log_mask(LOG_UNIMP, "FIFO write not implemented\n");
1167
+}
1168
+
1169
+static const MemoryRegionOps dwc2_mmio_hreg2_ops = {
1170
+ .read = dwc2_hreg2_read,
1171
+ .write = dwc2_hreg2_write,
1172
+ .impl.min_access_size = 4,
1173
+ .impl.max_access_size = 4,
1174
+ .endianness = DEVICE_LITTLE_ENDIAN,
1175
+};
1176
+
1177
+static void dwc2_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
1178
+ unsigned int stream)
1179
+{
1180
+ DWC2State *s = container_of(bus, DWC2State, bus);
1181
+
1182
+ trace_usb_dwc2_wakeup_endpoint(ep, stream);
1183
+
1184
+ /* TODO - do something here? */
1185
+ qemu_bh_schedule(s->async_bh);
1186
+}
1187
+
1188
+static USBBusOps dwc2_bus_ops = {
1189
+ .wakeup_endpoint = dwc2_wakeup_endpoint,
1190
+};
1191
+
1192
+static void dwc2_work_timer(void *opaque)
1193
+{
1194
+ DWC2State *s = opaque;
1195
+
1196
+ trace_usb_dwc2_work_timer();
1197
+ qemu_bh_schedule(s->async_bh);
1198
+}
1199
+
1200
+static void dwc2_reset_enter(Object *obj, ResetType type)
1201
+{
1202
+ DWC2Class *c = DWC2_GET_CLASS(obj);
1203
+ DWC2State *s = DWC2_USB(obj);
325
+ int i;
1204
+ int i;
326
+
1205
+
327
+ /* Init all the ptimers. */
1206
+ trace_usb_dwc2_reset_enter();
328
+ for (i = 0; i < NUM_TIMERS; i++) {
1207
+
329
+ struct Msf2Timer *st = &t->timers[i];
1208
+ if (c->parent_phases.enter) {
330
+
1209
+ c->parent_phases.enter(obj, type);
331
+ st->bh = qemu_bh_new(timer_hit, st);
1210
+ }
332
+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
1211
+
333
+ ptimer_set_freq(st->ptimer, t->freq_hz);
1212
+ timer_del(s->frame_timer);
334
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
1213
+ qemu_bh_cancel(s->async_bh);
335
+ }
1214
+
336
+
1215
+ if (s->uport.dev && s->uport.dev->attached) {
337
+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
1216
+ usb_detach(&s->uport);
338
+ NUM_TIMERS * R_TIM1_MAX * 4);
1217
+ }
339
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
1218
+
340
+}
1219
+ dwc2_bus_stop(s);
341
+
1220
+
342
+static const VMStateDescription vmstate_timers = {
1221
+ s->gotgctl = GOTGCTL_BSESVLD | GOTGCTL_ASESVLD | GOTGCTL_CONID_B;
343
+ .name = "mss-timer-block",
1222
+ s->gotgint = 0;
1223
+ s->gahbcfg = 0;
1224
+ s->gusbcfg = 5 << GUSBCFG_USBTRDTIM_SHIFT;
1225
+ s->grstctl = GRSTCTL_AHBIDLE;
1226
+ s->gintsts = GINTSTS_CONIDSTSCHNG | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP |
1227
+ GINTSTS_CURMODE_HOST;
1228
+ s->gintmsk = 0;
1229
+ s->grxstsr = 0;
1230
+ s->grxstsp = 0;
1231
+ s->grxfsiz = 1024;
1232
+ s->gnptxfsiz = 1024 << FIFOSIZE_DEPTH_SHIFT;
1233
+ s->gnptxsts = (4 << FIFOSIZE_DEPTH_SHIFT) | 1024;
1234
+ s->gi2cctl = GI2CCTL_I2CDATSE0 | GI2CCTL_ACK;
1235
+ s->gpvndctl = 0;
1236
+ s->ggpio = 0;
1237
+ s->guid = 0;
1238
+ s->gsnpsid = 0x4f54294a;
1239
+ s->ghwcfg1 = 0;
1240
+ s->ghwcfg2 = (8 << GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT) |
1241
+ (4 << GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT) |
1242
+ (4 << GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT) |
1243
+ GHWCFG2_DYNAMIC_FIFO |
1244
+ GHWCFG2_PERIO_EP_SUPPORTED |
1245
+ ((DWC2_NB_CHAN - 1) << GHWCFG2_NUM_HOST_CHAN_SHIFT) |
1246
+ (GHWCFG2_INT_DMA_ARCH << GHWCFG2_ARCHITECTURE_SHIFT) |
1247
+ (GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST << GHWCFG2_OP_MODE_SHIFT);
1248
+ s->ghwcfg3 = (4096 << GHWCFG3_DFIFO_DEPTH_SHIFT) |
1249
+ (4 << GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT) |
1250
+ (4 << GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT);
1251
+ s->ghwcfg4 = 0;
1252
+ s->glpmcfg = 0;
1253
+ s->gpwrdn = GPWRDN_PWRDNRSTN;
1254
+ s->gdfifocfg = 0;
1255
+ s->gadpctl = 0;
1256
+ s->grefclk = 0;
1257
+ s->gintmsk2 = 0;
1258
+ s->gintsts2 = 0;
1259
+
1260
+ s->hptxfsiz = 500 << FIFOSIZE_DEPTH_SHIFT;
1261
+
1262
+ s->hcfg = 2 << HCFG_RESVALID_SHIFT;
1263
+ s->hfir = 60000;
1264
+ s->hfnum = 0x3fff;
1265
+ s->hptxsts = (16 << TXSTS_QSPCAVAIL_SHIFT) | 32768;
1266
+ s->haint = 0;
1267
+ s->haintmsk = 0;
1268
+ s->hprt0 = 0;
1269
+
1270
+ memset(s->hreg1, 0, sizeof(s->hreg1));
1271
+ memset(s->pcgreg, 0, sizeof(s->pcgreg));
1272
+
1273
+ s->sof_time = 0;
1274
+ s->frame_number = 0;
1275
+ s->fi = USB_FRMINTVL - 1;
1276
+ s->next_chan = 0;
1277
+ s->working = false;
1278
+
1279
+ for (i = 0; i < DWC2_NB_CHAN; i++) {
1280
+ s->packet[i].needs_service = false;
1281
+ }
1282
+}
1283
+
1284
+static void dwc2_reset_hold(Object *obj)
1285
+{
1286
+ DWC2Class *c = DWC2_GET_CLASS(obj);
1287
+ DWC2State *s = DWC2_USB(obj);
1288
+
1289
+ trace_usb_dwc2_reset_hold();
1290
+
1291
+ if (c->parent_phases.hold) {
1292
+ c->parent_phases.hold(obj);
1293
+ }
1294
+
1295
+ dwc2_update_irq(s);
1296
+}
1297
+
1298
+static void dwc2_reset_exit(Object *obj)
1299
+{
1300
+ DWC2Class *c = DWC2_GET_CLASS(obj);
1301
+ DWC2State *s = DWC2_USB(obj);
1302
+
1303
+ trace_usb_dwc2_reset_exit();
1304
+
1305
+ if (c->parent_phases.exit) {
1306
+ c->parent_phases.exit(obj);
1307
+ }
1308
+
1309
+ s->hprt0 = HPRT0_PWR;
1310
+ if (s->uport.dev && s->uport.dev->attached) {
1311
+ usb_attach(&s->uport);
1312
+ usb_device_reset(s->uport.dev);
1313
+ }
1314
+}
1315
+
1316
+static void dwc2_realize(DeviceState *dev, Error **errp)
1317
+{
1318
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1319
+ DWC2State *s = DWC2_USB(dev);
1320
+ Object *obj;
1321
+ Error *err = NULL;
1322
+
1323
+ obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
1324
+ if (err) {
1325
+ error_setg(errp, "dwc2: required dma-mr link not found: %s",
1326
+ error_get_pretty(err));
1327
+ return;
1328
+ }
1329
+ assert(obj != NULL);
1330
+
1331
+ s->dma_mr = MEMORY_REGION(obj);
1332
+ address_space_init(&s->dma_as, s->dma_mr, "dwc2");
1333
+
1334
+ usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev);
1335
+ usb_register_port(&s->bus, &s->uport, s, 0, &dwc2_port_ops,
1336
+ USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL |
1337
+ (s->usb_version == 2 ? USB_SPEED_MASK_HIGH : 0));
1338
+ s->uport.dev = 0;
1339
+
1340
+ s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000; /* 1000000 */
1341
+ if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) {
1342
+ s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 */
1343
+ } else {
1344
+ s->usb_bit_time = 1;
1345
+ }
1346
+
1347
+ s->fi = USB_FRMINTVL - 1;
1348
+ s->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_frame_boundary, s);
1349
+ s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_work_timer, s);
1350
+ s->async_bh = qemu_bh_new(dwc2_work_bh, s);
1351
+
1352
+ sysbus_init_irq(sbd, &s->irq);
1353
+}
1354
+
1355
+static void dwc2_init(Object *obj)
1356
+{
1357
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1358
+ DWC2State *s = DWC2_USB(obj);
1359
+
1360
+ memory_region_init(&s->container, obj, "dwc2", DWC2_MMIO_SIZE);
1361
+ sysbus_init_mmio(sbd, &s->container);
1362
+
1363
+ memory_region_init_io(&s->hsotg, obj, &dwc2_mmio_hsotg_ops, s,
1364
+ "dwc2-io", 4 * KiB);
1365
+ memory_region_add_subregion(&s->container, 0x0000, &s->hsotg);
1366
+
1367
+ memory_region_init_io(&s->fifos, obj, &dwc2_mmio_hreg2_ops, s,
1368
+ "dwc2-fifo", 64 * KiB);
1369
+ memory_region_add_subregion(&s->container, 0x1000, &s->fifos);
1370
+}
1371
+
1372
+static const VMStateDescription vmstate_dwc2_state_packet = {
1373
+ .name = "dwc2/packet",
344
+ .version_id = 1,
1374
+ .version_id = 1,
345
+ .minimum_version_id = 1,
1375
+ .minimum_version_id = 1,
346
+ .fields = (VMStateField[]) {
1376
+ .fields = (VMStateField[]) {
347
+ VMSTATE_PTIMER(ptimer, struct Msf2Timer),
1377
+ VMSTATE_UINT32(devadr, DWC2Packet),
348
+ VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),
1378
+ VMSTATE_UINT32(epnum, DWC2Packet),
1379
+ VMSTATE_UINT32(epdir, DWC2Packet),
1380
+ VMSTATE_UINT32(mps, DWC2Packet),
1381
+ VMSTATE_UINT32(pid, DWC2Packet),
1382
+ VMSTATE_UINT32(index, DWC2Packet),
1383
+ VMSTATE_UINT32(pcnt, DWC2Packet),
1384
+ VMSTATE_UINT32(len, DWC2Packet),
1385
+ VMSTATE_INT32(async, DWC2Packet),
1386
+ VMSTATE_BOOL(small, DWC2Packet),
1387
+ VMSTATE_BOOL(needs_service, DWC2Packet),
349
+ VMSTATE_END_OF_LIST()
1388
+ VMSTATE_END_OF_LIST()
350
+ }
1389
+ },
351
+};
1390
+};
352
+
1391
+
353
+static const VMStateDescription vmstate_mss_timer = {
1392
+const VMStateDescription vmstate_dwc2_state = {
354
+ .name = TYPE_MSS_TIMER,
1393
+ .name = "dwc2",
355
+ .version_id = 1,
1394
+ .version_id = 1,
356
+ .minimum_version_id = 1,
1395
+ .minimum_version_id = 1,
357
+ .fields = (VMStateField[]) {
1396
+ .fields = (VMStateField[]) {
358
+ VMSTATE_UINT32(freq_hz, MSSTimerState),
1397
+ VMSTATE_UINT32_ARRAY(glbreg, DWC2State,
359
+ VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
1398
+ DWC2_GLBREG_SIZE / sizeof(uint32_t)),
360
+ vmstate_timers, struct Msf2Timer),
1399
+ VMSTATE_UINT32_ARRAY(fszreg, DWC2State,
1400
+ DWC2_FSZREG_SIZE / sizeof(uint32_t)),
1401
+ VMSTATE_UINT32_ARRAY(hreg0, DWC2State,
1402
+ DWC2_HREG0_SIZE / sizeof(uint32_t)),
1403
+ VMSTATE_UINT32_ARRAY(hreg1, DWC2State,
1404
+ DWC2_HREG1_SIZE / sizeof(uint32_t)),
1405
+ VMSTATE_UINT32_ARRAY(pcgreg, DWC2State,
1406
+ DWC2_PCGREG_SIZE / sizeof(uint32_t)),
1407
+
1408
+ VMSTATE_TIMER_PTR(eof_timer, DWC2State),
1409
+ VMSTATE_TIMER_PTR(frame_timer, DWC2State),
1410
+ VMSTATE_INT64(sof_time, DWC2State),
1411
+ VMSTATE_INT64(usb_frame_time, DWC2State),
1412
+ VMSTATE_INT64(usb_bit_time, DWC2State),
1413
+ VMSTATE_UINT32(usb_version, DWC2State),
1414
+ VMSTATE_UINT16(frame_number, DWC2State),
1415
+ VMSTATE_UINT16(fi, DWC2State),
1416
+ VMSTATE_UINT16(next_chan, DWC2State),
1417
+ VMSTATE_BOOL(working, DWC2State),
1418
+
1419
+ VMSTATE_STRUCT_ARRAY(packet, DWC2State, DWC2_NB_CHAN, 1,
1420
+ vmstate_dwc2_state_packet, DWC2Packet),
1421
+ VMSTATE_UINT8_2DARRAY(usb_buf, DWC2State, DWC2_NB_CHAN,
1422
+ DWC2_MAX_XFER_SIZE),
1423
+
361
+ VMSTATE_END_OF_LIST()
1424
+ VMSTATE_END_OF_LIST()
362
+ }
1425
+ }
363
+};
1426
+};
364
+
1427
+
365
+static Property mss_timer_properties[] = {
1428
+static Property dwc2_usb_properties[] = {
366
+ /* Libero GUI shows 100Mhz as default for clocks */
1429
+ DEFINE_PROP_UINT32("usb_version", DWC2State, usb_version, 2),
367
+ DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
368
+ 100 * 1000000),
369
+ DEFINE_PROP_END_OF_LIST(),
1430
+ DEFINE_PROP_END_OF_LIST(),
370
+};
1431
+};
371
+
1432
+
372
+static void mss_timer_class_init(ObjectClass *klass, void *data)
1433
+static void dwc2_class_init(ObjectClass *klass, void *data)
373
+{
1434
+{
374
+ DeviceClass *dc = DEVICE_CLASS(klass);
1435
+ DeviceClass *dc = DEVICE_CLASS(klass);
375
+
1436
+ DWC2Class *c = DWC2_CLASS(klass);
376
+ dc->props = mss_timer_properties;
1437
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
377
+ dc->vmsd = &vmstate_mss_timer;
1438
+
378
+}
1439
+ dc->realize = dwc2_realize;
379
+
1440
+ dc->vmsd = &vmstate_dwc2_state;
380
+static const TypeInfo mss_timer_info = {
1441
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
381
+ .name = TYPE_MSS_TIMER,
1442
+ device_class_set_props(dc, dwc2_usb_properties);
1443
+ resettable_class_set_parent_phases(rc, dwc2_reset_enter, dwc2_reset_hold,
1444
+ dwc2_reset_exit, &c->parent_phases);
1445
+}
1446
+
1447
+static const TypeInfo dwc2_usb_type_info = {
1448
+ .name = TYPE_DWC2_USB,
382
+ .parent = TYPE_SYS_BUS_DEVICE,
1449
+ .parent = TYPE_SYS_BUS_DEVICE,
383
+ .instance_size = sizeof(MSSTimerState),
1450
+ .instance_size = sizeof(DWC2State),
384
+ .instance_init = mss_timer_init,
1451
+ .instance_init = dwc2_init,
385
+ .class_init = mss_timer_class_init,
1452
+ .class_size = sizeof(DWC2Class),
386
+};
1453
+ .class_init = dwc2_class_init,
387
+
1454
+};
388
+static void mss_timer_register_types(void)
1455
+
389
+{
1456
+static void dwc2_usb_register_types(void)
390
+ type_register_static(&mss_timer_info);
1457
+{
391
+}
1458
+ type_register_static(&dwc2_usb_type_info);
392
+
1459
+}
393
+type_init(mss_timer_register_types)
1460
+
1461
+type_init(dwc2_usb_register_types)
1462
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
1463
index XXXXXXX..XXXXXXX 100644
1464
--- a/hw/usb/Kconfig
1465
+++ b/hw/usb/Kconfig
1466
@@ -XXX,XX +XXX,XX @@ config USB_MUSB
1467
bool
1468
select USB
1469
1470
+config USB_DWC2
1471
+ bool
1472
+ default y
1473
+ select USB
1474
+
1475
config TUSB6010
1476
bool
1477
select USB_MUSB
1478
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
1479
index XXXXXXX..XXXXXXX 100644
1480
--- a/hw/usb/Makefile.objs
1481
+++ b/hw/usb/Makefile.objs
1482
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o
1483
common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o
1484
common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
1485
common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
1486
+common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o
1487
1488
common-obj-$(CONFIG_TUSB6010) += tusb6010.o
1489
common-obj-$(CONFIG_IMX) += chipidea.o
1490
diff --git a/hw/usb/trace-events b/hw/usb/trace-events
1491
index XXXXXXX..XXXXXXX 100644
1492
--- a/hw/usb/trace-events
1493
+++ b/hw/usb/trace-events
1494
@@ -XXX,XX +XXX,XX @@ usb_xhci_xfer_error(void *xfer, uint32_t ret) "%p: ret %d"
1495
usb_xhci_unimplemented(const char *item, int nr) "%s (0x%x)"
1496
usb_xhci_enforced_limit(const char *item) "%s"
1497
1498
+# hcd-dwc2.c
1499
+usb_dwc2_update_irq(uint32_t level) "level=%d"
1500
+usb_dwc2_raise_global_irq(uint32_t intr) "0x%08x"
1501
+usb_dwc2_lower_global_irq(uint32_t intr) "0x%08x"
1502
+usb_dwc2_raise_host_irq(uint32_t intr) "0x%04x"
1503
+usb_dwc2_lower_host_irq(uint32_t intr) "0x%04x"
1504
+usb_dwc2_sof(int64_t next) "next SOF %" PRId64
1505
+usb_dwc2_bus_start(void) "start SOFs"
1506
+usb_dwc2_bus_stop(void) "stop SOFs"
1507
+usb_dwc2_find_device(uint8_t addr) "%d"
1508
+usb_dwc2_port_disabled(uint32_t pnum) "port %d disabled"
1509
+usb_dwc2_device_found(uint32_t pnum) "device found on port %d"
1510
+usb_dwc2_device_not_found(void) "device not found"
1511
+usb_dwc2_handle_packet(uint32_t chan, void *dev, void *pkt, uint32_t ep, const char *type, const char *dir, uint32_t mps, uint32_t len, uint32_t pcnt) "ch %d dev %p pkt %p ep %d type %s dir %s mps %d len %d pcnt %d"
1512
+usb_dwc2_memory_read(uint32_t addr, uint32_t len) "addr %d len %d"
1513
+usb_dwc2_packet_status(const char *status, uint32_t len) "status %s len %d"
1514
+usb_dwc2_packet_error(const char *status) "ERROR %s"
1515
+usb_dwc2_async_packet(void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "pkt %p ch %d dev %p ep %d %s len %d"
1516
+usb_dwc2_memory_write(uint32_t addr, uint32_t len) "addr %d len %d"
1517
+usb_dwc2_packet_done(const char *status, uint32_t actual, uint32_t len, uint32_t pcnt) "status %s actual %d len %d pcnt %d"
1518
+usb_dwc2_packet_next(const char *status, uint32_t len, uint32_t pcnt) "status %s len %d pcnt %d"
1519
+usb_dwc2_attach(void *port) "port %p"
1520
+usb_dwc2_attach_speed(const char *speed) "%s-speed device attached"
1521
+usb_dwc2_detach(void *port) "port %p"
1522
+usb_dwc2_child_detach(void *port, void *child) "port %p child %p"
1523
+usb_dwc2_wakeup(void *port) "port %p"
1524
+usb_dwc2_async_packet_complete(void *port, void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "port %p packet %p ch %d dev %p ep %d %s len %d"
1525
+usb_dwc2_work_bh(void) ""
1526
+usb_dwc2_work_bh_service(uint32_t first, uint32_t current, void *dev, uint32_t ep) "first %d servicing %d dev %p ep %d"
1527
+usb_dwc2_work_bh_next(uint32_t chan) "next %d"
1528
+usb_dwc2_enable_chan(uint32_t chan, void *dev, void *pkt, uint32_t ep) "ch %d dev %p pkt %p ep %d"
1529
+usb_dwc2_glbreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
1530
+usb_dwc2_glbreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
1531
+usb_dwc2_fszreg_read(uint64_t addr, uint32_t val) " 0x%04" PRIx64 " HPTXFSIZ val 0x%08x"
1532
+usb_dwc2_fszreg_write(uint64_t addr, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " HPTXFSIZ val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
1533
+usb_dwc2_hreg0_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
1534
+usb_dwc2_hreg0_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
1535
+usb_dwc2_hreg1_read(uint64_t addr, const char *reg, uint64_t chan, uint32_t val) " 0x%04" PRIx64 " %s%" PRId64 " val 0x%08x"
1536
+usb_dwc2_hreg1_write(uint64_t addr, const char *reg, uint64_t chan, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s%" PRId64 " val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
1537
+usb_dwc2_pcgreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x"
1538
+usb_dwc2_pcgreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
1539
+usb_dwc2_hreg2_read(uint64_t addr, uint64_t fifo, uint32_t val) " 0x%04" PRIx64 " FIFO%" PRId64 " val 0x%08x"
1540
+usb_dwc2_hreg2_write(uint64_t addr, uint64_t fifo, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " FIFO%" PRId64 " val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64
1541
+usb_dwc2_hreg0_action(const char *s) "%s"
1542
+usb_dwc2_wakeup_endpoint(void *ep, uint32_t stream) "endp %p stream %d"
1543
+usb_dwc2_work_timer(void) ""
1544
+usb_dwc2_reset_enter(void) "=== RESET enter ==="
1545
+usb_dwc2_reset_hold(void) "=== RESET hold ==="
1546
+usb_dwc2_reset_exit(void) "=== RESET exit ==="
1547
+
1548
# desc.c
1549
usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d"
1550
usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d"
394
--
1551
--
395
2.7.4
1552
2.20.1
396
1553
397
1554
diff view generated by jsdifflib
1
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
1
From: Paul Zimmerman <pauldzim@gmail.com>
2
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
3
preempt execution. The simple way to achieve this is to clear the
4
enable bit for it, since the enable bit isn't guest visible.
5
2
3
The dwc-hsotg (dwc2) USB host depends on a short packet to
4
indicate the end of an IN transfer. The usb-storage driver
5
currently doesn't provide this, so fix it.
6
7
I have tested this change rather extensively using a PC
8
emulation with xhci, ehci, and uhci controllers, and have
9
not observed any regressions.
10
11
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
12
Message-id: 20200520235349.21215-6-pauldzim@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org
9
---
14
---
10
hw/intc/armv7m_nvic.c | 12 ++++++++++--
15
hw/usb/dev-storage.c | 15 ++++++++++++++-
11
1 file changed, 10 insertions(+), 2 deletions(-)
16
1 file changed, 14 insertions(+), 1 deletion(-)
12
17
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/armv7m_nvic.c
20
--- a/hw/usb/dev-storage.c
16
+++ b/hw/intc/armv7m_nvic.c
21
+++ b/hw/usb/dev-storage.c
17
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
22
@@ -XXX,XX +XXX,XX @@ static void usb_msd_copy_data(MSDState *s, USBPacket *p)
18
(R_V7M_AIRCR_SYSRESETREQS_MASK |
23
usb_packet_copy(p, scsi_req_get_buf(s->req) + s->scsi_off, len);
19
R_V7M_AIRCR_BFHFNMINS_MASK |
24
s->scsi_len -= len;
20
R_V7M_AIRCR_PRIS_MASK);
25
s->scsi_off += len;
21
- /* BFHFNMINS changes the priority of Secure HardFault */
26
+ if (len > s->data_len) {
22
+ /* BFHFNMINS changes the priority of Secure HardFault, and
27
+ len = s->data_len;
23
+ * allows a pending Non-secure HardFault to preempt (which
28
+ }
24
+ * we implement by marking it enabled).
29
s->data_len -= len;
25
+ */
30
if (s->scsi_len == 0 || s->data_len == 0) {
26
if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
31
scsi_req_continue(s->req);
27
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
32
@@ -XXX,XX +XXX,XX @@ static void usb_msd_command_complete(SCSIRequest *req, uint32_t status, size_t r
28
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
33
if (s->data_len) {
29
} else {
34
int len = (p->iov.size - p->actual_length);
30
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
35
usb_packet_skip(p, len);
31
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
36
+ if (len > s->data_len) {
37
+ len = s->data_len;
38
+ }
39
s->data_len -= len;
40
}
41
if (s->data_len == 0) {
42
@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
43
int len = p->iov.size - p->actual_length;
44
if (len) {
45
usb_packet_skip(p, len);
46
+ if (len > s->data_len) {
47
+ len = s->data_len;
48
+ }
49
s->data_len -= len;
50
if (s->data_len == 0) {
51
s->mode = USB_MSDM_CSW;
52
@@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p)
53
int len = p->iov.size - p->actual_length;
54
if (len) {
55
usb_packet_skip(p, len);
56
+ if (len > s->data_len) {
57
+ len = s->data_len;
58
+ }
59
s->data_len -= len;
60
if (s->data_len == 0) {
61
s->mode = USB_MSDM_CSW;
62
}
32
}
63
}
33
}
64
}
34
nvic_irq_update(s);
65
- if (p->actual_length < p->iov.size) {
35
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
66
+ if (p->actual_length < p->iov.size && (p->short_not_ok ||
36
NVICState *s = NVIC(dev);
67
+ s->scsi_len >= p->ep->max_packet_size)) {
37
68
DPRINTF("Deferring packet %p [wait data-in]\n", p);
38
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
69
s->packet = p;
39
- s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
70
p->status = USB_RET_ASYNC;
40
/* MEM, BUS, and USAGE are enabled through
41
* the System Handler Control register
42
*/
43
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
44
45
/* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
46
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
47
+ /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
48
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
49
+ } else {
50
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
51
}
52
53
/* Strictly speaking the reset handler should be enabled.
54
--
71
--
55
2.7.4
72
2.20.1
56
73
57
74
diff view generated by jsdifflib
1
Drop the use of old_mmio in the omap2_gpio memory ops.
1
From: Paul Zimmerman <pauldzim@gmail.com>
2
2
3
Wire the dwc-hsotg (dwc2) emulation into Qemu
4
5
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
6
Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
7
Message-id: 20200520235349.21215-7-pauldzim@gmail.com
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-3-git-send-email-peter.maydell@linaro.org
6
---
9
---
7
hw/gpio/omap_gpio.c | 26 ++++++++++++--------------
10
include/hw/arm/bcm2835_peripherals.h | 3 ++-
8
1 file changed, 12 insertions(+), 14 deletions(-)
11
hw/arm/bcm2835_peripherals.c | 21 ++++++++++++++++++++-
12
2 files changed, 22 insertions(+), 2 deletions(-)
9
13
10
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
14
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
11
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/gpio/omap_gpio.c
16
--- a/include/hw/arm/bcm2835_peripherals.h
13
+++ b/hw/gpio/omap_gpio.c
17
+++ b/include/hw/arm/bcm2835_peripherals.h
14
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_write(void *opaque, hwaddr addr,
18
@@ -XXX,XX +XXX,XX @@
15
}
19
#include "hw/sd/bcm2835_sdhost.h"
20
#include "hw/gpio/bcm2835_gpio.h"
21
#include "hw/timer/bcm2835_systmr.h"
22
+#include "hw/usb/hcd-dwc2.h"
23
#include "hw/misc/unimp.h"
24
25
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
26
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
27
UnimplementedDeviceState ave0;
28
UnimplementedDeviceState bscsl;
29
UnimplementedDeviceState smi;
30
- UnimplementedDeviceState dwc2;
31
+ DWC2State dwc2;
32
UnimplementedDeviceState sdramc;
33
} BCM2835PeripheralState;
34
35
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/arm/bcm2835_peripherals.c
38
+++ b/hw/arm/bcm2835_peripherals.c
39
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
40
/* Mphi */
41
sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
42
TYPE_BCM2835_MPHI);
43
+
44
+ /* DWC2 */
45
+ sysbus_init_child_obj(obj, "dwc2", &s->dwc2, sizeof(s->dwc2),
46
+ TYPE_DWC2_USB);
47
+
48
+ object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
49
+ OBJECT(&s->gpu_bus_mr));
16
}
50
}
17
51
18
-static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
52
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
19
+static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr,
53
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
20
+ unsigned size)
54
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
21
{
55
INTERRUPT_HOSTPORT));
22
return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
56
23
}
57
+ /* DWC2 */
24
58
+ object_property_set_bool(OBJECT(&s->dwc2), true, "realized", &err);
25
static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
59
+ if (err) {
26
- uint32_t value)
60
+ error_propagate(errp, err);
27
+ uint64_t value, unsigned size)
28
{
29
uint32_t cur = 0;
30
uint32_t mask = 0xffff;
31
32
+ if (size == 4) {
33
+ omap2_gpio_module_write(opaque, addr, value);
34
+ return;
61
+ return;
35
+ }
62
+ }
36
+
63
+
37
switch (addr & ~3) {
64
+ memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET,
38
case 0x00:    /* GPIO_REVISION */
65
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0));
39
case 0x14:    /* GPIO_SYSSTATUS */
66
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0,
40
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
67
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
68
+ INTERRUPT_USB));
69
+
70
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
71
create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
72
create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
73
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
74
create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
75
create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
76
create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
77
- create_unimp(s, &s->dwc2, "dwc-usb2", USB_OTG_OFFSET, 0x1000);
78
create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
41
}
79
}
42
80
43
static const MemoryRegionOps omap2_gpio_module_ops = {
44
- .old_mmio = {
45
- .read = {
46
- omap2_gpio_module_readp,
47
- omap2_gpio_module_readp,
48
- omap2_gpio_module_read,
49
- },
50
- .write = {
51
- omap2_gpio_module_writep,
52
- omap2_gpio_module_writep,
53
- omap2_gpio_module_write,
54
- },
55
- },
56
+ .read = omap2_gpio_module_readp,
57
+ .write = omap2_gpio_module_writep,
58
+ .valid.min_access_size = 1,
59
+ .valid.max_access_size = 4,
60
.endianness = DEVICE_NATIVE_ENDIAN,
61
};
62
63
--
81
--
64
2.7.4
82
2.20.1
65
83
66
84
diff view generated by jsdifflib
1
Update the code in nvic_rettobase() so that it checks the
1
From: Paul Zimmerman <pauldzim@gmail.com>
2
sec_vectors[] array as well as the vectors[] array if needed.
3
2
3
Add a check for functional dwc-hsotg (dwc2) USB host emulation to
4
the Raspi 2 acceptance test
5
6
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
8
Message-id: 20200520235349.21215-8-pauldzim@gmail.com
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505240046-11454-7-git-send-email-peter.maydell@linaro.org
7
---
10
---
8
hw/intc/armv7m_nvic.c | 5 ++++-
11
tests/acceptance/boot_linux_console.py | 9 +++++++--
9
1 file changed, 4 insertions(+), 1 deletion(-)
12
1 file changed, 7 insertions(+), 2 deletions(-)
10
13
11
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
14
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/armv7m_nvic.c
16
--- a/tests/acceptance/boot_linux_console.py
14
+++ b/hw/intc/armv7m_nvic.c
17
+++ b/tests/acceptance/boot_linux_console.py
15
@@ -XXX,XX +XXX,XX @@ static int nvic_pending_prio(NVICState *s)
18
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
16
static bool nvic_rettobase(NVICState *s)
19
17
{
20
self.vm.set_console()
18
int irq, nhand = 0;
21
kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
19
+ bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
22
- serial_kernel_cmdline[uart_id])
20
23
+ serial_kernel_cmdline[uart_id] +
21
for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
24
+ ' root=/dev/mmcblk0p2 rootwait ' +
22
- if (s->vectors[irq].active) {
25
+ 'dwc_otg.fiq_fsm_enable=0')
23
+ if (s->vectors[irq].active ||
26
self.vm.add_args('-kernel', kernel_path,
24
+ (check_sec && irq < NVIC_INTERNAL_VECTORS &&
27
'-dtb', dtb_path,
25
+ s->sec_vectors[irq].active)) {
28
- '-append', kernel_command_line)
26
nhand++;
29
+ '-append', kernel_command_line,
27
if (nhand == 2) {
30
+ '-device', 'usb-kbd')
28
return 0;
31
self.vm.launch()
32
console_pattern = 'Kernel command line: %s' % kernel_command_line
33
self.wait_for_console_pattern(console_pattern)
34
+ console_pattern = 'Product: QEMU USB Keyboard'
35
+ self.wait_for_console_pattern(console_pattern)
36
37
def test_arm_raspi2_uart0(self):
38
"""
29
--
39
--
30
2.7.4
40
2.20.1
31
41
32
42
diff view generated by jsdifflib
1
Update the nvic_recompute_state() code to handle the security
1
Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift
2
extension and its associated banked registers.
2
group to decodetree.
3
4
Code that uses the resulting cached state (ie the irq
5
acknowledge and complete code) will be updated in a later
6
commit.
7
3
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
6
Message-id: 20200522145520.6778-2-peter.maydell@linaro.org
11
---
7
---
12
hw/intc/armv7m_nvic.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++--
8
target/arm/neon-dp.decode | 25 ++++++++++++++++++++++
13
hw/intc/trace-events | 1 +
9
target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
14
2 files changed, 147 insertions(+), 5 deletions(-)
10
target/arm/translate.c | 18 +++++++---------
11
3 files changed, 71 insertions(+), 10 deletions(-)
15
12
16
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/armv7m_nvic.c
15
--- a/target/arm/neon-dp.decode
19
+++ b/hw/intc/armv7m_nvic.c
16
+++ b/target/arm/neon-dp.decode
20
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
21
* (higher than the highest possible priority value)
18
VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
22
*/
19
VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
23
#define NVIC_NOEXC_PRIO 0x100
20
VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
24
+/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
21
+
25
+#define NVIC_NS_PRIO_LIMIT 0x80
22
+######################################################################
26
23
+# 2-reg-and-shift grouping:
27
static const uint8_t nvic_id[] = {
24
+# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
28
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
25
+######################################################################
29
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
26
+&2reg_shift vm vd q shift size
30
return false;
27
+
31
}
28
+@2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \
32
29
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=3
33
+static bool exc_is_banked(int exc)
30
+@2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \
31
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=2
32
+@2reg_shl_h .... ... . . . 01 shift:4 .... .... 0 q:1 . . .... \
33
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=1
34
+@2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \
35
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=0
36
+
37
+VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
38
+VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
39
+VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
40
+VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
41
+
42
+VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
43
+VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
44
+VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
45
+VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
46
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate-neon.inc.c
49
+++ b/target/arm/translate-neon.inc.c
50
@@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
51
DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds)
52
DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs)
53
DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins)
54
+
55
+static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
34
+{
56
+{
35
+ /* Return true if this is one of the limited set of exceptions which
57
+ /* Handle a 2-reg-shift insn which can be vectorized. */
36
+ * are banked (and thus have state in sec_vectors[])
58
+ int vec_size = a->q ? 16 : 8;
37
+ */
59
+ int rd_ofs = neon_reg_offset(a->vd, 0);
38
+ return exc == ARMV7M_EXCP_HARD ||
60
+ int rm_ofs = neon_reg_offset(a->vm, 0);
39
+ exc == ARMV7M_EXCP_MEM ||
40
+ exc == ARMV7M_EXCP_USAGE ||
41
+ exc == ARMV7M_EXCP_SVC ||
42
+ exc == ARMV7M_EXCP_PENDSV ||
43
+ exc == ARMV7M_EXCP_SYSTICK;
44
+}
45
+
61
+
46
/* Return a mask word which clears the subpriority bits from
62
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
47
* a priority value for an M-profile exception, leaving only
48
* the group priority.
49
*/
50
-static inline uint32_t nvic_gprio_mask(NVICState *s)
51
+static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
52
+{
53
+ return ~0U << (s->prigroup[secure] + 1);
54
+}
55
+
56
+static bool exc_targets_secure(NVICState *s, int exc)
57
+{
58
+ /* Return true if this non-banked exception targets Secure state. */
59
+ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
60
+ return false;
63
+ return false;
61
+ }
64
+ }
62
+
65
+
63
+ if (exc >= NVIC_FIRST_IRQ) {
66
+ /* UNDEF accesses to D16-D31 if they don't exist. */
64
+ return !s->itns[exc];
67
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
68
+ ((a->vd | a->vm) & 0x10)) {
69
+ return false;
65
+ }
70
+ }
66
+
71
+
67
+ /* Function shouldn't be called for banked exceptions. */
72
+ if ((a->vm | a->vd) & a->q) {
68
+ assert(!exc_is_banked(exc));
73
+ return false;
74
+ }
69
+
75
+
70
+ switch (exc) {
76
+ if (!vfp_access_check(s)) {
71
+ case ARMV7M_EXCP_NMI:
72
+ case ARMV7M_EXCP_BUS:
73
+ return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
74
+ case ARMV7M_EXCP_SECURE:
75
+ return true;
76
+ case ARMV7M_EXCP_DEBUG:
77
+ /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
78
+ return false;
79
+ default:
80
+ /* reset, and reserved (unused) low exception numbers.
81
+ * We'll get called by code that loops through all the exception
82
+ * numbers, but it doesn't matter what we return here as these
83
+ * non-existent exceptions will never be pended or active.
84
+ */
85
+ return true;
77
+ return true;
86
+ }
78
+ }
79
+
80
+ fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size);
81
+ return true;
87
+}
82
+}
88
+
83
+
89
+static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
84
+#define DO_2SH(INSN, FUNC) \
90
+{
85
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
91
+ /* Return the group priority for this exception, given its raw
86
+ { \
92
+ * (group-and-subgroup) priority value and whether it is targeting
87
+ return do_vector_2sh(s, a, FUNC); \
93
+ * secure state or not.
88
+ } \
94
+ */
95
+ if (rawprio < 0) {
96
+ return rawprio;
97
+ }
98
+ rawprio &= nvic_gprio_mask(s, targets_secure);
99
+ /* AIRCR.PRIS causes us to squash all NS priorities into the
100
+ * lower half of the total range
101
+ */
102
+ if (!targets_secure &&
103
+ (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
104
+ rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
105
+ }
106
+ return rawprio;
107
+}
108
+
89
+
109
+/* Recompute vectpending and exception_prio for a CPU which implements
90
+DO_2SH(VSHL, tcg_gen_gvec_shli)
110
+ * the Security extension
91
+DO_2SH(VSLI, gen_gvec_sli)
111
+ */
92
diff --git a/target/arm/translate.c b/target/arm/translate.c
112
+static void nvic_recompute_state_secure(NVICState *s)
93
index XXXXXXX..XXXXXXX 100644
113
{
94
--- a/target/arm/translate.c
114
- return ~0U << (s->prigroup[M_REG_NS] + 1);
95
+++ b/target/arm/translate.c
115
+ int i, bank;
96
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
116
+ int pend_prio = NVIC_NOEXC_PRIO;
97
if ((insn & 0x00380080) != 0) {
117
+ int active_prio = NVIC_NOEXC_PRIO;
98
/* Two registers and shift. */
118
+ int pend_irq = 0;
99
op = (insn >> 8) & 0xf;
119
+ bool pending_is_s_banked = false;
120
+
100
+
121
+ /* R_CQRV: precedence is by:
101
+ switch (op) {
122
+ * - lowest group priority; if both the same then
102
+ case 5: /* VSHL, VSLI */
123
+ * - lowest subpriority; if both the same then
103
+ return 1; /* handled by decodetree */
124
+ * - lowest exception number; if both the same (ie banked) then
104
+ default:
125
+ * - secure exception takes precedence
105
+ break;
126
+ * Compare pseudocode RawExecutionPriority.
127
+ * Annoyingly, now we have two prigroup values (for S and NS)
128
+ * we can't do the loop comparison on raw priority values.
129
+ */
130
+ for (i = 1; i < s->num_irq; i++) {
131
+ for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
132
+ VecInfo *vec;
133
+ int prio;
134
+ bool targets_secure;
135
+
136
+ if (bank == M_REG_S) {
137
+ if (!exc_is_banked(i)) {
138
+ continue;
139
+ }
140
+ vec = &s->sec_vectors[i];
141
+ targets_secure = true;
142
+ } else {
143
+ vec = &s->vectors[i];
144
+ targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
145
+ }
106
+ }
146
+
107
+
147
+ prio = exc_group_prio(s, vec->prio, targets_secure);
108
if (insn & (1 << 7)) {
148
+ if (vec->enabled && vec->pending && prio < pend_prio) {
109
/* 64-bit shift. */
149
+ pend_prio = prio;
110
if (op > 7) {
150
+ pend_irq = i;
111
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
151
+ pending_is_s_banked = (bank == M_REG_S);
112
gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
152
+ }
113
vec_size, vec_size);
153
+ if (vec->active && prio < active_prio) {
114
return 0;
154
+ active_prio = prio;
115
-
155
+ }
116
- case 5: /* VSHL, VSLI */
156
+ }
117
- if (u) { /* VSLI */
157
+ }
118
- gen_gvec_sli(size, rd_ofs, rm_ofs, shift,
158
+
119
- vec_size, vec_size);
159
+ s->vectpending_is_s_banked = pending_is_s_banked;
120
- } else { /* VSHL */
160
+ s->vectpending = pend_irq;
121
- tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
161
+ s->vectpending_prio = pend_prio;
122
- vec_size, vec_size);
162
+ s->exception_prio = active_prio;
123
- }
163
+
124
- return 0;
164
+ trace_nvic_recompute_state_secure(s->vectpending,
125
}
165
+ s->vectpending_is_s_banked,
126
166
+ s->vectpending_prio,
127
if (size == 3) {
167
+ s->exception_prio);
168
}
169
170
/* Recompute vectpending and exception_prio */
171
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
172
int active_prio = NVIC_NOEXC_PRIO;
173
int pend_irq = 0;
174
175
+ /* In theory we could write one function that handled both
176
+ * the "security extension present" and "not present"; however
177
+ * the security related changes significantly complicate the
178
+ * recomputation just by themselves and mixing both cases together
179
+ * would be even worse, so we retain a separate non-secure-only
180
+ * version for CPUs which don't implement the security extension.
181
+ */
182
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
183
+ nvic_recompute_state_secure(s);
184
+ return;
185
+ }
186
+
187
for (i = 1; i < s->num_irq; i++) {
188
VecInfo *vec = &s->vectors[i];
189
190
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
191
}
192
193
if (active_prio > 0) {
194
- active_prio &= nvic_gprio_mask(s);
195
+ active_prio &= nvic_gprio_mask(s, false);
196
}
197
198
if (pend_prio > 0) {
199
- pend_prio &= nvic_gprio_mask(s);
200
+ pend_prio &= nvic_gprio_mask(s, false);
201
}
202
203
s->vectpending = pend_irq;
204
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
205
} else if (env->v7m.primask[env->v7m.secure]) {
206
running = 0;
207
} else if (env->v7m.basepri[env->v7m.secure] > 0) {
208
- running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
209
+ running = env->v7m.basepri[env->v7m.secure] &
210
+ nvic_gprio_mask(s, env->v7m.secure);
211
} else {
212
running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
213
}
214
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/intc/trace-events
217
+++ b/hw/intc/trace-events
218
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
219
220
# hw/intc/armv7m_nvic.c
221
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
222
+nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
223
nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
224
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
225
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
226
--
128
--
227
2.7.4
129
2.20.1
228
130
229
131
diff view generated by jsdifflib
1
Make the set_prio() function take a bool indicating
1
Convert the VSHR 2-reg-shift insns to decodetree.
2
whether to pend the secure or non-secure version of a banked
2
3
interrupt, and use this to implement the correct banking
3
Note that unlike the legacy decoder, we present the right shift
4
semantics for the SHPR registers.
4
amount to the trans_ function as a positive integer.
5
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
8
Message-id: 20200522145520.6778-3-peter.maydell@linaro.org
9
---
9
---
10
hw/intc/armv7m_nvic.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-----
10
target/arm/neon-dp.decode | 25 ++++++++++++++++++++
11
hw/intc/trace-events | 2 +-
11
target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++
12
2 files changed, 88 insertions(+), 10 deletions(-)
12
target/arm/translate.c | 21 +----------------
13
3 files changed, 67 insertions(+), 20 deletions(-)
13
14
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
17
--- a/target/arm/neon-dp.decode
17
+++ b/hw/intc/armv7m_nvic.c
18
+++ b/target/arm/neon-dp.decode
18
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_raw_execution_priority(void *opaque)
19
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
19
return s->exception_prio;
20
######################################################################
21
&2reg_shift vm vd q shift size
22
23
+# Right shifts are encoded as N - shift, where N is the element size in bits.
24
+%neon_rshift_i6 16:6 !function=rsub_64
25
+%neon_rshift_i5 16:5 !function=rsub_32
26
+%neon_rshift_i4 16:4 !function=rsub_16
27
+%neon_rshift_i3 16:3 !function=rsub_8
28
+
29
+@2reg_shr_d .... ... . . . ...... .... .... 1 q:1 . . .... \
30
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
31
+@2reg_shr_s .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
32
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
33
+@2reg_shr_h .... ... . . . 01 .... .... .... 0 q:1 . . .... \
34
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
35
+@2reg_shr_b .... ... . . . 001 ... .... .... 0 q:1 . . .... \
36
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
37
+
38
@2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \
39
&2reg_shift vm=%vm_dp vd=%vd_dp size=3
40
@2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \
41
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
42
@2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \
43
&2reg_shift vm=%vm_dp vd=%vd_dp size=0
44
45
+VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
46
+VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
47
+VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
48
+VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
49
+
50
+VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
51
+VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
52
+VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
53
+VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
54
+
55
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
56
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
57
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
58
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/translate-neon.inc.c
61
+++ b/target/arm/translate-neon.inc.c
62
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
63
return x + 1;
20
}
64
}
21
65
22
-/* caller must call nvic_irq_update() after this */
66
+static inline int rsub_64(DisasContext *s, int x)
23
-static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
67
+{
24
+/* caller must call nvic_irq_update() after this.
68
+ return 64 - x;
25
+ * secure indicates the bank to use for banked exceptions (we assert if
26
+ * we are passed secure=true for a non-banked exception).
27
+ */
28
+static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
29
{
30
assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
31
assert(irq < s->num_irq);
32
33
- s->vectors[irq].prio = prio;
34
+ if (secure) {
35
+ assert(exc_is_banked(irq));
36
+ s->sec_vectors[irq].prio = prio;
37
+ } else {
38
+ s->vectors[irq].prio = prio;
39
+ }
40
+
41
+ trace_nvic_set_prio(irq, secure, prio);
42
+}
69
+}
43
+
70
+
44
+/* Return the current raw priority register value.
71
+static inline int rsub_32(DisasContext *s, int x)
45
+ * secure indicates the bank to use for banked exceptions (we assert if
46
+ * we are passed secure=true for a non-banked exception).
47
+ */
48
+static int get_prio(NVICState *s, unsigned irq, bool secure)
49
+{
72
+{
50
+ assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
73
+ return 32 - x;
51
+ assert(irq < s->num_irq);
74
+}
52
75
+static inline int rsub_16(DisasContext *s, int x)
53
- trace_nvic_set_prio(irq, prio);
76
+{
54
+ if (secure) {
77
+ return 16 - x;
55
+ assert(exc_is_banked(irq));
78
+}
56
+ return s->sec_vectors[irq].prio;
79
+static inline int rsub_8(DisasContext *s, int x)
80
+{
81
+ return 8 - x;
82
+}
83
+
84
/* Include the generated Neon decoder */
85
#include "decode-neon-dp.inc.c"
86
#include "decode-neon-ls.inc.c"
87
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
88
89
DO_2SH(VSHL, tcg_gen_gvec_shli)
90
DO_2SH(VSLI, gen_gvec_sli)
91
+
92
+static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
93
+{
94
+ /* Signed shift out of range results in all-sign-bits */
95
+ a->shift = MIN(a->shift, (8 << a->size) - 1);
96
+ return do_vector_2sh(s, a, tcg_gen_gvec_sari);
97
+}
98
+
99
+static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
100
+ int64_t shift, uint32_t oprsz, uint32_t maxsz)
101
+{
102
+ tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0);
103
+}
104
+
105
+static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
106
+{
107
+ /* Shift out of range is architecturally valid and results in zero. */
108
+ if (a->shift >= (8 << a->size)) {
109
+ return do_vector_2sh(s, a, gen_zero_rd_2sh);
57
+ } else {
110
+ } else {
58
+ return s->vectors[irq].prio;
111
+ return do_vector_2sh(s, a, tcg_gen_gvec_shri);
59
+ }
60
}
61
62
/* Recompute state and assert irq line accordingly.
63
@@ -XXX,XX +XXX,XX @@ static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
64
}
65
}
66
67
+static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs)
68
+{
69
+ /* Behaviour for the SHPR register field for this exception:
70
+ * return M_REG_NS to use the nonsecure vector (including for
71
+ * non-banked exceptions), M_REG_S for the secure version of
72
+ * a banked exception, and -1 if this field should RAZ/WI.
73
+ */
74
+ switch (exc) {
75
+ case ARMV7M_EXCP_MEM:
76
+ case ARMV7M_EXCP_USAGE:
77
+ case ARMV7M_EXCP_SVC:
78
+ case ARMV7M_EXCP_PENDSV:
79
+ case ARMV7M_EXCP_SYSTICK:
80
+ /* Banked exceptions */
81
+ return attrs.secure;
82
+ case ARMV7M_EXCP_BUS:
83
+ /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
84
+ if (!attrs.secure &&
85
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
86
+ return -1;
87
+ }
88
+ return M_REG_NS;
89
+ case ARMV7M_EXCP_SECURE:
90
+ /* Not banked, RAZ/WI from nonsecure */
91
+ if (!attrs.secure) {
92
+ return -1;
93
+ }
94
+ return M_REG_NS;
95
+ case ARMV7M_EXCP_DEBUG:
96
+ /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
97
+ return M_REG_NS;
98
+ case 8 ... 10:
99
+ case 13:
100
+ /* RES0 */
101
+ return -1;
102
+ default:
103
+ /* Not reachable due to decode of SHPR register addresses */
104
+ g_assert_not_reached();
105
+ }
112
+ }
106
+}
113
+}
107
+
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
108
static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
109
uint64_t *data, unsigned size,
110
MemTxAttrs attrs)
111
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
112
}
113
}
114
break;
115
- case 0xd18 ... 0xd23: /* System Handler Priority. */
116
+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
117
val = 0;
118
for (i = 0; i < size; i++) {
119
- val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
120
+ unsigned hdlidx = (offset - 0xd14) + i;
121
+ int sbank = shpr_bank(s, hdlidx, attrs);
122
+
123
+ if (sbank < 0) {
124
+ continue;
125
+ }
126
+ val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
127
}
128
break;
129
case 0xfe0 ... 0xfff: /* ID. */
130
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
131
132
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
133
if (attrs.secure || s->itns[startvec + i]) {
134
- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
135
+ set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff);
136
}
137
}
138
nvic_irq_update(s);
139
return MEMTX_OK;
140
- case 0xd18 ... 0xd23: /* System Handler Priority. */
141
+ case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
142
for (i = 0; i < size; i++) {
143
unsigned hdlidx = (offset - 0xd14) + i;
144
- set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
145
+ int newprio = extract32(value, i * 8, 8);
146
+ int sbank = shpr_bank(s, hdlidx, attrs);
147
+
148
+ if (sbank < 0) {
149
+ continue;
150
+ }
151
+ set_prio(s, hdlidx, sbank, newprio);
152
}
153
nvic_irq_update(s);
154
return MEMTX_OK;
155
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
156
index XXXXXXX..XXXXXXX 100644
115
index XXXXXXX..XXXXXXX 100644
157
--- a/hw/intc/trace-events
116
--- a/target/arm/translate.c
158
+++ b/hw/intc/trace-events
117
+++ b/target/arm/translate.c
159
@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S
118
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
160
# hw/intc/armv7m_nvic.c
119
op = (insn >> 8) & 0xf;
161
nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"
120
162
nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"
121
switch (op) {
163
-nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
122
+ case 0: /* VSHR */
164
+nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
123
case 5: /* VSHL, VSLI */
165
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
124
return 1; /* handled by decodetree */
166
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
125
default:
167
nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
126
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
127
}
128
129
switch (op) {
130
- case 0: /* VSHR */
131
- /* Right shift comes here negative. */
132
- shift = -shift;
133
- /* Shifts larger than the element size are architecturally
134
- * valid. Unsigned results in all zeros; signed results
135
- * in all sign bits.
136
- */
137
- if (!u) {
138
- tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
139
- MIN(shift, (8 << size) - 1),
140
- vec_size, vec_size);
141
- } else if (shift >= 8 << size) {
142
- tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size,
143
- vec_size, 0);
144
- } else {
145
- tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
146
- vec_size, vec_size);
147
- }
148
- return 0;
149
-
150
case 1: /* VSRA */
151
/* Right shift comes here negative. */
152
shift = -shift;
168
--
153
--
169
2.7.4
154
2.20.1
170
155
171
156
diff view generated by jsdifflib
1
The Application Interrupt and Reset Control Register has some changes
1
Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree.
2
for v8M:
2
(These are the last instructions in the group that are vectorized;
3
* new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
3
the rest all require looping over each element.)
4
real state if the security extension is implemented and otherwise
5
are constant
6
* the PRIGROUP field is banked between security states
7
* non-secure code can be blocked from using the SYSRESET bit
8
to reset the system if SYSRESETREQS is set
9
10
Implement the new state and the changes to register read and write.
11
For the moment we ignore the effects of the secure PRIGROUP.
12
We will implement the effects of PRIS and BFHFNMIS later.
13
4
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
7
Message-id: 20200522145520.6778-4-peter.maydell@linaro.org
17
---
8
---
18
include/hw/intc/armv7m_nvic.h | 3 ++-
9
target/arm/neon-dp.decode | 35 ++++++++++++++++++++++
19
target/arm/cpu.h | 12 +++++++++++
10
target/arm/translate-neon.inc.c | 7 +++++
20
hw/intc/armv7m_nvic.c | 49 +++++++++++++++++++++++++++++++++----------
11
target/arm/translate.c | 52 +++------------------------------
21
target/arm/cpu.c | 7 +++++++
12
3 files changed, 46 insertions(+), 48 deletions(-)
22
4 files changed, 59 insertions(+), 12 deletions(-)
23
13
24
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
14
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/intc/armv7m_nvic.h
16
--- a/target/arm/neon-dp.decode
27
+++ b/include/hw/intc/armv7m_nvic.h
17
+++ b/target/arm/neon-dp.decode
28
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
18
@@ -XXX,XX +XXX,XX @@ VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
29
* Entries in sec_vectors[] for non-banked exception numbers are unused.
19
VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
30
*/
20
VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
31
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
21
32
- uint32_t prigroup;
22
+VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
33
+ /* The PRIGROUP field in AIRCR is banked */
23
+VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
34
+ uint32_t prigroup[M_REG_NUM_BANKS];
24
+VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
35
25
+VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
36
/* The following fields are all cached state that can be recalculated
26
+
37
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
27
+VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
38
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
28
+VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
29
+VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
30
+VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
31
+
32
+VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
33
+VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
34
+VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
35
+VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
36
+
37
+VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
38
+VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
39
+VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
40
+VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
41
+
42
+VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
43
+VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
44
+VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
45
+VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
46
+
47
+VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
48
+VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
49
+VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
50
+VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
51
+
52
+VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
53
+VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
54
+VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
55
+VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
56
+
57
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
58
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
59
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
60
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
39
index XXXXXXX..XXXXXXX 100644
61
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu.h
62
--- a/target/arm/translate-neon.inc.c
41
+++ b/target/arm/cpu.h
63
+++ b/target/arm/translate-neon.inc.c
42
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
64
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
43
int exception;
65
44
uint32_t primask[M_REG_NUM_BANKS];
66
DO_2SH(VSHL, tcg_gen_gvec_shli)
45
uint32_t faultmask[M_REG_NUM_BANKS];
67
DO_2SH(VSLI, gen_gvec_sli)
46
+ uint32_t aircr; /* only holds r/w state if security extn implemented */
68
+DO_2SH(VSRI, gen_gvec_sri)
47
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
69
+DO_2SH(VSRA_S, gen_gvec_ssra)
48
} v7m;
70
+DO_2SH(VSRA_U, gen_gvec_usra)
49
71
+DO_2SH(VRSHR_S, gen_gvec_srshr)
50
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKALIGN, 9, 1)
72
+DO_2SH(VRSHR_U, gen_gvec_urshr)
51
FIELD(V7M_CCR, DC, 16, 1)
73
+DO_2SH(VRSRA_S, gen_gvec_srsra)
52
FIELD(V7M_CCR, IC, 17, 1)
74
+DO_2SH(VRSRA_U, gen_gvec_ursra)
53
75
54
+/* V7M AIRCR bits */
76
static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
55
+FIELD(V7M_AIRCR, VECTRESET, 0, 1)
77
{
56
+FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
78
diff --git a/target/arm/translate.c b/target/arm/translate.c
57
+FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
58
+FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
59
+FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
60
+FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
61
+FIELD(V7M_AIRCR, PRIS, 14, 1)
62
+FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
63
+FIELD(V7M_AIRCR, VECTKEY, 16, 16)
64
+
65
/* V7M CFSR bits for MMFSR */
66
FIELD(V7M_CFSR, IACCVIOL, 0, 1)
67
FIELD(V7M_CFSR, DACCVIOL, 1, 1)
68
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
69
index XXXXXXX..XXXXXXX 100644
79
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/intc/armv7m_nvic.c
80
--- a/target/arm/translate.c
71
+++ b/hw/intc/armv7m_nvic.c
81
+++ b/target/arm/translate.c
72
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
82
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
73
*/
83
74
static inline uint32_t nvic_gprio_mask(NVICState *s)
84
switch (op) {
75
{
85
case 0: /* VSHR */
76
- return ~0U << (s->prigroup + 1);
86
+ case 1: /* VSRA */
77
+ return ~0U << (s->prigroup[M_REG_NS] + 1);
87
+ case 2: /* VRSHR */
78
}
88
+ case 3: /* VRSRA */
79
89
+ case 4: /* VSRI */
80
/* Recompute vectpending and exception_prio */
90
case 5: /* VSHL, VSLI */
81
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
91
return 1; /* handled by decodetree */
82
return val;
92
default:
83
case 0xd08: /* Vector Table Offset. */
93
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
84
return cpu->env.v7m.vecbase[attrs.secure];
94
shift = shift - (1 << (size + 3));
85
- case 0xd0c: /* Application Interrupt/Reset Control. */
95
}
86
- return 0xfa050000 | (s->prigroup << 8);
96
87
+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
97
- switch (op) {
88
+ val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);
98
- case 1: /* VSRA */
89
+ if (attrs.secure) {
99
- /* Right shift comes here negative. */
90
+ /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
100
- shift = -shift;
91
+ val |= cpu->env.v7m.aircr;
101
- if (u) {
92
+ } else {
102
- gen_gvec_usra(size, rd_ofs, rm_ofs, shift,
93
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
103
- vec_size, vec_size);
94
+ /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
104
- } else {
95
+ * security isn't supported then BFHFNMINS is RAO (and
105
- gen_gvec_ssra(size, rd_ofs, rm_ofs, shift,
96
+ * the bit in env.v7m.aircr is always set).
106
- vec_size, vec_size);
97
+ */
107
- }
98
+ val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;
108
- return 0;
99
+ }
109
-
100
+ }
110
- case 2: /* VRSHR */
101
+ return val;
111
- /* Right shift comes here negative. */
102
case 0xd10: /* System Control. */
112
- shift = -shift;
103
/* TODO: Implement SLEEPONEXIT. */
113
- if (u) {
104
return 0;
114
- gen_gvec_urshr(size, rd_ofs, rm_ofs, shift,
105
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
115
- vec_size, vec_size);
106
case 0xd08: /* Vector Table Offset. */
116
- } else {
107
cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
117
- gen_gvec_srshr(size, rd_ofs, rm_ofs, shift,
108
break;
118
- vec_size, vec_size);
109
- case 0xd0c: /* Application Interrupt/Reset Control. */
119
- }
110
- if ((value >> 16) == 0x05fa) {
120
- return 0;
111
- if (value & 4) {
121
-
112
- qemu_irq_pulse(s->sysresetreq);
122
- case 3: /* VRSRA */
113
+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
123
- /* Right shift comes here negative. */
114
+ if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {
124
- shift = -shift;
115
+ if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
125
- if (u) {
116
+ if (attrs.secure ||
126
- gen_gvec_ursra(size, rd_ofs, rm_ofs, shift,
117
+ !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
127
- vec_size, vec_size);
118
+ qemu_irq_pulse(s->sysresetreq);
128
- } else {
119
+ }
129
- gen_gvec_srsra(size, rd_ofs, rm_ofs, shift,
120
}
130
- vec_size, vec_size);
121
- if (value & 2) {
131
- }
122
+ if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
132
- return 0;
123
qemu_log_mask(LOG_GUEST_ERROR,
133
-
124
"Setting VECTCLRACTIVE when not in DEBUG mode "
134
- case 4: /* VSRI */
125
"is UNPREDICTABLE\n");
135
- if (!u) {
126
}
136
- return 1;
127
- if (value & 1) {
137
- }
128
+ if (value & R_V7M_AIRCR_VECTRESET_MASK) {
138
- /* Right shift comes here negative. */
129
+ /* NB: this bit is RES0 in v8M */
139
- shift = -shift;
130
qemu_log_mask(LOG_GUEST_ERROR,
140
- gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
131
"Setting VECTRESET when not in DEBUG mode "
141
- vec_size, vec_size);
132
"is UNPREDICTABLE\n");
142
- return 0;
133
}
143
- }
134
- s->prigroup = extract32(value, 8, 3);
144
-
135
+ s->prigroup[attrs.secure] = extract32(value,
145
if (size == 3) {
136
+ R_V7M_AIRCR_PRIGROUP_SHIFT,
146
count = q + 1;
137
+ R_V7M_AIRCR_PRIGROUP_LENGTH);
147
} else {
138
+ if (attrs.secure) {
139
+ /* These bits are only writable by secure */
140
+ cpu->env.v7m.aircr = value &
141
+ (R_V7M_AIRCR_SYSRESETREQS_MASK |
142
+ R_V7M_AIRCR_BFHFNMINS_MASK |
143
+ R_V7M_AIRCR_PRIS_MASK);
144
+ }
145
nvic_irq_update(s);
146
}
147
break;
148
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic_security = {
149
.fields = (VMStateField[]) {
150
VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,
151
vmstate_VecInfo, VecInfo),
152
+ VMSTATE_UINT32(prigroup[M_REG_S], NVICState),
153
VMSTATE_END_OF_LIST()
154
}
155
};
156
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_nvic = {
157
.fields = (VMStateField[]) {
158
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
159
vmstate_VecInfo, VecInfo),
160
- VMSTATE_UINT32(prigroup, NVICState),
161
+ VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),
162
VMSTATE_END_OF_LIST()
163
},
164
.subsections = (const VMStateDescription*[]) {
165
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
166
index XXXXXXX..XXXXXXX 100644
167
--- a/target/arm/cpu.c
168
+++ b/target/arm/cpu.c
169
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
170
171
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
172
env->v7m.secure = true;
173
+ } else {
174
+ /* This bit resets to 0 if security is supported, but 1 if
175
+ * it is not. The bit is not present in v7M, but we set it
176
+ * here so we can avoid having to make checks on it conditional
177
+ * on ARM_FEATURE_V8 (we don't let the guest see the bit).
178
+ */
179
+ env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
180
}
181
182
/* In v7M the reset value of this bit is IMPDEF, but ARM recommends
183
--
148
--
184
2.7.4
149
2.20.1
185
150
186
151
diff view generated by jsdifflib
1
Don't use old_mmio in the memory region ops struct.
1
Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree.
2
These are the last of the simple shift-by-immediate insns.
2
3
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-6-git-send-email-peter.maydell@linaro.org
6
Message-id: 20200522145520.6778-5-peter.maydell@linaro.org
6
---
7
---
7
hw/i2c/omap_i2c.c | 44 ++++++++++++++++++++++++++++++++------------
8
target/arm/neon-dp.decode | 15 +++++
8
1 file changed, 32 insertions(+), 12 deletions(-)
9
target/arm/translate-neon.inc.c | 108 +++++++++++++++++++++++++++++++
9
10
target/arm/translate.c | 110 +-------------------------------
10
diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
11
3 files changed, 126 insertions(+), 107 deletions(-)
12
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
11
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/i2c/omap_i2c.c
15
--- a/target/arm/neon-dp.decode
13
+++ b/hw/i2c/omap_i2c.c
16
+++ b/target/arm/neon-dp.decode
14
@@ -XXX,XX +XXX,XX @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
17
@@ -XXX,XX +XXX,XX @@ VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
18
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
19
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
20
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
21
+
22
+VQSHLU_64_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
23
+VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
24
+VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
25
+VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
26
+
27
+VQSHL_S_64_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
28
+VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
29
+VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
30
+VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
31
+
32
+VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
33
+VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
34
+VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
35
+VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
36
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/translate-neon.inc.c
39
+++ b/target/arm/translate-neon.inc.c
40
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
41
return do_vector_2sh(s, a, tcg_gen_gvec_shri);
15
}
42
}
16
}
43
}
17
44
+
18
+static uint64_t omap_i2c_readfn(void *opaque, hwaddr addr,
45
+static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
19
+ unsigned size)
46
+ NeonGenTwo64OpEnvFn *fn)
20
+{
47
+{
21
+ switch (size) {
48
+ /*
22
+ case 2:
49
+ * 2-reg-and-shift operations, size == 3 case, where the
23
+ return omap_i2c_read(opaque, addr);
50
+ * function needs to be passed cpu_env.
24
+ default:
51
+ */
25
+ return omap_badwidth_read16(opaque, addr);
52
+ TCGv_i64 constimm;
26
+ }
53
+ int pass;
54
+
55
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
56
+ return false;
57
+ }
58
+
59
+ /* UNDEF accesses to D16-D31 if they don't exist. */
60
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
61
+ ((a->vd | a->vm) & 0x10)) {
62
+ return false;
63
+ }
64
+
65
+ if ((a->vm | a->vd) & a->q) {
66
+ return false;
67
+ }
68
+
69
+ if (!vfp_access_check(s)) {
70
+ return true;
71
+ }
72
+
73
+ /*
74
+ * To avoid excessive duplication of ops we implement shift
75
+ * by immediate using the variable shift operations.
76
+ */
77
+ constimm = tcg_const_i64(dup_const(a->size, a->shift));
78
+
79
+ for (pass = 0; pass < a->q + 1; pass++) {
80
+ TCGv_i64 tmp = tcg_temp_new_i64();
81
+
82
+ neon_load_reg64(tmp, a->vm + pass);
83
+ fn(tmp, cpu_env, tmp, constimm);
84
+ neon_store_reg64(tmp, a->vd + pass);
85
+ }
86
+ tcg_temp_free_i64(constimm);
87
+ return true;
27
+}
88
+}
28
+
89
+
29
+static void omap_i2c_writefn(void *opaque, hwaddr addr,
90
+static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
30
+ uint64_t value, unsigned size)
91
+ NeonGenTwoOpEnvFn *fn)
31
+{
92
+{
32
+ switch (size) {
93
+ /*
33
+ case 1:
94
+ * 2-reg-and-shift operations, size < 3 case, where the
34
+ /* Only the last fifo write can be 8 bit. */
95
+ * helper needs to be passed cpu_env.
35
+ omap_i2c_writeb(opaque, addr, value);
96
+ */
36
+ break;
97
+ TCGv_i32 constimm;
37
+ case 2:
98
+ int pass;
38
+ omap_i2c_write(opaque, addr, value);
99
+
39
+ break;
100
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
40
+ default:
101
+ return false;
41
+ omap_badwidth_write16(opaque, addr, value);
102
+ }
42
+ break;
103
+
43
+ }
104
+ /* UNDEF accesses to D16-D31 if they don't exist. */
105
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
106
+ ((a->vd | a->vm) & 0x10)) {
107
+ return false;
108
+ }
109
+
110
+ if ((a->vm | a->vd) & a->q) {
111
+ return false;
112
+ }
113
+
114
+ if (!vfp_access_check(s)) {
115
+ return true;
116
+ }
117
+
118
+ /*
119
+ * To avoid excessive duplication of ops we implement shift
120
+ * by immediate using the variable shift operations.
121
+ */
122
+ constimm = tcg_const_i32(dup_const(a->size, a->shift));
123
+
124
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
125
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
126
+ fn(tmp, cpu_env, tmp, constimm);
127
+ neon_store_reg(a->vd, pass, tmp);
128
+ }
129
+ tcg_temp_free_i32(constimm);
130
+ return true;
44
+}
131
+}
45
+
132
+
46
static const MemoryRegionOps omap_i2c_ops = {
133
+#define DO_2SHIFT_ENV(INSN, FUNC) \
47
- .old_mmio = {
134
+ static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \
48
- .read = {
135
+ { \
49
- omap_badwidth_read16,
136
+ return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \
50
- omap_i2c_read,
137
+ } \
51
- omap_badwidth_read16,
138
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
52
- },
139
+ { \
53
- .write = {
140
+ static NeonGenTwoOpEnvFn * const fns[] = { \
54
- omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
141
+ gen_helper_neon_##FUNC##8, \
55
- omap_i2c_write,
142
+ gen_helper_neon_##FUNC##16, \
56
- omap_badwidth_write16,
143
+ gen_helper_neon_##FUNC##32, \
57
- },
144
+ }; \
58
- },
145
+ assert(a->size < ARRAY_SIZE(fns)); \
59
+ .read = omap_i2c_readfn,
146
+ return do_2shift_env_32(s, a, fns[a->size]); \
60
+ .write = omap_i2c_writefn,
147
+ }
61
+ .valid.min_access_size = 1,
148
+
62
+ .valid.max_access_size = 4,
149
+DO_2SHIFT_ENV(VQSHLU, qshlu_s)
63
.endianness = DEVICE_NATIVE_ENDIAN,
150
+DO_2SHIFT_ENV(VQSHL_U, qshl_u)
64
};
151
+DO_2SHIFT_ENV(VQSHL_S, qshl_s)
65
152
diff --git a/target/arm/translate.c b/target/arm/translate.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/target/arm/translate.c
155
+++ b/target/arm/translate.c
156
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
157
}
158
}
159
160
-#define GEN_NEON_INTEGER_OP_ENV(name) do { \
161
- switch ((size << 1) | u) { \
162
- case 0: \
163
- gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
164
- break; \
165
- case 1: \
166
- gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
167
- break; \
168
- case 2: \
169
- gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
170
- break; \
171
- case 3: \
172
- gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
173
- break; \
174
- case 4: \
175
- gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
176
- break; \
177
- case 5: \
178
- gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
179
- break; \
180
- default: return 1; \
181
- }} while (0)
182
-
183
static TCGv_i32 neon_load_scratch(int scratch)
184
{
185
TCGv_i32 tmp = tcg_temp_new_i32();
186
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
187
int size;
188
int shift;
189
int pass;
190
- int count;
191
int u;
192
int vec_size;
193
uint32_t imm;
194
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
195
case 3: /* VRSRA */
196
case 4: /* VSRI */
197
case 5: /* VSHL, VSLI */
198
+ case 6: /* VQSHLU */
199
+ case 7: /* VQSHL */
200
return 1; /* handled by decodetree */
201
default:
202
break;
203
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
204
size--;
205
}
206
shift = (insn >> 16) & ((1 << (3 + size)) - 1);
207
- if (op < 8) {
208
- /* Shift by immediate:
209
- VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
210
- if (q && ((rd | rm) & 1)) {
211
- return 1;
212
- }
213
- if (!u && (op == 4 || op == 6)) {
214
- return 1;
215
- }
216
- /* Right shifts are encoded as N - shift, where N is the
217
- element size in bits. */
218
- if (op <= 4) {
219
- shift = shift - (1 << (size + 3));
220
- }
221
-
222
- if (size == 3) {
223
- count = q + 1;
224
- } else {
225
- count = q ? 4: 2;
226
- }
227
-
228
- /* To avoid excessive duplication of ops we implement shift
229
- * by immediate using the variable shift operations.
230
- */
231
- imm = dup_const(size, shift);
232
-
233
- for (pass = 0; pass < count; pass++) {
234
- if (size == 3) {
235
- neon_load_reg64(cpu_V0, rm + pass);
236
- tcg_gen_movi_i64(cpu_V1, imm);
237
- switch (op) {
238
- case 6: /* VQSHLU */
239
- gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
240
- cpu_V0, cpu_V1);
241
- break;
242
- case 7: /* VQSHL */
243
- if (u) {
244
- gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
245
- cpu_V0, cpu_V1);
246
- } else {
247
- gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
248
- cpu_V0, cpu_V1);
249
- }
250
- break;
251
- default:
252
- g_assert_not_reached();
253
- }
254
- neon_store_reg64(cpu_V0, rd + pass);
255
- } else { /* size < 3 */
256
- /* Operands in T0 and T1. */
257
- tmp = neon_load_reg(rm, pass);
258
- tmp2 = tcg_temp_new_i32();
259
- tcg_gen_movi_i32(tmp2, imm);
260
- switch (op) {
261
- case 6: /* VQSHLU */
262
- switch (size) {
263
- case 0:
264
- gen_helper_neon_qshlu_s8(tmp, cpu_env,
265
- tmp, tmp2);
266
- break;
267
- case 1:
268
- gen_helper_neon_qshlu_s16(tmp, cpu_env,
269
- tmp, tmp2);
270
- break;
271
- case 2:
272
- gen_helper_neon_qshlu_s32(tmp, cpu_env,
273
- tmp, tmp2);
274
- break;
275
- default:
276
- abort();
277
- }
278
- break;
279
- case 7: /* VQSHL */
280
- GEN_NEON_INTEGER_OP_ENV(qshl);
281
- break;
282
- default:
283
- g_assert_not_reached();
284
- }
285
- tcg_temp_free_i32(tmp2);
286
- neon_store_reg(rd, pass, tmp);
287
- }
288
- } /* for pass */
289
- } else if (op < 10) {
290
+ if (op < 10) {
291
/* Shift by immediate and narrow:
292
VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
293
int input_unsigned = (op == 8) ? !u : u;
66
--
294
--
67
2.7.4
295
2.20.1
68
296
69
297
diff view generated by jsdifflib
1
Now that we have a banked FAULTMASK register and banked exceptions,
1
Convert the Neon narrowing shifts where op==8 to decodetree:
2
we can implement the correct check in cpu_mmu_index() for whether
2
* VSHRN
3
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
3
* VRSHRN
4
handlers which have requested a negative execution priority to run
4
* VQSHRUN
5
with the MPU disabled. In v8M the test has to check this for the
5
* VQRSHRUN
6
current security state and so takes account of banking.
7
6
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
9
Message-id: 20200522145520.6778-6-peter.maydell@linaro.org
11
---
10
---
12
target/arm/cpu.h | 21 ++++++++++++++++-----
11
target/arm/neon-dp.decode | 27 ++++++
13
hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++++++
12
target/arm/translate-neon.inc.c | 167 ++++++++++++++++++++++++++++++++
14
2 files changed, 45 insertions(+), 5 deletions(-)
13
target/arm/translate.c | 1 +
15
14
3 files changed, 195 insertions(+)
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
16
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
18
--- a/target/arm/neon-dp.decode
19
+++ b/target/arm/cpu.h
19
+++ b/target/arm/neon-dp.decode
20
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq);
20
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
21
* (v8M ARM ARM I_PKLD.)
21
@2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \
22
*/
22
&2reg_shift vm=%vm_dp vd=%vd_dp size=0
23
int armv7m_nvic_raw_execution_priority(void *opaque);
23
24
+/**
24
+# Narrowing right shifts: here the Q bit is part of the opcode decode
25
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
25
+@2reg_shrn_d .... ... . . . 1 ..... .... .... 0 . . . .... \
26
+ * priority is negative for the specified security state.
26
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
27
+ * @opaque: the NVIC
27
+ shift=%neon_rshift_i5
28
+ * @secure: the security state to test
28
+@2reg_shrn_s .... ... . . . 01 .... .... .... 0 . . . .... \
29
+ * This corresponds to the pseudocode IsReqExecPriNeg().
29
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
30
+ */
30
+ shift=%neon_rshift_i4
31
+#ifndef CONFIG_USER_ONLY
31
+@2reg_shrn_h .... ... . . . 001 ... .... .... 0 . . . .... \
32
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
32
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
33
+#else
33
+ shift=%neon_rshift_i3
34
+static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
34
+
35
+{
35
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
36
+ return false;
36
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
37
+}
37
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
38
+#endif
38
@@ -XXX,XX +XXX,XX @@ VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
39
39
VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
40
/* Interface for defining coprocessor registers.
40
VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
41
* Registers are defined in tables of arm_cp_reginfo structs
41
VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
42
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
42
+
43
if (arm_feature(env, ARM_FEATURE_M)) {
43
+VSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
44
ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
44
+VSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
45
45
+VSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
46
- /* Execution priority is negative if FAULTMASK is set or
46
+
47
- * we're in a HardFault or NMI handler.
47
+VRSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
48
- */
48
+VRSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
49
- if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
49
+VRSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
50
- || env->v7m.faultmask[env->v7m.secure]) {
50
+
51
+ if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {
51
+VQSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
52
mmu_idx = ARMMMUIdx_MNegPri;
52
+VQSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
53
}
53
+VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
54
54
+
55
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
55
+VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
56
+VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
57
+VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
58
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
56
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/intc/armv7m_nvic.c
60
--- a/target/arm/translate-neon.inc.c
58
+++ b/hw/intc/armv7m_nvic.c
61
+++ b/target/arm/translate-neon.inc.c
59
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
62
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
60
return MIN(running, s->exception_prio);
63
DO_2SHIFT_ENV(VQSHLU, qshlu_s)
61
}
64
DO_2SHIFT_ENV(VQSHL_U, qshl_u)
62
65
DO_2SHIFT_ENV(VQSHL_S, qshl_s)
63
+bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
66
+
64
+{
67
+static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
65
+ /* Return true if the requested execution priority is negative
68
+ NeonGenTwo64OpFn *shiftfn,
66
+ * for the specified security state, ie that security state
69
+ NeonGenNarrowEnvFn *narrowfn)
67
+ * has an active NMI or HardFault or has set its FAULTMASK.
70
+{
68
+ * Note that this is not the same as whether the execution
71
+ /* 2-reg-and-shift narrowing-shift operations, size == 3 case */
69
+ * priority is actually negative (for instance AIRCR.PRIS may
72
+ TCGv_i64 constimm, rm1, rm2;
70
+ * mean we don't allow FAULTMASK_NS to actually make the execution
73
+ TCGv_i32 rd;
71
+ * priority negative). Compare pseudocode IsReqExcPriNeg().
74
+
75
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
76
+ return false;
77
+ }
78
+
79
+ /* UNDEF accesses to D16-D31 if they don't exist. */
80
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
81
+ ((a->vd | a->vm) & 0x10)) {
82
+ return false;
83
+ }
84
+
85
+ if (a->vm & 1) {
86
+ return false;
87
+ }
88
+
89
+ if (!vfp_access_check(s)) {
90
+ return true;
91
+ }
92
+
93
+ /*
94
+ * This is always a right shift, and the shiftfn is always a
95
+ * left-shift helper, which thus needs the negated shift count.
72
+ */
96
+ */
73
+ NVICState *s = opaque;
97
+ constimm = tcg_const_i64(-a->shift);
74
+
98
+ rm1 = tcg_temp_new_i64();
75
+ if (s->cpu->env.v7m.faultmask[secure]) {
99
+ rm2 = tcg_temp_new_i64();
100
+
101
+ /* Load both inputs first to avoid potential overwrite if rm == rd */
102
+ neon_load_reg64(rm1, a->vm);
103
+ neon_load_reg64(rm2, a->vm + 1);
104
+
105
+ shiftfn(rm1, rm1, constimm);
106
+ rd = tcg_temp_new_i32();
107
+ narrowfn(rd, cpu_env, rm1);
108
+ neon_store_reg(a->vd, 0, rd);
109
+
110
+ shiftfn(rm2, rm2, constimm);
111
+ rd = tcg_temp_new_i32();
112
+ narrowfn(rd, cpu_env, rm2);
113
+ neon_store_reg(a->vd, 1, rd);
114
+
115
+ tcg_temp_free_i64(rm1);
116
+ tcg_temp_free_i64(rm2);
117
+ tcg_temp_free_i64(constimm);
118
+
119
+ return true;
120
+}
121
+
122
+static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
123
+ NeonGenTwoOpFn *shiftfn,
124
+ NeonGenNarrowEnvFn *narrowfn)
125
+{
126
+ /* 2-reg-and-shift narrowing-shift operations, size < 3 case */
127
+ TCGv_i32 constimm, rm1, rm2, rm3, rm4;
128
+ TCGv_i64 rtmp;
129
+ uint32_t imm;
130
+
131
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
132
+ return false;
133
+ }
134
+
135
+ /* UNDEF accesses to D16-D31 if they don't exist. */
136
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
137
+ ((a->vd | a->vm) & 0x10)) {
138
+ return false;
139
+ }
140
+
141
+ if (a->vm & 1) {
142
+ return false;
143
+ }
144
+
145
+ if (!vfp_access_check(s)) {
76
+ return true;
146
+ return true;
77
+ }
147
+ }
78
+
148
+
79
+ if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
149
+ /*
80
+ s->vectors[ARMV7M_EXCP_HARD].active) {
150
+ * This is always a right shift, and the shiftfn is always a
81
+ return true;
151
+ * left-shift helper, which thus needs the negated shift count
82
+ }
152
+ * duplicated into each lane of the immediate value.
83
+
153
+ */
84
+ if (s->vectors[ARMV7M_EXCP_NMI].active &&
154
+ if (a->size == 1) {
85
+ exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
155
+ imm = (uint16_t)(-a->shift);
86
+ return true;
156
+ imm |= imm << 16;
87
+ }
157
+ } else {
88
+
158
+ /* size == 2 */
89
+ return false;
159
+ imm = -a->shift;
90
+}
160
+ }
91
+
161
+ constimm = tcg_const_i32(imm);
92
bool armv7m_nvic_can_take_pending_exception(void *opaque)
162
+
93
{
163
+ /* Load all inputs first to avoid potential overwrite */
94
NVICState *s = opaque;
164
+ rm1 = neon_load_reg(a->vm, 0);
165
+ rm2 = neon_load_reg(a->vm, 1);
166
+ rm3 = neon_load_reg(a->vm + 1, 0);
167
+ rm4 = neon_load_reg(a->vm + 1, 1);
168
+ rtmp = tcg_temp_new_i64();
169
+
170
+ shiftfn(rm1, rm1, constimm);
171
+ shiftfn(rm2, rm2, constimm);
172
+
173
+ tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
174
+ tcg_temp_free_i32(rm2);
175
+
176
+ narrowfn(rm1, cpu_env, rtmp);
177
+ neon_store_reg(a->vd, 0, rm1);
178
+
179
+ shiftfn(rm3, rm3, constimm);
180
+ shiftfn(rm4, rm4, constimm);
181
+ tcg_temp_free_i32(constimm);
182
+
183
+ tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
184
+ tcg_temp_free_i32(rm4);
185
+
186
+ narrowfn(rm3, cpu_env, rtmp);
187
+ tcg_temp_free_i64(rtmp);
188
+ neon_store_reg(a->vd, 1, rm3);
189
+ return true;
190
+}
191
+
192
+#define DO_2SN_64(INSN, FUNC, NARROWFUNC) \
193
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
194
+ { \
195
+ return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \
196
+ }
197
+#define DO_2SN_32(INSN, FUNC, NARROWFUNC) \
198
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
199
+ { \
200
+ return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \
201
+ }
202
+
203
+static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
204
+{
205
+ tcg_gen_extrl_i64_i32(dest, src);
206
+}
207
+
208
+static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
209
+{
210
+ gen_helper_neon_narrow_u16(dest, src);
211
+}
212
+
213
+static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
214
+{
215
+ gen_helper_neon_narrow_u8(dest, src);
216
+}
217
+
218
+DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32)
219
+DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16)
220
+DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8)
221
+
222
+DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32)
223
+DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16)
224
+DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8)
225
+
226
+DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32)
227
+DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16)
228
+DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
229
+
230
+DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
231
+DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
232
+DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
233
diff --git a/target/arm/translate.c b/target/arm/translate.c
234
index XXXXXXX..XXXXXXX 100644
235
--- a/target/arm/translate.c
236
+++ b/target/arm/translate.c
237
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
238
case 5: /* VSHL, VSLI */
239
case 6: /* VQSHLU */
240
case 7: /* VQSHL */
241
+ case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
242
return 1; /* handled by decodetree */
243
default:
244
break;
95
--
245
--
96
2.7.4
246
2.20.1
97
247
98
248
diff view generated by jsdifflib
1
Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()
1
Convert the remaining Neon narrowing shifts to decodetree:
2
functions take a bool indicating whether to pend the secure
2
* VQSHRN
3
or non-secure version of a banked interrupt, and update the
3
* VQRSHRN
4
callsites accordingly.
5
6
In most callsites we can simply pass the correct security
7
state in; in a couple of cases we use TODO comments to indicate
8
that we will return the code in a subsequent commit.
9
4
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505240046-11454-10-git-send-email-peter.maydell@linaro.org
7
Message-id: 20200522145520.6778-7-peter.maydell@linaro.org
13
---
8
---
14
target/arm/cpu.h | 14 ++++++++++-
9
target/arm/neon-dp.decode | 20 ++++++
15
hw/intc/armv7m_nvic.c | 64 ++++++++++++++++++++++++++++++++++++++-------------
10
target/arm/translate-neon.inc.c | 15 +++++
16
target/arm/helper.c | 24 +++++++++++--------
11
target/arm/translate.c | 110 +-------------------------------
17
hw/intc/trace-events | 4 ++--
12
3 files changed, 37 insertions(+), 108 deletions(-)
18
4 files changed, 77 insertions(+), 29 deletions(-)
13
19
14
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
16
--- a/target/arm/neon-dp.decode
23
+++ b/target/arm/cpu.h
17
+++ b/target/arm/neon-dp.decode
24
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
18
@@ -XXX,XX +XXX,XX @@ VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
25
return true;
19
VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
26
}
20
VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
27
#endif
21
VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
28
-void armv7m_nvic_set_pending(void *opaque, int irq);
22
+
29
+/**
23
+# VQSHRN with signed input
30
+ * armv7m_nvic_set_pending: mark the specified exception as pending
24
+VQSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
31
+ * @opaque: the NVIC
25
+VQSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
32
+ * @irq: the exception number to mark pending
26
+VQSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
33
+ * @secure: false for non-banked exceptions or for the nonsecure
27
+
34
+ * version of a banked exception, true for the secure version of a banked
28
+# VQRSHRN with signed input
35
+ * exception.
29
+VQRSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
36
+ *
30
+VQRSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
37
+ * Marks the specified exception as pending. Note that we will assert()
31
+VQRSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
38
+ * if @secure is true and @irq does not specify one of the fixed set
32
+
39
+ * of architecturally banked exceptions.
33
+# VQSHRN with unsigned input
40
+ */
34
+VQSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
41
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
35
+VQSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
42
void armv7m_nvic_acknowledge_irq(void *opaque);
36
+VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
43
/**
37
+
44
* armv7m_nvic_complete_irq: complete specified interrupt or exception
38
+# VQRSHRN with unsigned input
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
39
+VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
40
+VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
41
+VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
42
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
46
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
44
--- a/target/arm/translate-neon.inc.c
48
+++ b/hw/intc/armv7m_nvic.c
45
+++ b/target/arm/translate-neon.inc.c
49
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
46
@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
50
qemu_set_irq(s->excpout, lvl);
47
DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
51
}
48
DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
52
49
DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
53
-static void armv7m_nvic_clear_pending(void *opaque, int irq)
50
+DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32)
54
+/**
51
+DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16)
55
+ * armv7m_nvic_clear_pending: mark the specified exception as not pending
52
+DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8)
56
+ * @opaque: the NVIC
53
+
57
+ * @irq: the exception number to mark as not pending
54
+DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32)
58
+ * @secure: false for non-banked exceptions or for the nonsecure
55
+DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16)
59
+ * version of a banked exception, true for the secure version of a banked
56
+DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8)
60
+ * exception.
57
+
61
+ *
58
+DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32)
62
+ * Marks the specified exception as not pending. Note that we will assert()
59
+DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16)
63
+ * if @secure is true and @irq does not specify one of the fixed set
60
+DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
64
+ * of architecturally banked exceptions.
61
+
65
+ */
62
+DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
66
+static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
63
+DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
67
{
64
+DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
68
NVICState *s = (NVICState *)opaque;
65
diff --git a/target/arm/translate.c b/target/arm/translate.c
69
VecInfo *vec;
66
index XXXXXXX..XXXXXXX 100644
70
67
--- a/target/arm/translate.c
71
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
68
+++ b/target/arm/translate.c
72
69
@@ -XXX,XX +XXX,XX @@ static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
73
- vec = &s->vectors[irq];
74
- trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
75
+ if (secure) {
76
+ assert(exc_is_banked(irq));
77
+ vec = &s->sec_vectors[irq];
78
+ } else {
79
+ vec = &s->vectors[irq];
80
+ }
81
+ trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
82
if (vec->pending) {
83
vec->pending = 0;
84
nvic_irq_update(s);
85
}
70
}
86
}
71
}
87
72
88
-void armv7m_nvic_set_pending(void *opaque, int irq)
73
-static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
89
+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
74
- int q, int u)
75
-{
76
- if (q) {
77
- if (u) {
78
- switch (size) {
79
- case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
80
- case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
81
- default: abort();
82
- }
83
- } else {
84
- switch (size) {
85
- case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
86
- case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
87
- default: abort();
88
- }
89
- }
90
- } else {
91
- if (u) {
92
- switch (size) {
93
- case 1: gen_helper_neon_shl_u16(var, var, shift); break;
94
- case 2: gen_ushl_i32(var, var, shift); break;
95
- default: abort();
96
- }
97
- } else {
98
- switch (size) {
99
- case 1: gen_helper_neon_shl_s16(var, var, shift); break;
100
- case 2: gen_sshl_i32(var, var, shift); break;
101
- default: abort();
102
- }
103
- }
104
- }
105
-}
106
-
107
static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
90
{
108
{
91
NVICState *s = (NVICState *)opaque;
109
if (u) {
92
+ bool banked = exc_is_banked(irq);
110
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
93
VecInfo *vec;
111
case 6: /* VQSHLU */
94
112
case 7: /* VQSHL */
95
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
113
case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
96
+ assert(!secure || banked);
114
+ case 9: /* VQSHRN, VQRSHRN */
97
115
return 1; /* handled by decodetree */
98
- vec = &s->vectors[irq];
116
default:
99
- trace_nvic_set_pending(irq, vec->enabled, vec->prio);
117
break;
100
+ vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
118
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
101
119
size--;
102
+ trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);
103
104
if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
105
/* If a synchronous exception is pending then it may be
106
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq)
107
"(current priority %d)\n", irq, running);
108
}
120
}
109
121
shift = (insn >> 16) & ((1 << (3 + size)) - 1);
110
- /* We can do the escalation, so we take HardFault instead */
122
- if (op < 10) {
111
+ /* We can do the escalation, so we take HardFault instead.
123
- /* Shift by immediate and narrow:
112
+ * If BFHFNMINS is set then we escalate to the banked HF for
124
- VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
113
+ * the target security state of the original exception; otherwise
125
- int input_unsigned = (op == 8) ? !u : u;
114
+ * we take a Secure HardFault.
126
- if (rm & 1) {
115
+ */
127
- return 1;
116
irq = ARMV7M_EXCP_HARD;
128
- }
117
- vec = &s->vectors[irq];
129
- shift = shift - (1 << (size + 3));
118
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
130
- size++;
119
+ (secure ||
131
- if (size == 3) {
120
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
132
- tmp64 = tcg_const_i64(shift);
121
+ vec = &s->sec_vectors[irq];
133
- neon_load_reg64(cpu_V0, rm);
122
+ } else {
134
- neon_load_reg64(cpu_V1, rm + 1);
123
+ vec = &s->vectors[irq];
135
- for (pass = 0; pass < 2; pass++) {
124
+ }
136
- TCGv_i64 in;
125
+ /* HF may be banked but there is only one shared HFSR */
137
- if (pass == 0) {
126
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
138
- in = cpu_V0;
127
}
139
- } else {
128
}
140
- in = cpu_V1;
129
@@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level)
141
- }
130
if (level != vec->level) {
142
- if (q) {
131
vec->level = level;
143
- if (input_unsigned) {
132
if (level) {
144
- gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
133
- armv7m_nvic_set_pending(s, n);
145
- } else {
134
+ armv7m_nvic_set_pending(s, n, false);
146
- gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
135
}
147
- }
136
}
148
- } else {
137
}
149
- if (input_unsigned) {
138
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
150
- gen_ushl_i64(cpu_V0, in, tmp64);
139
}
151
- } else {
140
case 0xd04: /* Interrupt Control State. */
152
- gen_sshl_i64(cpu_V0, in, tmp64);
141
if (value & (1 << 31)) {
153
- }
142
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
154
- }
143
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
155
- tmp = tcg_temp_new_i32();
144
}
156
- gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
145
if (value & (1 << 28)) {
157
- neon_store_reg(rd, pass, tmp);
146
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
158
- } /* for pass */
147
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
159
- tcg_temp_free_i64(tmp64);
148
} else if (value & (1 << 27)) {
160
- } else {
149
- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
161
- if (size == 1) {
150
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);
162
- imm = (uint16_t)shift;
151
}
163
- imm |= imm << 16;
152
if (value & (1 << 26)) {
164
- } else {
153
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
165
- /* size == 2 */
154
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
166
- imm = (uint32_t)shift;
155
} else if (value & (1 << 25)) {
167
- }
156
- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
168
- tmp2 = tcg_const_i32(imm);
157
+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);
169
- tmp4 = neon_load_reg(rm + 1, 0);
158
}
170
- tmp5 = neon_load_reg(rm + 1, 1);
159
break;
171
- for (pass = 0; pass < 2; pass++) {
160
case 0xd08: /* Vector Table Offset. */
172
- if (pass == 0) {
161
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
173
- tmp = neon_load_reg(rm, 0);
162
{
174
- } else {
163
int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
175
- tmp = tmp4;
164
if (excnum < s->num_irq) {
176
- }
165
- armv7m_nvic_set_pending(s, excnum);
177
- gen_neon_shift_narrow(size, tmp, tmp2, q,
166
+ armv7m_nvic_set_pending(s, excnum, false);
178
- input_unsigned);
167
}
179
- if (pass == 0) {
168
break;
180
- tmp3 = neon_load_reg(rm, 1);
169
}
181
- } else {
170
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
182
- tmp3 = tmp5;
171
/* SysTick just asked us to pend its exception.
183
- }
172
* (This is different from an external interrupt line's
184
- gen_neon_shift_narrow(size, tmp3, tmp2, q,
173
* behaviour.)
185
- input_unsigned);
174
+ * TODO: when we implement the banked systicks we must make
186
- tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
175
+ * this pend the correct banked exception.
187
- tcg_temp_free_i32(tmp);
176
*/
188
- tcg_temp_free_i32(tmp3);
177
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
189
- tmp = tcg_temp_new_i32();
178
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);
190
- gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
179
}
191
- neon_store_reg(rd, pass, tmp);
180
}
192
- } /* for pass */
181
193
- tcg_temp_free_i32(tmp2);
182
diff --git a/target/arm/helper.c b/target/arm/helper.c
194
- }
183
index XXXXXXX..XXXXXXX 100644
195
- } else if (op == 10) {
184
--- a/target/arm/helper.c
196
+ if (op == 10) {
185
+++ b/target/arm/helper.c
197
/* VSHLL, VMOVL */
186
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
198
if (q || (rd & 1)) {
187
* stack, directly take a usage fault on the current stack.
199
return 1;
188
*/
189
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
190
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
191
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
192
v7m_exception_taken(cpu, excret);
193
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
194
"stackframe: failed exception return integrity check\n");
195
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
196
* exception return excret specified then this is a UsageFault.
197
*/
198
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
199
- /* Take an INVPC UsageFault by pushing the stack again. */
200
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
201
+ /* Take an INVPC UsageFault by pushing the stack again.
202
+ * TODO: the v8M version of this code should target the
203
+ * background state for this exception.
204
+ */
205
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);
206
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
207
v7m_push_stack(cpu);
208
v7m_exception_taken(cpu, excret);
209
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
210
handle it. */
211
switch (cs->exception_index) {
212
case EXCP_UDEF:
213
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
214
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
215
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
216
break;
217
case EXCP_NOCP:
218
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
219
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
220
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
221
break;
222
case EXCP_INVSTATE:
223
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
224
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
225
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
226
break;
227
case EXCP_SWI:
228
/* The PC already points to the next instruction. */
229
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
230
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
231
break;
232
case EXCP_PREFETCH_ABORT:
233
case EXCP_DATA_ABORT:
234
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
235
env->v7m.bfar);
236
break;
237
}
238
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
239
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
240
break;
241
default:
242
/* All other FSR values are either MPU faults or "can't happen
243
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
244
env->v7m.mmfar[env->v7m.secure]);
245
break;
246
}
247
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
248
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,
249
+ env->v7m.secure);
250
break;
251
}
252
break;
253
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
254
return;
255
}
256
}
257
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
258
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
259
break;
260
case EXCP_IRQ:
261
break;
262
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
263
index XXXXXXX..XXXXXXX 100644
264
--- a/hw/intc/trace-events
265
+++ b/hw/intc/trace-events
266
@@ -XXX,XX +XXX,XX @@ nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"
267
nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
268
nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
269
nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
270
-nvic_set_pending(int irq, int en, int prio) "NVIC set pending irq %d (enabled: %d priority %d)"
271
-nvic_clear_pending(int irq, int en, int prio) "NVIC clear pending irq %d (enabled: %d priority %d)"
272
+nvic_set_pending(int irq, bool secure, int en, int prio) "NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)"
273
+nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
274
nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
275
nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
276
nvic_complete_irq(int irq) "NVIC complete IRQ %d"
277
--
200
--
278
2.7.4
201
2.20.1
279
202
280
203
diff view generated by jsdifflib
1
Don't use the old_mmio struct in memory region ops.
1
Convert the VSHLL and VMOVL insns from the 2-reg-shift group
2
to decodetree. Since the loop always has two passes, we unroll
3
it to avoid the awkward reassignment of one TCGv to another.
2
4
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
7
Message-id: 20200522145520.6778-8-peter.maydell@linaro.org
6
---
8
---
7
hw/timer/omap_gptimer.c | 49 +++++++++++++++++++++++++++++++++++++------------
9
target/arm/neon-dp.decode | 16 +++++++
8
1 file changed, 37 insertions(+), 12 deletions(-)
10
target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++
9
11
target/arm/translate.c | 46 +------------------
10
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
12
3 files changed, 99 insertions(+), 44 deletions(-)
13
14
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
11
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/timer/omap_gptimer.c
16
--- a/target/arm/neon-dp.decode
13
+++ b/hw/timer/omap_gptimer.c
17
+++ b/target/arm/neon-dp.decode
14
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
18
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
15
s->writeh = (uint16_t) value;
19
&2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
16
}
20
shift=%neon_rshift_i3
17
21
18
+static uint64_t omap_gp_timer_readfn(void *opaque, hwaddr addr,
22
+# Long left shifts: again Q is part of opcode decode
19
+ unsigned size)
23
+@2reg_shll_s .... ... . . . 1 shift:5 .... .... 0 . . . .... \
24
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
25
+@2reg_shll_h .... ... . . . 01 shift:4 .... .... 0 . . . .... \
26
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
27
+@2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \
28
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
29
+
30
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
31
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
32
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
33
@@ -XXX,XX +XXX,XX @@ VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
34
VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
35
VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
36
VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
37
+
38
+VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
39
+VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
40
+VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
41
+
42
+VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
43
+VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
44
+VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
45
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate-neon.inc.c
48
+++ b/target/arm/translate-neon.inc.c
49
@@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
50
DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
51
DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
52
DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
53
+
54
+static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
55
+ NeonGenWidenFn *widenfn, bool u)
20
+{
56
+{
21
+ switch (size) {
57
+ TCGv_i64 tmp;
22
+ case 1:
58
+ TCGv_i32 rm0, rm1;
23
+ return omap_badwidth_read32(opaque, addr);
59
+ uint64_t widen_mask = 0;
24
+ case 2:
60
+
25
+ return omap_gp_timer_readh(opaque, addr);
61
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
26
+ case 4:
62
+ return false;
27
+ return omap_gp_timer_readw(opaque, addr);
63
+ }
28
+ default:
64
+
29
+ g_assert_not_reached();
65
+ /* UNDEF accesses to D16-D31 if they don't exist. */
30
+ }
66
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
67
+ ((a->vd | a->vm) & 0x10)) {
68
+ return false;
69
+ }
70
+
71
+ if (a->vd & 1) {
72
+ return false;
73
+ }
74
+
75
+ if (!vfp_access_check(s)) {
76
+ return true;
77
+ }
78
+
79
+ /*
80
+ * This is a widen-and-shift operation. The shift is always less
81
+ * than the width of the source type, so after widening the input
82
+ * vector we can simply shift the whole 64-bit widened register,
83
+ * and then clear the potential overflow bits resulting from left
84
+ * bits of the narrow input appearing as right bits of the left
85
+ * neighbour narrow input. Calculate a mask of bits to clear.
86
+ */
87
+ if ((a->shift != 0) && (a->size < 2 || u)) {
88
+ int esize = 8 << a->size;
89
+ widen_mask = MAKE_64BIT_MASK(0, esize);
90
+ widen_mask >>= esize - a->shift;
91
+ widen_mask = dup_const(a->size + 1, widen_mask);
92
+ }
93
+
94
+ rm0 = neon_load_reg(a->vm, 0);
95
+ rm1 = neon_load_reg(a->vm, 1);
96
+ tmp = tcg_temp_new_i64();
97
+
98
+ widenfn(tmp, rm0);
99
+ if (a->shift != 0) {
100
+ tcg_gen_shli_i64(tmp, tmp, a->shift);
101
+ tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
102
+ }
103
+ neon_store_reg64(tmp, a->vd);
104
+
105
+ widenfn(tmp, rm1);
106
+ if (a->shift != 0) {
107
+ tcg_gen_shli_i64(tmp, tmp, a->shift);
108
+ tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
109
+ }
110
+ neon_store_reg64(tmp, a->vd + 1);
111
+ tcg_temp_free_i64(tmp);
112
+ return true;
31
+}
113
+}
32
+
114
+
33
+static void omap_gp_timer_writefn(void *opaque, hwaddr addr,
115
+static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a)
34
+ uint64_t value, unsigned size)
35
+{
116
+{
36
+ switch (size) {
117
+ NeonGenWidenFn *widenfn[] = {
37
+ case 1:
118
+ gen_helper_neon_widen_s8,
38
+ omap_badwidth_write32(opaque, addr, value);
119
+ gen_helper_neon_widen_s16,
39
+ break;
120
+ tcg_gen_ext_i32_i64,
40
+ case 2:
121
+ };
41
+ omap_gp_timer_writeh(opaque, addr, value);
122
+ return do_vshll_2sh(s, a, widenfn[a->size], false);
42
+ break;
43
+ case 4:
44
+ omap_gp_timer_write(opaque, addr, value);
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
+}
123
+}
50
+
124
+
51
static const MemoryRegionOps omap_gp_timer_ops = {
125
+static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
52
- .old_mmio = {
126
+{
53
- .read = {
127
+ NeonGenWidenFn *widenfn[] = {
54
- omap_badwidth_read32,
128
+ gen_helper_neon_widen_u8,
55
- omap_gp_timer_readh,
129
+ gen_helper_neon_widen_u16,
56
- omap_gp_timer_readw,
130
+ tcg_gen_extu_i32_i64,
57
- },
131
+ };
58
- .write = {
132
+ return do_vshll_2sh(s, a, widenfn[a->size], true);
59
- omap_badwidth_write32,
133
+}
60
- omap_gp_timer_writeh,
134
diff --git a/target/arm/translate.c b/target/arm/translate.c
61
- omap_gp_timer_write,
135
index XXXXXXX..XXXXXXX 100644
62
- },
136
--- a/target/arm/translate.c
63
- },
137
+++ b/target/arm/translate.c
64
+ .read = omap_gp_timer_readfn,
138
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
65
+ .write = omap_gp_timer_writefn,
139
case 7: /* VQSHL */
66
+ .valid.min_access_size = 1,
140
case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
67
+ .valid.max_access_size = 4,
141
case 9: /* VQSHRN, VQRSHRN */
68
.endianness = DEVICE_NATIVE_ENDIAN,
142
+ case 10: /* VSHLL, including VMOVL */
69
};
143
return 1; /* handled by decodetree */
70
144
default:
145
break;
146
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
147
size--;
148
}
149
shift = (insn >> 16) & ((1 << (3 + size)) - 1);
150
- if (op == 10) {
151
- /* VSHLL, VMOVL */
152
- if (q || (rd & 1)) {
153
- return 1;
154
- }
155
- tmp = neon_load_reg(rm, 0);
156
- tmp2 = neon_load_reg(rm, 1);
157
- for (pass = 0; pass < 2; pass++) {
158
- if (pass == 1)
159
- tmp = tmp2;
160
-
161
- gen_neon_widen(cpu_V0, tmp, size, u);
162
-
163
- if (shift != 0) {
164
- /* The shift is less than the width of the source
165
- type, so we can just shift the whole register. */
166
- tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
167
- /* Widen the result of shift: we need to clear
168
- * the potential overflow bits resulting from
169
- * left bits of the narrow input appearing as
170
- * right bits of left the neighbour narrow
171
- * input. */
172
- if (size < 2 || !u) {
173
- uint64_t imm64;
174
- if (size == 0) {
175
- imm = (0xffu >> (8 - shift));
176
- imm |= imm << 16;
177
- } else if (size == 1) {
178
- imm = 0xffff >> (16 - shift);
179
- } else {
180
- /* size == 2 */
181
- imm = 0xffffffff >> (32 - shift);
182
- }
183
- if (size < 2) {
184
- imm64 = imm | (((uint64_t)imm) << 32);
185
- } else {
186
- imm64 = imm;
187
- }
188
- tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
189
- }
190
- }
191
- neon_store_reg64(cpu_V0, rd + pass);
192
- }
193
- } else if (op >= 14) {
194
+ if (op >= 14) {
195
/* VCVT fixed-point. */
196
TCGv_ptr fpst;
197
TCGv_i32 shiftv;
71
--
198
--
72
2.7.4
199
2.20.1
73
200
74
201
diff view generated by jsdifflib
1
Update nvic_exec_prio() to support the v8M changes:
1
Convert the VCVT fixed-point conversion operations in the
2
* BASEPRI, FAULTMASK and PRIMASK are all banked
2
Neon 2-regs-and-shift group to decodetree.
3
* AIRCR.PRIS can affect NS priorities
4
* AIRCR.BFHFNMINS affects FAULTMASK behaviour
5
6
These changes mean that it's no longer possible to
7
definitely say that if FAULTMASK is set it overrides
8
PRIMASK, and if PRIMASK is set it overrides BASEPRI
9
(since if PRIMASK_NS is set and AIRCR.PRIS is set then
10
whether that 0x80 priority should take effect or the
11
priority in BASEPRI_S depends on the value of BASEPRI_S,
12
for instance). So we switch to the same approach used
13
by the pseudocode of working through BASEPRI, PRIMASK
14
and FAULTMASK and overriding the previous values if
15
needed.
16
3
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 1505240046-11454-16-git-send-email-peter.maydell@linaro.org
6
Message-id: 20200522145520.6778-9-peter.maydell@linaro.org
20
---
7
---
21
hw/intc/armv7m_nvic.c | 51 ++++++++++++++++++++++++++++++++++++++++++---------
8
target/arm/neon-dp.decode | 11 +++++
22
1 file changed, 42 insertions(+), 9 deletions(-)
9
target/arm/translate-neon.inc.c | 49 +++++++++++++++++++++
10
target/arm/translate.c | 75 +--------------------------------
11
3 files changed, 62 insertions(+), 73 deletions(-)
23
12
24
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/intc/armv7m_nvic.c
15
--- a/target/arm/neon-dp.decode
27
+++ b/hw/intc/armv7m_nvic.c
16
+++ b/target/arm/neon-dp.decode
28
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
17
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
29
static inline int nvic_exec_prio(NVICState *s)
18
@2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \
30
{
19
&2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
31
CPUARMState *env = &s->cpu->env;
20
32
- int running;
21
+# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
33
+ int running = NVIC_NOEXC_PRIO;
22
+@2reg_vcvt .... ... . . . 1 ..... .... .... . q:1 . . .... \
34
23
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
35
- if (env->v7m.faultmask[env->v7m.secure]) {
24
+
36
- running = -1;
25
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
37
- } else if (env->v7m.primask[env->v7m.secure]) {
26
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
38
+ if (env->v7m.basepri[M_REG_NS] > 0) {
27
VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
39
+ running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
28
@@ -XXX,XX +XXX,XX @@ VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
29
VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
30
VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
31
VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
32
+
33
+# VCVT fixed<->float conversions
34
+# TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
35
+VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
36
+VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
37
+VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
38
+VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
39
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate-neon.inc.c
42
+++ b/target/arm/translate-neon.inc.c
43
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
44
};
45
return do_vshll_2sh(s, a, widenfn[a->size], true);
46
}
47
+
48
+static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
49
+ NeonGenTwoSingleOPFn *fn)
50
+{
51
+ /* FP operations in 2-reg-and-shift group */
52
+ TCGv_i32 tmp, shiftv;
53
+ TCGv_ptr fpstatus;
54
+ int pass;
55
+
56
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
57
+ return false;
40
+ }
58
+ }
41
+
59
+
42
+ if (env->v7m.basepri[M_REG_S] > 0) {
60
+ /* UNDEF accesses to D16-D31 if they don't exist. */
43
+ int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
61
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
44
+ if (running > basepri) {
62
+ ((a->vd | a->vm) & 0x10)) {
45
+ running = basepri;
63
+ return false;
46
+ }
47
+ }
64
+ }
48
+
65
+
49
+ if (env->v7m.primask[M_REG_NS]) {
66
+ if ((a->vm | a->vd) & a->q) {
50
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
67
+ return false;
51
+ if (running > NVIC_NS_PRIO_LIMIT) {
52
+ running = NVIC_NS_PRIO_LIMIT;
53
+ }
54
+ } else {
55
+ running = 0;
56
+ }
57
+ }
68
+ }
58
+
69
+
59
+ if (env->v7m.primask[M_REG_S]) {
70
+ if (!vfp_access_check(s)) {
60
running = 0;
71
+ return true;
61
- } else if (env->v7m.basepri[env->v7m.secure] > 0) {
62
- running = env->v7m.basepri[env->v7m.secure] &
63
- nvic_gprio_mask(s, env->v7m.secure);
64
- } else {
65
- running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
66
}
67
+
68
+ if (env->v7m.faultmask[M_REG_NS]) {
69
+ if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
70
+ running = -1;
71
+ } else {
72
+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
73
+ if (running > NVIC_NS_PRIO_LIMIT) {
74
+ running = NVIC_NS_PRIO_LIMIT;
75
+ }
76
+ } else {
77
+ running = 0;
78
+ }
79
+ }
80
+ }
72
+ }
81
+
73
+
82
+ if (env->v7m.faultmask[M_REG_S]) {
74
+ fpstatus = get_fpstatus_ptr(1);
83
+ running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
75
+ shiftv = tcg_const_i32(a->shift);
76
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
77
+ tmp = neon_load_reg(a->vm, pass);
78
+ fn(tmp, tmp, shiftv, fpstatus);
79
+ neon_store_reg(a->vd, pass, tmp);
80
+ }
81
+ tcg_temp_free_ptr(fpstatus);
82
+ tcg_temp_free_i32(shiftv);
83
+ return true;
84
+}
85
+
86
+#define DO_FP_2SH(INSN, FUNC) \
87
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
88
+ { \
89
+ return do_fp_2sh(s, a, FUNC); \
84
+ }
90
+ }
85
+
91
+
86
/* consider priority of active handler */
92
+DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
87
return MIN(running, s->exception_prio);
93
+DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
88
}
94
+DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
95
+DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
96
diff --git a/target/arm/translate.c b/target/arm/translate.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/target/arm/translate.c
99
+++ b/target/arm/translate.c
100
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
101
int q;
102
int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs;
103
int size;
104
- int shift;
105
int pass;
106
int u;
107
int vec_size;
108
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
109
return 1;
110
} else if (insn & (1 << 4)) {
111
if ((insn & 0x00380080) != 0) {
112
- /* Two registers and shift. */
113
- op = (insn >> 8) & 0xf;
114
-
115
- switch (op) {
116
- case 0: /* VSHR */
117
- case 1: /* VSRA */
118
- case 2: /* VRSHR */
119
- case 3: /* VRSRA */
120
- case 4: /* VSRI */
121
- case 5: /* VSHL, VSLI */
122
- case 6: /* VQSHLU */
123
- case 7: /* VQSHL */
124
- case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
125
- case 9: /* VQSHRN, VQRSHRN */
126
- case 10: /* VSHLL, including VMOVL */
127
- return 1; /* handled by decodetree */
128
- default:
129
- break;
130
- }
131
-
132
- if (insn & (1 << 7)) {
133
- /* 64-bit shift. */
134
- if (op > 7) {
135
- return 1;
136
- }
137
- size = 3;
138
- } else {
139
- size = 2;
140
- while ((insn & (1 << (size + 19))) == 0)
141
- size--;
142
- }
143
- shift = (insn >> 16) & ((1 << (3 + size)) - 1);
144
- if (op >= 14) {
145
- /* VCVT fixed-point. */
146
- TCGv_ptr fpst;
147
- TCGv_i32 shiftv;
148
- VFPGenFixPointFn *fn;
149
-
150
- if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
151
- return 1;
152
- }
153
-
154
- if (!(op & 1)) {
155
- if (u) {
156
- fn = gen_helper_vfp_ultos;
157
- } else {
158
- fn = gen_helper_vfp_sltos;
159
- }
160
- } else {
161
- if (u) {
162
- fn = gen_helper_vfp_touls_round_to_zero;
163
- } else {
164
- fn = gen_helper_vfp_tosls_round_to_zero;
165
- }
166
- }
167
-
168
- /* We have already masked out the must-be-1 top bit of imm6,
169
- * hence this 32-shift where the ARM ARM has 64-imm6.
170
- */
171
- shift = 32 - shift;
172
- fpst = get_fpstatus_ptr(1);
173
- shiftv = tcg_const_i32(shift);
174
- for (pass = 0; pass < (q ? 4 : 2); pass++) {
175
- TCGv_i32 tmpf = neon_load_reg(rm, pass);
176
- fn(tmpf, tmpf, shiftv, fpst);
177
- neon_store_reg(rd, pass, tmpf);
178
- }
179
- tcg_temp_free_ptr(fpst);
180
- tcg_temp_free_i32(shiftv);
181
- } else {
182
- return 1;
183
- }
184
+ /* Two registers and shift: handled by decodetree */
185
+ return 1;
186
} else { /* (insn & 0x00380080) == 0 */
187
int invert, reg_ofs, vec_size;
188
89
--
189
--
90
2.7.4
190
2.20.1
91
191
92
192
diff view generated by jsdifflib
1
Handle banking of SHCSR: some register bits are banked between
1
Convert the insns in the one-register-and-immediate group to decodetree.
2
Secure and Non-Secure, and some are only accessible to Secure.
2
3
In the new decode, our asimd_imm_const() function returns a 64-bit value
4
rather than a 32-bit one, which means we don't need to treat cmode=14 op=1
5
as a special case in the decoder (it is the only encoding where the two
6
halves of the 64-bit value are different).
3
7
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1505240046-11454-19-git-send-email-peter.maydell@linaro.org
10
Message-id: 20200522145520.6778-10-peter.maydell@linaro.org
7
---
11
---
8
hw/intc/armv7m_nvic.c | 221 ++++++++++++++++++++++++++++++++++++++------------
12
target/arm/neon-dp.decode | 22 ++++++
9
1 file changed, 169 insertions(+), 52 deletions(-)
13
target/arm/translate-neon.inc.c | 118 ++++++++++++++++++++++++++++++++
10
14
target/arm/translate.c | 101 +--------------------------
11
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
3 files changed, 142 insertions(+), 99 deletions(-)
16
17
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/armv7m_nvic.c
19
--- a/target/arm/neon-dp.decode
14
+++ b/hw/intc/armv7m_nvic.c
20
+++ b/target/arm/neon-dp.decode
15
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
21
@@ -XXX,XX +XXX,XX @@ VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
16
val = cpu->env.v7m.ccr[attrs.secure];
22
VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
17
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
23
VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
18
return val;
24
VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
19
- case 0xd24: /* System Handler Status. */
25
+
20
+ case 0xd24: /* System Handler Control and State (SHCSR) */
26
+######################################################################
21
val = 0;
27
+# 1-reg-and-modified-immediate grouping:
22
- if (s->vectors[ARMV7M_EXCP_MEM].active) {
28
+# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
23
- val |= (1 << 0);
29
+######################################################################
24
- }
30
+
25
- if (s->vectors[ARMV7M_EXCP_BUS].active) {
31
+&1reg_imm vd q imm cmode op
26
- val |= (1 << 1);
32
+
27
- }
33
+%asimd_imm_value 24:1 16:3 0:4
28
- if (s->vectors[ARMV7M_EXCP_USAGE].active) {
34
+
29
- val |= (1 << 3);
35
+@1reg_imm .... ... . . . ... ... .... .... . q:1 . . .... \
30
+ if (attrs.secure) {
36
+ &1reg_imm imm=%asimd_imm_value vd=%vd_dp
31
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {
37
+
32
+ val |= (1 << 0);
38
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
33
+ }
39
+# not in a way we can conveniently represent in decodetree without
34
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {
40
+# a lot of repetition:
35
+ val |= (1 << 2);
41
+# VORR: op=0, (cmode & 1) && cmode < 12
36
+ }
42
+# VBIC: op=1, (cmode & 1) && cmode < 12
37
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {
43
+# VMOV: everything else
38
+ val |= (1 << 3);
44
+# So we have a single decode line and check the cmode/op in the
39
+ }
45
+# trans function.
40
+ if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {
46
+Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
41
+ val |= (1 << 7);
47
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
42
+ }
48
index XXXXXXX..XXXXXXX 100644
43
+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {
49
--- a/target/arm/translate-neon.inc.c
44
+ val |= (1 << 10);
50
+++ b/target/arm/translate-neon.inc.c
45
+ }
51
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
46
+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {
52
DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
47
+ val |= (1 << 11);
53
DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
48
+ }
54
DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
49
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {
55
+
50
+ val |= (1 << 12);
56
+static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
51
+ }
57
+{
52
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {
58
+ /*
53
+ val |= (1 << 13);
59
+ * Expand the encoded constant.
54
+ }
60
+ * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
55
+ if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {
61
+ * We choose to not special-case this and will behave as if a
56
+ val |= (1 << 15);
62
+ * valid constant encoding of 0 had been given.
57
+ }
63
+ * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
58
+ if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {
64
+ */
59
+ val |= (1 << 16);
65
+ switch (cmode) {
60
+ }
66
+ case 0: case 1:
61
+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {
67
+ /* no-op */
62
+ val |= (1 << 18);
68
+ break;
63
+ }
69
+ case 2: case 3:
64
+ if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {
70
+ imm <<= 8;
65
+ val |= (1 << 21);
71
+ break;
66
+ }
72
+ case 4: case 5:
67
+ /* SecureFault is not banked but is always RAZ/WI to NS */
73
+ imm <<= 16;
68
+ if (s->vectors[ARMV7M_EXCP_SECURE].active) {
74
+ break;
69
+ val |= (1 << 4);
75
+ case 6: case 7:
70
+ }
76
+ imm <<= 24;
71
+ if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {
77
+ break;
72
+ val |= (1 << 19);
78
+ case 8: case 9:
73
+ }
79
+ imm |= imm << 16;
74
+ if (s->vectors[ARMV7M_EXCP_SECURE].pending) {
80
+ break;
75
+ val |= (1 << 20);
81
+ case 10: case 11:
76
+ }
82
+ imm = (imm << 8) | (imm << 24);
77
+ } else {
83
+ break;
78
+ if (s->vectors[ARMV7M_EXCP_MEM].active) {
84
+ case 12:
79
+ val |= (1 << 0);
85
+ imm = (imm << 8) | 0xff;
80
+ }
86
+ break;
81
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
87
+ case 13:
82
+ /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
88
+ imm = (imm << 16) | 0xffff;
83
+ if (s->vectors[ARMV7M_EXCP_HARD].active) {
89
+ break;
84
+ val |= (1 << 2);
90
+ case 14:
85
+ }
91
+ if (op) {
86
+ if (s->vectors[ARMV7M_EXCP_HARD].pending) {
92
+ /*
87
+ val |= (1 << 21);
93
+ * This is the only case where the top and bottom 32 bits
94
+ * of the encoded constant differ.
95
+ */
96
+ uint64_t imm64 = 0;
97
+ int n;
98
+
99
+ for (n = 0; n < 8; n++) {
100
+ if (imm & (1 << n)) {
101
+ imm64 |= (0xffULL << (n * 8));
88
+ }
102
+ }
89
+ }
103
+ }
90
+ if (s->vectors[ARMV7M_EXCP_USAGE].active) {
104
+ return imm64;
91
+ val |= (1 << 3);
105
+ }
92
+ }
106
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
93
+ if (s->vectors[ARMV7M_EXCP_SVC].active) {
107
+ break;
94
+ val |= (1 << 7);
108
+ case 15:
95
+ }
109
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
96
+ if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
110
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
97
+ val |= (1 << 10);
111
+ break;
98
+ }
112
+ }
99
+ if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
113
+ if (op) {
100
+ val |= (1 << 11);
114
+ imm = ~imm;
101
+ }
115
+ }
102
+ if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
116
+ return dup_const(MO_32, imm);
103
+ val |= (1 << 12);
117
+}
104
+ }
118
+
105
+ if (s->vectors[ARMV7M_EXCP_MEM].pending) {
119
+static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
106
+ val |= (1 << 13);
120
+ GVecGen2iFn *fn)
107
+ }
121
+{
108
+ if (s->vectors[ARMV7M_EXCP_SVC].pending) {
122
+ uint64_t imm;
109
+ val |= (1 << 15);
123
+ int reg_ofs, vec_size;
110
+ }
124
+
111
+ if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
125
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
112
+ val |= (1 << 16);
126
+ return false;
113
+ }
127
+ }
114
+ if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
128
+
115
+ val |= (1 << 18);
129
+ /* UNDEF accesses to D16-D31 if they don't exist. */
116
+ }
130
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
117
}
131
+ return false;
118
- if (s->vectors[ARMV7M_EXCP_SVC].active) {
132
+ }
119
- val |= (1 << 7);
133
+
120
+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
134
+ if (a->vd & a->q) {
121
+ if (s->vectors[ARMV7M_EXCP_BUS].active) {
135
+ return false;
122
+ val |= (1 << 1);
136
+ }
123
+ }
137
+
124
+ if (s->vectors[ARMV7M_EXCP_BUS].pending) {
138
+ if (!vfp_access_check(s)) {
125
+ val |= (1 << 14);
139
+ return true;
126
+ }
140
+ }
127
+ if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
141
+
128
+ val |= (1 << 17);
142
+ reg_ofs = neon_reg_offset(a->vd, 0);
129
+ }
143
+ vec_size = a->q ? 16 : 8;
130
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
144
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
131
+ s->vectors[ARMV7M_EXCP_NMI].active) {
145
+
132
+ /* NMIACT is not present in v7M */
146
+ fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size);
133
+ val |= (1 << 5);
147
+ return true;
134
+ }
148
+}
135
}
149
+
136
+
150
+static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs,
137
+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
151
+ int64_t c, uint32_t oprsz, uint32_t maxsz)
138
if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
152
+{
139
val |= (1 << 8);
153
+ tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c);
140
}
154
+}
141
- if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
155
+
142
- val |= (1 << 10);
156
+static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
157
+{
158
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
159
+ GVecGen2iFn *fn;
160
+
161
+ if ((a->cmode & 1) && a->cmode < 12) {
162
+ /* for op=1, the imm will be inverted, so BIC becomes AND. */
163
+ fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori;
164
+ } else {
165
+ /* There is one unallocated cmode/op combination in this space */
166
+ if (a->cmode == 15 && a->op == 1) {
167
+ return false;
168
+ }
169
+ fn = gen_VMOV_1r;
170
+ }
171
+ return do_1reg_imm(s, a, fn);
172
+}
173
diff --git a/target/arm/translate.c b/target/arm/translate.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/target/arm/translate.c
176
+++ b/target/arm/translate.c
177
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
178
/* Three register same length: handled by decodetree */
179
return 1;
180
} else if (insn & (1 << 4)) {
181
- if ((insn & 0x00380080) != 0) {
182
- /* Two registers and shift: handled by decodetree */
183
- return 1;
184
- } else { /* (insn & 0x00380080) == 0 */
185
- int invert, reg_ofs, vec_size;
186
-
187
- if (q && (rd & 1)) {
188
- return 1;
189
- }
190
-
191
- op = (insn >> 8) & 0xf;
192
- /* One register and immediate. */
193
- imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
194
- invert = (insn & (1 << 5)) != 0;
195
- /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
196
- * We choose to not special-case this and will behave as if a
197
- * valid constant encoding of 0 had been given.
198
- */
199
- switch (op) {
200
- case 0: case 1:
201
- /* no-op */
202
- break;
203
- case 2: case 3:
204
- imm <<= 8;
205
- break;
206
- case 4: case 5:
207
- imm <<= 16;
208
- break;
209
- case 6: case 7:
210
- imm <<= 24;
211
- break;
212
- case 8: case 9:
213
- imm |= imm << 16;
214
- break;
215
- case 10: case 11:
216
- imm = (imm << 8) | (imm << 24);
217
- break;
218
- case 12:
219
- imm = (imm << 8) | 0xff;
220
- break;
221
- case 13:
222
- imm = (imm << 16) | 0xffff;
223
- break;
224
- case 14:
225
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
226
- if (invert) {
227
- imm = ~imm;
228
- }
229
- break;
230
- case 15:
231
- if (invert) {
232
- return 1;
233
- }
234
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
235
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
236
- break;
237
- }
238
- if (invert) {
239
- imm = ~imm;
240
- }
241
-
242
- reg_ofs = neon_reg_offset(rd, 0);
243
- vec_size = q ? 16 : 8;
244
-
245
- if (op & 1 && op < 12) {
246
- if (invert) {
247
- /* The immediate value has already been inverted,
248
- * so BIC becomes AND.
249
- */
250
- tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,
251
- vec_size, vec_size);
252
- } else {
253
- tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,
254
- vec_size, vec_size);
255
- }
256
- } else {
257
- /* VMOV, VMVN. */
258
- if (op == 14 && invert) {
259
- TCGv_i64 t64 = tcg_temp_new_i64();
260
-
261
- for (pass = 0; pass <= q; ++pass) {
262
- uint64_t val = 0;
263
- int n;
264
-
265
- for (n = 0; n < 8; n++) {
266
- if (imm & (1 << (n + pass * 8))) {
267
- val |= 0xffull << (n * 8);
268
- }
269
- }
270
- tcg_gen_movi_i64(t64, val);
271
- neon_store_reg64(t64, rd + pass);
272
- }
273
- tcg_temp_free_i64(t64);
274
- } else {
275
- tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size,
276
- vec_size, imm);
277
- }
278
- }
143
- }
279
- }
144
- if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
280
+ /* Two registers and shift or reg and imm: handled by decodetree */
145
- val |= (1 << 11);
281
+ return 1;
146
- }
282
} else { /* (insn & 0x00800010 == 0x00800000) */
147
- if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
283
if (size != 3) {
148
- val |= (1 << 12);
284
op = (insn >> 8) & 0xf;
149
- }
150
- if (s->vectors[ARMV7M_EXCP_MEM].pending) {
151
- val |= (1 << 13);
152
- }
153
- if (s->vectors[ARMV7M_EXCP_BUS].pending) {
154
- val |= (1 << 14);
155
- }
156
- if (s->vectors[ARMV7M_EXCP_SVC].pending) {
157
- val |= (1 << 15);
158
- }
159
- if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
160
- val |= (1 << 16);
161
- }
162
- if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
163
- val |= (1 << 17);
164
- }
165
- if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
166
- val |= (1 << 18);
167
- }
168
return val;
169
case 0xd28: /* Configurable Fault Status. */
170
/* The BFSR bits [15:8] are shared between security states
171
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
172
173
cpu->env.v7m.ccr[attrs.secure] = value;
174
break;
175
- case 0xd24: /* System Handler Control. */
176
- s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
177
- s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
178
- s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
179
- s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
180
+ case 0xd24: /* System Handler Control and State (SHCSR) */
181
+ if (attrs.secure) {
182
+ s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
183
+ /* Secure HardFault active bit cannot be written */
184
+ s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
185
+ s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
186
+ s->sec_vectors[ARMV7M_EXCP_PENDSV].active =
187
+ (value & (1 << 10)) != 0;
188
+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =
189
+ (value & (1 << 11)) != 0;
190
+ s->sec_vectors[ARMV7M_EXCP_USAGE].pending =
191
+ (value & (1 << 12)) != 0;
192
+ s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
193
+ s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
194
+ s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
195
+ s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
196
+ s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
197
+ (value & (1 << 18)) != 0;
198
+ /* SecureFault not banked, but RAZ/WI to NS */
199
+ s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
200
+ s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
201
+ s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;
202
+ } else {
203
+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
204
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
205
+ /* HARDFAULTPENDED is not present in v7M */
206
+ s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;
207
+ }
208
+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
209
+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
210
+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
211
+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
212
+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
213
+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
214
+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
215
+ s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
216
+ s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
217
+ }
218
+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
219
+ s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
220
+ s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
221
+ s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
222
+ }
223
+ /* NMIACT can only be written if the write is of a zero, with
224
+ * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
225
+ */
226
+ if (!attrs.secure && cpu->env.v7m.secure &&
227
+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
228
+ (value & (1 << 5)) == 0) {
229
+ s->vectors[ARMV7M_EXCP_NMI].active = 0;
230
+ }
231
+ /* HARDFAULTACT can only be written if the write is of a zero
232
+ * to the non-secure HardFault state by the CPU in secure state.
233
+ * The only case where we can be targeting the non-secure HF state
234
+ * when in secure state is if this is a write via the NS alias
235
+ * and BFHFNMINS is 1.
236
+ */
237
+ if (!attrs.secure && cpu->env.v7m.secure &&
238
+ (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&
239
+ (value & (1 << 2)) == 0) {
240
+ s->vectors[ARMV7M_EXCP_HARD].active = 0;
241
+ }
242
+
243
+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
244
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
245
- s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
246
- s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
247
- s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
248
- s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
249
- s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
250
- s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
251
- s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
252
- s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
253
- s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
254
nvic_irq_update(s);
255
break;
256
case 0xd28: /* Configurable Fault Status. */
257
--
285
--
258
2.7.4
286
2.20.1
259
287
260
288
diff view generated by jsdifflib