ARM queue: mostly patches from me, but also the Smartfusion2 board.

The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:

Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921

for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:

msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)

* more preparatory work for v8M support

* convert some omap devices away from old_mmio

* remove out of date ARM ARM section references in comments

* add the Smartfusion2 board

Peter Maydell (26):

target/arm: Implement MSR/MRS access to NS banked registers

nvic: Add banked exception states

nvic: Add cached vectpending_is_s_banked state

nvic: Add cached vectpending_prio state

nvic: Implement AIRCR changes for v8M

nvic: Make ICSR.RETTOBASE handle banked exceptions

nvic: Implement NVIC_ITNS<n> registers

nvic: Handle banked exceptions in nvic_recompute_state()

nvic: Make set_pending and clear_pending take a secure parameter

nvic: Make SHPR registers banked

nvic: Compare group priority for escalation to HF

nvic: In escalation to HardFault, support HF not being priority -1

nvic: Implement v8M changes to fixed priority exceptions

nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear

nvic: Handle v8M changes in nvic_exec_prio()

target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()

nvic: Make ICSR banked for v8M

nvic: Make SHCSR banked for v8M

nvic: Support banked exceptions in acknowledge and complete

target/arm: Remove out of date ARM ARM section references in A64 decoder

hw/arm/palm.c: Don't use old_mmio for static_ops

hw/gpio/omap_gpio.c: Don't use old_mmio

hw/timer/omap_synctimer.c: Don't use old_mmio

hw/timer/omap_gptimer: Don't use old_mmio

hw/i2c/omap_i2c.c: Don't use old_mmio

hw/arm/omap2.c: Don't use old_mmio

Subbaraya Sundeep (5):

msf2: Add Smartfusion2 System timer

msf2: Microsemi Smartfusion2 System Register block

msf2: Add Smartfusion2 SPI controller

msf2: Add Smartfusion2 SoC

msf2: Add Emcraft's Smartfusion2 SOM kit

hw/arm/Makefile.objs | 1 +

hw/misc/Makefile.objs | 1 +

hw/ssi/Makefile.objs | 1 +

hw/timer/Makefile.objs | 1 +

include/hw/arm/msf2-soc.h | 67 +++

include/hw/intc/armv7m_nvic.h | 33 +-

include/hw/misc/msf2-sysreg.h | 77 ++++

include/hw/ssi/mss-spi.h | 58 +++

include/hw/timer/mss-timer.h | 64 +++

target/arm/cpu.h | 62 ++-

hw/arm/msf2-soc.c | 238 +++++++++++

hw/arm/msf2-som.c | 105 +++++

hw/arm/omap2.c | 49 ++-

hw/arm/palm.c | 30 +-

hw/gpio/omap_gpio.c | 26 +-

hw/i2c/omap_i2c.c | 44 +-

hw/intc/armv7m_nvic.c | 913 ++++++++++++++++++++++++++++++++++------

hw/misc/msf2-sysreg.c | 160 +++++++

hw/ssi/mss-spi.c | 404 ++++++++++++++++++

hw/timer/mss-timer.c | 289 +++++++++++++

hw/timer/omap_gptimer.c | 49 ++-

hw/timer/omap_synctimer.c | 35 +-

target/arm/cpu.c | 7 +

target/arm/helper.c | 142 ++++++-

target/arm/translate-a64.c | 227 +++++-----

default-configs/arm-softmmu.mak | 1 +

hw/intc/trace-events | 13 +-

hw/misc/trace-events | 5 +

28 files changed, 2735 insertions(+), 367 deletions(-)

create mode 100644 include/hw/arm/msf2-soc.h

create mode 100644 include/hw/misc/msf2-sysreg.h

create mode 100644 include/hw/ssi/mss-spi.h

create mode 100644 include/hw/timer/mss-timer.h

create mode 100644 hw/arm/msf2-soc.c

create mode 100644 hw/arm/msf2-som.c

create mode 100644 hw/misc/msf2-sysreg.c

create mode 100644 hw/ssi/mss-spi.c

create mode 100644 hw/timer/mss-timer.c

From: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Modelled Microsemi's Smartfusion2 SPI controller.

Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20170920201737.25723-4-f4bug@amsat.org

hw/ssi/Makefile.objs | 1 +

include/hw/ssi/mss-spi.h | 58 +++++++

hw/ssi/mss-spi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++

3 files changed, 463 insertions(+)

create mode 100644 include/hw/ssi/mss-spi.h

create mode 100644 hw/ssi/mss-spi.c

diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs

--- a/hw/ssi/Makefile.objs

+++ b/hw/ssi/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o

common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o

common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o

common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o

+common-obj-$(CONFIG_MSF2) += mss-spi.o

obj-$(CONFIG_OMAP) += omap_spi.o

obj-$(CONFIG_IMX) += imx_spi.o

diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h

+++ b/include/hw/ssi/mss-spi.h

+ * Microsemi SmartFusion2 SPI

+ *

+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>

+#ifndef HW_MSS_SPI_H

+#define HW_MSS_SPI_H

+

+#include "hw/sysbus.h"

+#include "hw/ssi/ssi.h"

+#include "qemu/fifo32.h"

+

+#define TYPE_MSS_SPI "mss-spi"

+#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)

+

+#define R_SPI_MAX 16

+

+typedef struct MSSSpiState {

+

+ MemoryRegion mmio;

+

+ qemu_irq irq;

+

+ qemu_irq cs_line;

+

+ SSIBus *spi;

+

+ Fifo32 rx_fifo;

+ Fifo32 tx_fifo;

+

+ int fifo_depth;

+ uint32_t frame_count;

+ bool enabled;

+

+ uint32_t regs[R_SPI_MAX];

+} MSSSpiState;

+

+#endif /* HW_MSS_SPI_H */

diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c

+++ b/hw/ssi/mss-spi.c

+ * Block model of SPI controller present in

+ * Microsemi's SmartFusion2 and SmartFusion SoCs.

+ *

+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>

+#include "hw/ssi/mss-spi.h"

+

+#ifndef MSS_SPI_ERR_DEBUG

+#define MSS_SPI_ERR_DEBUG 0

+#define DB_PRINT_L(lvl, fmt, args...) do { \

+ if (MSS_SPI_ERR_DEBUG >= lvl) { \

+ qemu_log("%s: " fmt "\n", __func__, ## args); \

+ } \

+} while (0);

+

+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)

+

+#define FIFO_CAPACITY 32

+

+#define R_SPI_CONTROL 0

+#define R_SPI_DFSIZE 1

+#define R_SPI_STATUS 2

+#define R_SPI_INTCLR 3

+#define R_SPI_RX 4

+#define R_SPI_TX 5

+#define R_SPI_CLKGEN 6

+#define R_SPI_SS 7

+#define R_SPI_MIS 8

+#define R_SPI_RIS 9

+

+#define S_TXDONE (1 << 0)

+#define S_RXRDY (1 << 1)

+#define S_RXCHOVRF (1 << 2)

+#define S_RXFIFOFUL (1 << 4)

+#define S_RXFIFOFULNXT (1 << 5)

+#define S_RXFIFOEMP (1 << 6)

+#define S_RXFIFOEMPNXT (1 << 7)

+#define S_TXFIFOFUL (1 << 8)

+#define S_TXFIFOFULNXT (1 << 9)

+#define S_TXFIFOEMP (1 << 10)

+#define S_TXFIFOEMPNXT (1 << 11)

+#define S_FRAMESTART (1 << 12)

+#define S_SSEL (1 << 13)

+#define S_ACTIVE (1 << 14)

+

+#define C_ENABLE (1 << 0)

+#define C_MODE (1 << 1)

+#define C_INTRXDATA (1 << 4)

+#define C_INTTXDATA (1 << 5)

+#define C_INTRXOVRFLO (1 << 6)

+#define C_SPS (1 << 26)

+#define C_BIGFIFO (1 << 29)

+#define C_RESET (1 << 31)

+

+#define FRAMESZ_MASK 0x1F

+#define FMCOUNT_MASK 0x00FFFF00

+#define FMCOUNT_SHIFT 8

+

+static void txfifo_reset(MSSSpiState *s)

+{

+ fifo32_reset(&s->tx_fifo);

+

+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;

+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;

+}

+

+static void rxfifo_reset(MSSSpiState *s)

+{

+ fifo32_reset(&s->rx_fifo);

+

+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;

+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;

+}

+

+static void set_fifodepth(MSSSpiState *s)

+{

+ unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;

+

+ if (size <= 8) {

+ s->fifo_depth = 32;

+ } else if (size <= 16) {

+ s->fifo_depth = 16;

+ } else if (size <= 32) {

+ s->fifo_depth = 8;

+ } else {

+ s->fifo_depth = 4;

+ }

+}

+

+static void update_mis(MSSSpiState *s)

+{

+ uint32_t reg = s->regs[R_SPI_CONTROL];

+ uint32_t tmp;

+

+ /*

+ * form the Control register interrupt enable bits

+ * same as RIS, MIS and Interrupt clear registers for simplicity

+ */

+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |

+ ((reg & C_INTTXDATA) >> 5);

+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];

+}

+

+static void spi_update_irq(MSSSpiState *s)

+{

+ int irq;

+

+ update_mis(s);

+ irq = !!(s->regs[R_SPI_MIS]);

+

+ qemu_set_irq(s->irq, irq);

+}

+

+static void mss_spi_reset(DeviceState *d)

+{

+ MSSSpiState *s = MSS_SPI(d);

+

+ memset(s->regs, 0, sizeof s->regs);

+ s->regs[R_SPI_CONTROL] = 0x80000102;

+ s->regs[R_SPI_DFSIZE] = 0x4;

+ s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;

+ s->regs[R_SPI_CLKGEN] = 0x7;

+ s->regs[R_SPI_RIS] = 0x0;

+

+ s->fifo_depth = 4;

+ s->frame_count = 1;

+ s->enabled = false;

+

+ rxfifo_reset(s);

+ txfifo_reset(s);

+}

+

+static uint64_t

+spi_read(void *opaque, hwaddr addr, unsigned int size)

+{

+ MSSSpiState *s = opaque;

+ uint32_t ret = 0;

+

+ addr >>= 2;

+ switch (addr) {

+ case R_SPI_RX:

+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;

+ s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;

+ ret = fifo32_pop(&s->rx_fifo);

+ if (fifo32_is_empty(&s->rx_fifo)) {

+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;

+ }

+ break;

+

+ case R_SPI_MIS:

+ update_mis(s);

+ ret = s->regs[R_SPI_MIS];

+ break;

+

+ default:

+ if (addr < ARRAY_SIZE(s->regs)) {

+ ret = s->regs[addr];

+ } else {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,

+ addr * 4);

+ return ret;

+ }

+ break;

+ }

+

+ DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);

+ spi_update_irq(s);

+ return ret;

+}

+

+static void assert_cs(MSSSpiState *s)

+{

+ qemu_set_irq(s->cs_line, 0);

+}

+

+static void deassert_cs(MSSSpiState *s)

+{

+ qemu_set_irq(s->cs_line, 1);

+}

+

+static void spi_flush_txfifo(MSSSpiState *s)

+{

+ uint32_t tx;

+ uint32_t rx;

+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);

+

+ /*

+ * Chip Select(CS) is automatically controlled by this controller.

+ * If SPS bit is set in Control register then CS is asserted

+ * until all the frames set in frame count of Control register are

+ * transferred. If SPS is not set then CS pulses between frames.

+ * Note that Slave Select register specifies which of the CS line

+ * has to be controlled automatically by controller. Bits SS[7:1] are for

+ * masters in FPGA fabric since we model only Microcontroller subsystem

+ * of Smartfusion2 we control only one CS(SS[0]) line.

+ */

+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {

+ assert_cs(s);

+

+ s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);

+

+ tx = fifo32_pop(&s->tx_fifo);

+ DB_PRINT("data tx:0x%" PRIx32, tx);

+ rx = ssi_transfer(s->spi, tx);

+ DB_PRINT("data rx:0x%" PRIx32, rx);

+

+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {

+ s->regs[R_SPI_STATUS] |= S_RXCHOVRF;

+ s->regs[R_SPI_RIS] |= S_RXCHOVRF;

+ } else {

+ fifo32_push(&s->rx_fifo, rx);

+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;

+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {

+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;

+ } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {

+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;

+ }

+ }

+ s->frame_count--;

+ if (!sps) {

+ deassert_cs(s);

+ }

+ }

+

+ if (!s->frame_count) {

+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>

+ FMCOUNT_SHIFT;

+ deassert_cs(s);

+ s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;

+ s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;

+ }

+}

+

+static void spi_write(void *opaque, hwaddr addr,

+ uint64_t val64, unsigned int size)

+{

+ MSSSpiState *s = opaque;

+ uint32_t value = val64;

+

+ DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);

+ addr >>= 2;

+

+ switch (addr) {

+ case R_SPI_TX:

+ /* adding to already full FIFO */

+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {

+ break;

+ }

+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;

+ fifo32_push(&s->tx_fifo, value);

+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {

+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;

+ } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {

+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;

+ }

+ if (s->enabled) {

+ spi_flush_txfifo(s);

+ }

+ break;

+

+ case R_SPI_CONTROL:

+ s->regs[R_SPI_CONTROL] = value;

+ if (value & C_BIGFIFO) {

+ set_fifodepth(s);

+ } else {

+ s->fifo_depth = 4;

+ }

+ s->enabled = value & C_ENABLE;

+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;

+ if (value & C_RESET) {

+ mss_spi_reset(DEVICE(s));

+ }

+ break;

+

+ case R_SPI_DFSIZE:

+ if (s->enabled) {

+ break;

+ }

+ s->regs[R_SPI_DFSIZE] = value;

+ break;

+

+ case R_SPI_INTCLR:

+ s->regs[R_SPI_INTCLR] = value;

+ if (value & S_TXDONE) {

+ s->regs[R_SPI_RIS] &= ~S_TXDONE;

+ }

+ if (value & S_RXRDY) {

+ s->regs[R_SPI_RIS] &= ~S_RXRDY;

+ }

+ if (value & S_RXCHOVRF) {

+ s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;

+ }

+ break;

+

+ case R_SPI_MIS:

+ case R_SPI_STATUS:

+ case R_SPI_RIS:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Write to read only register 0x%" HWADDR_PRIx "\n",

+ __func__, addr * 4);

+ break;

+

+ default:

+ if (addr < ARRAY_SIZE(s->regs)) {

+ s->regs[addr] = value;

+ } else {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,

+ addr * 4);

+ }

+ break;

+ }

+

+ spi_update_irq(s);

+}

+

+static const MemoryRegionOps spi_ops = {

+ .read = spi_read,

+ .write = spi_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .valid = {

+ .min_access_size = 1,

+ .max_access_size = 4

+static void mss_spi_realize(DeviceState *dev, Error **errp)

+{

+ MSSSpiState *s = MSS_SPI(dev);

+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

+

+ s->spi = ssi_create_bus(dev, "spi");

+

+ sysbus_init_irq(sbd, &s->irq);

+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);

+ sysbus_init_irq(sbd, &s->cs_line);

+

+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,

+ TYPE_MSS_SPI, R_SPI_MAX * 4);

+ sysbus_init_mmio(sbd, &s->mmio);

+

+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);

+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);

+}

+

+static const VMStateDescription vmstate_mss_spi = {

+ .name = TYPE_MSS_SPI,

+ VMSTATE_FIFO32(tx_fifo, MSSSpiState),

+ VMSTATE_FIFO32(rx_fifo, MSSSpiState),

+ VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),

+ VMSTATE_END_OF_LIST()

+static void mss_spi_class_init(ObjectClass *klass, void *data)

+ dc->realize = mss_spi_realize;

+ dc->reset = mss_spi_reset;

+ dc->vmsd = &vmstate_mss_spi;

+}

+

+static const TypeInfo mss_spi_info = {

+ .name = TYPE_MSS_SPI,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(MSSSpiState),

+ .class_init = mss_spi_class_init,

+static void mss_spi_register_types(void)

+{

+ type_register_static(&mss_spi_info);

+}

+

+type_init(mss_spi_register_types)

2.7.4

Update the nvic_recompute_state() code to handle the security

extension and its associated banked registers.

Code that uses the resulting cached state (ie the irq

acknowledge and complete code) will be updated in a later

commit.

hw/intc/armv7m_nvic.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++--

hw/intc/trace-events | 1 +

2 files changed, 147 insertions(+), 5 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

* (higher than the highest possible priority value)

*/

#define NVIC_NOEXC_PRIO 0x100

+/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */

+#define NVIC_NS_PRIO_LIMIT 0x80

static const uint8_t nvic_id[] = {

0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1

@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)

return false;

+static bool exc_is_banked(int exc)

+ /* Return true if this is one of the limited set of exceptions which

+ * are banked (and thus have state in sec_vectors[])

+ */

+ return exc == ARMV7M_EXCP_HARD ||

+ exc == ARMV7M_EXCP_MEM ||

+ exc == ARMV7M_EXCP_USAGE ||

+ exc == ARMV7M_EXCP_SVC ||

+ exc == ARMV7M_EXCP_PENDSV ||

+ exc == ARMV7M_EXCP_SYSTICK;

/* Return a mask word which clears the subpriority bits from

* a priority value for an M-profile exception, leaving only

* the group priority.

*/

-static inline uint32_t nvic_gprio_mask(NVICState *s)

+static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)

+ return ~0U << (s->prigroup[secure] + 1);

+static bool exc_targets_secure(NVICState *s, int exc)

+{

+ /* Return true if this non-banked exception targets Secure state. */

+ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {

+ return false;

+ }

+ if (exc >= NVIC_FIRST_IRQ) {

+ return !s->itns[exc];

+ }

+ /* Function shouldn't be called for banked exceptions. */

+ assert(!exc_is_banked(exc));

+

+ switch (exc) {

+ case ARMV7M_EXCP_NMI:

+ case ARMV7M_EXCP_BUS:

+ return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);

+ case ARMV7M_EXCP_SECURE:

+ return true;

+ case ARMV7M_EXCP_DEBUG:

+ /* TODO: controlled by DEMCR.SDME, which we don't yet implement */

+ return false;

+ default:

+ /* reset, and reserved (unused) low exception numbers.

+ * We'll get called by code that loops through all the exception

+ * numbers, but it doesn't matter what we return here as these

+ * non-existent exceptions will never be pended or active.

+ */

+ return true;

+ }

+static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)

+ /* Return the group priority for this exception, given its raw

+ * (group-and-subgroup) priority value and whether it is targeting

+ * secure state or not.

+ */

+ if (rawprio < 0) {

+ return rawprio;

+ }

+ rawprio &= nvic_gprio_mask(s, targets_secure);

+ /* AIRCR.PRIS causes us to squash all NS priorities into the

+ * lower half of the total range

+ */

+ if (!targets_secure &&

+ (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {

+ rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;

+ }

+ return rawprio;

+/* Recompute vectpending and exception_prio for a CPU which implements

+ * the Security extension

+ */

+static void nvic_recompute_state_secure(NVICState *s)

{

- return ~0U << (s->prigroup[M_REG_NS] + 1);

+ int i, bank;

+ int pend_prio = NVIC_NOEXC_PRIO;

+ int active_prio = NVIC_NOEXC_PRIO;

+ int pend_irq = 0;

+ bool pending_is_s_banked = false;

+ /* R_CQRV: precedence is by:

+ * - lowest group priority; if both the same then

+ * - lowest subpriority; if both the same then

+ * - lowest exception number; if both the same (ie banked) then

+ * - secure exception takes precedence

+ * Compare pseudocode RawExecutionPriority.

+ * Annoyingly, now we have two prigroup values (for S and NS)

+ * we can't do the loop comparison on raw priority values.

+ for (i = 1; i < s->num_irq; i++) {

+ for (bank = M_REG_S; bank >= M_REG_NS; bank--) {

+ VecInfo *vec;

+ int prio;

+ bool targets_secure;

+ if (bank == M_REG_S) {

+ if (!exc_is_banked(i)) {

+ continue;

+ }

+ vec = &s->sec_vectors[i];

+ targets_secure = true;

+ } else {

+ vec = &s->vectors[i];

+ targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);

+ }

+ prio = exc_group_prio(s, vec->prio, targets_secure);

+ if (vec->enabled && vec->pending && prio < pend_prio) {

+ pend_prio = prio;

+ pend_irq = i;

+ pending_is_s_banked = (bank == M_REG_S);

+ }

+ if (vec->active && prio < active_prio) {

+ active_prio = prio;

+ }

+ }

+ }

+

+ s->vectpending_is_s_banked = pending_is_s_banked;

+ s->vectpending = pend_irq;

+ s->vectpending_prio = pend_prio;

+ s->exception_prio = active_prio;

+

+ trace_nvic_recompute_state_secure(s->vectpending,

+ s->vectpending_is_s_banked,

+ s->vectpending_prio,

+ s->exception_prio);

}

/* Recompute vectpending and exception_prio */

@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)

int active_prio = NVIC_NOEXC_PRIO;

int pend_irq = 0;

+ /* In theory we could write one function that handled both

+ * the "security extension present" and "not present"; however

+ * the security related changes significantly complicate the

+ * recomputation just by themselves and mixing both cases together

+ * would be even worse, so we retain a separate non-secure-only

+ * version for CPUs which don't implement the security extension.

+ */

+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {

+ nvic_recompute_state_secure(s);

+ return;

+ }

+

for (i = 1; i < s->num_irq; i++) {

VecInfo *vec = &s->vectors[i];

@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)

}

if (active_prio > 0) {

- active_prio &= nvic_gprio_mask(s);

+ active_prio &= nvic_gprio_mask(s, false);

}

if (pend_prio > 0) {

- pend_prio &= nvic_gprio_mask(s);

+ pend_prio &= nvic_gprio_mask(s, false);

}

s->vectpending = pend_irq;

@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)

} else if (env->v7m.primask[env->v7m.secure]) {

running = 0;

} else if (env->v7m.basepri[env->v7m.secure] > 0) {

- running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);

+ running = env->v7m.basepri[env->v7m.secure] &

+ nvic_gprio_mask(s, env->v7m.secure);

} else {

running = NVIC_NOEXC_PRIO; /* lower than any possible priority */

}

diff --git a/hw/intc/trace-events b/hw/intc/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/trace-events

+++ b/hw/intc/trace-events

@@ -XXX,XX +XXX,XX @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending S

# hw/intc/armv7m_nvic.c

nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d"

+nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d"

nvic_set_prio(int irq, uint8_t prio) "NVIC set irq %d priority %d"

nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"

nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"

2.7.4

Handle banking of SHCSR: some register bits are banked between

Secure and Non-Secure, and some are only accessible to Secure.

hw/intc/armv7m_nvic.c | 221 ++++++++++++++++++++++++++++++++++++++------------

1 file changed, 169 insertions(+), 52 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

val = cpu->env.v7m.ccr[attrs.secure];

val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;

return val;

- case 0xd24: /* System Handler Status. */

+ case 0xd24: /* System Handler Control and State (SHCSR) */

val = 0;

- if (s->vectors[ARMV7M_EXCP_MEM].active) {

- val |= (1 << 0);

- }

- if (s->vectors[ARMV7M_EXCP_BUS].active) {

- val |= (1 << 1);

- }

- if (s->vectors[ARMV7M_EXCP_USAGE].active) {

- val |= (1 << 3);

+ if (attrs.secure) {

+ if (s->sec_vectors[ARMV7M_EXCP_MEM].active) {

+ val |= (1 << 0);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_HARD].active) {

+ val |= (1 << 2);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) {

+ val |= (1 << 3);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {

+ val |= (1 << 7);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) {

+ val |= (1 << 10);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) {

+ val |= (1 << 11);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {

+ val |= (1 << 12);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {

+ val |= (1 << 13);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {

+ val |= (1 << 15);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) {

+ val |= (1 << 16);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) {

+ val |= (1 << 18);

+ }

+ if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {

+ val |= (1 << 21);

+ }

+ /* SecureFault is not banked but is always RAZ/WI to NS */

+ if (s->vectors[ARMV7M_EXCP_SECURE].active) {

+ val |= (1 << 4);

+ }

+ if (s->vectors[ARMV7M_EXCP_SECURE].enabled) {

+ val |= (1 << 19);

+ }

+ if (s->vectors[ARMV7M_EXCP_SECURE].pending) {

+ val |= (1 << 20);

+ }

+ } else {

+ if (s->vectors[ARMV7M_EXCP_MEM].active) {

+ val |= (1 << 0);

+ }

+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {

+ /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */

+ if (s->vectors[ARMV7M_EXCP_HARD].active) {

+ val |= (1 << 2);

+ }

+ if (s->vectors[ARMV7M_EXCP_HARD].pending) {

+ val |= (1 << 21);

+ }

+ }

+ if (s->vectors[ARMV7M_EXCP_USAGE].active) {

+ val |= (1 << 3);

+ }

+ if (s->vectors[ARMV7M_EXCP_SVC].active) {

+ val |= (1 << 7);

+ }

+ if (s->vectors[ARMV7M_EXCP_PENDSV].active) {

+ val |= (1 << 10);

+ }

+ if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {

+ val |= (1 << 11);

+ }

+ if (s->vectors[ARMV7M_EXCP_USAGE].pending) {

+ val |= (1 << 12);

+ }

+ if (s->vectors[ARMV7M_EXCP_MEM].pending) {

+ val |= (1 << 13);

+ }

+ if (s->vectors[ARMV7M_EXCP_SVC].pending) {

+ val |= (1 << 15);

+ }

+ if (s->vectors[ARMV7M_EXCP_MEM].enabled) {

+ val |= (1 << 16);

+ }

+ if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {

+ val |= (1 << 18);

+ }

}

- if (s->vectors[ARMV7M_EXCP_SVC].active) {

- val |= (1 << 7);

+ if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {

+ if (s->vectors[ARMV7M_EXCP_BUS].active) {

+ val |= (1 << 1);

+ }

+ if (s->vectors[ARMV7M_EXCP_BUS].pending) {

+ val |= (1 << 14);

+ }

+ if (s->vectors[ARMV7M_EXCP_BUS].enabled) {

+ val |= (1 << 17);

+ }

+ if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&

+ s->vectors[ARMV7M_EXCP_NMI].active) {

+ /* NMIACT is not present in v7M */

+ val |= (1 << 5);

+ }

}

+ /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */

if (s->vectors[ARMV7M_EXCP_DEBUG].active) {

val |= (1 << 8);

}

- if (s->vectors[ARMV7M_EXCP_PENDSV].active) {

- val |= (1 << 10);

- }

- if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {

- val |= (1 << 11);

- }

- if (s->vectors[ARMV7M_EXCP_USAGE].pending) {

- val |= (1 << 12);

- }

- if (s->vectors[ARMV7M_EXCP_MEM].pending) {

- val |= (1 << 13);

- }

- if (s->vectors[ARMV7M_EXCP_BUS].pending) {

- val |= (1 << 14);

- }

- if (s->vectors[ARMV7M_EXCP_SVC].pending) {

- val |= (1 << 15);

- }

- if (s->vectors[ARMV7M_EXCP_MEM].enabled) {

- val |= (1 << 16);

- }

- if (s->vectors[ARMV7M_EXCP_BUS].enabled) {

- val |= (1 << 17);

- }

- if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {

- val |= (1 << 18);

- }

return val;

case 0xd28: /* Configurable Fault Status. */

/* The BFSR bits [15:8] are shared between security states

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

cpu->env.v7m.ccr[attrs.secure] = value;

break;

- case 0xd24: /* System Handler Control. */

- s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;

- s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;

- s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;

- s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;

+ case 0xd24: /* System Handler Control and State (SHCSR) */

+ if (attrs.secure) {

+ s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;

+ /* Secure HardFault active bit cannot be written */

+ s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_PENDSV].active =

+ (value & (1 << 10)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =

+ (value & (1 << 11)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_USAGE].pending =

+ (value & (1 << 12)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;

+ s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =

+ (value & (1 << 18)) != 0;

+ /* SecureFault not banked, but RAZ/WI to NS */

+ s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;

+ s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;

+ s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;

+ } else {

+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;

+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {

+ /* HARDFAULTPENDED is not present in v7M */

+ s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;

+ }

+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;

+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;

+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;

+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;

+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;

+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;

+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;

+ s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;

+ s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;