[Qemu-devel] [PULL 00/18] target-arm queue
[PULL 00/35] target-arm queue
1
ARM queue: nothing particularly exciting, but 18 patches
1
The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
2
is enough to send out.
3
2
4
thanks
3
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
5
-- PMM
6
4
7
The following changes since commit 3dabde1128b671f36ac6cb36b97b273139964420:
5
are available in the Git repository at:
8
6
9
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20170914' into staging (2017-09-14 16:33:02 +0100)
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
10
8
11
are available in the git repository at:
9
for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
12
10
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170914
11
docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
14
15
for you to fetch changes up to ce3bc112cdb1d462e2d52eaa17a7314e7f3af504:
16
17
mps2-an511: Fix wiring of UART overflow interrupt lines (2017-09-14 18:43:19 +0100)
18
12
19
----------------------------------------------------------------
13
----------------------------------------------------------------
20
target-arm queue:
14
target-arm queue:
21
* v7M: various code cleanups
15
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
22
* v7M: set correct BFSR bits on bus fault
16
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
23
* v7M: clear exclusive monitor on reset and exception entry/exit
17
* Fix some errors in SVE/SME handling of MTE tags
24
* v7M: don't apply priority mask to negative priorities
18
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
25
* zcu102: support 'secure' and 'virtualization' machine properties
19
* hw/block/tc58128: Don't emit deprecation warning under qtest
26
* aarch64: fix ERET single stepping
20
* tests/qtest: Fix handling of npcm7xx and GMAC tests
27
* gpex: implement PCI INTx routing
21
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
28
* mps2-an511: fix UART overflow interrupt line wiring
22
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
23
* Don't assert on vmload/vmsave of M-profile CPUs
24
* hw/arm/smmuv3: add support for stage 1 access fault
25
* hw/arm/stellaris: QOM cleanups
26
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
27
* Improve Cortex_R52 IMPDEF sysreg modelling
28
* Allow access to SPSR_hyp from hyp mode
29
* New board model mps3-an536 (Cortex-R52)
29
30
30
----------------------------------------------------------------
31
----------------------------------------------------------------
31
Alistair Francis (5):
32
Luc Michel (1):
32
xlnx-ep108: Rename to ZCU102
33
hw/arm/smmuv3: add support for stage 1 access fault
33
xlnx-zcu102: Manually create the machines
34
xlnx-zcu102: Add a machine level secure property
35
xlnx-zcu102: Add a machine level virtualization property
36
xlnx-zcu102: Mark the EP108 machine as deprecated
37
34
38
Jaroslaw Pelczar (1):
35
Nabih Estefan (1):
39
AArch64: Fix single stepping of ERET instruction
36
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
40
37
41
Peter Maydell (8):
38
Peter Maydell (22):
42
target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2
39
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
43
target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
40
hw/block/tc58128: Don't emit deprecation warning under qtest
44
target/arm: Get PRECISERR and IBUSERR the right way round
41
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
45
nvic: Don't apply group priority mask to negative priorities
42
tests/qtest/bios-tables-test: Allow changes to virt GTDT
46
target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()
43
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
47
target/arm: Add and use defines for EXCRET constants
44
tests/qtest/bios-tables-tests: Update virt golden reference
48
target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()
45
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
49
mps2-an511: Fix wiring of UART overflow interrupt lines
46
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
47
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
48
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
49
target/arm: The Cortex-R52 has a read-only CBAR
50
target/arm: Add Cortex-R52 IMPDEF sysregs
51
target/arm: Allow access to SPSR_hyp from hyp mode
52
hw/misc/mps2-scc: Fix condition for CFG3 register
53
hw/misc/mps2-scc: Factor out which-board conditionals
54
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
55
hw/arm/mps3r: Initial skeleton for mps3-an536 board
56
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
57
hw/arm/mps3r: Add UARTs
58
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
59
hw/arm/mps3r: Add remaining devices
60
docs: Add documentation for the mps3-an536 board
50
61
51
Pranavkumar Sawargaonkar (3):
62
Philippe Mathieu-Daudé (5):
52
hw/pci-host/gpex: Set INTx index/gsi mapping
63
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
53
hw/arm/virt: Set INTx/gsi mapping
64
hw/arm/stellaris: Convert ADC controller to Resettable interface
54
hw/pci-host/gpex: Implement PCI INTx routing
65
hw/arm/stellaris: Convert I2C controller to Resettable interface
66
hw/arm/stellaris: Add missing QOM 'machine' parent
67
hw/arm/stellaris: Add missing QOM 'SoC' parent
55
68
56
Richard Henderson (1):
69
Richard Henderson (6):
57
target/arm: Avoid an extra temporary for store_exclusive
70
linux-user/aarch64: Choose SYNC as the preferred MTE mode
71
target/arm: Fix nregs computation in do_{ld,st}_zpa
72
target/arm: Adjust and validate mtedesc sizem1
73
target/arm: Split out make_svemte_desc
74
target/arm: Handle mte in do_ldrq, do_ldro
75
target/arm: Fix SVE/SME gross MTE suppression checks
58
76
59
hw/arm/Makefile.objs | 2 +-
77
MAINTAINERS | 3 +-
60
include/hw/arm/xlnx-zynqmp.h | 2 +
78
docs/system/arm/mps2.rst | 37 +-
61
include/hw/pci-host/gpex.h | 3 +
79
configs/devices/arm-softmmu/default.mak | 1 +
62
target/arm/cpu.h | 35 +++---
80
hw/arm/smmuv3-internal.h | 1 +
63
target/arm/internals.h | 20 ++++
81
include/hw/arm/smmu-common.h | 1 +
64
hw/arm/mps2.c | 4 +-
82
include/hw/arm/virt.h | 2 +
65
hw/arm/virt.c | 1 +
83
include/hw/misc/mps2-scc.h | 1 +
66
hw/arm/xlnx-ep108.c | 139 -----------------------
84
linux-user/aarch64/target_prctl.h | 29 +-
67
hw/arm/xlnx-zcu102.c | 259 +++++++++++++++++++++++++++++++++++++++++++
85
target/arm/internals.h | 2 +-
68
hw/arm/xlnx-zynqmp.c | 3 +-
86
target/arm/tcg/translate-a64.h | 2 +
69
hw/intc/armv7m_nvic.c | 11 +-
87
hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++
70
hw/pci-host/gpex.c | 22 ++++
88
hw/arm/npcm7xx.c | 1 +
71
target/arm/cpu.c | 6 +
89
hw/arm/smmu-common.c | 11 +
72
target/arm/helper.c | 43 ++++---
90
hw/arm/smmuv3.c | 1 +
73
target/arm/op_helper.c | 2 +-
91
hw/arm/stellaris.c | 47 ++-
74
target/arm/translate-a64.c | 27 ++---
92
hw/arm/virt-acpi-build.c | 20 +-
75
16 files changed, 382 insertions(+), 197 deletions(-)
93
hw/arm/virt.c | 60 ++-
76
delete mode 100644 hw/arm/xlnx-ep108.c
94
hw/arm/xilinx_zynq.c | 2 +
77
create mode 100644 hw/arm/xlnx-zcu102.c
95
hw/block/tc58128.c | 4 +-
96
hw/misc/mps2-scc.c | 138 ++++++-
97
hw/pci-host/raven.c | 1 +
98
target/arm/helper.c | 14 +-
99
target/arm/tcg/cpu32.c | 109 ++++++
100
target/arm/tcg/op_helper.c | 43 ++-
101
target/arm/tcg/sme_helper.c | 8 +-
102
target/arm/tcg/sve_helper.c | 12 +-
103
target/arm/tcg/translate-sme.c | 15 +-
104
target/arm/tcg/translate-sve.c | 83 +++--
105
target/arm/tcg/translate.c | 19 +-
106
tests/qtest/npcm7xx_emc-test.c | 5 +-
107
tests/qtest/npcm_gmac-test.c | 84 +----
108
hw/arm/Kconfig | 5 +
109
hw/arm/meson.build | 1 +
110
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
111
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
112
tests/qtest/meson.build | 4 +-
113
36 files changed, 1184 insertions(+), 222 deletions(-)
114
create mode 100644 hw/arm/mps3r.c
78
115
diff view generated by jsdifflib
New patch
[PULL 01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
4
connect FIQ output of the GIC CPU interfaces to the CPU.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240130152548.17855-1-philmd@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/xilinx_zynq.c | 2 ++
12
1 file changed, 2 insertions(+)
13
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xilinx_zynq.c
17
+++ b/hw/arm/xilinx_zynq.c
18
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
19
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
20
sysbus_connect_irq(busdev, 0,
21
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
22
+ sysbus_connect_irq(busdev, 1,
23
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
24
25
for (n = 0; n < 64; n++) {
26
pic[n] = qdev_get_gpio_in(dev, n);
27
--
28
2.34.1
29
30
diff view generated by jsdifflib
New patch
[PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The API does not generate an error for setting ASYNC | SYNC; that merely
4
constrains the selection vs the per-cpu default. For qemu linux-user,
5
choose SYNC as the default.
6
7
Cc: qemu-stable@nongnu.org
8
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
11
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
15
1 file changed, 17 insertions(+), 12 deletions(-)
16
17
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/linux-user/aarch64/target_prctl.h
20
+++ b/linux-user/aarch64/target_prctl.h
21
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
22
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
23
24
if (cpu_isar_feature(aa64_mte, cpu)) {
25
- switch (arg2 & PR_MTE_TCF_MASK) {
26
- case PR_MTE_TCF_NONE:
27
- case PR_MTE_TCF_SYNC:
28
- case PR_MTE_TCF_ASYNC:
29
- break;
30
- default:
31
- return -EINVAL;
32
- }
33
-
34
/*
35
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
36
- * Note that the syscall values are consistent with hw.
37
+ *
38
+ * The kernel has a per-cpu configuration for the sysadmin,
39
+ * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
40
+ * which qemu does not implement.
41
+ *
42
+ * Because there is no performance difference between the modes, and
43
+ * because SYNC is most useful for debugging MTE errors, choose SYNC
44
+ * as the preferred mode. With this preference, and the way the API
45
+ * uses only two bits, there is no way for the program to select
46
+ * ASYMM mode.
47
*/
48
- env->cp15.sctlr_el[1] =
49
- deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
50
+ unsigned tcf = 0;
51
+ if (arg2 & PR_MTE_TCF_SYNC) {
52
+ tcf = 1;
53
+ } else if (arg2 & PR_MTE_TCF_ASYNC) {
54
+ tcf = 2;
55
+ }
56
+ env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
57
58
/*
59
* Write PR_MTE_TAG to GCR_EL1[Exclude].
60
--
61
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The field is encoded as [0-3], which is convenient for
4
indexing our array of function pointers, but the true
5
value is [1-4]. Adjust before calling do_mem_zpa.
6
7
Add an assert, and move the comment re passing ZT to
8
the helper back next to the relevant code.
9
10
Cc: qemu-stable@nongnu.org
11
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
14
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/tcg/translate-sve.c | 16 ++++++++--------
19
1 file changed, 8 insertions(+), 8 deletions(-)
20
21
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/tcg/translate-sve.c
24
+++ b/target/arm/tcg/translate-sve.c
25
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
26
TCGv_ptr t_pg;
27
int desc = 0;
28
29
- /*
30
- * For e.g. LD4, there are not enough arguments to pass all 4
31
- * registers as pointers, so encode the regno into the data field.
32
- * For consistency, do this even for LD1.
33
- */
34
+ assert(mte_n >= 1 && mte_n <= 4);
35
if (s->mte_active[0]) {
36
int msz = dtype_msz(dtype);
37
38
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
39
addr = clean_data_tbi(s, addr);
40
}
41
42
+ /*
43
+ * For e.g. LD4, there are not enough arguments to pass all 4
44
+ * registers as pointers, so encode the regno into the data field.
45
+ * For consistency, do this even for LD1.
46
+ */
47
desc = simd_desc(vsz, vsz, zt | desc);
48
t_pg = tcg_temp_new_ptr();
49
50
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
51
* accessible via the instruction encoding.
52
*/
53
assert(fn != NULL);
54
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
55
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
56
}
57
58
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
59
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
60
if (nreg == 0) {
61
/* ST1 */
62
fn = fn_single[s->mte_active[0]][be][msz][esz];
63
- nreg = 1;
64
} else {
65
/* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
66
assert(msz == esz);
67
fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
68
}
69
assert(fn != NULL);
70
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
71
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
72
}
73
74
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
75
--
76
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/18] target/arm: Add and use defines for EXCRET constants
[PULL 04/35] target/arm: Adjust and validate mtedesc sizem1
1
The exception-return magic values get some new bits in v8M, which
1
From: Richard Henderson <richard.henderson@linaro.org>
2
makes some bit definitions for them worthwhile.
3
2
4
We don't use the bit definitions for the switch on the low bits
3
When we added SVE_MTEDESC_SHIFT, we effectively limited the
5
which checks the return type for v7M, because this is defined
4
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
6
in the v7M ARM ARM as a set of valid values rather than via
5
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
7
per-bit checks.
6
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
8
7
8
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11
Message-id: 1505137930-13255-7-git-send-email-peter.maydell@linaro.org
12
---
14
---
13
target/arm/internals.h | 10 ++++++++++
15
target/arm/internals.h | 2 +-
14
target/arm/helper.c | 14 +++++++++-----
16
target/arm/tcg/translate-sve.c | 7 ++++---
15
2 files changed, 19 insertions(+), 5 deletions(-)
17
2 files changed, 5 insertions(+), 4 deletions(-)
16
18
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
21
--- a/target/arm/internals.h
20
+++ b/target/arm/internals.h
22
+++ b/target/arm/internals.h
21
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CONTROL, NPRIV, 0, 1)
23
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2)
22
FIELD(V7M_CONTROL, SPSEL, 1, 1)
24
FIELD(MTEDESC, TCMA, 6, 2)
23
FIELD(V7M_CONTROL, FPCA, 2, 1)
25
FIELD(MTEDESC, WRITE, 8, 1)
24
26
FIELD(MTEDESC, ALIGN, 9, 3)
25
+/* Bit definitions for v7M exception return payload */
27
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
26
+FIELD(V7M_EXCRET, ES, 0, 1)
28
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */
27
+FIELD(V7M_EXCRET, RES0, 1, 1)
29
28
+FIELD(V7M_EXCRET, SPSEL, 2, 1)
30
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
29
+FIELD(V7M_EXCRET, MODE, 3, 1)
31
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
30
+FIELD(V7M_EXCRET, FTYPE, 4, 1)
32
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
31
+FIELD(V7M_EXCRET, DCRS, 5, 1)
32
+FIELD(V7M_EXCRET, S, 6, 1)
33
+FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
34
+
35
/*
36
* For AArch64, map a given EL to an index in the banked_spsr array.
37
* Note that this mapping and the AArch32 mapping defined in bank_number()
38
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/helper.c
34
--- a/target/arm/tcg/translate-sve.c
41
+++ b/target/arm/helper.c
35
+++ b/target/arm/tcg/translate-sve.c
42
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
36
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
43
" previous exception %d\n",
37
{
44
type, env->v7m.exception);
38
unsigned vsz = vec_full_reg_size(s);
45
39
TCGv_ptr t_pg;
46
- if (extract32(type, 5, 23) != extract32(-1, 5, 23)) {
40
+ uint32_t sizem1;
47
+ if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
41
int desc = 0;
48
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
42
49
"exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);
43
assert(mte_n >= 1 && mte_n <= 4);
50
}
44
+ sizem1 = (mte_n << dtype_msz(dtype)) - 1;
51
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
45
+ assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
52
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
46
if (s->mte_active[0]) {
53
*/
47
- int msz = dtype_msz(dtype);
54
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
48
-
55
- int es = type & 1;
49
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
56
+ int es = type & R_V7M_EXCRET_ES_MASK;
50
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
57
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
51
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
58
env->v7m.faultmask[es] = 0;
52
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
59
}
53
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
60
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
54
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
61
return; /* Never happens. Keep compiler happy. */
55
desc <<= SVE_MTEDESC_SHIFT;
62
}
56
} else {
63
57
addr = clean_data_tbi(s, addr);
64
- lr = 0xfffffff1;
65
+ lr = R_V7M_EXCRET_RES1_MASK |
66
+ R_V7M_EXCRET_S_MASK |
67
+ R_V7M_EXCRET_DCRS_MASK |
68
+ R_V7M_EXCRET_FTYPE_MASK |
69
+ R_V7M_EXCRET_ES_MASK;
70
if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
71
- lr |= 4;
72
+ lr |= R_V7M_EXCRET_SPSEL_MASK;
73
}
74
if (!arm_v7m_is_handler_mode(env)) {
75
- lr |= 8;
76
+ lr |= R_V7M_EXCRET_MODE_MASK;
77
}
78
79
v7m_push_stack(cpu);
80
--
58
--
81
2.7.4
59
2.34.1
82
83
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/18] target/arm: Avoid an extra temporary for store_exclusive
[PULL 05/35] target/arm: Split out make_svemte_desc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Instead of copying addr to a local temp, reuse the value (which we
3
Share code that creates mtedesc and embeds within simd_desc.
4
have just compared as equal) already saved in cpu_exclusive_addr.
5
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
8
Message-id: 20170908163859.29820-1-richard.henderson@linaro.org
9
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-a64.c | 26 +++++++++-----------------
12
target/arm/tcg/translate-a64.h | 2 ++
12
1 file changed, 9 insertions(+), 17 deletions(-)
13
target/arm/tcg/translate-sme.c | 15 +++--------
14
target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
15
3 files changed, 31 insertions(+), 33 deletions(-)
13
16
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
19
--- a/target/arm/tcg/translate-a64.h
17
+++ b/target/arm/translate-a64.c
20
+++ b/target/arm/tcg/translate-a64.h
18
@@ -XXX,XX +XXX,XX @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
21
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
22
bool sve_access_check(DisasContext *s);
23
bool sme_enabled_check(DisasContext *s);
24
bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
25
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
26
+ uint32_t msz, bool is_write, uint32_t data);
27
28
/* This function corresponds to CheckStreamingSVEEnabled. */
29
static inline bool sme_sm_enabled_check(DisasContext *s)
30
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/tcg/translate-sme.c
33
+++ b/target/arm/tcg/translate-sme.c
34
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
35
36
TCGv_ptr t_za, t_pg;
37
TCGv_i64 addr;
38
- int svl, desc = 0;
39
+ uint32_t desc;
40
bool be = s->be_data == MO_BE;
41
bool mte = s->mte_active[0];
42
43
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
44
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
45
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
46
47
- if (mte) {
48
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
49
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
50
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
51
- desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
52
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
53
- desc <<= SVE_MTEDESC_SHIFT;
54
- } else {
55
+ if (!mte) {
56
addr = clean_data_tbi(s, addr);
57
}
58
- svl = streaming_vec_reg_size(s);
59
- desc = simd_desc(svl, svl, desc);
60
+
61
+ desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
62
63
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
64
tcg_constant_i32(desc));
65
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/tcg/translate-sve.c
68
+++ b/target/arm/tcg/translate-sve.c
69
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
70
3, 2, 1, 3
71
};
72
73
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
74
- int dtype, uint32_t mte_n, bool is_write,
75
- gen_helper_gvec_mem *fn)
76
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
77
+ uint32_t msz, bool is_write, uint32_t data)
78
{
79
- unsigned vsz = vec_full_reg_size(s);
80
- TCGv_ptr t_pg;
81
uint32_t sizem1;
82
- int desc = 0;
83
+ uint32_t desc = 0;
84
85
- assert(mte_n >= 1 && mte_n <= 4);
86
- sizem1 = (mte_n << dtype_msz(dtype)) - 1;
87
+ /* Assert all of the data fits, with or without MTE enabled. */
88
+ assert(nregs >= 1 && nregs <= 4);
89
+ sizem1 = (nregs << msz) - 1;
90
assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
91
+ assert(data < 1u << SVE_MTEDESC_SHIFT);
92
+
93
if (s->mte_active[0]) {
94
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
95
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
96
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
97
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
98
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
99
desc <<= SVE_MTEDESC_SHIFT;
100
- } else {
101
+ }
102
+ return simd_desc(vsz, vsz, desc | data);
103
+}
104
+
105
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
106
+ int dtype, uint32_t nregs, bool is_write,
107
+ gen_helper_gvec_mem *fn)
108
+{
109
+ TCGv_ptr t_pg;
110
+ uint32_t desc;
111
+
112
+ if (!s->mte_active[0]) {
113
addr = clean_data_tbi(s, addr);
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
117
* registers as pointers, so encode the regno into the data field.
118
* For consistency, do this even for LD1.
119
*/
120
- desc = simd_desc(vsz, vsz, zt | desc);
121
+ desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
122
+ dtype_msz(dtype), is_write, zt);
123
t_pg = tcg_temp_new_ptr();
124
125
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
126
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
127
int scale, TCGv_i64 scalar, int msz, bool is_write,
128
gen_helper_gvec_mem_scatter *fn)
129
{
130
- unsigned vsz = vec_full_reg_size(s);
131
TCGv_ptr t_zm = tcg_temp_new_ptr();
132
TCGv_ptr t_pg = tcg_temp_new_ptr();
133
TCGv_ptr t_zt = tcg_temp_new_ptr();
134
- int desc = 0;
135
-
136
- if (s->mte_active[0]) {
137
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
138
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
139
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
140
- desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
141
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
142
- desc <<= SVE_MTEDESC_SHIFT;
143
- }
144
- desc = simd_desc(vsz, vsz, desc | scale);
145
+ uint32_t desc;
146
147
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
148
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
149
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
150
+
151
+ desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
152
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
19
}
153
}
20
154
21
static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
22
- TCGv_i64 inaddr, int size, int is_pair)
23
+ TCGv_i64 addr, int size, int is_pair)
24
{
25
/* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
26
* && (!is_pair || env->exclusive_high == [addr + datasize])) {
27
@@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
28
*/
29
TCGLabel *fail_label = gen_new_label();
30
TCGLabel *done_label = gen_new_label();
31
- TCGv_i64 addr = tcg_temp_local_new_i64();
32
TCGv_i64 tmp;
33
34
- /* Copy input into a local temp so it is not trashed when the
35
- * basic block ends at the branch insn.
36
- */
37
- tcg_gen_mov_i64(addr, inaddr);
38
tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
39
40
tmp = tcg_temp_new_i64();
41
@@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
42
} else {
43
tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt));
44
}
45
- tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp,
46
+ tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,
47
+ cpu_exclusive_val, tmp,
48
get_mem_index(s),
49
MO_64 | MO_ALIGN | s->be_data);
50
tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
51
} else if (s->be_data == MO_LE) {
52
- gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt),
53
- cpu_reg(s, rt2));
54
+ gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr,
55
+ cpu_reg(s, rt), cpu_reg(s, rt2));
56
} else {
57
- gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, rt),
58
- cpu_reg(s, rt2));
59
+ gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr,
60
+ cpu_reg(s, rt), cpu_reg(s, rt2));
61
}
62
} else {
63
- TCGv_i64 val = cpu_reg(s, rt);
64
- tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val,
65
- get_mem_index(s),
66
+ tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,
67
+ cpu_reg(s, rt), get_mem_index(s),
68
size | MO_ALIGN | s->be_data);
69
tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
70
}
71
-
72
- tcg_temp_free_i64(addr);
73
-
74
tcg_gen_mov_i64(cpu_reg(s, rd), tmp);
75
tcg_temp_free_i64(tmp);
76
tcg_gen_br(done_label);
77
--
155
--
78
2.7.4
156
2.34.1
79
80
diff view generated by jsdifflib
New patch
[PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
These functions "use the standard load helpers", but
4
fail to clean_data_tbi or populate mtedesc.
5
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
10
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
14
1 file changed, 13 insertions(+), 2 deletions(-)
15
16
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/tcg/translate-sve.c
19
+++ b/target/arm/tcg/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
21
unsigned vsz = vec_full_reg_size(s);
22
TCGv_ptr t_pg;
23
int poff;
24
+ uint32_t desc;
25
26
/* Load the first quadword using the normal predicated load helpers. */
27
+ if (!s->mte_active[0]) {
28
+ addr = clean_data_tbi(s, addr);
29
+ }
30
+
31
poff = pred_full_reg_offset(s, pg);
32
if (vsz > 16) {
33
/*
34
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
35
36
gen_helper_gvec_mem *fn
37
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
38
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
39
+ desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
40
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
41
42
/* Replicate that first quadword. */
43
if (vsz > 16) {
44
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
45
unsigned vsz_r32;
46
TCGv_ptr t_pg;
47
int poff, doff;
48
+ uint32_t desc;
49
50
if (vsz < 32) {
51
/*
52
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
53
}
54
55
/* Load the first octaword using the normal predicated load helpers. */
56
+ if (!s->mte_active[0]) {
57
+ addr = clean_data_tbi(s, addr);
58
+ }
59
60
poff = pred_full_reg_offset(s, pg);
61
if (vsz > 32) {
62
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
63
64
gen_helper_gvec_mem *fn
65
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
66
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
67
+ desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
68
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
69
70
/*
71
* Replicate that first octaword.
72
--
73
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/35] target/arm: Fix SVE/SME gross MTE suppression checks
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The TBI and TCMA bits are located within mtedesc, not desc.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/tcg/sme_helper.c | 8 ++++----
13
target/arm/tcg/sve_helper.c | 12 ++++++------
14
2 files changed, 10 insertions(+), 10 deletions(-)
15
16
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/tcg/sme_helper.c
19
+++ b/target/arm/tcg/sme_helper.c
20
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
21
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
22
23
/* Perform gross MTE suppression early. */
24
- if (!tbi_check(desc, bit55) ||
25
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
26
+ if (!tbi_check(mtedesc, bit55) ||
27
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
28
mtedesc = 0;
29
}
30
31
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
32
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
33
34
/* Perform gross MTE suppression early. */
35
- if (!tbi_check(desc, bit55) ||
36
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
37
+ if (!tbi_check(mtedesc, bit55) ||
38
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
39
mtedesc = 0;
40
}
41
42
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/tcg/sve_helper.c
45
+++ b/target/arm/tcg/sve_helper.c
46
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
47
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
48
49
/* Perform gross MTE suppression early. */
50
- if (!tbi_check(desc, bit55) ||
51
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
52
+ if (!tbi_check(mtedesc, bit55) ||
53
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
54
mtedesc = 0;
55
}
56
57
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
58
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
59
60
/* Perform gross MTE suppression early. */
61
- if (!tbi_check(desc, bit55) ||
62
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
63
+ if (!tbi_check(mtedesc, bit55) ||
64
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
65
mtedesc = 0;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
69
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
70
71
/* Perform gross MTE suppression early. */
72
- if (!tbi_check(desc, bit55) ||
73
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
74
+ if (!tbi_check(mtedesc, bit55) ||
75
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
76
mtedesc = 0;
77
}
78
79
--
80
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/18] AArch64: Fix single stepping of ERET instruction
[PULL 08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
1
From: Jaroslaw Pelczar <j.pelczar@samsung.com>
1
The raven_io_ops MemoryRegionOps is the only one in the source tree
2
which sets .valid.unaligned to indicate that it should support
3
unaligned accesses and which does not also set .impl.unaligned to
4
indicate that its read and write functions can do the unaligned
5
handling themselves. This is a problem, because at the moment the
6
core memory system does not implement the support for handling
7
unaligned accesses by doing a series of aligned accesses and
8
combining them (system/memory.c:access_with_adjusted_size() has a
9
TODO comment noting this).
2
10
3
Previously when single stepping through ERET instruction via GDB
11
Fortunately raven_io_read() and raven_io_write() will correctly deal
4
would result in debugger entering the "next" PC after ERET instruction.
12
with the case of being passed an unaligned address, so we can fix the
5
When debugging in kernel mode, this will also cause unintended behavior,
13
missing unaligned access support by setting .impl.unaligned in the
6
because debugger will try to access memory from EL0 point of view.
14
MemoryRegionOps struct.
7
15
8
Signed-off-by: Jaroslaw Pelczar <j.pelczar@samsung.com>
16
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
9
Message-id: 001c01d32895$483027f0$d89077d0$@samsung.com
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Tested-by: Cédric Le Goater <clg@redhat.com>
19
Reviewed-by: Cédric Le Goater <clg@redhat.com>
20
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
12
---
21
---
13
target/arm/translate-a64.c | 1 +
22
hw/pci-host/raven.c | 1 +
14
1 file changed, 1 insertion(+)
23
1 file changed, 1 insertion(+)
15
24
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
25
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
17
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
27
--- a/hw/pci-host/raven.c
19
+++ b/target/arm/translate-a64.c
28
+++ b/hw/pci-host/raven.c
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
21
default:
30
.write = raven_io_write,
22
gen_a64_set_pc_im(dc->pc);
31
.endianness = DEVICE_LITTLE_ENDIAN,
23
/* fall through */
32
.impl.max_access_size = 4,
24
+ case DISAS_EXIT:
33
+ .impl.unaligned = true,
25
case DISAS_JUMP:
34
.valid.unaligned = true,
26
if (dc->base.singlestep_enabled) {
35
};
27
gen_exception_internal(EXCP_DEBUG);
36
28
--
37
--
29
2.7.4
38
2.34.1
30
39
31
40
diff view generated by jsdifflib
New patch
[PULL 09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
1
Suppress the deprecation warning when we're running under qtest,
2
to avoid "make check" including warning messages in its output.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
7
---
8
hw/block/tc58128.c | 4 +++-
9
1 file changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/block/tc58128.c
14
+++ b/hw/block/tc58128.c
15
@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
16
17
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
18
{
19
- warn_report_once("The TC58128 flash device is deprecated");
20
+ if (!qtest_enabled()) {
21
+ warn_report_once("The TC58128 flash device is deprecated");
22
+ }
23
init_dev(&tc58128_devs[0], zone1);
24
init_dev(&tc58128_devs[1], zone2);
25
return sh7750_register_io_device(s, &tc58128);
26
--
27
2.34.1
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/18] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2
[PULL 10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
1
Use a symbolic constant M_REG_NUM_BANKS for the array size for
1
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
2
registers which are banked by M profile security state, rather
2
because we already get the coverage of those tests via qtests_arm,
3
than hardcoding lots of 2s.
3
and we don't want to use extra CI minutes testing them twice.
4
4
5
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
6
that change.
7
8
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
9
Message-id: 1505137930-13255-2-git-send-email-peter.maydell@linaro.org
10
---
12
---
11
target/arm/cpu.h | 35 +++++++++++++++++++----------------
13
tests/qtest/meson.build | 1 -
12
1 file changed, 19 insertions(+), 16 deletions(-)
14
1 file changed, 1 deletion(-)
13
15
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
18
--- a/tests/qtest/meson.build
17
+++ b/target/arm/cpu.h
19
+++ b/tests/qtest/meson.build
18
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
19
* accessed via env->registerfield[env->v7m.secure] (whether the security
21
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
20
* extension is implemented or not).
22
(config_all_accel.has_key('CONFIG_TCG') and \
21
*/
23
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
22
-#define M_REG_NS 0
24
- (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
23
-#define M_REG_S 1
25
['arm-cpu-features',
24
+enum {
26
'numa-test',
25
+ M_REG_NS = 0,
27
'boot-serial-test',
26
+ M_REG_S = 1,
27
+ M_REG_NUM_BANKS = 2,
28
+};
29
30
/* ARM-specific interrupt pending bits. */
31
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
32
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
33
uint32_t other_sp;
34
uint32_t other_ss_msp;
35
uint32_t other_ss_psp;
36
- uint32_t vecbase[2];
37
- uint32_t basepri[2];
38
- uint32_t control[2];
39
- uint32_t ccr[2]; /* Configuration and Control */
40
- uint32_t cfsr[2]; /* Configurable Fault Status */
41
+ uint32_t vecbase[M_REG_NUM_BANKS];
42
+ uint32_t basepri[M_REG_NUM_BANKS];
43
+ uint32_t control[M_REG_NUM_BANKS];
44
+ uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
45
+ uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
46
uint32_t hfsr; /* HardFault Status */
47
uint32_t dfsr; /* Debug Fault Status Register */
48
- uint32_t mmfar[2]; /* MemManage Fault Address */
49
+ uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
50
uint32_t bfar; /* BusFault Address */
51
- unsigned mpu_ctrl[2]; /* MPU_CTRL */
52
+ unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
53
int exception;
54
- uint32_t primask[2];
55
- uint32_t faultmask[2];
56
+ uint32_t primask[M_REG_NUM_BANKS];
57
+ uint32_t faultmask[M_REG_NUM_BANKS];
58
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
59
} v7m;
60
61
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
62
uint32_t *drbar;
63
uint32_t *drsr;
64
uint32_t *dracr;
65
- uint32_t rnr[2];
66
+ uint32_t rnr[M_REG_NUM_BANKS];
67
} pmsav7;
68
69
/* PMSAv8 MPU */
70
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
71
* pmsav7.rnr (region number register)
72
* pmsav7_dregion (number of configured regions)
73
*/
74
- uint32_t *rbar[2];
75
- uint32_t *rlar[2];
76
- uint32_t mair0[2];
77
- uint32_t mair1[2];
78
+ uint32_t *rbar[M_REG_NUM_BANKS];
79
+ uint32_t *rlar[M_REG_NUM_BANKS];
80
+ uint32_t mair0[M_REG_NUM_BANKS];
81
+ uint32_t mair1[M_REG_NUM_BANKS];
82
} pmsav8;
83
84
void *nvic;
85
--
28
--
86
2.7.4
29
2.34.1
87
30
88
31
diff view generated by jsdifflib
New patch
[PULL 11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
1
Allow changes to the virt GTDT -- we are going to add the IRQ
2
entry for a new timer to it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
6
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
7
---
8
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/bios-tables-test-allowed-diff.h
14
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
15
@@ -1 +1,3 @@
16
/* List of comma-separated changed AML files to ignore */
17
+"tests/data/acpi/virt/FACP",
18
+"tests/data/acpi/virt/GTDT",
19
--
20
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/18] hw/arm/virt: Set INTx/gsi mapping
[PULL 12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
1
From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
1
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
2
2
non-secure EL2 virtual timer. We implemented the timer itself in the
3
Let's provide the GPEX host bridge with the INTx/gsi mapping. This is
3
CPU model, but never wired up its IRQ line to the GIC.
4
needed for INTx/gsi routing.
4
5
5
Wire up the IRQ line (this is always safe whether the CPU has the
6
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
6
interrupt or not, since it always creates the outbound IRQ line).
7
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
7
Report it to the guest via dtb and ACPI if the CPU has the feature.
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
9
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
The DTB binding is documented in the kernel's
10
Tested-by: Feng Kan <fkan@apm.com>
10
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
11
Message-id: 1505296004-6798-3-git-send-email-eric.auger@redhat.com
11
and the ACPI table entries are documented in the ACPI specification
12
version 6.3 or later.
13
14
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
15
FADT table rev to show that we might be using 6.3 features.
16
17
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
18
versions prior to edk2-stable202311, for users who use the virt board
19
with 'virtualization=on' to enable EL2 emulation and are booting an
20
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
21
that EDK2 will assert on bootup:
22
23
ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
24
25
If you see that assertion you should do one of:
26
* update your EDK2 binaries to edk2-stable202311 or newer
27
* use the 'virt-8.2' versioned machine type
28
* not use 'virtualization=on'
29
30
(The versions shipped with QEMU itself have the fix.)
31
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
34
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
13
---
35
---
14
hw/arm/virt.c | 1 +
36
include/hw/arm/virt.h | 2 ++
15
1 file changed, 1 insertion(+)
37
hw/arm/virt-acpi-build.c | 20 ++++++++++----
16
38
hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------
39
3 files changed, 67 insertions(+), 15 deletions(-)
40
41
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/virt.h
44
+++ b/include/hw/arm/virt.h
45
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
46
/* Machines < 6.2 have no support for describing cpu topology to guest */
47
bool no_cpu_topology;
48
bool no_tcg_lpa2;
49
+ bool no_ns_el2_virt_timer_irq;
50
};
51
52
struct VirtMachineState {
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
54
PCIBus *bus;
55
char *oem_id;
56
char *oem_table_id;
57
+ bool ns_el2_virt_timer_irq;
58
};
59
60
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
61
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/virt-acpi-build.c
64
+++ b/hw/arm/virt-acpi-build.c
65
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
}
67
68
/*
69
- * ACPI spec, Revision 5.1
70
- * 5.2.24 Generic Timer Description Table (GTDT)
71
+ * ACPI spec, Revision 6.5
72
+ * 5.2.25 Generic Timer Description Table (GTDT)
73
*/
74
static void
75
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
76
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
77
uint32_t irqflags = vmc->claim_edge_triggered_timers ?
78
1 : /* Interrupt is Edge triggered */
79
0; /* Interrupt is Level triggered */
80
- AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
81
+ AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
82
.oem_table_id = vms->oem_table_id };
83
84
acpi_table_begin(&table, table_data);
85
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
86
build_append_int_noprefix(table_data, 0, 4);
87
/* Platform Timer Offset */
88
build_append_int_noprefix(table_data, 0, 4);
89
-
90
+ if (vms->ns_el2_virt_timer_irq) {
91
+ /* Virtual EL2 Timer GSIV */
92
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
93
+ /* Virtual EL2 Timer Flags */
94
+ build_append_int_noprefix(table_data, irqflags, 4);
95
+ } else {
96
+ build_append_int_noprefix(table_data, 0, 4);
97
+ build_append_int_noprefix(table_data, 0, 4);
98
+ }
99
acpi_table_end(linker, &table);
100
}
101
102
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
103
static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
104
VirtMachineState *vms, unsigned dsdt_tbl_offset)
105
{
106
- /* ACPI v6.0 */
107
+ /* ACPI v6.3 */
108
AcpiFadtData fadt = {
109
.rev = 6,
110
- .minor_ver = 0,
111
+ .minor_ver = 3,
112
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
113
.xdsdt_tbl_offset = &dsdt_tbl_offset,
114
};
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
115
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
116
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
117
--- a/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
118
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic)
119
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
22
120
qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
23
for (i = 0; i < GPEX_NUM_IRQS; i++) {
121
}
24
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
122
25
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
123
+/*
124
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
125
+ * but we don't want to advertise it to the guest in the dtb or ACPI
126
+ * table unless it's really going to do something.
127
+ */
128
+static bool ns_el2_virt_timer_present(void)
129
+{
130
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
131
+ CPUARMState *env = &cpu->env;
132
+
133
+ return arm_feature(env, ARM_FEATURE_AARCH64) &&
134
+ arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
135
+}
136
+
137
static void create_fdt(VirtMachineState *vms)
138
{
139
MachineState *ms = MACHINE(vms);
140
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
141
"arm,armv7-timer");
26
}
142
}
27
143
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
28
pci = PCI_HOST_BRIDGE(dev);
144
- qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
145
- GIC_FDT_IRQ_TYPE_PPI,
146
- INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
147
- GIC_FDT_IRQ_TYPE_PPI,
148
- INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
149
- GIC_FDT_IRQ_TYPE_PPI,
150
- INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
151
- GIC_FDT_IRQ_TYPE_PPI,
152
- INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
153
+ if (vms->ns_el2_virt_timer_irq) {
154
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
155
+ GIC_FDT_IRQ_TYPE_PPI,
156
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
157
+ GIC_FDT_IRQ_TYPE_PPI,
158
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
159
+ GIC_FDT_IRQ_TYPE_PPI,
160
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
161
+ GIC_FDT_IRQ_TYPE_PPI,
162
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
163
+ GIC_FDT_IRQ_TYPE_PPI,
164
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
165
+ } else {
166
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
167
+ GIC_FDT_IRQ_TYPE_PPI,
168
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
169
+ GIC_FDT_IRQ_TYPE_PPI,
170
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
171
+ GIC_FDT_IRQ_TYPE_PPI,
172
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
173
+ GIC_FDT_IRQ_TYPE_PPI,
174
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
175
+ }
176
}
177
178
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
179
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
180
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
181
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
182
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
183
+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
184
};
185
186
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
187
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
188
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
189
object_unref(cpuobj);
190
}
191
+
192
+ /* Now we've created the CPUs we can see if they have the hypvirt timer */
193
+ vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
194
+ !vmc->no_ns_el2_virt_timer_irq;
195
+
196
fdt_add_timer_nodes(vms);
197
fdt_add_cpu_nodes(vms);
198
199
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
200
201
static void virt_machine_8_2_options(MachineClass *mc)
202
{
203
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
204
+
205
virt_machine_9_0_options(mc);
206
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
207
+ /*
208
+ * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
209
+ * earlier machines. (Exposing it tickles a bug in older EDK2
210
+ * guest BIOS binaries.)
211
+ */
212
+ vmc->no_ns_el2_virt_timer_irq = true;
213
}
214
DEFINE_VIRT_MACHINE(8, 2)
215
29
--
216
--
30
2.7.4
217
2.34.1
31
32
diff view generated by jsdifflib
New patch
[PULL 13/35] tests/qtest/bios-tables-tests: Update virt golden reference
1
1
Update the virt golden reference files to say that the FACP is ACPI
2
v6.3, and the GTDT table is a revision 3 table with space for the
3
virtual EL2 timer.
4
5
Diffs from iasl:
6
7
@@ -XXX,XX +XXX,XX @@
8
/*
9
* Intel ACPI Component Architecture
10
* AML/ASL+ Disassembler version 20200925 (64-bit version)
11
* Copyright (c) 2000 - 2020 Intel Corporation
12
*
13
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
14
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
15
*
16
* ACPI Data Table [FACP]
17
*
18
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
19
*/
20
21
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
22
[004h 0004 4] Table Length : 00000114
23
[008h 0008 1] Revision : 06
24
-[009h 0009 1] Checksum : 15
25
+[009h 0009 1] Checksum : 12
26
[00Ah 0010 6] Oem ID : "BOCHS "
27
[010h 0016 8] Oem Table ID : "BXPC "
28
[018h 0024 4] Oem Revision : 00000001
29
[01Ch 0028 4] Asl Compiler ID : "BXPC"
30
[020h 0032 4] Asl Compiler Revision : 00000001
31
32
[024h 0036 4] FACS Address : 00000000
33
[028h 0040 4] DSDT Address : 00000000
34
[02Ch 0044 1] Model : 00
35
[02Dh 0045 1] PM Profile : 00 [Unspecified]
36
[02Eh 0046 2] SCI Interrupt : 0000
37
[030h 0048 4] SMI Command Port : 00000000
38
[034h 0052 1] ACPI Enable Value : 00
39
[035h 0053 1] ACPI Disable Value : 00
40
[036h 0054 1] S4BIOS Command : 00
41
[037h 0055 1] P-State Control : 00
42
@@ -XXX,XX +XXX,XX @@
43
Use APIC Physical Destination Mode (V4) : 0
44
Hardware Reduced (V5) : 1
45
Low Power S0 Idle (V5) : 0
46
47
[074h 0116 12] Reset Register : [Generic Address Structure]
48
[074h 0116 1] Space ID : 00 [SystemMemory]
49
[075h 0117 1] Bit Width : 00
50
[076h 0118 1] Bit Offset : 00
51
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
52
[078h 0120 8] Address : 0000000000000000
53
54
[080h 0128 1] Value to cause reset : 00
55
[081h 0129 2] ARM Flags (decoded below) : 0003
56
PSCI Compliant : 1
57
Must use HVC for PSCI : 1
58
59
-[083h 0131 1] FADT Minor Revision : 00
60
+[083h 0131 1] FADT Minor Revision : 03
61
[084h 0132 8] FACS Address : 0000000000000000
62
[08Ch 0140 8] DSDT Address : 0000000000000000
63
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
64
[094h 0148 1] Space ID : 00 [SystemMemory]
65
[095h 0149 1] Bit Width : 00
66
[096h 0150 1] Bit Offset : 00
67
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
68
[098h 0152 8] Address : 0000000000000000
69
70
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
71
[0A0h 0160 1] Space ID : 00 [SystemMemory]
72
[0A1h 0161 1] Bit Width : 00
73
[0A2h 0162 1] Bit Offset : 00
74
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
75
[0A4h 0164 8] Address : 0000000000000000
76
77
@@ -XXX,XX +XXX,XX @@
78
[0F5h 0245 1] Bit Width : 00
79
[0F6h 0246 1] Bit Offset : 00
80
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
81
[0F8h 0248 8] Address : 0000000000000000
82
83
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
84
[100h 0256 1] Space ID : 00 [SystemMemory]
85
[101h 0257 1] Bit Width : 00
86
[102h 0258 1] Bit Offset : 00
87
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
88
[104h 0260 8] Address : 0000000000000000
89
90
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
91
92
Raw Table Data: Length 276 (0x114)
93
94
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
95
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
96
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
97
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
98
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
99
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
100
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
101
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
102
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
103
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
104
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
105
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
106
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
107
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
108
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
109
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
110
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
111
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
112
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
113
0110: 00 00 00 00 // ....
114
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
* Intel ACPI Component Architecture
118
* AML/ASL+ Disassembler version 20200925 (64-bit version)
119
* Copyright (c) 2000 - 2020 Intel Corporation
120
*
121
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
122
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
123
*
124
* ACPI Data Table [GTDT]
125
*
126
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
127
*/
128
129
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
130
-[004h 0004 4] Table Length : 00000060
131
-[008h 0008 1] Revision : 02
132
-[009h 0009 1] Checksum : 9C
133
+[004h 0004 4] Table Length : 00000068
134
+[008h 0008 1] Revision : 03
135
+[009h 0009 1] Checksum : 93
136
[00Ah 0010 6] Oem ID : "BOCHS "
137
[010h 0016 8] Oem Table ID : "BXPC "
138
[018h 0024 4] Oem Revision : 00000001
139
[01Ch 0028 4] Asl Compiler ID : "BXPC"
140
[020h 0032 4] Asl Compiler Revision : 00000001
141
142
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
143
[02Ch 0044 4] Reserved : 00000000
144
145
[030h 0048 4] Secure EL1 Interrupt : 0000001D
146
[034h 0052 4] EL1 Flags (decoded below) : 00000000
147
Trigger Mode : 0
148
Polarity : 0
149
Always On : 0
150
151
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
152
@@ -XXX,XX +XXX,XX @@
153
154
[040h 0064 4] Virtual Timer Interrupt : 0000001B
155
[044h 0068 4] VT Flags (decoded below) : 00000000
156
Trigger Mode : 0
157
Polarity : 0
158
Always On : 0
159
160
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
161
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
162
Trigger Mode : 0
163
Polarity : 0
164
Always On : 0
165
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
166
167
[058h 0088 4] Platform Timer Count : 00000000
168
[05Ch 0092 4] Platform Timer Offset : 00000000
169
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
170
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
171
172
-Raw Table Data: Length 96 (0x60)
173
+Raw Table Data: Length 104 (0x68)
174
175
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
176
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
177
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
178
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
179
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
180
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
181
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
182
+ 0060: 00 00 00 00 00 00 00 00 // ........
183
184
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
186
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
187
---
188
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
189
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
190
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
191
3 files changed, 2 deletions(-)
192
193
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/qtest/bios-tables-test-allowed-diff.h
196
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
197
@@ -1,3 +1 @@
198
/* List of comma-separated changed AML files to ignore */
199
-"tests/data/acpi/virt/FACP",
200
-"tests/data/acpi/virt/GTDT",
201
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
202
index XXXXXXX..XXXXXXX 100644
203
GIT binary patch
204
delta 25
205
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
206
207
delta 28
208
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
209
210
diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
211
index XXXXXXX..XXXXXXX 100644
212
GIT binary patch
213
delta 25
214
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
215
216
delta 16
217
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
218
219
--
220
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
1
The patchset adding the GMAC ethernet to this SoC crossed in the
2
mail with the patchset cleaning up the NIC handling. When we
3
create the GMAC modules we must call qemu_configure_nic_device()
4
so that the user has the opportunity to use the -nic commandline
5
option to create a network backend and connect it to the GMACs.
1
6
7
Add the missing call.
8
9
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
12
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
13
---
14
hw/arm/npcm7xx.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/npcm7xx.c
20
+++ b/hw/arm/npcm7xx.c
21
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
22
for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
23
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
24
25
+ qemu_configure_nic_device(DEVICE(sbd), false, NULL);
26
/*
27
* The device exists regardless of whether it's connected to a QEMU
28
* netdev backend. So always instantiate it even if there is no
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
1
Currently QEMU will warn if there is a NIC on the board that
2
is not connected to a backend. By default the '-nic user' will
3
get used for all NICs, but if you manually connect a specific
4
NIC to a specific backend, then the other NICs on the board
5
have no backend and will be warned about:
1
6
7
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
8
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
9
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
10
11
So suppress those warnings by manually connecting every NIC
12
on the board to some backend.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
18
---
19
tests/qtest/npcm7xx_emc-test.c | 5 ++++-
20
1 file changed, 4 insertions(+), 1 deletion(-)
21
22
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/tests/qtest/npcm7xx_emc-test.c
25
+++ b/tests/qtest/npcm7xx_emc-test.c
26
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
27
* KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
28
* in the 'model' field to specify the device to match.
29
*/
30
- g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
31
+ g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
32
+ "-nic user,model=npcm7xx-emc "
33
+ "-nic user,model=npcm-gmac "
34
+ "-nic user,model=npcm-gmac",
35
test_sockets[1], module_num);
36
37
g_test_queue_destroy(packet_test_clear, test_sockets);
38
--
39
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/18] target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()
[PULL 16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
1
In the v7M and v8M ARM ARM, the magic exception return values are
1
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
2
referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_*
2
CPU, and in fact if you try to do it we will assert:
3
constants to define bits within them. Rename the 'type' variable
4
which holds the exception return value in do_v7m_exception_exit()
5
to excret, making it clearer that it does hold an EXC_RETURN value.
6
3
4
#6 0x00007ffff4b95e96 in __GI___assert_fail
5
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
6
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
7
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
8
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
9
10
We might call pmu_counter_enabled() on an M-profile CPU (for example
11
from the migration pre/post hooks in machine.c); this should always
12
return false because these CPUs don't set ARM_FEATURE_PMU.
13
14
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
15
have done the early return for "PMU not present".
16
17
This fixes an assertion failure if you try to do a loadvm or
18
savevm for an M-profile board.
19
20
Cc: qemu-stable@nongnu.org
21
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1505137930-13255-8-git-send-email-peter.maydell@linaro.org
25
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
12
---
26
---
13
target/arm/helper.c | 23 ++++++++++++-----------
27
target/arm/helper.c | 12 ++++++++++--
14
1 file changed, 12 insertions(+), 11 deletions(-)
28
1 file changed, 10 insertions(+), 2 deletions(-)
15
29
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
32
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
33
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static void v7m_push_stack(ARMCPU *cpu)
34
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
21
static void do_v7m_exception_exit(ARMCPU *cpu)
35
bool enabled, prohibited = false, filtered;
22
{
36
bool secure = arm_is_secure(env);
23
CPUARMState *env = &cpu->env;
37
int el = arm_current_el(env);
24
- uint32_t type;
38
- uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
25
+ uint32_t excret;
39
- uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
26
uint32_t xpsr;
40
+ uint64_t mdcr_el2;
27
bool ufault = false;
41
+ uint8_t hpmn;
28
bool return_to_sp_process = false;
42
29
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
43
+ /*
30
* the target value up between env->regs[15] and env->thumb in
44
+ * We might be called for M-profile cores where MDCR_EL2 doesn't
31
* gen_bx(). Reconstitute it.
45
+ * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
32
*/
46
+ * must be before we read that value.
33
- type = env->regs[15];
47
+ */
34
+ excret = env->regs[15];
48
if (!arm_feature(env, ARM_FEATURE_PMU)) {
35
if (env->thumb) {
49
return false;
36
- type |= 1;
37
+ excret |= 1;
38
}
50
}
39
51
40
qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32
52
+ mdcr_el2 = arm_mdcr_el2_eff(env);
41
" previous exception %d\n",
53
+ hpmn = mdcr_el2 & MDCR_HPMN;
42
- type, env->v7m.exception);
54
+
43
+ excret, env->v7m.exception);
55
if (!arm_feature(env, ARM_FEATURE_EL2) ||
44
56
(counter < hpmn || counter == 31)) {
45
- if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
57
e = env->cp15.c9_pmcr & PMCRE;
46
+ if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
47
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
48
- "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);
49
+ "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n",
50
+ excret);
51
}
52
53
if (env->v7m.exception != ARMV7M_EXCP_NMI) {
54
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
55
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
56
*/
57
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
58
- int es = type & R_V7M_EXCRET_ES_MASK;
59
+ int es = excret & R_V7M_EXCRET_ES_MASK;
60
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
61
env->v7m.faultmask[es] = 0;
62
}
63
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
64
g_assert_not_reached();
65
}
66
67
- switch (type & 0xf) {
68
+ switch (excret & 0xf) {
69
case 1: /* Return to Handler */
70
return_to_handler = true;
71
break;
72
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
73
*/
74
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
75
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
76
- v7m_exception_taken(cpu, type);
77
+ v7m_exception_taken(cpu, excret);
78
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
79
"stackframe: failed exception return integrity check\n");
80
return;
81
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
82
83
/* The restored xPSR exception field will be zero if we're
84
* resuming in Thread mode. If that doesn't match what the
85
- * exception return type specified then this is a UsageFault.
86
+ * exception return excret specified then this is a UsageFault.
87
*/
88
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
89
/* Take an INVPC UsageFault by pushing the stack again. */
90
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
91
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
92
v7m_push_stack(cpu);
93
- v7m_exception_taken(cpu, type);
94
+ v7m_exception_taken(cpu, excret);
95
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "
96
"failed exception return integrity check\n");
97
return;
98
--
58
--
99
2.7.4
59
2.34.1
100
60
101
61
diff view generated by jsdifflib
New patch
[PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
1
From: Nabih Estefan <nabihestefan@google.com>
1
2
3
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
4
of 8xx. Also fix comments referencing this and values expecting 8xx.
5
6
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
7
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: commit message tweaks]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
15
tests/qtest/meson.build | 3 +-
16
2 files changed, 4 insertions(+), 83 deletions(-)
17
18
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/tests/qtest/npcm_gmac-test.c
21
+++ b/tests/qtest/npcm_gmac-test.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
23
const GMACModule *module;
24
} TestData;
25
26
-/* Values extracted from hw/arm/npcm8xx.c */
27
+/* Values extracted from hw/arm/npcm7xx.c */
28
static const GMACModule gmac_module_list[] = {
29
{
30
.irq = 14,
31
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
32
.irq = 15,
33
.base_addr = 0xf0804000
34
},
35
- {
36
- .irq = 16,
37
- .base_addr = 0xf0806000
38
- },
39
- {
40
- .irq = 17,
41
- .base_addr = 0xf0808000
42
- }
43
};
44
45
/* Returns the index of the GMAC module. */
46
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
47
return qtest_readl(qts, mod->base_addr + regno);
48
}
49
50
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
51
- NPCMRegister regno)
52
-{
53
- uint32_t write_value = (regno & 0x3ffe00) >> 9;
54
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
55
- uint32_t read_offset = regno & 0x1ff;
56
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
57
-}
58
-
59
/* Check that GMAC registers are reset to default value */
60
static void test_init(gconstpointer test_data)
61
{
62
const TestData *td = test_data;
63
const GMACModule *mod = td->module;
64
- QTestState *qts = qtest_init("-machine npcm845-evb");
65
+ QTestState *qts = qtest_init("-machine npcm750-evb");
66
67
#define CHECK_REG32(regno, value) \
68
do { \
69
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
70
} while (0)
71
72
-#define CHECK_REG_PCS(regno, value) \
73
- do { \
74
- g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
75
- } while (0)
76
-
77
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
78
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
79
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
80
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
81
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
82
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
83
84
- /* TODO Add registers PCS */
85
- if (mod->base_addr == 0xf0802000) {
86
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
87
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
88
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
89
-
90
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
91
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
92
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
93
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
94
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
95
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
96
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
97
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
98
-
99
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
100
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
101
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
102
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
103
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
104
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
105
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
106
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
107
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
108
-
109
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
110
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
111
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
112
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
113
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
114
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
115
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
116
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
117
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
118
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
119
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
120
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
121
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
122
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
123
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
124
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
125
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
126
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
127
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
128
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
129
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
130
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
131
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
132
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
133
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
134
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
135
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
136
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
137
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
138
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
139
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
140
- }
141
-
142
qtest_quit(qts);
143
}
144
145
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
146
index XXXXXXX..XXXXXXX 100644
147
--- a/tests/qtest/meson.build
148
+++ b/tests/qtest/meson.build
149
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
150
'npcm7xx_sdhci-test',
151
'npcm7xx_smbus-test',
152
'npcm7xx_timer-test',
153
- 'npcm7xx_watchdog_timer-test'] + \
154
+ 'npcm7xx_watchdog_timer-test',
155
+ 'npcm_gmac-test'] + \
156
(slirp.found() ? ['npcm7xx_emc-test'] : [])
157
qtests_aspeed = \
158
['aspeed_hace-test',
159
--
160
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/35] hw/arm/smmuv3: add support for stage 1 access fault
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
An access fault is raised when the Access Flag is not set in the
4
looked-up PTE and the AFFD field is not set in the corresponding context
5
descriptor. This was already implemented for stage 2. Implement it for
6
stage 1 as well.
7
8
Signed-off-by: Luc Michel <luc.michel@amd.com>
9
Reviewed-by: Mostafa Saleh <smostafa@google.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Tested-by: Mostafa Saleh <smostafa@google.com>
12
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
13
[PMM: tweaked comment text]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/smmuv3-internal.h | 1 +
17
include/hw/arm/smmu-common.h | 1 +
18
hw/arm/smmu-common.c | 11 +++++++++++
19
hw/arm/smmuv3.c | 1 +
20
4 files changed, 14 insertions(+)
21
22
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/smmuv3-internal.h
25
+++ b/hw/arm/smmuv3-internal.h
26
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
27
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
28
#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
29
#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
30
+#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
31
#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
32
#define CD_HD(x) extract32((x)->word[1], 10 , 1)
33
#define CD_HA(x) extract32((x)->word[1], 11 , 1)
34
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/arm/smmu-common.h
37
+++ b/include/hw/arm/smmu-common.h
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
39
bool disabled; /* smmu is disabled */
40
bool bypassed; /* translation is bypassed */
41
bool aborted; /* translation is aborted */
42
+ bool affd; /* AF fault disable */
43
uint32_t iotlb_hits; /* counts IOTLB hits */
44
uint32_t iotlb_misses; /* counts IOTLB misses*/
45
/* Used by stage-1 only. */
46
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/smmu-common.c
49
+++ b/hw/arm/smmu-common.c
50
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
51
pte_addr, pte, iova, gpa,
52
block_size >> 20);
53
}
54
+
55
+ /*
56
+ * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
57
+ * are 0 we take an Access flag fault. (5.4. Context Descriptor)
58
+ * An Access flag fault takes priority over a Permission fault.
59
+ */
60
+ if (!PTE_AF(pte) && !cfg->affd) {
61
+ info->type = SMMU_PTW_ERR_ACCESS;
62
+ goto error;
63
+ }
64
+
65
ap = PTE_AP(pte);
66
if (is_permission_fault(ap, perm)) {
67
info->type = SMMU_PTW_ERR_PERMISSION;
68
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/smmuv3.c
71
+++ b/hw/arm/smmuv3.c
72
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
73
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
74
cfg->tbi = CD_TBI(cd);
75
cfg->asid = CD_ASID(cd);
76
+ cfg->affd = CD_AFFD(cd);
77
78
trace_smmuv3_decode_cd(cfg->oas);
79
80
--
81
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/18] hw/pci-host/gpex: Implement PCI INTx routing
[PULL 19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
1
From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Now we are able to retrieve the gsi from the INTx pin, let's
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
enable intx_to_irq routing. From that point on, irqfd becomes
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
usable along with INTx when assigning a PCIe device.
5
Message-id: 20240213155214.13619-2-philmd@linaro.org
6
7
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
8
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Andrew Jones <drjones@redhat.com>
11
Tested-by: Feng Kan <fkan@apm.com>
12
Message-id: 1505296004-6798-4-git-send-email-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
7
---
15
hw/pci-host/gpex.c | 12 ++++++++++++
8
hw/arm/stellaris.c | 6 ++++--
16
1 file changed, 12 insertions(+)
9
1 file changed, 4 insertions(+), 2 deletions(-)
17
10
18
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
19
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/pci-host/gpex.c
13
--- a/hw/arm/stellaris.c
21
+++ b/hw/pci-host/gpex.c
14
+++ b/hw/arm/stellaris.c
22
@@ -XXX,XX +XXX,XX @@ int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
23
return 0;
16
}
24
}
17
}
25
18
26
+static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
19
-static void stellaris_adc_reset(StellarisADCState *s)
27
+{
20
+static void stellaris_adc_reset_hold(Object *obj)
28
+ PCIINTxRoute route;
29
+ GPEXHost *s = opaque;
30
+
31
+ route.mode = PCI_INTX_ENABLED;
32
+ route.irq = s->irq_num[pin];
33
+
34
+ return route;
35
+}
36
+
37
static void gpex_host_realize(DeviceState *dev, Error **errp)
38
{
21
{
39
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
22
+ StellarisADCState *s = STELLARIS_ADC(obj);
40
@@ -XXX,XX +XXX,XX @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
23
int n;
41
&s->io_ioport, 0, 4, TYPE_PCIE_BUS);
24
42
25
for (n = 0; n < 4; n++) {
43
qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
26
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
44
+ pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
27
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
45
qdev_init_nofail(DEVICE(&s->gpex_root));
28
"adc", 0x1000);
29
sysbus_init_mmio(sbd, &s->iomem);
30
- stellaris_adc_reset(s);
31
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
46
}
32
}
47
33
34
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
35
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
36
{
37
DeviceClass *dc = DEVICE_CLASS(klass);
38
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
39
40
+ rc->phases.hold = stellaris_adc_reset_hold;
41
dc->vmsd = &vmstate_stellaris_adc;
42
}
43
48
--
44
--
49
2.7.4
45
2.34.1
50
46
51
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/18] xlnx-zcu102: Add a machine level virtualization property
[PULL 20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Add a machine level virtualization property. This defaults to false and can be
3
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
4
set to true using this machine command line argument:
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
-machine xlnx-zcu102,virtualization=on
5
Message-id: 20240213155214.13619-3-philmd@linaro.org
6
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
This follows what the ARM virt machine does.
8
9
This property only applies to the ZCU102 machine. The EP108 machine does
10
not have this property.
11
12
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
8
---
16
include/hw/arm/xlnx-zynqmp.h | 2 ++
9
hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
17
hw/arm/xlnx-zcu102.c | 30 +++++++++++++++++++++++++++++-
10
1 file changed, 22 insertions(+), 4 deletions(-)
18
hw/arm/xlnx-zynqmp.c | 3 ++-
19
3 files changed, 33 insertions(+), 2 deletions(-)
20
11
21
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
22
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/xlnx-zynqmp.h
14
--- a/hw/arm/stellaris.c
24
+++ b/include/hw/arm/xlnx-zynqmp.h
15
+++ b/hw/arm/stellaris.c
25
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState {
16
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
26
17
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
27
/* Has the ARM Security extensions? */
28
bool secure;
29
+ /* Has the ARM Virtualization extensions? */
30
+ bool virt;
31
/* Has the RPU subsystem? */
32
bool has_rpu;
33
} XlnxZynqMPState;
34
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/arm/xlnx-zcu102.c
37
+++ b/hw/arm/xlnx-zcu102.c
38
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
39
MemoryRegion ddr_ram;
40
41
bool secure;
42
+ bool virt;
43
} XlnxZCU102;
44
45
#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
46
@@ -XXX,XX +XXX,XX @@ static void zcu102_set_secure(Object *obj, bool value, Error **errp)
47
s->secure = value;
48
}
18
}
49
19
50
+static bool zcu102_get_virt(Object *obj, Error **errp)
20
-/* I2C controller. */
51
+{
21
+/*
52
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
22
+ * I2C controller.
23
+ * ??? For now we only implement the master interface.
24
+ */
25
26
#define TYPE_STELLARIS_I2C "stellaris-i2c"
27
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
29
stellaris_i2c_update(s);
30
}
31
32
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
33
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
34
{
35
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
53
+
36
+
54
+ return s->virt;
37
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
38
i2c_end_transfer(s->bus);
55
+}
39
+}
56
+
40
+
57
+static void zcu102_set_virt(Object *obj, bool value, Error **errp)
41
+static void stellaris_i2c_reset_hold(Object *obj)
58
+{
42
+{
59
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
43
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
60
+
44
61
+ s->virt = value;
45
s->msa = 0;
46
s->mcs = 0;
47
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
48
s->mimr = 0;
49
s->mris = 0;
50
s->mcr = 0;
62
+}
51
+}
63
+
52
+
64
static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
53
+static void stellaris_i2c_reset_exit(Object *obj)
54
+{
55
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
56
+
57
stellaris_i2c_update(s);
58
}
59
60
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
61
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
62
"i2c", 0x1000);
63
sysbus_init_mmio(sbd, &s->iomem);
64
- /* ??? For now we only implement the master interface. */
65
- stellaris_i2c_reset(s);
66
}
67
68
/* Analogue to Digital Converter. This is only partially implemented,
69
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
70
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
65
{
71
{
66
int i;
72
DeviceClass *dc = DEVICE_CLASS(klass);
67
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
73
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
68
"ddr-ram", &error_abort);
74
69
object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
75
+ rc->phases.enter = stellaris_i2c_reset_enter;
70
&error_fatal);
76
+ rc->phases.hold = stellaris_i2c_reset_hold;
71
+ object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",
77
+ rc->phases.exit = stellaris_i2c_reset_exit;
72
+ &error_fatal);
78
dc->vmsd = &vmstate_stellaris_i2c;
73
74
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
75
76
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_instance_init(Object *obj)
77
{
78
XlnxZCU102 *s = EP108_MACHINE(obj);
79
80
- /* EP108, we don't support setting secure */
81
+ /* EP108, we don't support setting secure or virt */
82
s->secure = false;
83
+ s->virt = false;
84
}
79
}
85
80
86
static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
87
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
88
"Set on/off to enable/disable the ARM "
89
"Security Extensions (TrustZone)",
90
NULL);
91
+
92
+ /* Default to virt (EL2) being disabled */
93
+ s->virt = false;
94
+ object_property_add_bool(obj, "virtualization", zcu102_get_virt,
95
+ zcu102_set_virt, NULL);
96
+ object_property_set_description(obj, "virtualization",
97
+ "Set on/off to enable/disable emulating a "
98
+ "guest CPU which implements the ARM "
99
+ "Virtualization Extensions",
100
+ NULL);
101
}
102
103
static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
104
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/arm/xlnx-zynqmp.c
107
+++ b/hw/arm/xlnx-zynqmp.c
108
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
109
object_property_set_bool(OBJECT(&s->apu_cpu[i]),
110
s->secure, "has_el3", NULL);
111
object_property_set_bool(OBJECT(&s->apu_cpu[i]),
112
- false, "has_el2", NULL);
113
+ s->virt, "has_el2", NULL);
114
object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
115
"reset-cbar", &error_abort);
116
object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
117
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
118
static Property xlnx_zynqmp_props[] = {
119
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
120
DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
121
+ DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
122
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
123
DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
124
MemoryRegion *),
125
--
81
--
126
2.7.4
82
2.34.1
127
83
128
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/18] mps2-an511: Fix wiring of UART overflow interrupt lines
[PULL 21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
1
Fix an error that meant we were wiring every UART's overflow
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
interrupts into the same inputs 0 and 1 of the OR gate,
3
rather than giving each its own input.
4
2
5
Cc: qemu-stable@nongnu.org
3
QDev objects created with qdev_new() need to manually add
4
their parent relationship with object_property_add_child().
5
6
This commit plug the devices which aren't part of the SoC;
7
they will be plugged into a SoC container in the next one.
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20240213155214.13619-4-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9
Message-id: 1505232834-20890-1-git-send-email-peter.maydell@linaro.org
10
---
13
---
11
hw/arm/mps2.c | 4 ++--
14
hw/arm/stellaris.c | 4 ++++
12
1 file changed, 2 insertions(+), 2 deletions(-)
15
1 file changed, 4 insertions(+)
13
16
14
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
17
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/mps2.c
19
--- a/hw/arm/stellaris.c
17
+++ b/hw/arm/mps2.c
20
+++ b/hw/arm/stellaris.c
18
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
21
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
19
cmsdk_apb_uart_create(uartbase[i],
22
&error_fatal);
20
qdev_get_gpio_in(txrx_orgate_dev, 0),
23
21
qdev_get_gpio_in(txrx_orgate_dev, 1),
24
ssddev = qdev_new("ssd0323");
22
- qdev_get_gpio_in(orgate_dev, 0),
25
+ object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
23
- qdev_get_gpio_in(orgate_dev, 1),
26
qdev_prop_set_uint8(ssddev, "cs", 1);
24
+ qdev_get_gpio_in(orgate_dev, i * 2),
27
qdev_realize_and_unref(ssddev, bus, &error_fatal);
25
+ qdev_get_gpio_in(orgate_dev, i * 2 + 1),
28
26
NULL,
29
gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
27
uartchr, SYSCLK_FRQ);
30
+ object_property_add_child(OBJECT(ms), "splitter",
31
+ OBJECT(gpio_d_splitter));
32
qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
33
qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
34
qdev_connect_gpio_out(
35
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
36
DeviceState *gpad;
37
38
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
39
+ object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
40
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
41
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
28
}
42
}
29
--
43
--
30
2.7.4
44
2.34.1
31
45
32
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/18] xlnx-ep108: Rename to ZCU102
[PULL 22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
The EP108 is a early access development board. Now that silicon is in
3
QDev objects created with qdev_new() need to manually add
4
production people have access to the ZCU102. Let's rename the internal
4
their parent relationship with object_property_add_child().
5
QEMU files and variables to use the ZCU102.
6
5
7
There is no functional change here as the EP108 is still a valid board
6
Since we don't model the SoC, just use a QOM container.
8
option.
9
7
10
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20240213155214.13619-5-philmd@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
12
---
14
hw/arm/Makefile.objs | 2 +-
13
hw/arm/stellaris.c | 11 ++++++++++-
15
hw/arm/{xlnx-ep108.c => xlnx-zcu102.c} | 30 +++++++++++++++---------------
14
1 file changed, 10 insertions(+), 1 deletion(-)
16
2 files changed, 16 insertions(+), 16 deletions(-)
17
rename hw/arm/{xlnx-ep108.c => xlnx-zcu102.c} (85%)
18
15
19
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
16
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/Makefile.objs
18
--- a/hw/arm/stellaris.c
22
+++ b/hw/arm/Makefile.objs
19
+++ b/hw/arm/stellaris.c
23
@@ -XXX,XX +XXX,XX @@ obj-y += omap1.o omap2.o strongarm.o
20
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
24
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
21
* 400fe000 system control
25
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
22
*/
26
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
23
27
-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
24
+ Object *soc_container;
28
+obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-zcu102.o
25
DeviceState *gpio_dev[7], *nvic;
29
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
26
qemu_irq gpio_in[7][8];
30
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
27
qemu_irq gpio_out[7][8];
31
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
32
diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-zcu102.c
29
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
33
similarity index 85%
30
sram_size = ((board->dc0 >> 18) + 1) * 1024;
34
rename from hw/arm/xlnx-ep108.c
31
35
rename to hw/arm/xlnx-zcu102.c
32
+ soc_container = object_new("container");
36
index XXXXXXX..XXXXXXX 100644
33
+ object_property_add_child(OBJECT(ms), "soc", soc_container);
37
--- a/hw/arm/xlnx-ep108.c
34
+
38
+++ b/hw/arm/xlnx-zcu102.c
35
/* Flash programming is done via the SCU, so pretend it is ROM. */
39
@@ -XXX,XX +XXX,XX @@
36
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
40
/*
37
&error_fatal);
41
- * Xilinx ZynqMP EP108 board
38
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
42
+ * Xilinx ZynqMP ZCU102 board
39
* need its sysclk output.
43
*
40
*/
44
* Copyright (C) 2015 Xilinx Inc
41
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
45
* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
42
+ object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
46
@@ -XXX,XX +XXX,XX @@
43
47
#include "exec/address-spaces.h"
44
/*
48
#include "qemu/log.h"
45
* Most devices come preprogrammed with a MAC address in the user data.
49
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
50
-typedef struct XlnxEP108 {
47
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
51
+typedef struct XlnxZCU102 {
48
52
XlnxZynqMPState soc;
49
nvic = qdev_new(TYPE_ARMV7M);
53
MemoryRegion ddr_ram;
50
+ object_property_add_child(soc_container, "v7m", OBJECT(nvic));
54
-} XlnxEP108;
51
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
55
+} XlnxZCU102;
52
qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
56
53
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
57
-static struct arm_boot_info xlnx_ep108_binfo;
54
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
58
+static struct arm_boot_info xlnx_zcu102_binfo;
55
59
56
dev = qdev_new(TYPE_STELLARIS_GPTM);
60
-static void xlnx_ep108_init(MachineState *machine)
57
sbd = SYS_BUS_DEVICE(dev);
61
+static void xlnx_zcu102_init(MachineState *machine)
58
+ object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
62
{
59
qdev_connect_clock_in(dev, "clk",
63
- XlnxEP108 *s = g_new0(XlnxEP108, 1);
60
qdev_get_clock_out(ssys_dev, "SYSCLK"));
64
+ XlnxZCU102 *s = g_new0(XlnxZCU102, 1);
61
sysbus_realize_and_unref(sbd, &error_fatal);
65
int i;
62
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
66
uint64_t ram_size = machine->ram_size;
63
67
64
if (board->dc1 & (1 << 3)) { /* watchdog present */
68
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)
65
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
69
}
66
-
70
67
+ object_property_add_child(soc_container, "wdg", OBJECT(dev));
71
if (ram_size < 0x08000000) {
68
qdev_connect_clock_in(dev, "WDOGCLK",
72
- qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for EP108",
69
qdev_get_clock_out(ssys_dev, "SYSCLK"));
73
+ qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
70
74
ram_size);
71
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
75
}
72
SysBusDevice *sbd;
76
73
77
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)
74
dev = qdev_new("pl011_luminary");
78
75
+ object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
79
/* TODO create and connect IDE devices for ide_drive_get() */
76
sbd = SYS_BUS_DEVICE(dev);
80
77
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
81
- xlnx_ep108_binfo.ram_size = ram_size;
78
sysbus_realize_and_unref(sbd, &error_fatal);
82
- xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
83
- xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
80
DeviceState *enet;
84
- xlnx_ep108_binfo.initrd_filename = machine->initrd_filename;
81
85
- xlnx_ep108_binfo.loader_start = 0;
82
enet = qdev_new("stellaris_enet");
86
- arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_ep108_binfo);
83
+ object_property_add_child(soc_container, "enet", OBJECT(enet));
87
+ xlnx_zcu102_binfo.ram_size = ram_size;
84
if (nd) {
88
+ xlnx_zcu102_binfo.kernel_filename = machine->kernel_filename;
85
qdev_set_nic_properties(enet, nd);
89
+ xlnx_zcu102_binfo.kernel_cmdline = machine->kernel_cmdline;
86
} else {
90
+ xlnx_zcu102_binfo.initrd_filename = machine->initrd_filename;
91
+ xlnx_zcu102_binfo.loader_start = 0;
92
+ arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
93
}
94
95
static void xlnx_ep108_machine_init(MachineClass *mc)
96
{
97
mc->desc = "Xilinx ZynqMP EP108 board";
98
- mc->init = xlnx_ep108_init;
99
+ mc->init = xlnx_zcu102_init;
100
mc->block_default_type = IF_IDE;
101
mc->units_per_default_bus = 1;
102
mc->ignore_memory_transaction_failures = true;
103
@@ -XXX,XX +XXX,XX @@ DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init)
104
static void xlnx_zcu102_machine_init(MachineClass *mc)
105
{
106
mc->desc = "Xilinx ZynqMP ZCU102 board";
107
- mc->init = xlnx_ep108_init;
108
+ mc->init = xlnx_zcu102_init;
109
mc->block_default_type = IF_IDE;
110
mc->units_per_default_bus = 1;
111
mc->ignore_memory_transaction_failures = true;
112
--
87
--
113
2.7.4
88
2.34.1
114
89
115
90
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/18] target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()
[PULL 23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
1
In do_v7m_exception_exit(), there's no need to force the high 4
1
We support two different encodings for the AArch32 IMPDEF
2
bits of 'type' to 1 when calling v7m_exception_taken(), because
2
CBAR register -- older cores like the Cortex A9, A7, A15
3
we know that they're always 1 or we could not have got to this
3
have this at 4, c15, c0, 0; newer cores like the
4
"handle return to magic exception return address" code. Remove
4
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
5
the unnecessary ORs.
5
6
When we implemented this we picked which encoding to
7
use based on whether the CPU set ARM_FEATURE_AARCH64.
8
However this isn't right for three cases:
9
* the qemu-system-arm 'max' CPU, which is supposed to be
10
a variant on a Cortex-A57; it ought to use the same
11
encoding the A57 does and which the AArch64 'max'
12
exposes to AArch32 guest code
13
* the Cortex-R52, which is AArch32-only but has the CBAR
14
at the newer encoding (and where we incorrectly are
15
not yet setting ARM_FEATURE_CBAR_RO anyway)
16
* any possible future support for other v8 AArch32
17
only CPUs, or for supporting "boot the CPU into
18
AArch32 mode" on our existing cores like the A57 etc
19
20
Make the decision of the encoding be based on whether
21
the CPU implements the ARM_FEATURE_V8 flag instead.
22
23
This changes the behaviour only for the qemu-system-arm
24
'-cpu max'. We don't expect anybody to be relying on the
25
old behaviour because:
26
* it's not what the real hardware Cortex-A57 does
27
(and that's what our ID register claims we are)
28
* we don't implement the memory-mapped GICv3 support
29
which is the only thing that exists at the peripheral
30
base address pointed to by the register
6
31
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
34
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
10
Message-id: 1505137930-13255-6-git-send-email-peter.maydell@linaro.org
11
---
35
---
12
target/arm/helper.c | 4 ++--
36
target/arm/helper.c | 2 +-
13
1 file changed, 2 insertions(+), 2 deletions(-)
37
1 file changed, 1 insertion(+), 1 deletion(-)
14
38
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
43
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
44
* AArch64 cores we might need to add a specific feature flag
45
* to indicate cores with "flavour 2" CBAR.
20
*/
46
*/
21
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
47
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
22
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
48
+ if (arm_feature(env, ARM_FEATURE_V8)) {
23
- v7m_exception_taken(cpu, type | 0xf0000000);
49
/* 32 bit view is [31:18] 0...0 [43:32]. */
24
+ v7m_exception_taken(cpu, type);
50
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
25
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
51
| extract64(cpu->reset_cbar, 32, 12);
26
"stackframe: failed exception return integrity check\n");
27
return;
28
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
29
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
30
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
31
v7m_push_stack(cpu);
32
- v7m_exception_taken(cpu, type | 0xf0000000);
33
+ v7m_exception_taken(cpu, type);
34
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "
35
"failed exception return integrity check\n");
36
return;
37
--
52
--
38
2.7.4
53
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 24/35] target/arm: The Cortex-R52 has a read-only CBAR
1
The Cortex-R52 implements the Configuration Base Address Register
2
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
3
type, so that our implementation provides the register and the
4
associated qdev property.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
18
set_feature(&cpu->env, ARM_FEATURE_PMSA);
19
set_feature(&cpu->env, ARM_FEATURE_NEON);
20
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
21
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
22
cpu->midr = 0x411fd133; /* r1p3 */
23
cpu->revidr = 0x00000000;
24
cpu->reset_fpsid = 0x41034023;
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
1
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
2
also by enabling the AUXCR feature which defines the ACTLR
3
and HACTLR registers. As is our usual practice, we make these
4
simple reads-as-zero stubs for now.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
11
1 file changed, 108 insertions(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
19
}
20
21
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
22
+ { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
23
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
24
+ { .name = "IMP_ATCMREGIONR",
25
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
26
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
27
+ { .name = "IMP_BTCMREGIONR",
28
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
29
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
30
+ { .name = "IMP_CTCMREGIONR",
31
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
32
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ { .name = "IMP_CSCTLR",
34
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "IMP_BPCTLR",
37
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
38
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
+ { .name = "IMP_MEMPROTCLR",
40
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
41
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
+ { .name = "IMP_SLAVEPCTLR",
43
+ .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
44
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
+ { .name = "IMP_PERIPHREGIONR",
46
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
47
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
48
+ { .name = "IMP_FLASHIFREGIONR",
49
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "IMP_BUILDOPTR",
52
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
53
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "IMP_PINOPTR",
55
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
56
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ { .name = "IMP_QOSR",
58
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
59
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60
+ { .name = "IMP_BUSTIMEOUTR",
61
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
62
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
+ { .name = "IMP_INTMONR",
64
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
65
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66
+ { .name = "IMP_ICERR0",
67
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
68
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69
+ { .name = "IMP_ICERR1",
70
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
71
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
+ { .name = "IMP_DCERR0",
73
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
74
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
+ { .name = "IMP_DCERR1",
76
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
77
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78
+ { .name = "IMP_TCMERR0",
79
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
80
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
+ { .name = "IMP_TCMERR1",
82
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
83
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ { .name = "IMP_TCMSYNDR0",
85
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
86
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+ { .name = "IMP_TCMSYNDR1",
88
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
89
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
90
+ { .name = "IMP_FLASHERR0",
91
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
92
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
93
+ { .name = "IMP_FLASHERR1",
94
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
95
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
96
+ { .name = "IMP_CDBGDR0",
97
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
98
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
99
+ { .name = "IMP_CBDGBR1",
100
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
101
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
102
+ { .name = "IMP_TESTR0",
103
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
104
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
105
+ { .name = "IMP_TESTR1",
106
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
107
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
108
+ { .name = "IMP_CDBGDCI",
109
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
110
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
111
+ { .name = "IMP_CDBGDCT",
112
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
113
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
114
+ { .name = "IMP_CDBGICT",
115
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
116
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
117
+ { .name = "IMP_CDBGDCD",
118
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
119
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
120
+ { .name = "IMP_CDBGICD",
121
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
122
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
123
+};
124
+
125
+
126
static void cortex_r52_initfn(Object *obj)
127
{
128
ARMCPU *cpu = ARM_CPU(obj);
129
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
130
set_feature(&cpu->env, ARM_FEATURE_NEON);
131
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
132
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
133
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
134
cpu->midr = 0x411fd133; /* r1p3 */
135
cpu->revidr = 0x00000000;
136
cpu->reset_fpsid = 0x41034023;
137
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
138
139
cpu->pmsav7_dregion = 16;
140
cpu->pmsav8r_hdregion = 16;
141
+
142
+ define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
143
}
144
145
static void cortex_r5f_initfn(Object *obj)
146
--
147
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/35] target/arm: Allow access to SPSR_hyp from hyp mode
1
Architecturally, the AArch32 MSR/MRS to/from banked register
2
instructions are UNPREDICTABLE for attempts to access a banked
3
register that the guest could access in a more direct way (e.g.
4
using this insn to access r8_fiq when already in FIQ mode). QEMU has
5
chosen to UNDEF on all of these.
1
6
7
However, for the case of accessing SPSR_hyp from hyp mode, it turns
8
out that real hardware permits this, with the same effect as if the
9
guest had directly written to SPSR. Further, there is some
10
guest code out there that assumes it can do this, because it
11
happens to work on hardware: an example Cortex-R52 startup code
12
fragment uses this, and it got copied into various other places,
13
including Zephyr. Zephyr was fixed to not use this:
14
https://github.com/zephyrproject-rtos/zephyr/issues/47330
15
but other examples are still out there, like the selftest
16
binary for the MPS3-AN536.
17
18
For convenience of being able to run guest code, permit
19
this UNPREDICTABLE access instead of UNDEFing it.
20
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
24
---
25
target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
26
target/arm/tcg/translate.c | 19 +++++++++++------
27
2 files changed, 43 insertions(+), 19 deletions(-)
28
29
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/tcg/op_helper.c
32
+++ b/target/arm/tcg/op_helper.c
33
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
34
*/
35
int curmode = env->uncached_cpsr & CPSR_M;
36
37
- if (regno == 17) {
38
- /* ELR_Hyp: a special case because access from tgtmode is OK */
39
- if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
40
- goto undef;
41
+ if (tgtmode == ARM_CPU_MODE_HYP) {
42
+ /*
43
+ * Handle Hyp target regs first because some are special cases
44
+ * which don't want the usual "not accessible from tgtmode" check.
45
+ */
46
+ switch (regno) {
47
+ case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
48
+ if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
49
+ goto undef;
50
+ }
51
+ break;
52
+ case 13:
53
+ if (curmode != ARM_CPU_MODE_MON) {
54
+ goto undef;
55
+ }
56
+ break;
57
+ default:
58
+ g_assert_not_reached();
59
}
60
return;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
63
}
64
}
65
66
- if (tgtmode == ARM_CPU_MODE_HYP) {
67
- /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
68
- if (curmode != ARM_CPU_MODE_MON) {
69
- goto undef;
70
- }
71
- }
72
-
73
return;
74
75
undef:
76
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
77
78
switch (regno) {
79
case 16: /* SPSRs */
80
- env->banked_spsr[bank_number(tgtmode)] = value;
81
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
82
+ /* Only happens for SPSR_Hyp access in Hyp mode */
83
+ env->spsr = value;
84
+ } else {
85
+ env->banked_spsr[bank_number(tgtmode)] = value;
86
+ }
87
break;
88
case 17: /* ELR_Hyp */
89
env->elr_el[2] = value;
90
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
91
92
switch (regno) {
93
case 16: /* SPSRs */
94
- return env->banked_spsr[bank_number(tgtmode)];
95
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
96
+ /* Only happens for SPSR_Hyp access in Hyp mode */
97
+ return env->spsr;
98
+ } else {
99
+ return env->banked_spsr[bank_number(tgtmode)];
100
+ }
101
case 17: /* ELR_Hyp */
102
return env->elr_el[2];
103
case 13:
104
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/tcg/translate.c
107
+++ b/target/arm/tcg/translate.c
108
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
109
break;
110
case ARM_CPU_MODE_HYP:
111
/*
112
- * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
113
- * (and so we can forbid accesses from EL2 or below). elr_hyp
114
- * can be accessed also from Hyp mode, so forbid accesses from
115
- * EL0 or EL1.
116
+ * r13_hyp can only be accessed from Monitor mode, and so we
117
+ * can forbid accesses from EL2 or below.
118
+ * elr_hyp can be accessed also from Hyp mode, so forbid
119
+ * accesses from EL0 or EL1.
120
+ * SPSR_hyp is supposed to be in the same category as r13_hyp
121
+ * and UNPREDICTABLE if accessed from anything except Monitor
122
+ * mode. However there is some real-world code that will do
123
+ * it because at least some hardware happens to permit the
124
+ * access. (Notably a standard Cortex-R52 startup code fragment
125
+ * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
126
+ * this (incorrect) guest code to run.
127
*/
128
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
129
- (s->current_el < 3 && *regno != 17)) {
130
+ if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
131
+ || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
132
goto undef;
133
}
134
break;
135
--
136
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/18] xlnx-zcu102: Mark the EP108 machine as deprecated
[PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
We currently guard the CFG3 register read with
2
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
3
which is clearly wrong as it is never true.
2
4
3
The EP108 is the same as the ZCU102, mark it as deprecated as we don't
5
This register is present on all board types except AN524
4
need two machines.
6
and AN527; correct the condition.
5
7
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
8
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
9
---
13
---
10
hw/arm/xlnx-zcu102.c | 2 +-
14
hw/misc/mps2-scc.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
16
13
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
17
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/xlnx-zcu102.c
19
--- a/hw/misc/mps2-scc.c
16
+++ b/hw/arm/xlnx-zcu102.c
20
+++ b/hw/misc/mps2-scc.c
17
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
21
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
18
{
22
r = s->cfg2;
19
MachineClass *mc = MACHINE_CLASS(oc);
23
break;
20
24
case A_CFG3:
21
- mc->desc = "Xilinx ZynqMP EP108 board";
25
- if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
22
+ mc->desc = "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-zcu102)";
26
+ if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
23
mc->init = xlnx_ep108_init;
27
/* CFG3 reserved on AN524 */
24
mc->block_default_type = IF_IDE;
28
goto bad_offset;
25
mc->units_per_default_bus = 1;
29
}
26
--
30
--
27
2.7.4
31
2.34.1
28
32
29
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/18] xlnx-zcu102: Manually create the machines
[PULL 28/35] hw/misc/mps2-scc: Factor out which-board conditionals
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
The MPS SCC device has a lot of different flavours for the various
2
different MPS FPGA images, which look mostly similar but have
3
differences in how particular registers are handled. Currently we
4
deal with this with a lot of open-coded checks on scc_partno(), but
5
as we add more board types this is getting a bit hard to read.
2
6
3
In preperation for future work let's manually create the Xilnx machines.
7
Factor out the conditions into some functions which we can
4
This will allow us to set properties for the machines in the future.
8
give more descriptive names to.
5
9
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
9
---
14
---
10
hw/arm/xlnx-zcu102.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++-----
15
hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
11
1 file changed, 67 insertions(+), 7 deletions(-)
16
1 file changed, 31 insertions(+), 14 deletions(-)
12
17
13
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
18
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/xlnx-zcu102.c
20
--- a/hw/misc/mps2-scc.c
16
+++ b/hw/arm/xlnx-zcu102.c
21
+++ b/hw/misc/mps2-scc.c
17
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
18
#include "qemu/log.h"
23
return extract32(s->id, 4, 8);
19
20
typedef struct XlnxZCU102 {
21
+ MachineState parent_obj;
22
+
23
XlnxZynqMPState soc;
24
MemoryRegion ddr_ram;
25
} XlnxZCU102;
26
27
+#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
28
+#define ZCU102_MACHINE(obj) \
29
+ OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
30
+
31
+#define TYPE_EP108_MACHINE MACHINE_TYPE_NAME("xlnx-ep108")
32
+#define EP108_MACHINE(obj) \
33
+ OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE)
34
+
35
static struct arm_boot_info xlnx_zcu102_binfo;
36
37
-static void xlnx_zcu102_init(MachineState *machine)
38
+static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
39
{
40
- XlnxZCU102 *s = g_new0(XlnxZCU102, 1);
41
int i;
42
uint64_t ram_size = machine->ram_size;
43
44
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
45
arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
46
}
24
}
47
25
48
-static void xlnx_ep108_machine_init(MachineClass *mc)
26
+/* Is CFG_REG2 present? */
49
+static void xlnx_ep108_init(MachineState *machine)
27
+static bool have_cfg2(MPS2SCC *s)
50
+{
28
+{
51
+ XlnxZCU102 *s = EP108_MACHINE(machine);
29
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
52
+
53
+ xlnx_zynqmp_init(s, machine);
54
+}
30
+}
55
+
31
+
56
+static void xlnx_ep108_machine_instance_init(Object *obj)
32
+/* Is CFG_REG3 present? */
57
{
33
+static bool have_cfg3(MPS2SCC *s)
34
+{
35
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
58
+}
36
+}
59
+
37
+
60
+static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
38
+/* Is CFG_REG5 present? */
39
+static bool have_cfg5(MPS2SCC *s)
61
+{
40
+{
62
+ MachineClass *mc = MACHINE_CLASS(oc);
41
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
63
+
64
mc->desc = "Xilinx ZynqMP EP108 board";
65
- mc->init = xlnx_zcu102_init;
66
+ mc->init = xlnx_ep108_init;
67
mc->block_default_type = IF_IDE;
68
mc->units_per_default_bus = 1;
69
mc->ignore_memory_transaction_failures = true;
70
}
71
72
-DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init)
73
+static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
74
+ .name = MACHINE_TYPE_NAME("xlnx-ep108"),
75
+ .parent = TYPE_MACHINE,
76
+ .class_init = xlnx_ep108_machine_class_init,
77
+ .instance_init = xlnx_ep108_machine_instance_init,
78
+ .instance_size = sizeof(XlnxZCU102),
79
+};
80
81
-static void xlnx_zcu102_machine_init(MachineClass *mc)
82
+static void xlnx_ep108_machine_init_register_types(void)
83
{
84
+ type_register_static(&xlnx_ep108_machine_init_typeinfo);
85
+}
42
+}
86
+
43
+
87
+static void xlnx_zcu102_init(MachineState *machine)
44
+/* Is CFG_REG6 present? */
45
+static bool have_cfg6(MPS2SCC *s)
88
+{
46
+{
89
+ XlnxZCU102 *s = ZCU102_MACHINE(machine);
47
+ return scc_partno(s) == 0x524;
90
+
91
+ xlnx_zynqmp_init(s, machine);
92
+}
48
+}
93
+
49
+
94
+static void xlnx_zcu102_machine_instance_init(Object *obj)
50
/* Handle a write via the SYS_CFG channel to the specified function/device.
95
+{
51
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
96
+}
52
*/
97
+
53
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
98
+static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
54
r = s->cfg1;
99
+{
55
break;
100
+ MachineClass *mc = MACHINE_CLASS(oc);
56
case A_CFG2:
101
+
57
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
102
mc->desc = "Xilinx ZynqMP ZCU102 board";
58
- /* CFG2 reserved on other boards */
103
mc->init = xlnx_zcu102_init;
59
+ if (!have_cfg2(s)) {
104
mc->block_default_type = IF_IDE;
60
goto bad_offset;
105
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_init(MachineClass *mc)
61
}
106
mc->ignore_memory_transaction_failures = true;
62
r = s->cfg2;
107
}
63
break;
108
64
case A_CFG3:
109
-DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init)
65
- if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
110
+static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
66
- /* CFG3 reserved on AN524 */
111
+ .name = MACHINE_TYPE_NAME("xlnx-zcu102"),
67
+ if (!have_cfg3(s)) {
112
+ .parent = TYPE_MACHINE,
68
goto bad_offset;
113
+ .class_init = xlnx_zcu102_machine_class_init,
69
}
114
+ .instance_init = xlnx_zcu102_machine_instance_init,
70
/* These are user-settable DIP switches on the board. We don't
115
+ .instance_size = sizeof(XlnxZCU102),
71
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
116
+};
72
r = s->cfg4;
117
+
73
break;
118
+static void xlnx_zcu102_machine_init_register_types(void)
74
case A_CFG5:
119
+{
75
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
120
+ type_register_static(&xlnx_zcu102_machine_init_typeinfo);
76
- /* CFG5 reserved on other boards */
121
+}
77
+ if (!have_cfg5(s)) {
122
+
78
goto bad_offset;
123
+type_init(xlnx_zcu102_machine_init_register_types)
79
}
124
+type_init(xlnx_ep108_machine_init_register_types)
80
r = s->cfg5;
81
break;
82
case A_CFG6:
83
- if (scc_partno(s) != 0x524) {
84
- /* CFG6 reserved on other boards */
85
+ if (!have_cfg6(s)) {
86
goto bad_offset;
87
}
88
r = s->cfg6;
89
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
90
}
91
break;
92
case A_CFG2:
93
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
94
- /* CFG2 reserved on other boards */
95
+ if (!have_cfg2(s)) {
96
goto bad_offset;
97
}
98
/* AN524: QSPI Select signal */
99
s->cfg2 = value;
100
break;
101
case A_CFG5:
102
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
103
- /* CFG5 reserved on other boards */
104
+ if (!have_cfg5(s)) {
105
goto bad_offset;
106
}
107
/* AN524: ACLK frequency in Hz */
108
s->cfg5 = value;
109
break;
110
case A_CFG6:
111
- if (scc_partno(s) != 0x524) {
112
- /* CFG6 reserved on other boards */
113
+ if (!have_cfg6(s)) {
114
goto bad_offset;
115
}
116
/* AN524: Clock divider for BRAM */
125
--
117
--
126
2.7.4
118
2.34.1
127
119
128
120
diff view generated by jsdifflib
New patch
[PULL 29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
1
1
The MPS2 SCC device is broadly the same for all FPGA images, but has
2
minor differences in the behaviour of the CFG registers depending on
3
the image. In many cases we don't really care about the functionality
4
controlled by these registers and a reads-as-written or similar
5
behaviour is sufficient for the moment.
6
7
For the AN536 the required behaviour is:
8
9
* A_CFG0 has CPU reset and halt bits
10
- implement as reads-as-written for the moment
11
* A_CFG1 has flash or ATCM address 0 remap handling
12
- QEMU doesn't model this; implement as reads-as-written
13
* A_CFG2 has QSPI select (like AN524)
14
- implemented (no behaviour, as with AN524)
15
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
16
- QEMU doesn't care about these, so use the existing
17
RAZ behaviour for convenience
18
* A_CFG4 is board rev (like all other images)
19
- no change needed
20
* A_CFG5 is ACLK frq in hz (like AN524)
21
- implemented as reads-as-written, as for other boards
22
* A_CFG6 is core 0 vector table base address
23
- implemented as reads-as-written for the moment
24
* A_CFG7 is core 1 vector table base address
25
- implemented as reads-as-written for the moment
26
27
Make the changes necessary for this; leave TODO comments where
28
appropriate to indicate where we might want to come back and
29
implement things like CPU reset.
30
31
The other aspects of the device specific to this FPGA image (like the
32
values of the board ID and similar registers) will be set via the
33
device's qdev properties.
34
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
38
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
39
---
40
include/hw/misc/mps2-scc.h | 1 +
41
hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++----
42
2 files changed, 92 insertions(+), 10 deletions(-)
43
44
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/misc/mps2-scc.h
47
+++ b/include/hw/misc/mps2-scc.h
48
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
49
uint32_t cfg4;
50
uint32_t cfg5;
51
uint32_t cfg6;
52
+ uint32_t cfg7;
53
uint32_t cfgdata_rtn;
54
uint32_t cfgdata_out;
55
uint32_t cfgctrl;
56
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/mps2-scc.c
59
+++ b/hw/misc/mps2-scc.c
60
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
61
REG32(CFG4, 0x10)
62
REG32(CFG5, 0x14)
63
REG32(CFG6, 0x18)
64
+REG32(CFG7, 0x1c)
65
REG32(CFGDATA_RTN, 0xa0)
66
REG32(CFGDATA_OUT, 0xa4)
67
REG32(CFGCTRL, 0xa8)
68
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
69
/* Is CFG_REG2 present? */
70
static bool have_cfg2(MPS2SCC *s)
71
{
72
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
73
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
74
+ scc_partno(s) == 0x536;
75
}
76
77
/* Is CFG_REG3 present? */
78
static bool have_cfg3(MPS2SCC *s)
79
{
80
- return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
81
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
82
+ scc_partno(s) != 0x536;
83
}
84
85
/* Is CFG_REG5 present? */
86
static bool have_cfg5(MPS2SCC *s)
87
{
88
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
89
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
90
+ scc_partno(s) == 0x536;
91
}
92
93
/* Is CFG_REG6 present? */
94
static bool have_cfg6(MPS2SCC *s)
95
{
96
- return scc_partno(s) == 0x524;
97
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
98
+}
99
+
100
+/* Is CFG_REG7 present? */
101
+static bool have_cfg7(MPS2SCC *s)
102
+{
103
+ return scc_partno(s) == 0x536;
104
+}
105
+
106
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
107
+static bool cfg0_is_remap(MPS2SCC *s)
108
+{
109
+ return scc_partno(s) != 0x536;
110
+}
111
+
112
+/* Is CFG_REG1 driving a set of LEDs? */
113
+static bool cfg1_is_leds(MPS2SCC *s)
114
+{
115
+ return scc_partno(s) != 0x536;
116
}
117
118
/* Handle a write via the SYS_CFG channel to the specified function/device.
119
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
120
if (!have_cfg3(s)) {
121
goto bad_offset;
122
}
123
- /* These are user-settable DIP switches on the board. We don't
124
+ /*
125
+ * These are user-settable DIP switches on the board. We don't
126
* model that, so just return zeroes.
127
+ *
128
+ * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
129
+ * bits". These change which part of the DDR4 the motherboard
130
+ * configuration controller can see in its memory map (see the
131
+ * appnote section 2.4). QEMU doesn't model the MCC at all, so these
132
+ * bits are not interesting to us; read-as-zero is as good as anything
133
+ * else.
134
*/
135
r = 0;
136
break;
137
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
138
}
139
r = s->cfg6;
140
break;
141
+ case A_CFG7:
142
+ if (!have_cfg7(s)) {
143
+ goto bad_offset;
144
+ }
145
+ r = s->cfg7;
146
+ break;
147
case A_CFGDATA_RTN:
148
r = s->cfgdata_rtn;
149
break;
150
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
151
* we always reflect bit 0 in the 'remap' GPIO output line,
152
* and let the board wire it up or not as it chooses.
153
* TODO on some boards bit 1 is CPU_WAIT.
154
+ *
155
+ * TODO: on the AN536 this register controls reset and halt
156
+ * for both CPUs. For the moment we don't implement this, so the
157
+ * register just reads as written.
158
*/
159
s->cfg0 = value;
160
- qemu_set_irq(s->remap, s->cfg0 & 1);
161
+ if (cfg0_is_remap(s)) {
162
+ qemu_set_irq(s->remap, s->cfg0 & 1);
163
+ }
164
break;
165
case A_CFG1:
166
s->cfg1 = value;
167
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
168
- led_set_state(s->led[i], extract32(value, i, 1));
169
+ /*
170
+ * On most boards this register drives LEDs.
171
+ *
172
+ * TODO: for AN536 this controls whether flash and ATCM are
173
+ * enabled or disabled on reset. QEMU doesn't model this, and
174
+ * always wires up RAM in the ATCM area and ROM in the flash area.
175
+ */
176
+ if (cfg1_is_leds(s)) {
177
+ for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
178
+ led_set_state(s->led[i], extract32(value, i, 1));
179
+ }
180
}
181
break;
182
case A_CFG2:
183
if (!have_cfg2(s)) {
184
goto bad_offset;
185
}
186
- /* AN524: QSPI Select signal */
187
+ /* AN524, AN536: QSPI Select signal */
188
s->cfg2 = value;
189
break;
190
case A_CFG5:
191
if (!have_cfg5(s)) {
192
goto bad_offset;
193
}
194
- /* AN524: ACLK frequency in Hz */
195
+ /* AN524, AN536: ACLK frequency in Hz */
196
s->cfg5 = value;
197
break;
198
case A_CFG6:
199
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
200
goto bad_offset;
201
}
202
/* AN524: Clock divider for BRAM */
203
+ /* AN536: Core 0 vector table base address */
204
+ s->cfg6 = value;
205
+ break;
206
+ case A_CFG7:
207
+ if (!have_cfg7(s)) {
208
+ goto bad_offset;
209
+ }
210
+ /* AN536: Core 1 vector table base address */
211
s->cfg6 = value;
212
break;
213
case A_CFGDATA_OUT:
214
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
215
g_free(s->oscclk_reset);
216
}
217
218
+static bool cfg7_needed(void *opaque)
219
+{
220
+ MPS2SCC *s = opaque;
221
+
222
+ return have_cfg7(s);
223
+}
224
+
225
+static const VMStateDescription vmstate_cfg7 = {
226
+ .name = "mps2-scc/cfg7",
227
+ .version_id = 1,
228
+ .minimum_version_id = 1,
229
+ .needed = cfg7_needed,
230
+ .fields = (const VMStateField[]) {
231
+ VMSTATE_UINT32(cfg7, MPS2SCC),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
static const VMStateDescription mps2_scc_vmstate = {
237
.name = "mps2-scc",
238
.version_id = 3,
239
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
240
VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
241
0, vmstate_info_uint32, uint32_t),
242
VMSTATE_END_OF_LIST()
243
+ },
244
+ .subsections = (const VMStateDescription * const []) {
245
+ &vmstate_cfg7,
246
+ NULL
247
}
248
};
249
250
--
251
2.34.1
252
253
diff view generated by jsdifflib
New patch
[PULL 30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
1
1
The AN536 is another FPGA image for the MPS3 development board. Unlike
2
the existing FPGA images we already model, this board uses a Cortex-R
3
family CPU, and it does not use any equivalent to the M-profile
4
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
5
It's therefore more convenient for us to model it as a completely
6
separate C file.
7
8
This commit adds the basic skeleton of the board model, and the
9
code to create all the RAM and ROM. We assume that we're probably
10
going to want to add more images in future, so use the same
11
base class/subclass setup that mps2-tz.c uses, even though at
12
the moment there's only a single subclass.
13
14
Following commits will add the CPUs and the peripherals.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
19
---
20
MAINTAINERS | 3 +-
21
configs/devices/arm-softmmu/default.mak | 1 +
22
hw/arm/mps3r.c | 239 ++++++++++++++++++++++++
23
hw/arm/Kconfig | 5 +
24
hw/arm/meson.build | 1 +
25
5 files changed, 248 insertions(+), 1 deletion(-)
26
create mode 100644 hw/arm/mps3r.c
27
28
diff --git a/MAINTAINERS b/MAINTAINERS
29
index XXXXXXX..XXXXXXX 100644
30
--- a/MAINTAINERS
31
+++ b/MAINTAINERS
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
33
F: hw/pci-host/designware.c
34
F: include/hw/pci-host/designware.h
35
36
-MPS2
37
+MPS2 / MPS3
38
M: Peter Maydell <peter.maydell@linaro.org>
39
L: qemu-arm@nongnu.org
40
S: Maintained
41
F: hw/arm/mps2.c
42
F: hw/arm/mps2-tz.c
43
+F: hw/arm/mps3r.c
44
F: hw/misc/mps2-*.c
45
F: include/hw/misc/mps2-*.h
46
F: hw/arm/armsse.c
47
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
48
index XXXXXXX..XXXXXXX 100644
49
--- a/configs/devices/arm-softmmu/default.mak
50
+++ b/configs/devices/arm-softmmu/default.mak
51
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
52
# CONFIG_INTEGRATOR=n
53
# CONFIG_FSL_IMX31=n
54
# CONFIG_MUSICPAL=n
55
+# CONFIG_MPS3R=n
56
# CONFIG_MUSCA=n
57
# CONFIG_CHEETAH=n
58
# CONFIG_SX1=n
59
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
60
new file mode 100644
61
index XXXXXXX..XXXXXXX
62
--- /dev/null
63
+++ b/hw/arm/mps3r.c
64
@@ -XXX,XX +XXX,XX @@
65
+/*
66
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
67
+ * (For M-profile images see mps2.c and mps2tz.c.)
68
+ *
69
+ * Copyright (c) 2017 Linaro Limited
70
+ * Written by Peter Maydell
71
+ *
72
+ * This program is free software; you can redistribute it and/or modify
73
+ * it under the terms of the GNU General Public License version 2 or
74
+ * (at your option) any later version.
75
+ */
76
+
77
+/*
78
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
79
+ * which use the Cortex-R CPUs. We model these separately from the
80
+ * M-profile images, because on M-profile the FPGA image is based on
81
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
82
+ * the R-profile FPGA images don't have that abstraction layer.
83
+ *
84
+ * We model the following FPGA images here:
85
+ * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
86
+ *
87
+ * Application Note AN536:
88
+ * https://developer.arm.com/documentation/dai0536/latest/
89
+ */
90
+
91
+#include "qemu/osdep.h"
92
+#include "qemu/units.h"
93
+#include "qapi/error.h"
94
+#include "exec/address-spaces.h"
95
+#include "cpu.h"
96
+#include "hw/boards.h"
97
+#include "hw/arm/boot.h"
98
+
99
+/* Define the layout of RAM and ROM in a board */
100
+typedef struct RAMInfo {
101
+ const char *name;
102
+ hwaddr base;
103
+ hwaddr size;
104
+ int mrindex; /* index into rams[]; -1 for the system RAM block */
105
+ int flags;
106
+} RAMInfo;
107
+
108
+/*
109
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
110
+ * emulation of that much guest RAM, so artificially make it smaller.
111
+ */
112
+#if HOST_LONG_BITS == 32
113
+#define MPS3_DDR_SIZE (1 * GiB)
114
+#else
115
+#define MPS3_DDR_SIZE (3 * GiB)
116
+#endif
117
+
118
+/*
119
+ * Flag values:
120
+ * IS_MAIN: this is the main machine RAM
121
+ * IS_ROM: this area is read-only
122
+ */
123
+#define IS_MAIN 1
124
+#define IS_ROM 2
125
+
126
+#define MPS3R_RAM_MAX 9
127
+
128
+typedef enum MPS3RFPGAType {
129
+ FPGA_AN536,
130
+} MPS3RFPGAType;
131
+
132
+struct MPS3RMachineClass {
133
+ MachineClass parent;
134
+ MPS3RFPGAType fpga_type;
135
+ const RAMInfo *raminfo;
136
+};
137
+
138
+struct MPS3RMachineState {
139
+ MachineState parent;
140
+ MemoryRegion ram[MPS3R_RAM_MAX];
141
+};
142
+
143
+#define TYPE_MPS3R_MACHINE "mps3r"
144
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
145
+
146
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
147
+
148
+static const RAMInfo an536_raminfo[] = {
149
+ {
150
+ .name = "ATCM",
151
+ .base = 0x00000000,
152
+ .size = 0x00008000,
153
+ .mrindex = 0,
154
+ }, {
155
+ /* We model the QSPI flash as simple ROM for now */
156
+ .name = "QSPI",
157
+ .base = 0x08000000,
158
+ .size = 0x00800000,
159
+ .flags = IS_ROM,
160
+ .mrindex = 1,
161
+ }, {
162
+ .name = "BRAM",
163
+ .base = 0x10000000,
164
+ .size = 0x00080000,
165
+ .mrindex = 2,
166
+ }, {
167
+ .name = "DDR",
168
+ .base = 0x20000000,
169
+ .size = MPS3_DDR_SIZE,
170
+ .mrindex = -1,
171
+ }, {
172
+ .name = "ATCM0",
173
+ .base = 0xee000000,
174
+ .size = 0x00008000,
175
+ .mrindex = 3,
176
+ }, {
177
+ .name = "BTCM0",
178
+ .base = 0xee100000,
179
+ .size = 0x00008000,
180
+ .mrindex = 4,
181
+ }, {
182
+ .name = "CTCM0",
183
+ .base = 0xee200000,
184
+ .size = 0x00008000,
185
+ .mrindex = 5,
186
+ }, {
187
+ .name = "ATCM1",
188
+ .base = 0xee400000,
189
+ .size = 0x00008000,
190
+ .mrindex = 6,
191
+ }, {
192
+ .name = "BTCM1",
193
+ .base = 0xee500000,
194
+ .size = 0x00008000,
195
+ .mrindex = 7,
196
+ }, {
197
+ .name = "CTCM1",
198
+ .base = 0xee600000,
199
+ .size = 0x00008000,
200
+ .mrindex = 8,
201
+ }, {
202
+ .name = NULL,
203
+ }
204
+};
205
+
206
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
207
+ const RAMInfo *raminfo)
208
+{
209
+ /* Return an initialized MemoryRegion for the RAMInfo. */
210
+ MemoryRegion *ram;
211
+
212
+ if (raminfo->mrindex < 0) {
213
+ /* Means this RAMInfo is for QEMU's "system memory" */
214
+ MachineState *machine = MACHINE(mms);
215
+ assert(!(raminfo->flags & IS_ROM));
216
+ return machine->ram;
217
+ }
218
+
219
+ assert(raminfo->mrindex < MPS3R_RAM_MAX);
220
+ ram = &mms->ram[raminfo->mrindex];
221
+
222
+ memory_region_init_ram(ram, NULL, raminfo->name,
223
+ raminfo->size, &error_fatal);
224
+ if (raminfo->flags & IS_ROM) {
225
+ memory_region_set_readonly(ram, true);
226
+ }
227
+ return ram;
228
+}
229
+
230
+static void mps3r_common_init(MachineState *machine)
231
+{
232
+ MPS3RMachineState *mms = MPS3R_MACHINE(machine);
233
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
234
+ MemoryRegion *sysmem = get_system_memory();
235
+
236
+ for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
237
+ MemoryRegion *mr = mr_for_raminfo(mms, ri);
238
+ memory_region_add_subregion(sysmem, ri->base, mr);
239
+ }
240
+}
241
+
242
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
243
+{
244
+ /*
245
+ * Set mc->default_ram_size and default_ram_id from the
246
+ * information in mmc->raminfo.
247
+ */
248
+ MachineClass *mc = MACHINE_CLASS(mmc);
249
+ const RAMInfo *p;
250
+
251
+ for (p = mmc->raminfo; p->name; p++) {
252
+ if (p->mrindex < 0) {
253
+ /* Found the entry for "system memory" */
254
+ mc->default_ram_size = p->size;
255
+ mc->default_ram_id = p->name;
256
+ return;
257
+ }
258
+ }
259
+ g_assert_not_reached();
260
+}
261
+
262
+static void mps3r_class_init(ObjectClass *oc, void *data)
263
+{
264
+ MachineClass *mc = MACHINE_CLASS(oc);
265
+
266
+ mc->init = mps3r_common_init;
267
+}
268
+
269
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
270
+{
271
+ MachineClass *mc = MACHINE_CLASS(oc);
272
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
273
+ static const char * const valid_cpu_types[] = {
274
+ ARM_CPU_TYPE_NAME("cortex-r52"),
275
+ NULL
276
+ };
277
+
278
+ mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
279
+ mc->default_cpus = 2;
280
+ mc->min_cpus = mc->default_cpus;
281
+ mc->max_cpus = mc->default_cpus;
282
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
283
+ mc->valid_cpu_types = valid_cpu_types;
284
+ mmc->raminfo = an536_raminfo;
285
+ mps3r_set_default_ram_info(mmc);
286
+}
287
+
288
+static const TypeInfo mps3r_machine_types[] = {
289
+ {
290
+ .name = TYPE_MPS3R_MACHINE,
291
+ .parent = TYPE_MACHINE,
292
+ .abstract = true,
293
+ .instance_size = sizeof(MPS3RMachineState),
294
+ .class_size = sizeof(MPS3RMachineClass),
295
+ .class_init = mps3r_class_init,
296
+ }, {
297
+ .name = TYPE_MPS3R_AN536_MACHINE,
298
+ .parent = TYPE_MPS3R_MACHINE,
299
+ .class_init = mps3r_an536_class_init,
300
+ },
301
+};
302
+
303
+DEFINE_TYPES(mps3r_machine_types);
304
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
305
index XXXXXXX..XXXXXXX 100644
306
--- a/hw/arm/Kconfig
307
+++ b/hw/arm/Kconfig
308
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
309
select PFLASH_CFI01
310
select SMC91C111
311
312
+config MPS3R
313
+ bool
314
+ default y
315
+ depends on TCG && ARM
316
+
317
config MUSCA
318
bool
319
default y
320
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/arm/meson.build
323
+++ b/hw/arm/meson.build
324
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
325
arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
326
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
327
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
328
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
329
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
330
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
331
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
332
--
333
2.34.1
334
335
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/18] xlnx-zcu102: Add a machine level secure property
[PULL 31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
Create the CPUs, the GIC, and the per-CPU RAM block for
2
the mps3-an536 board.
2
3
3
Add a machine level secure property. This defaults to false and can be
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
set to true using this machine command line argument:
5
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
5
-machine xlnx-zcu102,secure=on
6
---
7
hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
8
1 file changed, 177 insertions(+), 3 deletions(-)
6
9
7
This follows what the ARM virt machine does.
10
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
8
9
This property only applies to the ZCU102 machine. The EP108 machine does
10
not have this property.
11
12
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/xlnx-zcu102.c | 32 ++++++++++++++++++++++++++++++++
17
1 file changed, 32 insertions(+)
18
19
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/xlnx-zcu102.c
12
--- a/hw/arm/mps3r.c
22
+++ b/hw/arm/xlnx-zcu102.c
13
+++ b/hw/arm/mps3r.c
23
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
14
@@ -XXX,XX +XXX,XX @@
24
15
#include "qemu/osdep.h"
25
XlnxZynqMPState soc;
16
#include "qemu/units.h"
26
MemoryRegion ddr_ram;
17
#include "qapi/error.h"
27
+
18
+#include "qapi/qmp/qlist.h"
28
+ bool secure;
19
#include "exec/address-spaces.h"
29
} XlnxZCU102;
20
#include "cpu.h"
30
21
#include "hw/boards.h"
31
#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
22
+#include "hw/qdev-properties.h"
32
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
23
#include "hw/arm/boot.h"
33
24
+#include "hw/arm/bsa.h"
34
static struct arm_boot_info xlnx_zcu102_binfo;
25
+#include "hw/intc/arm_gicv3.h"
35
26
36
+static bool zcu102_get_secure(Object *obj, Error **errp)
27
/* Define the layout of RAM and ROM in a board */
28
typedef struct RAMInfo {
29
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
30
#define IS_ROM 2
31
32
#define MPS3R_RAM_MAX 9
33
+#define MPS3R_CPU_MAX 2
34
+
35
+#define PERIPHBASE 0xf0000000
36
+#define NUM_SPIS 96
37
38
typedef enum MPS3RFPGAType {
39
FPGA_AN536,
40
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
41
MachineClass parent;
42
MPS3RFPGAType fpga_type;
43
const RAMInfo *raminfo;
44
+ hwaddr loader_start;
45
};
46
47
struct MPS3RMachineState {
48
MachineState parent;
49
+ struct arm_boot_info bootinfo;
50
MemoryRegion ram[MPS3R_RAM_MAX];
51
+ Object *cpu[MPS3R_CPU_MAX];
52
+ MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
53
+ MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
54
+ MemoryRegion cpu_ram[MPS3R_CPU_MAX];
55
+ GICv3State gic;
56
};
57
58
#define TYPE_MPS3R_MACHINE "mps3r"
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
60
return ram;
61
}
62
63
+/*
64
+ * There is no defined secondary boot protocol for Linux for the AN536,
65
+ * because real hardware has a restriction that atomic operations between
66
+ * the two CPUs do not function correctly, and so true SMP is not
67
+ * possible. Therefore for cases where the user is directly booting
68
+ * a kernel, we treat the system as essentially uniprocessor, and
69
+ * put the secondary CPU into power-off state (as if the user on the
70
+ * real hardware had configured the secondary to be halted via the
71
+ * SCC config registers).
72
+ *
73
+ * Note that the default secondary boot code would not work here anyway
74
+ * as it assumes a GICv2, and we have a GICv3.
75
+ */
76
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
77
+ const struct arm_boot_info *info)
37
+{
78
+{
38
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
79
+ /*
39
+
80
+ * Power the secondary CPU off. This means we don't need to write any
40
+ return s->secure;
81
+ * boot code into guest memory. Note that the 'cpu' argument to this
82
+ * function is the primary CPU we passed to arm_load_kernel(), not
83
+ * the secondary. Loop around all the other CPUs, as the boot.c
84
+ * code does for the "disable secondaries if PSCI is enabled" case.
85
+ */
86
+ for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
87
+ if (cs != first_cpu) {
88
+ object_property_set_bool(OBJECT(cs), "start-powered-off", true,
89
+ &error_abort);
90
+ }
91
+ }
41
+}
92
+}
42
+
93
+
43
+static void zcu102_set_secure(Object *obj, bool value, Error **errp)
94
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
44
+{
96
+{
45
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
97
+ /* We don't need to do anything here because the CPU will be off */
46
+
47
+ s->secure = value;
48
+}
98
+}
49
+
99
+
50
static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
100
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
101
+{
102
+ MachineState *machine = MACHINE(mms);
103
+ DeviceState *gicdev;
104
+ QList *redist_region_count;
105
+
106
+ object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
107
+ gicdev = DEVICE(&mms->gic);
108
+ qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
109
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
110
+ redist_region_count = qlist_new();
111
+ qlist_append_int(redist_region_count, machine->smp.cpus);
112
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
113
+ object_property_set_link(OBJECT(&mms->gic), "sysmem",
114
+ OBJECT(sysmem), &error_fatal);
115
+ sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
116
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
118
+ /*
119
+ * Wire the outputs from each CPU's generic timer and the GICv3
120
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
121
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
122
+ */
123
+ for (int i = 0; i < machine->smp.cpus; i++) {
124
+ DeviceState *cpudev = DEVICE(mms->cpu[i]);
125
+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
126
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
127
+ int irq;
128
+ /*
129
+ * Mapping from the output timer irq lines from the CPU to the
130
+ * GIC PPI inputs used for this board. This isn't a BSA board,
131
+ * but it uses the standard convention for the PPI numbers.
132
+ */
133
+ const int timer_irq[] = {
134
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
135
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
136
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
137
+ };
138
+
139
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
140
+ qdev_connect_gpio_out(cpudev, irq,
141
+ qdev_get_gpio_in(gicdev,
142
+ intidbase + timer_irq[irq]));
143
+ }
144
+
145
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
146
+ qdev_get_gpio_in(gicdev,
147
+ intidbase + ARCH_GIC_MAINT_IRQ));
148
+
149
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
150
+ qdev_get_gpio_in(gicdev,
151
+ intidbase + VIRTUAL_PMU_IRQ));
152
+
153
+ sysbus_connect_irq(gicsbd, i,
154
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
155
+ sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
156
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
157
+ sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
158
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
159
+ sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
160
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
161
+ }
162
+}
163
+
164
static void mps3r_common_init(MachineState *machine)
51
{
165
{
52
int i;
166
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
53
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
167
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
54
168
MemoryRegion *mr = mr_for_raminfo(mms, ri);
55
object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram),
169
memory_region_add_subregion(sysmem, ri->base, mr);
56
"ddr-ram", &error_abort);
170
}
57
+ object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
171
+
58
+ &error_fatal);
172
+ assert(machine->smp.cpus <= MPS3R_CPU_MAX);
59
173
+ for (int i = 0; i < machine->smp.cpus; i++) {
60
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
174
+ g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
61
175
+ g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)
176
+ g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
63
177
+
64
static void xlnx_ep108_machine_instance_init(Object *obj)
178
+ /*
65
{
179
+ * Each CPU has some private RAM/peripherals, so create the container
66
+ XlnxZCU102 *s = EP108_MACHINE(obj);
180
+ * which will house those, with the whole-machine system memory being
67
+
181
+ * used where there's no CPU-specific device. Note that we need the
68
+ /* EP108, we don't support setting secure */
182
+ * sysmem_alias aliases because we can't put one MR (the original
69
+ s->secure = false;
183
+ * 'sysmem') into more than one other MR.
184
+ */
185
+ memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
186
+ sysmem_name, UINT64_MAX);
187
+ memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
188
+ alias_name, sysmem, 0, UINT64_MAX);
189
+ memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
190
+ &mms->sysmem_alias[i], -1);
191
+
192
+ mms->cpu[i] = object_new(machine->cpu_type);
193
+ object_property_set_link(mms->cpu[i], "memory",
194
+ OBJECT(&mms->cpu_sysmem[i]), &error_abort);
195
+ object_property_set_int(mms->cpu[i], "reset-cbar",
196
+ PERIPHBASE, &error_abort);
197
+ qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
198
+ object_unref(mms->cpu[i]);
199
+
200
+ /* Per-CPU RAM */
201
+ memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
202
+ 0x1000, &error_fatal);
203
+ memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
204
+ &mms->cpu_ram[i]);
205
+ }
206
+
207
+ create_gic(mms, sysmem);
208
+
209
+ mms->bootinfo.ram_size = machine->ram_size;
210
+ mms->bootinfo.board_id = -1;
211
+ mms->bootinfo.loader_start = mmc->loader_start;
212
+ mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
213
+ mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
214
+ arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
70
}
215
}
71
216
72
static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
217
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
73
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
218
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
74
219
/* Found the entry for "system memory" */
75
static void xlnx_zcu102_machine_instance_init(Object *obj)
220
mc->default_ram_size = p->size;
76
{
221
mc->default_ram_id = p->name;
77
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
222
+ mmc->loader_start = p->base;
78
+
223
return;
79
+ /* Default to secure mode being disabled */
224
}
80
+ s->secure = false;
225
}
81
+ object_property_add_bool(obj, "secure", zcu102_get_secure,
226
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
82
+ zcu102_set_secure, NULL);
227
};
83
+ object_property_set_description(obj, "secure",
228
84
+ "Set on/off to enable/disable the ARM "
229
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
85
+ "Security Extensions (TrustZone)",
230
- mc->default_cpus = 2;
86
+ NULL);
231
- mc->min_cpus = mc->default_cpus;
87
}
232
- mc->max_cpus = mc->default_cpus;
88
233
+ /*
89
static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
234
+ * In the real FPGA image there are always two cores, but the standard
235
+ * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
236
+ * that the second core is held in reset and halted. Many images built for
237
+ * the board do not expect the second core to run at startup (especially
238
+ * since on the real FPGA image it is not possible to use LDREX/STREX
239
+ * in RAM between the two cores, so a true SMP setup isn't supported).
240
+ *
241
+ * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
242
+ * with the default being -smp 1. This seems a more intuitive UI for
243
+ * QEMU users than, for instance, having a machine property to allow
244
+ * the user to set the initial value of the SYSCON 0x000 register.
245
+ */
246
+ mc->default_cpus = 1;
247
+ mc->min_cpus = 1;
248
+ mc->max_cpus = 2;
249
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
250
mc->valid_cpu_types = valid_cpu_types;
251
mmc->raminfo = an536_raminfo;
90
--
252
--
91
2.7.4
253
2.34.1
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/18] hw/pci-host/gpex: Set INTx index/gsi mapping
[PULL 32/35] hw/arm/mps3r: Add UARTs
1
From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
1
This board has a lot of UARTs: there is one UART per CPU in the
2
per-CPU peripheral part of the address map, whose interrupts are
3
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
4
normal part of the peripheral space, whose interrupts are shared
5
peripheral interrupts.
2
6
3
To implement INTx to gsi routing we need to pass the gpex host
7
Connect and wire them all up; this involves some OR gates where
4
bridge the gsi associated to each INTx index. Let's introduce
8
multiple overflow interrupts are wired into one GIC input.
5
irq_num array and gpex_set_irq_num setter function.
6
9
7
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
8
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Tested-by: Feng Kan <fkan@apm.com>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Message-id: 1505296004-6798-2-git-send-email-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
14
---
13
---
15
include/hw/pci-host/gpex.h | 3 +++
14
hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
16
hw/pci-host/gpex.c | 10 ++++++++++
15
1 file changed, 94 insertions(+)
17
2 files changed, 13 insertions(+)
18
16
19
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
17
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/pci-host/gpex.h
19
--- a/hw/arm/mps3r.c
22
+++ b/include/hw/pci-host/gpex.h
20
+++ b/hw/arm/mps3r.c
23
@@ -XXX,XX +XXX,XX @@ typedef struct GPEXHost {
21
@@ -XXX,XX +XXX,XX @@
24
MemoryRegion io_ioport;
22
#include "qapi/qmp/qlist.h"
25
MemoryRegion io_mmio;
23
#include "exec/address-spaces.h"
26
qemu_irq irq[GPEX_NUM_IRQS];
24
#include "cpu.h"
27
+ int irq_num[GPEX_NUM_IRQS];
25
+#include "sysemu/sysemu.h"
28
} GPEXHost;
26
#include "hw/boards.h"
29
27
+#include "hw/or-irq.h"
30
+int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
28
#include "hw/qdev-properties.h"
29
#include "hw/arm/boot.h"
30
#include "hw/arm/bsa.h"
31
+#include "hw/char/cmsdk-apb-uart.h"
32
#include "hw/intc/arm_gicv3.h"
33
34
/* Define the layout of RAM and ROM in a board */
35
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
36
37
#define MPS3R_RAM_MAX 9
38
#define MPS3R_CPU_MAX 2
39
+#define MPS3R_UART_MAX 4 /* shared UART count */
40
41
#define PERIPHBASE 0xf0000000
42
#define NUM_SPIS 96
43
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
44
MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
45
MemoryRegion cpu_ram[MPS3R_CPU_MAX];
46
GICv3State gic;
47
+ /* per-CPU UARTs followed by the shared UARTs */
48
+ CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
49
+ OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
50
+ OrIRQState uart_oflow;
51
};
52
53
#define TYPE_MPS3R_MACHINE "mps3r"
54
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
55
56
OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
57
58
+/*
59
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
60
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
61
+ * model we just roll them all into one.
62
+ */
63
+#define CLK_FRQ 50000000
31
+
64
+
32
#endif /* HW_GPEX_H */
65
static const RAMInfo an536_raminfo[] = {
33
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
66
{
34
index XXXXXXX..XXXXXXX 100644
67
.name = "ATCM",
35
--- a/hw/pci-host/gpex.c
68
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
36
+++ b/hw/pci-host/gpex.c
69
}
37
@@ -XXX,XX +XXX,XX @@ static void gpex_set_irq(void *opaque, int irq_num, int level)
38
qemu_set_irq(s->irq[irq_num], level);
39
}
70
}
40
71
41
+int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
72
+/*
73
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
74
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
75
+ */
76
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
77
+ hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
78
+ qemu_irq txoverirq, qemu_irq rxoverirq,
79
+ qemu_irq combirq)
42
+{
80
+{
43
+ if (index >= GPEX_NUM_IRQS) {
81
+ g_autofree char *s = g_strdup_printf("uart%d", uartno);
44
+ return -EINVAL;
82
+ SysBusDevice *sbd;
45
+ }
46
+
83
+
47
+ s->irq_num[index] = gsi;
84
+ assert(uartno < ARRAY_SIZE(mms->uart));
48
+ return 0;
85
+ object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
86
+ TYPE_CMSDK_APB_UART);
87
+ qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
88
+ qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
89
+ sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
90
+ sysbus_realize(sbd, &error_fatal);
91
+ memory_region_add_subregion(mem, baseaddr,
92
+ sysbus_mmio_get_region(sbd, 0));
93
+ sysbus_connect_irq(sbd, 0, txirq);
94
+ sysbus_connect_irq(sbd, 1, rxirq);
95
+ sysbus_connect_irq(sbd, 2, txoverirq);
96
+ sysbus_connect_irq(sbd, 3, rxoverirq);
97
+ sysbus_connect_irq(sbd, 4, combirq);
49
+}
98
+}
50
+
99
+
51
static void gpex_host_realize(DeviceState *dev, Error **errp)
100
static void mps3r_common_init(MachineState *machine)
52
{
101
{
53
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
102
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
103
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
104
MemoryRegion *sysmem = get_system_memory();
105
+ DeviceState *gicdev;
106
107
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
108
MemoryRegion *mr = mr_for_raminfo(mms, ri);
109
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
110
}
111
112
create_gic(mms, sysmem);
113
+ gicdev = DEVICE(&mms->gic);
114
+
115
+ /*
116
+ * UARTs 0 and 1 are per-CPU; their interrupts are wired to
117
+ * the relevant CPU's PPI 0..3, aka INTID 16..19
118
+ */
119
+ for (int i = 0; i < machine->smp.cpus; i++) {
120
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
121
+ g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
122
+ DeviceState *orgate;
123
+
124
+ /* The two overflow IRQs from the UART are ORed together into PPI 3 */
125
+ object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
126
+ TYPE_OR_IRQ);
127
+ orgate = DEVICE(&mms->cpu_uart_oflow[i]);
128
+ qdev_prop_set_uint32(orgate, "num-lines", 2);
129
+ qdev_realize(orgate, NULL, &error_fatal);
130
+ qdev_connect_gpio_out(orgate, 0,
131
+ qdev_get_gpio_in(gicdev, intidbase + 19));
132
+
133
+ create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
134
+ qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
135
+ qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
136
+ qdev_get_gpio_in(orgate, 0), /* txover */
137
+ qdev_get_gpio_in(orgate, 1), /* rxover */
138
+ qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
139
+ }
140
+ /*
141
+ * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
142
+ * together into IRQ 17
143
+ */
144
+ object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
145
+ &mms->uart_oflow, TYPE_OR_IRQ);
146
+ qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
147
+ MPS3R_UART_MAX * 2);
148
+ qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
149
+ qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
150
+ qdev_get_gpio_in(gicdev, 17));
151
+
152
+ for (int i = 0; i < MPS3R_UART_MAX; i++) {
153
+ hwaddr baseaddr = 0xe0205000 + i * 0x1000;
154
+ int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
155
+
156
+ create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
157
+ qdev_get_gpio_in(gicdev, txirq),
158
+ qdev_get_gpio_in(gicdev, rxirq),
159
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
160
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
161
+ qdev_get_gpio_in(gicdev, combirq));
162
+ }
163
164
mms->bootinfo.ram_size = machine->ram_size;
165
mms->bootinfo.board_id = -1;
54
--
166
--
55
2.7.4
167
2.34.1
56
168
57
169
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/18] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
[PULL 33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
1
For M profile we must clear the exclusive monitor on reset, exception
1
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
2
entry and exception exit. We weren't doing any of these things; fix
2
board. These are all simple devices that just need to be created and
3
this bug.
3
wired up.
4
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
8
Message-id: 1505137930-13255-3-git-send-email-peter.maydell@linaro.org
9
---
8
---
10
target/arm/internals.h | 10 ++++++++++
9
hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
11
target/arm/cpu.c | 6 ++++++
10
1 file changed, 59 insertions(+)
12
target/arm/helper.c | 2 ++
13
target/arm/op_helper.c | 2 +-
14
4 files changed, 19 insertions(+), 1 deletion(-)
15
11
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
14
--- a/hw/arm/mps3r.c
19
+++ b/target/arm/internals.h
15
+++ b/hw/arm/mps3r.c
20
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu);
16
@@ -XXX,XX +XXX,XX @@
21
#endif
17
#include "sysemu/sysemu.h"
22
18
#include "hw/boards.h"
23
/**
19
#include "hw/or-irq.h"
24
+ * arm_clear_exclusive: clear the exclusive monitor
20
+#include "hw/qdev-clock.h"
25
+ * @env: CPU env
21
#include "hw/qdev-properties.h"
26
+ * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
22
#include "hw/arm/boot.h"
27
+ */
23
#include "hw/arm/bsa.h"
28
+static inline void arm_clear_exclusive(CPUARMState *env)
24
#include "hw/char/cmsdk-apb-uart.h"
29
+{
25
+#include "hw/i2c/arm_sbcon_i2c.h"
30
+ env->exclusive_addr = -1;
26
#include "hw/intc/arm_gicv3.h"
31
+}
27
+#include "hw/misc/unimp.h"
28
+#include "hw/timer/cmsdk-apb-dualtimer.h"
29
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
30
31
/* Define the layout of RAM and ROM in a board */
32
typedef struct RAMInfo {
33
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
34
CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
35
OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
36
OrIRQState uart_oflow;
37
+ CMSDKAPBWatchdog watchdog;
38
+ CMSDKAPBDualTimer dualtimer;
39
+ ArmSbconI2CState i2c[5];
40
+ Clock *clk;
41
};
42
43
#define TYPE_MPS3R_MACHINE "mps3r"
44
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
45
MemoryRegion *sysmem = get_system_memory();
46
DeviceState *gicdev;
47
48
+ mms->clk = clock_new(OBJECT(machine), "CLK");
49
+ clock_set_hz(mms->clk, CLK_FRQ);
32
+
50
+
33
+/**
51
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
34
* ARMMMUFaultInfo: Information describing an ARM MMU Fault
52
MemoryRegion *mr = mr_for_raminfo(mms, ri);
35
* @s2addr: Address that caused a fault at stage 2
53
memory_region_add_subregion(sysmem, ri->base, mr);
36
* @stage2: True if we faulted at stage 2
54
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
37
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
55
qdev_get_gpio_in(gicdev, combirq));
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu.c
40
+++ b/target/arm/cpu.c
41
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
42
env->regs[15] = 0xFFFF0000;
43
}
56
}
44
57
45
+ /* M profile requires that reset clears the exclusive monitor;
58
+ for (int i = 0; i < 4; i++) {
46
+ * A profile does not, but clearing it makes more sense than having it
59
+ /* CMSDK GPIO controllers */
47
+ * set with an exclusive access on address zero.
60
+ g_autofree char *s = g_strdup_printf("gpio%d", i);
48
+ */
61
+ create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
49
+ arm_clear_exclusive(env);
62
+ }
50
+
63
+
51
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
64
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
52
#endif
65
+ TYPE_CMSDK_APB_WATCHDOG);
53
66
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
54
diff --git a/target/arm/helper.c b/target/arm/helper.c
67
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
55
index XXXXXXX..XXXXXXX 100644
68
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
56
--- a/target/arm/helper.c
69
+ qdev_get_gpio_in(gicdev, 0));
57
+++ b/target/arm/helper.c
70
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
58
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr)
71
+
59
72
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
60
armv7m_nvic_acknowledge_irq(env->nvic);
73
+ TYPE_CMSDK_APB_DUALTIMER);
61
switch_v7m_sp(env, 0);
74
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
62
+ arm_clear_exclusive(env);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
63
/* Clear IT bits */
76
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
64
env->condexec_bits = 0;
77
+ qdev_get_gpio_in(gicdev, 3));
65
env->regs[14] = lr;
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
66
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
79
+ qdev_get_gpio_in(gicdev, 1));
67
}
80
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
68
81
+ qdev_get_gpio_in(gicdev, 2));
69
/* Otherwise, we have a successful exception exit. */
82
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
70
+ arm_clear_exclusive(env);
83
+
71
qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
84
+ for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
72
}
85
+ static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
73
86
+ 0xe0103000, /* Audio */
74
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
87
+ 0xe0107000, /* Shield0 */
75
index XXXXXXX..XXXXXXX 100644
88
+ 0xe0108000, /* Shield1 */
76
--- a/target/arm/op_helper.c
89
+ 0xe0109000}; /* DDR4 EEPROM */
77
+++ b/target/arm/op_helper.c
90
+ g_autofree char *s = g_strdup_printf("i2c%d", i);
78
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env)
91
+
79
92
+ object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
80
aarch64_save_sp(env, cur_el);
93
+ TYPE_ARM_SBCON_I2C);
81
94
+ sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
82
- env->exclusive_addr = -1;
95
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
83
+ arm_clear_exclusive(env);
96
+ if (i != 2 && i != 3) {
84
97
+ /*
85
/* We must squash the PSTATE.SS bit to zero unless both of the
98
+ * internal-only bus: mark it full to avoid user-created
86
* following hold:
99
+ * i2c devices being plugged into it.
100
+ */
101
+ qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
102
+ }
103
+ }
104
+
105
mms->bootinfo.ram_size = machine->ram_size;
106
mms->bootinfo.board_id = -1;
107
mms->bootinfo.loader_start = mmc->loader_start;
87
--
108
--
88
2.7.4
109
2.34.1
89
110
90
111
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/18] nvic: Don't apply group priority mask to negative priorities
[PULL 34/35] hw/arm/mps3r: Add remaining devices
1
In several places we were unconditionally applying the
1
Add the remaining devices (or unimplemented-device stubs) for
2
nvic_gprio_mask() to a priority value. This is incorrect
2
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
3
if the priority is one of the fixed negative priority
3
QSPI write-config block, and ethernet.
4
values (for NMI and HardFault), so don't do it.
5
6
This bug would have caused both NMI and HardFault to be
7
considered as the same priority and so NMI wouldn't
8
correctly preempt HardFault.
9
4
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 1505137930-13255-5-git-send-email-peter.maydell@linaro.org
7
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
13
---
8
---
14
hw/intc/armv7m_nvic.c | 11 +++++++++--
9
hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
15
1 file changed, 9 insertions(+), 2 deletions(-)
10
1 file changed, 74 insertions(+)
16
11
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
14
--- a/hw/arm/mps3r.c
20
+++ b/hw/intc/armv7m_nvic.c
15
+++ b/hw/arm/mps3r.c
21
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
16
@@ -XXX,XX +XXX,XX @@
17
#include "hw/char/cmsdk-apb-uart.h"
18
#include "hw/i2c/arm_sbcon_i2c.h"
19
#include "hw/intc/arm_gicv3.h"
20
+#include "hw/misc/mps2-scc.h"
21
+#include "hw/misc/mps2-fpgaio.h"
22
#include "hw/misc/unimp.h"
23
+#include "hw/net/lan9118.h"
24
+#include "hw/rtc/pl031.h"
25
+#include "hw/ssi/pl022.h"
26
#include "hw/timer/cmsdk-apb-dualtimer.h"
27
#include "hw/watchdog/cmsdk-apb-watchdog.h"
28
29
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
30
CMSDKAPBWatchdog watchdog;
31
CMSDKAPBDualTimer dualtimer;
32
ArmSbconI2CState i2c[5];
33
+ PL022State spi[3];
34
+ MPS2SCC scc;
35
+ MPS2FPGAIO fpgaio;
36
+ UnimplementedDeviceState i2s_audio;
37
+ PL031State rtc;
38
Clock *clk;
39
};
40
41
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
42
}
43
};
44
45
+static const int an536_oscclk[] = {
46
+ 24000000, /* 24MHz reference for RTC and timers */
47
+ 50000000, /* 50MHz ACLK */
48
+ 50000000, /* 50MHz MCLK */
49
+ 50000000, /* 50MHz GPUCLK */
50
+ 24576000, /* 24.576MHz AUDCLK */
51
+ 23750000, /* 23.75MHz HDLCDCLK */
52
+ 100000000, /* 100MHz DDR4_REF_CLK */
53
+};
54
+
55
static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
56
const RAMInfo *raminfo)
57
{
58
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
59
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
60
MemoryRegion *sysmem = get_system_memory();
61
DeviceState *gicdev;
62
+ QList *oscclk;
63
64
mms->clk = clock_new(OBJECT(machine), "CLK");
65
clock_set_hz(mms->clk, CLK_FRQ);
66
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
22
}
67
}
23
}
68
}
24
69
25
+ if (active_prio > 0) {
70
+ for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
26
+ active_prio &= nvic_gprio_mask(s);
71
+ g_autofree char *s = g_strdup_printf("spi%d", i);
72
+ hwaddr baseaddr = 0xe0104000 + i * 0x1000;
73
+
74
+ object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
77
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
78
+ qdev_get_gpio_in(gicdev, 22 + i));
27
+ }
79
+ }
28
+
80
+
29
s->vectpending = pend_irq;
81
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
30
- s->exception_prio = active_prio & nvic_gprio_mask(s);
82
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
31
+ s->exception_prio = active_prio;
83
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
32
84
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
33
trace_nvic_recompute_state(s->vectpending, s->exception_prio);
85
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
34
}
86
+ oscclk = qlist_new();
35
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
87
+ for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
36
assert(vec->enabled);
88
+ qlist_append_int(oscclk, an536_oscclk[i]);
37
assert(vec->pending);
38
39
- pendgroupprio = vec->prio & nvic_gprio_mask(s);
40
+ pendgroupprio = vec->prio;
41
+ if (pendgroupprio > 0) {
42
+ pendgroupprio &= nvic_gprio_mask(s);
43
+ }
89
+ }
44
assert(pendgroupprio < running);
90
+ qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
45
91
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
46
trace_nvic_acknowledge_irq(pending, vec->prio);
92
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
93
+
94
+ create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
95
+
96
+ object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
97
+ TYPE_MPS2_FPGAIO);
98
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
99
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
100
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
101
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
102
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
104
+
105
+ create_unimplemented_device("clcd", 0xe0209000, 0x1000);
106
+
107
+ object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
108
+ sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
109
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
110
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
111
+ qdev_get_gpio_in(gicdev, 4));
112
+
113
+ /*
114
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
115
+ * except that it doesn't support the checksum-offload feature.
116
+ */
117
+ lan9118_init(0xe0300000,
118
+ qdev_get_gpio_in(gicdev, 18));
119
+
120
+ create_unimplemented_device("usb", 0xe0301000, 0x1000);
121
+ create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
122
+
123
mms->bootinfo.ram_size = machine->ram_size;
124
mms->bootinfo.board_id = -1;
125
mms->bootinfo.loader_start = mmc->loader_start;
47
--
126
--
48
2.7.4
127
2.34.1
49
128
50
129
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/18] target/arm: Get PRECISERR and IBUSERR the right way round
[PULL 35/35] docs: Add documentation for the mps3-an536 board
1
For a bus fault, the M profile BFSR bit PRECISERR means a bus
1
Add documentation for the mps3-an536 board type.
2
fault on a data access, and IBUSERR means a bus fault on an
3
instruction access. We had these the wrong way around; fix this.
4
2
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
8
Message-id: 1505137930-13255-4-git-send-email-peter.maydell@linaro.org
9
---
6
---
10
target/arm/helper.c | 8 ++++----
7
docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
11
1 file changed, 4 insertions(+), 4 deletions(-)
8
1 file changed, 34 insertions(+), 3 deletions(-)
12
9
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
10
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
12
--- a/docs/system/arm/mps2.rst
16
+++ b/target/arm/helper.c
13
+++ b/docs/system/arm/mps2.rst
17
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
14
@@ -XXX,XX +XXX,XX @@
18
case 0x8: /* External Abort */
15
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
19
switch (cs->exception_index) {
16
-=========================================================================================================================================================
20
case EXCP_PREFETCH_ABORT:
17
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
21
- env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK;
18
+=========================================================================================================================================================================
22
- qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n");
19
23
+ env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
20
-These board models all use Arm M-profile CPUs.
24
+ qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n");
21
+These board models use Arm M-profile or R-profile CPUs.
25
break;
22
26
case EXCP_DATA_ABORT:
23
The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
27
env->v7m.cfsr[M_REG_NS] |=
24
bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
28
- (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
25
@@ -XXX,XX +XXX,XX @@ FPGA image.
29
+ (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
26
30
env->v7m.bfar = env->exception.vaddress;
27
QEMU models the following FPGA images:
31
qemu_log_mask(CPU_LOG_INT,
28
32
- "...with CFSR.IBUSERR and BFAR 0x%x\n",
29
+FPGA images using M-profile CPUs:
33
+ "...with CFSR.PRECISERR and BFAR 0x%x\n",
30
+
34
env->v7m.bfar);
31
``mps2-an385``
35
break;
32
Cortex-M3 as documented in Arm Application Note AN385
36
}
33
``mps2-an386``
34
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
35
``mps3-an547``
36
Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
37
38
+FPGA images using R-profile CPUs:
39
+
40
+``mps3-an536``
41
+ Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
42
+
43
Differences between QEMU and real hardware:
44
45
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
46
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
47
flash, but only as simple ROM, so attempting to rewrite the flash
48
from the guest will fail
49
- QEMU does not model the USB controller in MPS3 boards
50
+- AN536 does not support runtime control of CPU reset and halt via
51
+ the SCC CFG_REG0 register.
52
+- AN536 does not support enabling or disabling the flash and ATCM
53
+ interfaces via the SCC CFG_REG1 register.
54
+- AN536 does not support setting of the initial vector table
55
+ base address via the SCC CFG_REG6 and CFG_REG7 register config,
56
+ and does not provide a mechanism for specifying these values at
57
+ startup, so all guest images must be built to start from TCM
58
+ (i.e. to expect the interrupt vector base at 0 from reset).
59
+- AN536 defaults to only creating a single CPU; this is the equivalent
60
+ of the way the real FPGA image usually runs with the second Cortex-R52
61
+ held in halt via the initial SCC CFG_REG0 register setting. You can
62
+ create the second CPU with ``-smp 2``; both CPUs will then start
63
+ execution immediately on startup.
64
+
65
+Note that for the AN536 the first UART is accessible only by
66
+CPU0, and the second UART is accessible only by CPU1. The
67
+first UART accessible shared between both CPUs is the third
68
+UART. Guest software might therefore be built to use either
69
+the first UART or the third UART; if you don't see any output
70
+from the UART you are looking at, try one of the others.
71
+(Even if the AN536 machine is started with a single CPU and so
72
+no "CPU1-only UART", the UART numbering remains the same,
73
+with the third UART being the first of the shared ones.)
74
75
Machine-specific options
76
""""""""""""""""""""""""
37
--
77
--
38
2.7.4
78
2.34.1
39
79
40
80
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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