| 1 | ARM queue: nothing particularly exciting, but 18 patches | 1 | v2: drop pvpanic-pci patches. |
|---|---|---|---|
| 2 | is enough to send out. | ||
| 3 | 2 | ||
| 4 | thanks | 3 | The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c: |
| 5 | -- PMM | ||
| 6 | 4 | ||
| 7 | The following changes since commit 3dabde1128b671f36ac6cb36b97b273139964420: | 5 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000) |
| 8 | 6 | ||
| 9 | Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20170914' into staging (2017-09-14 16:33:02 +0100) | 7 | are available in the Git repository at: |
| 10 | 8 | ||
| 11 | are available in the git repository at: | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1 |
| 12 | 10 | ||
| 13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170914 | 11 | for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8: |
| 14 | 12 | ||
| 15 | for you to fetch changes up to ce3bc112cdb1d462e2d52eaa17a7314e7f3af504: | 13 | docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000) |
| 16 | |||
| 17 | mps2-an511: Fix wiring of UART overflow interrupt lines (2017-09-14 18:43:19 +0100) | ||
| 18 | 14 | ||
| 19 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 20 | target-arm queue: | 16 | target-arm queue: |
| 21 | * v7M: various code cleanups | 17 | * Implement IMPDEF pauth algorithm |
| 22 | * v7M: set correct BFSR bits on bus fault | 18 | * Support ARMv8.4-SEL2 |
| 23 | * v7M: clear exclusive monitor on reset and exception entry/exit | 19 | * Fix bug where we were truncating predicate vector lengths in SVE insns |
| 24 | * v7M: don't apply priority mask to negative priorities | 20 | * npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 25 | * zcu102: support 'secure' and 'virtualization' machine properties | 21 | * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 26 | * aarch64: fix ERET single stepping | 22 | * docs: Build and install all the docs in a single manual |
| 27 | * gpex: implement PCI INTx routing | ||
| 28 | * mps2-an511: fix UART overflow interrupt line wiring | ||
| 29 | 23 | ||
| 30 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 31 | Alistair Francis (5): | 25 | Gan Qixin (1): |
| 32 | xlnx-ep108: Rename to ZCU102 | 26 | npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 33 | xlnx-zcu102: Manually create the machines | ||
| 34 | xlnx-zcu102: Add a machine level secure property | ||
| 35 | xlnx-zcu102: Add a machine level virtualization property | ||
| 36 | xlnx-zcu102: Mark the EP108 machine as deprecated | ||
| 37 | 27 | ||
| 38 | Jaroslaw Pelczar (1): | 28 | Peter Maydell (1): |
| 39 | AArch64: Fix single stepping of ERET instruction | 29 | docs: Build and install all the docs in a single manual |
| 40 | 30 | ||
| 41 | Peter Maydell (8): | 31 | Philippe Mathieu-Daudé (1): |
| 42 | target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 | 32 | target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 43 | target/arm: Clear exclusive monitor on v7M reset, exception entry/exit | ||
| 44 | target/arm: Get PRECISERR and IBUSERR the right way round | ||
| 45 | nvic: Don't apply group priority mask to negative priorities | ||
| 46 | target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() | ||
| 47 | target/arm: Add and use defines for EXCRET constants | ||
| 48 | target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() | ||
| 49 | mps2-an511: Fix wiring of UART overflow interrupt lines | ||
| 50 | 33 | ||
| 51 | Pranavkumar Sawargaonkar (3): | 34 | Richard Henderson (7): |
| 52 | hw/pci-host/gpex: Set INTx index/gsi mapping | 35 | target/arm: Implement an IMPDEF pauth algorithm |
| 53 | hw/arm/virt: Set INTx/gsi mapping | 36 | target/arm: Add cpu properties to control pauth |
| 54 | hw/pci-host/gpex: Implement PCI INTx routing | 37 | target/arm: Use object_property_add_bool for "sve" property |
| 38 | target/arm: Introduce PREDDESC field definitions | ||
| 39 | target/arm: Update PFIRST, PNEXT for pred_desc | ||
| 40 | target/arm: Update ZIP, UZP, TRN for pred_desc | ||
| 41 | target/arm: Update REV, PUNPK for pred_desc | ||
| 55 | 42 | ||
| 56 | Richard Henderson (1): | 43 | Rémi Denis-Courmont (19): |
| 57 | target/arm: Avoid an extra temporary for store_exclusive | 44 | target/arm: remove redundant tests |
| 45 | target/arm: add arm_is_el2_enabled() helper | ||
| 46 | target/arm: use arm_is_el2_enabled() where applicable | ||
| 47 | target/arm: use arm_hcr_el2_eff() where applicable | ||
| 48 | target/arm: factor MDCR_EL2 common handling | ||
| 49 | target/arm: Define isar_feature function to test for presence of SEL2 | ||
| 50 | target/arm: add 64-bit S-EL2 to EL exception table | ||
| 51 | target/arm: add MMU stage 1 for Secure EL2 | ||
| 52 | target/arm: add ARMv8.4-SEL2 system registers | ||
| 53 | target/arm: handle VMID change in secure state | ||
| 54 | target/arm: do S1_ptw_translate() before address space lookup | ||
| 55 | target/arm: translate NS bit in page-walks | ||
| 56 | target/arm: generalize 2-stage page-walk condition | ||
| 57 | target/arm: secure stage 2 translation regime | ||
| 58 | target/arm: set HPFAR_EL2.NS on secure stage 2 faults | ||
| 59 | target/arm: revector to run-time pick target EL | ||
| 60 | target/arm: Implement SCR_EL2.EEL2 | ||
| 61 | target/arm: enable Secure EL2 in max CPU | ||
| 62 | target/arm: refactor vae1_tlbmask() | ||
| 58 | 63 | ||
| 59 | hw/arm/Makefile.objs | 2 +- | 64 | docs/conf.py | 46 ++++- |
| 60 | include/hw/arm/xlnx-zynqmp.h | 2 + | 65 | docs/devel/conf.py | 15 -- |
| 61 | include/hw/pci-host/gpex.h | 3 + | 66 | docs/index.html.in | 17 -- |
| 62 | target/arm/cpu.h | 35 +++--- | 67 | docs/interop/conf.py | 28 --- |
| 63 | target/arm/internals.h | 20 ++++ | 68 | docs/meson.build | 64 +++--- |
| 64 | hw/arm/mps2.c | 4 +- | 69 | docs/specs/conf.py | 16 -- |
| 65 | hw/arm/virt.c | 1 + | 70 | docs/system/arm/cpu-features.rst | 21 ++ |
| 66 | hw/arm/xlnx-ep108.c | 139 ----------------------- | 71 | docs/system/conf.py | 28 --- |
| 67 | hw/arm/xlnx-zcu102.c | 259 +++++++++++++++++++++++++++++++++++++++++++ | 72 | docs/tools/conf.py | 37 ---- |
| 68 | hw/arm/xlnx-zynqmp.c | 3 +- | 73 | docs/user/conf.py | 15 -- |
| 69 | hw/intc/armv7m_nvic.c | 11 +- | 74 | include/qemu/xxhash.h | 98 +++++++++ |
| 70 | hw/pci-host/gpex.c | 22 ++++ | 75 | target/arm/cpu-param.h | 2 +- |
| 71 | target/arm/cpu.c | 6 + | 76 | target/arm/cpu.h | 107 ++++++++-- |
| 72 | target/arm/helper.c | 43 ++++--- | 77 | target/arm/internals.h | 45 +++++ |
| 73 | target/arm/op_helper.c | 2 +- | 78 | target/arm/cpu.c | 23 ++- |
| 74 | target/arm/translate-a64.c | 27 ++--- | 79 | target/arm/cpu64.c | 65 ++++-- |
| 75 | 16 files changed, 382 insertions(+), 197 deletions(-) | 80 | target/arm/helper-a64.c | 8 +- |
| 76 | delete mode 100644 hw/arm/xlnx-ep108.c | 81 | target/arm/helper.c | 414 ++++++++++++++++++++++++++------------- |
| 77 | create mode 100644 hw/arm/xlnx-zcu102.c | 82 | target/arm/m_helper.c | 2 +- |
| 83 | target/arm/monitor.c | 1 + | ||
| 84 | target/arm/op_helper.c | 4 +- | ||
| 85 | target/arm/pauth_helper.c | 27 ++- | ||
| 86 | target/arm/sve_helper.c | 33 ++-- | ||
| 87 | target/arm/tlb_helper.c | 3 + | ||
| 88 | target/arm/translate-a64.c | 4 + | ||
| 89 | target/arm/translate-sve.c | 31 ++- | ||
| 90 | target/arm/translate.c | 36 +++- | ||
| 91 | tests/qtest/arm-cpu-features.c | 13 ++ | ||
| 92 | tests/qtest/npcm7xx_adc-test.c | 1 + | ||
| 93 | .gitlab-ci.yml | 4 +- | ||
| 94 | 30 files changed, 770 insertions(+), 438 deletions(-) | ||
| 95 | delete mode 100644 docs/devel/conf.py | ||
| 96 | delete mode 100644 docs/index.html.in | ||
| 97 | delete mode 100644 docs/interop/conf.py | ||
| 98 | delete mode 100644 docs/specs/conf.py | ||
| 99 | delete mode 100644 docs/system/conf.py | ||
| 100 | delete mode 100644 docs/tools/conf.py | ||
| 101 | delete mode 100644 docs/user/conf.py | ||
| 78 | 102 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Use a symbolic constant M_REG_NUM_BANKS for the array size for | ||
| 2 | registers which are banked by M profile security state, rather | ||
| 3 | than hardcoding lots of 2s. | ||
| 4 | 1 | ||
| 5 | Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 9 | Message-id: 1505137930-13255-2-git-send-email-peter.maydell@linaro.org | ||
| 10 | --- | ||
| 11 | target/arm/cpu.h | 35 +++++++++++++++++++---------------- | ||
| 12 | 1 file changed, 19 insertions(+), 16 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/cpu.h | ||
| 17 | +++ b/target/arm/cpu.h | ||
| 18 | @@ -XXX,XX +XXX,XX @@ | ||
| 19 | * accessed via env->registerfield[env->v7m.secure] (whether the security | ||
| 20 | * extension is implemented or not). | ||
| 21 | */ | ||
| 22 | -#define M_REG_NS 0 | ||
| 23 | -#define M_REG_S 1 | ||
| 24 | +enum { | ||
| 25 | + M_REG_NS = 0, | ||
| 26 | + M_REG_S = 1, | ||
| 27 | + M_REG_NUM_BANKS = 2, | ||
| 28 | +}; | ||
| 29 | |||
| 30 | /* ARM-specific interrupt pending bits. */ | ||
| 31 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | ||
| 32 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
| 33 | uint32_t other_sp; | ||
| 34 | uint32_t other_ss_msp; | ||
| 35 | uint32_t other_ss_psp; | ||
| 36 | - uint32_t vecbase[2]; | ||
| 37 | - uint32_t basepri[2]; | ||
| 38 | - uint32_t control[2]; | ||
| 39 | - uint32_t ccr[2]; /* Configuration and Control */ | ||
| 40 | - uint32_t cfsr[2]; /* Configurable Fault Status */ | ||
| 41 | + uint32_t vecbase[M_REG_NUM_BANKS]; | ||
| 42 | + uint32_t basepri[M_REG_NUM_BANKS]; | ||
| 43 | + uint32_t control[M_REG_NUM_BANKS]; | ||
| 44 | + uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ | ||
| 45 | + uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ | ||
| 46 | uint32_t hfsr; /* HardFault Status */ | ||
| 47 | uint32_t dfsr; /* Debug Fault Status Register */ | ||
| 48 | - uint32_t mmfar[2]; /* MemManage Fault Address */ | ||
| 49 | + uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ | ||
| 50 | uint32_t bfar; /* BusFault Address */ | ||
| 51 | - unsigned mpu_ctrl[2]; /* MPU_CTRL */ | ||
| 52 | + unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ | ||
| 53 | int exception; | ||
| 54 | - uint32_t primask[2]; | ||
| 55 | - uint32_t faultmask[2]; | ||
| 56 | + uint32_t primask[M_REG_NUM_BANKS]; | ||
| 57 | + uint32_t faultmask[M_REG_NUM_BANKS]; | ||
| 58 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | ||
| 59 | } v7m; | ||
| 60 | |||
| 61 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
| 62 | uint32_t *drbar; | ||
| 63 | uint32_t *drsr; | ||
| 64 | uint32_t *dracr; | ||
| 65 | - uint32_t rnr[2]; | ||
| 66 | + uint32_t rnr[M_REG_NUM_BANKS]; | ||
| 67 | } pmsav7; | ||
| 68 | |||
| 69 | /* PMSAv8 MPU */ | ||
| 70 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
| 71 | * pmsav7.rnr (region number register) | ||
| 72 | * pmsav7_dregion (number of configured regions) | ||
| 73 | */ | ||
| 74 | - uint32_t *rbar[2]; | ||
| 75 | - uint32_t *rlar[2]; | ||
| 76 | - uint32_t mair0[2]; | ||
| 77 | - uint32_t mair1[2]; | ||
| 78 | + uint32_t *rbar[M_REG_NUM_BANKS]; | ||
| 79 | + uint32_t *rlar[M_REG_NUM_BANKS]; | ||
| 80 | + uint32_t mair0[M_REG_NUM_BANKS]; | ||
| 81 | + uint32_t mair1[M_REG_NUM_BANKS]; | ||
| 82 | } pmsav8; | ||
| 83 | |||
| 84 | void *nvic; | ||
| 85 | -- | ||
| 86 | 2.7.4 | ||
| 87 | |||
| 88 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | For M profile we must clear the exclusive monitor on reset, exception | ||
| 2 | entry and exception exit. We weren't doing any of these things; fix | ||
| 3 | this bug. | ||
| 4 | 1 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 1505137930-13255-3-git-send-email-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/internals.h | 10 ++++++++++ | ||
| 11 | target/arm/cpu.c | 6 ++++++ | ||
| 12 | target/arm/helper.c | 2 ++ | ||
| 13 | target/arm/op_helper.c | 2 +- | ||
| 14 | 4 files changed, 19 insertions(+), 1 deletion(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/internals.h | ||
| 19 | +++ b/target/arm/internals.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu); | ||
| 21 | #endif | ||
| 22 | |||
| 23 | /** | ||
| 24 | + * arm_clear_exclusive: clear the exclusive monitor | ||
| 25 | + * @env: CPU env | ||
| 26 | + * Clear the CPU's exclusive monitor, like the guest CLREX instruction. | ||
| 27 | + */ | ||
| 28 | +static inline void arm_clear_exclusive(CPUARMState *env) | ||
| 29 | +{ | ||
| 30 | + env->exclusive_addr = -1; | ||
| 31 | +} | ||
| 32 | + | ||
| 33 | +/** | ||
| 34 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault | ||
| 35 | * @s2addr: Address that caused a fault at stage 2 | ||
| 36 | * @stage2: True if we faulted at stage 2 | ||
| 37 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 38 | index XXXXXXX..XXXXXXX 100644 | ||
| 39 | --- a/target/arm/cpu.c | ||
| 40 | +++ b/target/arm/cpu.c | ||
| 41 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
| 42 | env->regs[15] = 0xFFFF0000; | ||
| 43 | } | ||
| 44 | |||
| 45 | + /* M profile requires that reset clears the exclusive monitor; | ||
| 46 | + * A profile does not, but clearing it makes more sense than having it | ||
| 47 | + * set with an exclusive access on address zero. | ||
| 48 | + */ | ||
| 49 | + arm_clear_exclusive(env); | ||
| 50 | + | ||
| 51 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | ||
| 52 | #endif | ||
| 53 | |||
| 54 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 55 | index XXXXXXX..XXXXXXX 100644 | ||
| 56 | --- a/target/arm/helper.c | ||
| 57 | +++ b/target/arm/helper.c | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) | ||
| 59 | |||
| 60 | armv7m_nvic_acknowledge_irq(env->nvic); | ||
| 61 | switch_v7m_sp(env, 0); | ||
| 62 | + arm_clear_exclusive(env); | ||
| 63 | /* Clear IT bits */ | ||
| 64 | env->condexec_bits = 0; | ||
| 65 | env->regs[14] = lr; | ||
| 66 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 67 | } | ||
| 68 | |||
| 69 | /* Otherwise, we have a successful exception exit. */ | ||
| 70 | + arm_clear_exclusive(env); | ||
| 71 | qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); | ||
| 72 | } | ||
| 73 | |||
| 74 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
| 75 | index XXXXXXX..XXXXXXX 100644 | ||
| 76 | --- a/target/arm/op_helper.c | ||
| 77 | +++ b/target/arm/op_helper.c | ||
| 78 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env) | ||
| 79 | |||
| 80 | aarch64_save_sp(env, cur_el); | ||
| 81 | |||
| 82 | - env->exclusive_addr = -1; | ||
| 83 | + arm_clear_exclusive(env); | ||
| 84 | |||
| 85 | /* We must squash the PSTATE.SS bit to zero unless both of the | ||
| 86 | * following hold: | ||
| 87 | -- | ||
| 88 | 2.7.4 | ||
| 89 | |||
| 90 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | For a bus fault, the M profile BFSR bit PRECISERR means a bus | ||
| 2 | fault on a data access, and IBUSERR means a bus fault on an | ||
| 3 | instruction access. We had these the wrong way around; fix this. | ||
| 4 | 1 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 1505137930-13255-4-git-send-email-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/helper.c | 8 ++++---- | ||
| 11 | 1 file changed, 4 insertions(+), 4 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/helper.c | ||
| 16 | +++ b/target/arm/helper.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
| 18 | case 0x8: /* External Abort */ | ||
| 19 | switch (cs->exception_index) { | ||
| 20 | case EXCP_PREFETCH_ABORT: | ||
| 21 | - env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK; | ||
| 22 | - qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); | ||
| 23 | + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; | ||
| 24 | + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); | ||
| 25 | break; | ||
| 26 | case EXCP_DATA_ABORT: | ||
| 27 | env->v7m.cfsr[M_REG_NS] |= | ||
| 28 | - (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); | ||
| 29 | + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); | ||
| 30 | env->v7m.bfar = env->exception.vaddress; | ||
| 31 | qemu_log_mask(CPU_LOG_INT, | ||
| 32 | - "...with CFSR.IBUSERR and BFAR 0x%x\n", | ||
| 33 | + "...with CFSR.PRECISERR and BFAR 0x%x\n", | ||
| 34 | env->v7m.bfar); | ||
| 35 | break; | ||
| 36 | } | ||
| 37 | -- | ||
| 38 | 2.7.4 | ||
| 39 | |||
| 40 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In several places we were unconditionally applying the | ||
| 2 | nvic_gprio_mask() to a priority value. This is incorrect | ||
| 3 | if the priority is one of the fixed negative priority | ||
| 4 | values (for NMI and HardFault), so don't do it. | ||
| 5 | 1 | ||
| 6 | This bug would have caused both NMI and HardFault to be | ||
| 7 | considered as the same priority and so NMI wouldn't | ||
| 8 | correctly preempt HardFault. | ||
| 9 | |||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 1505137930-13255-5-git-send-email-peter.maydell@linaro.org | ||
| 13 | --- | ||
| 14 | hw/intc/armv7m_nvic.c | 11 +++++++++-- | ||
| 15 | 1 file changed, 9 insertions(+), 2 deletions(-) | ||
| 16 | |||
| 17 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/hw/intc/armv7m_nvic.c | ||
| 20 | +++ b/hw/intc/armv7m_nvic.c | ||
| 21 | @@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s) | ||
| 22 | } | ||
| 23 | } | ||
| 24 | |||
| 25 | + if (active_prio > 0) { | ||
| 26 | + active_prio &= nvic_gprio_mask(s); | ||
| 27 | + } | ||
| 28 | + | ||
| 29 | s->vectpending = pend_irq; | ||
| 30 | - s->exception_prio = active_prio & nvic_gprio_mask(s); | ||
| 31 | + s->exception_prio = active_prio; | ||
| 32 | |||
| 33 | trace_nvic_recompute_state(s->vectpending, s->exception_prio); | ||
| 34 | } | ||
| 35 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque) | ||
| 36 | assert(vec->enabled); | ||
| 37 | assert(vec->pending); | ||
| 38 | |||
| 39 | - pendgroupprio = vec->prio & nvic_gprio_mask(s); | ||
| 40 | + pendgroupprio = vec->prio; | ||
| 41 | + if (pendgroupprio > 0) { | ||
| 42 | + pendgroupprio &= nvic_gprio_mask(s); | ||
| 43 | + } | ||
| 44 | assert(pendgroupprio < running); | ||
| 45 | |||
| 46 | trace_nvic_acknowledge_irq(pending, vec->prio); | ||
| 47 | -- | ||
| 48 | 2.7.4 | ||
| 49 | |||
| 50 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In do_v7m_exception_exit(), there's no need to force the high 4 | ||
| 2 | bits of 'type' to 1 when calling v7m_exception_taken(), because | ||
| 3 | we know that they're always 1 or we could not have got to this | ||
| 4 | "handle return to magic exception return address" code. Remove | ||
| 5 | the unnecessary ORs. | ||
| 6 | 1 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Acked-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 10 | Message-id: 1505137930-13255-6-git-send-email-peter.maydell@linaro.org | ||
| 11 | --- | ||
| 12 | target/arm/helper.c | 4 ++-- | ||
| 13 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/helper.c | ||
| 18 | +++ b/target/arm/helper.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 20 | */ | ||
| 21 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | ||
| 22 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
| 23 | - v7m_exception_taken(cpu, type | 0xf0000000); | ||
| 24 | + v7m_exception_taken(cpu, type); | ||
| 25 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | ||
| 26 | "stackframe: failed exception return integrity check\n"); | ||
| 27 | return; | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 29 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
| 30 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | ||
| 31 | v7m_push_stack(cpu); | ||
| 32 | - v7m_exception_taken(cpu, type | 0xf0000000); | ||
| 33 | + v7m_exception_taken(cpu, type); | ||
| 34 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " | ||
| 35 | "failed exception return integrity check\n"); | ||
| 36 | return; | ||
| 37 | -- | ||
| 38 | 2.7.4 | ||
| 39 | |||
| 40 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The exception-return magic values get some new bits in v8M, which | ||
| 2 | makes some bit definitions for them worthwhile. | ||
| 3 | 1 | ||
| 4 | We don't use the bit definitions for the switch on the low bits | ||
| 5 | which checks the return type for v7M, because this is defined | ||
| 6 | in the v7M ARM ARM as a set of valid values rather than via | ||
| 7 | per-bit checks. | ||
| 8 | |||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 11 | Message-id: 1505137930-13255-7-git-send-email-peter.maydell@linaro.org | ||
| 12 | --- | ||
| 13 | target/arm/internals.h | 10 ++++++++++ | ||
| 14 | target/arm/helper.c | 14 +++++++++----- | ||
| 15 | 2 files changed, 19 insertions(+), 5 deletions(-) | ||
| 16 | |||
| 17 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/target/arm/internals.h | ||
| 20 | +++ b/target/arm/internals.h | ||
| 21 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_CONTROL, NPRIV, 0, 1) | ||
| 22 | FIELD(V7M_CONTROL, SPSEL, 1, 1) | ||
| 23 | FIELD(V7M_CONTROL, FPCA, 2, 1) | ||
| 24 | |||
| 25 | +/* Bit definitions for v7M exception return payload */ | ||
| 26 | +FIELD(V7M_EXCRET, ES, 0, 1) | ||
| 27 | +FIELD(V7M_EXCRET, RES0, 1, 1) | ||
| 28 | +FIELD(V7M_EXCRET, SPSEL, 2, 1) | ||
| 29 | +FIELD(V7M_EXCRET, MODE, 3, 1) | ||
| 30 | +FIELD(V7M_EXCRET, FTYPE, 4, 1) | ||
| 31 | +FIELD(V7M_EXCRET, DCRS, 5, 1) | ||
| 32 | +FIELD(V7M_EXCRET, S, 6, 1) | ||
| 33 | +FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ | ||
| 34 | + | ||
| 35 | /* | ||
| 36 | * For AArch64, map a given EL to an index in the banked_spsr array. | ||
| 37 | * Note that this mapping and the AArch32 mapping defined in bank_number() | ||
| 38 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/target/arm/helper.c | ||
| 41 | +++ b/target/arm/helper.c | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 43 | " previous exception %d\n", | ||
| 44 | type, env->v7m.exception); | ||
| 45 | |||
| 46 | - if (extract32(type, 5, 23) != extract32(-1, 5, 23)) { | ||
| 47 | + if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { | ||
| 48 | qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " | ||
| 49 | "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); | ||
| 50 | } | ||
| 51 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 52 | * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) | ||
| 53 | */ | ||
| 54 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
| 55 | - int es = type & 1; | ||
| 56 | + int es = type & R_V7M_EXCRET_ES_MASK; | ||
| 57 | if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { | ||
| 58 | env->v7m.faultmask[es] = 0; | ||
| 59 | } | ||
| 60 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
| 61 | return; /* Never happens. Keep compiler happy. */ | ||
| 62 | } | ||
| 63 | |||
| 64 | - lr = 0xfffffff1; | ||
| 65 | + lr = R_V7M_EXCRET_RES1_MASK | | ||
| 66 | + R_V7M_EXCRET_S_MASK | | ||
| 67 | + R_V7M_EXCRET_DCRS_MASK | | ||
| 68 | + R_V7M_EXCRET_FTYPE_MASK | | ||
| 69 | + R_V7M_EXCRET_ES_MASK; | ||
| 70 | if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { | ||
| 71 | - lr |= 4; | ||
| 72 | + lr |= R_V7M_EXCRET_SPSEL_MASK; | ||
| 73 | } | ||
| 74 | if (!arm_v7m_is_handler_mode(env)) { | ||
| 75 | - lr |= 8; | ||
| 76 | + lr |= R_V7M_EXCRET_MODE_MASK; | ||
| 77 | } | ||
| 78 | |||
| 79 | v7m_push_stack(cpu); | ||
| 80 | -- | ||
| 81 | 2.7.4 | ||
| 82 | |||
| 83 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In the v7M and v8M ARM ARM, the magic exception return values are | ||
| 2 | referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_* | ||
| 3 | constants to define bits within them. Rename the 'type' variable | ||
| 4 | which holds the exception return value in do_v7m_exception_exit() | ||
| 5 | to excret, making it clearer that it does hold an EXC_RETURN value. | ||
| 6 | 1 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 11 | Message-id: 1505137930-13255-8-git-send-email-peter.maydell@linaro.org | ||
| 12 | --- | ||
| 13 | target/arm/helper.c | 23 ++++++++++++----------- | ||
| 14 | 1 file changed, 12 insertions(+), 11 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/helper.c | ||
| 19 | +++ b/target/arm/helper.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static void v7m_push_stack(ARMCPU *cpu) | ||
| 21 | static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 22 | { | ||
| 23 | CPUARMState *env = &cpu->env; | ||
| 24 | - uint32_t type; | ||
| 25 | + uint32_t excret; | ||
| 26 | uint32_t xpsr; | ||
| 27 | bool ufault = false; | ||
| 28 | bool return_to_sp_process = false; | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 30 | * the target value up between env->regs[15] and env->thumb in | ||
| 31 | * gen_bx(). Reconstitute it. | ||
| 32 | */ | ||
| 33 | - type = env->regs[15]; | ||
| 34 | + excret = env->regs[15]; | ||
| 35 | if (env->thumb) { | ||
| 36 | - type |= 1; | ||
| 37 | + excret |= 1; | ||
| 38 | } | ||
| 39 | |||
| 40 | qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 | ||
| 41 | " previous exception %d\n", | ||
| 42 | - type, env->v7m.exception); | ||
| 43 | + excret, env->v7m.exception); | ||
| 44 | |||
| 45 | - if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { | ||
| 46 | + if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { | ||
| 47 | qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " | ||
| 48 | - "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); | ||
| 49 | + "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", | ||
| 50 | + excret); | ||
| 51 | } | ||
| 52 | |||
| 53 | if (env->v7m.exception != ARMV7M_EXCP_NMI) { | ||
| 54 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 55 | * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) | ||
| 56 | */ | ||
| 57 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
| 58 | - int es = type & R_V7M_EXCRET_ES_MASK; | ||
| 59 | + int es = excret & R_V7M_EXCRET_ES_MASK; | ||
| 60 | if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { | ||
| 61 | env->v7m.faultmask[es] = 0; | ||
| 62 | } | ||
| 63 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 64 | g_assert_not_reached(); | ||
| 65 | } | ||
| 66 | |||
| 67 | - switch (type & 0xf) { | ||
| 68 | + switch (excret & 0xf) { | ||
| 69 | case 1: /* Return to Handler */ | ||
| 70 | return_to_handler = true; | ||
| 71 | break; | ||
| 72 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 73 | */ | ||
| 74 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | ||
| 75 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
| 76 | - v7m_exception_taken(cpu, type); | ||
| 77 | + v7m_exception_taken(cpu, excret); | ||
| 78 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | ||
| 79 | "stackframe: failed exception return integrity check\n"); | ||
| 80 | return; | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
| 82 | |||
| 83 | /* The restored xPSR exception field will be zero if we're | ||
| 84 | * resuming in Thread mode. If that doesn't match what the | ||
| 85 | - * exception return type specified then this is a UsageFault. | ||
| 86 | + * exception return excret specified then this is a UsageFault. | ||
| 87 | */ | ||
| 88 | if (return_to_handler != arm_v7m_is_handler_mode(env)) { | ||
| 89 | /* Take an INVPC UsageFault by pushing the stack again. */ | ||
| 90 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
| 91 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | ||
| 92 | v7m_push_stack(cpu); | ||
| 93 | - v7m_exception_taken(cpu, type); | ||
| 94 | + v7m_exception_taken(cpu, excret); | ||
| 95 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " | ||
| 96 | "failed exception return integrity check\n"); | ||
| 97 | return; | ||
| 98 | -- | ||
| 99 | 2.7.4 | ||
| 100 | |||
| 101 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
| 2 | 1 | ||
| 3 | The EP108 is a early access development board. Now that silicon is in | ||
| 4 | production people have access to the ZCU102. Let's rename the internal | ||
| 5 | QEMU files and variables to use the ZCU102. | ||
| 6 | |||
| 7 | There is no functional change here as the EP108 is still a valid board | ||
| 8 | option. | ||
| 9 | |||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 11 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | --- | ||
| 14 | hw/arm/Makefile.objs | 2 +- | ||
| 15 | hw/arm/{xlnx-ep108.c => xlnx-zcu102.c} | 30 +++++++++++++++--------------- | ||
| 16 | 2 files changed, 16 insertions(+), 16 deletions(-) | ||
| 17 | rename hw/arm/{xlnx-ep108.c => xlnx-zcu102.c} (85%) | ||
| 18 | |||
| 19 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/hw/arm/Makefile.objs | ||
| 22 | +++ b/hw/arm/Makefile.objs | ||
| 23 | @@ -XXX,XX +XXX,XX @@ obj-y += omap1.o omap2.o strongarm.o | ||
| 24 | obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o | ||
| 25 | obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o | ||
| 26 | obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o | ||
| 27 | -obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o | ||
| 28 | +obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-zcu102.o | ||
| 29 | obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o | ||
| 30 | obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o | ||
| 31 | obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o | ||
| 32 | diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-zcu102.c | ||
| 33 | similarity index 85% | ||
| 34 | rename from hw/arm/xlnx-ep108.c | ||
| 35 | rename to hw/arm/xlnx-zcu102.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/hw/arm/xlnx-ep108.c | ||
| 38 | +++ b/hw/arm/xlnx-zcu102.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ | ||
| 40 | /* | ||
| 41 | - * Xilinx ZynqMP EP108 board | ||
| 42 | + * Xilinx ZynqMP ZCU102 board | ||
| 43 | * | ||
| 44 | * Copyright (C) 2015 Xilinx Inc | ||
| 45 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> | ||
| 46 | @@ -XXX,XX +XXX,XX @@ | ||
| 47 | #include "exec/address-spaces.h" | ||
| 48 | #include "qemu/log.h" | ||
| 49 | |||
| 50 | -typedef struct XlnxEP108 { | ||
| 51 | +typedef struct XlnxZCU102 { | ||
| 52 | XlnxZynqMPState soc; | ||
| 53 | MemoryRegion ddr_ram; | ||
| 54 | -} XlnxEP108; | ||
| 55 | +} XlnxZCU102; | ||
| 56 | |||
| 57 | -static struct arm_boot_info xlnx_ep108_binfo; | ||
| 58 | +static struct arm_boot_info xlnx_zcu102_binfo; | ||
| 59 | |||
| 60 | -static void xlnx_ep108_init(MachineState *machine) | ||
| 61 | +static void xlnx_zcu102_init(MachineState *machine) | ||
| 62 | { | ||
| 63 | - XlnxEP108 *s = g_new0(XlnxEP108, 1); | ||
| 64 | + XlnxZCU102 *s = g_new0(XlnxZCU102, 1); | ||
| 65 | int i; | ||
| 66 | uint64_t ram_size = machine->ram_size; | ||
| 67 | |||
| 68 | @@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine) | ||
| 69 | } | ||
| 70 | |||
| 71 | if (ram_size < 0x08000000) { | ||
| 72 | - qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for EP108", | ||
| 73 | + qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102", | ||
| 74 | ram_size); | ||
| 75 | } | ||
| 76 | |||
| 77 | @@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine) | ||
| 78 | |||
| 79 | /* TODO create and connect IDE devices for ide_drive_get() */ | ||
| 80 | |||
| 81 | - xlnx_ep108_binfo.ram_size = ram_size; | ||
| 82 | - xlnx_ep108_binfo.kernel_filename = machine->kernel_filename; | ||
| 83 | - xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline; | ||
| 84 | - xlnx_ep108_binfo.initrd_filename = machine->initrd_filename; | ||
| 85 | - xlnx_ep108_binfo.loader_start = 0; | ||
| 86 | - arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_ep108_binfo); | ||
| 87 | + xlnx_zcu102_binfo.ram_size = ram_size; | ||
| 88 | + xlnx_zcu102_binfo.kernel_filename = machine->kernel_filename; | ||
| 89 | + xlnx_zcu102_binfo.kernel_cmdline = machine->kernel_cmdline; | ||
| 90 | + xlnx_zcu102_binfo.initrd_filename = machine->initrd_filename; | ||
| 91 | + xlnx_zcu102_binfo.loader_start = 0; | ||
| 92 | + arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); | ||
| 93 | } | ||
| 94 | |||
| 95 | static void xlnx_ep108_machine_init(MachineClass *mc) | ||
| 96 | { | ||
| 97 | mc->desc = "Xilinx ZynqMP EP108 board"; | ||
| 98 | - mc->init = xlnx_ep108_init; | ||
| 99 | + mc->init = xlnx_zcu102_init; | ||
| 100 | mc->block_default_type = IF_IDE; | ||
| 101 | mc->units_per_default_bus = 1; | ||
| 102 | mc->ignore_memory_transaction_failures = true; | ||
| 103 | @@ -XXX,XX +XXX,XX @@ DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) | ||
| 104 | static void xlnx_zcu102_machine_init(MachineClass *mc) | ||
| 105 | { | ||
| 106 | mc->desc = "Xilinx ZynqMP ZCU102 board"; | ||
| 107 | - mc->init = xlnx_ep108_init; | ||
| 108 | + mc->init = xlnx_zcu102_init; | ||
| 109 | mc->block_default_type = IF_IDE; | ||
| 110 | mc->units_per_default_bus = 1; | ||
| 111 | mc->ignore_memory_transaction_failures = true; | ||
| 112 | -- | ||
| 113 | 2.7.4 | ||
| 114 | |||
| 115 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
| 2 | 1 | ||
| 3 | In preperation for future work let's manually create the Xilnx machines. | ||
| 4 | This will allow us to set properties for the machines in the future. | ||
| 5 | |||
| 6 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 7 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | hw/arm/xlnx-zcu102.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++----- | ||
| 11 | 1 file changed, 67 insertions(+), 7 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/hw/arm/xlnx-zcu102.c | ||
| 16 | +++ b/hw/arm/xlnx-zcu102.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ | ||
| 18 | #include "qemu/log.h" | ||
| 19 | |||
| 20 | typedef struct XlnxZCU102 { | ||
| 21 | + MachineState parent_obj; | ||
| 22 | + | ||
| 23 | XlnxZynqMPState soc; | ||
| 24 | MemoryRegion ddr_ram; | ||
| 25 | } XlnxZCU102; | ||
| 26 | |||
| 27 | +#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") | ||
| 28 | +#define ZCU102_MACHINE(obj) \ | ||
| 29 | + OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE) | ||
| 30 | + | ||
| 31 | +#define TYPE_EP108_MACHINE MACHINE_TYPE_NAME("xlnx-ep108") | ||
| 32 | +#define EP108_MACHINE(obj) \ | ||
| 33 | + OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE) | ||
| 34 | + | ||
| 35 | static struct arm_boot_info xlnx_zcu102_binfo; | ||
| 36 | |||
| 37 | -static void xlnx_zcu102_init(MachineState *machine) | ||
| 38 | +static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) | ||
| 39 | { | ||
| 40 | - XlnxZCU102 *s = g_new0(XlnxZCU102, 1); | ||
| 41 | int i; | ||
| 42 | uint64_t ram_size = machine->ram_size; | ||
| 43 | |||
| 44 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine) | ||
| 45 | arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); | ||
| 46 | } | ||
| 47 | |||
| 48 | -static void xlnx_ep108_machine_init(MachineClass *mc) | ||
| 49 | +static void xlnx_ep108_init(MachineState *machine) | ||
| 50 | +{ | ||
| 51 | + XlnxZCU102 *s = EP108_MACHINE(machine); | ||
| 52 | + | ||
| 53 | + xlnx_zynqmp_init(s, machine); | ||
| 54 | +} | ||
| 55 | + | ||
| 56 | +static void xlnx_ep108_machine_instance_init(Object *obj) | ||
| 57 | { | ||
| 58 | +} | ||
| 59 | + | ||
| 60 | +static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) | ||
| 61 | +{ | ||
| 62 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
| 63 | + | ||
| 64 | mc->desc = "Xilinx ZynqMP EP108 board"; | ||
| 65 | - mc->init = xlnx_zcu102_init; | ||
| 66 | + mc->init = xlnx_ep108_init; | ||
| 67 | mc->block_default_type = IF_IDE; | ||
| 68 | mc->units_per_default_bus = 1; | ||
| 69 | mc->ignore_memory_transaction_failures = true; | ||
| 70 | } | ||
| 71 | |||
| 72 | -DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) | ||
| 73 | +static const TypeInfo xlnx_ep108_machine_init_typeinfo = { | ||
| 74 | + .name = MACHINE_TYPE_NAME("xlnx-ep108"), | ||
| 75 | + .parent = TYPE_MACHINE, | ||
| 76 | + .class_init = xlnx_ep108_machine_class_init, | ||
| 77 | + .instance_init = xlnx_ep108_machine_instance_init, | ||
| 78 | + .instance_size = sizeof(XlnxZCU102), | ||
| 79 | +}; | ||
| 80 | |||
| 81 | -static void xlnx_zcu102_machine_init(MachineClass *mc) | ||
| 82 | +static void xlnx_ep108_machine_init_register_types(void) | ||
| 83 | { | ||
| 84 | + type_register_static(&xlnx_ep108_machine_init_typeinfo); | ||
| 85 | +} | ||
| 86 | + | ||
| 87 | +static void xlnx_zcu102_init(MachineState *machine) | ||
| 88 | +{ | ||
| 89 | + XlnxZCU102 *s = ZCU102_MACHINE(machine); | ||
| 90 | + | ||
| 91 | + xlnx_zynqmp_init(s, machine); | ||
| 92 | +} | ||
| 93 | + | ||
| 94 | +static void xlnx_zcu102_machine_instance_init(Object *obj) | ||
| 95 | +{ | ||
| 96 | +} | ||
| 97 | + | ||
| 98 | +static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) | ||
| 99 | +{ | ||
| 100 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
| 101 | + | ||
| 102 | mc->desc = "Xilinx ZynqMP ZCU102 board"; | ||
| 103 | mc->init = xlnx_zcu102_init; | ||
| 104 | mc->block_default_type = IF_IDE; | ||
| 105 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_init(MachineClass *mc) | ||
| 106 | mc->ignore_memory_transaction_failures = true; | ||
| 107 | } | ||
| 108 | |||
| 109 | -DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) | ||
| 110 | +static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { | ||
| 111 | + .name = MACHINE_TYPE_NAME("xlnx-zcu102"), | ||
| 112 | + .parent = TYPE_MACHINE, | ||
| 113 | + .class_init = xlnx_zcu102_machine_class_init, | ||
| 114 | + .instance_init = xlnx_zcu102_machine_instance_init, | ||
| 115 | + .instance_size = sizeof(XlnxZCU102), | ||
| 116 | +}; | ||
| 117 | + | ||
| 118 | +static void xlnx_zcu102_machine_init_register_types(void) | ||
| 119 | +{ | ||
| 120 | + type_register_static(&xlnx_zcu102_machine_init_typeinfo); | ||
| 121 | +} | ||
| 122 | + | ||
| 123 | +type_init(xlnx_zcu102_machine_init_register_types) | ||
| 124 | +type_init(xlnx_ep108_machine_init_register_types) | ||
| 125 | -- | ||
| 126 | 2.7.4 | ||
| 127 | |||
| 128 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Add a machine level secure property. This defaults to false and can be | ||
| 4 | set to true using this machine command line argument: | ||
| 5 | -machine xlnx-zcu102,secure=on | ||
| 6 | |||
| 7 | This follows what the ARM virt machine does. | ||
| 8 | |||
| 9 | This property only applies to the ZCU102 machine. The EP108 machine does | ||
| 10 | not have this property. | ||
| 11 | |||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 13 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | --- | ||
| 16 | hw/arm/xlnx-zcu102.c | 32 ++++++++++++++++++++++++++++++++ | ||
| 17 | 1 file changed, 32 insertions(+) | ||
| 18 | |||
| 19 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/hw/arm/xlnx-zcu102.c | ||
| 22 | +++ b/hw/arm/xlnx-zcu102.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 { | ||
| 24 | |||
| 25 | XlnxZynqMPState soc; | ||
| 26 | MemoryRegion ddr_ram; | ||
| 27 | + | ||
| 28 | + bool secure; | ||
| 29 | } XlnxZCU102; | ||
| 30 | |||
| 31 | #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") | ||
| 32 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 { | ||
| 33 | |||
| 34 | static struct arm_boot_info xlnx_zcu102_binfo; | ||
| 35 | |||
| 36 | +static bool zcu102_get_secure(Object *obj, Error **errp) | ||
| 37 | +{ | ||
| 38 | + XlnxZCU102 *s = ZCU102_MACHINE(obj); | ||
| 39 | + | ||
| 40 | + return s->secure; | ||
| 41 | +} | ||
| 42 | + | ||
| 43 | +static void zcu102_set_secure(Object *obj, bool value, Error **errp) | ||
| 44 | +{ | ||
| 45 | + XlnxZCU102 *s = ZCU102_MACHINE(obj); | ||
| 46 | + | ||
| 47 | + s->secure = value; | ||
| 48 | +} | ||
| 49 | + | ||
| 50 | static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) | ||
| 51 | { | ||
| 52 | int i; | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) | ||
| 54 | |||
| 55 | object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram), | ||
| 56 | "ddr-ram", &error_abort); | ||
| 57 | + object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", | ||
| 58 | + &error_fatal); | ||
| 59 | |||
| 60 | object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); | ||
| 61 | |||
| 62 | @@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine) | ||
| 63 | |||
| 64 | static void xlnx_ep108_machine_instance_init(Object *obj) | ||
| 65 | { | ||
| 66 | + XlnxZCU102 *s = EP108_MACHINE(obj); | ||
| 67 | + | ||
| 68 | + /* EP108, we don't support setting secure */ | ||
| 69 | + s->secure = false; | ||
| 70 | } | ||
| 71 | |||
| 72 | static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) | ||
| 73 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine) | ||
| 74 | |||
| 75 | static void xlnx_zcu102_machine_instance_init(Object *obj) | ||
| 76 | { | ||
| 77 | + XlnxZCU102 *s = ZCU102_MACHINE(obj); | ||
| 78 | + | ||
| 79 | + /* Default to secure mode being disabled */ | ||
| 80 | + s->secure = false; | ||
| 81 | + object_property_add_bool(obj, "secure", zcu102_get_secure, | ||
| 82 | + zcu102_set_secure, NULL); | ||
| 83 | + object_property_set_description(obj, "secure", | ||
| 84 | + "Set on/off to enable/disable the ARM " | ||
| 85 | + "Security Extensions (TrustZone)", | ||
| 86 | + NULL); | ||
| 87 | } | ||
| 88 | |||
| 89 | static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) | ||
| 90 | -- | ||
| 91 | 2.7.4 | ||
| 92 | |||
| 93 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Add a machine level virtualization property. This defaults to false and can be | ||
| 4 | set to true using this machine command line argument: | ||
| 5 | -machine xlnx-zcu102,virtualization=on | ||
| 6 | |||
| 7 | This follows what the ARM virt machine does. | ||
| 8 | |||
| 9 | This property only applies to the ZCU102 machine. The EP108 machine does | ||
| 10 | not have this property. | ||
| 11 | |||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 13 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | --- | ||
| 16 | include/hw/arm/xlnx-zynqmp.h | 2 ++ | ||
| 17 | hw/arm/xlnx-zcu102.c | 30 +++++++++++++++++++++++++++++- | ||
| 18 | hw/arm/xlnx-zynqmp.c | 3 ++- | ||
| 19 | 3 files changed, 33 insertions(+), 2 deletions(-) | ||
| 20 | |||
| 21 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/include/hw/arm/xlnx-zynqmp.h | ||
| 24 | +++ b/include/hw/arm/xlnx-zynqmp.h | ||
| 25 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState { | ||
| 26 | |||
| 27 | /* Has the ARM Security extensions? */ | ||
| 28 | bool secure; | ||
| 29 | + /* Has the ARM Virtualization extensions? */ | ||
| 30 | + bool virt; | ||
| 31 | /* Has the RPU subsystem? */ | ||
| 32 | bool has_rpu; | ||
| 33 | } XlnxZynqMPState; | ||
| 34 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c | ||
| 35 | index XXXXXXX..XXXXXXX 100644 | ||
| 36 | --- a/hw/arm/xlnx-zcu102.c | ||
| 37 | +++ b/hw/arm/xlnx-zcu102.c | ||
| 38 | @@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 { | ||
| 39 | MemoryRegion ddr_ram; | ||
| 40 | |||
| 41 | bool secure; | ||
| 42 | + bool virt; | ||
| 43 | } XlnxZCU102; | ||
| 44 | |||
| 45 | #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") | ||
| 46 | @@ -XXX,XX +XXX,XX @@ static void zcu102_set_secure(Object *obj, bool value, Error **errp) | ||
| 47 | s->secure = value; | ||
| 48 | } | ||
| 49 | |||
| 50 | +static bool zcu102_get_virt(Object *obj, Error **errp) | ||
| 51 | +{ | ||
| 52 | + XlnxZCU102 *s = ZCU102_MACHINE(obj); | ||
| 53 | + | ||
| 54 | + return s->virt; | ||
| 55 | +} | ||
| 56 | + | ||
| 57 | +static void zcu102_set_virt(Object *obj, bool value, Error **errp) | ||
| 58 | +{ | ||
| 59 | + XlnxZCU102 *s = ZCU102_MACHINE(obj); | ||
| 60 | + | ||
| 61 | + s->virt = value; | ||
| 62 | +} | ||
| 63 | + | ||
| 64 | static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) | ||
| 65 | { | ||
| 66 | int i; | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) | ||
| 68 | "ddr-ram", &error_abort); | ||
| 69 | object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", | ||
| 70 | &error_fatal); | ||
| 71 | + object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization", | ||
| 72 | + &error_fatal); | ||
| 73 | |||
| 74 | object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); | ||
| 75 | |||
| 76 | @@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_instance_init(Object *obj) | ||
| 77 | { | ||
| 78 | XlnxZCU102 *s = EP108_MACHINE(obj); | ||
| 79 | |||
| 80 | - /* EP108, we don't support setting secure */ | ||
| 81 | + /* EP108, we don't support setting secure or virt */ | ||
| 82 | s->secure = false; | ||
| 83 | + s->virt = false; | ||
| 84 | } | ||
| 85 | |||
| 86 | static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) | ||
| 87 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj) | ||
| 88 | "Set on/off to enable/disable the ARM " | ||
| 89 | "Security Extensions (TrustZone)", | ||
| 90 | NULL); | ||
| 91 | + | ||
| 92 | + /* Default to virt (EL2) being disabled */ | ||
| 93 | + s->virt = false; | ||
| 94 | + object_property_add_bool(obj, "virtualization", zcu102_get_virt, | ||
| 95 | + zcu102_set_virt, NULL); | ||
| 96 | + object_property_set_description(obj, "virtualization", | ||
| 97 | + "Set on/off to enable/disable emulating a " | ||
| 98 | + "guest CPU which implements the ARM " | ||
| 99 | + "Virtualization Extensions", | ||
| 100 | + NULL); | ||
| 101 | } | ||
| 102 | |||
| 103 | static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) | ||
| 104 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
| 105 | index XXXXXXX..XXXXXXX 100644 | ||
| 106 | --- a/hw/arm/xlnx-zynqmp.c | ||
| 107 | +++ b/hw/arm/xlnx-zynqmp.c | ||
| 108 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
| 109 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), | ||
| 110 | s->secure, "has_el3", NULL); | ||
| 111 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), | ||
| 112 | - false, "has_el2", NULL); | ||
| 113 | + s->virt, "has_el2", NULL); | ||
| 114 | object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, | ||
| 115 | "reset-cbar", &error_abort); | ||
| 116 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", | ||
| 117 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
| 118 | static Property xlnx_zynqmp_props[] = { | ||
| 119 | DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), | ||
| 120 | DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), | ||
| 121 | + DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), | ||
| 122 | DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), | ||
| 123 | DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, | ||
| 124 | MemoryRegion *), | ||
| 125 | -- | ||
| 126 | 2.7.4 | ||
| 127 | |||
| 128 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alistair Francis <alistair.francis@xilinx.com> | ||
| 2 | 1 | ||
| 3 | The EP108 is the same as the ZCU102, mark it as deprecated as we don't | ||
| 4 | need two machines. | ||
| 5 | |||
| 6 | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 7 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | hw/arm/xlnx-zcu102.c | 2 +- | ||
| 11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 12 | |||
| 13 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/hw/arm/xlnx-zcu102.c | ||
| 16 | +++ b/hw/arm/xlnx-zcu102.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) | ||
| 18 | { | ||
| 19 | MachineClass *mc = MACHINE_CLASS(oc); | ||
| 20 | |||
| 21 | - mc->desc = "Xilinx ZynqMP EP108 board"; | ||
| 22 | + mc->desc = "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-zcu102)"; | ||
| 23 | mc->init = xlnx_ep108_init; | ||
| 24 | mc->block_default_type = IF_IDE; | ||
| 25 | mc->units_per_default_bus = 1; | ||
| 26 | -- | ||
| 27 | 2.7.4 | ||
| 28 | |||
| 29 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Jaroslaw Pelczar <j.pelczar@samsung.com> | ||
| 2 | 1 | ||
| 3 | Previously when single stepping through ERET instruction via GDB | ||
| 4 | would result in debugger entering the "next" PC after ERET instruction. | ||
| 5 | When debugging in kernel mode, this will also cause unintended behavior, | ||
| 6 | because debugger will try to access memory from EL0 point of view. | ||
| 7 | |||
| 8 | Signed-off-by: Jaroslaw Pelczar <j.pelczar@samsung.com> | ||
| 9 | Message-id: 001c01d32895$483027f0$d89077d0$@samsung.com | ||
| 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | target/arm/translate-a64.c | 1 + | ||
| 14 | 1 file changed, 1 insertion(+) | ||
| 15 | |||
| 16 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/translate-a64.c | ||
| 19 | +++ b/target/arm/translate-a64.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
| 21 | default: | ||
| 22 | gen_a64_set_pc_im(dc->pc); | ||
| 23 | /* fall through */ | ||
| 24 | + case DISAS_EXIT: | ||
| 25 | case DISAS_JUMP: | ||
| 26 | if (dc->base.singlestep_enabled) { | ||
| 27 | gen_exception_internal(EXCP_DEBUG); | ||
| 28 | -- | ||
| 29 | 2.7.4 | ||
| 30 | |||
| 31 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Instead of copying addr to a local temp, reuse the value (which we | ||
| 4 | have just compared as equal) already saved in cpu_exclusive_addr. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 8 | Message-id: 20170908163859.29820-1-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/translate-a64.c | 26 +++++++++----------------- | ||
| 12 | 1 file changed, 9 insertions(+), 17 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/translate-a64.c | ||
| 17 | +++ b/target/arm/translate-a64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, | ||
| 19 | } | ||
| 20 | |||
| 21 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | ||
| 22 | - TCGv_i64 inaddr, int size, int is_pair) | ||
| 23 | + TCGv_i64 addr, int size, int is_pair) | ||
| 24 | { | ||
| 25 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] | ||
| 26 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | ||
| 27 | @@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | ||
| 28 | */ | ||
| 29 | TCGLabel *fail_label = gen_new_label(); | ||
| 30 | TCGLabel *done_label = gen_new_label(); | ||
| 31 | - TCGv_i64 addr = tcg_temp_local_new_i64(); | ||
| 32 | TCGv_i64 tmp; | ||
| 33 | |||
| 34 | - /* Copy input into a local temp so it is not trashed when the | ||
| 35 | - * basic block ends at the branch insn. | ||
| 36 | - */ | ||
| 37 | - tcg_gen_mov_i64(addr, inaddr); | ||
| 38 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); | ||
| 39 | |||
| 40 | tmp = tcg_temp_new_i64(); | ||
| 41 | @@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | ||
| 42 | } else { | ||
| 43 | tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); | ||
| 44 | } | ||
| 45 | - tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, | ||
| 46 | + tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, | ||
| 47 | + cpu_exclusive_val, tmp, | ||
| 48 | get_mem_index(s), | ||
| 49 | MO_64 | MO_ALIGN | s->be_data); | ||
| 50 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); | ||
| 51 | } else if (s->be_data == MO_LE) { | ||
| 52 | - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), | ||
| 53 | - cpu_reg(s, rt2)); | ||
| 54 | + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, | ||
| 55 | + cpu_reg(s, rt), cpu_reg(s, rt2)); | ||
| 56 | } else { | ||
| 57 | - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, rt), | ||
| 58 | - cpu_reg(s, rt2)); | ||
| 59 | + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, | ||
| 60 | + cpu_reg(s, rt), cpu_reg(s, rt2)); | ||
| 61 | } | ||
| 62 | } else { | ||
| 63 | - TCGv_i64 val = cpu_reg(s, rt); | ||
| 64 | - tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val, | ||
| 65 | - get_mem_index(s), | ||
| 66 | + tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, | ||
| 67 | + cpu_reg(s, rt), get_mem_index(s), | ||
| 68 | size | MO_ALIGN | s->be_data); | ||
| 69 | tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); | ||
| 70 | } | ||
| 71 | - | ||
| 72 | - tcg_temp_free_i64(addr); | ||
| 73 | - | ||
| 74 | tcg_gen_mov_i64(cpu_reg(s, rd), tmp); | ||
| 75 | tcg_temp_free_i64(tmp); | ||
| 76 | tcg_gen_br(done_label); | ||
| 77 | -- | ||
| 78 | 2.7.4 | ||
| 79 | |||
| 80 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> | ||
| 2 | 1 | ||
| 3 | To implement INTx to gsi routing we need to pass the gpex host | ||
| 4 | bridge the gsi associated to each INTx index. Let's introduce | ||
| 5 | irq_num array and gpex_set_irq_num setter function. | ||
| 6 | |||
| 7 | Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> | ||
| 8 | Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org> | ||
| 9 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
| 10 | Tested-by: Feng Kan <fkan@apm.com> | ||
| 11 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
| 12 | Message-id: 1505296004-6798-2-git-send-email-eric.auger@redhat.com | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | include/hw/pci-host/gpex.h | 3 +++ | ||
| 16 | hw/pci-host/gpex.c | 10 ++++++++++ | ||
| 17 | 2 files changed, 13 insertions(+) | ||
| 18 | |||
| 19 | diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/include/hw/pci-host/gpex.h | ||
| 22 | +++ b/include/hw/pci-host/gpex.h | ||
| 23 | @@ -XXX,XX +XXX,XX @@ typedef struct GPEXHost { | ||
| 24 | MemoryRegion io_ioport; | ||
| 25 | MemoryRegion io_mmio; | ||
| 26 | qemu_irq irq[GPEX_NUM_IRQS]; | ||
| 27 | + int irq_num[GPEX_NUM_IRQS]; | ||
| 28 | } GPEXHost; | ||
| 29 | |||
| 30 | +int gpex_set_irq_num(GPEXHost *s, int index, int gsi); | ||
| 31 | + | ||
| 32 | #endif /* HW_GPEX_H */ | ||
| 33 | diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/hw/pci-host/gpex.c | ||
| 36 | +++ b/hw/pci-host/gpex.c | ||
| 37 | @@ -XXX,XX +XXX,XX @@ static void gpex_set_irq(void *opaque, int irq_num, int level) | ||
| 38 | qemu_set_irq(s->irq[irq_num], level); | ||
| 39 | } | ||
| 40 | |||
| 41 | +int gpex_set_irq_num(GPEXHost *s, int index, int gsi) | ||
| 42 | +{ | ||
| 43 | + if (index >= GPEX_NUM_IRQS) { | ||
| 44 | + return -EINVAL; | ||
| 45 | + } | ||
| 46 | + | ||
| 47 | + s->irq_num[index] = gsi; | ||
| 48 | + return 0; | ||
| 49 | +} | ||
| 50 | + | ||
| 51 | static void gpex_host_realize(DeviceState *dev, Error **errp) | ||
| 52 | { | ||
| 53 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); | ||
| 54 | -- | ||
| 55 | 2.7.4 | ||
| 56 | |||
| 57 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> | ||
| 2 | 1 | ||
| 3 | Let's provide the GPEX host bridge with the INTx/gsi mapping. This is | ||
| 4 | needed for INTx/gsi routing. | ||
| 5 | |||
| 6 | Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> | ||
| 7 | Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org> | ||
| 8 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
| 9 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
| 10 | Tested-by: Feng Kan <fkan@apm.com> | ||
| 11 | Message-id: 1505296004-6798-3-git-send-email-eric.auger@redhat.com | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | --- | ||
| 14 | hw/arm/virt.c | 1 + | ||
| 15 | 1 file changed, 1 insertion(+) | ||
| 16 | |||
| 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/hw/arm/virt.c | ||
| 20 | +++ b/hw/arm/virt.c | ||
| 21 | @@ -XXX,XX +XXX,XX @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) | ||
| 22 | |||
| 23 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | ||
| 24 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | ||
| 25 | + gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); | ||
| 26 | } | ||
| 27 | |||
| 28 | pci = PCI_HOST_BRIDGE(dev); | ||
| 29 | -- | ||
| 30 | 2.7.4 | ||
| 31 | |||
| 32 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> | ||
| 2 | 1 | ||
| 3 | Now we are able to retrieve the gsi from the INTx pin, let's | ||
| 4 | enable intx_to_irq routing. From that point on, irqfd becomes | ||
| 5 | usable along with INTx when assigning a PCIe device. | ||
| 6 | |||
| 7 | Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> | ||
| 8 | Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org> | ||
| 9 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
| 10 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
| 11 | Tested-by: Feng Kan <fkan@apm.com> | ||
| 12 | Message-id: 1505296004-6798-4-git-send-email-eric.auger@redhat.com | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | hw/pci-host/gpex.c | 12 ++++++++++++ | ||
| 16 | 1 file changed, 12 insertions(+) | ||
| 17 | |||
| 18 | diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/hw/pci-host/gpex.c | ||
| 21 | +++ b/hw/pci-host/gpex.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ int gpex_set_irq_num(GPEXHost *s, int index, int gsi) | ||
| 23 | return 0; | ||
| 24 | } | ||
| 25 | |||
| 26 | +static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) | ||
| 27 | +{ | ||
| 28 | + PCIINTxRoute route; | ||
| 29 | + GPEXHost *s = opaque; | ||
| 30 | + | ||
| 31 | + route.mode = PCI_INTX_ENABLED; | ||
| 32 | + route.irq = s->irq_num[pin]; | ||
| 33 | + | ||
| 34 | + return route; | ||
| 35 | +} | ||
| 36 | + | ||
| 37 | static void gpex_host_realize(DeviceState *dev, Error **errp) | ||
| 38 | { | ||
| 39 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static void gpex_host_realize(DeviceState *dev, Error **errp) | ||
| 41 | &s->io_ioport, 0, 4, TYPE_PCIE_BUS); | ||
| 42 | |||
| 43 | qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus)); | ||
| 44 | + pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); | ||
| 45 | qdev_init_nofail(DEVICE(&s->gpex_root)); | ||
| 46 | } | ||
| 47 | |||
| 48 | -- | ||
| 49 | 2.7.4 | ||
| 50 | |||
| 51 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Fix an error that meant we were wiring every UART's overflow | ||
| 2 | interrupts into the same inputs 0 and 1 of the OR gate, | ||
| 3 | rather than giving each its own input. | ||
| 4 | 1 | ||
| 5 | Cc: qemu-stable@nongnu.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
| 9 | Message-id: 1505232834-20890-1-git-send-email-peter.maydell@linaro.org | ||
| 10 | --- | ||
| 11 | hw/arm/mps2.c | 4 ++-- | ||
| 12 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/hw/arm/mps2.c | ||
| 17 | +++ b/hw/arm/mps2.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | ||
| 19 | cmsdk_apb_uart_create(uartbase[i], | ||
| 20 | qdev_get_gpio_in(txrx_orgate_dev, 0), | ||
| 21 | qdev_get_gpio_in(txrx_orgate_dev, 1), | ||
| 22 | - qdev_get_gpio_in(orgate_dev, 0), | ||
| 23 | - qdev_get_gpio_in(orgate_dev, 1), | ||
| 24 | + qdev_get_gpio_in(orgate_dev, i * 2), | ||
| 25 | + qdev_get_gpio_in(orgate_dev, i * 2 + 1), | ||
| 26 | NULL, | ||
| 27 | uartchr, SYSCLK_FRQ); | ||
| 28 | } | ||
| 29 | -- | ||
| 30 | 2.7.4 | ||
| 31 | |||
| 32 | diff view generated by jsdifflib |