1
ARM queue: nothing particularly exciting, but 18 patches
1
Small pile of bug fixes for rc1. I've included my patches to get
2
is enough to send out.
2
our docs building with Sphinx 3, just for convenience...
3
3
4
thanks
5
-- PMM
4
-- PMM
6
5
7
The following changes since commit 3dabde1128b671f36ac6cb36b97b273139964420:
6
The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96:
8
7
9
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20170914' into staging (2017-09-14 16:33:02 +0100)
8
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000)
10
9
11
are available in the git repository at:
10
are available in the Git repository at:
12
11
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170914
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102
14
13
15
for you to fetch changes up to ce3bc112cdb1d462e2d52eaa17a7314e7f3af504:
14
for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a:
16
15
17
mps2-an511: Fix wiring of UART overflow interrupt lines (2017-09-14 18:43:19 +0100)
16
tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* v7M: various code cleanups
20
* target/arm: Fix Neon emulation bugs on big-endian hosts
22
* v7M: set correct BFSR bits on bus fault
21
* target/arm: fix handling of HCR.FB
23
* v7M: clear exclusive monitor on reset and exception entry/exit
22
* target/arm: fix LORID_EL1 access check
24
* v7M: don't apply priority mask to negative priorities
23
* disas/capstone: Fix monitor disassembly of >32 bytes
25
* zcu102: support 'secure' and 'virtualization' machine properties
24
* hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
26
* aarch64: fix ERET single stepping
25
* hw/arm/boot: fix SVE for EL3 direct kernel boot
27
* gpex: implement PCI INTx routing
26
* hw/display/omap_lcdc: Fix potential NULL pointer dereference
28
* mps2-an511: fix UART overflow interrupt line wiring
27
* hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
28
* target/arm: Get correct MMU index for other-security-state
29
* configure: Test that gio libs from pkg-config work
30
* hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
31
* docs: Fix building with Sphinx 3
32
* tests/qtest/npcm7xx_rng-test: Disable randomness tests
29
33
30
----------------------------------------------------------------
34
----------------------------------------------------------------
31
Alistair Francis (5):
35
AlexChen (2):
32
xlnx-ep108: Rename to ZCU102
36
hw/display/omap_lcdc: Fix potential NULL pointer dereference
33
xlnx-zcu102: Manually create the machines
37
hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
34
xlnx-zcu102: Add a machine level secure property
35
xlnx-zcu102: Add a machine level virtualization property
36
xlnx-zcu102: Mark the EP108 machine as deprecated
37
38
38
Jaroslaw Pelczar (1):
39
Peter Maydell (9):
39
AArch64: Fix single stepping of ERET instruction
40
target/arm: Fix float16 pairwise Neon ops on big-endian hosts
41
target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
42
disas/capstone: Fix monitor disassembly of >32 bytes
43
target/arm: Get correct MMU index for other-security-state
44
configure: Test that gio libs from pkg-config work
45
hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
46
scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
47
qemu-option-trace.rst.inc: Don't use option:: markup
48
tests/qtest/npcm7xx_rng-test: Disable randomness tests
40
49
41
Peter Maydell (8):
50
Philippe Mathieu-Daudé (1):
42
target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2
51
hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
43
target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
44
target/arm: Get PRECISERR and IBUSERR the right way round
45
nvic: Don't apply group priority mask to negative priorities
46
target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()
47
target/arm: Add and use defines for EXCRET constants
48
target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()
49
mps2-an511: Fix wiring of UART overflow interrupt lines
50
52
51
Pranavkumar Sawargaonkar (3):
53
Richard Henderson (11):
52
hw/pci-host/gpex: Set INTx index/gsi mapping
54
target/arm: Introduce neon_full_reg_offset
53
hw/arm/virt: Set INTx/gsi mapping
55
target/arm: Move neon_element_offset to translate.c
54
hw/pci-host/gpex: Implement PCI INTx routing
56
target/arm: Use neon_element_offset in neon_load/store_reg
57
target/arm: Use neon_element_offset in vfp_reg_offset
58
target/arm: Add read/write_neon_element32
59
target/arm: Expand read/write_neon_element32 to all MemOp
60
target/arm: Rename neon_load_reg32 to vfp_load_reg32
61
target/arm: Add read/write_neon_element64
62
target/arm: Rename neon_load_reg64 to vfp_load_reg64
63
target/arm: Simplify do_long_3d and do_2scalar_long
64
target/arm: Improve do_prewiden_3d
55
65
56
Richard Henderson (1):
66
Rémi Denis-Courmont (3):
57
target/arm: Avoid an extra temporary for store_exclusive
67
target/arm: fix handling of HCR.FB
68
target/arm: fix LORID_EL1 access check
69
hw/arm/boot: fix SVE for EL3 direct kernel boot
58
70
59
hw/arm/Makefile.objs | 2 +-
71
docs/qemu-option-trace.rst.inc | 6 +-
60
include/hw/arm/xlnx-zynqmp.h | 2 +
72
configure | 10 +-
61
include/hw/pci-host/gpex.h | 3 +
73
include/hw/intc/arm_gicv3_common.h | 1 -
62
target/arm/cpu.h | 35 +++---
74
disas/capstone.c | 2 +-
63
target/arm/internals.h | 20 ++++
75
hw/arm/boot.c | 3 +
64
hw/arm/mps2.c | 4 +-
76
hw/arm/smmuv3.c | 3 +-
65
hw/arm/virt.c | 1 +
77
hw/display/exynos4210_fimd.c | 4 +-
66
hw/arm/xlnx-ep108.c | 139 -----------------------
78
hw/display/omap_lcdc.c | 10 +-
67
hw/arm/xlnx-zcu102.c | 259 +++++++++++++++++++++++++++++++++++++++++++
79
hw/intc/arm_gicv3_cpuif.c | 5 +-
68
hw/arm/xlnx-zynqmp.c | 3 +-
80
target/arm/helper.c | 24 +-
69
hw/intc/armv7m_nvic.c | 11 +-
81
target/arm/m_helper.c | 3 +-
70
hw/pci-host/gpex.c | 22 ++++
82
target/arm/translate.c | 153 +++++++++---
71
target/arm/cpu.c | 6 +
83
target/arm/vec_helper.c | 12 +-
72
target/arm/helper.c | 43 ++++---
84
tests/qtest/npcm7xx_rng-test.c | 14 +-
73
target/arm/op_helper.c | 2 +-
85
scripts/kernel-doc | 18 +-
74
target/arm/translate-a64.c | 27 ++---
86
target/arm/translate-neon.c.inc | 472 ++++++++++++++++++++-----------------
75
16 files changed, 382 insertions(+), 197 deletions(-)
87
target/arm/translate-vfp.c.inc | 341 +++++++++++----------------
76
delete mode 100644 hw/arm/xlnx-ep108.c
88
17 files changed, 588 insertions(+), 493 deletions(-)
77
create mode 100644 hw/arm/xlnx-zcu102.c
78
89
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In preperation for future work let's manually create the Xilnx machines.
3
This function makes it clear that we're talking about the whole
4
This will allow us to set properties for the machines in the future.
4
register, and not the 32-bit piece at index 0. This fixes a bug
5
when running on a big-endian host.
5
6
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Message-id: 20201030022618.785675-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
hw/arm/xlnx-zcu102.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++-----
12
target/arm/translate.c | 8 ++++++
11
1 file changed, 67 insertions(+), 7 deletions(-)
13
target/arm/translate-neon.c.inc | 44 ++++++++++++++++-----------------
14
target/arm/translate-vfp.c.inc | 2 +-
15
3 files changed, 31 insertions(+), 23 deletions(-)
12
16
13
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/xlnx-zcu102.c
19
--- a/target/arm/translate.c
16
+++ b/hw/arm/xlnx-zcu102.c
20
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
18
#include "qemu/log.h"
22
unallocated_encoding(s);
19
20
typedef struct XlnxZCU102 {
21
+ MachineState parent_obj;
22
+
23
XlnxZynqMPState soc;
24
MemoryRegion ddr_ram;
25
} XlnxZCU102;
26
27
+#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
28
+#define ZCU102_MACHINE(obj) \
29
+ OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
30
+
31
+#define TYPE_EP108_MACHINE MACHINE_TYPE_NAME("xlnx-ep108")
32
+#define EP108_MACHINE(obj) \
33
+ OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE)
34
+
35
static struct arm_boot_info xlnx_zcu102_binfo;
36
37
-static void xlnx_zcu102_init(MachineState *machine)
38
+static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
39
{
40
- XlnxZCU102 *s = g_new0(XlnxZCU102, 1);
41
int i;
42
uint64_t ram_size = machine->ram_size;
43
44
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
45
arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
46
}
23
}
47
24
48
-static void xlnx_ep108_machine_init(MachineClass *mc)
25
+/*
49
+static void xlnx_ep108_init(MachineState *machine)
26
+ * Return the offset of a "full" NEON Dreg.
27
+ */
28
+static long neon_full_reg_offset(unsigned reg)
50
+{
29
+{
51
+ XlnxZCU102 *s = EP108_MACHINE(machine);
30
+ return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
52
+
53
+ xlnx_zynqmp_init(s, machine);
54
+}
31
+}
55
+
32
+
56
+static void xlnx_ep108_machine_instance_init(Object *obj)
33
static inline long vfp_reg_offset(bool dp, unsigned reg)
57
{
34
{
58
+}
35
if (dp) {
59
+
36
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
60
+static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
37
index XXXXXXX..XXXXXXX 100644
61
+{
38
--- a/target/arm/translate-neon.c.inc
62
+ MachineClass *mc = MACHINE_CLASS(oc);
39
+++ b/target/arm/translate-neon.c.inc
63
+
40
@@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size)
64
mc->desc = "Xilinx ZynqMP EP108 board";
41
ofs ^= 8 - element_size;
65
- mc->init = xlnx_zcu102_init;
42
}
66
+ mc->init = xlnx_ep108_init;
43
#endif
67
mc->block_default_type = IF_IDE;
44
- return neon_reg_offset(reg, 0) + ofs;
68
mc->units_per_default_bus = 1;
45
+ return neon_full_reg_offset(reg) + ofs;
69
mc->ignore_memory_transaction_failures = true;
70
}
46
}
71
47
72
-DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init)
48
static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
73
+static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
49
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
74
+ .name = MACHINE_TYPE_NAME("xlnx-ep108"),
50
* We cannot write 16 bytes at once because the
75
+ .parent = TYPE_MACHINE,
51
* destination is unaligned.
76
+ .class_init = xlnx_ep108_machine_class_init,
52
*/
77
+ .instance_init = xlnx_ep108_machine_instance_init,
53
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
78
+ .instance_size = sizeof(XlnxZCU102),
54
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
79
+};
55
8, 8, tmp);
80
56
- tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
81
-static void xlnx_zcu102_machine_init(MachineClass *mc)
57
- neon_reg_offset(vd, 0), 8, 8);
82
+static void xlnx_ep108_machine_init_register_types(void)
58
+ tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1),
59
+ neon_full_reg_offset(vd), 8, 8);
60
} else {
61
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
62
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
63
vec_size, vec_size, tmp);
64
}
65
tcg_gen_addi_i32(addr, addr, 1 << size);
66
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
67
static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
83
{
68
{
84
+ type_register_static(&xlnx_ep108_machine_init_typeinfo);
69
int vec_size = a->q ? 16 : 8;
85
+}
70
- int rd_ofs = neon_reg_offset(a->vd, 0);
86
+
71
- int rn_ofs = neon_reg_offset(a->vn, 0);
87
+static void xlnx_zcu102_init(MachineState *machine)
72
- int rm_ofs = neon_reg_offset(a->vm, 0);
88
+{
73
+ int rd_ofs = neon_full_reg_offset(a->vd);
89
+ XlnxZCU102 *s = ZCU102_MACHINE(machine);
74
+ int rn_ofs = neon_full_reg_offset(a->vn);
90
+
75
+ int rm_ofs = neon_full_reg_offset(a->vm);
91
+ xlnx_zynqmp_init(s, machine);
76
92
+}
77
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
93
+
78
return false;
94
+static void xlnx_zcu102_machine_instance_init(Object *obj)
79
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
95
+{
80
{
96
+}
81
/* Handle a 2-reg-shift insn which can be vectorized. */
97
+
82
int vec_size = a->q ? 16 : 8;
98
+static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
83
- int rd_ofs = neon_reg_offset(a->vd, 0);
99
+{
84
- int rm_ofs = neon_reg_offset(a->vm, 0);
100
+ MachineClass *mc = MACHINE_CLASS(oc);
85
+ int rd_ofs = neon_full_reg_offset(a->vd);
101
+
86
+ int rm_ofs = neon_full_reg_offset(a->vm);
102
mc->desc = "Xilinx ZynqMP ZCU102 board";
87
103
mc->init = xlnx_zcu102_init;
88
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
104
mc->block_default_type = IF_IDE;
89
return false;
105
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_init(MachineClass *mc)
90
@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
106
mc->ignore_memory_transaction_failures = true;
91
{
92
/* FP operations in 2-reg-and-shift group */
93
int vec_size = a->q ? 16 : 8;
94
- int rd_ofs = neon_reg_offset(a->vd, 0);
95
- int rm_ofs = neon_reg_offset(a->vm, 0);
96
+ int rd_ofs = neon_full_reg_offset(a->vd);
97
+ int rm_ofs = neon_full_reg_offset(a->vm);
98
TCGv_ptr fpst;
99
100
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
101
@@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
102
return true;
103
}
104
105
- reg_ofs = neon_reg_offset(a->vd, 0);
106
+ reg_ofs = neon_full_reg_offset(a->vd);
107
vec_size = a->q ? 16 : 8;
108
imm = asimd_imm_const(a->imm, a->cmode, a->op);
109
110
@@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
111
return true;
112
}
113
114
- tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0),
115
- neon_reg_offset(a->vn, 0),
116
- neon_reg_offset(a->vm, 0),
117
+ tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd),
118
+ neon_full_reg_offset(a->vn),
119
+ neon_full_reg_offset(a->vm),
120
16, 16, 0, fn_gvec);
121
return true;
107
}
122
}
108
123
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
109
-DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init)
124
{
110
+static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
125
/* Two registers and a scalar, using gvec */
111
+ .name = MACHINE_TYPE_NAME("xlnx-zcu102"),
126
int vec_size = a->q ? 16 : 8;
112
+ .parent = TYPE_MACHINE,
127
- int rd_ofs = neon_reg_offset(a->vd, 0);
113
+ .class_init = xlnx_zcu102_machine_class_init,
128
- int rn_ofs = neon_reg_offset(a->vn, 0);
114
+ .instance_init = xlnx_zcu102_machine_instance_init,
129
+ int rd_ofs = neon_full_reg_offset(a->vd);
115
+ .instance_size = sizeof(XlnxZCU102),
130
+ int rn_ofs = neon_full_reg_offset(a->vn);
116
+};
131
int rm_ofs;
117
+
132
int idx;
118
+static void xlnx_zcu102_machine_init_register_types(void)
133
TCGv_ptr fpstatus;
119
+{
134
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
120
+ type_register_static(&xlnx_zcu102_machine_init_typeinfo);
135
/* a->vm is M:Vm, which encodes both register and index */
121
+}
136
idx = extract32(a->vm, a->size + 2, 2);
122
+
137
a->vm = extract32(a->vm, 0, a->size + 2);
123
+type_init(xlnx_zcu102_machine_init_register_types)
138
- rm_ofs = neon_reg_offset(a->vm, 0);
124
+type_init(xlnx_ep108_machine_init_register_types)
139
+ rm_ofs = neon_full_reg_offset(a->vm);
140
141
fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD);
142
tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus,
143
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
144
return true;
145
}
146
147
- tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0),
148
+ tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd),
149
neon_element_offset(a->vm, a->index, a->size),
150
a->q ? 16 : 8, a->q ? 16 : 8);
151
return true;
152
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
153
static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
154
{
155
int vec_size = a->q ? 16 : 8;
156
- int rd_ofs = neon_reg_offset(a->vd, 0);
157
- int rm_ofs = neon_reg_offset(a->vm, 0);
158
+ int rd_ofs = neon_full_reg_offset(a->vd);
159
+ int rm_ofs = neon_full_reg_offset(a->vm);
160
161
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
162
return false;
163
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
164
index XXXXXXX..XXXXXXX 100644
165
--- a/target/arm/translate-vfp.c.inc
166
+++ b/target/arm/translate-vfp.c.inc
167
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
168
}
169
170
tmp = load_reg(s, a->rt);
171
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
172
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn),
173
vec_size, vec_size, tmp);
174
tcg_temp_free_i32(tmp);
175
125
--
176
--
126
2.7.4
177
2.20.1
127
178
128
179
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Instead of copying addr to a local temp, reuse the value (which we
3
This will shortly have users outside of translate-neon.c.inc.
4
have just compared as equal) already saved in cpu_exclusive_addr.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
6
Message-id: 20201030022618.785675-3-richard.henderson@linaro.org
8
Message-id: 20170908163859.29820-1-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
9
---
11
target/arm/translate-a64.c | 26 +++++++++-----------------
10
target/arm/translate.c | 20 ++++++++++++++++++++
12
1 file changed, 9 insertions(+), 17 deletions(-)
11
target/arm/translate-neon.c.inc | 19 -------------------
12
2 files changed, 20 insertions(+), 19 deletions(-)
13
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
16
--- a/target/arm/translate.c
17
+++ b/target/arm/translate-a64.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
18
@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
19
return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
19
}
20
}
20
21
21
static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
22
+/*
22
- TCGv_i64 inaddr, int size, int is_pair)
23
+ * Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
23
+ TCGv_i64 addr, int size, int is_pair)
24
+ * where 0 is the least significant end of the register.
25
+ */
26
+static long neon_element_offset(int reg, int element, MemOp size)
27
+{
28
+ int element_size = 1 << size;
29
+ int ofs = element * element_size;
30
+#ifdef HOST_WORDS_BIGENDIAN
31
+ /*
32
+ * Calculate the offset assuming fully little-endian,
33
+ * then XOR to account for the order of the 8-byte units.
34
+ */
35
+ if (element_size < 8) {
36
+ ofs ^= 8 - element_size;
37
+ }
38
+#endif
39
+ return neon_full_reg_offset(reg) + ofs;
40
+}
41
+
42
static inline long vfp_reg_offset(bool dp, unsigned reg)
24
{
43
{
25
/* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
44
if (dp) {
26
* && (!is_pair || env->exclusive_high == [addr + datasize])) {
45
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
27
@@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
46
index XXXXXXX..XXXXXXX 100644
28
*/
47
--- a/target/arm/translate-neon.c.inc
29
TCGLabel *fail_label = gen_new_label();
48
+++ b/target/arm/translate-neon.c.inc
30
TCGLabel *done_label = gen_new_label();
49
@@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x)
31
- TCGv_i64 addr = tcg_temp_local_new_i64();
50
#include "decode-neon-ls.c.inc"
32
TCGv_i64 tmp;
51
#include "decode-neon-shared.c.inc"
33
52
34
- /* Copy input into a local temp so it is not trashed when the
53
-/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
35
- * basic block ends at the branch insn.
54
- * where 0 is the least significant end of the register.
55
- */
56
-static inline long
57
-neon_element_offset(int reg, int element, MemOp size)
58
-{
59
- int element_size = 1 << size;
60
- int ofs = element * element_size;
61
-#ifdef HOST_WORDS_BIGENDIAN
62
- /* Calculate the offset assuming fully little-endian,
63
- * then XOR to account for the order of the 8-byte units.
36
- */
64
- */
37
- tcg_gen_mov_i64(addr, inaddr);
65
- if (element_size < 8) {
38
tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
66
- ofs ^= 8 - element_size;
39
67
- }
40
tmp = tcg_temp_new_i64();
68
-#endif
41
@@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
69
- return neon_full_reg_offset(reg) + ofs;
42
} else {
70
-}
43
tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt));
44
}
45
- tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp,
46
+ tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,
47
+ cpu_exclusive_val, tmp,
48
get_mem_index(s),
49
MO_64 | MO_ALIGN | s->be_data);
50
tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
51
} else if (s->be_data == MO_LE) {
52
- gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt),
53
- cpu_reg(s, rt2));
54
+ gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr,
55
+ cpu_reg(s, rt), cpu_reg(s, rt2));
56
} else {
57
- gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, rt),
58
- cpu_reg(s, rt2));
59
+ gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr,
60
+ cpu_reg(s, rt), cpu_reg(s, rt2));
61
}
62
} else {
63
- TCGv_i64 val = cpu_reg(s, rt);
64
- tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val,
65
- get_mem_index(s),
66
+ tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,
67
+ cpu_reg(s, rt), get_mem_index(s),
68
size | MO_ALIGN | s->be_data);
69
tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
70
}
71
-
71
-
72
- tcg_temp_free_i64(addr);
72
static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
73
-
73
{
74
tcg_gen_mov_i64(cpu_reg(s, rd), tmp);
74
long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
75
tcg_temp_free_i64(tmp);
76
tcg_gen_br(done_label);
77
--
75
--
78
2.7.4
76
2.20.1
79
77
80
78
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add a machine level virtualization property. This defaults to false and can be
3
These are the only users of neon_reg_offset, so remove that.
4
set to true using this machine command line argument:
5
-machine xlnx-zcu102,virtualization=on
6
4
7
This follows what the ARM virt machine does.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
6
Message-id: 20201030022618.785675-4-richard.henderson@linaro.org
9
This property only applies to the ZCU102 machine. The EP108 machine does
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
not have this property.
11
12
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
9
---
16
include/hw/arm/xlnx-zynqmp.h | 2 ++
10
target/arm/translate.c | 14 ++------------
17
hw/arm/xlnx-zcu102.c | 30 +++++++++++++++++++++++++++++-
11
1 file changed, 2 insertions(+), 12 deletions(-)
18
hw/arm/xlnx-zynqmp.c | 3 ++-
19
3 files changed, 33 insertions(+), 2 deletions(-)
20
12
21
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
22
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/xlnx-zynqmp.h
15
--- a/target/arm/translate.c
24
+++ b/include/hw/arm/xlnx-zynqmp.h
16
+++ b/target/arm/translate.c
25
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState {
17
@@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg)
26
18
}
27
/* Has the ARM Security extensions? */
28
bool secure;
29
+ /* Has the ARM Virtualization extensions? */
30
+ bool virt;
31
/* Has the RPU subsystem? */
32
bool has_rpu;
33
} XlnxZynqMPState;
34
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/arm/xlnx-zcu102.c
37
+++ b/hw/arm/xlnx-zcu102.c
38
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
39
MemoryRegion ddr_ram;
40
41
bool secure;
42
+ bool virt;
43
} XlnxZCU102;
44
45
#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
46
@@ -XXX,XX +XXX,XX @@ static void zcu102_set_secure(Object *obj, bool value, Error **errp)
47
s->secure = value;
48
}
19
}
49
20
50
+static bool zcu102_get_virt(Object *obj, Error **errp)
21
-/* Return the offset of a 32-bit piece of a NEON register.
51
+{
22
- zero is the least significant end of the register. */
52
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
23
-static inline long
53
+
24
-neon_reg_offset (int reg, int n)
54
+ return s->virt;
25
-{
55
+}
26
- int sreg;
56
+
27
- sreg = reg * 2 + n;
57
+static void zcu102_set_virt(Object *obj, bool value, Error **errp)
28
- return vfp_reg_offset(0, sreg);
58
+{
29
-}
59
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
30
-
60
+
31
static TCGv_i32 neon_load_reg(int reg, int pass)
61
+ s->virt = value;
62
+}
63
+
64
static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
65
{
32
{
66
int i;
33
TCGv_i32 tmp = tcg_temp_new_i32();
67
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
34
- tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
68
"ddr-ram", &error_abort);
35
+ tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
69
object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
36
return tmp;
70
&error_fatal);
37
}
71
+ object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",
38
72
+ &error_fatal);
39
static void neon_store_reg(int reg, int pass, TCGv_i32 var)
73
74
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
75
76
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_instance_init(Object *obj)
77
{
40
{
78
XlnxZCU102 *s = EP108_MACHINE(obj);
41
- tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
79
42
+ tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
80
- /* EP108, we don't support setting secure */
43
tcg_temp_free_i32(var);
81
+ /* EP108, we don't support setting secure or virt */
82
s->secure = false;
83
+ s->virt = false;
84
}
44
}
85
45
86
static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
87
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
88
"Set on/off to enable/disable the ARM "
89
"Security Extensions (TrustZone)",
90
NULL);
91
+
92
+ /* Default to virt (EL2) being disabled */
93
+ s->virt = false;
94
+ object_property_add_bool(obj, "virtualization", zcu102_get_virt,
95
+ zcu102_set_virt, NULL);
96
+ object_property_set_description(obj, "virtualization",
97
+ "Set on/off to enable/disable emulating a "
98
+ "guest CPU which implements the ARM "
99
+ "Virtualization Extensions",
100
+ NULL);
101
}
102
103
static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
104
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/arm/xlnx-zynqmp.c
107
+++ b/hw/arm/xlnx-zynqmp.c
108
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
109
object_property_set_bool(OBJECT(&s->apu_cpu[i]),
110
s->secure, "has_el3", NULL);
111
object_property_set_bool(OBJECT(&s->apu_cpu[i]),
112
- false, "has_el2", NULL);
113
+ s->virt, "has_el2", NULL);
114
object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
115
"reset-cbar", &error_abort);
116
object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
117
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
118
static Property xlnx_zynqmp_props[] = {
119
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
120
DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
121
+ DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
122
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
123
DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
124
MemoryRegion *),
125
--
46
--
126
2.7.4
47
2.20.1
127
48
128
49
diff view generated by jsdifflib
1
From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Now we are able to retrieve the gsi from the INTx pin, let's
3
This seems a bit more readable than using offsetof CPU_DoubleU.
4
enable intx_to_irq routing. From that point on, irqfd becomes
5
usable along with INTx when assigning a PCIe device.
6
4
7
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
6
Message-id: 20201030022618.785675-5-richard.henderson@linaro.org
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Andrew Jones <drjones@redhat.com>
11
Tested-by: Feng Kan <fkan@apm.com>
12
Message-id: 1505296004-6798-4-git-send-email-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
9
---
15
hw/pci-host/gpex.c | 12 ++++++++++++
10
target/arm/translate.c | 13 ++++---------
16
1 file changed, 12 insertions(+)
11
1 file changed, 4 insertions(+), 9 deletions(-)
17
12
18
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/pci-host/gpex.c
15
--- a/target/arm/translate.c
21
+++ b/hw/pci-host/gpex.c
16
+++ b/target/arm/translate.c
22
@@ -XXX,XX +XXX,XX @@ int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
17
@@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size)
23
return 0;
18
return neon_full_reg_offset(reg) + ofs;
24
}
19
}
25
20
26
+static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
21
-static inline long vfp_reg_offset(bool dp, unsigned reg)
27
+{
22
+/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */
28
+ PCIINTxRoute route;
23
+static long vfp_reg_offset(bool dp, unsigned reg)
29
+ GPEXHost *s = opaque;
30
+
31
+ route.mode = PCI_INTX_ENABLED;
32
+ route.irq = s->irq_num[pin];
33
+
34
+ return route;
35
+}
36
+
37
static void gpex_host_realize(DeviceState *dev, Error **errp)
38
{
24
{
39
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
25
if (dp) {
40
@@ -XXX,XX +XXX,XX @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
26
- return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
41
&s->io_ioport, 0, 4, TYPE_PCIE_BUS);
27
+ return neon_element_offset(reg, 0, MO_64);
42
28
} else {
43
qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
29
- long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]);
44
+ pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
30
- if (reg & 1) {
45
qdev_init_nofail(DEVICE(&s->gpex_root));
31
- ofs += offsetof(CPU_DoubleU, l.upper);
32
- } else {
33
- ofs += offsetof(CPU_DoubleU, l.lower);
34
- }
35
- return ofs;
36
+ return neon_element_offset(reg >> 1, reg & 1, MO_32);
37
}
46
}
38
}
47
39
48
--
40
--
49
2.7.4
41
2.20.1
50
42
51
43
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add a machine level secure property. This defaults to false and can be
3
Model these off the aa64 read/write_vec_element functions.
4
set to true using this machine command line argument:
4
Use it within translate-neon.c.inc. The new functions do
5
-machine xlnx-zcu102,secure=on
5
not allocate or free temps, so this rearranges the calling
6
code a bit.
6
7
7
This follows what the ARM virt machine does.
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
9
Message-id: 20201030022618.785675-6-richard.henderson@linaro.org
9
This property only applies to the ZCU102 machine. The EP108 machine does
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
not have this property.
11
12
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
hw/arm/xlnx-zcu102.c | 32 ++++++++++++++++++++++++++++++++
13
target/arm/translate.c | 26 ++++
17
1 file changed, 32 insertions(+)
14
target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------
15
2 files changed, 183 insertions(+), 99 deletions(-)
18
16
19
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/xlnx-zcu102.c
19
--- a/target/arm/translate.c
22
+++ b/hw/arm/xlnx-zcu102.c
20
+++ b/target/arm/translate.c
23
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
21
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
24
22
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
25
XlnxZynqMPState soc;
23
}
26
MemoryRegion ddr_ram;
24
27
+
25
+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
28
+ bool secure;
29
} XlnxZCU102;
30
31
#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
32
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
33
34
static struct arm_boot_info xlnx_zcu102_binfo;
35
36
+static bool zcu102_get_secure(Object *obj, Error **errp)
37
+{
26
+{
38
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
27
+ long off = neon_element_offset(reg, ele, size);
39
+
28
+
40
+ return s->secure;
29
+ switch (size) {
30
+ case MO_32:
31
+ tcg_gen_ld_i32(dest, cpu_env, off);
32
+ break;
33
+ default:
34
+ g_assert_not_reached();
35
+ }
41
+}
36
+}
42
+
37
+
43
+static void zcu102_set_secure(Object *obj, bool value, Error **errp)
38
+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
44
+{
39
+{
45
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
40
+ long off = neon_element_offset(reg, ele, size);
46
+
41
+
47
+ s->secure = value;
42
+ switch (size) {
43
+ case MO_32:
44
+ tcg_gen_st_i32(src, cpu_env, off);
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
48
+}
49
+}
49
+
50
+
50
static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
51
static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
51
{
52
{
52
int i;
53
TCGv_ptr ret = tcg_temp_new_ptr();
53
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
54
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
54
55
index XXXXXXX..XXXXXXX 100644
55
object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram),
56
--- a/target/arm/translate-neon.c.inc
56
"ddr-ram", &error_abort);
57
+++ b/target/arm/translate-neon.c.inc
57
+ object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
58
@@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
58
+ &error_fatal);
59
* early. Since Q is 0 there are always just two passes, so instead
59
60
* of a complicated loop over each pass we just unroll.
60
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
61
*/
61
62
- tmp = neon_load_reg(a->vn, 0);
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)
63
- tmp2 = neon_load_reg(a->vn, 1);
63
64
+ tmp = tcg_temp_new_i32();
64
static void xlnx_ep108_machine_instance_init(Object *obj)
65
+ tmp2 = tcg_temp_new_i32();
66
+ tmp3 = tcg_temp_new_i32();
67
+
68
+ read_neon_element32(tmp, a->vn, 0, MO_32);
69
+ read_neon_element32(tmp2, a->vn, 1, MO_32);
70
fn(tmp, tmp, tmp2);
71
- tcg_temp_free_i32(tmp2);
72
73
- tmp3 = neon_load_reg(a->vm, 0);
74
- tmp2 = neon_load_reg(a->vm, 1);
75
+ read_neon_element32(tmp3, a->vm, 0, MO_32);
76
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
77
fn(tmp3, tmp3, tmp2);
78
- tcg_temp_free_i32(tmp2);
79
80
- neon_store_reg(a->vd, 0, tmp);
81
- neon_store_reg(a->vd, 1, tmp3);
82
+ write_neon_element32(tmp, a->vd, 0, MO_32);
83
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
84
+
85
+ tcg_temp_free_i32(tmp);
86
+ tcg_temp_free_i32(tmp2);
87
+ tcg_temp_free_i32(tmp3);
88
return true;
89
}
90
91
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
92
* 2-reg-and-shift operations, size < 3 case, where the
93
* helper needs to be passed cpu_env.
94
*/
95
- TCGv_i32 constimm;
96
+ TCGv_i32 constimm, tmp;
97
int pass;
98
99
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
100
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
101
* by immediate using the variable shift operations.
102
*/
103
constimm = tcg_const_i32(dup_const(a->size, a->shift));
104
+ tmp = tcg_temp_new_i32();
105
106
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
107
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
108
+ read_neon_element32(tmp, a->vm, pass, MO_32);
109
fn(tmp, cpu_env, tmp, constimm);
110
- neon_store_reg(a->vd, pass, tmp);
111
+ write_neon_element32(tmp, a->vd, pass, MO_32);
112
}
113
+ tcg_temp_free_i32(tmp);
114
tcg_temp_free_i32(constimm);
115
return true;
116
}
117
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
118
constimm = tcg_const_i64(-a->shift);
119
rm1 = tcg_temp_new_i64();
120
rm2 = tcg_temp_new_i64();
121
+ rd = tcg_temp_new_i32();
122
123
/* Load both inputs first to avoid potential overwrite if rm == rd */
124
neon_load_reg64(rm1, a->vm);
125
neon_load_reg64(rm2, a->vm + 1);
126
127
shiftfn(rm1, rm1, constimm);
128
- rd = tcg_temp_new_i32();
129
narrowfn(rd, cpu_env, rm1);
130
- neon_store_reg(a->vd, 0, rd);
131
+ write_neon_element32(rd, a->vd, 0, MO_32);
132
133
shiftfn(rm2, rm2, constimm);
134
- rd = tcg_temp_new_i32();
135
narrowfn(rd, cpu_env, rm2);
136
- neon_store_reg(a->vd, 1, rd);
137
+ write_neon_element32(rd, a->vd, 1, MO_32);
138
139
+ tcg_temp_free_i32(rd);
140
tcg_temp_free_i64(rm1);
141
tcg_temp_free_i64(rm2);
142
tcg_temp_free_i64(constimm);
143
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
144
constimm = tcg_const_i32(imm);
145
146
/* Load all inputs first to avoid potential overwrite */
147
- rm1 = neon_load_reg(a->vm, 0);
148
- rm2 = neon_load_reg(a->vm, 1);
149
- rm3 = neon_load_reg(a->vm + 1, 0);
150
- rm4 = neon_load_reg(a->vm + 1, 1);
151
+ rm1 = tcg_temp_new_i32();
152
+ rm2 = tcg_temp_new_i32();
153
+ rm3 = tcg_temp_new_i32();
154
+ rm4 = tcg_temp_new_i32();
155
+ read_neon_element32(rm1, a->vm, 0, MO_32);
156
+ read_neon_element32(rm2, a->vm, 1, MO_32);
157
+ read_neon_element32(rm3, a->vm, 2, MO_32);
158
+ read_neon_element32(rm4, a->vm, 3, MO_32);
159
rtmp = tcg_temp_new_i64();
160
161
shiftfn(rm1, rm1, constimm);
162
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
163
tcg_temp_free_i32(rm2);
164
165
narrowfn(rm1, cpu_env, rtmp);
166
- neon_store_reg(a->vd, 0, rm1);
167
+ write_neon_element32(rm1, a->vd, 0, MO_32);
168
+ tcg_temp_free_i32(rm1);
169
170
shiftfn(rm3, rm3, constimm);
171
shiftfn(rm4, rm4, constimm);
172
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
173
174
narrowfn(rm3, cpu_env, rtmp);
175
tcg_temp_free_i64(rtmp);
176
- neon_store_reg(a->vd, 1, rm3);
177
+ write_neon_element32(rm3, a->vd, 1, MO_32);
178
+ tcg_temp_free_i32(rm3);
179
return true;
180
}
181
182
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
183
widen_mask = dup_const(a->size + 1, widen_mask);
184
}
185
186
- rm0 = neon_load_reg(a->vm, 0);
187
- rm1 = neon_load_reg(a->vm, 1);
188
+ rm0 = tcg_temp_new_i32();
189
+ rm1 = tcg_temp_new_i32();
190
+ read_neon_element32(rm0, a->vm, 0, MO_32);
191
+ read_neon_element32(rm1, a->vm, 1, MO_32);
192
tmp = tcg_temp_new_i64();
193
194
widenfn(tmp, rm0);
195
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
196
if (src1_wide) {
197
neon_load_reg64(rn0_64, a->vn);
198
} else {
199
- TCGv_i32 tmp = neon_load_reg(a->vn, 0);
200
+ TCGv_i32 tmp = tcg_temp_new_i32();
201
+ read_neon_element32(tmp, a->vn, 0, MO_32);
202
widenfn(rn0_64, tmp);
203
tcg_temp_free_i32(tmp);
204
}
205
- rm = neon_load_reg(a->vm, 0);
206
+ rm = tcg_temp_new_i32();
207
+ read_neon_element32(rm, a->vm, 0, MO_32);
208
209
widenfn(rm_64, rm);
210
tcg_temp_free_i32(rm);
211
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
212
if (src1_wide) {
213
neon_load_reg64(rn1_64, a->vn + 1);
214
} else {
215
- TCGv_i32 tmp = neon_load_reg(a->vn, 1);
216
+ TCGv_i32 tmp = tcg_temp_new_i32();
217
+ read_neon_element32(tmp, a->vn, 1, MO_32);
218
widenfn(rn1_64, tmp);
219
tcg_temp_free_i32(tmp);
220
}
221
- rm = neon_load_reg(a->vm, 1);
222
+ rm = tcg_temp_new_i32();
223
+ read_neon_element32(rm, a->vm, 1, MO_32);
224
225
neon_store_reg64(rn0_64, a->vd);
226
227
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
228
229
narrowfn(rd1, rn_64);
230
231
- neon_store_reg(a->vd, 0, rd0);
232
- neon_store_reg(a->vd, 1, rd1);
233
+ write_neon_element32(rd0, a->vd, 0, MO_32);
234
+ write_neon_element32(rd1, a->vd, 1, MO_32);
235
236
+ tcg_temp_free_i32(rd0);
237
+ tcg_temp_free_i32(rd1);
238
tcg_temp_free_i64(rn_64);
239
tcg_temp_free_i64(rm_64);
240
241
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
242
rd0 = tcg_temp_new_i64();
243
rd1 = tcg_temp_new_i64();
244
245
- rn = neon_load_reg(a->vn, 0);
246
- rm = neon_load_reg(a->vm, 0);
247
+ rn = tcg_temp_new_i32();
248
+ rm = tcg_temp_new_i32();
249
+ read_neon_element32(rn, a->vn, 0, MO_32);
250
+ read_neon_element32(rm, a->vm, 0, MO_32);
251
opfn(rd0, rn, rm);
252
- tcg_temp_free_i32(rn);
253
- tcg_temp_free_i32(rm);
254
255
- rn = neon_load_reg(a->vn, 1);
256
- rm = neon_load_reg(a->vm, 1);
257
+ read_neon_element32(rn, a->vn, 1, MO_32);
258
+ read_neon_element32(rm, a->vm, 1, MO_32);
259
opfn(rd1, rn, rm);
260
tcg_temp_free_i32(rn);
261
tcg_temp_free_i32(rm);
262
@@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var)
263
264
static inline TCGv_i32 neon_get_scalar(int size, int reg)
65
{
265
{
66
+ XlnxZCU102 *s = EP108_MACHINE(obj);
266
- TCGv_i32 tmp;
67
+
267
- if (size == 1) {
68
+ /* EP108, we don't support setting secure */
268
- tmp = neon_load_reg(reg & 7, reg >> 4);
69
+ s->secure = false;
269
+ TCGv_i32 tmp = tcg_temp_new_i32();
70
}
270
+ if (size == MO_16) {
71
271
+ read_neon_element32(tmp, reg & 7, reg >> 4, MO_32);
72
static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
272
if (reg & 8) {
73
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
273
gen_neon_dup_high16(tmp);
74
274
} else {
75
static void xlnx_zcu102_machine_instance_init(Object *obj)
275
gen_neon_dup_low16(tmp);
276
}
277
} else {
278
- tmp = neon_load_reg(reg & 15, reg >> 4);
279
+ read_neon_element32(tmp, reg & 15, reg >> 4, MO_32);
280
}
281
return tmp;
282
}
283
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
284
* perform an accumulation operation of that result into the
285
* destination.
286
*/
287
- TCGv_i32 scalar;
288
+ TCGv_i32 scalar, tmp;
289
int pass;
290
291
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
292
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
293
}
294
295
scalar = neon_get_scalar(a->size, a->vm);
296
+ tmp = tcg_temp_new_i32();
297
298
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
299
- TCGv_i32 tmp = neon_load_reg(a->vn, pass);
300
+ read_neon_element32(tmp, a->vn, pass, MO_32);
301
opfn(tmp, tmp, scalar);
302
if (accfn) {
303
- TCGv_i32 rd = neon_load_reg(a->vd, pass);
304
+ TCGv_i32 rd = tcg_temp_new_i32();
305
+ read_neon_element32(rd, a->vd, pass, MO_32);
306
accfn(tmp, rd, tmp);
307
tcg_temp_free_i32(rd);
308
}
309
- neon_store_reg(a->vd, pass, tmp);
310
+ write_neon_element32(tmp, a->vd, pass, MO_32);
311
}
312
+ tcg_temp_free_i32(tmp);
313
tcg_temp_free_i32(scalar);
314
return true;
315
}
316
@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
317
* performs a kind of fused op-then-accumulate using a helper
318
* function that takes all of rd, rn and the scalar at once.
319
*/
320
- TCGv_i32 scalar;
321
+ TCGv_i32 scalar, rn, rd;
322
int pass;
323
324
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
325
@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
326
}
327
328
scalar = neon_get_scalar(a->size, a->vm);
329
+ rn = tcg_temp_new_i32();
330
+ rd = tcg_temp_new_i32();
331
332
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
333
- TCGv_i32 rn = neon_load_reg(a->vn, pass);
334
- TCGv_i32 rd = neon_load_reg(a->vd, pass);
335
+ read_neon_element32(rn, a->vn, pass, MO_32);
336
+ read_neon_element32(rd, a->vd, pass, MO_32);
337
opfn(rd, cpu_env, rn, scalar, rd);
338
- tcg_temp_free_i32(rn);
339
- neon_store_reg(a->vd, pass, rd);
340
+ write_neon_element32(rd, a->vd, pass, MO_32);
341
}
342
+ tcg_temp_free_i32(rn);
343
+ tcg_temp_free_i32(rd);
344
tcg_temp_free_i32(scalar);
345
346
return true;
347
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
348
scalar = neon_get_scalar(a->size, a->vm);
349
350
/* Load all inputs before writing any outputs, in case of overlap */
351
- rn = neon_load_reg(a->vn, 0);
352
+ rn = tcg_temp_new_i32();
353
+ read_neon_element32(rn, a->vn, 0, MO_32);
354
rn0_64 = tcg_temp_new_i64();
355
opfn(rn0_64, rn, scalar);
356
- tcg_temp_free_i32(rn);
357
358
- rn = neon_load_reg(a->vn, 1);
359
+ read_neon_element32(rn, a->vn, 1, MO_32);
360
rn1_64 = tcg_temp_new_i64();
361
opfn(rn1_64, rn, scalar);
362
tcg_temp_free_i32(rn);
363
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
364
return false;
365
}
366
n <<= 3;
367
+ tmp = tcg_temp_new_i32();
368
if (a->op) {
369
- tmp = neon_load_reg(a->vd, 0);
370
+ read_neon_element32(tmp, a->vd, 0, MO_32);
371
} else {
372
- tmp = tcg_temp_new_i32();
373
tcg_gen_movi_i32(tmp, 0);
374
}
375
- tmp2 = neon_load_reg(a->vm, 0);
376
+ tmp2 = tcg_temp_new_i32();
377
+ read_neon_element32(tmp2, a->vm, 0, MO_32);
378
ptr1 = vfp_reg_ptr(true, a->vn);
379
tmp4 = tcg_const_i32(n);
380
gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
381
- tcg_temp_free_i32(tmp);
382
+
383
if (a->op) {
384
- tmp = neon_load_reg(a->vd, 1);
385
+ read_neon_element32(tmp, a->vd, 1, MO_32);
386
} else {
387
- tmp = tcg_temp_new_i32();
388
tcg_gen_movi_i32(tmp, 0);
389
}
390
- tmp3 = neon_load_reg(a->vm, 1);
391
+ tmp3 = tcg_temp_new_i32();
392
+ read_neon_element32(tmp3, a->vm, 1, MO_32);
393
gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
394
+ tcg_temp_free_i32(tmp);
395
tcg_temp_free_i32(tmp4);
396
tcg_temp_free_ptr(ptr1);
397
- neon_store_reg(a->vd, 0, tmp2);
398
- neon_store_reg(a->vd, 1, tmp3);
399
- tcg_temp_free_i32(tmp);
400
+
401
+ write_neon_element32(tmp2, a->vd, 0, MO_32);
402
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
403
+ tcg_temp_free_i32(tmp2);
404
+ tcg_temp_free_i32(tmp3);
405
return true;
406
}
407
408
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
409
static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
76
{
410
{
77
+ XlnxZCU102 *s = ZCU102_MACHINE(obj);
411
int pass, half;
78
+
412
+ TCGv_i32 tmp[2];
79
+ /* Default to secure mode being disabled */
413
80
+ s->secure = false;
414
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
81
+ object_property_add_bool(obj, "secure", zcu102_get_secure,
415
return false;
82
+ zcu102_set_secure, NULL);
416
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
83
+ object_property_set_description(obj, "secure",
417
return true;
84
+ "Set on/off to enable/disable the ARM "
418
}
85
+ "Security Extensions (TrustZone)",
419
86
+ NULL);
420
- for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
87
}
421
- TCGv_i32 tmp[2];
88
422
+ tmp[0] = tcg_temp_new_i32();
89
static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
423
+ tmp[1] = tcg_temp_new_i32();
424
425
+ for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
426
for (half = 0; half < 2; half++) {
427
- tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
428
+ read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32);
429
switch (a->size) {
430
case 0:
431
tcg_gen_bswap32_i32(tmp[half], tmp[half]);
432
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
433
g_assert_not_reached();
434
}
435
}
436
- neon_store_reg(a->vd, pass * 2, tmp[1]);
437
- neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
438
+ write_neon_element32(tmp[1], a->vd, pass * 2, MO_32);
439
+ write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32);
440
}
441
+
442
+ tcg_temp_free_i32(tmp[0]);
443
+ tcg_temp_free_i32(tmp[1]);
444
return true;
445
}
446
447
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
448
rm0_64 = tcg_temp_new_i64();
449
rm1_64 = tcg_temp_new_i64();
450
rd_64 = tcg_temp_new_i64();
451
- tmp = neon_load_reg(a->vm, pass * 2);
452
+
453
+ tmp = tcg_temp_new_i32();
454
+ read_neon_element32(tmp, a->vm, pass * 2, MO_32);
455
widenfn(rm0_64, tmp);
456
- tcg_temp_free_i32(tmp);
457
- tmp = neon_load_reg(a->vm, pass * 2 + 1);
458
+ read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32);
459
widenfn(rm1_64, tmp);
460
tcg_temp_free_i32(tmp);
461
+
462
opfn(rd_64, rm0_64, rm1_64);
463
tcg_temp_free_i64(rm0_64);
464
tcg_temp_free_i64(rm1_64);
465
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
466
narrowfn(rd0, cpu_env, rm);
467
neon_load_reg64(rm, a->vm + 1);
468
narrowfn(rd1, cpu_env, rm);
469
- neon_store_reg(a->vd, 0, rd0);
470
- neon_store_reg(a->vd, 1, rd1);
471
+ write_neon_element32(rd0, a->vd, 0, MO_32);
472
+ write_neon_element32(rd1, a->vd, 1, MO_32);
473
+ tcg_temp_free_i32(rd0);
474
+ tcg_temp_free_i32(rd1);
475
tcg_temp_free_i64(rm);
476
return true;
477
}
478
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
479
}
480
481
rd = tcg_temp_new_i64();
482
+ rm0 = tcg_temp_new_i32();
483
+ rm1 = tcg_temp_new_i32();
484
485
- rm0 = neon_load_reg(a->vm, 0);
486
- rm1 = neon_load_reg(a->vm, 1);
487
+ read_neon_element32(rm0, a->vm, 0, MO_32);
488
+ read_neon_element32(rm1, a->vm, 1, MO_32);
489
490
widenfn(rd, rm0);
491
tcg_gen_shli_i64(rd, rd, 8 << a->size);
492
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
493
494
fpst = fpstatus_ptr(FPST_STD);
495
ahp = get_ahp_flag();
496
- tmp = neon_load_reg(a->vm, 0);
497
+ tmp = tcg_temp_new_i32();
498
+ read_neon_element32(tmp, a->vm, 0, MO_32);
499
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
500
- tmp2 = neon_load_reg(a->vm, 1);
501
+ tmp2 = tcg_temp_new_i32();
502
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
503
gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
504
tcg_gen_shli_i32(tmp2, tmp2, 16);
505
tcg_gen_or_i32(tmp2, tmp2, tmp);
506
- tcg_temp_free_i32(tmp);
507
- tmp = neon_load_reg(a->vm, 2);
508
+ read_neon_element32(tmp, a->vm, 2, MO_32);
509
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
510
- tmp3 = neon_load_reg(a->vm, 3);
511
- neon_store_reg(a->vd, 0, tmp2);
512
+ tmp3 = tcg_temp_new_i32();
513
+ read_neon_element32(tmp3, a->vm, 3, MO_32);
514
+ write_neon_element32(tmp2, a->vd, 0, MO_32);
515
+ tcg_temp_free_i32(tmp2);
516
gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
517
tcg_gen_shli_i32(tmp3, tmp3, 16);
518
tcg_gen_or_i32(tmp3, tmp3, tmp);
519
- neon_store_reg(a->vd, 1, tmp3);
520
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
521
+ tcg_temp_free_i32(tmp3);
522
tcg_temp_free_i32(tmp);
523
tcg_temp_free_i32(ahp);
524
tcg_temp_free_ptr(fpst);
525
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
526
fpst = fpstatus_ptr(FPST_STD);
527
ahp = get_ahp_flag();
528
tmp3 = tcg_temp_new_i32();
529
- tmp = neon_load_reg(a->vm, 0);
530
- tmp2 = neon_load_reg(a->vm, 1);
531
+ tmp2 = tcg_temp_new_i32();
532
+ tmp = tcg_temp_new_i32();
533
+ read_neon_element32(tmp, a->vm, 0, MO_32);
534
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
535
tcg_gen_ext16u_i32(tmp3, tmp);
536
gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
537
- neon_store_reg(a->vd, 0, tmp3);
538
+ write_neon_element32(tmp3, a->vd, 0, MO_32);
539
tcg_gen_shri_i32(tmp, tmp, 16);
540
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
541
- neon_store_reg(a->vd, 1, tmp);
542
- tmp3 = tcg_temp_new_i32();
543
+ write_neon_element32(tmp, a->vd, 1, MO_32);
544
+ tcg_temp_free_i32(tmp);
545
tcg_gen_ext16u_i32(tmp3, tmp2);
546
gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
547
- neon_store_reg(a->vd, 2, tmp3);
548
+ write_neon_element32(tmp3, a->vd, 2, MO_32);
549
+ tcg_temp_free_i32(tmp3);
550
tcg_gen_shri_i32(tmp2, tmp2, 16);
551
gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
552
- neon_store_reg(a->vd, 3, tmp2);
553
+ write_neon_element32(tmp2, a->vd, 3, MO_32);
554
+ tcg_temp_free_i32(tmp2);
555
tcg_temp_free_i32(ahp);
556
tcg_temp_free_ptr(fpst);
557
558
@@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
559
560
static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
561
{
562
+ TCGv_i32 tmp;
563
int pass;
564
565
/* Handle a 2-reg-misc operation by iterating 32 bits at a time */
566
@@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
567
return true;
568
}
569
570
+ tmp = tcg_temp_new_i32();
571
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
572
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
573
+ read_neon_element32(tmp, a->vm, pass, MO_32);
574
fn(tmp, tmp);
575
- neon_store_reg(a->vd, pass, tmp);
576
+ write_neon_element32(tmp, a->vd, pass, MO_32);
577
}
578
+ tcg_temp_free_i32(tmp);
579
580
return true;
581
}
582
@@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a)
583
return true;
584
}
585
586
- if (a->size == 2) {
587
+ tmp = tcg_temp_new_i32();
588
+ tmp2 = tcg_temp_new_i32();
589
+ if (a->size == MO_32) {
590
for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
591
- tmp = neon_load_reg(a->vm, pass);
592
- tmp2 = neon_load_reg(a->vd, pass + 1);
593
- neon_store_reg(a->vm, pass, tmp2);
594
- neon_store_reg(a->vd, pass + 1, tmp);
595
+ read_neon_element32(tmp, a->vm, pass, MO_32);
596
+ read_neon_element32(tmp2, a->vd, pass + 1, MO_32);
597
+ write_neon_element32(tmp2, a->vm, pass, MO_32);
598
+ write_neon_element32(tmp, a->vd, pass + 1, MO_32);
599
}
600
} else {
601
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
602
- tmp = neon_load_reg(a->vm, pass);
603
- tmp2 = neon_load_reg(a->vd, pass);
604
- if (a->size == 0) {
605
+ read_neon_element32(tmp, a->vm, pass, MO_32);
606
+ read_neon_element32(tmp2, a->vd, pass, MO_32);
607
+ if (a->size == MO_8) {
608
gen_neon_trn_u8(tmp, tmp2);
609
} else {
610
gen_neon_trn_u16(tmp, tmp2);
611
}
612
- neon_store_reg(a->vm, pass, tmp2);
613
- neon_store_reg(a->vd, pass, tmp);
614
+ write_neon_element32(tmp2, a->vm, pass, MO_32);
615
+ write_neon_element32(tmp, a->vd, pass, MO_32);
616
}
617
}
618
+ tcg_temp_free_i32(tmp);
619
+ tcg_temp_free_i32(tmp2);
620
return true;
621
}
90
--
622
--
91
2.7.4
623
2.20.1
92
624
93
625
diff view generated by jsdifflib
New patch
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
We can then use this to improve VMOV (scalar to gp) and
4
VMOV (gp to scalar) so that we simply perform the memory
5
operation that we wanted, rather than inserting or
6
extracting from a 32-bit quantity.
7
8
These were the last uses of neon_load/store_reg, so remove them.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20201030022618.785675-7-richard.henderson@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/translate.c | 50 +++++++++++++-----------
16
target/arm/translate-vfp.c.inc | 71 +++++-----------------------------
17
2 files changed, 37 insertions(+), 84 deletions(-)
18
19
diff --git a/target/arm/translate.c b/target/arm/translate.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate.c
22
+++ b/target/arm/translate.c
23
@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
24
* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
25
* where 0 is the least significant end of the register.
26
*/
27
-static long neon_element_offset(int reg, int element, MemOp size)
28
+static long neon_element_offset(int reg, int element, MemOp memop)
29
{
30
- int element_size = 1 << size;
31
+ int element_size = 1 << (memop & MO_SIZE);
32
int ofs = element * element_size;
33
#ifdef HOST_WORDS_BIGENDIAN
34
/*
35
@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
36
}
37
}
38
39
-static TCGv_i32 neon_load_reg(int reg, int pass)
40
-{
41
- TCGv_i32 tmp = tcg_temp_new_i32();
42
- tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
43
- return tmp;
44
-}
45
-
46
-static void neon_store_reg(int reg, int pass, TCGv_i32 var)
47
-{
48
- tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
49
- tcg_temp_free_i32(var);
50
-}
51
-
52
static inline void neon_load_reg64(TCGv_i64 var, int reg)
53
{
54
tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
55
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
56
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
57
}
58
59
-static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
60
+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
61
{
62
- long off = neon_element_offset(reg, ele, size);
63
+ long off = neon_element_offset(reg, ele, memop);
64
65
- switch (size) {
66
- case MO_32:
67
+ switch (memop) {
68
+ case MO_SB:
69
+ tcg_gen_ld8s_i32(dest, cpu_env, off);
70
+ break;
71
+ case MO_UB:
72
+ tcg_gen_ld8u_i32(dest, cpu_env, off);
73
+ break;
74
+ case MO_SW:
75
+ tcg_gen_ld16s_i32(dest, cpu_env, off);
76
+ break;
77
+ case MO_UW:
78
+ tcg_gen_ld16u_i32(dest, cpu_env, off);
79
+ break;
80
+ case MO_UL:
81
+ case MO_SL:
82
tcg_gen_ld_i32(dest, cpu_env, off);
83
break;
84
default:
85
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
86
}
87
}
88
89
-static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
90
+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
91
{
92
- long off = neon_element_offset(reg, ele, size);
93
+ long off = neon_element_offset(reg, ele, memop);
94
95
- switch (size) {
96
+ switch (memop) {
97
+ case MO_8:
98
+ tcg_gen_st8_i32(src, cpu_env, off);
99
+ break;
100
+ case MO_16:
101
+ tcg_gen_st16_i32(src, cpu_env, off);
102
+ break;
103
case MO_32:
104
tcg_gen_st_i32(src, cpu_env, off);
105
break;
106
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-vfp.c.inc
109
+++ b/target/arm/translate-vfp.c.inc
110
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
111
{
112
/* VMOV scalar to general purpose register */
113
TCGv_i32 tmp;
114
- int pass;
115
- uint32_t offset;
116
117
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
118
- if (a->size == 2
119
+ /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
120
+ if (a->size == MO_32
121
? !dc_isar_feature(aa32_fpsp_v2, s)
122
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
123
return false;
124
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
125
return false;
126
}
127
128
- offset = a->index << a->size;
129
- pass = extract32(offset, 2, 1);
130
- offset = extract32(offset, 0, 2) * 8;
131
-
132
if (!vfp_access_check(s)) {
133
return true;
134
}
135
136
- tmp = neon_load_reg(a->vn, pass);
137
- switch (a->size) {
138
- case 0:
139
- if (offset) {
140
- tcg_gen_shri_i32(tmp, tmp, offset);
141
- }
142
- if (a->u) {
143
- gen_uxtb(tmp);
144
- } else {
145
- gen_sxtb(tmp);
146
- }
147
- break;
148
- case 1:
149
- if (a->u) {
150
- if (offset) {
151
- tcg_gen_shri_i32(tmp, tmp, 16);
152
- } else {
153
- gen_uxth(tmp);
154
- }
155
- } else {
156
- if (offset) {
157
- tcg_gen_sari_i32(tmp, tmp, 16);
158
- } else {
159
- gen_sxth(tmp);
160
- }
161
- }
162
- break;
163
- case 2:
164
- break;
165
- }
166
+ tmp = tcg_temp_new_i32();
167
+ read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN));
168
store_reg(s, a->rt, tmp);
169
170
return true;
171
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
172
static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
173
{
174
/* VMOV general purpose register to scalar */
175
- TCGv_i32 tmp, tmp2;
176
- int pass;
177
- uint32_t offset;
178
+ TCGv_i32 tmp;
179
180
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
181
- if (a->size == 2
182
+ /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
183
+ if (a->size == MO_32
184
? !dc_isar_feature(aa32_fpsp_v2, s)
185
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
186
return false;
187
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
188
return false;
189
}
190
191
- offset = a->index << a->size;
192
- pass = extract32(offset, 2, 1);
193
- offset = extract32(offset, 0, 2) * 8;
194
-
195
if (!vfp_access_check(s)) {
196
return true;
197
}
198
199
tmp = load_reg(s, a->rt);
200
- switch (a->size) {
201
- case 0:
202
- tmp2 = neon_load_reg(a->vn, pass);
203
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
204
- tcg_temp_free_i32(tmp2);
205
- break;
206
- case 1:
207
- tmp2 = neon_load_reg(a->vn, pass);
208
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
209
- tcg_temp_free_i32(tmp2);
210
- break;
211
- case 2:
212
- break;
213
- }
214
- neon_store_reg(a->vn, pass, tmp);
215
+ write_neon_element32(tmp, a->vn, a->index, a->size);
216
+ tcg_temp_free_i32(tmp);
217
218
return true;
219
}
220
--
221
2.20.1
222
223
diff view generated by jsdifflib
1
In the v7M and v8M ARM ARM, the magic exception return values are
1
From: Richard Henderson <richard.henderson@linaro.org>
2
referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_*
3
constants to define bits within them. Rename the 'type' variable
4
which holds the exception return value in do_v7m_exception_exit()
5
to excret, making it clearer that it does hold an EXC_RETURN value.
6
2
3
The only uses of this function are for loading VFP
4
single-precision values, and nothing to do with NEON.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201030022618.785675-8-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1505137930-13255-8-git-send-email-peter.maydell@linaro.org
12
---
10
---
13
target/arm/helper.c | 23 ++++++++++++-----------
11
target/arm/translate.c | 4 +-
14
1 file changed, 12 insertions(+), 11 deletions(-)
12
target/arm/translate-vfp.c.inc | 184 ++++++++++++++++-----------------
13
2 files changed, 94 insertions(+), 94 deletions(-)
15
14
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
17
--- a/target/arm/translate.c
19
+++ b/target/arm/helper.c
18
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ static void v7m_push_stack(ARMCPU *cpu)
19
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg)
21
static void do_v7m_exception_exit(ARMCPU *cpu)
20
tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
21
}
22
23
-static inline void neon_load_reg32(TCGv_i32 var, int reg)
24
+static inline void vfp_load_reg32(TCGv_i32 var, int reg)
22
{
25
{
23
CPUARMState *env = &cpu->env;
26
tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
24
- uint32_t type;
27
}
25
+ uint32_t excret;
28
26
uint32_t xpsr;
29
-static inline void neon_store_reg32(TCGv_i32 var, int reg)
27
bool ufault = false;
30
+static inline void vfp_store_reg32(TCGv_i32 var, int reg)
28
bool return_to_sp_process = false;
31
{
29
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
32
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
30
* the target value up between env->regs[15] and env->thumb in
33
}
31
* gen_bx(). Reconstitute it.
34
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
32
*/
35
index XXXXXXX..XXXXXXX 100644
33
- type = env->regs[15];
36
--- a/target/arm/translate-vfp.c.inc
34
+ excret = env->regs[15];
37
+++ b/target/arm/translate-vfp.c.inc
35
if (env->thumb) {
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
36
- type |= 1;
39
frn = tcg_temp_new_i32();
37
+ excret |= 1;
40
frm = tcg_temp_new_i32();
38
}
41
dest = tcg_temp_new_i32();
39
42
- neon_load_reg32(frn, rn);
40
qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32
43
- neon_load_reg32(frm, rm);
41
" previous exception %d\n",
44
+ vfp_load_reg32(frn, rn);
42
- type, env->v7m.exception);
45
+ vfp_load_reg32(frm, rm);
43
+ excret, env->v7m.exception);
46
switch (a->cc) {
44
47
case 0: /* eq: Z */
45
- if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
48
tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
46
+ if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
49
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
47
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
50
if (sz == 1) {
48
- "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);
51
tcg_gen_andi_i32(dest, dest, 0xffff);
49
+ "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n",
52
}
50
+ excret);
53
- neon_store_reg32(dest, rd);
51
}
54
+ vfp_store_reg32(dest, rd);
52
55
tcg_temp_free_i32(frn);
53
if (env->v7m.exception != ARMV7M_EXCP_NMI) {
56
tcg_temp_free_i32(frm);
54
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
57
tcg_temp_free_i32(dest);
55
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
58
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
56
*/
59
TCGv_i32 tcg_res;
57
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
60
tcg_op = tcg_temp_new_i32();
58
- int es = type & R_V7M_EXCRET_ES_MASK;
61
tcg_res = tcg_temp_new_i32();
59
+ int es = excret & R_V7M_EXCRET_ES_MASK;
62
- neon_load_reg32(tcg_op, rm);
60
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
63
+ vfp_load_reg32(tcg_op, rm);
61
env->v7m.faultmask[es] = 0;
64
if (sz == 1) {
65
gen_helper_rinth(tcg_res, tcg_op, fpst);
66
} else {
67
gen_helper_rints(tcg_res, tcg_op, fpst);
68
}
69
- neon_store_reg32(tcg_res, rd);
70
+ vfp_store_reg32(tcg_res, rd);
71
tcg_temp_free_i32(tcg_op);
72
tcg_temp_free_i32(tcg_res);
73
}
74
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
75
gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
76
}
77
tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
78
- neon_store_reg32(tcg_tmp, rd);
79
+ vfp_store_reg32(tcg_tmp, rd);
80
tcg_temp_free_i32(tcg_tmp);
81
tcg_temp_free_i64(tcg_res);
82
tcg_temp_free_i64(tcg_double);
83
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
84
TCGv_i32 tcg_single, tcg_res;
85
tcg_single = tcg_temp_new_i32();
86
tcg_res = tcg_temp_new_i32();
87
- neon_load_reg32(tcg_single, rm);
88
+ vfp_load_reg32(tcg_single, rm);
89
if (sz == 1) {
90
if (is_signed) {
91
gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst);
92
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
93
gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
62
}
94
}
63
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
95
}
96
- neon_store_reg32(tcg_res, rd);
97
+ vfp_store_reg32(tcg_res, rd);
98
tcg_temp_free_i32(tcg_res);
99
tcg_temp_free_i32(tcg_single);
100
}
101
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
102
if (a->l) {
103
/* VFP to general purpose register */
104
tmp = tcg_temp_new_i32();
105
- neon_load_reg32(tmp, a->vn);
106
+ vfp_load_reg32(tmp, a->vn);
107
tcg_gen_andi_i32(tmp, tmp, 0xffff);
108
store_reg(s, a->rt, tmp);
109
} else {
110
/* general purpose register to VFP */
111
tmp = load_reg(s, a->rt);
112
tcg_gen_andi_i32(tmp, tmp, 0xffff);
113
- neon_store_reg32(tmp, a->vn);
114
+ vfp_store_reg32(tmp, a->vn);
115
tcg_temp_free_i32(tmp);
116
}
117
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
119
if (a->l) {
120
/* VFP to general purpose register */
121
tmp = tcg_temp_new_i32();
122
- neon_load_reg32(tmp, a->vn);
123
+ vfp_load_reg32(tmp, a->vn);
124
if (a->rt == 15) {
125
/* Set the 4 flag bits in the CPSR. */
126
gen_set_nzcv(tmp);
127
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
128
} else {
129
/* general purpose register to VFP */
130
tmp = load_reg(s, a->rt);
131
- neon_store_reg32(tmp, a->vn);
132
+ vfp_store_reg32(tmp, a->vn);
133
tcg_temp_free_i32(tmp);
134
}
135
136
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
137
if (a->op) {
138
/* fpreg to gpreg */
139
tmp = tcg_temp_new_i32();
140
- neon_load_reg32(tmp, a->vm);
141
+ vfp_load_reg32(tmp, a->vm);
142
store_reg(s, a->rt, tmp);
143
tmp = tcg_temp_new_i32();
144
- neon_load_reg32(tmp, a->vm + 1);
145
+ vfp_load_reg32(tmp, a->vm + 1);
146
store_reg(s, a->rt2, tmp);
147
} else {
148
/* gpreg to fpreg */
149
tmp = load_reg(s, a->rt);
150
- neon_store_reg32(tmp, a->vm);
151
+ vfp_store_reg32(tmp, a->vm);
152
tcg_temp_free_i32(tmp);
153
tmp = load_reg(s, a->rt2);
154
- neon_store_reg32(tmp, a->vm + 1);
155
+ vfp_store_reg32(tmp, a->vm + 1);
156
tcg_temp_free_i32(tmp);
157
}
158
159
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
160
if (a->op) {
161
/* fpreg to gpreg */
162
tmp = tcg_temp_new_i32();
163
- neon_load_reg32(tmp, a->vm * 2);
164
+ vfp_load_reg32(tmp, a->vm * 2);
165
store_reg(s, a->rt, tmp);
166
tmp = tcg_temp_new_i32();
167
- neon_load_reg32(tmp, a->vm * 2 + 1);
168
+ vfp_load_reg32(tmp, a->vm * 2 + 1);
169
store_reg(s, a->rt2, tmp);
170
} else {
171
/* gpreg to fpreg */
172
tmp = load_reg(s, a->rt);
173
- neon_store_reg32(tmp, a->vm * 2);
174
+ vfp_store_reg32(tmp, a->vm * 2);
175
tcg_temp_free_i32(tmp);
176
tmp = load_reg(s, a->rt2);
177
- neon_store_reg32(tmp, a->vm * 2 + 1);
178
+ vfp_store_reg32(tmp, a->vm * 2 + 1);
179
tcg_temp_free_i32(tmp);
180
}
181
182
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a)
183
tmp = tcg_temp_new_i32();
184
if (a->l) {
185
gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
186
- neon_store_reg32(tmp, a->vd);
187
+ vfp_store_reg32(tmp, a->vd);
188
} else {
189
- neon_load_reg32(tmp, a->vd);
190
+ vfp_load_reg32(tmp, a->vd);
191
gen_aa32_st16(s, tmp, addr, get_mem_index(s));
192
}
193
tcg_temp_free_i32(tmp);
194
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
195
tmp = tcg_temp_new_i32();
196
if (a->l) {
197
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
198
- neon_store_reg32(tmp, a->vd);
199
+ vfp_store_reg32(tmp, a->vd);
200
} else {
201
- neon_load_reg32(tmp, a->vd);
202
+ vfp_load_reg32(tmp, a->vd);
203
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
204
}
205
tcg_temp_free_i32(tmp);
206
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
207
if (a->l) {
208
/* load */
209
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
210
- neon_store_reg32(tmp, a->vd + i);
211
+ vfp_store_reg32(tmp, a->vd + i);
212
} else {
213
/* store */
214
- neon_load_reg32(tmp, a->vd + i);
215
+ vfp_load_reg32(tmp, a->vd + i);
216
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
217
}
218
tcg_gen_addi_i32(addr, addr, offset);
219
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
220
fd = tcg_temp_new_i32();
221
fpst = fpstatus_ptr(FPST_FPCR);
222
223
- neon_load_reg32(f0, vn);
224
- neon_load_reg32(f1, vm);
225
+ vfp_load_reg32(f0, vn);
226
+ vfp_load_reg32(f1, vm);
227
228
for (;;) {
229
if (reads_vd) {
230
- neon_load_reg32(fd, vd);
231
+ vfp_load_reg32(fd, vd);
232
}
233
fn(fd, f0, f1, fpst);
234
- neon_store_reg32(fd, vd);
235
+ vfp_store_reg32(fd, vd);
236
237
if (veclen == 0) {
238
break;
239
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
240
veclen--;
241
vd = vfp_advance_sreg(vd, delta_d);
242
vn = vfp_advance_sreg(vn, delta_d);
243
- neon_load_reg32(f0, vn);
244
+ vfp_load_reg32(f0, vn);
245
if (delta_m) {
246
vm = vfp_advance_sreg(vm, delta_m);
247
- neon_load_reg32(f1, vm);
248
+ vfp_load_reg32(f1, vm);
249
}
250
}
251
252
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn,
253
fd = tcg_temp_new_i32();
254
fpst = fpstatus_ptr(FPST_FPCR_F16);
255
256
- neon_load_reg32(f0, vn);
257
- neon_load_reg32(f1, vm);
258
+ vfp_load_reg32(f0, vn);
259
+ vfp_load_reg32(f1, vm);
260
261
if (reads_vd) {
262
- neon_load_reg32(fd, vd);
263
+ vfp_load_reg32(fd, vd);
264
}
265
fn(fd, f0, f1, fpst);
266
- neon_store_reg32(fd, vd);
267
+ vfp_store_reg32(fd, vd);
268
269
tcg_temp_free_i32(f0);
270
tcg_temp_free_i32(f1);
271
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
272
f0 = tcg_temp_new_i32();
273
fd = tcg_temp_new_i32();
274
275
- neon_load_reg32(f0, vm);
276
+ vfp_load_reg32(f0, vm);
277
278
for (;;) {
279
fn(fd, f0);
280
- neon_store_reg32(fd, vd);
281
+ vfp_store_reg32(fd, vd);
282
283
if (veclen == 0) {
284
break;
285
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
286
/* single source one-many */
287
while (veclen--) {
288
vd = vfp_advance_sreg(vd, delta_d);
289
- neon_store_reg32(fd, vd);
290
+ vfp_store_reg32(fd, vd);
291
}
292
break;
293
}
294
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
295
veclen--;
296
vd = vfp_advance_sreg(vd, delta_d);
297
vm = vfp_advance_sreg(vm, delta_m);
298
- neon_load_reg32(f0, vm);
299
+ vfp_load_reg32(f0, vm);
300
}
301
302
tcg_temp_free_i32(f0);
303
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
304
}
305
306
f0 = tcg_temp_new_i32();
307
- neon_load_reg32(f0, vm);
308
+ vfp_load_reg32(f0, vm);
309
fn(f0, f0);
310
- neon_store_reg32(f0, vd);
311
+ vfp_store_reg32(f0, vd);
312
tcg_temp_free_i32(f0);
313
314
return true;
315
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
316
vm = tcg_temp_new_i32();
317
vd = tcg_temp_new_i32();
318
319
- neon_load_reg32(vn, a->vn);
320
- neon_load_reg32(vm, a->vm);
321
+ vfp_load_reg32(vn, a->vn);
322
+ vfp_load_reg32(vm, a->vm);
323
if (neg_n) {
324
/* VFNMS, VFMS */
325
gen_helper_vfp_negh(vn, vn);
326
}
327
- neon_load_reg32(vd, a->vd);
328
+ vfp_load_reg32(vd, a->vd);
329
if (neg_d) {
330
/* VFNMA, VFNMS */
331
gen_helper_vfp_negh(vd, vd);
332
}
333
fpst = fpstatus_ptr(FPST_FPCR_F16);
334
gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst);
335
- neon_store_reg32(vd, a->vd);
336
+ vfp_store_reg32(vd, a->vd);
337
338
tcg_temp_free_ptr(fpst);
339
tcg_temp_free_i32(vn);
340
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
341
vm = tcg_temp_new_i32();
342
vd = tcg_temp_new_i32();
343
344
- neon_load_reg32(vn, a->vn);
345
- neon_load_reg32(vm, a->vm);
346
+ vfp_load_reg32(vn, a->vn);
347
+ vfp_load_reg32(vm, a->vm);
348
if (neg_n) {
349
/* VFNMS, VFMS */
350
gen_helper_vfp_negs(vn, vn);
351
}
352
- neon_load_reg32(vd, a->vd);
353
+ vfp_load_reg32(vd, a->vd);
354
if (neg_d) {
355
/* VFNMA, VFNMS */
356
gen_helper_vfp_negs(vd, vd);
357
}
358
fpst = fpstatus_ptr(FPST_FPCR);
359
gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
360
- neon_store_reg32(vd, a->vd);
361
+ vfp_store_reg32(vd, a->vd);
362
363
tcg_temp_free_ptr(fpst);
364
tcg_temp_free_i32(vn);
365
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a)
366
}
367
368
fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm));
369
- neon_store_reg32(fd, a->vd);
370
+ vfp_store_reg32(fd, a->vd);
371
tcg_temp_free_i32(fd);
372
return true;
373
}
374
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
375
fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
376
377
for (;;) {
378
- neon_store_reg32(fd, vd);
379
+ vfp_store_reg32(fd, vd);
380
381
if (veclen == 0) {
382
break;
383
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a)
384
vd = tcg_temp_new_i32();
385
vm = tcg_temp_new_i32();
386
387
- neon_load_reg32(vd, a->vd);
388
+ vfp_load_reg32(vd, a->vd);
389
if (a->z) {
390
tcg_gen_movi_i32(vm, 0);
391
} else {
392
- neon_load_reg32(vm, a->vm);
393
+ vfp_load_reg32(vm, a->vm);
394
}
395
396
if (a->e) {
397
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
398
vd = tcg_temp_new_i32();
399
vm = tcg_temp_new_i32();
400
401
- neon_load_reg32(vd, a->vd);
402
+ vfp_load_reg32(vd, a->vd);
403
if (a->z) {
404
tcg_gen_movi_i32(vm, 0);
405
} else {
406
- neon_load_reg32(vm, a->vm);
407
+ vfp_load_reg32(vm, a->vm);
408
}
409
410
if (a->e) {
411
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
412
/* The T bit tells us if we want the low or high 16 bits of Vm */
413
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
414
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
415
- neon_store_reg32(tmp, a->vd);
416
+ vfp_store_reg32(tmp, a->vd);
417
tcg_temp_free_i32(ahp_mode);
418
tcg_temp_free_ptr(fpst);
419
tcg_temp_free_i32(tmp);
420
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
421
ahp_mode = get_ahp_flag();
422
tmp = tcg_temp_new_i32();
423
424
- neon_load_reg32(tmp, a->vm);
425
+ vfp_load_reg32(tmp, a->vm);
426
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
427
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
428
tcg_temp_free_i32(ahp_mode);
429
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a)
430
}
431
432
tmp = tcg_temp_new_i32();
433
- neon_load_reg32(tmp, a->vm);
434
+ vfp_load_reg32(tmp, a->vm);
435
fpst = fpstatus_ptr(FPST_FPCR_F16);
436
gen_helper_rinth(tmp, tmp, fpst);
437
- neon_store_reg32(tmp, a->vd);
438
+ vfp_store_reg32(tmp, a->vd);
439
tcg_temp_free_ptr(fpst);
440
tcg_temp_free_i32(tmp);
441
return true;
442
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
443
}
444
445
tmp = tcg_temp_new_i32();
446
- neon_load_reg32(tmp, a->vm);
447
+ vfp_load_reg32(tmp, a->vm);
448
fpst = fpstatus_ptr(FPST_FPCR);
449
gen_helper_rints(tmp, tmp, fpst);
450
- neon_store_reg32(tmp, a->vd);
451
+ vfp_store_reg32(tmp, a->vd);
452
tcg_temp_free_ptr(fpst);
453
tcg_temp_free_i32(tmp);
454
return true;
455
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
456
}
457
458
tmp = tcg_temp_new_i32();
459
- neon_load_reg32(tmp, a->vm);
460
+ vfp_load_reg32(tmp, a->vm);
461
fpst = fpstatus_ptr(FPST_FPCR_F16);
462
tcg_rmode = tcg_const_i32(float_round_to_zero);
463
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
464
gen_helper_rinth(tmp, tmp, fpst);
465
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
466
- neon_store_reg32(tmp, a->vd);
467
+ vfp_store_reg32(tmp, a->vd);
468
tcg_temp_free_ptr(fpst);
469
tcg_temp_free_i32(tcg_rmode);
470
tcg_temp_free_i32(tmp);
471
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
472
}
473
474
tmp = tcg_temp_new_i32();
475
- neon_load_reg32(tmp, a->vm);
476
+ vfp_load_reg32(tmp, a->vm);
477
fpst = fpstatus_ptr(FPST_FPCR);
478
tcg_rmode = tcg_const_i32(float_round_to_zero);
479
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
480
gen_helper_rints(tmp, tmp, fpst);
481
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
482
- neon_store_reg32(tmp, a->vd);
483
+ vfp_store_reg32(tmp, a->vd);
484
tcg_temp_free_ptr(fpst);
485
tcg_temp_free_i32(tcg_rmode);
486
tcg_temp_free_i32(tmp);
487
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a)
488
}
489
490
tmp = tcg_temp_new_i32();
491
- neon_load_reg32(tmp, a->vm);
492
+ vfp_load_reg32(tmp, a->vm);
493
fpst = fpstatus_ptr(FPST_FPCR_F16);
494
gen_helper_rinth_exact(tmp, tmp, fpst);
495
- neon_store_reg32(tmp, a->vd);
496
+ vfp_store_reg32(tmp, a->vd);
497
tcg_temp_free_ptr(fpst);
498
tcg_temp_free_i32(tmp);
499
return true;
500
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
501
}
502
503
tmp = tcg_temp_new_i32();
504
- neon_load_reg32(tmp, a->vm);
505
+ vfp_load_reg32(tmp, a->vm);
506
fpst = fpstatus_ptr(FPST_FPCR);
507
gen_helper_rints_exact(tmp, tmp, fpst);
508
- neon_store_reg32(tmp, a->vd);
509
+ vfp_store_reg32(tmp, a->vd);
510
tcg_temp_free_ptr(fpst);
511
tcg_temp_free_i32(tmp);
512
return true;
513
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
514
515
vm = tcg_temp_new_i32();
516
vd = tcg_temp_new_i64();
517
- neon_load_reg32(vm, a->vm);
518
+ vfp_load_reg32(vm, a->vm);
519
gen_helper_vfp_fcvtds(vd, vm, cpu_env);
520
neon_store_reg64(vd, a->vd);
521
tcg_temp_free_i32(vm);
522
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
523
vm = tcg_temp_new_i64();
524
neon_load_reg64(vm, a->vm);
525
gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
526
- neon_store_reg32(vd, a->vd);
527
+ vfp_store_reg32(vd, a->vd);
528
tcg_temp_free_i32(vd);
529
tcg_temp_free_i64(vm);
530
return true;
531
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
532
}
533
534
vm = tcg_temp_new_i32();
535
- neon_load_reg32(vm, a->vm);
536
+ vfp_load_reg32(vm, a->vm);
537
fpst = fpstatus_ptr(FPST_FPCR_F16);
538
if (a->s) {
539
/* i32 -> f16 */
540
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
541
/* u32 -> f16 */
542
gen_helper_vfp_uitoh(vm, vm, fpst);
543
}
544
- neon_store_reg32(vm, a->vd);
545
+ vfp_store_reg32(vm, a->vd);
546
tcg_temp_free_i32(vm);
547
tcg_temp_free_ptr(fpst);
548
return true;
549
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
550
}
551
552
vm = tcg_temp_new_i32();
553
- neon_load_reg32(vm, a->vm);
554
+ vfp_load_reg32(vm, a->vm);
555
fpst = fpstatus_ptr(FPST_FPCR);
556
if (a->s) {
557
/* i32 -> f32 */
558
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
559
/* u32 -> f32 */
560
gen_helper_vfp_uitos(vm, vm, fpst);
561
}
562
- neon_store_reg32(vm, a->vd);
563
+ vfp_store_reg32(vm, a->vd);
564
tcg_temp_free_i32(vm);
565
tcg_temp_free_ptr(fpst);
566
return true;
567
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
568
569
vm = tcg_temp_new_i32();
570
vd = tcg_temp_new_i64();
571
- neon_load_reg32(vm, a->vm);
572
+ vfp_load_reg32(vm, a->vm);
573
fpst = fpstatus_ptr(FPST_FPCR);
574
if (a->s) {
575
/* i32 -> f64 */
576
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
577
vd = tcg_temp_new_i32();
578
neon_load_reg64(vm, a->vm);
579
gen_helper_vjcvt(vd, vm, cpu_env);
580
- neon_store_reg32(vd, a->vd);
581
+ vfp_store_reg32(vd, a->vd);
582
tcg_temp_free_i64(vm);
583
tcg_temp_free_i32(vd);
584
return true;
585
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
586
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
587
588
vd = tcg_temp_new_i32();
589
- neon_load_reg32(vd, a->vd);
590
+ vfp_load_reg32(vd, a->vd);
591
592
fpst = fpstatus_ptr(FPST_FPCR_F16);
593
shift = tcg_const_i32(frac_bits);
594
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
64
g_assert_not_reached();
595
g_assert_not_reached();
65
}
596
}
66
597
67
- switch (type & 0xf) {
598
- neon_store_reg32(vd, a->vd);
68
+ switch (excret & 0xf) {
599
+ vfp_store_reg32(vd, a->vd);
69
case 1: /* Return to Handler */
600
tcg_temp_free_i32(vd);
70
return_to_handler = true;
601
tcg_temp_free_i32(shift);
71
break;
602
tcg_temp_free_ptr(fpst);
72
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
603
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
73
*/
604
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
74
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
605
75
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
606
vd = tcg_temp_new_i32();
76
- v7m_exception_taken(cpu, type);
607
- neon_load_reg32(vd, a->vd);
77
+ v7m_exception_taken(cpu, excret);
608
+ vfp_load_reg32(vd, a->vd);
78
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
609
79
"stackframe: failed exception return integrity check\n");
610
fpst = fpstatus_ptr(FPST_FPCR);
80
return;
611
shift = tcg_const_i32(frac_bits);
81
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
612
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
82
613
g_assert_not_reached();
83
/* The restored xPSR exception field will be zero if we're
614
}
84
* resuming in Thread mode. If that doesn't match what the
615
85
- * exception return type specified then this is a UsageFault.
616
- neon_store_reg32(vd, a->vd);
86
+ * exception return excret specified then this is a UsageFault.
617
+ vfp_store_reg32(vd, a->vd);
87
*/
618
tcg_temp_free_i32(vd);
88
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
619
tcg_temp_free_i32(shift);
89
/* Take an INVPC UsageFault by pushing the stack again. */
620
tcg_temp_free_ptr(fpst);
90
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
621
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
91
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
622
92
v7m_push_stack(cpu);
623
fpst = fpstatus_ptr(FPST_FPCR_F16);
93
- v7m_exception_taken(cpu, type);
624
vm = tcg_temp_new_i32();
94
+ v7m_exception_taken(cpu, excret);
625
- neon_load_reg32(vm, a->vm);
95
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "
626
+ vfp_load_reg32(vm, a->vm);
96
"failed exception return integrity check\n");
627
97
return;
628
if (a->s) {
629
if (a->rz) {
630
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
631
gen_helper_vfp_touih(vm, vm, fpst);
632
}
633
}
634
- neon_store_reg32(vm, a->vd);
635
+ vfp_store_reg32(vm, a->vd);
636
tcg_temp_free_i32(vm);
637
tcg_temp_free_ptr(fpst);
638
return true;
639
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
640
641
fpst = fpstatus_ptr(FPST_FPCR);
642
vm = tcg_temp_new_i32();
643
- neon_load_reg32(vm, a->vm);
644
+ vfp_load_reg32(vm, a->vm);
645
646
if (a->s) {
647
if (a->rz) {
648
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
649
gen_helper_vfp_touis(vm, vm, fpst);
650
}
651
}
652
- neon_store_reg32(vm, a->vd);
653
+ vfp_store_reg32(vm, a->vd);
654
tcg_temp_free_i32(vm);
655
tcg_temp_free_ptr(fpst);
656
return true;
657
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
658
gen_helper_vfp_touid(vd, vm, fpst);
659
}
660
}
661
- neon_store_reg32(vd, a->vd);
662
+ vfp_store_reg32(vd, a->vd);
663
tcg_temp_free_i32(vd);
664
tcg_temp_free_i64(vm);
665
tcg_temp_free_ptr(fpst);
666
@@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a)
667
/* Insert low half of Vm into high half of Vd */
668
rm = tcg_temp_new_i32();
669
rd = tcg_temp_new_i32();
670
- neon_load_reg32(rm, a->vm);
671
- neon_load_reg32(rd, a->vd);
672
+ vfp_load_reg32(rm, a->vm);
673
+ vfp_load_reg32(rd, a->vd);
674
tcg_gen_deposit_i32(rd, rd, rm, 16, 16);
675
- neon_store_reg32(rd, a->vd);
676
+ vfp_store_reg32(rd, a->vd);
677
tcg_temp_free_i32(rm);
678
tcg_temp_free_i32(rd);
679
return true;
680
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a)
681
682
/* Set Vd to high half of Vm */
683
rm = tcg_temp_new_i32();
684
- neon_load_reg32(rm, a->vm);
685
+ vfp_load_reg32(rm, a->vm);
686
tcg_gen_shri_i32(rm, rm, 16);
687
- neon_store_reg32(rm, a->vd);
688
+ vfp_store_reg32(rm, a->vd);
689
tcg_temp_free_i32(rm);
690
return true;
691
}
98
--
692
--
99
2.7.4
693
2.20.1
100
694
101
695
diff view generated by jsdifflib
New patch
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Replace all uses of neon_load/store_reg64 within translate-neon.c.inc.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20201030022618.785675-9-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.c | 26 +++++++++
11
target/arm/translate-neon.c.inc | 94 ++++++++++++++++-----------------
12
2 files changed, 73 insertions(+), 47 deletions(-)
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
19
}
20
}
21
22
+static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
23
+{
24
+ long off = neon_element_offset(reg, ele, memop);
25
+
26
+ switch (memop) {
27
+ case MO_Q:
28
+ tcg_gen_ld_i64(dest, cpu_env, off);
29
+ break;
30
+ default:
31
+ g_assert_not_reached();
32
+ }
33
+}
34
+
35
static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
36
{
37
long off = neon_element_offset(reg, ele, memop);
38
@@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
39
}
40
}
41
42
+static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
43
+{
44
+ long off = neon_element_offset(reg, ele, memop);
45
+
46
+ switch (memop) {
47
+ case MO_64:
48
+ tcg_gen_st_i64(src, cpu_env, off);
49
+ break;
50
+ default:
51
+ g_assert_not_reached();
52
+ }
53
+}
54
+
55
static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
56
{
57
TCGv_ptr ret = tcg_temp_new_ptr();
58
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/translate-neon.c.inc
61
+++ b/target/arm/translate-neon.c.inc
62
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
63
for (pass = 0; pass < a->q + 1; pass++) {
64
TCGv_i64 tmp = tcg_temp_new_i64();
65
66
- neon_load_reg64(tmp, a->vm + pass);
67
+ read_neon_element64(tmp, a->vm, pass, MO_64);
68
fn(tmp, cpu_env, tmp, constimm);
69
- neon_store_reg64(tmp, a->vd + pass);
70
+ write_neon_element64(tmp, a->vd, pass, MO_64);
71
tcg_temp_free_i64(tmp);
72
}
73
tcg_temp_free_i64(constimm);
74
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
75
rd = tcg_temp_new_i32();
76
77
/* Load both inputs first to avoid potential overwrite if rm == rd */
78
- neon_load_reg64(rm1, a->vm);
79
- neon_load_reg64(rm2, a->vm + 1);
80
+ read_neon_element64(rm1, a->vm, 0, MO_64);
81
+ read_neon_element64(rm2, a->vm, 1, MO_64);
82
83
shiftfn(rm1, rm1, constimm);
84
narrowfn(rd, cpu_env, rm1);
85
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
86
tcg_gen_shli_i64(tmp, tmp, a->shift);
87
tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
88
}
89
- neon_store_reg64(tmp, a->vd);
90
+ write_neon_element64(tmp, a->vd, 0, MO_64);
91
92
widenfn(tmp, rm1);
93
tcg_temp_free_i32(rm1);
94
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
95
tcg_gen_shli_i64(tmp, tmp, a->shift);
96
tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
97
}
98
- neon_store_reg64(tmp, a->vd + 1);
99
+ write_neon_element64(tmp, a->vd, 1, MO_64);
100
tcg_temp_free_i64(tmp);
101
return true;
102
}
103
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
104
rm_64 = tcg_temp_new_i64();
105
106
if (src1_wide) {
107
- neon_load_reg64(rn0_64, a->vn);
108
+ read_neon_element64(rn0_64, a->vn, 0, MO_64);
109
} else {
110
TCGv_i32 tmp = tcg_temp_new_i32();
111
read_neon_element32(tmp, a->vn, 0, MO_32);
112
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
113
* avoid incorrect results if a narrow input overlaps with the result.
114
*/
115
if (src1_wide) {
116
- neon_load_reg64(rn1_64, a->vn + 1);
117
+ read_neon_element64(rn1_64, a->vn, 1, MO_64);
118
} else {
119
TCGv_i32 tmp = tcg_temp_new_i32();
120
read_neon_element32(tmp, a->vn, 1, MO_32);
121
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
122
rm = tcg_temp_new_i32();
123
read_neon_element32(rm, a->vm, 1, MO_32);
124
125
- neon_store_reg64(rn0_64, a->vd);
126
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
127
128
widenfn(rm_64, rm);
129
tcg_temp_free_i32(rm);
130
opfn(rn1_64, rn1_64, rm_64);
131
- neon_store_reg64(rn1_64, a->vd + 1);
132
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
133
134
tcg_temp_free_i64(rn0_64);
135
tcg_temp_free_i64(rn1_64);
136
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
137
rd0 = tcg_temp_new_i32();
138
rd1 = tcg_temp_new_i32();
139
140
- neon_load_reg64(rn_64, a->vn);
141
- neon_load_reg64(rm_64, a->vm);
142
+ read_neon_element64(rn_64, a->vn, 0, MO_64);
143
+ read_neon_element64(rm_64, a->vm, 0, MO_64);
144
145
opfn(rn_64, rn_64, rm_64);
146
147
narrowfn(rd0, rn_64);
148
149
- neon_load_reg64(rn_64, a->vn + 1);
150
- neon_load_reg64(rm_64, a->vm + 1);
151
+ read_neon_element64(rn_64, a->vn, 1, MO_64);
152
+ read_neon_element64(rm_64, a->vm, 1, MO_64);
153
154
opfn(rn_64, rn_64, rm_64);
155
156
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
157
/* Don't store results until after all loads: they might overlap */
158
if (accfn) {
159
tmp = tcg_temp_new_i64();
160
- neon_load_reg64(tmp, a->vd);
161
+ read_neon_element64(tmp, a->vd, 0, MO_64);
162
accfn(tmp, tmp, rd0);
163
- neon_store_reg64(tmp, a->vd);
164
- neon_load_reg64(tmp, a->vd + 1);
165
+ write_neon_element64(tmp, a->vd, 0, MO_64);
166
+ read_neon_element64(tmp, a->vd, 1, MO_64);
167
accfn(tmp, tmp, rd1);
168
- neon_store_reg64(tmp, a->vd + 1);
169
+ write_neon_element64(tmp, a->vd, 1, MO_64);
170
tcg_temp_free_i64(tmp);
171
} else {
172
- neon_store_reg64(rd0, a->vd);
173
- neon_store_reg64(rd1, a->vd + 1);
174
+ write_neon_element64(rd0, a->vd, 0, MO_64);
175
+ write_neon_element64(rd1, a->vd, 1, MO_64);
176
}
177
178
tcg_temp_free_i64(rd0);
179
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
180
181
if (accfn) {
182
TCGv_i64 t64 = tcg_temp_new_i64();
183
- neon_load_reg64(t64, a->vd);
184
+ read_neon_element64(t64, a->vd, 0, MO_64);
185
accfn(t64, t64, rn0_64);
186
- neon_store_reg64(t64, a->vd);
187
- neon_load_reg64(t64, a->vd + 1);
188
+ write_neon_element64(t64, a->vd, 0, MO_64);
189
+ read_neon_element64(t64, a->vd, 1, MO_64);
190
accfn(t64, t64, rn1_64);
191
- neon_store_reg64(t64, a->vd + 1);
192
+ write_neon_element64(t64, a->vd, 1, MO_64);
193
tcg_temp_free_i64(t64);
194
} else {
195
- neon_store_reg64(rn0_64, a->vd);
196
- neon_store_reg64(rn1_64, a->vd + 1);
197
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
198
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
199
}
200
tcg_temp_free_i64(rn0_64);
201
tcg_temp_free_i64(rn1_64);
202
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
203
right = tcg_temp_new_i64();
204
dest = tcg_temp_new_i64();
205
206
- neon_load_reg64(right, a->vn);
207
- neon_load_reg64(left, a->vm);
208
+ read_neon_element64(right, a->vn, 0, MO_64);
209
+ read_neon_element64(left, a->vm, 0, MO_64);
210
tcg_gen_extract2_i64(dest, right, left, a->imm * 8);
211
- neon_store_reg64(dest, a->vd);
212
+ write_neon_element64(dest, a->vd, 0, MO_64);
213
214
tcg_temp_free_i64(left);
215
tcg_temp_free_i64(right);
216
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
217
destright = tcg_temp_new_i64();
218
219
if (a->imm < 8) {
220
- neon_load_reg64(right, a->vn);
221
- neon_load_reg64(middle, a->vn + 1);
222
+ read_neon_element64(right, a->vn, 0, MO_64);
223
+ read_neon_element64(middle, a->vn, 1, MO_64);
224
tcg_gen_extract2_i64(destright, right, middle, a->imm * 8);
225
- neon_load_reg64(left, a->vm);
226
+ read_neon_element64(left, a->vm, 0, MO_64);
227
tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8);
228
} else {
229
- neon_load_reg64(right, a->vn + 1);
230
- neon_load_reg64(middle, a->vm);
231
+ read_neon_element64(right, a->vn, 1, MO_64);
232
+ read_neon_element64(middle, a->vm, 0, MO_64);
233
tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8);
234
- neon_load_reg64(left, a->vm + 1);
235
+ read_neon_element64(left, a->vm, 1, MO_64);
236
tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8);
237
}
238
239
- neon_store_reg64(destright, a->vd);
240
- neon_store_reg64(destleft, a->vd + 1);
241
+ write_neon_element64(destright, a->vd, 0, MO_64);
242
+ write_neon_element64(destleft, a->vd, 1, MO_64);
243
244
tcg_temp_free_i64(destright);
245
tcg_temp_free_i64(destleft);
246
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
247
248
if (accfn) {
249
TCGv_i64 tmp64 = tcg_temp_new_i64();
250
- neon_load_reg64(tmp64, a->vd + pass);
251
+ read_neon_element64(tmp64, a->vd, pass, MO_64);
252
accfn(rd_64, tmp64, rd_64);
253
tcg_temp_free_i64(tmp64);
254
}
255
- neon_store_reg64(rd_64, a->vd + pass);
256
+ write_neon_element64(rd_64, a->vd, pass, MO_64);
257
tcg_temp_free_i64(rd_64);
258
}
259
return true;
260
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
261
rd0 = tcg_temp_new_i32();
262
rd1 = tcg_temp_new_i32();
263
264
- neon_load_reg64(rm, a->vm);
265
+ read_neon_element64(rm, a->vm, 0, MO_64);
266
narrowfn(rd0, cpu_env, rm);
267
- neon_load_reg64(rm, a->vm + 1);
268
+ read_neon_element64(rm, a->vm, 1, MO_64);
269
narrowfn(rd1, cpu_env, rm);
270
write_neon_element32(rd0, a->vd, 0, MO_32);
271
write_neon_element32(rd1, a->vd, 1, MO_32);
272
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
273
274
widenfn(rd, rm0);
275
tcg_gen_shli_i64(rd, rd, 8 << a->size);
276
- neon_store_reg64(rd, a->vd);
277
+ write_neon_element64(rd, a->vd, 0, MO_64);
278
widenfn(rd, rm1);
279
tcg_gen_shli_i64(rd, rd, 8 << a->size);
280
- neon_store_reg64(rd, a->vd + 1);
281
+ write_neon_element64(rd, a->vd, 1, MO_64);
282
283
tcg_temp_free_i64(rd);
284
tcg_temp_free_i32(rm0);
285
@@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
286
rm = tcg_temp_new_i64();
287
rd = tcg_temp_new_i64();
288
for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
289
- neon_load_reg64(rm, a->vm + pass);
290
- neon_load_reg64(rd, a->vd + pass);
291
- neon_store_reg64(rm, a->vd + pass);
292
- neon_store_reg64(rd, a->vm + pass);
293
+ read_neon_element64(rm, a->vm, pass, MO_64);
294
+ read_neon_element64(rd, a->vd, pass, MO_64);
295
+ write_neon_element64(rm, a->vd, pass, MO_64);
296
+ write_neon_element64(rd, a->vm, pass, MO_64);
297
}
298
tcg_temp_free_i64(rm);
299
tcg_temp_free_i64(rd);
300
--
301
2.20.1
302
303
diff view generated by jsdifflib
New patch
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
The only uses of this function are for loading VFP
4
double-precision values, and nothing to do with NEON.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201030022618.785675-10-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate.c | 8 ++--
12
target/arm/translate-vfp.c.inc | 84 +++++++++++++++++-----------------
13
2 files changed, 46 insertions(+), 46 deletions(-)
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
18
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
20
}
21
}
22
23
-static inline void neon_load_reg64(TCGv_i64 var, int reg)
24
+static inline void vfp_load_reg64(TCGv_i64 var, int reg)
25
{
26
- tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
27
+ tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
28
}
29
30
-static inline void neon_store_reg64(TCGv_i64 var, int reg)
31
+static inline void vfp_store_reg64(TCGv_i64 var, int reg)
32
{
33
- tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
34
+ tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
35
}
36
37
static inline void vfp_load_reg32(TCGv_i32 var, int reg)
38
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/translate-vfp.c.inc
41
+++ b/target/arm/translate-vfp.c.inc
42
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
43
tcg_gen_ext_i32_i64(nf, cpu_NF);
44
tcg_gen_ext_i32_i64(vf, cpu_VF);
45
46
- neon_load_reg64(frn, rn);
47
- neon_load_reg64(frm, rm);
48
+ vfp_load_reg64(frn, rn);
49
+ vfp_load_reg64(frm, rm);
50
switch (a->cc) {
51
case 0: /* eq: Z */
52
tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
53
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
54
tcg_temp_free_i64(tmp);
55
break;
56
}
57
- neon_store_reg64(dest, rd);
58
+ vfp_store_reg64(dest, rd);
59
tcg_temp_free_i64(frn);
60
tcg_temp_free_i64(frm);
61
tcg_temp_free_i64(dest);
62
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
63
TCGv_i64 tcg_res;
64
tcg_op = tcg_temp_new_i64();
65
tcg_res = tcg_temp_new_i64();
66
- neon_load_reg64(tcg_op, rm);
67
+ vfp_load_reg64(tcg_op, rm);
68
gen_helper_rintd(tcg_res, tcg_op, fpst);
69
- neon_store_reg64(tcg_res, rd);
70
+ vfp_store_reg64(tcg_res, rd);
71
tcg_temp_free_i64(tcg_op);
72
tcg_temp_free_i64(tcg_res);
73
} else {
74
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
75
tcg_double = tcg_temp_new_i64();
76
tcg_res = tcg_temp_new_i64();
77
tcg_tmp = tcg_temp_new_i32();
78
- neon_load_reg64(tcg_double, rm);
79
+ vfp_load_reg64(tcg_double, rm);
80
if (is_signed) {
81
gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
82
} else {
83
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
84
tmp = tcg_temp_new_i64();
85
if (a->l) {
86
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
87
- neon_store_reg64(tmp, a->vd);
88
+ vfp_store_reg64(tmp, a->vd);
89
} else {
90
- neon_load_reg64(tmp, a->vd);
91
+ vfp_load_reg64(tmp, a->vd);
92
gen_aa32_st64(s, tmp, addr, get_mem_index(s));
93
}
94
tcg_temp_free_i64(tmp);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
96
if (a->l) {
97
/* load */
98
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
99
- neon_store_reg64(tmp, a->vd + i);
100
+ vfp_store_reg64(tmp, a->vd + i);
101
} else {
102
/* store */
103
- neon_load_reg64(tmp, a->vd + i);
104
+ vfp_load_reg64(tmp, a->vd + i);
105
gen_aa32_st64(s, tmp, addr, get_mem_index(s));
106
}
107
tcg_gen_addi_i32(addr, addr, offset);
108
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
109
fd = tcg_temp_new_i64();
110
fpst = fpstatus_ptr(FPST_FPCR);
111
112
- neon_load_reg64(f0, vn);
113
- neon_load_reg64(f1, vm);
114
+ vfp_load_reg64(f0, vn);
115
+ vfp_load_reg64(f1, vm);
116
117
for (;;) {
118
if (reads_vd) {
119
- neon_load_reg64(fd, vd);
120
+ vfp_load_reg64(fd, vd);
121
}
122
fn(fd, f0, f1, fpst);
123
- neon_store_reg64(fd, vd);
124
+ vfp_store_reg64(fd, vd);
125
126
if (veclen == 0) {
127
break;
128
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
129
veclen--;
130
vd = vfp_advance_dreg(vd, delta_d);
131
vn = vfp_advance_dreg(vn, delta_d);
132
- neon_load_reg64(f0, vn);
133
+ vfp_load_reg64(f0, vn);
134
if (delta_m) {
135
vm = vfp_advance_dreg(vm, delta_m);
136
- neon_load_reg64(f1, vm);
137
+ vfp_load_reg64(f1, vm);
138
}
139
}
140
141
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
142
f0 = tcg_temp_new_i64();
143
fd = tcg_temp_new_i64();
144
145
- neon_load_reg64(f0, vm);
146
+ vfp_load_reg64(f0, vm);
147
148
for (;;) {
149
fn(fd, f0);
150
- neon_store_reg64(fd, vd);
151
+ vfp_store_reg64(fd, vd);
152
153
if (veclen == 0) {
154
break;
155
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
156
/* single source one-many */
157
while (veclen--) {
158
vd = vfp_advance_dreg(vd, delta_d);
159
- neon_store_reg64(fd, vd);
160
+ vfp_store_reg64(fd, vd);
161
}
162
break;
163
}
164
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
165
veclen--;
166
vd = vfp_advance_dreg(vd, delta_d);
167
vd = vfp_advance_dreg(vm, delta_m);
168
- neon_load_reg64(f0, vm);
169
+ vfp_load_reg64(f0, vm);
170
}
171
172
tcg_temp_free_i64(f0);
173
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
174
vm = tcg_temp_new_i64();
175
vd = tcg_temp_new_i64();
176
177
- neon_load_reg64(vn, a->vn);
178
- neon_load_reg64(vm, a->vm);
179
+ vfp_load_reg64(vn, a->vn);
180
+ vfp_load_reg64(vm, a->vm);
181
if (neg_n) {
182
/* VFNMS, VFMS */
183
gen_helper_vfp_negd(vn, vn);
184
}
185
- neon_load_reg64(vd, a->vd);
186
+ vfp_load_reg64(vd, a->vd);
187
if (neg_d) {
188
/* VFNMA, VFNMS */
189
gen_helper_vfp_negd(vd, vd);
190
}
191
fpst = fpstatus_ptr(FPST_FPCR);
192
gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
193
- neon_store_reg64(vd, a->vd);
194
+ vfp_store_reg64(vd, a->vd);
195
196
tcg_temp_free_ptr(fpst);
197
tcg_temp_free_i64(vn);
198
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
199
fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
200
201
for (;;) {
202
- neon_store_reg64(fd, vd);
203
+ vfp_store_reg64(fd, vd);
204
205
if (veclen == 0) {
206
break;
207
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
208
vd = tcg_temp_new_i64();
209
vm = tcg_temp_new_i64();
210
211
- neon_load_reg64(vd, a->vd);
212
+ vfp_load_reg64(vd, a->vd);
213
if (a->z) {
214
tcg_gen_movi_i64(vm, 0);
215
} else {
216
- neon_load_reg64(vm, a->vm);
217
+ vfp_load_reg64(vm, a->vm);
218
}
219
220
if (a->e) {
221
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
222
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
223
vd = tcg_temp_new_i64();
224
gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
225
- neon_store_reg64(vd, a->vd);
226
+ vfp_store_reg64(vd, a->vd);
227
tcg_temp_free_i32(ahp_mode);
228
tcg_temp_free_ptr(fpst);
229
tcg_temp_free_i32(tmp);
230
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
231
tmp = tcg_temp_new_i32();
232
vm = tcg_temp_new_i64();
233
234
- neon_load_reg64(vm, a->vm);
235
+ vfp_load_reg64(vm, a->vm);
236
gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
237
tcg_temp_free_i64(vm);
238
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
239
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
240
}
241
242
tmp = tcg_temp_new_i64();
243
- neon_load_reg64(tmp, a->vm);
244
+ vfp_load_reg64(tmp, a->vm);
245
fpst = fpstatus_ptr(FPST_FPCR);
246
gen_helper_rintd(tmp, tmp, fpst);
247
- neon_store_reg64(tmp, a->vd);
248
+ vfp_store_reg64(tmp, a->vd);
249
tcg_temp_free_ptr(fpst);
250
tcg_temp_free_i64(tmp);
251
return true;
252
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
253
}
254
255
tmp = tcg_temp_new_i64();
256
- neon_load_reg64(tmp, a->vm);
257
+ vfp_load_reg64(tmp, a->vm);
258
fpst = fpstatus_ptr(FPST_FPCR);
259
tcg_rmode = tcg_const_i32(float_round_to_zero);
260
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
261
gen_helper_rintd(tmp, tmp, fpst);
262
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
263
- neon_store_reg64(tmp, a->vd);
264
+ vfp_store_reg64(tmp, a->vd);
265
tcg_temp_free_ptr(fpst);
266
tcg_temp_free_i64(tmp);
267
tcg_temp_free_i32(tcg_rmode);
268
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
269
}
270
271
tmp = tcg_temp_new_i64();
272
- neon_load_reg64(tmp, a->vm);
273
+ vfp_load_reg64(tmp, a->vm);
274
fpst = fpstatus_ptr(FPST_FPCR);
275
gen_helper_rintd_exact(tmp, tmp, fpst);
276
- neon_store_reg64(tmp, a->vd);
277
+ vfp_store_reg64(tmp, a->vd);
278
tcg_temp_free_ptr(fpst);
279
tcg_temp_free_i64(tmp);
280
return true;
281
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
282
vd = tcg_temp_new_i64();
283
vfp_load_reg32(vm, a->vm);
284
gen_helper_vfp_fcvtds(vd, vm, cpu_env);
285
- neon_store_reg64(vd, a->vd);
286
+ vfp_store_reg64(vd, a->vd);
287
tcg_temp_free_i32(vm);
288
tcg_temp_free_i64(vd);
289
return true;
290
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
291
292
vd = tcg_temp_new_i32();
293
vm = tcg_temp_new_i64();
294
- neon_load_reg64(vm, a->vm);
295
+ vfp_load_reg64(vm, a->vm);
296
gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
297
vfp_store_reg32(vd, a->vd);
298
tcg_temp_free_i32(vd);
299
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
300
/* u32 -> f64 */
301
gen_helper_vfp_uitod(vd, vm, fpst);
302
}
303
- neon_store_reg64(vd, a->vd);
304
+ vfp_store_reg64(vd, a->vd);
305
tcg_temp_free_i32(vm);
306
tcg_temp_free_i64(vd);
307
tcg_temp_free_ptr(fpst);
308
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
309
310
vm = tcg_temp_new_i64();
311
vd = tcg_temp_new_i32();
312
- neon_load_reg64(vm, a->vm);
313
+ vfp_load_reg64(vm, a->vm);
314
gen_helper_vjcvt(vd, vm, cpu_env);
315
vfp_store_reg32(vd, a->vd);
316
tcg_temp_free_i64(vm);
317
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
318
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
319
320
vd = tcg_temp_new_i64();
321
- neon_load_reg64(vd, a->vd);
322
+ vfp_load_reg64(vd, a->vd);
323
324
fpst = fpstatus_ptr(FPST_FPCR);
325
shift = tcg_const_i32(frac_bits);
326
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
327
g_assert_not_reached();
328
}
329
330
- neon_store_reg64(vd, a->vd);
331
+ vfp_store_reg64(vd, a->vd);
332
tcg_temp_free_i64(vd);
333
tcg_temp_free_i32(shift);
334
tcg_temp_free_ptr(fpst);
335
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
336
fpst = fpstatus_ptr(FPST_FPCR);
337
vm = tcg_temp_new_i64();
338
vd = tcg_temp_new_i32();
339
- neon_load_reg64(vm, a->vm);
340
+ vfp_load_reg64(vm, a->vm);
341
342
if (a->s) {
343
if (a->rz) {
344
--
345
2.20.1
346
347
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
In both cases, we can sink the write-back and perform
4
the accumulate into the normal destination temps.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201030022618.785675-11-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-neon.c.inc | 23 +++++++++--------------
12
1 file changed, 9 insertions(+), 14 deletions(-)
13
14
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-neon.c.inc
17
+++ b/target/arm/translate-neon.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
19
if (accfn) {
20
tmp = tcg_temp_new_i64();
21
read_neon_element64(tmp, a->vd, 0, MO_64);
22
- accfn(tmp, tmp, rd0);
23
- write_neon_element64(tmp, a->vd, 0, MO_64);
24
+ accfn(rd0, tmp, rd0);
25
read_neon_element64(tmp, a->vd, 1, MO_64);
26
- accfn(tmp, tmp, rd1);
27
- write_neon_element64(tmp, a->vd, 1, MO_64);
28
+ accfn(rd1, tmp, rd1);
29
tcg_temp_free_i64(tmp);
30
- } else {
31
- write_neon_element64(rd0, a->vd, 0, MO_64);
32
- write_neon_element64(rd1, a->vd, 1, MO_64);
33
}
34
35
+ write_neon_element64(rd0, a->vd, 0, MO_64);
36
+ write_neon_element64(rd1, a->vd, 1, MO_64);
37
tcg_temp_free_i64(rd0);
38
tcg_temp_free_i64(rd1);
39
40
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
41
if (accfn) {
42
TCGv_i64 t64 = tcg_temp_new_i64();
43
read_neon_element64(t64, a->vd, 0, MO_64);
44
- accfn(t64, t64, rn0_64);
45
- write_neon_element64(t64, a->vd, 0, MO_64);
46
+ accfn(rn0_64, t64, rn0_64);
47
read_neon_element64(t64, a->vd, 1, MO_64);
48
- accfn(t64, t64, rn1_64);
49
- write_neon_element64(t64, a->vd, 1, MO_64);
50
+ accfn(rn1_64, t64, rn1_64);
51
tcg_temp_free_i64(t64);
52
- } else {
53
- write_neon_element64(rn0_64, a->vd, 0, MO_64);
54
- write_neon_element64(rn1_64, a->vd, 1, MO_64);
55
}
56
+
57
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
58
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
59
tcg_temp_free_i64(rn0_64);
60
tcg_temp_free_i64(rn1_64);
61
return true;
62
--
63
2.20.1
64
65
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The EP108 is a early access development board. Now that silicon is in
3
We can use proper widening loads to extend 32-bit inputs,
4
production people have access to the ZCU102. Let's rename the internal
4
and skip the "widenfn" step.
5
QEMU files and variables to use the ZCU102.
6
5
7
There is no functional change here as the EP108 is still a valid board
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
option.
7
Message-id: 20201030022618.785675-12-richard.henderson@linaro.org
9
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/arm/Makefile.objs | 2 +-
11
target/arm/translate.c | 6 +++
15
hw/arm/{xlnx-ep108.c => xlnx-zcu102.c} | 30 +++++++++++++++---------------
12
target/arm/translate-neon.c.inc | 66 ++++++++++++++++++---------------
16
2 files changed, 16 insertions(+), 16 deletions(-)
13
2 files changed, 43 insertions(+), 29 deletions(-)
17
rename hw/arm/{xlnx-ep108.c => xlnx-zcu102.c} (85%)
18
14
19
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/Makefile.objs
17
--- a/target/arm/translate.c
22
+++ b/hw/arm/Makefile.objs
18
+++ b/target/arm/translate.c
23
@@ -XXX,XX +XXX,XX @@ obj-y += omap1.o omap2.o strongarm.o
19
@@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
24
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
20
long off = neon_element_offset(reg, ele, memop);
25
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
21
26
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
22
switch (memop) {
27
-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
23
+ case MO_SL:
28
+obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-zcu102.o
24
+ tcg_gen_ld32s_i64(dest, cpu_env, off);
29
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
25
+ break;
30
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
26
+ case MO_UL:
31
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
27
+ tcg_gen_ld32u_i64(dest, cpu_env, off);
32
diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-zcu102.c
28
+ break;
33
similarity index 85%
29
case MO_Q:
34
rename from hw/arm/xlnx-ep108.c
30
tcg_gen_ld_i64(dest, cpu_env, off);
35
rename to hw/arm/xlnx-zcu102.c
31
break;
32
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
36
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/arm/xlnx-ep108.c
34
--- a/target/arm/translate-neon.c.inc
38
+++ b/hw/arm/xlnx-zcu102.c
35
+++ b/target/arm/translate-neon.c.inc
39
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
40
/*
37
static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
41
- * Xilinx ZynqMP EP108 board
38
NeonGenWidenFn *widenfn,
42
+ * Xilinx ZynqMP ZCU102 board
39
NeonGenTwo64OpFn *opfn,
43
*
40
- bool src1_wide)
44
* Copyright (C) 2015 Xilinx Inc
41
+ int src1_mop, int src2_mop)
45
* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
46
@@ -XXX,XX +XXX,XX @@
47
#include "exec/address-spaces.h"
48
#include "qemu/log.h"
49
50
-typedef struct XlnxEP108 {
51
+typedef struct XlnxZCU102 {
52
XlnxZynqMPState soc;
53
MemoryRegion ddr_ram;
54
-} XlnxEP108;
55
+} XlnxZCU102;
56
57
-static struct arm_boot_info xlnx_ep108_binfo;
58
+static struct arm_boot_info xlnx_zcu102_binfo;
59
60
-static void xlnx_ep108_init(MachineState *machine)
61
+static void xlnx_zcu102_init(MachineState *machine)
62
{
42
{
63
- XlnxEP108 *s = g_new0(XlnxEP108, 1);
43
/* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */
64
+ XlnxZCU102 *s = g_new0(XlnxZCU102, 1);
44
TCGv_i64 rn0_64, rn1_64, rm_64;
65
int i;
45
- TCGv_i32 rm;
66
uint64_t ram_size = machine->ram_size;
46
67
47
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
68
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)
48
return false;
49
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
50
return false;
69
}
51
}
70
52
71
if (ram_size < 0x08000000) {
53
- if (!widenfn || !opfn) {
72
- qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for EP108",
54
+ if (!opfn) {
73
+ qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
55
/* size == 3 case, which is an entirely different insn group */
74
ram_size);
56
return false;
75
}
57
}
76
58
77
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)
59
- if ((a->vd & 1) || (src1_wide && (a->vn & 1))) {
78
60
+ if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) {
79
/* TODO create and connect IDE devices for ide_drive_get() */
61
return false;
80
62
}
81
- xlnx_ep108_binfo.ram_size = ram_size;
63
82
- xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
64
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
83
- xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
65
rn1_64 = tcg_temp_new_i64();
84
- xlnx_ep108_binfo.initrd_filename = machine->initrd_filename;
66
rm_64 = tcg_temp_new_i64();
85
- xlnx_ep108_binfo.loader_start = 0;
67
86
- arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_ep108_binfo);
68
- if (src1_wide) {
87
+ xlnx_zcu102_binfo.ram_size = ram_size;
69
- read_neon_element64(rn0_64, a->vn, 0, MO_64);
88
+ xlnx_zcu102_binfo.kernel_filename = machine->kernel_filename;
70
+ if (src1_mop >= 0) {
89
+ xlnx_zcu102_binfo.kernel_cmdline = machine->kernel_cmdline;
71
+ read_neon_element64(rn0_64, a->vn, 0, src1_mop);
90
+ xlnx_zcu102_binfo.initrd_filename = machine->initrd_filename;
72
} else {
91
+ xlnx_zcu102_binfo.loader_start = 0;
73
TCGv_i32 tmp = tcg_temp_new_i32();
92
+ arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
74
read_neon_element32(tmp, a->vn, 0, MO_32);
75
widenfn(rn0_64, tmp);
76
tcg_temp_free_i32(tmp);
77
}
78
- rm = tcg_temp_new_i32();
79
- read_neon_element32(rm, a->vm, 0, MO_32);
80
+ if (src2_mop >= 0) {
81
+ read_neon_element64(rm_64, a->vm, 0, src2_mop);
82
+ } else {
83
+ TCGv_i32 tmp = tcg_temp_new_i32();
84
+ read_neon_element32(tmp, a->vm, 0, MO_32);
85
+ widenfn(rm_64, tmp);
86
+ tcg_temp_free_i32(tmp);
87
+ }
88
89
- widenfn(rm_64, rm);
90
- tcg_temp_free_i32(rm);
91
opfn(rn0_64, rn0_64, rm_64);
92
93
/*
94
* Load second pass inputs before storing the first pass result, to
95
* avoid incorrect results if a narrow input overlaps with the result.
96
*/
97
- if (src1_wide) {
98
- read_neon_element64(rn1_64, a->vn, 1, MO_64);
99
+ if (src1_mop >= 0) {
100
+ read_neon_element64(rn1_64, a->vn, 1, src1_mop);
101
} else {
102
TCGv_i32 tmp = tcg_temp_new_i32();
103
read_neon_element32(tmp, a->vn, 1, MO_32);
104
widenfn(rn1_64, tmp);
105
tcg_temp_free_i32(tmp);
106
}
107
- rm = tcg_temp_new_i32();
108
- read_neon_element32(rm, a->vm, 1, MO_32);
109
+ if (src2_mop >= 0) {
110
+ read_neon_element64(rm_64, a->vm, 1, src2_mop);
111
+ } else {
112
+ TCGv_i32 tmp = tcg_temp_new_i32();
113
+ read_neon_element32(tmp, a->vm, 1, MO_32);
114
+ widenfn(rm_64, tmp);
115
+ tcg_temp_free_i32(tmp);
116
+ }
117
118
write_neon_element64(rn0_64, a->vd, 0, MO_64);
119
120
- widenfn(rm_64, rm);
121
- tcg_temp_free_i32(rm);
122
opfn(rn1_64, rn1_64, rm_64);
123
write_neon_element64(rn1_64, a->vd, 1, MO_64);
124
125
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
126
return true;
93
}
127
}
94
128
95
static void xlnx_ep108_machine_init(MachineClass *mc)
129
-#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \
96
{
130
+#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \
97
mc->desc = "Xilinx ZynqMP EP108 board";
131
static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
98
- mc->init = xlnx_ep108_init;
132
{ \
99
+ mc->init = xlnx_zcu102_init;
133
static NeonGenWidenFn * const widenfn[] = { \
100
mc->block_default_type = IF_IDE;
134
gen_helper_neon_widen_##S##8, \
101
mc->units_per_default_bus = 1;
135
gen_helper_neon_widen_##S##16, \
102
mc->ignore_memory_transaction_failures = true;
136
- tcg_gen_##EXT##_i32_i64, \
103
@@ -XXX,XX +XXX,XX @@ DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init)
137
- NULL, \
104
static void xlnx_zcu102_machine_init(MachineClass *mc)
138
+ NULL, NULL, \
105
{
139
}; \
106
mc->desc = "Xilinx ZynqMP ZCU102 board";
140
static NeonGenTwo64OpFn * const addfn[] = { \
107
- mc->init = xlnx_ep108_init;
141
gen_helper_neon_##OP##l_u16, \
108
+ mc->init = xlnx_zcu102_init;
142
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
109
mc->block_default_type = IF_IDE;
143
tcg_gen_##OP##_i64, \
110
mc->units_per_default_bus = 1;
144
NULL, \
111
mc->ignore_memory_transaction_failures = true;
145
}; \
146
- return do_prewiden_3d(s, a, widenfn[a->size], \
147
- addfn[a->size], SRC1WIDE); \
148
+ int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1; \
149
+ return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \
150
+ SRC1WIDE ? MO_Q : narrow_mop, \
151
+ narrow_mop); \
152
}
153
154
-DO_PREWIDEN(VADDL_S, s, ext, add, false)
155
-DO_PREWIDEN(VADDL_U, u, extu, add, false)
156
-DO_PREWIDEN(VSUBL_S, s, ext, sub, false)
157
-DO_PREWIDEN(VSUBL_U, u, extu, sub, false)
158
-DO_PREWIDEN(VADDW_S, s, ext, add, true)
159
-DO_PREWIDEN(VADDW_U, u, extu, add, true)
160
-DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
161
-DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
162
+DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN)
163
+DO_PREWIDEN(VADDL_U, u, add, false, 0)
164
+DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN)
165
+DO_PREWIDEN(VSUBL_U, u, sub, false, 0)
166
+DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN)
167
+DO_PREWIDEN(VADDW_U, u, add, true, 0)
168
+DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN)
169
+DO_PREWIDEN(VSUBW_U, u, sub, true, 0)
170
171
static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
172
NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
112
--
173
--
113
2.7.4
174
2.20.1
114
175
115
176
diff view generated by jsdifflib
1
In several places we were unconditionally applying the
1
In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error
2
nvic_gprio_mask() to a priority value. This is incorrect
2
meant we were using the H4() address swizzler macro rather than the
3
if the priority is one of the fixed negative priority
3
H2() which is required for 2-byte data. This had no effect on
4
values (for NMI and HardFault), so don't do it.
4
little-endian hosts but meant we put the result data into the
5
5
destination Dreg in the wrong order on big-endian hosts.
6
This bug would have caused both NMI and HardFault to be
7
considered as the same priority and so NMI wouldn't
8
correctly preempt HardFault.
9
6
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1505137930-13255-5-git-send-email-peter.maydell@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20201028191712.4910-2-peter.maydell@linaro.org
13
---
11
---
14
hw/intc/armv7m_nvic.c | 11 +++++++++--
12
target/arm/vec_helper.c | 8 ++++----
15
1 file changed, 9 insertions(+), 2 deletions(-)
13
1 file changed, 4 insertions(+), 4 deletions(-)
16
14
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
17
--- a/target/arm/vec_helper.c
20
+++ b/hw/intc/armv7m_nvic.c
18
+++ b/target/arm/vec_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)
19
@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)
22
}
20
r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \
21
r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \
22
\
23
- d[H4(0)] = r0; \
24
- d[H4(1)] = r1; \
25
- d[H4(2)] = r2; \
26
- d[H4(3)] = r3; \
27
+ d[H2(0)] = r0; \
28
+ d[H2(1)] = r1; \
29
+ d[H2(2)] = r2; \
30
+ d[H2(3)] = r3; \
23
}
31
}
24
32
25
+ if (active_prio > 0) {
33
DO_NEON_PAIRWISE(neon_padd, add)
26
+ active_prio &= nvic_gprio_mask(s);
27
+ }
28
+
29
s->vectpending = pend_irq;
30
- s->exception_prio = active_prio & nvic_gprio_mask(s);
31
+ s->exception_prio = active_prio;
32
33
trace_nvic_recompute_state(s->vectpending, s->exception_prio);
34
}
35
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
36
assert(vec->enabled);
37
assert(vec->pending);
38
39
- pendgroupprio = vec->prio & nvic_gprio_mask(s);
40
+ pendgroupprio = vec->prio;
41
+ if (pendgroupprio > 0) {
42
+ pendgroupprio &= nvic_gprio_mask(s);
43
+ }
44
assert(pendgroupprio < running);
45
46
trace_nvic_acknowledge_irq(pending, vec->prio);
47
--
34
--
48
2.7.4
35
2.20.1
49
36
50
37
diff view generated by jsdifflib
1
In do_v7m_exception_exit(), there's no need to force the high 4
1
The helper functions for performing the udot/sdot operations against
2
bits of 'type' to 1 when calling v7m_exception_taken(), because
2
a scalar were not using an address-swizzling macro when converting
3
we know that they're always 1 or we could not have got to this
3
the index of the scalar element into a pointer into the vm array.
4
"handle return to magic exception return address" code. Remove
4
This had no effect on little-endian hosts but meant we generated
5
the unnecessary ORs.
5
incorrect results on big-endian hosts.
6
7
For these insns, the index is indexing over group of 4 8-bit values,
8
so 32 bits per indexed entity, and H4() is therefore what we want.
9
(For Neon the only possible input indexes are 0 and 1.)
6
10
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 1505137930-13255-6-git-send-email-peter.maydell@linaro.org
14
Message-id: 20201028191712.4910-3-peter.maydell@linaro.org
11
---
15
---
12
target/arm/helper.c | 4 ++--
16
target/arm/vec_helper.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
17
1 file changed, 2 insertions(+), 2 deletions(-)
14
18
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
21
--- a/target/arm/vec_helper.c
18
+++ b/target/arm/helper.c
22
+++ b/target/arm/vec_helper.c
19
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
23
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
20
*/
24
intptr_t index = simd_data(desc);
21
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
25
uint32_t *d = vd;
22
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
26
int8_t *n = vn;
23
- v7m_exception_taken(cpu, type | 0xf0000000);
27
- int8_t *m_indexed = (int8_t *)vm + index * 4;
24
+ v7m_exception_taken(cpu, type);
28
+ int8_t *m_indexed = (int8_t *)vm + H4(index) * 4;
25
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
29
26
"stackframe: failed exception return integrity check\n");
30
/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
27
return;
31
* Otherwise opr_sz is a multiple of 16.
28
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
32
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
29
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
33
intptr_t index = simd_data(desc);
30
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
34
uint32_t *d = vd;
31
v7m_push_stack(cpu);
35
uint8_t *n = vn;
32
- v7m_exception_taken(cpu, type | 0xf0000000);
36
- uint8_t *m_indexed = (uint8_t *)vm + index * 4;
33
+ v7m_exception_taken(cpu, type);
37
+ uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4;
34
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "
38
35
"failed exception return integrity check\n");
39
/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
36
return;
40
* Otherwise opr_sz is a multiple of 16.
37
--
41
--
38
2.7.4
42
2.20.1
39
43
40
44
diff view generated by jsdifflib
1
For a bus fault, the M profile BFSR bit PRECISERR means a bus
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
fault on a data access, and IBUSERR means a bus fault on an
3
instruction access. We had these the wrong way around; fix this.
4
2
3
HCR should be applied when NS is set, not when it is cleared.
4
5
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505137930-13255-4-git-send-email-peter.maydell@linaro.org
9
---
8
---
10
target/arm/helper.c | 8 ++++----
9
target/arm/helper.c | 5 ++---
11
1 file changed, 4 insertions(+), 4 deletions(-)
10
1 file changed, 2 insertions(+), 3 deletions(-)
12
11
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
14
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
15
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
16
@@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
18
case 0x8: /* External Abort */
17
19
switch (cs->exception_index) {
18
/*
20
case EXCP_PREFETCH_ABORT:
19
* Non-IS variants of TLB operations are upgraded to
21
- env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK;
20
- * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
22
- qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n");
21
+ * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
23
+ env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
22
* force broadcast of these operations.
24
+ qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n");
23
*/
25
break;
24
static bool tlb_force_broadcast(CPUARMState *env)
26
case EXCP_DATA_ABORT:
25
{
27
env->v7m.cfsr[M_REG_NS] |=
26
- return (env->cp15.hcr_el2 & HCR_FB) &&
28
- (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
27
- arm_current_el(env) == 1 && arm_is_secure_below_el3(env);
29
+ (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
28
+ return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
30
env->v7m.bfar = env->exception.vaddress;
29
}
31
qemu_log_mask(CPU_LOG_INT,
30
32
- "...with CFSR.IBUSERR and BFAR 0x%x\n",
31
static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
33
+ "...with CFSR.PRECISERR and BFAR 0x%x\n",
34
env->v7m.bfar);
35
break;
36
}
37
--
32
--
38
2.7.4
33
2.20.1
39
34
40
35
diff view generated by jsdifflib
1
For M profile we must clear the exclusive monitor on reset, exception
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
entry and exception exit. We weren't doing any of these things; fix
3
this bug.
4
2
3
Secure mode is not exempted from checking SCR_EL3.TLOR, and in the
4
future HCR_EL2.TLOR when S-EL2 is enabled.
5
6
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1505137930-13255-3-git-send-email-peter.maydell@linaro.org
9
---
9
---
10
target/arm/internals.h | 10 ++++++++++
10
target/arm/helper.c | 19 +++++--------------
11
target/arm/cpu.c | 6 ++++++
11
1 file changed, 5 insertions(+), 14 deletions(-)
12
target/arm/helper.c | 2 ++
13
target/arm/op_helper.c | 2 +-
14
4 files changed, 19 insertions(+), 1 deletion(-)
15
12
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu);
21
#endif
22
23
/**
24
+ * arm_clear_exclusive: clear the exclusive monitor
25
+ * @env: CPU env
26
+ * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
27
+ */
28
+static inline void arm_clear_exclusive(CPUARMState *env)
29
+{
30
+ env->exclusive_addr = -1;
31
+}
32
+
33
+/**
34
* ARMMMUFaultInfo: Information describing an ARM MMU Fault
35
* @s2addr: Address that caused a fault at stage 2
36
* @stage2: True if we faulted at stage 2
37
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu.c
40
+++ b/target/arm/cpu.c
41
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
42
env->regs[15] = 0xFFFF0000;
43
}
44
45
+ /* M profile requires that reset clears the exclusive monitor;
46
+ * A profile does not, but clearing it makes more sense than having it
47
+ * set with an exclusive access on address zero.
48
+ */
49
+ arm_clear_exclusive(env);
50
+
51
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
52
#endif
53
54
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
55
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/helper.c
15
--- a/target/arm/helper.c
57
+++ b/target/arm/helper.c
16
+++ b/target/arm/helper.c
58
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr)
17
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
59
18
#endif
60
armv7m_nvic_acknowledge_irq(env->nvic);
19
61
switch_v7m_sp(env, 0);
20
/* Shared logic between LORID and the rest of the LOR* registers.
62
+ arm_clear_exclusive(env);
21
- * Secure state has already been delt with.
63
/* Clear IT bits */
22
+ * Secure state exclusion has already been dealt with.
64
env->condexec_bits = 0;
23
*/
65
env->regs[14] = lr;
24
-static CPAccessResult access_lor_ns(CPUARMState *env)
66
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
25
+static CPAccessResult access_lor_ns(CPUARMState *env,
26
+ const ARMCPRegInfo *ri, bool isread)
27
{
28
int el = arm_current_el(env);
29
30
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env)
31
return CP_ACCESS_OK;
32
}
33
34
-static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,
35
- bool isread)
36
-{
37
- if (arm_is_secure_below_el3(env)) {
38
- /* Access ok in secure mode. */
39
- return CP_ACCESS_OK;
40
- }
41
- return access_lor_ns(env);
42
-}
43
-
44
static CPAccessResult access_lor_other(CPUARMState *env,
45
const ARMCPRegInfo *ri, bool isread)
46
{
47
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env,
48
/* Access denied in secure mode. */
49
return CP_ACCESS_TRAP;
67
}
50
}
68
51
- return access_lor_ns(env);
69
/* Otherwise, we have a successful exception exit. */
52
+ return access_lor_ns(env, ri, isread);
70
+ arm_clear_exclusive(env);
71
qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
72
}
53
}
73
54
74
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
55
/*
75
index XXXXXXX..XXXXXXX 100644
56
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
76
--- a/target/arm/op_helper.c
57
.type = ARM_CP_CONST, .resetvalue = 0 },
77
+++ b/target/arm/op_helper.c
58
{ .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
78
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env)
59
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
79
60
- .access = PL1_R, .accessfn = access_lorid,
80
aarch64_save_sp(env, cur_el);
61
+ .access = PL1_R, .accessfn = access_lor_ns,
81
62
.type = ARM_CP_CONST, .resetvalue = 0 },
82
- env->exclusive_addr = -1;
63
REGINFO_SENTINEL
83
+ arm_clear_exclusive(env);
64
};
84
85
/* We must squash the PSTATE.SS bit to zero unless both of the
86
* following hold:
87
--
65
--
88
2.7.4
66
2.20.1
89
67
90
68
diff view generated by jsdifflib
1
Fix an error that meant we were wiring every UART's overflow
1
If we're using the capstone disassembler, disassembly of a run of
2
interrupts into the same inputs 0 and 1 of the OR gate,
2
instructions more than 32 bytes long disassembles the wrong data for
3
rather than giving each its own input.
3
instructions beyond the 32 byte mark:
4
5
(qemu) xp /16x 0x100
6
0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000
7
0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000
8
0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574
9
0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000
10
(qemu) xp /16i 0x100
11
0x00000100: 00000005 andeq r0, r0, r5
12
0x00000104: 54410001 strbpl r0, [r1], #-1
13
0x00000108: 00000001 andeq r0, r0, r1
14
0x0000010c: 00001000 andeq r1, r0, r0
15
0x00000110: 00000000 andeq r0, r0, r0
16
0x00000114: 00000004 andeq r0, r0, r4
17
0x00000118: 54410002 strbpl r0, [r1], #-2
18
0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
19
0x00000120: 54410001 strbpl r0, [r1], #-1
20
0x00000124: 00000001 andeq r0, r0, r1
21
0x00000128: 00001000 andeq r1, r0, r0
22
0x0000012c: 00000000 andeq r0, r0, r0
23
0x00000130: 00000004 andeq r0, r0, r4
24
0x00000134: 54410002 strbpl r0, [r1], #-2
25
0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
26
0x0000013c: 00000000 andeq r0, r0, r0
27
28
Here the disassembly of 0x120..0x13f is using the data that is in
29
0x104..0x123.
30
31
This is caused by passing the wrong value to the read_memory_func().
32
The intention is that at this point in the loop the 'cap_buf' buffer
33
already contains 'csize' bytes of data for the instruction at guest
34
addr 'pc', and we want to read in an extra 'tsize' bytes. Those
35
extra bytes are therefore at 'pc + csize', not 'pc'. On the first
36
time through the loop 'csize' happens to be zero, so the initial read
37
of 32 bytes into cap_buf is correct and as long as the disassembly
38
never needs to read more data we return the correct information.
39
40
Use the correct guest address in the call to read_memory_func().
4
41
5
Cc: qemu-stable@nongnu.org
42
Cc: qemu-stable@nongnu.org
43
Fixes: https://bugs.launchpad.net/qemu/+bug/1900779
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
46
Message-id: 20201022132445.25039-1-peter.maydell@linaro.org
9
Message-id: 1505232834-20890-1-git-send-email-peter.maydell@linaro.org
10
---
47
---
11
hw/arm/mps2.c | 4 ++--
48
disas/capstone.c | 2 +-
12
1 file changed, 2 insertions(+), 2 deletions(-)
49
1 file changed, 1 insertion(+), 1 deletion(-)
13
50
14
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
51
diff --git a/disas/capstone.c b/disas/capstone.c
15
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/mps2.c
53
--- a/disas/capstone.c
17
+++ b/hw/arm/mps2.c
54
+++ b/disas/capstone.c
18
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
55
@@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
19
cmsdk_apb_uart_create(uartbase[i],
56
20
qdev_get_gpio_in(txrx_orgate_dev, 0),
57
/* Make certain that we can make progress. */
21
qdev_get_gpio_in(txrx_orgate_dev, 1),
58
assert(tsize != 0);
22
- qdev_get_gpio_in(orgate_dev, 0),
59
- info->read_memory_func(pc, cap_buf + csize, tsize, info);
23
- qdev_get_gpio_in(orgate_dev, 1),
60
+ info->read_memory_func(pc + csize, cap_buf + csize, tsize, info);
24
+ qdev_get_gpio_in(orgate_dev, i * 2),
61
csize += tsize;
25
+ qdev_get_gpio_in(orgate_dev, i * 2 + 1),
62
26
NULL,
63
if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
27
uartchr, SYSCLK_FRQ);
28
}
29
--
64
--
30
2.7.4
65
2.20.1
31
66
32
67
diff view generated by jsdifflib
1
From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
Let's provide the GPEX host bridge with the INTx/gsi mapping. This is
3
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
4
needed for INTx/gsi routing.
4
This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):
5
5
6
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
6
CID 1432363 (#1 of 1): Unintentional integer overflow:
7
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
7
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
overflow_before_widen:
9
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
Potentially overflowing expression 1 << scale with type int
10
Tested-by: Feng Kan <fkan@apm.com>
10
(32 bits, signed) is evaluated using 32-bit arithmetic, and
11
Message-id: 1505296004-6798-3-git-send-email-eric.auger@redhat.com
11
then used in a context that expects an expression of type
12
hwaddr (64 bits, unsigned).
13
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Acked-by: Eric Auger <eric.auger@redhat.com>
16
Message-id: 20201030144617.1535064-1-philmd@redhat.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
19
---
14
hw/arm/virt.c | 1 +
20
hw/arm/smmuv3.c | 3 ++-
15
1 file changed, 1 insertion(+)
21
1 file changed, 2 insertions(+), 1 deletion(-)
16
22
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
23
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
18
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
25
--- a/hw/arm/smmuv3.c
20
+++ b/hw/arm/virt.c
26
+++ b/hw/arm/smmuv3.c
21
@@ -XXX,XX +XXX,XX @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic)
27
@@ -XXX,XX +XXX,XX @@
22
28
*/
23
for (i = 0; i < GPEX_NUM_IRQS; i++) {
29
24
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
30
#include "qemu/osdep.h"
25
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
31
+#include "qemu/bitops.h"
32
#include "hw/irq.h"
33
#include "hw/sysbus.h"
34
#include "migration/vmstate.h"
35
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
36
scale = CMD_SCALE(cmd);
37
num = CMD_NUM(cmd);
38
ttl = CMD_TTL(cmd);
39
- num_pages = (num + 1) * (1 << (scale));
40
+ num_pages = (num + 1) * BIT_ULL(scale);
26
}
41
}
27
42
28
pci = PCI_HOST_BRIDGE(dev);
43
if (type == SMMU_CMD_TLBI_NH_VA) {
29
--
44
--
30
2.7.4
45
2.20.1
31
46
32
47
diff view generated by jsdifflib
1
From: Jaroslaw Pelczar <j.pelczar@samsung.com>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Previously when single stepping through ERET instruction via GDB
3
When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so
4
would result in debugger entering the "next" PC after ERET instruction.
4
that SVE will not trap to EL3.
5
When debugging in kernel mode, this will also cause unintended behavior,
6
because debugger will try to access memory from EL0 point of view.
7
5
8
Signed-off-by: Jaroslaw Pelczar <j.pelczar@samsung.com>
6
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
9
Message-id: 001c01d32895$483027f0$d89077d0$@samsung.com
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201030151541.11976-1-remi@remlab.net
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/translate-a64.c | 1 +
11
hw/arm/boot.c | 3 +++
14
1 file changed, 1 insertion(+)
12
1 file changed, 3 insertions(+)
15
13
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
16
--- a/hw/arm/boot.c
19
+++ b/target/arm/translate-a64.c
17
+++ b/hw/arm/boot.c
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
18
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
21
default:
19
if (cpu_isar_feature(aa64_mte, cpu)) {
22
gen_a64_set_pc_im(dc->pc);
20
env->cp15.scr_el3 |= SCR_ATA;
23
/* fall through */
21
}
24
+ case DISAS_EXIT:
22
+ if (cpu_isar_feature(aa64_sve, cpu)) {
25
case DISAS_JUMP:
23
+ env->cp15.cptr_el[3] |= CPTR_EZ;
26
if (dc->base.singlestep_enabled) {
24
+ }
27
gen_exception_internal(EXCP_DEBUG);
25
/* AArch64 kernels never boot in secure mode */
26
assert(!info->secure_boot);
27
/* This hook is only supported for AArch32 currently:
28
--
28
--
29
2.7.4
29
2.20.1
30
30
31
31
diff view generated by jsdifflib
1
From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
1
From: AlexChen <alex.chen@huawei.com>
2
2
3
To implement INTx to gsi routing we need to pass the gpex host
3
In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before
4
bridge the gsi associated to each INTx index. Let's introduce
4
being check if it is valid, which may lead to NULL pointer dereference.
5
irq_num array and gpex_set_irq_num setter function.
5
So move the assignment to surface after checking that the omap_lcd is valid
6
and move surface_bits_per_pixel(surface) to after the surface assignment.
6
7
7
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
8
Reported-by: Euler Robot <euler.robot@huawei.com>
8
Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>
9
Signed-off-by: AlexChen <alex.chen@huawei.com>
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 5F9CDB8A.9000001@huawei.com
10
Tested-by: Feng Kan <fkan@apm.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
Message-id: 1505296004-6798-2-git-send-email-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
include/hw/pci-host/gpex.h | 3 +++
14
hw/display/omap_lcdc.c | 10 +++++++---
16
hw/pci-host/gpex.c | 10 ++++++++++
15
1 file changed, 7 insertions(+), 3 deletions(-)
17
2 files changed, 13 insertions(+)
18
16
19
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
17
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/pci-host/gpex.h
19
--- a/hw/display/omap_lcdc.c
22
+++ b/include/hw/pci-host/gpex.h
20
+++ b/hw/display/omap_lcdc.c
23
@@ -XXX,XX +XXX,XX @@ typedef struct GPEXHost {
21
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
24
MemoryRegion io_ioport;
22
static void omap_update_display(void *opaque)
25
MemoryRegion io_mmio;
23
{
26
qemu_irq irq[GPEX_NUM_IRQS];
24
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
27
+ int irq_num[GPEX_NUM_IRQS];
25
- DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
28
} GPEXHost;
26
+ DisplaySurface *surface;
29
27
draw_line_func draw_line;
30
+int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
28
int size, height, first, last;
31
+
29
int width, linesize, step, bpp, frame_offset;
32
#endif /* HW_GPEX_H */
30
hwaddr frame_base;
33
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
31
34
index XXXXXXX..XXXXXXX 100644
32
- if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable ||
35
--- a/hw/pci-host/gpex.c
33
- !surface_bits_per_pixel(surface)) {
36
+++ b/hw/pci-host/gpex.c
34
+ if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) {
37
@@ -XXX,XX +XXX,XX @@ static void gpex_set_irq(void *opaque, int irq_num, int level)
35
+ return;
38
qemu_set_irq(s->irq[irq_num], level);
39
}
40
41
+int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
42
+{
43
+ if (index >= GPEX_NUM_IRQS) {
44
+ return -EINVAL;
45
+ }
36
+ }
46
+
37
+
47
+ s->irq_num[index] = gsi;
38
+ surface = qemu_console_surface(omap_lcd->con);
48
+ return 0;
39
+ if (!surface_bits_per_pixel(surface)) {
49
+}
40
return;
50
+
41
}
51
static void gpex_host_realize(DeviceState *dev, Error **errp)
42
52
{
53
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
54
--
43
--
55
2.7.4
44
2.20.1
56
45
57
46
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: AlexChen <alex.chen@huawei.com>
2
2
3
The EP108 is the same as the ZCU102, mark it as deprecated as we don't
3
In exynos4210_fimd_update(), the pointer s is dereferinced before
4
need two machines.
4
being check if it is valid, which may lead to NULL pointer dereference.
5
So move the assignment to global_width after checking that the s is valid.
5
6
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Signed-off-by: Alex Chen <alex.chen@huawei.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 5F9F8D88.9030102@huawei.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
hw/arm/xlnx-zcu102.c | 2 +-
13
hw/display/exynos4210_fimd.c | 4 +++-
11
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 3 insertions(+), 1 deletion(-)
12
15
13
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
16
diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/xlnx-zcu102.c
18
--- a/hw/display/exynos4210_fimd.c
16
+++ b/hw/arm/xlnx-zcu102.c
19
+++ b/hw/display/exynos4210_fimd.c
17
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
20
@@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque)
18
{
21
bool blend = false;
19
MachineClass *mc = MACHINE_CLASS(oc);
22
uint8_t *host_fb_addr;
20
23
bool is_dirty = false;
21
- mc->desc = "Xilinx ZynqMP EP108 board";
24
- const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
22
+ mc->desc = "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-zcu102)";
25
+ int global_width;
23
mc->init = xlnx_ep108_init;
26
24
mc->block_default_type = IF_IDE;
27
if (!s || !s->console || !s->enabled ||
25
mc->units_per_default_bus = 1;
28
surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
29
return;
30
}
31
+
32
+ global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
33
exynos4210_update_resolution(s);
34
surface = qemu_console_surface(s->console);
35
26
--
36
--
27
2.7.4
37
2.20.1
28
38
29
39
diff view generated by jsdifflib
New patch
1
In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to
2
armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el().
3
This is incorrect when the security state being queried is not the
4
current one, because arm_current_el() uses the current security state
5
to determine which of the banked CONTROL.nPRIV bits to look at.
6
The effect was that if (for instance) Secure state was in privileged
7
mode but Non-Secure was not then we would return the wrong MMU index.
1
8
9
The only places where we are using this function in a way that could
10
trigger this bug are for the stack loads during a v8M function-return
11
and for the instruction fetch of a v8M SG insn.
12
13
Fix the bug by expanding out the M-profile version of the
14
arm_current_el() logic inline so it can use the passed in secstate
15
rather than env->v7m.secure.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20201022164408.13214-1-peter.maydell@linaro.org
20
---
21
target/arm/m_helper.c | 3 ++-
22
1 file changed, 2 insertions(+), 1 deletion(-)
23
24
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/m_helper.c
27
+++ b/target/arm/m_helper.c
28
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
29
/* Return the MMU index for a v7M CPU in the specified security state */
30
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
31
{
32
- bool priv = arm_current_el(env) != 0;
33
+ bool priv = arm_v7m_is_handler_mode(env) ||
34
+ !(env->v7m.control[secstate] & 1);
35
36
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
37
}
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
New patch
1
On some hosts (eg Ubuntu Bionic) pkg-config returns a set of
2
libraries for gio-2.0 which don't actually work when compiling
3
statically. (Specifically, the returned library string includes
4
-lmount, but not -lblkid which -lmount depends upon, so linking
5
fails due to missing symbols.)
1
6
7
Check that the libraries work, and don't enable gio if they don't,
8
in the same way we do for gnutls.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20200928160402.7961-1-peter.maydell@linaro.org
14
---
15
configure | 10 +++++++++-
16
1 file changed, 9 insertions(+), 1 deletion(-)
17
18
diff --git a/configure b/configure
19
index XXXXXXX..XXXXXXX 100755
20
--- a/configure
21
+++ b/configure
22
@@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then
23
fi
24
25
if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
26
- gio=yes
27
gio_cflags=$($pkg_config --cflags gio-2.0)
28
gio_libs=$($pkg_config --libs gio-2.0)
29
gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0)
30
if [ ! -x "$gdbus_codegen" ]; then
31
gdbus_codegen=
32
fi
33
+ # Check that the libraries actually work -- Ubuntu 18.04 ships
34
+ # with pkg-config --static --libs data for gio-2.0 that is missing
35
+ # -lblkid and will give a link error.
36
+ write_c_skeleton
37
+ if compile_prog "" "gio_libs" ; then
38
+ gio=yes
39
+ else
40
+ gio=no
41
+ fi
42
else
43
gio=no
44
fi
45
--
46
2.20.1
47
48
diff view generated by jsdifflib
New patch
1
In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt
2
into the GICv3CPUState struct's maintenance_irq field. This will
3
only work if the board happens to have already wired up the CPU
4
maintenance IRQ before the GIC was realized. Unfortunately this is
5
not the case for the 'virt' board, and so the value that gets copied
6
is NULL (since a qemu_irq is really a pointer to an IRQState struct
7
under the hood). The effect is that the CPU interface code never
8
actually raises the maintenance interrupt line.
1
9
10
Instead, since the GICv3CPUState has a pointer to the CPUState, make
11
the dereference at the point where we want to raise the interrupt, to
12
avoid an implicit requirement on board code to wire things up in a
13
particular order.
14
15
Reported-by: Jose Martins <josemartins90@gmail.com>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20201009153904.28529-1-peter.maydell@linaro.org
18
Reviewed-by: Luc Michel <luc@lmichel.fr>
19
---
20
include/hw/intc/arm_gicv3_common.h | 1 -
21
hw/intc/arm_gicv3_cpuif.c | 5 ++---
22
2 files changed, 2 insertions(+), 4 deletions(-)
23
24
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/intc/arm_gicv3_common.h
27
+++ b/include/hw/intc/arm_gicv3_common.h
28
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
29
qemu_irq parent_fiq;
30
qemu_irq parent_virq;
31
qemu_irq parent_vfiq;
32
- qemu_irq maintenance_irq;
33
34
/* Redistributor */
35
uint32_t level; /* Current IRQ level */
36
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/intc/arm_gicv3_cpuif.c
39
+++ b/hw/intc/arm_gicv3_cpuif.c
40
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
41
int irqlevel = 0;
42
int fiqlevel = 0;
43
int maintlevel = 0;
44
+ ARMCPU *cpu = ARM_CPU(cs->cpu);
45
46
idx = hppvi_index(cs);
47
trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx);
48
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
49
50
qemu_set_irq(cs->parent_vfiq, fiqlevel);
51
qemu_set_irq(cs->parent_virq, irqlevel);
52
- qemu_set_irq(cs->maintenance_irq, maintlevel);
53
+ qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel);
54
}
55
56
static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
57
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
58
&& cpu->gic_num_lrs) {
59
int j;
60
61
- cs->maintenance_irq = cpu->gicv3_maintenance_interrupt;
62
-
63
cs->num_list_regs = cpu->gic_num_lrs;
64
cs->vpribits = cpu->gic_vpribits;
65
cs->vprebits = cpu->gic_vprebits;
66
--
67
2.20.1
68
69
diff view generated by jsdifflib
New patch
1
The kerneldoc script currently emits Sphinx markup for a macro with
2
arguments that uses the c:function directive. This is correct for
3
Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow
4
documentation of macros with arguments and c:function is not picky
5
about the syntax of what it is passed. However, in Sphinx 3 the
6
c:macro directive was enhanced to support macros with arguments,
7
and c:function was made more picky about what syntax it accepted.
1
8
9
When kerneldoc is told that it needs to produce output for Sphinx
10
3 or later, make it emit c:function only for functions and c:macro
11
for macros with arguments. We assume that anything with a return
12
type is a function and anything without is a macro.
13
14
This fixes the Sphinx error:
15
16
/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator
17
If declarator-id with parameters (e.g., 'void f(int arg)'):
18
Invalid C declaration: Expected identifier in nested name. [error at 25]
19
DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME)
20
-------------------------^
21
If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'):
22
Error in declarator or parameters
23
Invalid C declaration: Expecting "(" in parameters. [error at 39]
24
DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME)
25
---------------------------------------^
26
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
29
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
30
Message-id: 20201030174700.7204-2-peter.maydell@linaro.org
31
---
32
scripts/kernel-doc | 18 +++++++++++++++++-
33
1 file changed, 17 insertions(+), 1 deletion(-)
34
35
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
36
index XXXXXXX..XXXXXXX 100755
37
--- a/scripts/kernel-doc
38
+++ b/scripts/kernel-doc
39
@@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) {
40
    output_highlight_rst($args{'purpose'});
41
    $start = "\n\n**Syntax**\n\n ``";
42
} else {
43
-    print ".. c:function:: ";
44
+ if ((split(/\./, $sphinx_version))[0] >= 3) {
45
+ # Sphinx 3 and later distinguish macros and functions and
46
+ # complain if you use c:function with something that's not
47
+ # syntactically valid as a function declaration.
48
+ # We assume that anything with a return type is a function
49
+ # and anything without is a macro.
50
+ if ($args{'functiontype'} ne "") {
51
+ print ".. c:function:: ";
52
+ } else {
53
+ print ".. c:macro:: ";
54
+ }
55
+ } else {
56
+ # Older Sphinx don't support documenting macros that take
57
+ # arguments with c:macro, and don't complain about the use
58
+ # of c:function for this.
59
+ print ".. c:function:: ";
60
+ }
61
}
62
if ($args{'functiontype'} ne "") {
63
    $start .= $args{'functiontype'} . " " . $args{'function'} . " (";
64
--
65
2.20.1
66
67
diff view generated by jsdifflib
1
The exception-return magic values get some new bits in v8M, which
1
Sphinx 3.2 is pickier than earlier versions about the option:: markup,
2
makes some bit definitions for them worthwhile.
2
and complains about our usage in qemu-option-trace.rst:
3
3
4
We don't use the bit definitions for the switch on the low bits
4
../../docs/qemu-option-trace.rst.inc:4:Malformed option description
5
which checks the return type for v7M, because this is defined
5
'[enable=]PATTERN', should look like "opt", "-opt args", "--opt args",
6
in the v7M ARM ARM as a set of valid values rather than via
6
"/opt args" or "+opt args"
7
per-bit checks.
7
8
In this file, we're really trying to document the different parts of
9
the top-level --trace option, which qemu-nbd.rst and qemu-img.rst
10
have already introduced with an option:: markup. So it's not right
11
to use option:: here anyway. Switch to a different markup
12
(definition lists) which gives about the same formatted output.
13
14
(Unlike option::, this markup doesn't produce index entries; but
15
at the moment we don't do anything much with indexes anyway, and
16
in any case I think it doesn't make much sense to have individual
17
index entries for the sub-parts of the --trace option.)
8
18
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
20
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
11
Message-id: 1505137930-13255-7-git-send-email-peter.maydell@linaro.org
21
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
22
Message-id: 20201030174700.7204-3-peter.maydell@linaro.org
12
---
23
---
13
target/arm/internals.h | 10 ++++++++++
24
docs/qemu-option-trace.rst.inc | 6 +++---
14
target/arm/helper.c | 14 +++++++++-----
25
1 file changed, 3 insertions(+), 3 deletions(-)
15
2 files changed, 19 insertions(+), 5 deletions(-)
16
26
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
27
diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc
18
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
29
--- a/docs/qemu-option-trace.rst.inc
20
+++ b/target/arm/internals.h
30
+++ b/docs/qemu-option-trace.rst.inc
21
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CONTROL, NPRIV, 0, 1)
31
@@ -XXX,XX +XXX,XX @@
22
FIELD(V7M_CONTROL, SPSEL, 1, 1)
32
23
FIELD(V7M_CONTROL, FPCA, 2, 1)
33
Specify tracing options.
24
34
25
+/* Bit definitions for v7M exception return payload */
35
-.. option:: [enable=]PATTERN
26
+FIELD(V7M_EXCRET, ES, 0, 1)
36
+``[enable=]PATTERN``
27
+FIELD(V7M_EXCRET, RES0, 1, 1)
37
28
+FIELD(V7M_EXCRET, SPSEL, 2, 1)
38
Immediately enable events matching *PATTERN*
29
+FIELD(V7M_EXCRET, MODE, 3, 1)
39
(either event name or a globbing pattern). This option is only
30
+FIELD(V7M_EXCRET, FTYPE, 4, 1)
40
@@ -XXX,XX +XXX,XX @@ Specify tracing options.
31
+FIELD(V7M_EXCRET, DCRS, 5, 1)
41
32
+FIELD(V7M_EXCRET, S, 6, 1)
42
Use :option:`-trace help` to print a list of names of trace points.
33
+FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
43
34
+
44
-.. option:: events=FILE
35
/*
45
+``events=FILE``
36
* For AArch64, map a given EL to an index in the banked_spsr array.
46
37
* Note that this mapping and the AArch32 mapping defined in bank_number()
47
Immediately enable events listed in *FILE*.
38
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
The file must contain one event name (as listed in the ``trace-events-all``
39
index XXXXXXX..XXXXXXX 100644
49
@@ -XXX,XX +XXX,XX @@ Specify tracing options.
40
--- a/target/arm/helper.c
50
available if QEMU has been compiled with the ``simple``, ``log`` or
41
+++ b/target/arm/helper.c
51
``ftrace`` tracing backend.
42
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
52
43
" previous exception %d\n",
53
-.. option:: file=FILE
44
type, env->v7m.exception);
54
+``file=FILE``
45
55
46
- if (extract32(type, 5, 23) != extract32(-1, 5, 23)) {
56
Log output traces to *FILE*.
47
+ if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
57
This option is only available if QEMU has been compiled with
48
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
49
"exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);
50
}
51
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
52
* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
53
*/
54
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
55
- int es = type & 1;
56
+ int es = type & R_V7M_EXCRET_ES_MASK;
57
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
58
env->v7m.faultmask[es] = 0;
59
}
60
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
61
return; /* Never happens. Keep compiler happy. */
62
}
63
64
- lr = 0xfffffff1;
65
+ lr = R_V7M_EXCRET_RES1_MASK |
66
+ R_V7M_EXCRET_S_MASK |
67
+ R_V7M_EXCRET_DCRS_MASK |
68
+ R_V7M_EXCRET_FTYPE_MASK |
69
+ R_V7M_EXCRET_ES_MASK;
70
if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
71
- lr |= 4;
72
+ lr |= R_V7M_EXCRET_SPSEL_MASK;
73
}
74
if (!arm_v7m_is_handler_mode(env)) {
75
- lr |= 8;
76
+ lr |= R_V7M_EXCRET_MODE_MASK;
77
}
78
79
v7m_push_stack(cpu);
80
--
58
--
81
2.7.4
59
2.20.1
82
60
83
61
diff view generated by jsdifflib
1
Use a symbolic constant M_REG_NUM_BANKS for the array size for
1
The randomness tests in the NPCM7xx RNG test fail intermittently
2
registers which are banked by M profile security state, rather
2
but fairly frequently. On my machine running the test in a loop:
3
than hardcoding lots of 2s.
3
while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done
4
4
5
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
will fail in less than a minute with an error like:
6
ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs:
7
assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01)
8
9
(Failures have been observed on all 4 of the randomness tests,
10
not just first_byte_runs.)
11
12
It's not clear why these tests are failing like this, but intermittent
13
failures make CI and merge testing awkward, so disable running them
14
unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when
15
running the test suite, until we work out the cause.
16
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
19
Message-id: 20201102152454.8287-1-peter.maydell@linaro.org
9
Message-id: 1505137930-13255-2-git-send-email-peter.maydell@linaro.org
20
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
10
---
21
---
11
target/arm/cpu.h | 35 +++++++++++++++++++----------------
22
tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++----
12
1 file changed, 19 insertions(+), 16 deletions(-)
23
1 file changed, 10 insertions(+), 4 deletions(-)
13
24
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
15
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
27
--- a/tests/qtest/npcm7xx_rng-test.c
17
+++ b/target/arm/cpu.h
28
+++ b/tests/qtest/npcm7xx_rng-test.c
18
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
19
* accessed via env->registerfield[env->v7m.secure] (whether the security
30
20
* extension is implemented or not).
31
qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);
21
*/
32
qtest_add_func("npcm7xx_rng/rosel", test_rosel);
22
-#define M_REG_NS 0
33
- qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
23
-#define M_REG_S 1
34
- qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
24
+enum {
35
- qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
25
+ M_REG_NS = 0,
36
- qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
26
+ M_REG_S = 1,
37
+ /*
27
+ M_REG_NUM_BANKS = 2,
38
+ * These tests fail intermittently; only run them on explicit
28
+};
39
+ * request until we figure out why.
29
40
+ */
30
/* ARM-specific interrupt pending bits. */
41
+ if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) {
31
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
42
+ qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
32
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
43
+ qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
33
uint32_t other_sp;
44
+ qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
34
uint32_t other_ss_msp;
45
+ qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
35
uint32_t other_ss_psp;
46
+ }
36
- uint32_t vecbase[2];
47
37
- uint32_t basepri[2];
48
qtest_start("-machine npcm750-evb");
38
- uint32_t control[2];
49
ret = g_test_run();
39
- uint32_t ccr[2]; /* Configuration and Control */
40
- uint32_t cfsr[2]; /* Configurable Fault Status */
41
+ uint32_t vecbase[M_REG_NUM_BANKS];
42
+ uint32_t basepri[M_REG_NUM_BANKS];
43
+ uint32_t control[M_REG_NUM_BANKS];
44
+ uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
45
+ uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
46
uint32_t hfsr; /* HardFault Status */
47
uint32_t dfsr; /* Debug Fault Status Register */
48
- uint32_t mmfar[2]; /* MemManage Fault Address */
49
+ uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
50
uint32_t bfar; /* BusFault Address */
51
- unsigned mpu_ctrl[2]; /* MPU_CTRL */
52
+ unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
53
int exception;
54
- uint32_t primask[2];
55
- uint32_t faultmask[2];
56
+ uint32_t primask[M_REG_NUM_BANKS];
57
+ uint32_t faultmask[M_REG_NUM_BANKS];
58
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
59
} v7m;
60
61
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
62
uint32_t *drbar;
63
uint32_t *drsr;
64
uint32_t *dracr;
65
- uint32_t rnr[2];
66
+ uint32_t rnr[M_REG_NUM_BANKS];
67
} pmsav7;
68
69
/* PMSAv8 MPU */
70
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
71
* pmsav7.rnr (region number register)
72
* pmsav7_dregion (number of configured regions)
73
*/
74
- uint32_t *rbar[2];
75
- uint32_t *rlar[2];
76
- uint32_t mair0[2];
77
- uint32_t mair1[2];
78
+ uint32_t *rbar[M_REG_NUM_BANKS];
79
+ uint32_t *rlar[M_REG_NUM_BANKS];
80
+ uint32_t mair0[M_REG_NUM_BANKS];
81
+ uint32_t mair1[M_REG_NUM_BANKS];
82
} pmsav8;
83
84
void *nvic;
85
--
50
--
86
2.7.4
51
2.20.1
87
52
88
53
diff view generated by jsdifflib