ARM queue: nothing particularly exciting, but 18 patches

is enough to send out.

The following changes since commit 3dabde1128b671f36ac6cb36b97b273139964420:

Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20170914' into staging (2017-09-14 16:33:02 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170914

for you to fetch changes up to ce3bc112cdb1d462e2d52eaa17a7314e7f3af504:

mps2-an511: Fix wiring of UART overflow interrupt lines (2017-09-14 18:43:19 +0100)

* v7M: various code cleanups

* v7M: set correct BFSR bits on bus fault

* v7M: clear exclusive monitor on reset and exception entry/exit

* v7M: don't apply priority mask to negative priorities

* zcu102: support 'secure' and 'virtualization' machine properties

* aarch64: fix ERET single stepping

* gpex: implement PCI INTx routing

* mps2-an511: fix UART overflow interrupt line wiring

Alistair Francis (5):

xlnx-ep108: Rename to ZCU102

xlnx-zcu102: Manually create the machines

xlnx-zcu102: Add a machine level secure property

xlnx-zcu102: Add a machine level virtualization property

xlnx-zcu102: Mark the EP108 machine as deprecated

Jaroslaw Pelczar (1):

AArch64: Fix single stepping of ERET instruction

Peter Maydell (8):

target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2

target/arm: Clear exclusive monitor on v7M reset, exception entry/exit

target/arm: Get PRECISERR and IBUSERR the right way round

nvic: Don't apply group priority mask to negative priorities

target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()

target/arm: Add and use defines for EXCRET constants

target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()

mps2-an511: Fix wiring of UART overflow interrupt lines

Pranavkumar Sawargaonkar (3):

hw/pci-host/gpex: Set INTx index/gsi mapping

hw/arm/virt: Set INTx/gsi mapping

hw/pci-host/gpex: Implement PCI INTx routing

Richard Henderson (1):

target/arm: Avoid an extra temporary for store_exclusive

From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

Now we are able to retrieve the gsi from the INTx pin, let's

enable intx_to_irq routing. From that point on, irqfd becomes

usable along with INTx when assigning a PCIe device.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Andrew Jones <drjones@redhat.com>

Tested-by: Feng Kan <fkan@apm.com>

Message-id: 1505296004-6798-4-git-send-email-eric.auger@redhat.com

hw/pci-host/gpex.c | 12 ++++++++++++

1 file changed, 12 insertions(+)

diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c

--- a/hw/pci-host/gpex.c

+++ b/hw/pci-host/gpex.c

@@ -XXX,XX +XXX,XX @@ int gpex_set_irq_num(GPEXHost *s, int index, int gsi)

return 0;

}

+static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)

+{

+ PCIINTxRoute route;

+ GPEXHost *s = opaque;

+

+ route.mode = PCI_INTX_ENABLED;

+ route.irq = s->irq_num[pin];

+

+ return route;

+}

+

static void gpex_host_realize(DeviceState *dev, Error **errp)

PCIHostState *pci = PCI_HOST_BRIDGE(dev);

@@ -XXX,XX +XXX,XX @@ static void gpex_host_realize(DeviceState *dev, Error **errp)

&s->io_ioport, 0, 4, TYPE_PCIE_BUS);

qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));

+ pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);

qdev_init_nofail(DEVICE(&s->gpex_root));

}

2.7.4

From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

Let's provide the GPEX host bridge with the INTx/gsi mapping. This is

needed for INTx/gsi routing.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Andrew Jones <drjones@redhat.com>

Tested-by: Feng Kan <fkan@apm.com>

Message-id: 1505296004-6798-3-git-send-email-eric.auger@redhat.com

hw/arm/virt.c | 1 +

1 file changed, 1 insertion(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic)

for (i = 0; i < GPEX_NUM_IRQS; i++) {

sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);

+ gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);

}

pci = PCI_HOST_BRIDGE(dev);

2.7.4

From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

To implement INTx to gsi routing we need to pass the gpex host

bridge the gsi associated to each INTx index. Let's introduce

irq_num array and gpex_set_irq_num setter function.

Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

Signed-off-by: Tushar Jagad <tushar.jagad@linaro.org>

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Tested-by: Feng Kan <fkan@apm.com>

Reviewed-by: Andrew Jones <drjones@redhat.com>

Message-id: 1505296004-6798-2-git-send-email-eric.auger@redhat.com

include/hw/pci-host/gpex.h | 3 +++

hw/pci-host/gpex.c | 10 ++++++++++

2 files changed, 13 insertions(+)

diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h

--- a/include/hw/pci-host/gpex.h

+++ b/include/hw/pci-host/gpex.h

@@ -XXX,XX +XXX,XX @@ typedef struct GPEXHost {

MemoryRegion io_ioport;

MemoryRegion io_mmio;

qemu_irq irq[GPEX_NUM_IRQS];

+ int irq_num[GPEX_NUM_IRQS];

} GPEXHost;

+int gpex_set_irq_num(GPEXHost *s, int index, int gsi);

+

#endif /* HW_GPEX_H */

diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/pci-host/gpex.c

+++ b/hw/pci-host/gpex.c

@@ -XXX,XX +XXX,XX @@ static void gpex_set_irq(void *opaque, int irq_num, int level)

qemu_set_irq(s->irq[irq_num], level);

+int gpex_set_irq_num(GPEXHost *s, int index, int gsi)

+{

+ if (index >= GPEX_NUM_IRQS) {

+ return -EINVAL;

+ }

+

+ s->irq_num[index] = gsi;

+ return 0;

+}

+

static void gpex_host_realize(DeviceState *dev, Error **errp)

{

PCIHostState *pci = PCI_HOST_BRIDGE(dev);

2.7.4

From: Richard Henderson <richard.henderson@linaro.org>

Instead of copying addr to a local temp, reuse the value (which we

have just compared as equal) already saved in cpu_exclusive_addr.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>

Message-id: 20170908163859.29820-1-richard.henderson@linaro.org

target/arm/translate-a64.c | 26 +++++++++-----------------

1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,

}

static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,

- TCGv_i64 inaddr, int size, int is_pair)

+ TCGv_i64 addr, int size, int is_pair)

{

/* if (env->exclusive_addr == addr && env->exclusive_val == [addr]

* && (!is_pair || env->exclusive_high == [addr + datasize])) {

@@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,

TCGLabel *fail_label = gen_new_label();

TCGLabel *done_label = gen_new_label();

- TCGv_i64 addr = tcg_temp_local_new_i64();

TCGv_i64 tmp;

- /* Copy input into a local temp so it is not trashed when the

- * basic block ends at the branch insn.

- */

- tcg_gen_mov_i64(addr, inaddr);

tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);

tmp = tcg_temp_new_i64();

@@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,

} else {

tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt));

}

- tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp,

+ tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,

+ cpu_exclusive_val, tmp,

get_mem_index(s),

MO_64 | MO_ALIGN | s->be_data);

tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);

} else if (s->be_data == MO_LE) {

- gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt),

- cpu_reg(s, rt2));

+ gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr,

+ cpu_reg(s, rt), cpu_reg(s, rt2));

} else {

- gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, rt),

- cpu_reg(s, rt2));

+ gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr,

+ cpu_reg(s, rt), cpu_reg(s, rt2));

} else {

- TCGv_i64 val = cpu_reg(s, rt);

- tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val,

- get_mem_index(s),

+ tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,

+ cpu_reg(s, rt), get_mem_index(s),

size | MO_ALIGN | s->be_data);

tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);

}

-

- tcg_temp_free_i64(addr);

-

tcg_gen_mov_i64(cpu_reg(s, rd), tmp);

tcg_temp_free_i64(tmp);

tcg_gen_br(done_label);

2.7.4

The exception-return magic values get some new bits in v8M, which

makes some bit definitions for them worthwhile.

We don't use the bit definitions for the switch on the low bits

which checks the return type for v7M, because this is defined

in the v7M ARM ARM as a set of valid values rather than via

per-bit checks.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>

Message-id: 1505137930-13255-7-git-send-email-peter.maydell@linaro.org

target/arm/internals.h | 10 ++++++++++

target/arm/helper.c | 14 +++++++++-----

2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h

--- a/target/arm/internals.h

+++ b/target/arm/internals.h

@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CONTROL, NPRIV, 0, 1)

FIELD(V7M_CONTROL, SPSEL, 1, 1)

FIELD(V7M_CONTROL, FPCA, 2, 1)

+/* Bit definitions for v7M exception return payload */

+FIELD(V7M_EXCRET, ES, 0, 1)

+FIELD(V7M_EXCRET, RES0, 1, 1)

+FIELD(V7M_EXCRET, SPSEL, 2, 1)

+FIELD(V7M_EXCRET, MODE, 3, 1)

+FIELD(V7M_EXCRET, FTYPE, 4, 1)

+FIELD(V7M_EXCRET, DCRS, 5, 1)

+FIELD(V7M_EXCRET, S, 6, 1)

+FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */

/*

* For AArch64, map a given EL to an index in the banked_spsr array.

* Note that this mapping and the AArch32 mapping defined in bank_number()

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

" previous exception %d\n",

type, env->v7m.exception);

- if (extract32(type, 5, 23) != extract32(-1, 5, 23)) {

+ if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {

qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "

"exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);

}

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)

*/

if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {

- int es = type & 1;

+ int es = type & R_V7M_EXCRET_ES_MASK;

if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {

env->v7m.faultmask[es] = 0;

}

@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)

return; /* Never happens. Keep compiler happy. */

}

- lr = 0xfffffff1;

+ lr = R_V7M_EXCRET_RES1_MASK |

+ R_V7M_EXCRET_S_MASK |

+ R_V7M_EXCRET_DCRS_MASK |

+ R_V7M_EXCRET_FTYPE_MASK |

+ R_V7M_EXCRET_ES_MASK;

if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {

- lr |= 4;

+ lr |= R_V7M_EXCRET_SPSEL_MASK;

}

if (!arm_v7m_is_handler_mode(env)) {

- lr |= 8;

+ lr |= R_V7M_EXCRET_MODE_MASK;

}

v7m_push_stack(cpu);

2.7.4

In the v7M and v8M ARM ARM, the magic exception return values are

referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_*

constants to define bits within them. Rename the 'type' variable

which holds the exception return value in do_v7m_exception_exit()

to excret, making it clearer that it does hold an EXC_RETURN value.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1505137930-13255-8-git-send-email-peter.maydell@linaro.org

target/arm/helper.c | 23 ++++++++++++-----------

1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static void v7m_push_stack(ARMCPU *cpu)

static void do_v7m_exception_exit(ARMCPU *cpu)

{

CPUARMState *env = &cpu->env;

- uint32_t type;

+ uint32_t excret;

uint32_t xpsr;

bool ufault = false;

bool return_to_sp_process = false;

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

* the target value up between env->regs[15] and env->thumb in

* gen_bx(). Reconstitute it.

*/

- type = env->regs[15];

+ excret = env->regs[15];

if (env->thumb) {

- type |= 1;

+ excret |= 1;

}

qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32

" previous exception %d\n",

- type, env->v7m.exception);

+ excret, env->v7m.exception);

- if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {

+ if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {

qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "

- "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);

+ "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n",

+ excret);

}

if (env->v7m.exception != ARMV7M_EXCP_NMI) {

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

* which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)

*/

if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {

- int es = type & R_V7M_EXCRET_ES_MASK;

+ int es = excret & R_V7M_EXCRET_ES_MASK;

if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {

env->v7m.faultmask[es] = 0;

}

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

g_assert_not_reached();

}

- switch (type & 0xf) {

+ switch (excret & 0xf) {

case 1: /* Return to Handler */

return_to_handler = true;

break;

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

*/

env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;

armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

- v7m_exception_taken(cpu, type);

+ v7m_exception_taken(cpu, excret);

qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "

"stackframe: failed exception return integrity check\n");

return;

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

/* The restored xPSR exception field will be zero if we're

* resuming in Thread mode. If that doesn't match what the

- * exception return type specified then this is a UsageFault.

+ * exception return excret specified then this is a UsageFault.

*/

if (return_to_handler != arm_v7m_is_handler_mode(env)) {

/* Take an INVPC UsageFault by pushing the stack again. */

armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;

v7m_push_stack(cpu);

- v7m_exception_taken(cpu, type);

+ v7m_exception_taken(cpu, excret);

qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "

"failed exception return integrity check\n");

return;

2.7.4

In several places we were unconditionally applying the

nvic_gprio_mask() to a priority value. This is incorrect

if the priority is one of the fixed negative priority

values (for NMI and HardFault), so don't do it.

This bug would have caused both NMI and HardFault to be

considered as the same priority and so NMI wouldn't

correctly preempt HardFault.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1505137930-13255-5-git-send-email-peter.maydell@linaro.org

hw/intc/armv7m_nvic.c | 11 +++++++++--

1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state(NVICState *s)

}

}

+ if (active_prio > 0) {

+ active_prio &= nvic_gprio_mask(s);

+ }

s->vectpending = pend_irq;

- s->exception_prio = active_prio & nvic_gprio_mask(s);

+ s->exception_prio = active_prio;

trace_nvic_recompute_state(s->vectpending, s->exception_prio);

}

@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)

assert(vec->enabled);

assert(vec->pending);

- pendgroupprio = vec->prio & nvic_gprio_mask(s);

+ pendgroupprio = vec->prio;

+ if (pendgroupprio > 0) {

+ pendgroupprio &= nvic_gprio_mask(s);

+ }

assert(pendgroupprio < running);

trace_nvic_acknowledge_irq(pending, vec->prio);

2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

hw/arm/xlnx-zcu102.c | 2 +-

diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c

--- a/hw/arm/xlnx-zcu102.c

+++ b/hw/arm/xlnx-zcu102.c

@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)

{

MachineClass *mc = MACHINE_CLASS(oc);

- mc->desc = "Xilinx ZynqMP EP108 board";

+ mc->desc = "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-zcu102)";

mc->init = xlnx_ep108_init;

mc->block_default_type = IF_IDE;

mc->units_per_default_bus = 1;

2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

Add a machine level secure property. This defaults to false and can be

set to true using this machine command line argument:

-machine xlnx-zcu102,secure=on

This follows what the ARM virt machine does.

This property only applies to the ZCU102 machine. The EP108 machine does

not have this property.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/xlnx-zcu102.c | 32 ++++++++++++++++++++++++++++++++

1 file changed, 32 insertions(+)

diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c

--- a/hw/arm/xlnx-zcu102.c

+++ b/hw/arm/xlnx-zcu102.c

@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {

XlnxZynqMPState soc;

MemoryRegion ddr_ram;

+

+ bool secure;

} XlnxZCU102;

#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")

@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {

static struct arm_boot_info xlnx_zcu102_binfo;

+static bool zcu102_get_secure(Object *obj, Error **errp)

+{

+ XlnxZCU102 *s = ZCU102_MACHINE(obj);

+

+ return s->secure;

+}

+

+static void zcu102_set_secure(Object *obj, bool value, Error **errp)

+{

+ XlnxZCU102 *s = ZCU102_MACHINE(obj);

+

+ s->secure = value;

+}

+

static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)

int i;

@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)

object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram),

"ddr-ram", &error_abort);

+ object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",

+ &error_fatal);

object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);

@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_init(MachineState *machine)

static void xlnx_ep108_machine_instance_init(Object *obj)

+ XlnxZCU102 *s = EP108_MACHINE(obj);

+

+ /* EP108, we don't support setting secure */

+ s->secure = false;

static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)

@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)

static void xlnx_zcu102_machine_instance_init(Object *obj)

{

+ XlnxZCU102 *s = ZCU102_MACHINE(obj);

+

+ /* Default to secure mode being disabled */

+ s->secure = false;

+ object_property_add_bool(obj, "secure", zcu102_get_secure,

+ zcu102_set_secure, NULL);

+ object_property_set_description(obj, "secure",

+ "Set on/off to enable/disable the ARM "

+ "Security Extensions (TrustZone)",

+ NULL);

static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)

2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

Add a machine level virtualization property. This defaults to false and can be

set to true using this machine command line argument:

-machine xlnx-zcu102,virtualization=on

This follows what the ARM virt machine does.

This property only applies to the ZCU102 machine. The EP108 machine does

not have this property.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/arm/xlnx-zynqmp.h | 2 ++

hw/arm/xlnx-zcu102.c | 30 +++++++++++++++++++++++++++++-

hw/arm/xlnx-zynqmp.c | 3 ++-

3 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h

--- a/include/hw/arm/xlnx-zynqmp.h

+++ b/include/hw/arm/xlnx-zynqmp.h

@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZynqMPState {

/* Has the ARM Security extensions? */

bool secure;

+ /* Has the ARM Virtualization extensions? */

+ bool virt;

/* Has the RPU subsystem? */

bool has_rpu;

} XlnxZynqMPState;

diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c

--- a/hw/arm/xlnx-zcu102.c

+++ b/hw/arm/xlnx-zcu102.c

@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {

MemoryRegion ddr_ram;

bool secure;

+ bool virt;

} XlnxZCU102;

#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")

@@ -XXX,XX +XXX,XX @@ static void zcu102_set_secure(Object *obj, bool value, Error **errp)

s->secure = value;

+static bool zcu102_get_virt(Object *obj, Error **errp)

+{

+ XlnxZCU102 *s = ZCU102_MACHINE(obj);

+ return s->virt;

+}

+

+static void zcu102_set_virt(Object *obj, bool value, Error **errp)

+{

+ XlnxZCU102 *s = ZCU102_MACHINE(obj);

+

+ s->virt = value;

+}

+

static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)

{

int i;

@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)

"ddr-ram", &error_abort);

object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",

&error_fatal);

+ object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",

+ &error_fatal);

object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);

@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_instance_init(Object *obj)

{

XlnxZCU102 *s = EP108_MACHINE(obj);

- /* EP108, we don't support setting secure */

+ /* EP108, we don't support setting secure or virt */

s->secure = false;

+ s->virt = false;

static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)

@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)

"Set on/off to enable/disable the ARM "

"Security Extensions (TrustZone)",

NULL);

+

+ /* Default to virt (EL2) being disabled */

+ s->virt = false;

+ object_property_add_bool(obj, "virtualization", zcu102_get_virt,

+ zcu102_set_virt, NULL);

+ object_property_set_description(obj, "virtualization",

+ "Set on/off to enable/disable emulating a "

+ "guest CPU which implements the ARM "

+ "Virtualization Extensions",

+ NULL);

}

static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)

diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c

--- a/hw/arm/xlnx-zynqmp.c

+++ b/hw/arm/xlnx-zynqmp.c

@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)

object_property_set_bool(OBJECT(&s->apu_cpu[i]),

s->secure, "has_el3", NULL);

object_property_set_bool(OBJECT(&s->apu_cpu[i]),

- false, "has_el2", NULL);

+ s->virt, "has_el2", NULL);

object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,

"reset-cbar", &error_abort);

object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",

@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)

static Property xlnx_zynqmp_props[] = {

DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),

DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),

+ DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),

DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),

DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,

MemoryRegion *),

2.7.4