1 | Second ARM pull request of this week; this one has my next | 1 | target-arm queue: the big stuff here is the final part of |
---|---|---|---|
2 | set of v8M patches and a handful of more minor stuff from | 2 | rth's patches for Cortex-A76 and Neoverse-N1 support; |
3 | other people. | 3 | also present are Gavin's NUMA series and a few other things. |
4 | 4 | ||
5 | thanks | 5 | thanks |
6 | -- PMM | 6 | -- PMM |
7 | 7 | ||
8 | The following changes since commit 8ee5f9b3ecc94e3eb7a8235f4b2c3ec9024807f6: | 8 | The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b: |
9 | 9 | ||
10 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2017-09-07 10:45:18 +0100) | 10 | Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500) |
11 | 11 | ||
12 | are available in the git repository at: | 12 | are available in the Git repository at: |
13 | 13 | ||
14 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170907 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509 |
15 | 15 | ||
16 | for you to fetch changes up to c99a55d38dd5b5131f3fcbbaf41828a09ee62544: | 16 | for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34: |
17 | 17 | ||
18 | target/arm: Add Jazelle feature (2017-09-07 13:54:55 +0100) | 18 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100) |
19 | 19 | ||
20 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
21 | target-arm: | 21 | target-arm queue: |
22 | * cleanups converting to DEFINE_PROP_LINK | 22 | * MAINTAINERS/.mailmap: update email for Leif Lindholm |
23 | * allwinner-a10: mark as not user-creatable | 23 | * hw/arm: add version information to sbsa-ref machine DT |
24 | * initial patches working towards ARMv8M support | 24 | * Enable new features for -cpu max: |
25 | * implement generating aborts on memory transaction failures | 25 | FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only), |
26 | * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later | 26 | FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH |
27 | * Emulate Cortex-A76 | ||
28 | * Emulate Neoverse-N1 | ||
29 | * Fix the virt board default NUMA topology | ||
27 | 30 | ||
28 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
29 | Fam Zheng (6): | 32 | Gavin Shan (6): |
30 | armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK | 33 | qapi/machine.json: Add cluster-id |
31 | armv7m: Convert armv7m.memory to DEFINE_PROP_LINK | 34 | qtest/numa-test: Specify CPU topology in aarch64_numa_cpu() |
32 | gicv3: Convert to DEFINE_PROP_LINK | 35 | hw/arm/virt: Consider SMP configuration in CPU topology |
33 | xlnx_zynqmp: Convert to DEFINE_PROP_LINK | 36 | qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu() |
34 | xilinx_axienet: Convert to DEFINE_PROP_LINK | 37 | hw/arm/virt: Fix CPU's default NUMA node ID |
35 | xilinx_axidma: Convert to DEFINE_PROP_LINK | 38 | hw/acpi/aml-build: Use existing CPU topology to build PPTT table |
36 | 39 | ||
37 | Peter Maydell (23): | 40 | Leif Lindholm (2): |
38 | target/arm: Implement ARMv8M's PMSAv8 registers | 41 | MAINTAINERS/.mailmap: update email for Leif Lindholm |
39 | target/arm: Implement new PMSAv8 behaviour | 42 | hw/arm: add versioning to sbsa-ref machine DT |
40 | target/arm: Add state field, feature bit and migration for v8M secure state | ||
41 | target/arm: Register second AddressSpace for secure v8M CPUs | ||
42 | target/arm: Add MMU indexes for secure v8M | ||
43 | target/arm: Make BASEPRI register banked for v8M | ||
44 | target/arm: Make PRIMASK register banked for v8M | ||
45 | target/arm: Make FAULTMASK register banked for v8M | ||
46 | target/arm: Make CONTROL register banked for v8M | ||
47 | nvic: Add NS alias SCS region | ||
48 | target/arm: Make VTOR register banked for v8M | ||
49 | target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M | ||
50 | target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M | ||
51 | target/arm: Make MPU_RNR register banked for v8M | ||
52 | target/arm: Make MPU_CTRL register banked for v8M | ||
53 | target/arm: Make CCR register banked for v8M | ||
54 | target/arm: Make MMFAR banked for v8M | ||
55 | target/arm: Make CFSR register banked for v8M | ||
56 | target/arm: Move regime_is_secure() to target/arm/internals.h | ||
57 | target/arm: Implement BXNS, and banked stack pointers | ||
58 | boards.h: Define new flag ignore_memory_transaction_failures | ||
59 | hw/arm: Set ignore_memory_transaction_failures for most ARM boards | ||
60 | target/arm: Implement new do_transaction_failed hook | ||
61 | 43 | ||
62 | Portia Stephens (1): | 44 | Richard Henderson (24): |
63 | target/arm: Add Jazelle feature | 45 | target/arm: Handle cpreg registration for missing EL |
46 | target/arm: Drop EL3 no EL2 fallbacks | ||
47 | target/arm: Merge zcr reginfo | ||
48 | target/arm: Adjust definition of CONTEXTIDR_EL2 | ||
49 | target/arm: Move cortex impdef sysregs to cpu_tcg.c | ||
50 | target/arm: Update qemu-system-arm -cpu max to cortex-a57 | ||
51 | target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max | ||
52 | target/arm: Split out aa32_max_features | ||
53 | target/arm: Annotate arm_max_initfn with FEAT identifiers | ||
54 | target/arm: Use field names for manipulating EL2 and EL3 modes | ||
55 | target/arm: Enable FEAT_Debugv8p2 for -cpu max | ||
56 | target/arm: Enable FEAT_Debugv8p4 for -cpu max | ||
57 | target/arm: Add minimal RAS registers | ||
58 | target/arm: Enable SCR and HCR bits for RAS | ||
59 | target/arm: Implement virtual SError exceptions | ||
60 | target/arm: Implement ESB instruction | ||
61 | target/arm: Enable FEAT_RAS for -cpu max | ||
62 | target/arm: Enable FEAT_IESB for -cpu max | ||
63 | target/arm: Enable FEAT_CSV2 for -cpu max | ||
64 | target/arm: Enable FEAT_CSV2_2 for -cpu max | ||
65 | target/arm: Enable FEAT_CSV3 for -cpu max | ||
66 | target/arm: Enable FEAT_DGH for -cpu max | ||
67 | target/arm: Define cortex-a76 | ||
68 | target/arm: Define neoverse-n1 | ||
64 | 69 | ||
65 | Thomas Huth (1): | 70 | docs/system/arm/emulation.rst | 10 + |
66 | hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false | 71 | docs/system/arm/virt.rst | 2 + |
67 | 72 | qapi/machine.json | 6 +- | |
68 | include/hw/boards.h | 11 ++ | 73 | target/arm/cpregs.h | 11 + |
69 | include/hw/intc/armv7m_nvic.h | 1 + | 74 | target/arm/cpu.h | 23 ++ |
70 | include/qom/cpu.h | 7 +- | 75 | target/arm/helper.h | 1 + |
71 | target/arm/cpu.h | 101 ++++++++++++-- | 76 | target/arm/internals.h | 16 ++ |
72 | target/arm/helper.h | 2 + | 77 | target/arm/syndrome.h | 5 + |
73 | target/arm/internals.h | 36 +++++ | 78 | target/arm/a32.decode | 16 +- |
74 | target/arm/translate.h | 1 + | 79 | target/arm/t32.decode | 18 +- |
75 | hw/arm/allwinner-a10.c | 2 + | 80 | hw/acpi/aml-build.c | 111 ++++---- |
76 | hw/arm/armv7m.c | 16 +-- | 81 | hw/arm/sbsa-ref.c | 16 ++ |
77 | hw/arm/aspeed.c | 3 + | 82 | hw/arm/virt.c | 21 +- |
78 | hw/arm/collie.c | 1 + | 83 | hw/core/machine-hmp-cmds.c | 4 + |
79 | hw/arm/cubieboard.c | 1 + | 84 | hw/core/machine.c | 16 ++ |
80 | hw/arm/digic_boards.c | 1 + | 85 | target/arm/cpu.c | 66 ++++- |
81 | hw/arm/exynos4_boards.c | 2 + | 86 | target/arm/cpu64.c | 353 ++++++++++++++----------- |
82 | hw/arm/gumstix.c | 2 + | 87 | target/arm/cpu_tcg.c | 227 +++++++++++----- |
83 | hw/arm/highbank.c | 2 + | 88 | target/arm/helper.c | 600 +++++++++++++++++++++++++----------------- |
84 | hw/arm/imx25_pdk.c | 1 + | 89 | target/arm/op_helper.c | 43 +++ |
85 | hw/arm/integratorcp.c | 1 + | 90 | target/arm/translate-a64.c | 18 ++ |
86 | hw/arm/kzm.c | 1 + | 91 | target/arm/translate.c | 23 ++ |
87 | hw/arm/mainstone.c | 1 + | 92 | tests/qtest/numa-test.c | 19 +- |
88 | hw/arm/musicpal.c | 1 + | 93 | .mailmap | 3 +- |
89 | hw/arm/netduino2.c | 1 + | 94 | MAINTAINERS | 2 +- |
90 | hw/arm/nseries.c | 2 + | 95 | 25 files changed, 1068 insertions(+), 562 deletions(-) |
91 | hw/arm/omap_sx1.c | 2 + | ||
92 | hw/arm/palm.c | 1 + | ||
93 | hw/arm/raspi.c | 1 + | ||
94 | hw/arm/realview.c | 4 + | ||
95 | hw/arm/sabrelite.c | 1 + | ||
96 | hw/arm/spitz.c | 4 + | ||
97 | hw/arm/stellaris.c | 2 + | ||
98 | hw/arm/tosa.c | 1 + | ||
99 | hw/arm/versatilepb.c | 2 + | ||
100 | hw/arm/vexpress.c | 1 + | ||
101 | hw/arm/xilinx_zynq.c | 1 + | ||
102 | hw/arm/xlnx-ep108.c | 2 + | ||
103 | hw/arm/xlnx-zynqmp.c | 7 +- | ||
104 | hw/arm/z2.c | 1 + | ||
105 | hw/dma/xilinx_axidma.c | 16 +-- | ||
106 | hw/intc/arm_gicv3_its_kvm.c | 19 +-- | ||
107 | hw/intc/armv7m_nvic.c | 291 ++++++++++++++++++++++++++++++++------ | ||
108 | hw/net/xilinx_axienet.c | 16 +-- | ||
109 | qom/cpu.c | 16 +++ | ||
110 | target/arm/cpu.c | 88 +++++++++--- | ||
111 | target/arm/helper.c | 315 +++++++++++++++++++++++++++++++++--------- | ||
112 | target/arm/machine.c | 105 ++++++++++++-- | ||
113 | target/arm/op_helper.c | 43 ++++++ | ||
114 | target/arm/translate.c | 54 +++++++- | ||
115 | scripts/device-crash-test | 1 - | ||
116 | 48 files changed, 978 insertions(+), 213 deletions(-) | ||
117 | diff view generated by jsdifflib |
1 | Set the MachineClass flag ignore_memory_transaction_failures | 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> |
---|---|---|---|
2 | for almost all ARM boards. This means they retain the legacy | ||
3 | behaviour that accesses to unimplemented addresses will RAZ/WI | ||
4 | rather than aborting, when a subsequent commit adds support | ||
5 | for external aborts. | ||
6 | 2 | ||
7 | The exceptions are: | 3 | NUVIA was acquired by Qualcomm in March 2021, but kept functioning on |
8 | * virt -- we know that guests won't try to prod devices | 4 | separate infrastructure for a transitional period. We've now switched |
9 | that we don't describe in the device tree or ACPI tables | 5 | over to contributing as Qualcomm Innovation Center (quicinc), so update |
10 | * mps2 -- this board was written to use unimplemented-device | 6 | my email address to reflect this. |
11 | for all the ranges with devices we don't yet handle | ||
12 | 7 | ||
13 | New boards should not set the flag, but instead be written | 8 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> |
14 | like the mps2. | 9 | Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com |
10 | Cc: Leif Lindholm <leif@nuviainc.com> | ||
11 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | [Fixed commit message typo] | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | .mailmap | 3 ++- | ||
17 | MAINTAINERS | 2 +- | ||
18 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
15 | 19 | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | diff --git a/.mailmap b/.mailmap |
17 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
18 | Message-id: 1504626814-23124-3-git-send-email-peter.maydell@linaro.org | ||
19 | For the Xilinx boards: | ||
20 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
21 | --- | ||
22 | hw/arm/aspeed.c | 3 +++ | ||
23 | hw/arm/collie.c | 1 + | ||
24 | hw/arm/cubieboard.c | 1 + | ||
25 | hw/arm/digic_boards.c | 1 + | ||
26 | hw/arm/exynos4_boards.c | 2 ++ | ||
27 | hw/arm/gumstix.c | 2 ++ | ||
28 | hw/arm/highbank.c | 2 ++ | ||
29 | hw/arm/imx25_pdk.c | 1 + | ||
30 | hw/arm/integratorcp.c | 1 + | ||
31 | hw/arm/kzm.c | 1 + | ||
32 | hw/arm/mainstone.c | 1 + | ||
33 | hw/arm/musicpal.c | 1 + | ||
34 | hw/arm/netduino2.c | 1 + | ||
35 | hw/arm/nseries.c | 2 ++ | ||
36 | hw/arm/omap_sx1.c | 2 ++ | ||
37 | hw/arm/palm.c | 1 + | ||
38 | hw/arm/raspi.c | 1 + | ||
39 | hw/arm/realview.c | 4 ++++ | ||
40 | hw/arm/sabrelite.c | 1 + | ||
41 | hw/arm/spitz.c | 4 ++++ | ||
42 | hw/arm/stellaris.c | 2 ++ | ||
43 | hw/arm/tosa.c | 1 + | ||
44 | hw/arm/versatilepb.c | 2 ++ | ||
45 | hw/arm/vexpress.c | 1 + | ||
46 | hw/arm/xilinx_zynq.c | 1 + | ||
47 | hw/arm/xlnx-ep108.c | 2 ++ | ||
48 | hw/arm/z2.c | 1 + | ||
49 | 27 files changed, 43 insertions(+) | ||
50 | |||
51 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
53 | --- a/hw/arm/aspeed.c | 22 | --- a/.mailmap |
54 | +++ b/hw/arm/aspeed.c | 23 | +++ b/.mailmap |
55 | @@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data) | 24 | @@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com> |
56 | mc->no_floppy = 1; | 25 | Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> |
57 | mc->no_cdrom = 1; | 26 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> |
58 | mc->no_parallel = 1; | 27 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> |
59 | + mc->ignore_memory_transaction_failures = true; | 28 | -Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org> |
60 | } | 29 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> |
61 | 30 | +Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> | |
62 | static const TypeInfo palmetto_bmc_type = { | 31 | Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org> |
63 | @@ -XXX,XX +XXX,XX @@ static void ast2500_evb_class_init(ObjectClass *oc, void *data) | 32 | Paul Burton <paulburton@kernel.org> <paul.burton@mips.com> |
64 | mc->no_floppy = 1; | 33 | Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com> |
65 | mc->no_cdrom = 1; | 34 | diff --git a/MAINTAINERS b/MAINTAINERS |
66 | mc->no_parallel = 1; | ||
67 | + mc->ignore_memory_transaction_failures = true; | ||
68 | } | ||
69 | |||
70 | static const TypeInfo ast2500_evb_type = { | ||
71 | @@ -XXX,XX +XXX,XX @@ static void romulus_bmc_class_init(ObjectClass *oc, void *data) | ||
72 | mc->no_floppy = 1; | ||
73 | mc->no_cdrom = 1; | ||
74 | mc->no_parallel = 1; | ||
75 | + mc->ignore_memory_transaction_failures = true; | ||
76 | } | ||
77 | |||
78 | static const TypeInfo romulus_bmc_type = { | ||
79 | diff --git a/hw/arm/collie.c b/hw/arm/collie.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
81 | --- a/hw/arm/collie.c | 36 | --- a/MAINTAINERS |
82 | +++ b/hw/arm/collie.c | 37 | +++ b/MAINTAINERS |
83 | @@ -XXX,XX +XXX,XX @@ static void collie_machine_init(MachineClass *mc) | 38 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h |
84 | { | 39 | SBSA-REF |
85 | mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)"; | 40 | M: Radoslaw Biernacki <rad@semihalf.com> |
86 | mc->init = collie_init; | 41 | M: Peter Maydell <peter.maydell@linaro.org> |
87 | + mc->ignore_memory_transaction_failures = true; | 42 | -R: Leif Lindholm <leif@nuviainc.com> |
88 | } | 43 | +R: Leif Lindholm <quic_llindhol@quicinc.com> |
89 | 44 | L: qemu-arm@nongnu.org | |
90 | DEFINE_MACHINE("collie", collie_machine_init) | 45 | S: Maintained |
91 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | 46 | F: hw/arm/sbsa-ref.c |
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/hw/arm/cubieboard.c | ||
94 | +++ b/hw/arm/cubieboard.c | ||
95 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_machine_init(MachineClass *mc) | ||
96 | mc->init = cubieboard_init; | ||
97 | mc->block_default_type = IF_IDE; | ||
98 | mc->units_per_default_bus = 1; | ||
99 | + mc->ignore_memory_transaction_failures = true; | ||
100 | } | ||
101 | |||
102 | DEFINE_MACHINE("cubieboard", cubieboard_machine_init) | ||
103 | diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/hw/arm/digic_boards.c | ||
106 | +++ b/hw/arm/digic_boards.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static void canon_a1100_machine_init(MachineClass *mc) | ||
108 | { | ||
109 | mc->desc = "Canon PowerShot A1100 IS"; | ||
110 | mc->init = &canon_a1100_init; | ||
111 | + mc->ignore_memory_transaction_failures = true; | ||
112 | } | ||
113 | |||
114 | DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init) | ||
115 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | ||
116 | index XXXXXXX..XXXXXXX 100644 | ||
117 | --- a/hw/arm/exynos4_boards.c | ||
118 | +++ b/hw/arm/exynos4_boards.c | ||
119 | @@ -XXX,XX +XXX,XX @@ static void nuri_class_init(ObjectClass *oc, void *data) | ||
120 | mc->desc = "Samsung NURI board (Exynos4210)"; | ||
121 | mc->init = nuri_init; | ||
122 | mc->max_cpus = EXYNOS4210_NCPUS; | ||
123 | + mc->ignore_memory_transaction_failures = true; | ||
124 | } | ||
125 | |||
126 | static const TypeInfo nuri_type = { | ||
127 | @@ -XXX,XX +XXX,XX @@ static void smdkc210_class_init(ObjectClass *oc, void *data) | ||
128 | mc->desc = "Samsung SMDKC210 board (Exynos4210)"; | ||
129 | mc->init = smdkc210_init; | ||
130 | mc->max_cpus = EXYNOS4210_NCPUS; | ||
131 | + mc->ignore_memory_transaction_failures = true; | ||
132 | } | ||
133 | |||
134 | static const TypeInfo smdkc210_type = { | ||
135 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | ||
136 | index XXXXXXX..XXXXXXX 100644 | ||
137 | --- a/hw/arm/gumstix.c | ||
138 | +++ b/hw/arm/gumstix.c | ||
139 | @@ -XXX,XX +XXX,XX @@ static void connex_class_init(ObjectClass *oc, void *data) | ||
140 | |||
141 | mc->desc = "Gumstix Connex (PXA255)"; | ||
142 | mc->init = connex_init; | ||
143 | + mc->ignore_memory_transaction_failures = true; | ||
144 | } | ||
145 | |||
146 | static const TypeInfo connex_type = { | ||
147 | @@ -XXX,XX +XXX,XX @@ static void verdex_class_init(ObjectClass *oc, void *data) | ||
148 | |||
149 | mc->desc = "Gumstix Verdex (PXA270)"; | ||
150 | mc->init = verdex_init; | ||
151 | + mc->ignore_memory_transaction_failures = true; | ||
152 | } | ||
153 | |||
154 | static const TypeInfo verdex_type = { | ||
155 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
156 | index XXXXXXX..XXXXXXX 100644 | ||
157 | --- a/hw/arm/highbank.c | ||
158 | +++ b/hw/arm/highbank.c | ||
159 | @@ -XXX,XX +XXX,XX @@ static void highbank_class_init(ObjectClass *oc, void *data) | ||
160 | mc->block_default_type = IF_IDE; | ||
161 | mc->units_per_default_bus = 1; | ||
162 | mc->max_cpus = 4; | ||
163 | + mc->ignore_memory_transaction_failures = true; | ||
164 | } | ||
165 | |||
166 | static const TypeInfo highbank_type = { | ||
167 | @@ -XXX,XX +XXX,XX @@ static void midway_class_init(ObjectClass *oc, void *data) | ||
168 | mc->block_default_type = IF_IDE; | ||
169 | mc->units_per_default_bus = 1; | ||
170 | mc->max_cpus = 4; | ||
171 | + mc->ignore_memory_transaction_failures = true; | ||
172 | } | ||
173 | |||
174 | static const TypeInfo midway_type = { | ||
175 | diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c | ||
176 | index XXXXXXX..XXXXXXX 100644 | ||
177 | --- a/hw/arm/imx25_pdk.c | ||
178 | +++ b/hw/arm/imx25_pdk.c | ||
179 | @@ -XXX,XX +XXX,XX @@ static void imx25_pdk_machine_init(MachineClass *mc) | ||
180 | { | ||
181 | mc->desc = "ARM i.MX25 PDK board (ARM926)"; | ||
182 | mc->init = imx25_pdk_init; | ||
183 | + mc->ignore_memory_transaction_failures = true; | ||
184 | } | ||
185 | |||
186 | DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init) | ||
187 | diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c | ||
188 | index XXXXXXX..XXXXXXX 100644 | ||
189 | --- a/hw/arm/integratorcp.c | ||
190 | +++ b/hw/arm/integratorcp.c | ||
191 | @@ -XXX,XX +XXX,XX @@ static void integratorcp_machine_init(MachineClass *mc) | ||
192 | { | ||
193 | mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; | ||
194 | mc->init = integratorcp_init; | ||
195 | + mc->ignore_memory_transaction_failures = true; | ||
196 | } | ||
197 | |||
198 | DEFINE_MACHINE("integratorcp", integratorcp_machine_init) | ||
199 | diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/hw/arm/kzm.c | ||
202 | +++ b/hw/arm/kzm.c | ||
203 | @@ -XXX,XX +XXX,XX @@ static void kzm_machine_init(MachineClass *mc) | ||
204 | { | ||
205 | mc->desc = "ARM KZM Emulation Baseboard (ARM1136)"; | ||
206 | mc->init = kzm_init; | ||
207 | + mc->ignore_memory_transaction_failures = true; | ||
208 | } | ||
209 | |||
210 | DEFINE_MACHINE("kzm", kzm_machine_init) | ||
211 | diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c | ||
212 | index XXXXXXX..XXXXXXX 100644 | ||
213 | --- a/hw/arm/mainstone.c | ||
214 | +++ b/hw/arm/mainstone.c | ||
215 | @@ -XXX,XX +XXX,XX @@ static void mainstone2_machine_init(MachineClass *mc) | ||
216 | { | ||
217 | mc->desc = "Mainstone II (PXA27x)"; | ||
218 | mc->init = mainstone_init; | ||
219 | + mc->ignore_memory_transaction_failures = true; | ||
220 | } | ||
221 | |||
222 | DEFINE_MACHINE("mainstone", mainstone2_machine_init) | ||
223 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
224 | index XXXXXXX..XXXXXXX 100644 | ||
225 | --- a/hw/arm/musicpal.c | ||
226 | +++ b/hw/arm/musicpal.c | ||
227 | @@ -XXX,XX +XXX,XX @@ static void musicpal_machine_init(MachineClass *mc) | ||
228 | { | ||
229 | mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; | ||
230 | mc->init = musicpal_init; | ||
231 | + mc->ignore_memory_transaction_failures = true; | ||
232 | } | ||
233 | |||
234 | DEFINE_MACHINE("musicpal", musicpal_machine_init) | ||
235 | diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c | ||
236 | index XXXXXXX..XXXXXXX 100644 | ||
237 | --- a/hw/arm/netduino2.c | ||
238 | +++ b/hw/arm/netduino2.c | ||
239 | @@ -XXX,XX +XXX,XX @@ static void netduino2_machine_init(MachineClass *mc) | ||
240 | { | ||
241 | mc->desc = "Netduino 2 Machine"; | ||
242 | mc->init = netduino2_init; | ||
243 | + mc->ignore_memory_transaction_failures = true; | ||
244 | } | ||
245 | |||
246 | DEFINE_MACHINE("netduino2", netduino2_machine_init) | ||
247 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
248 | index XXXXXXX..XXXXXXX 100644 | ||
249 | --- a/hw/arm/nseries.c | ||
250 | +++ b/hw/arm/nseries.c | ||
251 | @@ -XXX,XX +XXX,XX @@ static void n800_class_init(ObjectClass *oc, void *data) | ||
252 | mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)"; | ||
253 | mc->init = n800_init; | ||
254 | mc->default_boot_order = ""; | ||
255 | + mc->ignore_memory_transaction_failures = true; | ||
256 | } | ||
257 | |||
258 | static const TypeInfo n800_type = { | ||
259 | @@ -XXX,XX +XXX,XX @@ static void n810_class_init(ObjectClass *oc, void *data) | ||
260 | mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)"; | ||
261 | mc->init = n810_init; | ||
262 | mc->default_boot_order = ""; | ||
263 | + mc->ignore_memory_transaction_failures = true; | ||
264 | } | ||
265 | |||
266 | static const TypeInfo n810_type = { | ||
267 | diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c | ||
268 | index XXXXXXX..XXXXXXX 100644 | ||
269 | --- a/hw/arm/omap_sx1.c | ||
270 | +++ b/hw/arm/omap_sx1.c | ||
271 | @@ -XXX,XX +XXX,XX @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) | ||
272 | |||
273 | mc->desc = "Siemens SX1 (OMAP310) V2"; | ||
274 | mc->init = sx1_init_v2; | ||
275 | + mc->ignore_memory_transaction_failures = true; | ||
276 | } | ||
277 | |||
278 | static const TypeInfo sx1_machine_v2_type = { | ||
279 | @@ -XXX,XX +XXX,XX @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) | ||
280 | |||
281 | mc->desc = "Siemens SX1 (OMAP310) V1"; | ||
282 | mc->init = sx1_init_v1; | ||
283 | + mc->ignore_memory_transaction_failures = true; | ||
284 | } | ||
285 | |||
286 | static const TypeInfo sx1_machine_v1_type = { | ||
287 | diff --git a/hw/arm/palm.c b/hw/arm/palm.c | ||
288 | index XXXXXXX..XXXXXXX 100644 | ||
289 | --- a/hw/arm/palm.c | ||
290 | +++ b/hw/arm/palm.c | ||
291 | @@ -XXX,XX +XXX,XX @@ static void palmte_machine_init(MachineClass *mc) | ||
292 | { | ||
293 | mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)"; | ||
294 | mc->init = palmte_init; | ||
295 | + mc->ignore_memory_transaction_failures = true; | ||
296 | } | ||
297 | |||
298 | DEFINE_MACHINE("cheetah", palmte_machine_init) | ||
299 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
300 | index XXXXXXX..XXXXXXX 100644 | ||
301 | --- a/hw/arm/raspi.c | ||
302 | +++ b/hw/arm/raspi.c | ||
303 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | ||
304 | mc->no_cdrom = 1; | ||
305 | mc->max_cpus = BCM2836_NCPUS; | ||
306 | mc->default_ram_size = 1024 * 1024 * 1024; | ||
307 | + mc->ignore_memory_transaction_failures = true; | ||
308 | }; | ||
309 | DEFINE_MACHINE("raspi2", raspi2_machine_init) | ||
310 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | ||
311 | index XXXXXXX..XXXXXXX 100644 | ||
312 | --- a/hw/arm/realview.c | ||
313 | +++ b/hw/arm/realview.c | ||
314 | @@ -XXX,XX +XXX,XX @@ static void realview_eb_class_init(ObjectClass *oc, void *data) | ||
315 | mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; | ||
316 | mc->init = realview_eb_init; | ||
317 | mc->block_default_type = IF_SCSI; | ||
318 | + mc->ignore_memory_transaction_failures = true; | ||
319 | } | ||
320 | |||
321 | static const TypeInfo realview_eb_type = { | ||
322 | @@ -XXX,XX +XXX,XX @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) | ||
323 | mc->init = realview_eb_mpcore_init; | ||
324 | mc->block_default_type = IF_SCSI; | ||
325 | mc->max_cpus = 4; | ||
326 | + mc->ignore_memory_transaction_failures = true; | ||
327 | } | ||
328 | |||
329 | static const TypeInfo realview_eb_mpcore_type = { | ||
330 | @@ -XXX,XX +XXX,XX @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data) | ||
331 | |||
332 | mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; | ||
333 | mc->init = realview_pb_a8_init; | ||
334 | + mc->ignore_memory_transaction_failures = true; | ||
335 | } | ||
336 | |||
337 | static const TypeInfo realview_pb_a8_type = { | ||
338 | @@ -XXX,XX +XXX,XX @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) | ||
339 | mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; | ||
340 | mc->init = realview_pbx_a9_init; | ||
341 | mc->max_cpus = 4; | ||
342 | + mc->ignore_memory_transaction_failures = true; | ||
343 | } | ||
344 | |||
345 | static const TypeInfo realview_pbx_a9_type = { | ||
346 | diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c | ||
347 | index XXXXXXX..XXXXXXX 100644 | ||
348 | --- a/hw/arm/sabrelite.c | ||
349 | +++ b/hw/arm/sabrelite.c | ||
350 | @@ -XXX,XX +XXX,XX @@ static void sabrelite_machine_init(MachineClass *mc) | ||
351 | mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; | ||
352 | mc->init = sabrelite_init; | ||
353 | mc->max_cpus = FSL_IMX6_NUM_CPUS; | ||
354 | + mc->ignore_memory_transaction_failures = true; | ||
355 | } | ||
356 | |||
357 | DEFINE_MACHINE("sabrelite", sabrelite_machine_init) | ||
358 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | ||
359 | index XXXXXXX..XXXXXXX 100644 | ||
360 | --- a/hw/arm/spitz.c | ||
361 | +++ b/hw/arm/spitz.c | ||
362 | @@ -XXX,XX +XXX,XX @@ static void akitapda_class_init(ObjectClass *oc, void *data) | ||
363 | |||
364 | mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; | ||
365 | mc->init = akita_init; | ||
366 | + mc->ignore_memory_transaction_failures = true; | ||
367 | } | ||
368 | |||
369 | static const TypeInfo akitapda_type = { | ||
370 | @@ -XXX,XX +XXX,XX @@ static void spitzpda_class_init(ObjectClass *oc, void *data) | ||
371 | mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)"; | ||
372 | mc->init = spitz_init; | ||
373 | mc->block_default_type = IF_IDE; | ||
374 | + mc->ignore_memory_transaction_failures = true; | ||
375 | } | ||
376 | |||
377 | static const TypeInfo spitzpda_type = { | ||
378 | @@ -XXX,XX +XXX,XX @@ static void borzoipda_class_init(ObjectClass *oc, void *data) | ||
379 | mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; | ||
380 | mc->init = borzoi_init; | ||
381 | mc->block_default_type = IF_IDE; | ||
382 | + mc->ignore_memory_transaction_failures = true; | ||
383 | } | ||
384 | |||
385 | static const TypeInfo borzoipda_type = { | ||
386 | @@ -XXX,XX +XXX,XX @@ static void terrierpda_class_init(ObjectClass *oc, void *data) | ||
387 | mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)"; | ||
388 | mc->init = terrier_init; | ||
389 | mc->block_default_type = IF_IDE; | ||
390 | + mc->ignore_memory_transaction_failures = true; | ||
391 | } | ||
392 | |||
393 | static const TypeInfo terrierpda_type = { | ||
394 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | ||
395 | index XXXXXXX..XXXXXXX 100644 | ||
396 | --- a/hw/arm/stellaris.c | ||
397 | +++ b/hw/arm/stellaris.c | ||
398 | @@ -XXX,XX +XXX,XX @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data) | ||
399 | |||
400 | mc->desc = "Stellaris LM3S811EVB"; | ||
401 | mc->init = lm3s811evb_init; | ||
402 | + mc->ignore_memory_transaction_failures = true; | ||
403 | } | ||
404 | |||
405 | static const TypeInfo lm3s811evb_type = { | ||
406 | @@ -XXX,XX +XXX,XX @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) | ||
407 | |||
408 | mc->desc = "Stellaris LM3S6965EVB"; | ||
409 | mc->init = lm3s6965evb_init; | ||
410 | + mc->ignore_memory_transaction_failures = true; | ||
411 | } | ||
412 | |||
413 | static const TypeInfo lm3s6965evb_type = { | ||
414 | diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c | ||
415 | index XXXXXXX..XXXXXXX 100644 | ||
416 | --- a/hw/arm/tosa.c | ||
417 | +++ b/hw/arm/tosa.c | ||
418 | @@ -XXX,XX +XXX,XX @@ static void tosapda_machine_init(MachineClass *mc) | ||
419 | mc->desc = "Sharp SL-6000 (Tosa) PDA (PXA255)"; | ||
420 | mc->init = tosa_init; | ||
421 | mc->block_default_type = IF_IDE; | ||
422 | + mc->ignore_memory_transaction_failures = true; | ||
423 | } | ||
424 | |||
425 | DEFINE_MACHINE("tosa", tosapda_machine_init) | ||
426 | diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c | ||
427 | index XXXXXXX..XXXXXXX 100644 | ||
428 | --- a/hw/arm/versatilepb.c | ||
429 | +++ b/hw/arm/versatilepb.c | ||
430 | @@ -XXX,XX +XXX,XX @@ static void versatilepb_class_init(ObjectClass *oc, void *data) | ||
431 | mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; | ||
432 | mc->init = vpb_init; | ||
433 | mc->block_default_type = IF_SCSI; | ||
434 | + mc->ignore_memory_transaction_failures = true; | ||
435 | } | ||
436 | |||
437 | static const TypeInfo versatilepb_type = { | ||
438 | @@ -XXX,XX +XXX,XX @@ static void versatileab_class_init(ObjectClass *oc, void *data) | ||
439 | mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; | ||
440 | mc->init = vab_init; | ||
441 | mc->block_default_type = IF_SCSI; | ||
442 | + mc->ignore_memory_transaction_failures = true; | ||
443 | } | ||
444 | |||
445 | static const TypeInfo versatileab_type = { | ||
446 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | ||
447 | index XXXXXXX..XXXXXXX 100644 | ||
448 | --- a/hw/arm/vexpress.c | ||
449 | +++ b/hw/arm/vexpress.c | ||
450 | @@ -XXX,XX +XXX,XX @@ static void vexpress_class_init(ObjectClass *oc, void *data) | ||
451 | mc->desc = "ARM Versatile Express"; | ||
452 | mc->init = vexpress_common_init; | ||
453 | mc->max_cpus = 4; | ||
454 | + mc->ignore_memory_transaction_failures = true; | ||
455 | } | ||
456 | |||
457 | static void vexpress_a9_class_init(ObjectClass *oc, void *data) | ||
458 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c | ||
459 | index XXXXXXX..XXXXXXX 100644 | ||
460 | --- a/hw/arm/xilinx_zynq.c | ||
461 | +++ b/hw/arm/xilinx_zynq.c | ||
462 | @@ -XXX,XX +XXX,XX @@ static void zynq_machine_init(MachineClass *mc) | ||
463 | mc->init = zynq_init; | ||
464 | mc->max_cpus = 1; | ||
465 | mc->no_sdcard = 1; | ||
466 | + mc->ignore_memory_transaction_failures = true; | ||
467 | } | ||
468 | |||
469 | DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) | ||
470 | diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c | ||
471 | index XXXXXXX..XXXXXXX 100644 | ||
472 | --- a/hw/arm/xlnx-ep108.c | ||
473 | +++ b/hw/arm/xlnx-ep108.c | ||
474 | @@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_init(MachineClass *mc) | ||
475 | mc->init = xlnx_ep108_init; | ||
476 | mc->block_default_type = IF_IDE; | ||
477 | mc->units_per_default_bus = 1; | ||
478 | + mc->ignore_memory_transaction_failures = true; | ||
479 | } | ||
480 | |||
481 | DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) | ||
482 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_init(MachineClass *mc) | ||
483 | mc->init = xlnx_ep108_init; | ||
484 | mc->block_default_type = IF_IDE; | ||
485 | mc->units_per_default_bus = 1; | ||
486 | + mc->ignore_memory_transaction_failures = true; | ||
487 | } | ||
488 | |||
489 | DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) | ||
490 | diff --git a/hw/arm/z2.c b/hw/arm/z2.c | ||
491 | index XXXXXXX..XXXXXXX 100644 | ||
492 | --- a/hw/arm/z2.c | ||
493 | +++ b/hw/arm/z2.c | ||
494 | @@ -XXX,XX +XXX,XX @@ static void z2_machine_init(MachineClass *mc) | ||
495 | { | ||
496 | mc->desc = "Zipit Z2 (PXA27x)"; | ||
497 | mc->init = z2_init; | ||
498 | + mc->ignore_memory_transaction_failures = true; | ||
499 | } | ||
500 | |||
501 | DEFINE_MACHINE("z2", z2_machine_init) | ||
502 | -- | 47 | -- |
503 | 2.7.4 | 48 | 2.25.1 |
504 | 49 | ||
505 | 50 | diff view generated by jsdifflib |
1 | Make the CONTROL register banked if v8M security extensions are enabled. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | More gracefully handle cpregs when EL2 and/or EL3 are missing. | ||
4 | If the reg is entirely inaccessible, do not register it at all. | ||
5 | If the reg is for EL2, and EL3 is present but EL2 is not, | ||
6 | either discard, squash to res0, const, or keep unchanged. | ||
7 | |||
8 | Per rule RJFFP, mark the 4 aarch32 hypervisor access registers | ||
9 | with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address | ||
10 | translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. | ||
11 | Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ. | ||
12 | |||
13 | This will simplify cpreg registration for conditional arm features. | ||
14 | |||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20220506180242.216785-2-richard.henderson@linaro.org | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 1503414539-28762-10-git-send-email-peter.maydell@linaro.org | ||
6 | --- | 19 | --- |
7 | target/arm/cpu.h | 5 +++-- | 20 | target/arm/cpregs.h | 11 +++ |
8 | target/arm/helper.c | 21 +++++++++++---------- | 21 | target/arm/helper.c | 178 ++++++++++++++++++++++++++++++-------------- |
9 | target/arm/machine.c | 3 ++- | 22 | 2 files changed, 133 insertions(+), 56 deletions(-) |
10 | target/arm/translate.c | 2 +- | 23 | |
11 | 4 files changed, 17 insertions(+), 14 deletions(-) | 24 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
12 | |||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.h | 26 | --- a/target/arm/cpregs.h |
16 | +++ b/target/arm/cpu.h | 27 | +++ b/target/arm/cpregs.h |
17 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 28 | @@ -XXX,XX +XXX,XX @@ enum { |
18 | uint32_t other_sp; | 29 | ARM_CP_SVE = 1 << 14, |
19 | uint32_t vecbase; | 30 | /* Flag: Do not expose in gdb sysreg xml. */ |
20 | uint32_t basepri[2]; | 31 | ARM_CP_NO_GDB = 1 << 15, |
21 | - uint32_t control; | 32 | + /* |
22 | + uint32_t control[2]; | 33 | + * Flags: If EL3 but not EL2... |
23 | uint32_t ccr; /* Configuration and Control */ | 34 | + * - UNDEF: discard the cpreg, |
24 | uint32_t cfsr; /* Configurable Fault Status */ | 35 | + * - KEEP: retain the cpreg as is, |
25 | uint32_t hfsr; /* HardFault Status */ | 36 | + * - C_NZ: set const on the cpreg, but retain resetvalue, |
26 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_v7m_is_handler_mode(CPUARMState *env) | 37 | + * - else: set const on the cpreg, zero resetvalue, aka RES0. |
27 | static inline int arm_current_el(CPUARMState *env) | 38 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. |
28 | { | 39 | + */ |
29 | if (arm_feature(env, ARM_FEATURE_M)) { | 40 | + ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, |
30 | - return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); | 41 | + ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, |
31 | + return arm_v7m_is_handler_mode(env) || | 42 | + ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, |
32 | + !(env->v7m.control[env->v7m.secure] & 1); | 43 | }; |
33 | } | 44 | |
34 | 45 | /* | |
35 | if (is_a64(env)) { | ||
36 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 46 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
37 | index XXXXXXX..XXXXXXX 100644 | 47 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/helper.c | 48 | --- a/target/arm/helper.c |
39 | +++ b/target/arm/helper.c | 49 | +++ b/target/arm/helper.c |
40 | @@ -XXX,XX +XXX,XX @@ static uint32_t v7m_pop(CPUARMState *env) | 50 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { |
41 | static void switch_v7m_sp(CPUARMState *env, bool new_spsel) | 51 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
52 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, | ||
53 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | ||
54 | - .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU, | ||
55 | + .access = PL2_RW, | ||
56 | + .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | ||
57 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, | ||
58 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, | ||
59 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | ||
60 | - .access = PL2_RW, .resetvalue = 0, | ||
61 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | ||
62 | .writefn = dacr_write, .raw_writefn = raw_write, | ||
63 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | ||
64 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | ||
65 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | ||
66 | - .access = PL2_RW, .resetvalue = 0, | ||
67 | + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | ||
68 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | ||
69 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | ||
70 | .type = ARM_CP_ALIAS, | ||
71 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
72 | .writefn = tlbimva_hyp_is_write }, | ||
73 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, | ||
74 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | ||
75 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
76 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
77 | .writefn = tlbi_aa64_alle2_write }, | ||
78 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, | ||
79 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | ||
80 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
81 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
82 | .writefn = tlbi_aa64_vae2_write }, | ||
83 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, | ||
84 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | ||
85 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
86 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
87 | .writefn = tlbi_aa64_vae2_write }, | ||
88 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | ||
89 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | ||
90 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
91 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
92 | .writefn = tlbi_aa64_alle2is_write }, | ||
93 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, | ||
94 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | ||
95 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
96 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
97 | .writefn = tlbi_aa64_vae2is_write }, | ||
98 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, | ||
99 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | ||
100 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
101 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
102 | .writefn = tlbi_aa64_vae2is_write }, | ||
103 | #ifndef CONFIG_USER_ONLY | ||
104 | /* Unlike the other EL2-related AT operations, these must | ||
105 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | ||
106 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | ||
108 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
109 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
110 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
111 | + .writefn = ats_write64 }, | ||
112 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | ||
113 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | ||
114 | .access = PL2_W, .accessfn = at_s1e2_access, | ||
115 | - .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, | ||
116 | + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, | ||
117 | + .writefn = ats_write64 }, | ||
118 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE | ||
119 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | ||
120 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | ||
121 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
122 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | ||
123 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | ||
124 | .access = PL2_RW, .accessfn = access_tda, | ||
125 | - .type = ARM_CP_NOP }, | ||
126 | + .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, | ||
127 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
128 | * Channel but Linux may try to access this register. The 32-bit | ||
129 | * alias is DBGDCCINT. | ||
130 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
131 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
132 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, | ||
133 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | ||
134 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
135 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
136 | .writefn = tlbi_aa64_rvae2is_write }, | ||
137 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | ||
138 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | ||
139 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
140 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
141 | .writefn = tlbi_aa64_rvae2is_write }, | ||
142 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | ||
143 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | ||
144 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
145 | .access = PL2_W, .type = ARM_CP_NOP }, | ||
146 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, | ||
147 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | ||
148 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
149 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
150 | .writefn = tlbi_aa64_rvae2is_write }, | ||
151 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | ||
152 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | ||
153 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
154 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
155 | .writefn = tlbi_aa64_rvae2is_write }, | ||
156 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | ||
157 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | ||
158 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
159 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
160 | .writefn = tlbi_aa64_rvae2_write }, | ||
161 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | ||
162 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | ||
163 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
164 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
165 | .writefn = tlbi_aa64_rvae2_write }, | ||
166 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | ||
167 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | ||
168 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
169 | .writefn = tlbi_aa64_vae1is_write }, | ||
170 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, | ||
171 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | ||
172 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
173 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
174 | .writefn = tlbi_aa64_alle2is_write }, | ||
175 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, | ||
176 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | ||
177 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
178 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
179 | .writefn = tlbi_aa64_vae2is_write }, | ||
180 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, | ||
181 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | ||
182 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
183 | .writefn = tlbi_aa64_alle1is_write }, | ||
184 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, | ||
185 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | ||
186 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
187 | + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, | ||
188 | .writefn = tlbi_aa64_vae2is_write }, | ||
189 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, | ||
190 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | ||
191 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
192 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
193 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
194 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
195 | - .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, | ||
196 | + .resetvalue = cpu->midr, | ||
197 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
198 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | ||
199 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
200 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
201 | .access = PL2_RW, .resetvalue = cpu->midr, | ||
202 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
203 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
204 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, | ||
205 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
206 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
207 | - .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, | ||
208 | + .resetvalue = vmpidr_def, | ||
209 | + .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | ||
210 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | ||
211 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
212 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
213 | - .access = PL2_RW, | ||
214 | - .resetvalue = vmpidr_def, | ||
215 | + .access = PL2_RW, .resetvalue = vmpidr_def, | ||
216 | + .type = ARM_CP_EL3_NO_EL2_C_NZ, | ||
217 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | ||
218 | }; | ||
219 | define_arm_cp_regs(cpu, vpidr_regs); | ||
220 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
221 | int crm, int opc1, int opc2, | ||
222 | const char *name) | ||
42 | { | 223 | { |
43 | uint32_t tmp; | 224 | + CPUARMState *env = &cpu->env; |
44 | - bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; | 225 | uint32_t key; |
45 | + uint32_t old_control = env->v7m.control[env->v7m.secure]; | 226 | ARMCPRegInfo *r2; |
46 | + bool old_spsel = old_control & R_V7M_CONTROL_SPSEL_MASK; | 227 | bool is64 = r->type & ARM_CP_64BIT; |
47 | 228 | bool ns = secstate & ARM_CP_SECSTATE_NS; | |
48 | if (old_spsel != new_spsel) { | 229 | int cp = r->cp; |
49 | tmp = env->v7m.other_sp; | 230 | - bool isbanked; |
50 | env->v7m.other_sp = env->regs[13]; | 231 | size_t name_len; |
51 | env->regs[13] = tmp; | 232 | + bool make_const; |
52 | 233 | ||
53 | - env->v7m.control = deposit32(env->v7m.control, | 234 | switch (state) { |
54 | + env->v7m.control[env->v7m.secure] = deposit32(old_control, | 235 | case ARM_CP_STATE_AA32: |
55 | R_V7M_CONTROL_SPSEL_SHIFT, | 236 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
56 | R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); | 237 | } |
57 | } | 238 | } |
58 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 239 | |
240 | + /* | ||
241 | + * Eliminate registers that are not present because the EL is missing. | ||
242 | + * Doing this here makes it easier to put all registers for a given | ||
243 | + * feature into the same ARMCPRegInfo array and define them all at once. | ||
244 | + */ | ||
245 | + make_const = false; | ||
246 | + if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
247 | + /* | ||
248 | + * An EL2 register without EL2 but with EL3 is (usually) RES0. | ||
249 | + * See rule RJFFP in section D1.1.3 of DDI0487H.a. | ||
250 | + */ | ||
251 | + int min_el = ctz32(r->access) / 2; | ||
252 | + if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | ||
253 | + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | ||
254 | + return; | ||
255 | + } | ||
256 | + make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | ||
257 | + } | ||
258 | + } else { | ||
259 | + CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | ||
260 | + ? PL2_RW : PL1_RW); | ||
261 | + if ((r->access & max_el) == 0) { | ||
262 | + return; | ||
263 | + } | ||
264 | + } | ||
265 | + | ||
266 | /* Combine cpreg and name into one allocation. */ | ||
267 | name_len = strlen(name) + 1; | ||
268 | r2 = g_malloc(sizeof(*r2) + name_len); | ||
269 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, | ||
270 | r2->opaque = opaque; | ||
59 | } | 271 | } |
60 | 272 | ||
61 | lr = 0xfffffff1; | 273 | - isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; |
62 | - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { | 274 | - if (isbanked) { |
63 | + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { | 275 | + if (make_const) { |
64 | lr |= 4; | 276 | + /* This should not have been a very special register to begin. */ |
277 | + int old_special = r2->type & ARM_CP_SPECIAL_MASK; | ||
278 | + assert(old_special == 0 || old_special == ARM_CP_NOP); | ||
279 | /* | ||
280 | - * Register is banked (using both entries in array). | ||
281 | - * Overwriting fieldoffset as the array is only used to define | ||
282 | - * banked registers but later only fieldoffset is used. | ||
283 | + * Set the special function to CONST, retaining the other flags. | ||
284 | + * This is important for e.g. ARM_CP_SVE so that we still | ||
285 | + * take the SVE trap if CPTR_EL3.EZ == 0. | ||
286 | */ | ||
287 | - r2->fieldoffset = r->bank_fieldoffsets[ns]; | ||
288 | - } | ||
289 | + r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; | ||
290 | + /* | ||
291 | + * Usually, these registers become RES0, but there are a few | ||
292 | + * special cases like VPIDR_EL2 which have a constant non-zero | ||
293 | + * value with writes ignored. | ||
294 | + */ | ||
295 | + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | ||
296 | + r2->resetvalue = 0; | ||
297 | + } | ||
298 | + /* | ||
299 | + * ARM_CP_CONST has precedence, so removing the callbacks and | ||
300 | + * offsets are not strictly necessary, but it is potentially | ||
301 | + * less confusing to debug later. | ||
302 | + */ | ||
303 | + r2->readfn = NULL; | ||
304 | + r2->writefn = NULL; | ||
305 | + r2->raw_readfn = NULL; | ||
306 | + r2->raw_writefn = NULL; | ||
307 | + r2->resetfn = NULL; | ||
308 | + r2->fieldoffset = 0; | ||
309 | + r2->bank_fieldoffsets[0] = 0; | ||
310 | + r2->bank_fieldoffsets[1] = 0; | ||
311 | + } else { | ||
312 | + bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | ||
313 | |||
314 | - if (state == ARM_CP_STATE_AA32) { | ||
315 | if (isbanked) { | ||
316 | /* | ||
317 | - * If the register is banked then we don't need to migrate or | ||
318 | - * reset the 32-bit instance in certain cases: | ||
319 | - * | ||
320 | - * 1) If the register has both 32-bit and 64-bit instances then we | ||
321 | - * can count on the 64-bit instance taking care of the | ||
322 | - * non-secure bank. | ||
323 | - * 2) If ARMv8 is enabled then we can count on a 64-bit version | ||
324 | - * taking care of the secure bank. This requires that separate | ||
325 | - * 32 and 64-bit definitions are provided. | ||
326 | + * Register is banked (using both entries in array). | ||
327 | + * Overwriting fieldoffset as the array is only used to define | ||
328 | + * banked registers but later only fieldoffset is used. | ||
329 | */ | ||
330 | - if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
331 | - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | ||
332 | + r2->fieldoffset = r->bank_fieldoffsets[ns]; | ||
333 | + } | ||
334 | + if (state == ARM_CP_STATE_AA32) { | ||
335 | + if (isbanked) { | ||
336 | + /* | ||
337 | + * If the register is banked then we don't need to migrate or | ||
338 | + * reset the 32-bit instance in certain cases: | ||
339 | + * | ||
340 | + * 1) If the register has both 32-bit and 64-bit instances | ||
341 | + * then we can count on the 64-bit instance taking care | ||
342 | + * of the non-secure bank. | ||
343 | + * 2) If ARMv8 is enabled then we can count on a 64-bit | ||
344 | + * version taking care of the secure bank. This requires | ||
345 | + * that separate 32 and 64-bit definitions are provided. | ||
346 | + */ | ||
347 | + if ((r->state == ARM_CP_STATE_BOTH && ns) || | ||
348 | + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | ||
349 | + r2->type |= ARM_CP_ALIAS; | ||
350 | + } | ||
351 | + } else if ((secstate != r->secure) && !ns) { | ||
352 | + /* | ||
353 | + * The register is not banked so we only want to allow | ||
354 | + * migration of the non-secure instance. | ||
355 | + */ | ||
356 | r2->type |= ARM_CP_ALIAS; | ||
357 | } | ||
358 | - } else if ((secstate != r->secure) && !ns) { | ||
359 | - /* | ||
360 | - * The register is not banked so we only want to allow migration | ||
361 | - * of the non-secure instance. | ||
362 | - */ | ||
363 | - r2->type |= ARM_CP_ALIAS; | ||
364 | - } | ||
365 | |||
366 | - if (HOST_BIG_ENDIAN && | ||
367 | - r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
368 | - r2->fieldoffset += sizeof(uint32_t); | ||
369 | + if (HOST_BIG_ENDIAN && | ||
370 | + r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | ||
371 | + r2->fieldoffset += sizeof(uint32_t); | ||
372 | + } | ||
373 | } | ||
65 | } | 374 | } |
66 | if (!arm_v7m_is_handler_mode(env)) { | 375 | |
67 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 376 | @@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
68 | return xpsr_read(env) & mask; | 377 | * multiple times. Special registers (ie NOP/WFI) are |
69 | break; | 378 | * never migratable and not even raw-accessible. |
70 | case 20: /* CONTROL */ | 379 | */ |
71 | - return env->v7m.control; | 380 | - if (r->type & ARM_CP_SPECIAL_MASK) { |
72 | + return env->v7m.control[env->v7m.secure]; | 381 | + if (r2->type & ARM_CP_SPECIAL_MASK) { |
382 | r2->type |= ARM_CP_NO_RAW; | ||
73 | } | 383 | } |
74 | 384 | if (((r->crm == CP_ANY) && crm != 0) || | |
75 | if (el == 0) { | ||
76 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
77 | |||
78 | switch (reg) { | ||
79 | case 8: /* MSP */ | ||
80 | - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? | ||
81 | + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? | ||
82 | env->v7m.other_sp : env->regs[13]; | ||
83 | case 9: /* PSP */ | ||
84 | - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? | ||
85 | + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? | ||
86 | env->regs[13] : env->v7m.other_sp; | ||
87 | case 16: /* PRIMASK */ | ||
88 | return env->v7m.primask[env->v7m.secure]; | ||
89 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
90 | } | ||
91 | break; | ||
92 | case 8: /* MSP */ | ||
93 | - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { | ||
94 | + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { | ||
95 | env->v7m.other_sp = val; | ||
96 | } else { | ||
97 | env->regs[13] = val; | ||
98 | } | ||
99 | break; | ||
100 | case 9: /* PSP */ | ||
101 | - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { | ||
102 | + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { | ||
103 | env->regs[13] = val; | ||
104 | } else { | ||
105 | env->v7m.other_sp = val; | ||
106 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
107 | if (!arm_v7m_is_handler_mode(env)) { | ||
108 | switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); | ||
109 | } | ||
110 | - env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; | ||
111 | - env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK; | ||
112 | + env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; | ||
113 | + env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; | ||
114 | break; | ||
115 | default: | ||
116 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" | ||
117 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/target/arm/machine.c | ||
120 | +++ b/target/arm/machine.c | ||
121 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
122 | .fields = (VMStateField[]) { | ||
123 | VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), | ||
124 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | ||
125 | - VMSTATE_UINT32(env.v7m.control, ARMCPU), | ||
126 | + VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), | ||
127 | VMSTATE_UINT32(env.v7m.ccr, ARMCPU), | ||
128 | VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | ||
129 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), | ||
130 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
131 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | ||
132 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | ||
133 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | ||
134 | + VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), | ||
135 | VMSTATE_END_OF_LIST() | ||
136 | } | ||
137 | }; | ||
138 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
139 | index XXXXXXX..XXXXXXX 100644 | ||
140 | --- a/target/arm/translate.c | ||
141 | +++ b/target/arm/translate.c | ||
142 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | ||
143 | if (xpsr & XPSR_EXCP) { | ||
144 | mode = "handler"; | ||
145 | } else { | ||
146 | - if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { | ||
147 | + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { | ||
148 | mode = "unpriv-thread"; | ||
149 | } else { | ||
150 | mode = "priv-thread"; | ||
151 | -- | 385 | -- |
152 | 2.7.4 | 386 | 2.25.1 |
153 | |||
154 | diff view generated by jsdifflib |
1 | Make the CFSR register banked if v8M security extensions are enabled. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Not all the bits in this register are banked: the BFSR | 3 | Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local |
4 | bits [15:8] are shared between S and NS, and we store them | 4 | vpidr_regs definition, and rely on the squashing to ARM_CP_CONST |
5 | in the NS copy of the register. | 5 | while registering for v8. |
6 | 6 | ||
7 | This is a behavior change for v7 cpus with Security Extensions and | ||
8 | without Virtualization Extensions, in that the virtualization cpregs | ||
9 | are now correctly not present. This would be a migration compatibility | ||
10 | break, except that we have an existing bug in which migration of 32-bit | ||
11 | cpus with Security Extensions enabled does not work. | ||
12 | |||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20220506180242.216785-3-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org | ||
10 | --- | 17 | --- |
11 | target/arm/cpu.h | 7 ++++++- | 18 | target/arm/helper.c | 158 ++++---------------------------------------- |
12 | hw/intc/armv7m_nvic.c | 15 +++++++++++++-- | 19 | 1 file changed, 13 insertions(+), 145 deletions(-) |
13 | target/arm/helper.c | 18 +++++++++--------- | 20 | |
14 | target/arm/machine.c | 3 ++- | ||
15 | 4 files changed, 30 insertions(+), 13 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpu.h | ||
20 | +++ b/target/arm/cpu.h | ||
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
22 | uint32_t basepri[2]; | ||
23 | uint32_t control[2]; | ||
24 | uint32_t ccr[2]; /* Configuration and Control */ | ||
25 | - uint32_t cfsr; /* Configurable Fault Status */ | ||
26 | + uint32_t cfsr[2]; /* Configurable Fault Status */ | ||
27 | uint32_t hfsr; /* HardFault Status */ | ||
28 | uint32_t dfsr; /* Debug Fault Status Register */ | ||
29 | uint32_t mmfar[2]; /* MemManage Fault Address */ | ||
30 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_CFSR, NOCP, 16 + 3, 1) | ||
31 | FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) | ||
32 | FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) | ||
33 | |||
34 | +/* V7M CFSR bit masks covering all of the subregister bits */ | ||
35 | +FIELD(V7M_CFSR, MMFSR, 0, 8) | ||
36 | +FIELD(V7M_CFSR, BFSR, 8, 8) | ||
37 | +FIELD(V7M_CFSR, UFSR, 16, 16) | ||
38 | + | ||
39 | /* V7M HFSR bits */ | ||
40 | FIELD(V7M_HFSR, VECTTBL, 1, 1) | ||
41 | FIELD(V7M_HFSR, FORCED, 30, 1) | ||
42 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/intc/armv7m_nvic.c | ||
45 | +++ b/hw/intc/armv7m_nvic.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
47 | } | ||
48 | return val; | ||
49 | case 0xd28: /* Configurable Fault Status. */ | ||
50 | - return cpu->env.v7m.cfsr; | ||
51 | + /* The BFSR bits [15:8] are shared between security states | ||
52 | + * and we store them in the NS copy | ||
53 | + */ | ||
54 | + val = cpu->env.v7m.cfsr[attrs.secure]; | ||
55 | + val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; | ||
56 | + return val; | ||
57 | case 0xd2c: /* Hard Fault Status. */ | ||
58 | return cpu->env.v7m.hfsr; | ||
59 | case 0xd30: /* Debug Fault Status. */ | ||
60 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
61 | nvic_irq_update(s); | ||
62 | break; | ||
63 | case 0xd28: /* Configurable Fault Status. */ | ||
64 | - cpu->env.v7m.cfsr &= ~value; /* W1C */ | ||
65 | + cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */ | ||
66 | + if (attrs.secure) { | ||
67 | + /* The BFSR bits [15:8] are shared between security states | ||
68 | + * and we store them in the NS copy. | ||
69 | + */ | ||
70 | + cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); | ||
71 | + } | ||
72 | break; | ||
73 | case 0xd2c: /* Hard Fault Status. */ | ||
74 | cpu->env.v7m.hfsr &= ~value; /* W1C */ | ||
75 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 21 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
76 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
77 | --- a/target/arm/helper.c | 23 | --- a/target/arm/helper.c |
78 | +++ b/target/arm/helper.c | 24 | +++ b/target/arm/helper.c |
79 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 25 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { |
80 | /* Bad exception return: instead of popping the exception | 26 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, |
81 | * stack, directly take a usage fault on the current stack. | 27 | }; |
82 | */ | 28 | |
83 | - env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; | 29 | -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
84 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | 30 | -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
85 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | 31 | - { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
86 | v7m_exception_taken(cpu, type | 0xf0000000); | 32 | - .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
87 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | 33 | - .access = PL2_RW, |
88 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 34 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, |
89 | if (return_to_handler != arm_v7m_is_handler_mode(env)) { | 35 | - { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, |
90 | /* Take an INVPC UsageFault by pushing the stack again. */ | 36 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
91 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | 37 | - .access = PL2_RW, |
92 | - env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; | 38 | - .type = ARM_CP_CONST, .resetvalue = 0 }, |
93 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | 39 | - { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
94 | v7m_push_stack(cpu); | 40 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, |
95 | v7m_exception_taken(cpu, type | 0xf0000000); | 41 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
96 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " | 42 | - { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
97 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 43 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
98 | switch (cs->exception_index) { | 44 | - .access = PL2_RW, |
99 | case EXCP_UDEF: | 45 | - .type = ARM_CP_CONST, .resetvalue = 0 }, |
100 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | 46 | - { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
101 | - env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; | 47 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, |
102 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; | 48 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
103 | break; | 49 | - { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
104 | case EXCP_NOCP: | 50 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, |
105 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | 51 | - .access = PL2_RW, .type = ARM_CP_CONST, |
106 | - env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; | 52 | - .resetvalue = 0 }, |
107 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; | 53 | - { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, |
108 | break; | 54 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
109 | case EXCP_INVSTATE: | 55 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
110 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | 56 | - { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
111 | - env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK; | 57 | - .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, |
112 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; | 58 | - .access = PL2_RW, .type = ARM_CP_CONST, |
113 | break; | 59 | - .resetvalue = 0 }, |
114 | case EXCP_SWI: | 60 | - { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
115 | /* The PC already points to the next instruction. */ | 61 | - .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
116 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 62 | - .access = PL2_RW, .type = ARM_CP_CONST, |
117 | case 0x8: /* External Abort */ | 63 | - .resetvalue = 0 }, |
118 | switch (cs->exception_index) { | 64 | - { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
119 | case EXCP_PREFETCH_ABORT: | 65 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, |
120 | - env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK; | 66 | - .access = PL2_RW, .type = ARM_CP_CONST, |
121 | + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK; | 67 | - .resetvalue = 0 }, |
122 | qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); | 68 | - { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, |
123 | break; | 69 | - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, |
124 | case EXCP_DATA_ABORT: | 70 | - .access = PL2_RW, .type = ARM_CP_CONST, |
125 | - env->v7m.cfsr |= | 71 | - .resetvalue = 0 }, |
126 | + env->v7m.cfsr[M_REG_NS] |= | 72 | - { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
127 | (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); | 73 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, |
128 | env->v7m.bfar = env->exception.vaddress; | 74 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
129 | qemu_log_mask(CPU_LOG_INT, | 75 | - { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
130 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 76 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, |
131 | */ | 77 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, |
132 | switch (cs->exception_index) { | 78 | - .type = ARM_CP_CONST, .resetvalue = 0 }, |
133 | case EXCP_PREFETCH_ABORT: | 79 | - { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
134 | - env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK; | 80 | - .cp = 15, .opc1 = 6, .crm = 2, |
135 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; | 81 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, |
136 | qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); | 82 | - .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, |
137 | break; | 83 | - { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, |
138 | case EXCP_DATA_ABORT: | 84 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, |
139 | - env->v7m.cfsr |= | 85 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
140 | + env->v7m.cfsr[env->v7m.secure] |= | 86 | - { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
141 | (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); | 87 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, |
142 | env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; | 88 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
143 | qemu_log_mask(CPU_LOG_INT, | 89 | - { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
144 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 90 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, |
145 | index XXXXXXX..XXXXXXX 100644 | 91 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
146 | --- a/target/arm/machine.c | 92 | - { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
147 | +++ b/target/arm/machine.c | 93 | - .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, |
148 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 94 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
149 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | 95 | - { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, |
150 | VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), | 96 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, |
151 | VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), | 97 | - .resetvalue = 0 }, |
152 | - VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | 98 | - { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
153 | + VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), | 99 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, |
154 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), | 100 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
155 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), | 101 | - { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
156 | VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), | 102 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, |
157 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 103 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
158 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), | 104 | - { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, |
159 | VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), | 105 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, |
160 | VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), | 106 | - .resetvalue = 0 }, |
161 | + VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), | 107 | - { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
162 | VMSTATE_END_OF_LIST() | 108 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, |
109 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
110 | - { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | ||
111 | - .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | ||
112 | - .resetvalue = 0 }, | ||
113 | - { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | ||
114 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | ||
115 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
116 | - { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | ||
117 | - .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | ||
118 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
119 | - { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | ||
120 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | ||
121 | - .access = PL2_RW, .accessfn = access_tda, | ||
122 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
123 | - { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
124 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | ||
125 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
126 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
127 | - { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
128 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | ||
129 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
130 | - { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
131 | - .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | ||
132 | - .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
133 | - { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | ||
134 | - .type = ARM_CP_CONST, | ||
135 | - .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | ||
136 | - .access = PL2_RW, .resetvalue = 0 }, | ||
137 | -}; | ||
138 | - | ||
139 | -/* Ditto, but for registers which exist in ARMv8 but not v7 */ | ||
140 | -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | ||
141 | - { .name = "HCR2", .state = ARM_CP_STATE_AA32, | ||
142 | - .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | ||
143 | - .access = PL2_RW, | ||
144 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
145 | -}; | ||
146 | - | ||
147 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
148 | { | ||
149 | ARMCPU *cpu = env_archcpu(env); | ||
150 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
151 | define_arm_cp_regs(cpu, v8_idregs); | ||
152 | define_arm_cp_regs(cpu, v8_cp_reginfo); | ||
163 | } | 153 | } |
164 | }; | 154 | - if (arm_feature(env, ARM_FEATURE_EL2)) { |
155 | + | ||
156 | + /* | ||
157 | + * Register the base EL2 cpregs. | ||
158 | + * Pre v8, these registers are implemented only as part of the | ||
159 | + * Virtualization Extensions (EL2 present). Beginning with v8, | ||
160 | + * if EL2 is missing but EL3 is enabled, mostly these become | ||
161 | + * RES0 from EL3, with some specific exceptions. | ||
162 | + */ | ||
163 | + if (arm_feature(env, ARM_FEATURE_EL2) | ||
164 | + || (arm_feature(env, ARM_FEATURE_EL3) | ||
165 | + && arm_feature(env, ARM_FEATURE_V8))) { | ||
166 | uint64_t vmpidr_def = mpidr_read_val(env); | ||
167 | ARMCPRegInfo vpidr_regs[] = { | ||
168 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | ||
169 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
170 | }; | ||
171 | define_one_arm_cp_reg(cpu, &rvbar); | ||
172 | } | ||
173 | - } else { | ||
174 | - /* If EL2 is missing but higher ELs are enabled, we need to | ||
175 | - * register the no_el2 reginfos. | ||
176 | - */ | ||
177 | - if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
178 | - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value | ||
179 | - * of MIDR_EL1 and MPIDR_EL1. | ||
180 | - */ | ||
181 | - ARMCPRegInfo vpidr_regs[] = { | ||
182 | - { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
183 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | ||
184 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
185 | - .type = ARM_CP_CONST, .resetvalue = cpu->midr, | ||
186 | - .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | ||
187 | - { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, | ||
188 | - .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | ||
189 | - .access = PL2_RW, .accessfn = access_el3_aa32ns, | ||
190 | - .type = ARM_CP_NO_RAW, | ||
191 | - .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | ||
192 | - }; | ||
193 | - define_arm_cp_regs(cpu, vpidr_regs); | ||
194 | - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); | ||
195 | - if (arm_feature(env, ARM_FEATURE_V8)) { | ||
196 | - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | ||
197 | - } | ||
198 | - } | ||
199 | } | ||
200 | + | ||
201 | + /* Register the base EL3 cpregs. */ | ||
202 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
203 | define_arm_cp_regs(cpu, el3_cp_reginfo); | ||
204 | ARMCPRegInfo el3_regs[] = { | ||
165 | -- | 205 | -- |
166 | 2.7.4 | 206 | 2.25.1 |
167 | |||
168 | diff view generated by jsdifflib |
1 | Make the MPU_RNR register banked if v8M security extensions are | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | enabled. | ||
3 | 2 | ||
3 | Drop zcr_no_el2_reginfo and merge the 3 registers into one array, | ||
4 | now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped | ||
5 | while registering. | ||
6 | |||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220506180242.216785-4-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 1503414539-28762-15-git-send-email-peter.maydell@linaro.org | ||
7 | --- | 11 | --- |
8 | target/arm/cpu.h | 2 +- | 12 | target/arm/helper.c | 55 ++++++++++++++------------------------------- |
9 | hw/intc/armv7m_nvic.c | 18 +++++++++--------- | 13 | 1 file changed, 17 insertions(+), 38 deletions(-) |
10 | target/arm/cpu.c | 3 ++- | ||
11 | target/arm/helper.c | 6 +++--- | ||
12 | target/arm/machine.c | 13 +++++++++++-- | ||
13 | 5 files changed, 26 insertions(+), 16 deletions(-) | ||
14 | 14 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/cpu.h | ||
18 | +++ b/target/arm/cpu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
20 | uint32_t *drbar; | ||
21 | uint32_t *drsr; | ||
22 | uint32_t *dracr; | ||
23 | - uint32_t rnr; | ||
24 | + uint32_t rnr[2]; | ||
25 | } pmsav7; | ||
26 | |||
27 | /* PMSAv8 MPU */ | ||
28 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/hw/intc/armv7m_nvic.c | ||
31 | +++ b/hw/intc/armv7m_nvic.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
33 | case 0xd94: /* MPU_CTRL */ | ||
34 | return cpu->env.v7m.mpu_ctrl; | ||
35 | case 0xd98: /* MPU_RNR */ | ||
36 | - return cpu->env.pmsav7.rnr; | ||
37 | + return cpu->env.pmsav7.rnr[attrs.secure]; | ||
38 | case 0xd9c: /* MPU_RBAR */ | ||
39 | case 0xda4: /* MPU_RBAR_A1 */ | ||
40 | case 0xdac: /* MPU_RBAR_A2 */ | ||
41 | case 0xdb4: /* MPU_RBAR_A3 */ | ||
42 | { | ||
43 | - int region = cpu->env.pmsav7.rnr; | ||
44 | + int region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
45 | |||
46 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
47 | /* PMSAv8M handling of the aliases is different from v7M: | ||
48 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
49 | case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | ||
50 | case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | ||
51 | { | ||
52 | - int region = cpu->env.pmsav7.rnr; | ||
53 | + int region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
54 | |||
55 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
56 | /* PMSAv8M handling of the aliases is different from v7M: | ||
57 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
58 | PRIu32 "/%" PRIu32 "\n", | ||
59 | value, cpu->pmsav7_dregion); | ||
60 | } else { | ||
61 | - cpu->env.pmsav7.rnr = value; | ||
62 | + cpu->env.pmsav7.rnr[attrs.secure] = value; | ||
63 | } | ||
64 | break; | ||
65 | case 0xd9c: /* MPU_RBAR */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
67 | */ | ||
68 | int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | ||
69 | |||
70 | - region = cpu->env.pmsav7.rnr; | ||
71 | + region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
72 | if (aliasno) { | ||
73 | region = deposit32(region, 0, 2, aliasno); | ||
74 | } | ||
75 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
76 | region, cpu->pmsav7_dregion); | ||
77 | return; | ||
78 | } | ||
79 | - cpu->env.pmsav7.rnr = region; | ||
80 | + cpu->env.pmsav7.rnr[attrs.secure] = region; | ||
81 | } else { | ||
82 | - region = cpu->env.pmsav7.rnr; | ||
83 | + region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
84 | } | ||
85 | |||
86 | if (region >= cpu->pmsav7_dregion) { | ||
87 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
88 | case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | ||
89 | case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | ||
90 | { | ||
91 | - int region = cpu->env.pmsav7.rnr; | ||
92 | + int region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
93 | |||
94 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
95 | /* PMSAv8M handling of the aliases is different from v7M: | ||
96 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
97 | */ | ||
98 | int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | ||
99 | |||
100 | - region = cpu->env.pmsav7.rnr; | ||
101 | + region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
102 | if (aliasno) { | ||
103 | region = deposit32(region, 0, 2, aliasno); | ||
104 | } | ||
105 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/cpu.c | ||
108 | +++ b/target/arm/cpu.c | ||
109 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
110 | sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | ||
111 | } | ||
112 | } | ||
113 | - env->pmsav7.rnr = 0; | ||
114 | + env->pmsav7.rnr[M_REG_NS] = 0; | ||
115 | + env->pmsav7.rnr[M_REG_S] = 0; | ||
116 | env->pmsav8.mair0[M_REG_NS] = 0; | ||
117 | env->pmsav8.mair0[M_REG_S] = 0; | ||
118 | env->pmsav8.mair1[M_REG_NS] = 0; | ||
119 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
120 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
121 | --- a/target/arm/helper.c | 17 | --- a/target/arm/helper.c |
122 | +++ b/target/arm/helper.c | 18 | +++ b/target/arm/helper.c |
123 | @@ -XXX,XX +XXX,XX @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) | 19 | @@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
124 | return 0; | ||
125 | } | 20 | } |
126 | |||
127 | - u32p += env->pmsav7.rnr; | ||
128 | + u32p += env->pmsav7.rnr[M_REG_NS]; | ||
129 | return *u32p; | ||
130 | } | 21 | } |
131 | 22 | ||
132 | @@ -XXX,XX +XXX,XX @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | 23 | -static const ARMCPRegInfo zcr_el1_reginfo = { |
133 | return; | 24 | - .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, |
25 | - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | ||
26 | - .access = PL1_RW, .type = ARM_CP_SVE, | ||
27 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | ||
28 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
29 | -}; | ||
30 | - | ||
31 | -static const ARMCPRegInfo zcr_el2_reginfo = { | ||
32 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
33 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
34 | - .access = PL2_RW, .type = ARM_CP_SVE, | ||
35 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | ||
36 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
37 | -}; | ||
38 | - | ||
39 | -static const ARMCPRegInfo zcr_no_el2_reginfo = { | ||
40 | - .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
41 | - .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
42 | - .access = PL2_RW, .type = ARM_CP_SVE, | ||
43 | - .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore | ||
44 | -}; | ||
45 | - | ||
46 | -static const ARMCPRegInfo zcr_el3_reginfo = { | ||
47 | - .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
48 | - .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
49 | - .access = PL3_RW, .type = ARM_CP_SVE, | ||
50 | - .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
51 | - .writefn = zcr_write, .raw_writefn = raw_write | ||
52 | +static const ARMCPRegInfo zcr_reginfo[] = { | ||
53 | + { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | ||
54 | + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | ||
55 | + .access = PL1_RW, .type = ARM_CP_SVE, | ||
56 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | ||
57 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
58 | + { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | ||
59 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | ||
60 | + .access = PL2_RW, .type = ARM_CP_SVE, | ||
61 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | ||
62 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
63 | + { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | ||
64 | + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | ||
65 | + .access = PL3_RW, .type = ARM_CP_SVE, | ||
66 | + .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | ||
67 | + .writefn = zcr_write, .raw_writefn = raw_write }, | ||
68 | }; | ||
69 | |||
70 | void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
71 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
134 | } | 72 | } |
135 | 73 | ||
136 | - u32p += env->pmsav7.rnr; | 74 | if (cpu_isar_feature(aa64_sve, cpu)) { |
137 | + u32p += env->pmsav7.rnr[M_REG_NS]; | 75 | - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); |
138 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | 76 | - if (arm_feature(env, ARM_FEATURE_EL2)) { |
139 | *u32p = value; | 77 | - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); |
140 | } | 78 | - } else { |
141 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | 79 | - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); |
142 | .resetfn = arm_cp_reset_ignore }, | 80 | - } |
143 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, | 81 | - if (arm_feature(env, ARM_FEATURE_EL3)) { |
144 | .access = PL1_RW, | 82 | - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); |
145 | - .fieldoffset = offsetof(CPUARMState, pmsav7.rnr), | 83 | - } |
146 | + .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), | 84 | + define_arm_cp_regs(cpu, zcr_reginfo); |
147 | .writefn = pmsav7_rgnr_write, | ||
148 | .resetfn = arm_cp_reset_ignore }, | ||
149 | REGINFO_SENTINEL | ||
150 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/target/arm/machine.c | ||
153 | +++ b/target/arm/machine.c | ||
154 | @@ -XXX,XX +XXX,XX @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) | ||
155 | { | ||
156 | ARMCPU *cpu = opaque; | ||
157 | |||
158 | - return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; | ||
159 | + return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; | ||
160 | } | ||
161 | |||
162 | static const VMStateDescription vmstate_pmsav7 = { | ||
163 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav7_rnr = { | ||
164 | .minimum_version_id = 1, | ||
165 | .needed = pmsav7_rnr_needed, | ||
166 | .fields = (VMStateField[]) { | ||
167 | - VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), | ||
168 | + VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), | ||
169 | VMSTATE_END_OF_LIST() | ||
170 | } | 85 | } |
171 | }; | 86 | |
172 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = { | 87 | #ifdef TARGET_AARCH64 |
173 | } | ||
174 | }; | ||
175 | |||
176 | +static bool s_rnr_vmstate_validate(void *opaque, int version_id) | ||
177 | +{ | ||
178 | + ARMCPU *cpu = opaque; | ||
179 | + | ||
180 | + return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; | ||
181 | +} | ||
182 | + | ||
183 | static bool m_security_needed(void *opaque) | ||
184 | { | ||
185 | ARMCPU *cpu = opaque; | ||
186 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
187 | 0, vmstate_info_uint32, uint32_t), | ||
188 | VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, | ||
189 | 0, vmstate_info_uint32, uint32_t), | ||
190 | + VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), | ||
191 | + VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), | ||
192 | VMSTATE_END_OF_LIST() | ||
193 | } | ||
194 | }; | ||
195 | -- | 88 | -- |
196 | 2.7.4 | 89 | 2.25.1 |
197 | |||
198 | diff view generated by jsdifflib |
1 | Make the MPU_CTRL register banked if v8M security extensions are | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | enabled. | ||
3 | 2 | ||
3 | This register is present for either VHE or Debugv8p2. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220506180242.216785-5-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org | ||
7 | --- | 9 | --- |
8 | target/arm/cpu.h | 2 +- | 10 | target/arm/helper.c | 15 +++++++++++---- |
9 | hw/intc/armv7m_nvic.c | 9 +++++---- | 11 | 1 file changed, 11 insertions(+), 4 deletions(-) |
10 | target/arm/helper.c | 5 +++-- | ||
11 | target/arm/machine.c | 3 ++- | ||
12 | 4 files changed, 11 insertions(+), 8 deletions(-) | ||
13 | 12 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
19 | uint32_t dfsr; /* Debug Fault Status Register */ | ||
20 | uint32_t mmfar; /* MemManage Fault Address */ | ||
21 | uint32_t bfar; /* BusFault Address */ | ||
22 | - unsigned mpu_ctrl; /* MPU_CTRL */ | ||
23 | + unsigned mpu_ctrl[2]; /* MPU_CTRL */ | ||
24 | int exception; | ||
25 | uint32_t primask[2]; | ||
26 | uint32_t faultmask[2]; | ||
27 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/hw/intc/armv7m_nvic.c | ||
30 | +++ b/hw/intc/armv7m_nvic.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
32 | return cpu->pmsav7_dregion << 8; | ||
33 | break; | ||
34 | case 0xd94: /* MPU_CTRL */ | ||
35 | - return cpu->env.v7m.mpu_ctrl; | ||
36 | + return cpu->env.v7m.mpu_ctrl[attrs.secure]; | ||
37 | case 0xd98: /* MPU_RNR */ | ||
38 | return cpu->env.pmsav7.rnr[attrs.secure]; | ||
39 | case 0xd9c: /* MPU_RBAR */ | ||
40 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
41 | qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " | ||
42 | "UNPREDICTABLE\n"); | ||
43 | } | ||
44 | - cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK | | ||
45 | - R_V7M_MPU_CTRL_HFNMIENA_MASK | | ||
46 | - R_V7M_MPU_CTRL_PRIVDEFENA_MASK); | ||
47 | + cpu->env.v7m.mpu_ctrl[attrs.secure] | ||
48 | + = value & (R_V7M_MPU_CTRL_ENABLE_MASK | | ||
49 | + R_V7M_MPU_CTRL_HFNMIENA_MASK | | ||
50 | + R_V7M_MPU_CTRL_PRIVDEFENA_MASK); | ||
51 | tlb_flush(CPU(cpu)); | ||
52 | break; | ||
53 | case 0xd98: /* MPU_RNR */ | ||
54 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
55 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
56 | --- a/target/arm/helper.c | 15 | --- a/target/arm/helper.c |
57 | +++ b/target/arm/helper.c | 16 | +++ b/target/arm/helper.c |
58 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env, | 17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = { |
59 | ARMMMUIdx mmu_idx) | 18 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
60 | { | 19 | }; |
61 | if (arm_feature(env, ARM_FEATURE_M)) { | 20 | |
62 | - switch (env->v7m.mpu_ctrl & | 21 | +static const ARMCPRegInfo contextidr_el2 = { |
63 | + switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & | 22 | + .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, |
64 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { | 23 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, |
65 | case R_V7M_MPU_CTRL_ENABLE_MASK: | 24 | + .access = PL2_RW, |
66 | /* Enabled, but not for HardFault and NMI */ | 25 | + .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) |
67 | @@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, | 26 | +}; |
27 | + | ||
28 | static const ARMCPRegInfo vhe_reginfo[] = { | ||
29 | - { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | ||
30 | - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | ||
31 | - .access = PL2_RW, | ||
32 | - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, | ||
33 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, | ||
34 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | ||
35 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | ||
36 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
37 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | ||
68 | } | 38 | } |
69 | 39 | ||
70 | if (arm_feature(env, ARM_FEATURE_M)) { | 40 | + if (cpu_isar_feature(aa64_vh, cpu) || |
71 | - return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | 41 | + cpu_isar_feature(aa64_debugv8p2, cpu)) { |
72 | + return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] | 42 | + define_one_arm_cp_reg(cpu, &contextidr_el2); |
73 | + & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | 43 | + } |
74 | } else { | 44 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { |
75 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | 45 | define_arm_cp_regs(cpu, vhe_reginfo); |
76 | } | 46 | } |
77 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/target/arm/machine.c | ||
80 | +++ b/target/arm/machine.c | ||
81 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
82 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), | ||
83 | VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), | ||
84 | VMSTATE_UINT32(env.v7m.bfar, ARMCPU), | ||
85 | - VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), | ||
86 | + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), | ||
87 | VMSTATE_INT32(env.v7m.exception, ARMCPU), | ||
88 | VMSTATE_END_OF_LIST() | ||
89 | }, | ||
90 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
91 | 0, vmstate_info_uint32, uint32_t), | ||
92 | VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), | ||
93 | VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), | ||
94 | + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), | ||
95 | VMSTATE_END_OF_LIST() | ||
96 | } | ||
97 | }; | ||
98 | -- | 47 | -- |
99 | 2.7.4 | 48 | 2.25.1 |
100 | |||
101 | diff view generated by jsdifflib |
1 | Move the regime_is_secure() utility function to internals.h; | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | we are going to want to call it from translate.c. | 2 | |
3 | 3 | Previously we were defining some of these in user-only mode, | |
4 | but none of them are accessible from user-only, therefore | ||
5 | define them only in system mode. | ||
6 | |||
7 | This will shortly be used from cpu_tcg.c also. | ||
8 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220506180242.216785-6-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 1503414539-28762-20-git-send-email-peter.maydell@linaro.org | ||
7 | --- | 13 | --- |
8 | target/arm/internals.h | 26 ++++++++++++++++++++++++++ | 14 | target/arm/internals.h | 6 ++++ |
9 | target/arm/helper.c | 26 -------------------------- | 15 | target/arm/cpu64.c | 64 +++--------------------------------------- |
10 | 2 files changed, 26 insertions(+), 26 deletions(-) | 16 | target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ |
17 | 3 files changed, 69 insertions(+), 60 deletions(-) | ||
11 | 18 | ||
12 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 19 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
13 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/internals.h | 21 | --- a/target/arm/internals.h |
15 | +++ b/target/arm/internals.h | 22 | +++ b/target/arm/internals.h |
16 | @@ -XXX,XX +XXX,XX @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) | 23 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); |
17 | } | 24 | int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); |
25 | #endif | ||
26 | |||
27 | +#ifdef CONFIG_USER_ONLY | ||
28 | +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | ||
29 | +#else | ||
30 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | ||
31 | +#endif | ||
32 | + | ||
33 | #endif | ||
34 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/cpu64.c | ||
37 | +++ b/target/arm/cpu64.c | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | #include "hvf_arm.h" | ||
40 | #include "qapi/visitor.h" | ||
41 | #include "hw/qdev-properties.h" | ||
42 | -#include "cpregs.h" | ||
43 | +#include "internals.h" | ||
44 | |||
45 | |||
46 | -#ifndef CONFIG_USER_ONLY | ||
47 | -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
48 | -{ | ||
49 | - ARMCPU *cpu = env_archcpu(env); | ||
50 | - | ||
51 | - /* Number of cores is in [25:24]; otherwise we RAZ */ | ||
52 | - return (cpu->core_count - 1) << 24; | ||
53 | -} | ||
54 | -#endif | ||
55 | - | ||
56 | -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
57 | -#ifndef CONFIG_USER_ONLY | ||
58 | - { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
59 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | ||
60 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | ||
61 | - .writefn = arm_cp_write_ignore }, | ||
62 | - { .name = "L2CTLR", | ||
63 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | ||
64 | - .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, | ||
65 | - .writefn = arm_cp_write_ignore }, | ||
66 | -#endif | ||
67 | - { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
68 | - .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | ||
69 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
70 | - { .name = "L2ECTLR", | ||
71 | - .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | ||
72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
73 | - { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | ||
74 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | ||
75 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
76 | - { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
77 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | ||
78 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | - { .name = "CPUACTLR", | ||
80 | - .cp = 15, .opc1 = 0, .crm = 15, | ||
81 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
82 | - { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
83 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | ||
84 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
85 | - { .name = "CPUECTLR", | ||
86 | - .cp = 15, .opc1 = 1, .crm = 15, | ||
87 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
88 | - { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
89 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | ||
90 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
91 | - { .name = "CPUMERRSR", | ||
92 | - .cp = 15, .opc1 = 2, .crm = 15, | ||
93 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
94 | - { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | ||
95 | - .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | ||
96 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
97 | - { .name = "L2MERRSR", | ||
98 | - .cp = 15, .opc1 = 3, .crm = 15, | ||
99 | - .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
100 | -}; | ||
101 | - | ||
102 | static void aarch64_a57_initfn(Object *obj) | ||
103 | { | ||
104 | ARMCPU *cpu = ARM_CPU(obj); | ||
105 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | ||
106 | cpu->gic_num_lrs = 4; | ||
107 | cpu->gic_vpribits = 5; | ||
108 | cpu->gic_vprebits = 5; | ||
109 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
110 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
18 | } | 111 | } |
19 | 112 | ||
20 | +/* Return true if this address translation regime is secure */ | 113 | static void aarch64_a53_initfn(Object *obj) |
21 | +static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | 114 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) |
115 | cpu->gic_num_lrs = 4; | ||
116 | cpu->gic_vpribits = 5; | ||
117 | cpu->gic_vprebits = 5; | ||
118 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
119 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
120 | } | ||
121 | |||
122 | static void aarch64_a72_initfn(Object *obj) | ||
123 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
124 | cpu->gic_num_lrs = 4; | ||
125 | cpu->gic_vpribits = 5; | ||
126 | cpu->gic_vprebits = 5; | ||
127 | - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
128 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
129 | } | ||
130 | |||
131 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | ||
132 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
133 | index XXXXXXX..XXXXXXX 100644 | ||
134 | --- a/target/arm/cpu_tcg.c | ||
135 | +++ b/target/arm/cpu_tcg.c | ||
136 | @@ -XXX,XX +XXX,XX @@ | ||
137 | #endif | ||
138 | #include "cpregs.h" | ||
139 | |||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
22 | +{ | 142 | +{ |
23 | + switch (mmu_idx) { | 143 | + ARMCPU *cpu = env_archcpu(env); |
24 | + case ARMMMUIdx_S12NSE0: | 144 | + |
25 | + case ARMMMUIdx_S12NSE1: | 145 | + /* Number of cores is in [25:24]; otherwise we RAZ */ |
26 | + case ARMMMUIdx_S1NSE0: | 146 | + return (cpu->core_count - 1) << 24; |
27 | + case ARMMMUIdx_S1NSE1: | ||
28 | + case ARMMMUIdx_S1E2: | ||
29 | + case ARMMMUIdx_S2NS: | ||
30 | + case ARMMMUIdx_MPriv: | ||
31 | + case ARMMMUIdx_MNegPri: | ||
32 | + case ARMMMUIdx_MUser: | ||
33 | + return false; | ||
34 | + case ARMMMUIdx_S1E3: | ||
35 | + case ARMMMUIdx_S1SE0: | ||
36 | + case ARMMMUIdx_S1SE1: | ||
37 | + case ARMMMUIdx_MSPriv: | ||
38 | + case ARMMMUIdx_MSNegPri: | ||
39 | + case ARMMMUIdx_MSUser: | ||
40 | + return true; | ||
41 | + default: | ||
42 | + g_assert_not_reached(); | ||
43 | + } | ||
44 | +} | 147 | +} |
45 | + | 148 | + |
46 | #endif | 149 | +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { |
47 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 150 | + { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, |
48 | index XXXXXXX..XXXXXXX 100644 | 151 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, |
49 | --- a/target/arm/helper.c | 152 | + .access = PL1_RW, .readfn = l2ctlr_read, |
50 | +++ b/target/arm/helper.c | 153 | + .writefn = arm_cp_write_ignore }, |
51 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | 154 | + { .name = "L2CTLR", |
52 | } | 155 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, |
53 | } | 156 | + .access = PL1_RW, .readfn = l2ctlr_read, |
54 | 157 | + .writefn = arm_cp_write_ignore }, | |
55 | -/* Return true if this address translation regime is secure */ | 158 | + { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, |
56 | -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | 159 | + .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, |
57 | -{ | 160 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
58 | - switch (mmu_idx) { | 161 | + { .name = "L2ECTLR", |
59 | - case ARMMMUIdx_S12NSE0: | 162 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, |
60 | - case ARMMMUIdx_S12NSE1: | 163 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
61 | - case ARMMMUIdx_S1NSE0: | 164 | + { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, |
62 | - case ARMMMUIdx_S1NSE1: | 165 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, |
63 | - case ARMMMUIdx_S1E2: | 166 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
64 | - case ARMMMUIdx_S2NS: | 167 | + { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, |
65 | - case ARMMMUIdx_MPriv: | 168 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, |
66 | - case ARMMMUIdx_MNegPri: | 169 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
67 | - case ARMMMUIdx_MUser: | 170 | + { .name = "CPUACTLR", |
68 | - return false; | 171 | + .cp = 15, .opc1 = 0, .crm = 15, |
69 | - case ARMMMUIdx_S1E3: | 172 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, |
70 | - case ARMMMUIdx_S1SE0: | 173 | + { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, |
71 | - case ARMMMUIdx_S1SE1: | 174 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, |
72 | - case ARMMMUIdx_MSPriv: | 175 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
73 | - case ARMMMUIdx_MSNegPri: | 176 | + { .name = "CPUECTLR", |
74 | - case ARMMMUIdx_MSUser: | 177 | + .cp = 15, .opc1 = 1, .crm = 15, |
75 | - return true; | 178 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, |
76 | - default: | 179 | + { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, |
77 | - g_assert_not_reached(); | 180 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, |
78 | - } | 181 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
79 | -} | 182 | + { .name = "CPUMERRSR", |
80 | - | 183 | + .cp = 15, .opc1 = 2, .crm = 15, |
81 | /* Return the SCTLR value which controls this address translation regime */ | 184 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, |
82 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | 185 | + { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, |
83 | { | 186 | + .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, |
187 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
188 | + { .name = "L2MERRSR", | ||
189 | + .cp = 15, .opc1 = 3, .crm = 15, | ||
190 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
191 | +}; | ||
192 | + | ||
193 | +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) | ||
194 | +{ | ||
195 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
196 | +} | ||
197 | +#endif /* !CONFIG_USER_ONLY */ | ||
198 | + | ||
199 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | ||
200 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | ||
201 | |||
84 | -- | 202 | -- |
85 | 2.7.4 | 203 | 2.25.1 |
86 | |||
87 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | Instead of starting with cortex-a15 and adding v8 features to |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. |
5 | Message-id: 20170905131149.10669-5-famz@redhat.com | 5 | This fixes the long-standing to-do where we only enabled v8 |
6 | features for user-only. | ||
7 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220506180242.216785-7-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 12 | --- |
9 | hw/arm/xlnx-zynqmp.c | 7 ++----- | 13 | target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- |
10 | 1 file changed, 2 insertions(+), 5 deletions(-) | 14 | 1 file changed, 92 insertions(+), 59 deletions(-) |
11 | 15 | ||
12 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | 16 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c |
13 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/arm/xlnx-zynqmp.c | 18 | --- a/target/arm/cpu_tcg.c |
15 | +++ b/hw/arm/xlnx-zynqmp.c | 19 | +++ b/target/arm/cpu_tcg.c |
16 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj) | 20 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) |
17 | &error_abort); | 21 | static void arm_max_initfn(Object *obj) |
18 | } | 22 | { |
19 | 23 | ARMCPU *cpu = ARM_CPU(obj); | |
20 | - object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION, | 24 | + uint32_t t; |
21 | - (Object **)&s->ddr_ram, | 25 | |
22 | - qdev_prop_allow_set_link_before_realize, | 26 | - cortex_a15_initfn(obj); |
23 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); | 27 | + /* aarch64_a57_initfn, advertising none of the aarch64 features */ |
28 | + cpu->dtb_compatible = "arm,cortex-a57"; | ||
29 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
30 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
31 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
32 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
33 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
34 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
35 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
36 | + cpu->midr = 0x411fd070; | ||
37 | + cpu->revidr = 0x00000000; | ||
38 | + cpu->reset_fpsid = 0x41034070; | ||
39 | + cpu->isar.mvfr0 = 0x10110222; | ||
40 | + cpu->isar.mvfr1 = 0x12111111; | ||
41 | + cpu->isar.mvfr2 = 0x00000043; | ||
42 | + cpu->ctr = 0x8444c004; | ||
43 | + cpu->reset_sctlr = 0x00c50838; | ||
44 | + cpu->isar.id_pfr0 = 0x00000131; | ||
45 | + cpu->isar.id_pfr1 = 0x00011011; | ||
46 | + cpu->isar.id_dfr0 = 0x03010066; | ||
47 | + cpu->id_afr0 = 0x00000000; | ||
48 | + cpu->isar.id_mmfr0 = 0x10101105; | ||
49 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
50 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
51 | + cpu->isar.id_mmfr3 = 0x02102211; | ||
52 | + cpu->isar.id_isar0 = 0x02101110; | ||
53 | + cpu->isar.id_isar1 = 0x13112111; | ||
54 | + cpu->isar.id_isar2 = 0x21232042; | ||
55 | + cpu->isar.id_isar3 = 0x01112131; | ||
56 | + cpu->isar.id_isar4 = 0x00011142; | ||
57 | + cpu->isar.id_isar5 = 0x00011121; | ||
58 | + cpu->isar.id_isar6 = 0; | ||
59 | + cpu->isar.dbgdidr = 0x3516d000; | ||
60 | + cpu->clidr = 0x0a200023; | ||
61 | + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
62 | + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | ||
63 | + cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
64 | + define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
65 | |||
66 | - /* old-style VFP short-vector support */ | ||
67 | - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
68 | + /* Add additional features supported by QEMU */ | ||
69 | + t = cpu->isar.id_isar5; | ||
70 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
71 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
72 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
73 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
74 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
75 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
76 | + cpu->isar.id_isar5 = t; | ||
77 | + | ||
78 | + t = cpu->isar.id_isar6; | ||
79 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
80 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
81 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
82 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
83 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
84 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
85 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
86 | + cpu->isar.id_isar6 = t; | ||
87 | + | ||
88 | + t = cpu->isar.mvfr1; | ||
89 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
90 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
91 | + cpu->isar.mvfr1 = t; | ||
92 | + | ||
93 | + t = cpu->isar.mvfr2; | ||
94 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
95 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
96 | + cpu->isar.mvfr2 = t; | ||
97 | + | ||
98 | + t = cpu->isar.id_mmfr3; | ||
99 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
100 | + cpu->isar.id_mmfr3 = t; | ||
101 | + | ||
102 | + t = cpu->isar.id_mmfr4; | ||
103 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
104 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
105 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
106 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
107 | + cpu->isar.id_mmfr4 = t; | ||
108 | + | ||
109 | + t = cpu->isar.id_pfr0; | ||
110 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
111 | + cpu->isar.id_pfr0 = t; | ||
112 | + | ||
113 | + t = cpu->isar.id_pfr2; | ||
114 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
115 | + cpu->isar.id_pfr2 = t; | ||
116 | |||
117 | #ifdef CONFIG_USER_ONLY | ||
118 | /* | ||
119 | - * We don't set these in system emulation mode for the moment, | ||
120 | - * since we don't correctly set (all of) the ID registers to | ||
121 | - * advertise them. | ||
122 | + * Break with true ARMv8 and add back old-style VFP short-vector support. | ||
123 | + * Only do this for user-mode, where -cpu max is the default, so that | ||
124 | + * older v6 and v7 programs are more likely to work without adjustment. | ||
125 | */ | ||
126 | - set_feature(&cpu->env, ARM_FEATURE_V8); | ||
127 | - { | ||
128 | - uint32_t t; | ||
24 | - | 129 | - |
25 | object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); | 130 | - t = cpu->isar.id_isar5; |
26 | qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); | 131 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); |
27 | 132 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | |
28 | @@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = { | 133 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); |
29 | DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), | 134 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); |
30 | DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), | 135 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); |
31 | DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), | 136 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); |
32 | + DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, | 137 | - cpu->isar.id_isar5 = t; |
33 | + MemoryRegion *), | 138 | - |
34 | DEFINE_PROP_END_OF_LIST() | 139 | - t = cpu->isar.id_isar6; |
35 | }; | 140 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); |
141 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
142 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
143 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
144 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
145 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
146 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
147 | - cpu->isar.id_isar6 = t; | ||
148 | - | ||
149 | - t = cpu->isar.mvfr1; | ||
150 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
151 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
152 | - cpu->isar.mvfr1 = t; | ||
153 | - | ||
154 | - t = cpu->isar.mvfr2; | ||
155 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
156 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
157 | - cpu->isar.mvfr2 = t; | ||
158 | - | ||
159 | - t = cpu->isar.id_mmfr3; | ||
160 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
161 | - cpu->isar.id_mmfr3 = t; | ||
162 | - | ||
163 | - t = cpu->isar.id_mmfr4; | ||
164 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
165 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
166 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
167 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
168 | - cpu->isar.id_mmfr4 = t; | ||
169 | - | ||
170 | - t = cpu->isar.id_pfr0; | ||
171 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
172 | - cpu->isar.id_pfr0 = t; | ||
173 | - | ||
174 | - t = cpu->isar.id_pfr2; | ||
175 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
176 | - cpu->isar.id_pfr2 = t; | ||
177 | - } | ||
178 | -#endif /* CONFIG_USER_ONLY */ | ||
179 | + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | ||
180 | +#endif | ||
181 | } | ||
182 | #endif /* !TARGET_AARCH64 */ | ||
36 | 183 | ||
37 | -- | 184 | -- |
38 | 2.7.4 | 185 | 2.25.1 |
39 | |||
40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | We set this for qemu-system-aarch64, but failed to do so | ||
4 | for the strictly 32-bit emulation. | ||
5 | |||
6 | Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220506180242.216785-8-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/cpu_tcg.c | 4 ++++ | ||
13 | 1 file changed, 4 insertions(+) | ||
14 | |||
15 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/cpu_tcg.c | ||
18 | +++ b/target/arm/cpu_tcg.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
20 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
21 | cpu->isar.id_pfr2 = t; | ||
22 | |||
23 | + t = cpu->isar.id_dfr0; | ||
24 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
25 | + cpu->isar.id_dfr0 = t; | ||
26 | + | ||
27 | #ifdef CONFIG_USER_ONLY | ||
28 | /* | ||
29 | * Break with true ARMv8 and add back old-style VFP short-vector support. | ||
30 | -- | ||
31 | 2.25.1 | diff view generated by jsdifflib |
1 | Implement the new do_transaction_failed hook for ARM, which should | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | cause the CPU to take a prefetch abort or data abort. | ||
3 | 2 | ||
3 | Share the code to set AArch32 max features so that we no | ||
4 | longer have code drift between qemu{-system,}-{arm,aarch64}. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-9-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
7 | Message-id: 1504626814-23124-4-git-send-email-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | target/arm/internals.h | 10 ++++++++++ | 11 | target/arm/internals.h | 2 + |
10 | target/arm/cpu.c | 1 + | 12 | target/arm/cpu64.c | 50 +----------------- |
11 | target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ | 13 | target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- |
12 | 3 files changed, 54 insertions(+) | 14 | 3 files changed, 65 insertions(+), 101 deletions(-) |
13 | 15 | ||
14 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/internals.h | 18 | --- a/target/arm/internals.h |
17 | +++ b/target/arm/internals.h | 19 | +++ b/target/arm/internals.h |
18 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | 20 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } |
19 | MMUAccessType access_type, | 21 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); |
20 | int mmu_idx, uintptr_t retaddr); | 22 | #endif |
21 | 23 | ||
22 | +/* arm_cpu_do_transaction_failed: handle a memory system error response | 24 | +void aa32_max_features(ARMCPU *cpu); |
23 | + * (eg "no device/memory present at address") by raising an external abort | 25 | + |
24 | + * exception | 26 | #endif |
25 | + */ | 27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
26 | +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | 28 | index XXXXXXX..XXXXXXX 100644 |
27 | + vaddr addr, unsigned size, | 29 | --- a/target/arm/cpu64.c |
28 | + MMUAccessType access_type, | 30 | +++ b/target/arm/cpu64.c |
29 | + int mmu_idx, MemTxAttrs attrs, | 31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
30 | + MemTxResult response, uintptr_t retaddr); | ||
31 | + | ||
32 | /* Call the EL change hook if one has been registered */ | ||
33 | static inline void arm_call_el_change_hook(ARMCPU *cpu) | ||
34 | { | 32 | { |
35 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 33 | ARMCPU *cpu = ARM_CPU(obj); |
34 | uint64_t t; | ||
35 | - uint32_t u; | ||
36 | |||
37 | if (kvm_enabled() || hvf_enabled()) { | ||
38 | /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ | ||
39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
40 | t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
41 | cpu->isar.id_aa64zfr0 = t; | ||
42 | |||
43 | - /* Replicate the same data to the 32-bit id registers. */ | ||
44 | - u = cpu->isar.id_isar5; | ||
45 | - u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ | ||
46 | - u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); | ||
47 | - u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); | ||
48 | - u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); | ||
49 | - u = FIELD_DP32(u, ID_ISAR5, RDM, 1); | ||
50 | - u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); | ||
51 | - cpu->isar.id_isar5 = u; | ||
52 | - | ||
53 | - u = cpu->isar.id_isar6; | ||
54 | - u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); | ||
55 | - u = FIELD_DP32(u, ID_ISAR6, DP, 1); | ||
56 | - u = FIELD_DP32(u, ID_ISAR6, FHM, 1); | ||
57 | - u = FIELD_DP32(u, ID_ISAR6, SB, 1); | ||
58 | - u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); | ||
59 | - u = FIELD_DP32(u, ID_ISAR6, BF16, 1); | ||
60 | - u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); | ||
61 | - cpu->isar.id_isar6 = u; | ||
62 | - | ||
63 | - u = cpu->isar.id_pfr0; | ||
64 | - u = FIELD_DP32(u, ID_PFR0, DIT, 1); | ||
65 | - cpu->isar.id_pfr0 = u; | ||
66 | - | ||
67 | - u = cpu->isar.id_pfr2; | ||
68 | - u = FIELD_DP32(u, ID_PFR2, SSBS, 1); | ||
69 | - cpu->isar.id_pfr2 = u; | ||
70 | - | ||
71 | - u = cpu->isar.id_mmfr3; | ||
72 | - u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
73 | - cpu->isar.id_mmfr3 = u; | ||
74 | - | ||
75 | - u = cpu->isar.id_mmfr4; | ||
76 | - u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
77 | - u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
78 | - u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
79 | - u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
80 | - cpu->isar.id_mmfr4 = u; | ||
81 | - | ||
82 | t = cpu->isar.id_aa64dfr0; | ||
83 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
84 | cpu->isar.id_aa64dfr0 = t; | ||
85 | |||
86 | - u = cpu->isar.id_dfr0; | ||
87 | - u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
88 | - cpu->isar.id_dfr0 = u; | ||
89 | - | ||
90 | - u = cpu->isar.mvfr1; | ||
91 | - u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
92 | - u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
93 | - cpu->isar.mvfr1 = u; | ||
94 | + /* Replicate the same data to the 32-bit id registers. */ | ||
95 | + aa32_max_features(cpu); | ||
96 | |||
97 | #ifdef CONFIG_USER_ONLY | ||
98 | /* | ||
99 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | 100 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/target/arm/cpu.c | 101 | --- a/target/arm/cpu_tcg.c |
38 | +++ b/target/arm/cpu.c | 102 | +++ b/target/arm/cpu_tcg.c |
39 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) | 103 | @@ -XXX,XX +XXX,XX @@ |
40 | #else | 104 | #endif |
41 | cc->do_interrupt = arm_cpu_do_interrupt; | 105 | #include "cpregs.h" |
42 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; | 106 | |
43 | + cc->do_transaction_failed = arm_cpu_do_transaction_failed; | 107 | + |
44 | cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; | 108 | +/* Share AArch32 -cpu max features with AArch64. */ |
45 | cc->asidx_from_attrs = arm_asidx_from_attrs; | 109 | +void aa32_max_features(ARMCPU *cpu) |
46 | cc->vmsd = &vmstate_arm_cpu; | ||
47 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/op_helper.c | ||
50 | +++ b/target/arm/op_helper.c | ||
51 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | ||
52 | deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); | ||
53 | } | ||
54 | |||
55 | +/* arm_cpu_do_transaction_failed: handle a memory system error response | ||
56 | + * (eg "no device/memory present at address") by raising an external abort | ||
57 | + * exception | ||
58 | + */ | ||
59 | +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | ||
60 | + vaddr addr, unsigned size, | ||
61 | + MMUAccessType access_type, | ||
62 | + int mmu_idx, MemTxAttrs attrs, | ||
63 | + MemTxResult response, uintptr_t retaddr) | ||
64 | +{ | 110 | +{ |
65 | + ARMCPU *cpu = ARM_CPU(cs); | 111 | + uint32_t t; |
66 | + CPUARMState *env = &cpu->env; | 112 | + |
67 | + uint32_t fsr, fsc; | 113 | + /* Add additional features supported by QEMU */ |
68 | + ARMMMUFaultInfo fi = {}; | 114 | + t = cpu->isar.id_isar5; |
69 | + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); | 115 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); |
70 | + | 116 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); |
71 | + if (retaddr) { | 117 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); |
72 | + /* now we have a real cpu fault */ | 118 | + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); |
73 | + cpu_restore_state(cs, retaddr); | 119 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); |
74 | + } | 120 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); |
75 | + | 121 | + cpu->isar.id_isar5 = t; |
76 | + /* The EA bit in syndromes and fault status registers is an | 122 | + |
77 | + * IMPDEF classification of external aborts. ARM implementations | 123 | + t = cpu->isar.id_isar6; |
78 | + * usually use this to indicate AXI bus Decode error (0) or | 124 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); |
79 | + * Slave error (1); in QEMU we follow that. | 125 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); |
80 | + */ | 126 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); |
81 | + fi.ea = (response != MEMTX_DECODE_ERROR); | 127 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); |
82 | + | 128 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); |
83 | + /* The fault status register format depends on whether we're using | 129 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); |
84 | + * the LPAE long descriptor format, or the short descriptor format. | 130 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); |
85 | + */ | 131 | + cpu->isar.id_isar6 = t; |
86 | + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { | 132 | + |
87 | + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ | 133 | + t = cpu->isar.mvfr1; |
88 | + fsr = (fi.ea << 12) | (1 << 9) | 0x10; | 134 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ |
89 | + } else { | 135 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ |
90 | + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ | 136 | + cpu->isar.mvfr1 = t; |
91 | + fsr = (fi.ea << 12) | 0x8; | 137 | + |
92 | + } | 138 | + t = cpu->isar.mvfr2; |
93 | + fsc = 0x10; | 139 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ |
94 | + | 140 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ |
95 | + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); | 141 | + cpu->isar.mvfr2 = t; |
142 | + | ||
143 | + t = cpu->isar.id_mmfr3; | ||
144 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
145 | + cpu->isar.id_mmfr3 = t; | ||
146 | + | ||
147 | + t = cpu->isar.id_mmfr4; | ||
148 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
149 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
150 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
151 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
152 | + cpu->isar.id_mmfr4 = t; | ||
153 | + | ||
154 | + t = cpu->isar.id_pfr0; | ||
155 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
156 | + cpu->isar.id_pfr0 = t; | ||
157 | + | ||
158 | + t = cpu->isar.id_pfr2; | ||
159 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
160 | + cpu->isar.id_pfr2 = t; | ||
161 | + | ||
162 | + t = cpu->isar.id_dfr0; | ||
163 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
164 | + cpu->isar.id_dfr0 = t; | ||
96 | +} | 165 | +} |
97 | + | 166 | + |
98 | #endif /* !defined(CONFIG_USER_ONLY) */ | 167 | #ifndef CONFIG_USER_ONLY |
99 | 168 | static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
100 | uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) | 169 | { |
170 | @@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) | ||
171 | static void arm_max_initfn(Object *obj) | ||
172 | { | ||
173 | ARMCPU *cpu = ARM_CPU(obj); | ||
174 | - uint32_t t; | ||
175 | |||
176 | /* aarch64_a57_initfn, advertising none of the aarch64 features */ | ||
177 | cpu->dtb_compatible = "arm,cortex-a57"; | ||
178 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
179 | cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
180 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
181 | |||
182 | - /* Add additional features supported by QEMU */ | ||
183 | - t = cpu->isar.id_isar5; | ||
184 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); | ||
185 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | ||
186 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | ||
187 | - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | ||
188 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | ||
189 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | ||
190 | - cpu->isar.id_isar5 = t; | ||
191 | - | ||
192 | - t = cpu->isar.id_isar6; | ||
193 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
194 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
195 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
196 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
197 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
198 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); | ||
199 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); | ||
200 | - cpu->isar.id_isar6 = t; | ||
201 | - | ||
202 | - t = cpu->isar.mvfr1; | ||
203 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ | ||
204 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ | ||
205 | - cpu->isar.mvfr1 = t; | ||
206 | - | ||
207 | - t = cpu->isar.mvfr2; | ||
208 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | ||
209 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | ||
210 | - cpu->isar.mvfr2 = t; | ||
211 | - | ||
212 | - t = cpu->isar.id_mmfr3; | ||
213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ | ||
214 | - cpu->isar.id_mmfr3 = t; | ||
215 | - | ||
216 | - t = cpu->isar.id_mmfr4; | ||
217 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
218 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
219 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
220 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
221 | - cpu->isar.id_mmfr4 = t; | ||
222 | - | ||
223 | - t = cpu->isar.id_pfr0; | ||
224 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); | ||
225 | - cpu->isar.id_pfr0 = t; | ||
226 | - | ||
227 | - t = cpu->isar.id_pfr2; | ||
228 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); | ||
229 | - cpu->isar.id_pfr2 = t; | ||
230 | - | ||
231 | - t = cpu->isar.id_dfr0; | ||
232 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
233 | - cpu->isar.id_dfr0 = t; | ||
234 | + aa32_max_features(cpu); | ||
235 | |||
236 | #ifdef CONFIG_USER_ONLY | ||
237 | /* | ||
101 | -- | 238 | -- |
102 | 2.7.4 | 239 | 2.25.1 |
103 | |||
104 | diff view generated by jsdifflib |
1 | For v8M the range 0xe002e000..0xe002efff is an alias region which | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | for secure accesses behaves like a NonSecure access to the main | ||
3 | SCS region. (For nonsecure accesses including when the security | ||
4 | extension is not implemented, it is RAZ/WI.) | ||
5 | 2 | ||
3 | Update the legacy feature names to the current names. | ||
4 | Provide feature names for id changes that were not marked. | ||
5 | Sort the field updates into increasing bitfield order. | ||
6 | |||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220506180242.216785-10-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 1503414539-28762-11-git-send-email-peter.maydell@linaro.org | ||
8 | --- | 11 | --- |
9 | include/hw/intc/armv7m_nvic.h | 1 + | 12 | target/arm/cpu64.c | 100 +++++++++++++++++++++---------------------- |
10 | hw/intc/armv7m_nvic.c | 66 ++++++++++++++++++++++++++++++++++++++++++- | 13 | target/arm/cpu_tcg.c | 48 ++++++++++----------- |
11 | 2 files changed, 66 insertions(+), 1 deletion(-) | 14 | 2 files changed, 74 insertions(+), 74 deletions(-) |
12 | 15 | ||
13 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | 16 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/intc/armv7m_nvic.h | 18 | --- a/target/arm/cpu64.c |
16 | +++ b/include/hw/intc/armv7m_nvic.h | 19 | +++ b/target/arm/cpu64.c |
17 | @@ -XXX,XX +XXX,XX @@ typedef struct NVICState { | 20 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
18 | int exception_prio; /* group prio of the highest prio active exception */ | 21 | cpu->midr = t; |
19 | 22 | ||
20 | MemoryRegion sysregmem; | 23 | t = cpu->isar.id_aa64isar0; |
21 | + MemoryRegion sysreg_ns_mem; | 24 | - t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ |
22 | MemoryRegion container; | 25 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); |
23 | 26 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ | |
24 | uint32_t num_irq; | 27 | + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ |
25 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 28 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ |
29 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ | ||
30 | t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | ||
31 | - t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); | ||
32 | - t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); | ||
33 | - t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); | ||
34 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); | ||
35 | - t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); | ||
36 | - t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); | ||
37 | - t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); | ||
38 | - t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ | ||
39 | - t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | ||
40 | - t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); | ||
41 | + t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ | ||
42 | + t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | ||
43 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | ||
44 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ | ||
45 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ | ||
46 | + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ | ||
47 | + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ | ||
48 | + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ | ||
49 | + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ | ||
50 | + t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ | ||
51 | cpu->isar.id_aa64isar0 = t; | ||
52 | |||
53 | t = cpu->isar.id_aa64isar1; | ||
54 | - t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); | ||
55 | - t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); | ||
56 | - t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); | ||
57 | - t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | ||
58 | - t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | ||
59 | - t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); | ||
60 | - t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); | ||
61 | - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ | ||
62 | - t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); | ||
63 | + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ | ||
64 | + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ | ||
65 | + t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ | ||
66 | + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ | ||
67 | + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ | ||
68 | + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ | ||
69 | + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ | ||
70 | + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ | ||
71 | + t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ | ||
72 | cpu->isar.id_aa64isar1 = t; | ||
73 | |||
74 | t = cpu->isar.id_aa64pfr0; | ||
75 | + t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ | ||
76 | + t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ | ||
77 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
78 | - t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); | ||
79 | - t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); | ||
80 | - t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); | ||
81 | - t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); | ||
82 | + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
83 | + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
84 | cpu->isar.id_aa64pfr0 = t; | ||
85 | |||
86 | t = cpu->isar.id_aa64pfr1; | ||
87 | - t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | ||
88 | - t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); | ||
89 | + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ | ||
90 | + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ | ||
91 | /* | ||
92 | * Begin with full support for MTE. This will be downgraded to MTE=0 | ||
93 | * during realize if the board provides no tag memory, much like | ||
94 | * we do for EL2 with the virtualization=on property. | ||
95 | */ | ||
96 | - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); | ||
97 | + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
98 | cpu->isar.id_aa64pfr1 = t; | ||
99 | |||
100 | t = cpu->isar.id_aa64mmfr0; | ||
101 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
102 | cpu->isar.id_aa64mmfr0 = t; | ||
103 | |||
104 | t = cpu->isar.id_aa64mmfr1; | ||
105 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | ||
106 | - t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); | ||
107 | - t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); | ||
108 | - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ | ||
109 | - t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ | ||
110 | - t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ | ||
111 | + t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | ||
112 | + t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | ||
113 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | ||
114 | + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | ||
115 | + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ | ||
116 | + t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | ||
117 | cpu->isar.id_aa64mmfr1 = t; | ||
118 | |||
119 | t = cpu->isar.id_aa64mmfr2; | ||
120 | - t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | ||
121 | - t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | ||
122 | - t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | ||
123 | - t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
124 | - t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
125 | - t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
126 | + t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ | ||
127 | + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ | ||
128 | + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
129 | + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ | ||
130 | + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
131 | + t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
132 | cpu->isar.id_aa64mmfr2 = t; | ||
133 | |||
134 | t = cpu->isar.id_aa64zfr0; | ||
135 | t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); | ||
136 | - t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ | ||
137 | - t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); | ||
138 | - t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); | ||
139 | - t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); | ||
140 | - t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); | ||
141 | - t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); | ||
142 | - t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); | ||
143 | - t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); | ||
144 | + t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ | ||
145 | + t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ | ||
146 | + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ | ||
147 | + t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ | ||
148 | + t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ | ||
149 | + t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ | ||
150 | + t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ | ||
151 | + t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ | ||
152 | cpu->isar.id_aa64zfr0 = t; | ||
153 | |||
154 | t = cpu->isar.id_aa64dfr0; | ||
155 | - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
156 | + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ | ||
157 | cpu->isar.id_aa64dfr0 = t; | ||
158 | |||
159 | /* Replicate the same data to the 32-bit id registers. */ | ||
160 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | 161 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/hw/intc/armv7m_nvic.c | 162 | --- a/target/arm/cpu_tcg.c |
28 | +++ b/hw/intc/armv7m_nvic.c | 163 | +++ b/target/arm/cpu_tcg.c |
29 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_sysreg_ops = { | 164 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
30 | .endianness = DEVICE_NATIVE_ENDIAN, | 165 | |
31 | }; | 166 | /* Add additional features supported by QEMU */ |
32 | 167 | t = cpu->isar.id_isar5; | |
33 | +static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, | 168 | - t = FIELD_DP32(t, ID_ISAR5, AES, 2); |
34 | + uint64_t value, unsigned size, | 169 | - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); |
35 | + MemTxAttrs attrs) | 170 | - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); |
36 | +{ | 171 | + t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ |
37 | + if (attrs.secure) { | 172 | + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ |
38 | + /* S accesses to the alias act like NS accesses to the real region */ | 173 | + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ |
39 | + attrs.secure = 0; | 174 | t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); |
40 | + return nvic_sysreg_write(opaque, addr, value, size, attrs); | 175 | - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); |
41 | + } else { | 176 | - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); |
42 | + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ | 177 | + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ |
43 | + if (attrs.user) { | 178 | + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ |
44 | + return MEMTX_ERROR; | 179 | cpu->isar.id_isar5 = t; |
45 | + } | 180 | |
46 | + return MEMTX_OK; | 181 | t = cpu->isar.id_isar6; |
47 | + } | 182 | - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); |
48 | +} | 183 | - t = FIELD_DP32(t, ID_ISAR6, DP, 1); |
49 | + | 184 | - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); |
50 | +static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, | 185 | - t = FIELD_DP32(t, ID_ISAR6, SB, 1); |
51 | + uint64_t *data, unsigned size, | 186 | - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); |
52 | + MemTxAttrs attrs) | 187 | - t = FIELD_DP32(t, ID_ISAR6, BF16, 1); |
53 | +{ | 188 | - t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); |
54 | + if (attrs.secure) { | 189 | + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ |
55 | + /* S accesses to the alias act like NS accesses to the real region */ | 190 | + t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ |
56 | + attrs.secure = 0; | 191 | + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ |
57 | + return nvic_sysreg_read(opaque, addr, data, size, attrs); | 192 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ |
58 | + } else { | 193 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ |
59 | + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ | 194 | + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ |
60 | + if (attrs.user) { | 195 | + t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ |
61 | + return MEMTX_ERROR; | 196 | cpu->isar.id_isar6 = t; |
62 | + } | 197 | |
63 | + *data = 0; | 198 | t = cpu->isar.mvfr1; |
64 | + return MEMTX_OK; | 199 | - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ |
65 | + } | 200 | - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ |
66 | +} | 201 | + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ |
67 | + | 202 | + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ |
68 | +static const MemoryRegionOps nvic_sysreg_ns_ops = { | 203 | cpu->isar.mvfr1 = t; |
69 | + .read_with_attrs = nvic_sysreg_ns_read, | 204 | |
70 | + .write_with_attrs = nvic_sysreg_ns_write, | 205 | t = cpu->isar.mvfr2; |
71 | + .endianness = DEVICE_NATIVE_ENDIAN, | 206 | - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ |
72 | +}; | 207 | - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ |
73 | + | 208 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ |
74 | static int nvic_post_load(void *opaque, int version_id) | 209 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ |
75 | { | 210 | cpu->isar.mvfr2 = t; |
76 | NVICState *s = opaque; | 211 | |
77 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | 212 | t = cpu->isar.id_mmfr3; |
78 | NVICState *s = NVIC(dev); | 213 | - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ |
79 | SysBusDevice *systick_sbd; | 214 | + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ |
80 | Error *err = NULL; | 215 | cpu->isar.id_mmfr3 = t; |
81 | + int regionlen; | 216 | |
82 | 217 | t = cpu->isar.id_mmfr4; | |
83 | s->cpu = ARM_CPU(qemu_get_cpu(0)); | 218 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ |
84 | assert(s->cpu); | 219 | - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ |
85 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | 220 | - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ |
86 | * 0xd00..0xd3c - SCS registers | 221 | - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ |
87 | * 0xd40..0xeff - Reserved or Not implemented | 222 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ |
88 | * 0xf00 - STIR | 223 | + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ |
89 | + * | 224 | + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ |
90 | + * Some registers within this space are banked between security states. | 225 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ |
91 | + * In v8M there is a second range 0xe002e000..0xe002efff which is the | 226 | cpu->isar.id_mmfr4 = t; |
92 | + * NonSecure alias SCS; secure accesses to this behave like NS accesses | 227 | |
93 | + * to the main SCS range, and non-secure accesses (including when | 228 | t = cpu->isar.id_pfr0; |
94 | + * the security extension is not implemented) are RAZ/WI. | 229 | - t = FIELD_DP32(t, ID_PFR0, DIT, 1); |
95 | + * Note that both the main SCS range and the alias range are defined | 230 | + t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ |
96 | + * to be exempt from memory attribution (R_BLJT) and so the memory | 231 | cpu->isar.id_pfr0 = t; |
97 | + * transaction attribute always matches the current CPU security | 232 | |
98 | + * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops | 233 | t = cpu->isar.id_pfr2; |
99 | + * wrappers we change attrs.secure to indicate the NS access; so | 234 | - t = FIELD_DP32(t, ID_PFR2, SSBS, 1); |
100 | + * generally code determining which banked register to use should | 235 | + t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ |
101 | + * use attrs.secure; code determining actual behaviour of the system | 236 | cpu->isar.id_pfr2 = t; |
102 | + * should use env->v7m.secure. | 237 | |
103 | */ | 238 | t = cpu->isar.id_dfr0; |
104 | - memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); | 239 | - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ |
105 | + regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; | 240 | + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ |
106 | + memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); | 241 | cpu->isar.id_dfr0 = t; |
107 | /* The system register region goes at the bottom of the priority | ||
108 | * stack as it covers the whole page. | ||
109 | */ | ||
110 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | ||
111 | sysbus_mmio_get_region(systick_sbd, 0), | ||
112 | 1); | ||
113 | |||
114 | + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { | ||
115 | + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), | ||
116 | + &nvic_sysreg_ns_ops, s, | ||
117 | + "nvic_sysregs_ns", 0x1000); | ||
118 | + memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); | ||
119 | + } | ||
120 | + | ||
121 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); | ||
122 | } | 242 | } |
123 | 243 | ||
124 | -- | 244 | -- |
125 | 2.7.4 | 245 | 2.25.1 |
126 | |||
127 | diff view generated by jsdifflib |
1 | If a v8M CPU supports the security extension then we need to | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | give it two AddressSpaces, the same way we do already for | ||
3 | an A profile core with EL3. | ||
4 | 2 | ||
3 | Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 | ||
4 | during arm_cpu_realizefn. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-11-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 1503414539-28762-5-git-send-email-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | target/arm/cpu.c | 13 ++++++------- | 11 | target/arm/cpu.c | 22 +++++++++++++--------- |
10 | 1 file changed, 6 insertions(+), 7 deletions(-) | 12 | 1 file changed, 13 insertions(+), 9 deletions(-) |
11 | 13 | ||
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/cpu.c | 16 | --- a/target/arm/cpu.c |
15 | +++ b/target/arm/cpu.c | 17 | +++ b/target/arm/cpu.c |
16 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
17 | init_cpreg_list(cpu); | 19 | */ |
20 | unset_feature(env, ARM_FEATURE_EL3); | ||
21 | |||
22 | - /* Disable the security extension feature bits in the processor feature | ||
23 | - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. | ||
24 | + /* | ||
25 | + * Disable the security extension feature bits in the processor | ||
26 | + * feature registers as well. | ||
27 | */ | ||
28 | - cpu->isar.id_pfr1 &= ~0xf0; | ||
29 | - cpu->isar.id_aa64pfr0 &= ~0xf000; | ||
30 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | ||
31 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
32 | + ID_AA64PFR0, EL3, 0); | ||
33 | } | ||
34 | |||
35 | if (!cpu->has_el2) { | ||
36 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
37 | } | ||
38 | |||
39 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | ||
40 | - /* Disable the hypervisor feature bits in the processor feature | ||
41 | - * registers if we don't have EL2. These are id_pfr1[15:12] and | ||
42 | - * id_aa64pfr0_el1[11:8]. | ||
43 | + /* | ||
44 | + * Disable the hypervisor feature bits in the processor feature | ||
45 | + * registers if we don't have EL2. | ||
46 | */ | ||
47 | - cpu->isar.id_aa64pfr0 &= ~0xf00; | ||
48 | - cpu->isar.id_pfr1 &= ~0xf000; | ||
49 | + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
50 | + ID_AA64PFR0, EL2, 0); | ||
51 | + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, | ||
52 | + ID_PFR1, VIRTUALIZATION, 0); | ||
53 | } | ||
18 | 54 | ||
19 | #ifndef CONFIG_USER_ONLY | 55 | #ifndef CONFIG_USER_ONLY |
20 | - if (cpu->has_el3) { | ||
21 | - cs->num_ases = 2; | ||
22 | - } else { | ||
23 | - cs->num_ases = 1; | ||
24 | - } | ||
25 | - | ||
26 | - if (cpu->has_el3) { | ||
27 | + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
28 | AddressSpace *as; | ||
29 | |||
30 | + cs->num_ases = 2; | ||
31 | + | ||
32 | if (!cpu->secure_memory) { | ||
33 | cpu->secure_memory = cs->memory; | ||
34 | } | ||
35 | as = address_space_init_shareable(cpu->secure_memory, | ||
36 | "cpu-secure-memory"); | ||
37 | cpu_address_space_init(cs, as, ARMASIdx_S); | ||
38 | + } else { | ||
39 | + cs->num_ases = 1; | ||
40 | } | ||
41 | + | ||
42 | cpu_address_space_init(cs, | ||
43 | address_space_init_shareable(cs->memory, | ||
44 | "cpu-memory"), | ||
45 | -- | 56 | -- |
46 | 2.7.4 | 57 | 2.25.1 |
47 | |||
48 | diff view generated by jsdifflib |
1 | From: Portia Stephens <portia.stephens@xilinx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This adds a feature bit indicating support of the (trivial) Jazelle | 3 | The only portion of FEAT_Debugv8p2 that is relevant to QEMU |
4 | implementation if ARM_FEATURE_V6 is set or if the processor is arm926 | 4 | is CONTEXTIDR_EL2, which is also conditionally implemented |
5 | or arm1026. This fixes the issue that any BXJ instruction will | 5 | with FEAT_VHE. The rest of the debug extension concerns the |
6 | result in an illegal_op. BXJ instructions will now check if the | 6 | External debug interface, which is outside the scope of QEMU. |
7 | architecture supports ARM_FEATURE_JAZELLE. | ||
8 | 7 | ||
9 | Signed-off-by: Portia Stephens <portia.stephens@xilinx.com> | ||
10 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
11 | Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com | ||
12 | [PMM: edited commit message and comment text a bit] | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220506180242.216785-12-richard.henderson@linaro.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 12 | --- |
16 | target/arm/cpu.h | 1 + | 13 | docs/system/arm/emulation.rst | 1 + |
17 | target/arm/cpu.c | 3 +++ | 14 | target/arm/cpu.c | 1 + |
18 | target/arm/translate.c | 2 +- | 15 | target/arm/cpu64.c | 1 + |
19 | 3 files changed, 5 insertions(+), 1 deletion(-) | 16 | target/arm/cpu_tcg.c | 2 ++ |
17 | 4 files changed, 5 insertions(+) | ||
20 | 18 | ||
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
22 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/cpu.h | 21 | --- a/docs/system/arm/emulation.rst |
24 | +++ b/target/arm/cpu.h | 22 | +++ b/docs/system/arm/emulation.rst |
25 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
26 | ARM_FEATURE_PMU, /* has PMU support */ | 24 | - FEAT_BTI (Branch Target Identification) |
27 | ARM_FEATURE_VBAR, /* has cp15 VBAR */ | 25 | - FEAT_DIT (Data Independent Timing instructions) |
28 | ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ | 26 | - FEAT_DPB (DC CVAP instruction) |
29 | + ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ | 27 | +- FEAT_Debugv8p2 (Debug changes for v8.2) |
30 | }; | 28 | - FEAT_DotProd (Advanced SIMD dot product instructions) |
31 | 29 | - FEAT_FCMA (Floating-point complex number instructions) | |
32 | static inline int arm_feature(CPUARMState *env, int feature) | 30 | - FEAT_FHM (Floating-point half-precision multiplication instructions) |
33 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 31 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
34 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/cpu.c | 33 | --- a/target/arm/cpu.c |
36 | +++ b/target/arm/cpu.c | 34 | +++ b/target/arm/cpu.c |
37 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 35 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
36 | * feature registers as well. | ||
37 | */ | ||
38 | cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); | ||
39 | + cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); | ||
40 | cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, | ||
41 | ID_AA64PFR0, EL3, 0); | ||
38 | } | 42 | } |
39 | if (arm_feature(env, ARM_FEATURE_V6)) { | 43 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
40 | set_feature(env, ARM_FEATURE_V5); | ||
41 | + set_feature(env, ARM_FEATURE_JAZELLE); | ||
42 | if (!arm_feature(env, ARM_FEATURE_M)) { | ||
43 | set_feature(env, ARM_FEATURE_AUXCR); | ||
44 | } | ||
45 | @@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj) | ||
46 | set_feature(&cpu->env, ARM_FEATURE_VFP); | ||
47 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
48 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | ||
49 | + set_feature(&cpu->env, ARM_FEATURE_JAZELLE); | ||
50 | cpu->midr = 0x41069265; | ||
51 | cpu->reset_fpsid = 0x41011090; | ||
52 | cpu->ctr = 0x1dd20d2; | ||
53 | @@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj) | ||
54 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | ||
55 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
56 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | ||
57 | + set_feature(&cpu->env, ARM_FEATURE_JAZELLE); | ||
58 | cpu->midr = 0x4106a262; | ||
59 | cpu->reset_fpsid = 0x410110a0; | ||
60 | cpu->ctr = 0x1dd20d2; | ||
61 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
63 | --- a/target/arm/translate.c | 45 | --- a/target/arm/cpu64.c |
64 | +++ b/target/arm/translate.c | 46 | +++ b/target/arm/cpu64.c |
65 | @@ -XXX,XX +XXX,XX @@ | 47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
66 | #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) | 48 | cpu->isar.id_aa64zfr0 = t; |
67 | /* currently all emulated v5 cores are also v5TE, so don't bother */ | 49 | |
68 | #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) | 50 | t = cpu->isar.id_aa64dfr0; |
69 | -#define ENABLE_ARCH_5J 0 | 51 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ |
70 | +#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE) | 52 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ |
71 | #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) | 53 | cpu->isar.id_aa64dfr0 = t; |
72 | #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) | 54 | |
73 | #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) | 55 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c |
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/arm/cpu_tcg.c | ||
58 | +++ b/target/arm/cpu_tcg.c | ||
59 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
60 | cpu->isar.id_pfr2 = t; | ||
61 | |||
62 | t = cpu->isar.id_dfr0; | ||
63 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ | ||
64 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ | ||
65 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ | ||
66 | cpu->isar.id_dfr0 = t; | ||
67 | } | ||
74 | -- | 68 | -- |
75 | 2.7.4 | 69 | 2.25.1 |
76 | |||
77 | diff view generated by jsdifflib |
1 | Define a new MachineClass field ignore_memory_transaction_failures. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | If this is flag is true then the CPU will ignore memory transaction | ||
3 | failures which should cause the CPU to take an exception due to an | ||
4 | access to an unassigned physical address; the transaction will | ||
5 | instead return zero (for a read) or be ignored (for a write). This | ||
6 | should be set only by legacy board models which rely on the old | ||
7 | RAZ/WI behaviour for handling devices that QEMU does not yet model. | ||
8 | New board models should instead use "unimplemented-device" for all | ||
9 | memory ranges where the guest will attempt to probe for a device that | ||
10 | QEMU doesn't implement and a stub device is required. | ||
11 | 2 | ||
12 | We need this for ARM boards, where we're about to implement support for | 3 | This extension concerns changes to the External Debug interface, |
13 | generating external aborts on memory transaction failures. Too many | 4 | with Secure and Non-secure access to the debug registers, and all |
14 | of our legacy board models rely on the RAZ/WI behaviour and we | 5 | of it is outside the scope of QEMU. Indicating support for this |
15 | would break currently working guests when their "probe for device" | 6 | is mandatory with FEAT_SEL2, which we do implement. |
16 | code provoked an external abort rather than a RAZ. | ||
17 | 7 | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220506180242.216785-13-richard.henderson@linaro.org | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
21 | Message-id: 1504626814-23124-2-git-send-email-peter.maydell@linaro.org | ||
22 | --- | 12 | --- |
23 | include/hw/boards.h | 11 +++++++++++ | 13 | docs/system/arm/emulation.rst | 1 + |
24 | include/qom/cpu.h | 7 ++++++- | 14 | target/arm/cpu64.c | 2 +- |
25 | qom/cpu.c | 16 ++++++++++++++++ | 15 | target/arm/cpu_tcg.c | 4 ++-- |
26 | 3 files changed, 33 insertions(+), 1 deletion(-) | 16 | 3 files changed, 4 insertions(+), 3 deletions(-) |
27 | 17 | ||
28 | diff --git a/include/hw/boards.h b/include/hw/boards.h | 18 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
29 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/include/hw/boards.h | 20 | --- a/docs/system/arm/emulation.rst |
31 | +++ b/include/hw/boards.h | 21 | +++ b/docs/system/arm/emulation.rst |
32 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 22 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
33 | * size than the target architecture's minimum. (Attempting to create | 23 | - FEAT_DIT (Data Independent Timing instructions) |
34 | * such a CPU will fail.) Note that changing this is a migration | 24 | - FEAT_DPB (DC CVAP instruction) |
35 | * compatibility break for the machine. | 25 | - FEAT_Debugv8p2 (Debug changes for v8.2) |
36 | + * @ignore_memory_transaction_failures: | 26 | +- FEAT_Debugv8p4 (Debug changes for v8.4) |
37 | + * If this is flag is true then the CPU will ignore memory transaction | 27 | - FEAT_DotProd (Advanced SIMD dot product instructions) |
38 | + * failures which should cause the CPU to take an exception due to an | 28 | - FEAT_FCMA (Floating-point complex number instructions) |
39 | + * access to an unassigned physical address; the transaction will instead | 29 | - FEAT_FHM (Floating-point half-precision multiplication instructions) |
40 | + * return zero (for a read) or be ignored (for a write). This should be | 30 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
41 | + * set only by legacy board models which rely on the old RAZ/WI behaviour | ||
42 | + * for handling devices that QEMU does not yet model. New board models | ||
43 | + * should instead use "unimplemented-device" for all memory ranges where | ||
44 | + * the guest will attempt to probe for a device that QEMU doesn't | ||
45 | + * implement and a stub device is required. | ||
46 | */ | ||
47 | struct MachineClass { | ||
48 | /*< private >*/ | ||
49 | @@ -XXX,XX +XXX,XX @@ struct MachineClass { | ||
50 | bool rom_file_has_mr; | ||
51 | int minimum_page_bits; | ||
52 | bool has_hotpluggable_cpus; | ||
53 | + bool ignore_memory_transaction_failures; | ||
54 | int numa_mem_align_shift; | ||
55 | void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes, | ||
56 | int nb_nodes, ram_addr_t size); | ||
57 | diff --git a/include/qom/cpu.h b/include/qom/cpu.h | ||
58 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
59 | --- a/include/qom/cpu.h | 32 | --- a/target/arm/cpu64.c |
60 | +++ b/include/qom/cpu.h | 33 | +++ b/target/arm/cpu64.c |
61 | @@ -XXX,XX +XXX,XX @@ struct qemu_work_item; | 34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
62 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes | 35 | cpu->isar.id_aa64zfr0 = t; |
63 | * to @trace_dstate). | 36 | |
64 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). | 37 | t = cpu->isar.id_aa64dfr0; |
65 | + * @ignore_memory_transaction_failures: Cached copy of the MachineState | 38 | - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ |
66 | + * flag of the same name: allows the board to suppress calling of the | 39 | + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ |
67 | + * CPU do_transaction_failed hook function. | 40 | t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ |
68 | * | 41 | cpu->isar.id_aa64dfr0 = t; |
69 | * State of one CPU core or thread. | 42 | |
70 | */ | 43 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c |
71 | @@ -XXX,XX +XXX,XX @@ struct CPUState { | ||
72 | */ | ||
73 | bool throttle_thread_scheduled; | ||
74 | |||
75 | + bool ignore_memory_transaction_failures; | ||
76 | + | ||
77 | /* Note that this is accessed at the start of every TB via a negative | ||
78 | offset from AREG0. Leave this field at the end so as to make the | ||
79 | (absolute value) offset as small as possible. This reduces code | ||
80 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, | ||
81 | { | ||
82 | CPUClass *cc = CPU_GET_CLASS(cpu); | ||
83 | |||
84 | - if (cc->do_transaction_failed) { | ||
85 | + if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { | ||
86 | cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, | ||
87 | mmu_idx, attrs, response, retaddr); | ||
88 | } | ||
89 | diff --git a/qom/cpu.c b/qom/cpu.c | ||
90 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
91 | --- a/qom/cpu.c | 45 | --- a/target/arm/cpu_tcg.c |
92 | +++ b/qom/cpu.c | 46 | +++ b/target/arm/cpu_tcg.c |
93 | @@ -XXX,XX +XXX,XX @@ | 47 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
94 | #include "exec/cpu-common.h" | 48 | cpu->isar.id_pfr2 = t; |
95 | #include "qemu/error-report.h" | 49 | |
96 | #include "sysemu/sysemu.h" | 50 | t = cpu->isar.id_dfr0; |
97 | +#include "hw/boards.h" | 51 | - t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ |
98 | #include "hw/qdev-properties.h" | 52 | - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ |
99 | #include "trace-root.h" | 53 | + t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ |
100 | 54 | + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ | |
101 | @@ -XXX,XX +XXX,XX @@ static void cpu_common_parse_features(const char *typename, char *features, | 55 | t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ |
102 | static void cpu_common_realizefn(DeviceState *dev, Error **errp) | 56 | cpu->isar.id_dfr0 = t; |
103 | { | 57 | } |
104 | CPUState *cpu = CPU(dev); | ||
105 | + Object *machine = qdev_get_machine(); | ||
106 | + | ||
107 | + /* qdev_get_machine() can return something that's not TYPE_MACHINE | ||
108 | + * if this is one of the user-only emulators; in that case there's | ||
109 | + * no need to check the ignore_memory_transaction_failures board flag. | ||
110 | + */ | ||
111 | + if (object_dynamic_cast(machine, TYPE_MACHINE)) { | ||
112 | + ObjectClass *oc = object_get_class(machine); | ||
113 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
114 | + | ||
115 | + if (mc) { | ||
116 | + cpu->ignore_memory_transaction_failures = | ||
117 | + mc->ignore_memory_transaction_failures; | ||
118 | + } | ||
119 | + } | ||
120 | |||
121 | if (dev->hotplugged) { | ||
122 | cpu_synchronize_post_init(cpu); | ||
123 | -- | 58 | -- |
124 | 2.7.4 | 59 | 2.25.1 |
125 | |||
126 | diff view generated by jsdifflib |
1 | Make the VTOR register banked if v8M security extensions are enabled. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add only the system registers required to implement zero error | ||
4 | records. This means that all values for ERRSELR are out of range, | ||
5 | which means that it and all of the indexed error record registers | ||
6 | need not be implemented. | ||
7 | |||
8 | Add the EL2 registers required for injecting virtual SError. | ||
9 | |||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20220506180242.216785-14-richard.henderson@linaro.org | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org | ||
6 | --- | 14 | --- |
7 | target/arm/cpu.h | 2 +- | 15 | target/arm/cpu.h | 5 +++ |
8 | hw/intc/armv7m_nvic.c | 13 +++++++------ | 16 | target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ |
9 | target/arm/helper.c | 2 +- | 17 | 2 files changed, 89 insertions(+) |
10 | target/arm/machine.c | 3 ++- | ||
11 | 4 files changed, 11 insertions(+), 9 deletions(-) | ||
12 | 18 | ||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
14 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.h | 21 | --- a/target/arm/cpu.h |
16 | +++ b/target/arm/cpu.h | 22 | +++ b/target/arm/cpu.h |
17 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 23 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
24 | uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ | ||
25 | uint64_t gcr_el1; | ||
26 | uint64_t rgsr_el1; | ||
27 | + | ||
28 | + /* Minimal RAS registers */ | ||
29 | + uint64_t disr_el1; | ||
30 | + uint64_t vdisr_el2; | ||
31 | + uint64_t vsesr_el2; | ||
32 | } cp15; | ||
18 | 33 | ||
19 | struct { | 34 | struct { |
20 | uint32_t other_sp; | ||
21 | - uint32_t vecbase; | ||
22 | + uint32_t vecbase[2]; | ||
23 | uint32_t basepri[2]; | ||
24 | uint32_t control[2]; | ||
25 | uint32_t ccr; /* Configuration and Control */ | ||
26 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/hw/intc/armv7m_nvic.c | ||
29 | +++ b/hw/intc/armv7m_nvic.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level) | ||
31 | } | ||
32 | } | ||
33 | |||
34 | -static uint32_t nvic_readl(NVICState *s, uint32_t offset) | ||
35 | +static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
36 | { | ||
37 | ARMCPU *cpu = s->cpu; | ||
38 | uint32_t val; | ||
39 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) | ||
40 | /* ISRPREEMPT not implemented */ | ||
41 | return val; | ||
42 | case 0xd08: /* Vector Table Offset. */ | ||
43 | - return cpu->env.v7m.vecbase; | ||
44 | + return cpu->env.v7m.vecbase[attrs.secure]; | ||
45 | case 0xd0c: /* Application Interrupt/Reset Control. */ | ||
46 | return 0xfa050000 | (s->prigroup << 8); | ||
47 | case 0xd10: /* System Control. */ | ||
48 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) | ||
49 | } | ||
50 | } | ||
51 | |||
52 | -static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
53 | +static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
54 | + MemTxAttrs attrs) | ||
55 | { | ||
56 | ARMCPU *cpu = s->cpu; | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
59 | } | ||
60 | break; | ||
61 | case 0xd08: /* Vector Table Offset. */ | ||
62 | - cpu->env.v7m.vecbase = value & 0xffffff80; | ||
63 | + cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; | ||
64 | break; | ||
65 | case 0xd0c: /* Application Interrupt/Reset Control. */ | ||
66 | if ((value >> 16) == 0x05fa) { | ||
67 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, | ||
68 | break; | ||
69 | default: | ||
70 | if (size == 4) { | ||
71 | - val = nvic_readl(s, offset); | ||
72 | + val = nvic_readl(s, offset, attrs); | ||
73 | } else { | ||
74 | qemu_log_mask(LOG_GUEST_ERROR, | ||
75 | "NVIC: Bad read of size %d at offset 0x%x\n", | ||
76 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, | ||
77 | return MEMTX_OK; | ||
78 | } | ||
79 | if (size == 4) { | ||
80 | - nvic_writel(s, offset, value); | ||
81 | + nvic_writel(s, offset, value, attrs); | ||
82 | return MEMTX_OK; | ||
83 | } | ||
84 | qemu_log_mask(LOG_GUEST_ERROR, | ||
85 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 35 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
86 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
87 | --- a/target/arm/helper.c | 37 | --- a/target/arm/helper.c |
88 | +++ b/target/arm/helper.c | 38 | +++ b/target/arm/helper.c |
89 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu) | 39 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { |
90 | CPUState *cs = CPU(cpu); | 40 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, |
91 | CPUARMState *env = &cpu->env; | 41 | }; |
92 | MemTxResult result; | 42 | |
93 | - hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; | 43 | +/* |
94 | + hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4; | 44 | + * Check for traps to RAS registers, which are controlled |
95 | uint32_t addr; | 45 | + * by HCR_EL2.TERR and SCR_EL3.TERR. |
96 | 46 | + */ | |
97 | addr = address_space_ldl(cs->as, vec, | 47 | +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, |
98 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 48 | + bool isread) |
99 | index XXXXXXX..XXXXXXX 100644 | 49 | +{ |
100 | --- a/target/arm/machine.c | 50 | + int el = arm_current_el(env); |
101 | +++ b/target/arm/machine.c | 51 | + |
102 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 52 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { |
103 | .minimum_version_id = 4, | 53 | + return CP_ACCESS_TRAP_EL2; |
104 | .needed = m_needed, | 54 | + } |
105 | .fields = (VMStateField[]) { | 55 | + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { |
106 | - VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), | 56 | + return CP_ACCESS_TRAP_EL3; |
107 | + VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), | 57 | + } |
108 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | 58 | + return CP_ACCESS_OK; |
109 | VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), | 59 | +} |
110 | VMSTATE_UINT32(env.v7m.ccr, ARMCPU), | 60 | + |
111 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 61 | +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
112 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | 62 | +{ |
113 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | 63 | + int el = arm_current_el(env); |
114 | VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), | 64 | + |
115 | + VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), | 65 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { |
116 | VMSTATE_END_OF_LIST() | 66 | + return env->cp15.vdisr_el2; |
67 | + } | ||
68 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | ||
69 | + return 0; /* RAZ/WI */ | ||
70 | + } | ||
71 | + return env->cp15.disr_el1; | ||
72 | +} | ||
73 | + | ||
74 | +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | ||
75 | +{ | ||
76 | + int el = arm_current_el(env); | ||
77 | + | ||
78 | + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | ||
79 | + env->cp15.vdisr_el2 = val; | ||
80 | + return; | ||
81 | + } | ||
82 | + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | ||
83 | + return; /* RAZ/WI */ | ||
84 | + } | ||
85 | + env->cp15.disr_el1 = val; | ||
86 | +} | ||
87 | + | ||
88 | +/* | ||
89 | + * Minimal RAS implementation with no Error Records. | ||
90 | + * Which means that all of the Error Record registers: | ||
91 | + * ERXADDR_EL1 | ||
92 | + * ERXCTLR_EL1 | ||
93 | + * ERXFR_EL1 | ||
94 | + * ERXMISC0_EL1 | ||
95 | + * ERXMISC1_EL1 | ||
96 | + * ERXMISC2_EL1 | ||
97 | + * ERXMISC3_EL1 | ||
98 | + * ERXPFGCDN_EL1 (RASv1p1) | ||
99 | + * ERXPFGCTL_EL1 (RASv1p1) | ||
100 | + * ERXPFGF_EL1 (RASv1p1) | ||
101 | + * ERXSTATUS_EL1 | ||
102 | + * and | ||
103 | + * ERRSELR_EL1 | ||
104 | + * may generate UNDEFINED, which is the effect we get by not | ||
105 | + * listing them at all. | ||
106 | + */ | ||
107 | +static const ARMCPRegInfo minimal_ras_reginfo[] = { | ||
108 | + { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | ||
109 | + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | ||
110 | + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | ||
111 | + .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | ||
112 | + { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
113 | + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | ||
114 | + .access = PL1_R, .accessfn = access_terr, | ||
115 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
116 | + { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | ||
117 | + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | ||
118 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | ||
119 | + { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | ||
120 | + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | ||
121 | + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | ||
122 | +}; | ||
123 | + | ||
124 | /* Return the exception level to which exceptions should be taken | ||
125 | * via SVEAccessTrap. If an exception should be routed through | ||
126 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | ||
127 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
128 | if (cpu_isar_feature(aa64_ssbs, cpu)) { | ||
129 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | ||
117 | } | 130 | } |
118 | }; | 131 | + if (cpu_isar_feature(any_ras, cpu)) { |
132 | + define_arm_cp_regs(cpu, minimal_ras_reginfo); | ||
133 | + } | ||
134 | |||
135 | if (cpu_isar_feature(aa64_vh, cpu) || | ||
136 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | ||
119 | -- | 137 | -- |
120 | 2.7.4 | 138 | 2.25.1 |
121 | |||
122 | diff view generated by jsdifflib |
1 | Make the FAULTMASK register banked if v8M security extensions are enabled. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Note that we do not yet implement the functionality of the new | 3 | Enable writes to the TERR and TEA bits when RAS is enabled. |
4 | AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to | 4 | These bits are otherwise RES0. |
5 | be restricted). | ||
6 | 5 | ||
7 | This patch includes the code to determine for v8M which copy | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | of FAULTMASK should be updated on exception exit; further | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | changes will be required to the exception exit code in general | 8 | Message-id: 20220506180242.216785-15-richard.henderson@linaro.org |
10 | to support v8M, so this is just a small piece of that. | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | ||
11 | target/arm/helper.c | 9 +++++++++ | ||
12 | 1 file changed, 9 insertions(+) | ||
11 | 13 | ||
12 | The v8M ARM ARM introduces a notation where individual paragraphs | ||
13 | are labelled with R (for rule) or I (for information) followed | ||
14 | by a random group of subscript letters. In comments where we want | ||
15 | to refer to a particular part of the manual we use this convention, | ||
16 | which should be more stable across document revisions than using | ||
17 | section or page numbers. | ||
18 | |||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 1503414539-28762-9-git-send-email-peter.maydell@linaro.org | ||
22 | --- | ||
23 | target/arm/cpu.h | 14 ++++++++++++-- | ||
24 | hw/intc/armv7m_nvic.c | 9 ++++++++- | ||
25 | target/arm/helper.c | 20 ++++++++++++++++---- | ||
26 | target/arm/machine.c | 5 +++-- | ||
27 | 4 files changed, 39 insertions(+), 9 deletions(-) | ||
28 | |||
29 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/cpu.h | ||
32 | +++ b/target/arm/cpu.h | ||
33 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
34 | unsigned mpu_ctrl; /* MPU_CTRL */ | ||
35 | int exception; | ||
36 | uint32_t primask[2]; | ||
37 | - uint32_t faultmask; | ||
38 | + uint32_t faultmask[2]; | ||
39 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | ||
40 | } v7m; | ||
41 | |||
42 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | ||
43 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
44 | */ | ||
45 | int armv7m_nvic_complete_irq(void *opaque, int irq); | ||
46 | +/** | ||
47 | + * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
48 | + * @opaque: the NVIC | ||
49 | + * | ||
50 | + * Returns: the raw execution priority as defined by the v8M architecture. | ||
51 | + * This is the execution priority minus the effects of AIRCR.PRIS, | ||
52 | + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
53 | + * (v8M ARM ARM I_PKLD.) | ||
54 | + */ | ||
55 | +int armv7m_nvic_raw_execution_priority(void *opaque); | ||
56 | |||
57 | /* Interface for defining coprocessor registers. | ||
58 | * Registers are defined in tables of arm_cp_reginfo structs | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) | ||
60 | * we're in a HardFault or NMI handler. | ||
61 | */ | ||
62 | if ((env->v7m.exception > 0 && env->v7m.exception <= 3) | ||
63 | - || env->v7m.faultmask) { | ||
64 | + || env->v7m.faultmask[env->v7m.secure]) { | ||
65 | mmu_idx = ARMMMUIdx_MNegPri; | ||
66 | } | ||
67 | |||
68 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/intc/armv7m_nvic.c | ||
71 | +++ b/hw/intc/armv7m_nvic.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | ||
73 | CPUARMState *env = &s->cpu->env; | ||
74 | int running; | ||
75 | |||
76 | - if (env->v7m.faultmask) { | ||
77 | + if (env->v7m.faultmask[env->v7m.secure]) { | ||
78 | running = -1; | ||
79 | } else if (env->v7m.primask[env->v7m.secure]) { | ||
80 | running = 0; | ||
81 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
82 | return nvic_exec_prio(s) > nvic_pending_prio(s); | ||
83 | } | ||
84 | |||
85 | +int armv7m_nvic_raw_execution_priority(void *opaque) | ||
86 | +{ | ||
87 | + NVICState *s = opaque; | ||
88 | + | ||
89 | + return s->exception_prio; | ||
90 | +} | ||
91 | + | ||
92 | /* caller must call nvic_irq_update() after this */ | ||
93 | static void set_prio(NVICState *s, unsigned irq, uint8_t prio) | ||
94 | { | ||
95 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
96 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
97 | --- a/target/arm/helper.c | 16 | --- a/target/arm/helper.c |
98 | +++ b/target/arm/helper.c | 17 | +++ b/target/arm/helper.c |
99 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 18 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
100 | } | 19 | } |
101 | 20 | valid_mask &= ~SCR_NET; | |
102 | if (env->v7m.exception != ARMV7M_EXCP_NMI) { | 21 | |
103 | - /* Auto-clear FAULTMASK on return from other than NMI */ | 22 | + if (cpu_isar_feature(aa64_ras, cpu)) { |
104 | - env->v7m.faultmask = 0; | 23 | + valid_mask |= SCR_TERR; |
105 | + /* Auto-clear FAULTMASK on return from other than NMI. | 24 | + } |
106 | + * If the security extension is implemented then this only | 25 | if (cpu_isar_feature(aa64_lor, cpu)) { |
107 | + * happens if the raw execution priority is >= 0; the | 26 | valid_mask |= SCR_TLOR; |
108 | + * value of the ES bit in the exception return value indicates | 27 | } |
109 | + * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) | 28 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
110 | + */ | 29 | } |
111 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 30 | } else { |
112 | + int es = type & 1; | 31 | valid_mask &= ~(SCR_RW | SCR_ST); |
113 | + if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { | 32 | + if (cpu_isar_feature(aa32_ras, cpu)) { |
114 | + env->v7m.faultmask[es] = 0; | 33 | + valid_mask |= SCR_TERR; |
115 | + } | ||
116 | + } else { | ||
117 | + env->v7m.faultmask[M_REG_NS] = 0; | ||
118 | + } | 34 | + } |
119 | } | 35 | } |
120 | 36 | ||
121 | switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { | 37 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
122 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 38 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
123 | case 18: /* BASEPRI_MAX */ | 39 | if (cpu_isar_feature(aa64_vh, cpu)) { |
124 | return env->v7m.basepri[env->v7m.secure]; | 40 | valid_mask |= HCR_E2H; |
125 | case 19: /* FAULTMASK */ | ||
126 | - return env->v7m.faultmask; | ||
127 | + return env->v7m.faultmask[env->v7m.secure]; | ||
128 | default: | ||
129 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" | ||
130 | " register %d\n", reg); | ||
131 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
132 | } | 41 | } |
133 | break; | 42 | + if (cpu_isar_feature(aa64_ras, cpu)) { |
134 | case 19: /* FAULTMASK */ | 43 | + valid_mask |= HCR_TERR | HCR_TEA; |
135 | - env->v7m.faultmask = val & 1; | 44 | + } |
136 | + env->v7m.faultmask[env->v7m.secure] = val & 1; | 45 | if (cpu_isar_feature(aa64_lor, cpu)) { |
137 | break; | 46 | valid_mask |= HCR_TLOR; |
138 | case 20: /* CONTROL */ | 47 | } |
139 | /* Writing to the SPSEL bit only has an effect if we are in | ||
140 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
141 | index XXXXXXX..XXXXXXX 100644 | ||
142 | --- a/target/arm/machine.c | ||
143 | +++ b/target/arm/machine.c | ||
144 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = { | ||
145 | .version_id = 1, | ||
146 | .minimum_version_id = 1, | ||
147 | .fields = (VMStateField[]) { | ||
148 | - VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), | ||
149 | + VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), | ||
150 | VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), | ||
151 | VMSTATE_END_OF_LIST() | ||
152 | } | ||
153 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
154 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), | ||
155 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | ||
156 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | ||
157 | + VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | ||
158 | VMSTATE_END_OF_LIST() | ||
159 | } | ||
160 | }; | ||
161 | @@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | ||
162 | * transferred using the vmstate_m_faultmask_primask subsection. | ||
163 | */ | ||
164 | if (val & CPSR_F) { | ||
165 | - env->v7m.faultmask = 1; | ||
166 | + env->v7m.faultmask[M_REG_NS] = 1; | ||
167 | } | ||
168 | if (val & CPSR_I) { | ||
169 | env->v7m.primask[M_REG_NS] = 1; | ||
170 | -- | 48 | -- |
171 | 2.7.4 | 49 | 2.25.1 |
172 | |||
173 | diff view generated by jsdifflib |
1 | Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | extensions are enabled. | ||
3 | 2 | ||
4 | We can freely add more items to vmstate_m_security without | 3 | Virtual SError exceptions are raised by setting HCR_EL2.VSE, |
5 | breaking migration compatibility, because no CPU currently | 4 | and are routed to EL1 just like other virtual exceptions. |
6 | has the ARM_FEATURE_M_SECURITY bit enabled and so this | ||
7 | subsection is not yet used by anything. | ||
8 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-16-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org | ||
12 | --- | 10 | --- |
13 | target/arm/cpu.h | 4 ++-- | 11 | target/arm/cpu.h | 2 ++ |
14 | hw/intc/armv7m_nvic.c | 8 ++++---- | 12 | target/arm/internals.h | 8 ++++++++ |
15 | target/arm/cpu.c | 26 ++++++++++++++++++++------ | 13 | target/arm/syndrome.h | 5 +++++ |
16 | target/arm/helper.c | 11 ++++++----- | 14 | target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- |
17 | target/arm/machine.c | 12 ++++++++---- | 15 | target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- |
18 | 5 files changed, 40 insertions(+), 21 deletions(-) | 16 | 5 files changed, 91 insertions(+), 2 deletions(-) |
19 | 17 | ||
20 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
21 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/cpu.h | 20 | --- a/target/arm/cpu.h |
23 | +++ b/target/arm/cpu.h | 21 | +++ b/target/arm/cpu.h |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 22 | @@ -XXX,XX +XXX,XX @@ |
25 | * pmsav7.rnr (region number register) | 23 | #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ |
26 | * pmsav7_dregion (number of configured regions) | 24 | #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ |
27 | */ | 25 | #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ |
28 | - uint32_t *rbar; | 26 | +#define EXCP_VSERR 24 |
29 | - uint32_t *rlar; | 27 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ |
30 | + uint32_t *rbar[2]; | 28 | |
31 | + uint32_t *rlar[2]; | 29 | #define ARMV7M_EXCP_RESET 1 |
32 | uint32_t mair0[2]; | 30 | @@ -XXX,XX +XXX,XX @@ enum { |
33 | uint32_t mair1[2]; | 31 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 |
34 | } pmsav8; | 32 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 |
35 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 33 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 |
36 | index XXXXXXX..XXXXXXX 100644 | 34 | +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 |
37 | --- a/hw/intc/armv7m_nvic.c | 35 | |
38 | +++ b/hw/intc/armv7m_nvic.c | 36 | /* The usual mapping for an AArch64 system register to its AArch32 |
39 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 37 | * counterpart is for the 32 bit world to have access to the lower |
40 | if (region >= cpu->pmsav7_dregion) { | 38 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
41 | return 0; | 39 | index XXXXXXX..XXXXXXX 100644 |
42 | } | 40 | --- a/target/arm/internals.h |
43 | - return cpu->env.pmsav8.rbar[region]; | 41 | +++ b/target/arm/internals.h |
44 | + return cpu->env.pmsav8.rbar[attrs.secure][region]; | 42 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu); |
45 | } | 43 | */ |
46 | 44 | void arm_cpu_update_vfiq(ARMCPU *cpu); | |
47 | if (region >= cpu->pmsav7_dregion) { | 45 | |
48 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 46 | +/** |
49 | if (region >= cpu->pmsav7_dregion) { | 47 | + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit |
50 | return 0; | 48 | + * |
51 | } | 49 | + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, |
52 | - return cpu->env.pmsav8.rlar[region]; | 50 | + * following a change to the HCR_EL2.VSE bit. |
53 | + return cpu->env.pmsav8.rlar[attrs.secure][region]; | 51 | + */ |
54 | } | 52 | +void arm_cpu_update_vserr(ARMCPU *cpu); |
55 | 53 | + | |
56 | if (region >= cpu->pmsav7_dregion) { | 54 | /** |
57 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 55 | * arm_mmu_idx_el: |
58 | if (region >= cpu->pmsav7_dregion) { | 56 | * @env: The cpu environment |
59 | return; | 57 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h |
60 | } | 58 | index XXXXXXX..XXXXXXX 100644 |
61 | - cpu->env.pmsav8.rbar[region] = value; | 59 | --- a/target/arm/syndrome.h |
62 | + cpu->env.pmsav8.rbar[attrs.secure][region] = value; | 60 | +++ b/target/arm/syndrome.h |
63 | tlb_flush(CPU(cpu)); | 61 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void) |
64 | return; | 62 | return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; |
65 | } | 63 | } |
66 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 64 | |
67 | if (region >= cpu->pmsav7_dregion) { | 65 | +static inline uint32_t syn_serror(uint32_t extra) |
68 | return; | 66 | +{ |
69 | } | 67 | + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; |
70 | - cpu->env.pmsav8.rlar[region] = value; | 68 | +} |
71 | + cpu->env.pmsav8.rlar[attrs.secure][region] = value; | 69 | + |
72 | tlb_flush(CPU(cpu)); | 70 | #endif /* TARGET_ARM_SYNDROME_H */ |
73 | return; | ||
74 | } | ||
75 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 71 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
76 | index XXXXXXX..XXXXXXX 100644 | 72 | index XXXXXXX..XXXXXXX 100644 |
77 | --- a/target/arm/cpu.c | 73 | --- a/target/arm/cpu.c |
78 | +++ b/target/arm/cpu.c | 74 | +++ b/target/arm/cpu.c |
79 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 75 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs) |
80 | if (arm_feature(env, ARM_FEATURE_PMSA)) { | 76 | return (cpu->power_state != PSCI_OFF) |
81 | if (cpu->pmsav7_dregion > 0) { | 77 | && cs->interrupt_request & |
82 | if (arm_feature(env, ARM_FEATURE_V8)) { | 78 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
83 | - memset(env->pmsav8.rbar, 0, | 79 | - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ |
84 | - sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); | 80 | + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR |
85 | - memset(env->pmsav8.rlar, 0, | 81 | | CPU_INTERRUPT_EXITTB); |
86 | - sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); | 82 | } |
87 | + memset(env->pmsav8.rbar[M_REG_NS], 0, | 83 | |
88 | + sizeof(*env->pmsav8.rbar[M_REG_NS]) | 84 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, |
89 | + * cpu->pmsav7_dregion); | 85 | return false; |
90 | + memset(env->pmsav8.rlar[M_REG_NS], 0, | 86 | } |
91 | + sizeof(*env->pmsav8.rlar[M_REG_NS]) | 87 | return !(env->daif & PSTATE_I); |
92 | + * cpu->pmsav7_dregion); | 88 | + case EXCP_VSERR: |
93 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 89 | + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { |
94 | + memset(env->pmsav8.rbar[M_REG_S], 0, | 90 | + /* VIRQs are only taken when hypervized. */ |
95 | + sizeof(*env->pmsav8.rbar[M_REG_S]) | 91 | + return false; |
96 | + * cpu->pmsav7_dregion); | 92 | + } |
97 | + memset(env->pmsav8.rlar[M_REG_S], 0, | 93 | + return !(env->daif & PSTATE_A); |
98 | + sizeof(*env->pmsav8.rlar[M_REG_S]) | 94 | default: |
99 | + * cpu->pmsav7_dregion); | 95 | g_assert_not_reached(); |
100 | + } | 96 | } |
101 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | 97 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
102 | memset(env->pmsav7.drbar, 0, | 98 | goto found; |
103 | sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | 99 | } |
104 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 100 | } |
105 | if (nr) { | 101 | + if (interrupt_request & CPU_INTERRUPT_VSERR) { |
106 | if (arm_feature(env, ARM_FEATURE_V8)) { | 102 | + excp_idx = EXCP_VSERR; |
107 | /* PMSAv8 */ | 103 | + target_el = 1; |
108 | - env->pmsav8.rbar = g_new0(uint32_t, nr); | 104 | + if (arm_excp_unmasked(cs, excp_idx, target_el, |
109 | - env->pmsav8.rlar = g_new0(uint32_t, nr); | 105 | + cur_el, secure, hcr_el2)) { |
110 | + env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); | 106 | + /* Taking a virtual abort clears HCR_EL2.VSE */ |
111 | + env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); | 107 | + env->cp15.hcr_el2 &= ~HCR_VSE; |
112 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 108 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); |
113 | + env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); | 109 | + goto found; |
114 | + env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); | 110 | + } |
115 | + } | 111 | + } |
116 | } else { | 112 | return false; |
117 | env->pmsav7.drbar = g_new0(uint32_t, nr); | 113 | |
118 | env->pmsav7.drsr = g_new0(uint32_t, nr); | 114 | found: |
115 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu) | ||
116 | } | ||
117 | } | ||
118 | |||
119 | +void arm_cpu_update_vserr(ARMCPU *cpu) | ||
120 | +{ | ||
121 | + /* | ||
122 | + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. | ||
123 | + */ | ||
124 | + CPUARMState *env = &cpu->env; | ||
125 | + CPUState *cs = CPU(cpu); | ||
126 | + | ||
127 | + bool new_state = env->cp15.hcr_el2 & HCR_VSE; | ||
128 | + | ||
129 | + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { | ||
130 | + if (new_state) { | ||
131 | + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
132 | + } else { | ||
133 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | ||
134 | + } | ||
135 | + } | ||
136 | +} | ||
137 | + | ||
138 | #ifndef CONFIG_USER_ONLY | ||
139 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | ||
140 | { | ||
119 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 141 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
120 | index XXXXXXX..XXXXXXX 100644 | 142 | index XXXXXXX..XXXXXXX 100644 |
121 | --- a/target/arm/helper.c | 143 | --- a/target/arm/helper.c |
122 | +++ b/target/arm/helper.c | 144 | +++ b/target/arm/helper.c |
123 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | 145 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
124 | { | 146 | } |
125 | ARMCPU *cpu = arm_env_get_cpu(env); | 147 | } |
126 | bool is_user = regime_is_user(env, mmu_idx); | 148 | |
127 | + uint32_t secure = regime_is_secure(env, mmu_idx); | 149 | - /* External aborts are not possible in QEMU so A bit is always clear */ |
128 | int n; | 150 | + if (hcr_el2 & HCR_AMO) { |
129 | int matchregion = -1; | 151 | + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { |
130 | bool hit = false; | 152 | + ret |= CPSR_A; |
131 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | 153 | + } |
132 | * with bits [4:0] all zeroes, but the limit address is bits | 154 | + } |
133 | * [31:5] from the register with bits [4:0] all ones. | 155 | + |
134 | */ | 156 | return ret; |
135 | - uint32_t base = env->pmsav8.rbar[n] & ~0x1f; | 157 | } |
136 | - uint32_t limit = env->pmsav8.rlar[n] | 0x1f; | 158 | |
137 | + uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; | 159 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
138 | + uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | 160 | g_assert(qemu_mutex_iothread_locked()); |
139 | 161 | arm_cpu_update_virq(cpu); | |
140 | - if (!(env->pmsav8.rlar[n] & 0x1)) { | 162 | arm_cpu_update_vfiq(cpu); |
141 | + if (!(env->pmsav8.rlar[secure][n] & 0x1)) { | 163 | + arm_cpu_update_vserr(cpu); |
142 | /* Region disabled */ | 164 | } |
143 | continue; | 165 | |
144 | } | 166 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
145 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | 167 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs) |
146 | /* hit using the background region */ | 168 | [EXCP_LSERR] = "v8M LSERR UsageFault", |
147 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | 169 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", |
148 | } else { | 170 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", |
149 | - uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2); | 171 | + [EXCP_VSERR] = "Virtual SERR", |
150 | - uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1); | 172 | }; |
151 | + uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); | 173 | |
152 | + uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | 174 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { |
153 | 175 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) | |
154 | if (m_is_system_region(env, address)) { | 176 | mask = CPSR_A | CPSR_I | CPSR_F; |
155 | /* System space is always execute never */ | 177 | offset = 4; |
156 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 178 | break; |
157 | index XXXXXXX..XXXXXXX 100644 | 179 | + case EXCP_VSERR: |
158 | --- a/target/arm/machine.c | 180 | + { |
159 | +++ b/target/arm/machine.c | 181 | + /* |
160 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = { | 182 | + * Note that this is reported as a data abort, but the DFAR |
161 | .minimum_version_id = 1, | 183 | + * has an UNKNOWN value. Construct the SError syndrome from |
162 | .needed = pmsav8_needed, | 184 | + * AET and ExT fields. |
163 | .fields = (VMStateField[]) { | 185 | + */ |
164 | - VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, | 186 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; |
165 | - vmstate_info_uint32, uint32_t), | 187 | + |
166 | - VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, | 188 | + if (extended_addresses_enabled(env)) { |
167 | - vmstate_info_uint32, uint32_t), | 189 | + env->exception.fsr = arm_fi_to_lfsc(&fi); |
168 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, | 190 | + } else { |
169 | + 0, vmstate_info_uint32, uint32_t), | 191 | + env->exception.fsr = arm_fi_to_sfsc(&fi); |
170 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, | 192 | + } |
171 | + 0, vmstate_info_uint32, uint32_t), | 193 | + env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; |
172 | VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), | 194 | + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
173 | VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), | 195 | + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", |
174 | VMSTATE_END_OF_LIST() | 196 | + env->exception.fsr); |
175 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 197 | + |
176 | VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), | 198 | + new_mode = ARM_CPU_MODE_ABT; |
177 | VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), | 199 | + addr = 0x10; |
178 | VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), | 200 | + mask = CPSR_A | CPSR_I; |
179 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, | 201 | + offset = 8; |
180 | + 0, vmstate_info_uint32, uint32_t), | 202 | + } |
181 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, | 203 | + break; |
182 | + 0, vmstate_info_uint32, uint32_t), | 204 | case EXCP_SMC: |
183 | VMSTATE_END_OF_LIST() | 205 | new_mode = ARM_CPU_MODE_MON; |
184 | } | 206 | addr = 0x08; |
185 | }; | 207 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
208 | case EXCP_VFIQ: | ||
209 | addr += 0x100; | ||
210 | break; | ||
211 | + case EXCP_VSERR: | ||
212 | + addr += 0x180; | ||
213 | + /* Construct the SError syndrome from IDS and ISS fields. */ | ||
214 | + env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | ||
215 | + env->cp15.esr_el[new_el] = env->exception.syndrome; | ||
216 | + break; | ||
217 | default: | ||
218 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | ||
219 | } | ||
186 | -- | 220 | -- |
187 | 2.7.4 | 221 | 2.25.1 |
188 | |||
189 | diff view generated by jsdifflib |
1 | Implement the BXNS v8M instruction, which is like BX but will do a | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | jump-and-switch-to-NonSecure if the branch target address has bit 0 | ||
3 | clear. | ||
4 | 2 | ||
5 | This is the first piece of code which implements "switch to the | 3 | Check for and defer any pending virtual SError. |
6 | other security state", so the commit also includes the code to | ||
7 | switch the stack pointers around, which is the only complicated | ||
8 | part of switching security state. | ||
9 | 4 | ||
10 | BLXNS is more complicated than just "BXNS but set the link register", | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | so we leave it for a separate commit. | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220506180242.216785-17-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/helper.h | 1 + | ||
11 | target/arm/a32.decode | 16 ++++++++------ | ||
12 | target/arm/t32.decode | 18 ++++++++-------- | ||
13 | target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-a64.c | 17 +++++++++++++++ | ||
15 | target/arm/translate.c | 23 ++++++++++++++++++++ | ||
16 | 6 files changed, 103 insertions(+), 15 deletions(-) | ||
12 | 17 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 1503414539-28762-21-git-send-email-peter.maydell@linaro.org | ||
16 | --- | ||
17 | target/arm/cpu.h | 13 +++++++++ | ||
18 | target/arm/helper.h | 2 ++ | ||
19 | target/arm/translate.h | 1 + | ||
20 | target/arm/helper.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ | ||
21 | target/arm/machine.c | 2 ++ | ||
22 | target/arm/translate.c | 42 ++++++++++++++++++++++++++- | ||
23 | 6 files changed, 138 insertions(+), 1 deletion(-) | ||
24 | |||
25 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/cpu.h | ||
28 | +++ b/target/arm/cpu.h | ||
29 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
30 | } cp15; | ||
31 | |||
32 | struct { | ||
33 | + /* M profile has up to 4 stack pointers: | ||
34 | + * a Main Stack Pointer and a Process Stack Pointer for each | ||
35 | + * of the Secure and Non-Secure states. (If the CPU doesn't support | ||
36 | + * the security extension then it has only two SPs.) | ||
37 | + * In QEMU we always store the currently active SP in regs[13], | ||
38 | + * and the non-active SP for the current security state in | ||
39 | + * v7m.other_sp. The stack pointers for the inactive security state | ||
40 | + * are stored in other_ss_msp and other_ss_psp. | ||
41 | + * switch_v7m_security_state() is responsible for rearranging them | ||
42 | + * when we change security state. | ||
43 | + */ | ||
44 | uint32_t other_sp; | ||
45 | + uint32_t other_ss_msp; | ||
46 | + uint32_t other_ss_psp; | ||
47 | uint32_t vecbase[2]; | ||
48 | uint32_t basepri[2]; | ||
49 | uint32_t control[2]; | ||
50 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 18 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
51 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
52 | --- a/target/arm/helper.h | 20 | --- a/target/arm/helper.h |
53 | +++ b/target/arm/helper.h | 21 | +++ b/target/arm/helper.h |
54 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(cpsr_read, i32, env) | 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env) |
55 | DEF_HELPER_3(v7m_msr, void, env, i32, i32) | 23 | DEF_HELPER_1(yield, void, env) |
56 | DEF_HELPER_2(v7m_mrs, i32, env, i32) | 24 | DEF_HELPER_1(pre_hvc, void, env) |
57 | 25 | DEF_HELPER_2(pre_smc, void, env, i32) | |
58 | +DEF_HELPER_2(v7m_bxns, void, env, i32) | 26 | +DEF_HELPER_1(vesb, void, env) |
59 | + | 27 | |
60 | DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) | 28 | DEF_HELPER_3(cpsr_write, void, env, i32, i32) |
61 | DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) | 29 | DEF_HELPER_2(cpsr_write_eret, void, env, i32) |
62 | DEF_HELPER_2(get_cp_reg, i32, env, ptr) | 30 | diff --git a/target/arm/a32.decode b/target/arm/a32.decode |
63 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 31 | index XXXXXXX..XXXXXXX 100644 |
64 | index XXXXXXX..XXXXXXX 100644 | 32 | --- a/target/arm/a32.decode |
65 | --- a/target/arm/translate.h | 33 | +++ b/target/arm/a32.decode |
66 | +++ b/target/arm/translate.h | 34 | @@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn |
67 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 35 | |
68 | int vec_len; | ||
69 | int vec_stride; | ||
70 | bool v7m_handler_mode; | ||
71 | + bool v8m_secure; /* true if v8M and we're in Secure mode */ | ||
72 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI | ||
73 | * so that top level loop can generate correct syndrome information. | ||
74 | */ | ||
75 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/helper.c | ||
78 | +++ b/target/arm/helper.c | ||
79 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
80 | return 0; | ||
81 | } | ||
82 | |||
83 | +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | ||
84 | +{ | ||
85 | + /* translate.c should never generate calls here in user-only mode */ | ||
86 | + g_assert_not_reached(); | ||
87 | +} | ||
88 | + | ||
89 | void switch_mode(CPUARMState *env, int mode) | ||
90 | { | 36 | { |
91 | ARMCPU *cpu = arm_env_get_cpu(env); | 37 | { |
92 | @@ -XXX,XX +XXX,XX @@ static uint32_t v7m_pop(CPUARMState *env) | 38 | - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 |
93 | return val; | 39 | - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 |
94 | } | 40 | - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 |
95 | 41 | + [ | |
96 | +/* Return true if we're using the process stack pointer (not the MSP) */ | 42 | + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 |
97 | +static bool v7m_using_psp(CPUARMState *env) | 43 | + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 |
98 | +{ | 44 | + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 |
99 | + /* Handler mode always uses the main stack; for thread mode | 45 | |
100 | + * the CONTROL.SPSEL bit determines the answer. | 46 | - # TODO: Implement SEV, SEVL; may help SMP performance. |
101 | + * Note that in v7M it is not possible to be in Handler mode with | 47 | - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 |
102 | + * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. | 48 | - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 |
103 | + */ | 49 | + # TODO: Implement SEV, SEVL; may help SMP performance. |
104 | + return !arm_v7m_is_handler_mode(env) && | 50 | + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 |
105 | + env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; | 51 | + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 |
106 | +} | 52 | + |
107 | + | 53 | + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 |
108 | /* Switch to V7M main or process stack pointer. */ | 54 | + ] |
109 | static void switch_v7m_sp(CPUARMState *env, bool new_spsel) | 55 | |
110 | { | 56 | # The canonical nop ends in 00000000, but the whole of the |
111 | @@ -XXX,XX +XXX,XX @@ static void switch_v7m_sp(CPUARMState *env, bool new_spsel) | 57 | # rest of the space executes as nop if otherwise unsupported. |
58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/t32.decode | ||
61 | +++ b/target/arm/t32.decode | ||
62 | @@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm | ||
63 | [ | ||
64 | # Hints, and CPS | ||
65 | { | ||
66 | - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | ||
67 | - WFE 1111 0011 1010 1111 1000 0000 0000 0010 | ||
68 | - WFI 1111 0011 1010 1111 1000 0000 0000 0011 | ||
69 | + [ | ||
70 | + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 | ||
71 | + WFE 1111 0011 1010 1111 1000 0000 0000 0010 | ||
72 | + WFI 1111 0011 1010 1111 1000 0000 0000 0011 | ||
73 | |||
74 | - # TODO: Implement SEV, SEVL; may help SMP performance. | ||
75 | - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
76 | - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
77 | + # TODO: Implement SEV, SEVL; may help SMP performance. | ||
78 | + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
79 | + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
80 | |||
81 | - # For M-profile minimal-RAS ESB can be a NOP, which is the | ||
82 | - # default behaviour since it is in the hint space. | ||
83 | - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
84 | + ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
85 | + ] | ||
86 | |||
87 | # The canonical nop ends in 0000 0000, but the whole rest | ||
88 | # of the space is "reserved hint, behaves as nop". | ||
89 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
90 | index XXXXXXX..XXXXXXX 100644 | ||
91 | --- a/target/arm/op_helper.c | ||
92 | +++ b/target/arm/op_helper.c | ||
93 | @@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, | ||
94 | access_type, mmu_idx, ra); | ||
112 | } | 95 | } |
113 | } | 96 | } |
114 | 97 | + | |
115 | +/* Switch M profile security state between NS and S */ | 98 | +/* |
116 | +static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) | 99 | + * This function corresponds to AArch64.vESBOperation(). |
100 | + * Note that the AArch32 version is not functionally different. | ||
101 | + */ | ||
102 | +void HELPER(vesb)(CPUARMState *env) | ||
117 | +{ | 103 | +{ |
118 | + uint32_t new_ss_msp, new_ss_psp; | 104 | + /* |
119 | + | 105 | + * The EL2Enabled() check is done inside arm_hcr_el2_eff, |
120 | + if (env->v7m.secure == new_secstate) { | 106 | + * and will return HCR_EL2.VSE == 0, so nothing happens. |
121 | + return; | ||
122 | + } | ||
123 | + | ||
124 | + /* All the banked state is accessed by looking at env->v7m.secure | ||
125 | + * except for the stack pointer; rearrange the SP appropriately. | ||
126 | + */ | 107 | + */ |
127 | + new_ss_msp = env->v7m.other_ss_msp; | 108 | + uint64_t hcr = arm_hcr_el2_eff(env); |
128 | + new_ss_psp = env->v7m.other_ss_psp; | 109 | + bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO); |
129 | + | 110 | + bool pending = enabled && (hcr & HCR_VSE); |
130 | + if (v7m_using_psp(env)) { | 111 | + bool masked = (env->daif & PSTATE_A); |
131 | + env->v7m.other_ss_psp = env->regs[13]; | 112 | + |
132 | + env->v7m.other_ss_msp = env->v7m.other_sp; | 113 | + /* If VSE pending and masked, defer the exception. */ |
133 | + } else { | 114 | + if (pending && masked) { |
134 | + env->v7m.other_ss_msp = env->regs[13]; | 115 | + uint32_t syndrome; |
135 | + env->v7m.other_ss_psp = env->v7m.other_sp; | 116 | + |
136 | + } | 117 | + if (arm_el_is_aa64(env, 1)) { |
137 | + | 118 | + /* Copy across IDS and ISS from VSESR. */ |
138 | + env->v7m.secure = new_secstate; | 119 | + syndrome = env->cp15.vsesr_el2 & 0x1ffffff; |
139 | + | 120 | + } else { |
140 | + if (v7m_using_psp(env)) { | 121 | + ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal }; |
141 | + env->regs[13] = new_ss_psp; | 122 | + |
142 | + env->v7m.other_sp = new_ss_msp; | 123 | + if (extended_addresses_enabled(env)) { |
143 | + } else { | 124 | + syndrome = arm_fi_to_lfsc(&fi); |
144 | + env->regs[13] = new_ss_msp; | 125 | + } else { |
145 | + env->v7m.other_sp = new_ss_psp; | 126 | + syndrome = arm_fi_to_sfsc(&fi); |
127 | + } | ||
128 | + /* Copy across AET and ExT from VSESR. */ | ||
129 | + syndrome |= env->cp15.vsesr_el2 & 0xd000; | ||
130 | + } | ||
131 | + | ||
132 | + /* Set VDISR_EL2.A along with the syndrome. */ | ||
133 | + env->cp15.vdisr_el2 = syndrome | (1u << 31); | ||
134 | + | ||
135 | + /* Clear pending virtual SError */ | ||
136 | + env->cp15.hcr_el2 &= ~HCR_VSE; | ||
137 | + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); | ||
146 | + } | 138 | + } |
147 | +} | 139 | +} |
148 | + | 140 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
149 | +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | 141 | index XXXXXXX..XXXXXXX 100644 |
150 | +{ | 142 | --- a/target/arm/translate-a64.c |
151 | + /* Handle v7M BXNS: | 143 | +++ b/target/arm/translate-a64.c |
152 | + * - if the return value is a magic value, do exception return (like BX) | 144 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, |
153 | + * - otherwise bit 0 of the return value is the target security state | 145 | gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); |
154 | + */ | 146 | } |
155 | + if (dest >= 0xff000000) { | 147 | break; |
156 | + /* This is an exception return magic value; put it where | 148 | + case 0b10000: /* ESB */ |
157 | + * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. | 149 | + /* Without RAS, we must implement this as NOP. */ |
158 | + * Note that if we ever add gen_ss_advance() singlestep support to | 150 | + if (dc_isar_feature(aa64_ras, s)) { |
159 | + * M profile this should count as an "instruction execution complete" | 151 | + /* |
160 | + * event (compare gen_bx_excret_final_code()). | 152 | + * QEMU does not have a source of physical SErrors, |
161 | + */ | 153 | + * so we are only concerned with virtual SErrors. |
162 | + env->regs[15] = dest & ~1; | 154 | + * The pseudocode in the ARM for this case is |
163 | + env->thumb = dest & 1; | 155 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then |
164 | + HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); | 156 | + * AArch64.vESBOperation(); |
165 | + /* notreached */ | 157 | + * Most of the condition can be evaluated at translation time. |
166 | + } | 158 | + * Test for EL2 present, and defer test for SEL2 to runtime. |
167 | + | 159 | + */ |
168 | + /* translate.c should have made BXNS UNDEF unless we're secure */ | 160 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { |
169 | + assert(env->v7m.secure); | 161 | + gen_helper_vesb(cpu_env); |
170 | + | 162 | + } |
171 | + switch_v7m_security_state(env, dest & 1); | 163 | + } |
172 | + env->thumb = 1; | 164 | + break; |
173 | + env->regs[15] = dest & ~1; | 165 | case 0b11000: /* PACIAZ */ |
174 | +} | 166 | if (s->pauth_active) { |
175 | + | 167 | gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], |
176 | static uint32_t arm_v7m_load_vector(ARMCPU *cpu) | ||
177 | { | ||
178 | CPUState *cs = CPU(cpu); | ||
179 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
180 | index XXXXXXX..XXXXXXX 100644 | ||
181 | --- a/target/arm/machine.c | ||
182 | +++ b/target/arm/machine.c | ||
183 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
184 | .needed = m_security_needed, | ||
185 | .fields = (VMStateField[]) { | ||
186 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), | ||
187 | + VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), | ||
188 | + VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), | ||
189 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | ||
190 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | ||
191 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | ||
192 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 168 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
193 | index XXXXXXX..XXXXXXX 100644 | 169 | index XXXXXXX..XXXXXXX 100644 |
194 | --- a/target/arm/translate.c | 170 | --- a/target/arm/translate.c |
195 | +++ b/target/arm/translate.c | 171 | +++ b/target/arm/translate.c |
196 | @@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s) | 172 | @@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) |
197 | gen_exception_internal(EXCP_EXCEPTION_EXIT); | 173 | return true; |
198 | } | 174 | } |
199 | 175 | ||
200 | +static inline void gen_bxns(DisasContext *s, int rm) | 176 | +static bool trans_ESB(DisasContext *s, arg_ESB *a) |
201 | +{ | 177 | +{ |
202 | + TCGv_i32 var = load_reg(s, rm); | 178 | + /* |
203 | + | 179 | + * For M-profile, minimal-RAS ESB can be a NOP. |
204 | + /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory | 180 | + * Without RAS, we must implement this as NOP. |
205 | + * we need to sync state before calling it, but: | ||
206 | + * - we don't need to do gen_set_pc_im() because the bxns helper will | ||
207 | + * always set the PC itself | ||
208 | + * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE | ||
209 | + * unless it's outside an IT block or the last insn in an IT block, | ||
210 | + * so we know that condexec == 0 (already set at the top of the TB) | ||
211 | + * is correct in the non-UNPREDICTABLE cases, and we can choose | ||
212 | + * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise. | ||
213 | + */ | 181 | + */ |
214 | + gen_helper_v7m_bxns(cpu_env, var); | 182 | + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) { |
215 | + tcg_temp_free_i32(var); | 183 | + /* |
216 | + s->is_jmp = DISAS_EXIT; | 184 | + * QEMU does not have a source of physical SErrors, |
185 | + * so we are only concerned with virtual SErrors. | ||
186 | + * The pseudocode in the ARM for this case is | ||
187 | + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then | ||
188 | + * AArch32.vESBOperation(); | ||
189 | + * Most of the condition can be evaluated at translation time. | ||
190 | + * Test for EL2 present, and defer test for SEL2 to runtime. | ||
191 | + */ | ||
192 | + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { | ||
193 | + gen_helper_vesb(cpu_env); | ||
194 | + } | ||
195 | + } | ||
196 | + return true; | ||
217 | +} | 197 | +} |
218 | + | 198 | + |
219 | /* Variant of store_reg which uses branch&exchange logic when storing | 199 | static bool trans_NOP(DisasContext *s, arg_NOP *a) |
220 | to r15 in ARM architecture v7 and above. The source must be a temporary | 200 | { |
221 | and will be marked as dead. */ | 201 | return true; |
222 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
223 | */ | ||
224 | bool link = insn & (1 << 7); | ||
225 | |||
226 | - if (insn & 7) { | ||
227 | + if (insn & 3) { | ||
228 | goto undef; | ||
229 | } | ||
230 | if (link) { | ||
231 | ARCH(5); | ||
232 | } | ||
233 | + if ((insn & 4)) { | ||
234 | + /* BXNS/BLXNS: only exists for v8M with the | ||
235 | + * security extensions, and always UNDEF if NonSecure. | ||
236 | + * We don't implement these in the user-only mode | ||
237 | + * either (in theory you can use them from Secure User | ||
238 | + * mode but they are too tied in to system emulation.) | ||
239 | + */ | ||
240 | + if (!s->v8m_secure || IS_USER_ONLY) { | ||
241 | + goto undef; | ||
242 | + } | ||
243 | + if (link) { | ||
244 | + /* BLXNS: not yet implemented */ | ||
245 | + goto undef; | ||
246 | + } else { | ||
247 | + gen_bxns(s, rm); | ||
248 | + } | ||
249 | + break; | ||
250 | + } | ||
251 | + /* BLX/BX */ | ||
252 | tmp = load_reg(s, rm); | ||
253 | if (link) { | ||
254 | val = (uint32_t)s->pc | 1; | ||
255 | @@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) | ||
256 | dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); | ||
257 | dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags); | ||
258 | dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags); | ||
259 | + dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && | ||
260 | + regime_is_secure(env, dc->mmu_idx); | ||
261 | dc->cp_regs = cpu->cp_regs; | ||
262 | dc->features = env->features; | ||
263 | |||
264 | -- | 202 | -- |
265 | 2.7.4 | 203 | 2.25.1 |
266 | |||
267 | diff view generated by jsdifflib |
1 | Make the MMFAR register banked if v8M security extensions are | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | enabled. | ||
3 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20220506180242.216785-18-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org | ||
7 | --- | 7 | --- |
8 | target/arm/cpu.h | 2 +- | 8 | docs/system/arm/emulation.rst | 1 + |
9 | hw/intc/armv7m_nvic.c | 4 ++-- | 9 | target/arm/cpu64.c | 1 + |
10 | target/arm/helper.c | 4 ++-- | 10 | target/arm/cpu_tcg.c | 1 + |
11 | target/arm/machine.c | 3 ++- | 11 | 3 files changed, 3 insertions(+) |
12 | 4 files changed, 7 insertions(+), 6 deletions(-) | ||
13 | 12 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 15 | --- a/docs/system/arm/emulation.rst |
17 | +++ b/target/arm/cpu.h | 16 | +++ b/docs/system/arm/emulation.rst |
18 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 17 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
19 | uint32_t cfsr; /* Configurable Fault Status */ | 18 | - FEAT_PMULL (PMULL, PMULL2 instructions) |
20 | uint32_t hfsr; /* HardFault Status */ | 19 | - FEAT_PMUv3p1 (PMU Extensions v3.1) |
21 | uint32_t dfsr; /* Debug Fault Status Register */ | 20 | - FEAT_PMUv3p4 (PMU Extensions v3.4) |
22 | - uint32_t mmfar; /* MemManage Fault Address */ | 21 | +- FEAT_RAS (Reliability, availability, and serviceability) |
23 | + uint32_t mmfar[2]; /* MemManage Fault Address */ | 22 | - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) |
24 | uint32_t bfar; /* BusFault Address */ | 23 | - FEAT_RNG (Random number generator) |
25 | unsigned mpu_ctrl[2]; /* MPU_CTRL */ | 24 | - FEAT_SB (Speculation Barrier) |
26 | int exception; | 25 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
27 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/hw/intc/armv7m_nvic.c | 27 | --- a/target/arm/cpu64.c |
30 | +++ b/hw/intc/armv7m_nvic.c | 28 | +++ b/target/arm/cpu64.c |
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 29 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
32 | case 0xd30: /* Debug Fault Status. */ | 30 | t = cpu->isar.id_aa64pfr0; |
33 | return cpu->env.v7m.dfsr; | 31 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ |
34 | case 0xd34: /* MMFAR MemManage Fault Address */ | 32 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ |
35 | - return cpu->env.v7m.mmfar; | 33 | + t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ |
36 | + return cpu->env.v7m.mmfar[attrs.secure]; | 34 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); |
37 | case 0xd38: /* Bus Fault Address. */ | 35 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ |
38 | return cpu->env.v7m.bfar; | 36 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ |
39 | case 0xd3c: /* Aux Fault Status. */ | 37 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c |
40 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
41 | cpu->env.v7m.dfsr &= ~value; /* W1C */ | ||
42 | break; | ||
43 | case 0xd34: /* Mem Manage Address. */ | ||
44 | - cpu->env.v7m.mmfar = value; | ||
45 | + cpu->env.v7m.mmfar[attrs.secure] = value; | ||
46 | return; | ||
47 | case 0xd38: /* Bus Fault Address. */ | ||
48 | cpu->env.v7m.bfar = value; | ||
49 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/target/arm/helper.c | 39 | --- a/target/arm/cpu_tcg.c |
52 | +++ b/target/arm/helper.c | 40 | +++ b/target/arm/cpu_tcg.c |
53 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 41 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
54 | case EXCP_DATA_ABORT: | 42 | |
55 | env->v7m.cfsr |= | 43 | t = cpu->isar.id_pfr0; |
56 | (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); | 44 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ |
57 | - env->v7m.mmfar = env->exception.vaddress; | 45 | + t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ |
58 | + env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; | 46 | cpu->isar.id_pfr0 = t; |
59 | qemu_log_mask(CPU_LOG_INT, | 47 | |
60 | "...with CFSR.DACCVIOL and MMFAR 0x%x\n", | 48 | t = cpu->isar.id_pfr2; |
61 | - env->v7m.mmfar); | ||
62 | + env->v7m.mmfar[env->v7m.secure]); | ||
63 | break; | ||
64 | } | ||
65 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); | ||
66 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/machine.c | ||
69 | +++ b/target/arm/machine.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
71 | VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | ||
72 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), | ||
73 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), | ||
74 | - VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), | ||
75 | + VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), | ||
76 | VMSTATE_UINT32(env.v7m.bfar, ARMCPU), | ||
77 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), | ||
78 | VMSTATE_INT32(env.v7m.exception, ARMCPU), | ||
79 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
80 | VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), | ||
81 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), | ||
82 | VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), | ||
83 | + VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), | ||
84 | VMSTATE_END_OF_LIST() | ||
85 | } | ||
86 | }; | ||
87 | -- | 49 | -- |
88 | 2.7.4 | 50 | 2.25.1 |
89 | |||
90 | diff view generated by jsdifflib |
1 | Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | extensions are enabled. | ||
3 | 2 | ||
3 | This feature is AArch64 only, and applies to physical SErrors, | ||
4 | which QEMU does not implement, thus the feature is a nop. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-19-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 1503414539-28762-13-git-send-email-peter.maydell@linaro.org | ||
7 | --- | 10 | --- |
8 | target/arm/cpu.h | 4 ++-- | 11 | docs/system/arm/emulation.rst | 1 + |
9 | hw/intc/armv7m_nvic.c | 8 ++++---- | 12 | target/arm/cpu64.c | 1 + |
10 | target/arm/cpu.c | 6 ++++-- | 13 | 2 files changed, 2 insertions(+) |
11 | target/arm/machine.c | 6 ++++-- | ||
12 | 4 files changed, 14 insertions(+), 10 deletions(-) | ||
13 | 14 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 17 | --- a/docs/system/arm/emulation.rst |
17 | +++ b/target/arm/cpu.h | 18 | +++ b/docs/system/arm/emulation.rst |
18 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 19 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
19 | */ | 20 | - FEAT_FlagM2 (Enhancements to flag manipulation instructions) |
20 | uint32_t *rbar; | 21 | - FEAT_HPDS (Hierarchical permission disables) |
21 | uint32_t *rlar; | 22 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) |
22 | - uint32_t mair0; | 23 | +- FEAT_IESB (Implicit error synchronization event) |
23 | - uint32_t mair1; | 24 | - FEAT_JSCVT (JavaScript conversion instructions) |
24 | + uint32_t mair0[2]; | 25 | - FEAT_LOR (Limited ordering regions) |
25 | + uint32_t mair1[2]; | 26 | - FEAT_LPA (Large Physical Address space) |
26 | } pmsav8; | 27 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
27 | |||
28 | void *nvic; | ||
29 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/hw/intc/armv7m_nvic.c | 29 | --- a/target/arm/cpu64.c |
32 | +++ b/hw/intc/armv7m_nvic.c | 30 | +++ b/target/arm/cpu64.c |
33 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
34 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | 32 | t = cpu->isar.id_aa64mmfr2; |
35 | goto bad_offset; | 33 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ |
36 | } | 34 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ |
37 | - return cpu->env.pmsav8.mair0; | 35 | + t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ |
38 | + return cpu->env.pmsav8.mair0[attrs.secure]; | 36 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ |
39 | case 0xdc4: /* MPU_MAIR1 */ | 37 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ |
40 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | 38 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ |
41 | goto bad_offset; | ||
42 | } | ||
43 | - return cpu->env.pmsav8.mair1; | ||
44 | + return cpu->env.pmsav8.mair1[attrs.secure]; | ||
45 | default: | ||
46 | bad_offset: | ||
47 | qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); | ||
48 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
49 | } | ||
50 | if (cpu->pmsav7_dregion) { | ||
51 | /* Register is RES0 if no MPU regions are implemented */ | ||
52 | - cpu->env.pmsav8.mair0 = value; | ||
53 | + cpu->env.pmsav8.mair0[attrs.secure] = value; | ||
54 | } | ||
55 | /* We don't need to do anything else because memory attributes | ||
56 | * only affect cacheability, and we don't implement caching. | ||
57 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
58 | } | ||
59 | if (cpu->pmsav7_dregion) { | ||
60 | /* Register is RES0 if no MPU regions are implemented */ | ||
61 | - cpu->env.pmsav8.mair1 = value; | ||
62 | + cpu->env.pmsav8.mair1[attrs.secure] = value; | ||
63 | } | ||
64 | /* We don't need to do anything else because memory attributes | ||
65 | * only affect cacheability, and we don't implement caching. | ||
66 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/cpu.c | ||
69 | +++ b/target/arm/cpu.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
71 | } | ||
72 | } | ||
73 | env->pmsav7.rnr = 0; | ||
74 | - env->pmsav8.mair0 = 0; | ||
75 | - env->pmsav8.mair1 = 0; | ||
76 | + env->pmsav8.mair0[M_REG_NS] = 0; | ||
77 | + env->pmsav8.mair0[M_REG_S] = 0; | ||
78 | + env->pmsav8.mair1[M_REG_NS] = 0; | ||
79 | + env->pmsav8.mair1[M_REG_S] = 0; | ||
80 | } | ||
81 | |||
82 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | ||
83 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/target/arm/machine.c | ||
86 | +++ b/target/arm/machine.c | ||
87 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = { | ||
88 | vmstate_info_uint32, uint32_t), | ||
89 | VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, | ||
90 | vmstate_info_uint32, uint32_t), | ||
91 | - VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), | ||
92 | - VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), | ||
93 | + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), | ||
94 | + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), | ||
95 | VMSTATE_END_OF_LIST() | ||
96 | } | ||
97 | }; | ||
98 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
99 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | ||
100 | VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), | ||
101 | VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), | ||
102 | + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), | ||
103 | + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), | ||
104 | VMSTATE_END_OF_LIST() | ||
105 | } | ||
106 | }; | ||
107 | -- | 39 | -- |
108 | 2.7.4 | 40 | 2.25.1 |
109 | |||
110 | diff view generated by jsdifflib |
1 | Make the PRIMASK register banked if v8M security extensions are enabled. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Note that we do not yet implement the functionality of the new | 3 | This extension concerns branch speculation, which TCG does |
4 | AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to | 4 | not implement. Thus we can trivially enable this feature. |
5 | be restricted). | ||
6 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-20-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 1503414539-28762-8-git-send-email-peter.maydell@linaro.org | ||
10 | --- | 10 | --- |
11 | target/arm/cpu.h | 2 +- | 11 | docs/system/arm/emulation.rst | 1 + |
12 | hw/intc/armv7m_nvic.c | 2 +- | 12 | target/arm/cpu64.c | 1 + |
13 | target/arm/helper.c | 4 ++-- | 13 | target/arm/cpu_tcg.c | 1 + |
14 | target/arm/machine.c | 9 +++++++-- | 14 | 3 files changed, 3 insertions(+) |
15 | 4 files changed, 11 insertions(+), 6 deletions(-) | ||
16 | 15 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 18 | --- a/docs/system/arm/emulation.rst |
20 | +++ b/target/arm/cpu.h | 19 | +++ b/docs/system/arm/emulation.rst |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
22 | uint32_t bfar; /* BusFault Address */ | 21 | - FEAT_BBM at level 2 (Translation table break-before-make levels) |
23 | unsigned mpu_ctrl; /* MPU_CTRL */ | 22 | - FEAT_BF16 (AArch64 BFloat16 instructions) |
24 | int exception; | 23 | - FEAT_BTI (Branch Target Identification) |
25 | - uint32_t primask; | 24 | +- FEAT_CSV2 (Cache speculation variant 2) |
26 | + uint32_t primask[2]; | 25 | - FEAT_DIT (Data Independent Timing instructions) |
27 | uint32_t faultmask; | 26 | - FEAT_DPB (DC CVAP instruction) |
28 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | 27 | - FEAT_Debugv8p2 (Debug changes for v8.2) |
29 | } v7m; | 28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
30 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/intc/armv7m_nvic.c | 30 | --- a/target/arm/cpu64.c |
33 | +++ b/hw/intc/armv7m_nvic.c | 31 | +++ b/target/arm/cpu64.c |
34 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | 32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
35 | 33 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | |
36 | if (env->v7m.faultmask) { | 34 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ |
37 | running = -1; | 35 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ |
38 | - } else if (env->v7m.primask) { | 36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ |
39 | + } else if (env->v7m.primask[env->v7m.secure]) { | 37 | cpu->isar.id_aa64pfr0 = t; |
40 | running = 0; | 38 | |
41 | } else if (env->v7m.basepri[env->v7m.secure] > 0) { | 39 | t = cpu->isar.id_aa64pfr1; |
42 | running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); | 40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c |
43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
45 | --- a/target/arm/helper.c | 42 | --- a/target/arm/cpu_tcg.c |
46 | +++ b/target/arm/helper.c | 43 | +++ b/target/arm/cpu_tcg.c |
47 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
48 | return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? | 45 | cpu->isar.id_mmfr4 = t; |
49 | env->regs[13] : env->v7m.other_sp; | 46 | |
50 | case 16: /* PRIMASK */ | 47 | t = cpu->isar.id_pfr0; |
51 | - return env->v7m.primask; | 48 | + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ |
52 | + return env->v7m.primask[env->v7m.secure]; | 49 | t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ |
53 | case 17: /* BASEPRI */ | 50 | t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ |
54 | case 18: /* BASEPRI_MAX */ | 51 | cpu->isar.id_pfr0 = t; |
55 | return env->v7m.basepri[env->v7m.secure]; | ||
56 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
57 | } | ||
58 | break; | ||
59 | case 16: /* PRIMASK */ | ||
60 | - env->v7m.primask = val & 1; | ||
61 | + env->v7m.primask[env->v7m.secure] = val & 1; | ||
62 | break; | ||
63 | case 17: /* BASEPRI */ | ||
64 | env->v7m.basepri[env->v7m.secure] = val & 0xff; | ||
65 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/machine.c | ||
68 | +++ b/target/arm/machine.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = { | ||
70 | .minimum_version_id = 1, | ||
71 | .fields = (VMStateField[]) { | ||
72 | VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), | ||
73 | - VMSTATE_UINT32(env.v7m.primask, ARMCPU), | ||
74 | + VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), | ||
75 | VMSTATE_END_OF_LIST() | ||
76 | } | ||
77 | }; | ||
78 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
79 | .fields = (VMStateField[]) { | ||
80 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), | ||
81 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | ||
82 | + VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | ||
83 | VMSTATE_END_OF_LIST() | ||
84 | } | ||
85 | }; | ||
86 | @@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | ||
87 | * differences are that the T bit is not in the same place, the | ||
88 | * primask/faultmask info may be in the CPSR I and F bits, and | ||
89 | * we do not want the mode bits. | ||
90 | + * We know that this cleanup happened before v8M, so there | ||
91 | + * is no complication with banked primask/faultmask. | ||
92 | */ | ||
93 | uint32_t newval = val; | ||
94 | |||
95 | + assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); | ||
96 | + | ||
97 | newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); | ||
98 | if (val & CPSR_T) { | ||
99 | newval |= XPSR_T; | ||
100 | @@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | ||
101 | env->v7m.faultmask = 1; | ||
102 | } | ||
103 | if (val & CPSR_I) { | ||
104 | - env->v7m.primask = 1; | ||
105 | + env->v7m.primask[M_REG_NS] = 1; | ||
106 | } | ||
107 | val = newval; | ||
108 | } | ||
109 | -- | 52 | -- |
110 | 2.7.4 | 53 | 2.25.1 |
111 | |||
112 | diff view generated by jsdifflib |
1 | Make the CCR register banked if v8M security extensions are enabled. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This is slightly more complicated than the other "add banking" | 3 | There is no branch prediction in TCG, therefore there is no |
4 | patches because there is one bit in the register which is not | 4 | need to actually include the context number into the predictor. |
5 | banked. We keep the live data in the NS copy of the register, | 5 | Therefore all we need to do is add the state for SCXTNUM_ELx. |
6 | and adjust it on register reads and writes. (Since we don't | ||
7 | currently implement the behaviour that the bit controls, there | ||
8 | is nowhere else that needs to care.) | ||
9 | 6 | ||
10 | This patch includes the enforcement of the bits which are newly | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | RES1 in ARMv8M. | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220506180242.216785-21-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | docs/system/arm/emulation.rst | 3 ++ | ||
13 | target/arm/cpu.h | 16 +++++++++ | ||
14 | target/arm/cpu.c | 5 +++ | ||
15 | target/arm/cpu64.c | 3 +- | ||
16 | target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- | ||
17 | 5 files changed, 86 insertions(+), 2 deletions(-) | ||
12 | 18 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
14 | Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org | 20 | index XXXXXXX..XXXXXXX 100644 |
15 | --- | 21 | --- a/docs/system/arm/emulation.rst |
16 | target/arm/cpu.h | 2 +- | 22 | +++ b/docs/system/arm/emulation.rst |
17 | hw/intc/armv7m_nvic.c | 33 +++++++++++++++++++++++++++------ | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
18 | target/arm/cpu.c | 12 +++++++++--- | 24 | - FEAT_BF16 (AArch64 BFloat16 instructions) |
19 | target/arm/helper.c | 5 +++-- | 25 | - FEAT_BTI (Branch Target Identification) |
20 | target/arm/machine.c | 3 ++- | 26 | - FEAT_CSV2 (Cache speculation variant 2) |
21 | 5 files changed, 42 insertions(+), 13 deletions(-) | 27 | +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) |
22 | 28 | +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | |
29 | +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) | ||
30 | - FEAT_DIT (Data Independent Timing instructions) | ||
31 | - FEAT_DPB (DC CVAP instruction) | ||
32 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
23 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 33 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
24 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/cpu.h | 35 | --- a/target/arm/cpu.h |
26 | +++ b/target/arm/cpu.h | 36 | +++ b/target/arm/cpu.h |
27 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 37 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
28 | uint32_t vecbase[2]; | 38 | ARMPACKey apdb; |
29 | uint32_t basepri[2]; | 39 | ARMPACKey apga; |
30 | uint32_t control[2]; | 40 | } keys; |
31 | - uint32_t ccr; /* Configuration and Control */ | 41 | + |
32 | + uint32_t ccr[2]; /* Configuration and Control */ | 42 | + uint64_t scxtnum_el[4]; |
33 | uint32_t cfsr; /* Configurable Fault Status */ | 43 | #endif |
34 | uint32_t hfsr; /* HardFault Status */ | 44 | |
35 | uint32_t dfsr; /* Debug Fault Status Register */ | 45 | #if defined(CONFIG_USER_ONLY) |
36 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 46 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); |
37 | index XXXXXXX..XXXXXXX 100644 | 47 | #define SCTLR_WXN (1U << 19) |
38 | --- a/hw/intc/armv7m_nvic.c | 48 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ |
39 | +++ b/hw/intc/armv7m_nvic.c | 49 | #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ |
40 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 50 | +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ |
41 | /* TODO: Implement SLEEPONEXIT. */ | 51 | #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ |
42 | return 0; | 52 | #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ |
43 | case 0xd14: /* Configuration Control. */ | 53 | #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ |
44 | - return cpu->env.v7m.ccr; | 54 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) |
45 | + /* The BFHFNMIGN bit is the only non-banked bit; we | 55 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; |
46 | + * keep it in the non-secure copy of the register. | ||
47 | + */ | ||
48 | + val = cpu->env.v7m.ccr[attrs.secure]; | ||
49 | + val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; | ||
50 | + return val; | ||
51 | case 0xd24: /* System Handler Status. */ | ||
52 | val = 0; | ||
53 | if (s->vectors[ARMV7M_EXCP_MEM].active) { | ||
54 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
55 | R_V7M_CCR_USERSETMPEND_MASK | | ||
56 | R_V7M_CCR_NONBASETHRDENA_MASK); | ||
57 | |||
58 | - cpu->env.v7m.ccr = value; | ||
59 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
60 | + /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ | ||
61 | + value |= R_V7M_CCR_NONBASETHRDENA_MASK | ||
62 | + | R_V7M_CCR_STKALIGN_MASK; | ||
63 | + } | ||
64 | + if (attrs.secure) { | ||
65 | + /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ | ||
66 | + cpu->env.v7m.ccr[M_REG_NS] = | ||
67 | + (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) | ||
68 | + | (value & R_V7M_CCR_BFHFNMIGN_MASK); | ||
69 | + value &= ~R_V7M_CCR_BFHFNMIGN_MASK; | ||
70 | + } | ||
71 | + | ||
72 | + cpu->env.v7m.ccr[attrs.secure] = value; | ||
73 | break; | ||
74 | case 0xd24: /* System Handler Control. */ | ||
75 | s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; | ||
76 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
77 | } | ||
78 | } | 56 | } |
79 | 57 | ||
80 | -static bool nvic_user_access_ok(NVICState *s, hwaddr offset) | 58 | +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) |
81 | +static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs) | 59 | +{ |
60 | + int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); | ||
61 | + if (key >= 2) { | ||
62 | + return true; /* FEAT_CSV2_2 */ | ||
63 | + } | ||
64 | + if (key == 1) { | ||
65 | + key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); | ||
66 | + return key >= 2; /* FEAT_CSV2_1p2 */ | ||
67 | + } | ||
68 | + return false; | ||
69 | +} | ||
70 | + | ||
71 | static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) | ||
82 | { | 72 | { |
83 | /* Return true if unprivileged access to this register is permitted. */ | 73 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; |
84 | switch (offset) { | ||
85 | case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ | ||
86 | - return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK; | ||
87 | + /* For access via STIR_NS it is the NS CCR.USERSETMPEND that | ||
88 | + * controls access even though the CPU is in Secure state (I_QDKX). | ||
89 | + */ | ||
90 | + return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; | ||
91 | default: | ||
92 | /* All other user accesses cause a BusFault unconditionally */ | ||
93 | return false; | ||
94 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, | ||
95 | unsigned i, startvec, end; | ||
96 | uint32_t val; | ||
97 | |||
98 | - if (attrs.user && !nvic_user_access_ok(s, addr)) { | ||
99 | + if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { | ||
100 | /* Generate BusFault for unprivileged accesses */ | ||
101 | return MEMTX_ERROR; | ||
102 | } | ||
103 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, | ||
104 | |||
105 | trace_nvic_sysreg_write(addr, value, size); | ||
106 | |||
107 | - if (attrs.user && !nvic_user_access_ok(s, addr)) { | ||
108 | + if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { | ||
109 | /* Generate BusFault for unprivileged accesses */ | ||
110 | return MEMTX_ERROR; | ||
111 | } | ||
112 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 74 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
113 | index XXXXXXX..XXXXXXX 100644 | 75 | index XXXXXXX..XXXXXXX 100644 |
114 | --- a/target/arm/cpu.c | 76 | --- a/target/arm/cpu.c |
115 | +++ b/target/arm/cpu.c | 77 | +++ b/target/arm/cpu.c |
116 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 78 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
117 | env->v7m.secure = true; | 79 | */ |
80 | env->cp15.gcr_el1 = 0x1ffff; | ||
118 | } | 81 | } |
119 | 82 | + /* | |
120 | - /* The reset value of this bit is IMPDEF, but ARM recommends | 83 | + * Disable access to SCXTNUM_EL0 from CSV2_1p2. |
121 | + /* In v7M the reset value of this bit is IMPDEF, but ARM recommends | 84 | + * This is not yet exposed from the Linux kernel in any way. |
122 | * that it resets to 1, so QEMU always does that rather than making | 85 | + */ |
123 | - * it dependent on CPU model. | 86 | + env->cp15.sctlr_el[1] |= SCTLR_TSCXT; |
124 | + * it dependent on CPU model. In v8M it is RES1. | 87 | #else |
125 | */ | 88 | /* Reset into the highest available EL */ |
126 | - env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; | 89 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
127 | + env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; | 90 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
128 | + env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; | 91 | index XXXXXXX..XXXXXXX 100644 |
129 | + if (arm_feature(env, ARM_FEATURE_V8)) { | 92 | --- a/target/arm/cpu64.c |
130 | + /* in v8M the NONBASETHRDENA bit [0] is RES1 */ | 93 | +++ b/target/arm/cpu64.c |
131 | + env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; | 94 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
132 | + env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; | 95 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); |
133 | + } | 96 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ |
134 | 97 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | |
135 | /* Unlike A/R profile, M profile defines the reset LR value */ | 98 | - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ |
136 | env->regs[14] = 0xffffffff; | 99 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ |
100 | cpu->isar.id_aa64pfr0 = t; | ||
101 | |||
102 | t = cpu->isar.id_aa64pfr1; | ||
103 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
104 | * we do for EL2 with the virtualization=on property. | ||
105 | */ | ||
106 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
107 | + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ | ||
108 | cpu->isar.id_aa64pfr1 = t; | ||
109 | |||
110 | t = cpu->isar.id_aa64mmfr0; | ||
137 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 111 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
138 | index XXXXXXX..XXXXXXX 100644 | 112 | index XXXXXXX..XXXXXXX 100644 |
139 | --- a/target/arm/helper.c | 113 | --- a/target/arm/helper.c |
140 | +++ b/target/arm/helper.c | 114 | +++ b/target/arm/helper.c |
141 | @@ -XXX,XX +XXX,XX @@ static void v7m_push_stack(ARMCPU *cpu) | 115 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
142 | uint32_t xpsr = xpsr_read(env); | 116 | if (cpu_isar_feature(aa64_mte, cpu)) { |
143 | 117 | valid_mask |= SCR_ATA; | |
144 | /* Align stack pointer if the guest wants that */ | 118 | } |
145 | - if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { | 119 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
146 | + if ((env->regs[13] & 4) && | 120 | + valid_mask |= SCR_ENSCXT; |
147 | + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { | 121 | + } |
148 | env->regs[13] -= 4; | 122 | } else { |
149 | xpsr |= XPSR_SPREALIGN; | 123 | valid_mask &= ~(SCR_RW | SCR_ST); |
124 | if (cpu_isar_feature(aa32_ras, cpu)) { | ||
125 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
126 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
127 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | ||
128 | } | ||
129 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
130 | + valid_mask |= HCR_ENSCXT; | ||
131 | + } | ||
150 | } | 132 | } |
151 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 133 | |
152 | /* fall through */ | 134 | /* Clear RES0 bits. */ |
153 | case 9: /* Return to Thread using Main stack */ | 135 | @@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) |
154 | if (!rettobase && | 136 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), |
155 | - !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) { | 137 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, |
156 | + !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MASK)) { | 138 | |
157 | ufault = true; | 139 | + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), |
158 | } | 140 | + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", |
159 | break; | 141 | + isar_feature_aa64_scxtnum }, |
160 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 142 | + |
161 | index XXXXXXX..XXXXXXX 100644 | 143 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ |
162 | --- a/target/arm/machine.c | 144 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ |
163 | +++ b/target/arm/machine.c | 145 | }; |
164 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 146 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { |
165 | VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), | 147 | }, |
166 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | 148 | }; |
167 | VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), | 149 | |
168 | - VMSTATE_UINT32(env.v7m.ccr, ARMCPU), | 150 | -#endif |
169 | + VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), | 151 | +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, |
170 | VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | 152 | + bool isread) |
171 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), | 153 | +{ |
172 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), | 154 | + uint64_t hcr = arm_hcr_el2_eff(env); |
173 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 155 | + int el = arm_current_el(env); |
174 | VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), | 156 | + |
175 | VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), | 157 | + if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { |
176 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), | 158 | + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { |
177 | + VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), | 159 | + if (hcr & HCR_TGE) { |
178 | VMSTATE_END_OF_LIST() | 160 | + return CP_ACCESS_TRAP_EL2; |
161 | + } | ||
162 | + return CP_ACCESS_TRAP; | ||
163 | + } | ||
164 | + } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | ||
165 | + return CP_ACCESS_TRAP_EL2; | ||
166 | + } | ||
167 | + if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | ||
168 | + return CP_ACCESS_TRAP_EL2; | ||
169 | + } | ||
170 | + if (el < 3 | ||
171 | + && arm_feature(env, ARM_FEATURE_EL3) | ||
172 | + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | ||
173 | + return CP_ACCESS_TRAP_EL3; | ||
174 | + } | ||
175 | + return CP_ACCESS_OK; | ||
176 | +} | ||
177 | + | ||
178 | +static const ARMCPRegInfo scxtnum_reginfo[] = { | ||
179 | + { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | ||
180 | + .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | ||
181 | + .access = PL0_RW, .accessfn = access_scxtnum, | ||
182 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, | ||
183 | + { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | ||
184 | + .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | ||
185 | + .access = PL1_RW, .accessfn = access_scxtnum, | ||
186 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, | ||
187 | + { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | ||
188 | + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | ||
189 | + .access = PL2_RW, .accessfn = access_scxtnum, | ||
190 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | ||
191 | + { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | ||
192 | + .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | ||
193 | + .access = PL3_RW, | ||
194 | + .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | ||
195 | +}; | ||
196 | +#endif /* TARGET_AARCH64 */ | ||
197 | |||
198 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
199 | bool isread) | ||
200 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
201 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | ||
202 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
179 | } | 203 | } |
180 | }; | 204 | + |
205 | + if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
206 | + define_arm_cp_regs(cpu, scxtnum_reginfo); | ||
207 | + } | ||
208 | #endif | ||
209 | |||
210 | if (cpu_isar_feature(any_predinv, cpu)) { | ||
181 | -- | 211 | -- |
182 | 2.7.4 | 212 | 2.25.1 |
183 | |||
184 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | This extension concerns cache speculation, which TCG does |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | not implement. Thus we can trivially enable this feature. |
5 | Message-id: 20170905131149.10669-7-famz@redhat.com | 5 | |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220506180242.216785-22-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 10 | --- |
9 | hw/dma/xilinx_axidma.c | 16 ++++------------ | 11 | docs/system/arm/emulation.rst | 1 + |
10 | 1 file changed, 4 insertions(+), 12 deletions(-) | 12 | target/arm/cpu64.c | 1 + |
13 | target/arm/cpu_tcg.c | 1 + | ||
14 | 3 files changed, 3 insertions(+) | ||
11 | 15 | ||
12 | diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c | 16 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
13 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/dma/xilinx_axidma.c | 18 | --- a/docs/system/arm/emulation.rst |
15 | +++ b/hw/dma/xilinx_axidma.c | 19 | +++ b/docs/system/arm/emulation.rst |
16 | @@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_init(Object *obj) | 20 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
17 | XilinxAXIDMA *s = XILINX_AXI_DMA(obj); | 21 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) |
18 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) |
19 | 23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | |
20 | - object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, | 24 | +- FEAT_CSV3 (Cache speculation variant 3) |
21 | - (Object **)&s->tx_data_dev, | 25 | - FEAT_DIT (Data Independent Timing instructions) |
22 | - qdev_prop_allow_set_link_before_realize, | 26 | - FEAT_DPB (DC CVAP instruction) |
23 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | 27 | - FEAT_Debugv8p2 (Debug changes for v8.2) |
24 | - &error_abort); | 28 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
25 | - object_property_add_link(obj, "axistream-control-connected", | 29 | index XXXXXXX..XXXXXXX 100644 |
26 | - TYPE_STREAM_SLAVE, | 30 | --- a/target/arm/cpu64.c |
27 | - (Object **)&s->tx_control_dev, | 31 | +++ b/target/arm/cpu64.c |
28 | - qdev_prop_allow_set_link_before_realize, | 32 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
29 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | 33 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ |
30 | - &error_abort); | 34 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ |
31 | - | 35 | t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ |
32 | object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), | 36 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ |
33 | TYPE_XILINX_AXI_DMA_DATA_STREAM); | 37 | cpu->isar.id_aa64pfr0 = t; |
34 | object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), | 38 | |
35 | @@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_init(Object *obj) | 39 | t = cpu->isar.id_aa64pfr1; |
36 | 40 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | |
37 | static Property axidma_properties[] = { | 41 | index XXXXXXX..XXXXXXX 100644 |
38 | DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000), | 42 | --- a/target/arm/cpu_tcg.c |
39 | + DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA, | 43 | +++ b/target/arm/cpu_tcg.c |
40 | + tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), | 44 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
41 | + DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA, | 45 | cpu->isar.id_pfr0 = t; |
42 | + tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), | 46 | |
43 | DEFINE_PROP_END_OF_LIST(), | 47 | t = cpu->isar.id_pfr2; |
44 | }; | 48 | + t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ |
49 | t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ | ||
50 | cpu->isar.id_pfr2 = t; | ||
45 | 51 | ||
46 | -- | 52 | -- |
47 | 2.7.4 | 53 | 2.25.1 |
48 | |||
49 | diff view generated by jsdifflib |
1 | Make the BASEPRI register banked if v8M security extensions are enabled. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Note that we do not yet implement the functionality of the new | 3 | This extension concerns not merging memory access, which TCG does |
4 | AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to | 4 | not implement. Thus we can trivially enable this feature. |
5 | be restricted). | 5 | Add a comment to handle_hint for the DGH instruction, but no code. |
6 | 6 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220506180242.216785-23-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 1503414539-28762-7-git-send-email-peter.maydell@linaro.org | ||
10 | --- | 11 | --- |
11 | target/arm/cpu.h | 14 +++++++++++++- | 12 | docs/system/arm/emulation.rst | 1 + |
12 | hw/intc/armv7m_nvic.c | 4 ++-- | 13 | target/arm/cpu64.c | 1 + |
13 | target/arm/helper.c | 10 ++++++---- | 14 | target/arm/translate-a64.c | 1 + |
14 | target/arm/machine.c | 3 ++- | 15 | 3 files changed, 3 insertions(+) |
15 | 4 files changed, 23 insertions(+), 8 deletions(-) | ||
16 | 16 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 19 | --- a/docs/system/arm/emulation.rst |
20 | +++ b/target/arm/cpu.h | 20 | +++ b/docs/system/arm/emulation.rst |
21 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
22 | #define ARMV7M_EXCP_PENDSV 14 | 22 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) |
23 | #define ARMV7M_EXCP_SYSTICK 15 | 23 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) |
24 | 24 | - FEAT_CSV3 (Cache speculation variant 3) | |
25 | +/* For M profile, some registers are banked secure vs non-secure; | 25 | +- FEAT_DGH (Data gathering hint) |
26 | + * these are represented as a 2-element array where the first element | 26 | - FEAT_DIT (Data Independent Timing instructions) |
27 | + * is the non-secure copy and the second is the secure copy. | 27 | - FEAT_DPB (DC CVAP instruction) |
28 | + * When the CPU does not have implement the security extension then | 28 | - FEAT_Debugv8p2 (Debug changes for v8.2) |
29 | + * only the first element is used. | 29 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
30 | + * This means that the copy for the current security state can be | ||
31 | + * accessed via env->registerfield[env->v7m.secure] (whether the security | ||
32 | + * extension is implemented or not). | ||
33 | + */ | ||
34 | +#define M_REG_NS 0 | ||
35 | +#define M_REG_S 1 | ||
36 | + | ||
37 | /* ARM-specific interrupt pending bits. */ | ||
38 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | ||
39 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 | ||
40 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
41 | struct { | ||
42 | uint32_t other_sp; | ||
43 | uint32_t vecbase; | ||
44 | - uint32_t basepri; | ||
45 | + uint32_t basepri[2]; | ||
46 | uint32_t control; | ||
47 | uint32_t ccr; /* Configuration and Control */ | ||
48 | uint32_t cfsr; /* Configurable Fault Status */ | ||
49 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/hw/intc/armv7m_nvic.c | 31 | --- a/target/arm/cpu64.c |
52 | +++ b/hw/intc/armv7m_nvic.c | 32 | +++ b/target/arm/cpu64.c |
53 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | 33 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
54 | running = -1; | 34 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ |
55 | } else if (env->v7m.primask) { | 35 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ |
56 | running = 0; | 36 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ |
57 | - } else if (env->v7m.basepri > 0) { | 37 | + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ |
58 | - running = env->v7m.basepri & nvic_gprio_mask(s); | 38 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ |
59 | + } else if (env->v7m.basepri[env->v7m.secure] > 0) { | 39 | cpu->isar.id_aa64isar1 = t; |
60 | + running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); | 40 | |
61 | } else { | 41 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
62 | running = NVIC_NOEXC_PRIO; /* lower than any possible priority */ | ||
63 | } | ||
64 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | 42 | index XXXXXXX..XXXXXXX 100644 |
66 | --- a/target/arm/helper.c | 43 | --- a/target/arm/translate-a64.c |
67 | +++ b/target/arm/helper.c | 44 | +++ b/target/arm/translate-a64.c |
68 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 45 | @@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn, |
69 | return env->v7m.primask; | ||
70 | case 17: /* BASEPRI */ | ||
71 | case 18: /* BASEPRI_MAX */ | ||
72 | - return env->v7m.basepri; | ||
73 | + return env->v7m.basepri[env->v7m.secure]; | ||
74 | case 19: /* FAULTMASK */ | ||
75 | return env->v7m.faultmask; | ||
76 | default: | ||
77 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
78 | env->v7m.primask = val & 1; | ||
79 | break; | 46 | break; |
80 | case 17: /* BASEPRI */ | 47 | case 0b00100: /* SEV */ |
81 | - env->v7m.basepri = val & 0xff; | 48 | case 0b00101: /* SEVL */ |
82 | + env->v7m.basepri[env->v7m.secure] = val & 0xff; | 49 | + case 0b00110: /* DGH */ |
50 | /* we treat all as NOP at least for now */ | ||
83 | break; | 51 | break; |
84 | case 18: /* BASEPRI_MAX */ | 52 | case 0b00111: /* XPACLRI */ |
85 | val &= 0xff; | ||
86 | - if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | ||
87 | - env->v7m.basepri = val; | ||
88 | + if (val != 0 && (val < env->v7m.basepri[env->v7m.secure] | ||
89 | + || env->v7m.basepri[env->v7m.secure] == 0)) { | ||
90 | + env->v7m.basepri[env->v7m.secure] = val; | ||
91 | + } | ||
92 | break; | ||
93 | case 19: /* FAULTMASK */ | ||
94 | env->v7m.faultmask = val & 1; | ||
95 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | ||
97 | --- a/target/arm/machine.c | ||
98 | +++ b/target/arm/machine.c | ||
99 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
100 | .needed = m_needed, | ||
101 | .fields = (VMStateField[]) { | ||
102 | VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), | ||
103 | - VMSTATE_UINT32(env.v7m.basepri, ARMCPU), | ||
104 | + VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | ||
105 | VMSTATE_UINT32(env.v7m.control, ARMCPU), | ||
106 | VMSTATE_UINT32(env.v7m.ccr, ARMCPU), | ||
107 | VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | ||
108 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
109 | .needed = m_security_needed, | ||
110 | .fields = (VMStateField[]) { | ||
111 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), | ||
112 | + VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | ||
113 | VMSTATE_END_OF_LIST() | ||
114 | } | ||
115 | }; | ||
116 | -- | 53 | -- |
117 | 2.7.4 | 54 | 2.25.1 |
118 | |||
119 | diff view generated by jsdifflib |
1 | Implement the behavioural side of the new PMSAv8 specification. | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Enable the a76 for virt and sbsa board use. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220506180242.216785-24-richard.henderson@linaro.org | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 1503414539-28762-3-git-send-email-peter.maydell@linaro.org | ||
6 | --- | 9 | --- |
7 | target/arm/helper.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++++- | 10 | docs/system/arm/virt.rst | 1 + |
8 | 1 file changed, 110 insertions(+), 1 deletion(-) | 11 | hw/arm/sbsa-ref.c | 1 + |
12 | hw/arm/virt.c | 1 + | ||
13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 69 insertions(+) | ||
9 | 15 | ||
10 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst |
11 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/target/arm/helper.c | 18 | --- a/docs/system/arm/virt.rst |
13 | +++ b/target/arm/helper.c | 19 | +++ b/docs/system/arm/virt.rst |
14 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, | 20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: |
15 | return !(*prot & (1 << access_type)); | 21 | - ``cortex-a53`` (64-bit) |
22 | - ``cortex-a57`` (64-bit) | ||
23 | - ``cortex-a72`` (64-bit) | ||
24 | +- ``cortex-a76`` (64-bit) | ||
25 | - ``a64fx`` (64-bit) | ||
26 | - ``host`` (with KVM only) | ||
27 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) | ||
28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/hw/arm/sbsa-ref.c | ||
31 | +++ b/hw/arm/sbsa-ref.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { | ||
33 | static const char * const valid_cpus[] = { | ||
34 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
35 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
36 | + ARM_CPU_TYPE_NAME("cortex-a76"), | ||
37 | ARM_CPU_TYPE_NAME("max"), | ||
38 | }; | ||
39 | |||
40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/virt.c | ||
43 | +++ b/hw/arm/virt.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | ||
45 | ARM_CPU_TYPE_NAME("cortex-a53"), | ||
46 | ARM_CPU_TYPE_NAME("cortex-a57"), | ||
47 | ARM_CPU_TYPE_NAME("cortex-a72"), | ||
48 | + ARM_CPU_TYPE_NAME("cortex-a76"), | ||
49 | ARM_CPU_TYPE_NAME("a64fx"), | ||
50 | ARM_CPU_TYPE_NAME("host"), | ||
51 | ARM_CPU_TYPE_NAME("max"), | ||
52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/cpu64.c | ||
55 | +++ b/target/arm/cpu64.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
57 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | ||
16 | } | 58 | } |
17 | 59 | ||
18 | +static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | 60 | +static void aarch64_a76_initfn(Object *obj) |
19 | + MMUAccessType access_type, ARMMMUIdx mmu_idx, | ||
20 | + hwaddr *phys_ptr, int *prot, uint32_t *fsr) | ||
21 | +{ | 61 | +{ |
22 | + ARMCPU *cpu = arm_env_get_cpu(env); | 62 | + ARMCPU *cpu = ARM_CPU(obj); |
23 | + bool is_user = regime_is_user(env, mmu_idx); | ||
24 | + int n; | ||
25 | + int matchregion = -1; | ||
26 | + bool hit = false; | ||
27 | + | 63 | + |
28 | + *phys_ptr = address; | 64 | + cpu->dtb_compatible = "arm,cortex-a76"; |
29 | + *prot = 0; | 65 | + set_feature(&cpu->env, ARM_FEATURE_V8); |
66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
30 | + | 73 | + |
31 | + /* Unlike the ARM ARM pseudocode, we don't need to check whether this | 74 | + /* Ordered by B2.4 AArch64 registers by functional group */ |
32 | + * was an exception vector read from the vector table (which is always | 75 | + cpu->clidr = 0x82000023; |
33 | + * done using the default system address map), because those accesses | 76 | + cpu->ctr = 0x8444C004; |
34 | + * are done in arm_v7m_load_vector(), which always does a direct | 77 | + cpu->dcz_blocksize = 4; |
35 | + * read using address_space_ldl(), rather than going via this function. | 78 | + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; |
36 | + */ | 79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; |
37 | + if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | 80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; |
38 | + hit = true; | 81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; |
39 | + } else if (m_is_ppb_region(env, address)) { | 82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; |
40 | + hit = true; | 83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; |
41 | + } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { | 84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ |
42 | + hit = true; | 85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; |
43 | + } else { | 86 | + cpu->id_afr0 = 0x00000000; |
44 | + for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | 87 | + cpu->isar.id_dfr0 = 0x04010088; |
45 | + /* region search */ | 88 | + cpu->isar.id_isar0 = 0x02101110; |
46 | + /* Note that the base address is bits [31:5] from the register | 89 | + cpu->isar.id_isar1 = 0x13112111; |
47 | + * with bits [4:0] all zeroes, but the limit address is bits | 90 | + cpu->isar.id_isar2 = 0x21232042; |
48 | + * [31:5] from the register with bits [4:0] all ones. | 91 | + cpu->isar.id_isar3 = 0x01112131; |
49 | + */ | 92 | + cpu->isar.id_isar4 = 0x00010142; |
50 | + uint32_t base = env->pmsav8.rbar[n] & ~0x1f; | 93 | + cpu->isar.id_isar5 = 0x01011121; |
51 | + uint32_t limit = env->pmsav8.rlar[n] | 0x1f; | 94 | + cpu->isar.id_isar6 = 0x00000010; |
95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
103 | + cpu->midr = 0x414fd0b1; /* r4p1 */ | ||
104 | + cpu->revidr = 0; | ||
52 | + | 105 | + |
53 | + if (!(env->pmsav8.rlar[n] & 0x1)) { | 106 | + /* From B2.18 CCSIDR_EL1 */ |
54 | + /* Region disabled */ | 107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ |
55 | + continue; | 108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ |
56 | + } | 109 | + cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ |
57 | + | 110 | + |
58 | + if (address < base || address > limit) { | 111 | + /* From B2.93 SCTLR_EL3 */ |
59 | + continue; | 112 | + cpu->reset_sctlr = 0x30c50838; |
60 | + } | ||
61 | + | 113 | + |
62 | + if (hit) { | 114 | + /* From B4.23 ICH_VTR_EL2 */ |
63 | + /* Multiple regions match -- always a failure (unlike | 115 | + cpu->gic_num_lrs = 4; |
64 | + * PMSAv7 where highest-numbered-region wins) | 116 | + cpu->gic_vpribits = 5; |
65 | + */ | 117 | + cpu->gic_vprebits = 5; |
66 | + *fsr = 0x00d; /* permission fault */ | ||
67 | + return true; | ||
68 | + } | ||
69 | + | 118 | + |
70 | + matchregion = n; | 119 | + /* From B5.1 AdvSIMD AArch64 register summary */ |
71 | + hit = true; | 120 | + cpu->isar.mvfr0 = 0x10110222; |
72 | + | 121 | + cpu->isar.mvfr1 = 0x13211111; |
73 | + if (base & ~TARGET_PAGE_MASK) { | 122 | + cpu->isar.mvfr2 = 0x00000043; |
74 | + qemu_log_mask(LOG_UNIMP, | ||
75 | + "MPU_RBAR[%d]: No support for MPU region base" | ||
76 | + "address of 0x%" PRIx32 ". Minimum alignment is " | ||
77 | + "%d\n", | ||
78 | + n, base, TARGET_PAGE_BITS); | ||
79 | + continue; | ||
80 | + } | ||
81 | + if ((limit + 1) & ~TARGET_PAGE_MASK) { | ||
82 | + qemu_log_mask(LOG_UNIMP, | ||
83 | + "MPU_RBAR[%d]: No support for MPU region limit" | ||
84 | + "address of 0x%" PRIx32 ". Minimum alignment is " | ||
85 | + "%d\n", | ||
86 | + n, limit, TARGET_PAGE_BITS); | ||
87 | + continue; | ||
88 | + } | ||
89 | + } | ||
90 | + } | ||
91 | + | ||
92 | + if (!hit) { | ||
93 | + /* background fault */ | ||
94 | + *fsr = 0; | ||
95 | + return true; | ||
96 | + } | ||
97 | + | ||
98 | + if (matchregion == -1) { | ||
99 | + /* hit using the background region */ | ||
100 | + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | ||
101 | + } else { | ||
102 | + uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2); | ||
103 | + uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1); | ||
104 | + | ||
105 | + if (m_is_system_region(env, address)) { | ||
106 | + /* System space is always execute never */ | ||
107 | + xn = 1; | ||
108 | + } | ||
109 | + | ||
110 | + *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | ||
111 | + if (*prot && !xn) { | ||
112 | + *prot |= PAGE_EXEC; | ||
113 | + } | ||
114 | + /* We don't need to look the attribute up in the MAIR0/MAIR1 | ||
115 | + * registers because that only tells us about cacheability. | ||
116 | + */ | ||
117 | + } | ||
118 | + | ||
119 | + *fsr = 0x00d; /* Permission fault */ | ||
120 | + return !(*prot & (1 << access_type)); | ||
121 | +} | 123 | +} |
122 | + | 124 | + |
123 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, | 125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) |
124 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | 126 | { |
125 | hwaddr *phys_ptr, int *prot, uint32_t *fsr) | 127 | /* |
126 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, | 128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { |
127 | bool ret; | 129 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, |
128 | *page_size = TARGET_PAGE_SIZE; | 130 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, |
129 | 131 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | |
130 | - if (arm_feature(env, ARM_FEATURE_V7)) { | 132 | + { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, |
131 | + if (arm_feature(env, ARM_FEATURE_V8)) { | 133 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, |
132 | + /* PMSAv8 */ | 134 | { .name = "max", .initfn = aarch64_max_initfn }, |
133 | + ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | 135 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) |
134 | + phys_ptr, prot, fsr); | ||
135 | + } else if (arm_feature(env, ARM_FEATURE_V7)) { | ||
136 | /* PMSAv7 */ | ||
137 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | ||
138 | phys_ptr, prot, fsr); | ||
139 | -- | 136 | -- |
140 | 2.7.4 | 137 | 2.25.1 |
141 | |||
142 | diff view generated by jsdifflib |
1 | As the first step in implementing ARM v8M's security extension: | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | * add a new feature bit ARM_FEATURE_M_SECURITY | ||
3 | * add the CPU state field that indicates whether the CPU is | ||
4 | currently in the secure state | ||
5 | * add a migration subsection for this new state | ||
6 | (we will add the Secure copies of banked register state | ||
7 | to this subsection in later patches) | ||
8 | * add a #define for the one new-in-v8M exception type | ||
9 | * make the CPU debug log print S/NS status | ||
10 | 2 | ||
3 | Enable the n1 for virt and sbsa board use. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220506180242.216785-25-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 1503414539-28762-4-git-send-email-peter.maydell@linaro.org | ||
14 | --- | 9 | --- |
15 | target/arm/cpu.h | 3 +++ | 10 | docs/system/arm/virt.rst | 1 + |
16 | target/arm/cpu.c | 4 ++++ | 11 | hw/arm/sbsa-ref.c | 1 + |
17 | target/arm/machine.c | 20 ++++++++++++++++++++ | 12 | hw/arm/virt.c | 1 + |
18 | target/arm/translate.c | 8 +++++++- | 13 | target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ |
19 | 4 files changed, 34 insertions(+), 1 deletion(-) | 14 | 4 files changed, 69 insertions(+) |
20 | 15 | ||
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst |
22 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/cpu.h | 18 | --- a/docs/system/arm/virt.rst |
24 | +++ b/target/arm/cpu.h | 19 | +++ b/docs/system/arm/virt.rst |
25 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: |
26 | #define ARMV7M_EXCP_MEM 4 | 21 | - ``cortex-a76`` (64-bit) |
27 | #define ARMV7M_EXCP_BUS 5 | 22 | - ``a64fx`` (64-bit) |
28 | #define ARMV7M_EXCP_USAGE 6 | 23 | - ``host`` (with KVM only) |
29 | +#define ARMV7M_EXCP_SECURE 7 | 24 | +- ``neoverse-n1`` (64-bit) |
30 | #define ARMV7M_EXCP_SVC 11 | 25 | - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) |
31 | #define ARMV7M_EXCP_DEBUG 12 | 26 | |
32 | #define ARMV7M_EXCP_PENDSV 14 | 27 | Note that the default is ``cortex-a15``, so for an AArch64 guest you must |
33 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 28 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
34 | int exception; | 29 | index XXXXXXX..XXXXXXX 100644 |
35 | uint32_t primask; | 30 | --- a/hw/arm/sbsa-ref.c |
36 | uint32_t faultmask; | 31 | +++ b/hw/arm/sbsa-ref.c |
37 | + uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | 32 | @@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = { |
38 | } v7m; | 33 | ARM_CPU_TYPE_NAME("cortex-a57"), |
39 | 34 | ARM_CPU_TYPE_NAME("cortex-a72"), | |
40 | /* Information associated with an exception about to be taken: | 35 | ARM_CPU_TYPE_NAME("cortex-a76"), |
41 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 36 | + ARM_CPU_TYPE_NAME("neoverse-n1"), |
42 | ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ | 37 | ARM_CPU_TYPE_NAME("max"), |
43 | ARM_FEATURE_PMU, /* has PMU support */ | ||
44 | ARM_FEATURE_VBAR, /* has cp15 VBAR */ | ||
45 | + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ | ||
46 | }; | 38 | }; |
47 | 39 | ||
48 | static inline int arm_feature(CPUARMState *env, int feature) | 40 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
49 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/target/arm/cpu.c | 42 | --- a/hw/arm/virt.c |
52 | +++ b/target/arm/cpu.c | 43 | +++ b/hw/arm/virt.c |
53 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 44 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { |
54 | uint32_t initial_pc; /* Loaded from 0x4 */ | 45 | ARM_CPU_TYPE_NAME("cortex-a72"), |
55 | uint8_t *rom; | 46 | ARM_CPU_TYPE_NAME("cortex-a76"), |
56 | 47 | ARM_CPU_TYPE_NAME("a64fx"), | |
57 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 48 | + ARM_CPU_TYPE_NAME("neoverse-n1"), |
58 | + env->v7m.secure = true; | 49 | ARM_CPU_TYPE_NAME("host"), |
59 | + } | 50 | ARM_CPU_TYPE_NAME("max"), |
51 | }; | ||
52 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/cpu64.c | ||
55 | +++ b/target/arm/cpu64.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj) | ||
57 | cpu->isar.mvfr2 = 0x00000043; | ||
58 | } | ||
59 | |||
60 | +static void aarch64_neoverse_n1_initfn(Object *obj) | ||
61 | +{ | ||
62 | + ARMCPU *cpu = ARM_CPU(obj); | ||
60 | + | 63 | + |
61 | /* The reset value of this bit is IMPDEF, but ARM recommends | 64 | + cpu->dtb_compatible = "arm,neoverse-n1"; |
62 | * that it resets to 1, so QEMU always does that rather than making | 65 | + set_feature(&cpu->env, ARM_FEATURE_V8); |
63 | * it dependent on CPU model. | 66 | + set_feature(&cpu->env, ARM_FEATURE_NEON); |
64 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 67 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
65 | index XXXXXXX..XXXXXXX 100644 | 68 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
66 | --- a/target/arm/machine.c | 69 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
67 | +++ b/target/arm/machine.c | 70 | + set_feature(&cpu->env, ARM_FEATURE_EL2); |
68 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = { | 71 | + set_feature(&cpu->env, ARM_FEATURE_EL3); |
69 | } | 72 | + set_feature(&cpu->env, ARM_FEATURE_PMU); |
70 | }; | ||
71 | |||
72 | +static bool m_security_needed(void *opaque) | ||
73 | +{ | ||
74 | + ARMCPU *cpu = opaque; | ||
75 | + CPUARMState *env = &cpu->env; | ||
76 | + | 73 | + |
77 | + return arm_feature(env, ARM_FEATURE_M_SECURITY); | 74 | + /* Ordered by B2.4 AArch64 registers by functional group */ |
75 | + cpu->clidr = 0x82000023; | ||
76 | + cpu->ctr = 0x8444c004; | ||
77 | + cpu->dcz_blocksize = 4; | ||
78 | + cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; | ||
79 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | ||
80 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | ||
81 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; | ||
82 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | ||
83 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | ||
84 | + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ | ||
85 | + cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; | ||
86 | + cpu->id_afr0 = 0x00000000; | ||
87 | + cpu->isar.id_dfr0 = 0x04010088; | ||
88 | + cpu->isar.id_isar0 = 0x02101110; | ||
89 | + cpu->isar.id_isar1 = 0x13112111; | ||
90 | + cpu->isar.id_isar2 = 0x21232042; | ||
91 | + cpu->isar.id_isar3 = 0x01112131; | ||
92 | + cpu->isar.id_isar4 = 0x00010142; | ||
93 | + cpu->isar.id_isar5 = 0x01011121; | ||
94 | + cpu->isar.id_isar6 = 0x00000010; | ||
95 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
96 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
97 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
98 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
99 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
100 | + cpu->isar.id_pfr0 = 0x10010131; | ||
101 | + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ | ||
102 | + cpu->isar.id_pfr2 = 0x00000011; | ||
103 | + cpu->midr = 0x414fd0c1; /* r4p1 */ | ||
104 | + cpu->revidr = 0; | ||
105 | + | ||
106 | + /* From B2.23 CCSIDR_EL1 */ | ||
107 | + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | ||
108 | + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | ||
109 | + cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ | ||
110 | + | ||
111 | + /* From B2.98 SCTLR_EL3 */ | ||
112 | + cpu->reset_sctlr = 0x30c50838; | ||
113 | + | ||
114 | + /* From B4.23 ICH_VTR_EL2 */ | ||
115 | + cpu->gic_num_lrs = 4; | ||
116 | + cpu->gic_vpribits = 5; | ||
117 | + cpu->gic_vprebits = 5; | ||
118 | + | ||
119 | + /* From B5.1 AdvSIMD AArch64 register summary */ | ||
120 | + cpu->isar.mvfr0 = 0x10110222; | ||
121 | + cpu->isar.mvfr1 = 0x13211111; | ||
122 | + cpu->isar.mvfr2 = 0x00000043; | ||
78 | +} | 123 | +} |
79 | + | 124 | + |
80 | +static const VMStateDescription vmstate_m_security = { | 125 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) |
81 | + .name = "cpu/m-security", | ||
82 | + .version_id = 1, | ||
83 | + .minimum_version_id = 1, | ||
84 | + .needed = m_security_needed, | ||
85 | + .fields = (VMStateField[]) { | ||
86 | + VMSTATE_UINT32(env.v7m.secure, ARMCPU), | ||
87 | + VMSTATE_END_OF_LIST() | ||
88 | + } | ||
89 | +}; | ||
90 | + | ||
91 | static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | ||
92 | VMStateField *field) | ||
93 | { | 126 | { |
94 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = { | 127 | /* |
95 | &vmstate_pmsav7_rnr, | 128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { |
96 | &vmstate_pmsav7, | 129 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, |
97 | &vmstate_pmsav8, | 130 | { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, |
98 | + &vmstate_m_security, | 131 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, |
99 | NULL | 132 | + { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, |
100 | } | 133 | { .name = "max", .initfn = aarch64_max_initfn }, |
101 | }; | 134 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) |
102 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 135 | { .name = "host", .initfn = aarch64_host_initfn }, |
103 | index XXXXXXX..XXXXXXX 100644 | ||
104 | --- a/target/arm/translate.c | ||
105 | +++ b/target/arm/translate.c | ||
106 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | ||
107 | if (arm_feature(env, ARM_FEATURE_M)) { | ||
108 | uint32_t xpsr = xpsr_read(env); | ||
109 | const char *mode; | ||
110 | + const char *ns_status = ""; | ||
111 | + | ||
112 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
113 | + ns_status = env->v7m.secure ? "S " : "NS "; | ||
114 | + } | ||
115 | |||
116 | if (xpsr & XPSR_EXCP) { | ||
117 | mode = "handler"; | ||
118 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | ||
119 | } | ||
120 | } | ||
121 | |||
122 | - cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", | ||
123 | + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", | ||
124 | xpsr, | ||
125 | xpsr & XPSR_N ? 'N' : '-', | ||
126 | xpsr & XPSR_Z ? 'Z' : '-', | ||
127 | xpsr & XPSR_C ? 'C' : '-', | ||
128 | xpsr & XPSR_V ? 'V' : '-', | ||
129 | xpsr & XPSR_T ? 'T' : 'A', | ||
130 | + ns_status, | ||
131 | mode); | ||
132 | } else { | ||
133 | uint32_t psr = cpsr_read(env); | ||
134 | -- | 136 | -- |
135 | 2.7.4 | 137 | 2.25.1 |
136 | |||
137 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> |
---|---|---|---|
2 | 2 | ||
3 | QEMU currently exits unexpectedly when the user accidentially | 3 | The sbsa-ref machine is continuously evolving. Some of the changes we |
4 | tries to do something like this: | 4 | want to make in the near future, to align with real components (e.g. |
5 | the GIC-700), will break compatibility for existing firmware. | ||
5 | 6 | ||
6 | $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic | 7 | Introduce two new properties to the DT generated on machine generation: |
7 | QEMU 2.9.93 monitor - type 'help' for more information | 8 | - machine-version-major |
8 | (qemu) device_add allwinner-a10 | 9 | To be incremented when a platform change makes the machine |
9 | Unsupported NIC model: smc91c111 | 10 | incompatible with existing firmware. |
11 | - machine-version-minor | ||
12 | To be incremented when functionality is added to the machine | ||
13 | without causing incompatibility with existing firmware. | ||
14 | to be reset to 0 when machine-version-major is incremented. | ||
10 | 15 | ||
11 | Exiting just due to a "device_add" should not happen. Looking closer | 16 | This versioning scheme is *neither*: |
12 | at the the realize and instance_init function of this device also | 17 | - A QEMU versioned machine type; a given version of QEMU will emulate |
13 | reveals that it is using serial_hds and nd_table directly there, so | 18 | a given version of the platform. |
14 | this device is clearly not creatable by the user and should be marked | 19 | - A reflection of level of SBSA (now SystemReady SR) support provided. |
15 | accordingly. | ||
16 | 20 | ||
17 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 21 | The version will increment on guest-visible functional changes only, |
18 | Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> | 22 | akin to a revision ID register found on a physical platform. |
19 | Message-id: 1503416789-32080-1-git-send-email-thuth@redhat.com | 23 | |
24 | These properties are both introduced with the value 0. | ||
25 | (Hence, a machine where the DT is lacking these nodes is equivalent | ||
26 | to version 0.0.) | ||
27 | |||
28 | Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
29 | Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com | ||
30 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Cc: Radoslaw Biernacki <rad@semihalf.com> | ||
32 | Cc: Cédric Le Goater <clg@kaod.org> | ||
20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 33 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 35 | --- |
23 | hw/arm/allwinner-a10.c | 2 ++ | 36 | hw/arm/sbsa-ref.c | 14 ++++++++++++++ |
24 | scripts/device-crash-test | 1 - | 37 | 1 file changed, 14 insertions(+) |
25 | 2 files changed, 2 insertions(+), 1 deletion(-) | ||
26 | 38 | ||
27 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | 39 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
28 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/hw/arm/allwinner-a10.c | 41 | --- a/hw/arm/sbsa-ref.c |
30 | +++ b/hw/arm/allwinner-a10.c | 42 | +++ b/hw/arm/sbsa-ref.c |
31 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_class_init(ObjectClass *oc, void *data) | 43 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms) |
32 | DeviceClass *dc = DEVICE_CLASS(oc); | 44 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); |
33 | 45 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
34 | dc->realize = aw_a10_realize; | 46 | |
35 | + /* Reason: Uses serial_hds in realize and nd_table in instance_init */ | 47 | + /* |
36 | + dc->user_creatable = false; | 48 | + * This versioning scheme is for informing platform fw only. It is neither: |
37 | } | 49 | + * - A QEMU versioned machine type; a given version of QEMU will emulate |
38 | 50 | + * a given version of the platform. | |
39 | static const TypeInfo aw_a10_type_info = { | 51 | + * - A reflection of level of SBSA (now SystemReady SR) support provided. |
40 | diff --git a/scripts/device-crash-test b/scripts/device-crash-test | 52 | + * |
41 | index XXXXXXX..XXXXXXX 100755 | 53 | + * machine-version-major: updated when changes breaking fw compatibility |
42 | --- a/scripts/device-crash-test | 54 | + * are introduced. |
43 | +++ b/scripts/device-crash-test | 55 | + * machine-version-minor: updated when features are added that don't break |
44 | @@ -XXX,XX +XXX,XX @@ ERROR_WHITELIST = [ | 56 | + * fw compatibility. |
45 | {'log':r"Device [\w.,-]+ can not be dynamically instantiated"}, | 57 | + */ |
46 | {'log':r"Platform Bus: Can not fit MMIO region of size "}, | 58 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); |
47 | # other more specific errors we will ignore: | 59 | + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0); |
48 | - {'device':'allwinner-a10', 'log':"Unsupported NIC model:"}, | 60 | + |
49 | {'device':'.*-spapr-cpu-core', 'log':r"CPU core type should be"}, | 61 | if (ms->numa_state->have_numa_distance) { |
50 | {'log':r"MSI(-X)? is not supported by interrupt controller"}, | 62 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); |
51 | {'log':r"pxb-pcie? devices cannot reside on a PCIe? bus"}, | 63 | uint32_t *matrix = g_malloc0(size); |
52 | -- | 64 | -- |
53 | 2.7.4 | 65 | 2.25.1 |
54 | 66 | ||
55 | 67 | diff view generated by jsdifflib |
1 | Now that MPU lookups can return different results for v8M | 1 | From: Gavin Shan <gshan@redhat.com> |
---|---|---|---|
2 | when the CPU is in secure vs non-secure state, we need to | ||
3 | have separate MMU indexes; add the secure counterparts | ||
4 | to the existing three M profile MMU indexes. | ||
5 | 2 | ||
3 | This adds cluster-id in CPU instance properties, which will be used | ||
4 | by arm/virt machine. Besides, the cluster-id is also verified or | ||
5 | dumped in various spots: | ||
6 | |||
7 | * hw/core/machine.c::machine_set_cpu_numa_node() to associate | ||
8 | CPU with its NUMA node. | ||
9 | |||
10 | * hw/core/machine.c::machine_numa_finish_cpu_init() to record | ||
11 | CPU slots with no NUMA mapping set. | ||
12 | |||
13 | * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump | ||
14 | cluster-id. | ||
15 | |||
16 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
17 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
18 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
19 | Message-id: 20220503140304.855514-2-gshan@redhat.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 1503414539-28762-6-git-send-email-peter.maydell@linaro.org | ||
9 | --- | 21 | --- |
10 | target/arm/cpu.h | 19 +++++++++++++++++-- | 22 | qapi/machine.json | 6 ++++-- |
11 | target/arm/helper.c | 9 ++++++++- | 23 | hw/core/machine-hmp-cmds.c | 4 ++++ |
12 | 2 files changed, 25 insertions(+), 3 deletions(-) | 24 | hw/core/machine.c | 16 ++++++++++++++++ |
25 | 3 files changed, 24 insertions(+), 2 deletions(-) | ||
13 | 26 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 27 | diff --git a/qapi/machine.json b/qapi/machine.json |
15 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 29 | --- a/qapi/machine.json |
17 | +++ b/target/arm/cpu.h | 30 | +++ b/qapi/machine.json |
18 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | 31 | @@ -XXX,XX +XXX,XX @@ |
19 | * Execution priority negative (this is like privileged, but the | 32 | # @node-id: NUMA node ID the CPU belongs to |
20 | * MPU HFNMIENA bit means that it may have different access permission | 33 | # @socket-id: socket number within node/board the CPU belongs to |
21 | * check results to normal privileged code, so can't share a TLB). | 34 | # @die-id: die number within socket the CPU belongs to (since 4.1) |
22 | + * If the CPU supports the v8M Security Extension then there are also: | 35 | -# @core-id: core number within die the CPU belongs to |
23 | + * Secure User | 36 | +# @cluster-id: cluster number within die the CPU belongs to (since 7.1) |
24 | + * Secure Privileged | 37 | +# @core-id: core number within cluster the CPU belongs to |
25 | + * Secure, execution priority negative | 38 | # @thread-id: thread number within core the CPU belongs to |
26 | * | 39 | # |
27 | * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code | 40 | -# Note: currently there are 5 properties that could be present |
28 | * are not quite the same -- different CPU types (most notably M profile | 41 | +# Note: currently there are 6 properties that could be present |
29 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx { | 42 | # but management should be prepared to pass through other |
30 | ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, | 43 | # properties with device_add command to allow for future |
31 | ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, | 44 | # interface extension. This also requires the filed names to be kept in |
32 | ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, | 45 | @@ -XXX,XX +XXX,XX @@ |
33 | + ARMMMUIdx_MSUser = 3 | ARM_MMU_IDX_M, | 46 | 'data': { '*node-id': 'int', |
34 | + ARMMMUIdx_MSPriv = 4 | ARM_MMU_IDX_M, | 47 | '*socket-id': 'int', |
35 | + ARMMMUIdx_MSNegPri = 5 | ARM_MMU_IDX_M, | 48 | '*die-id': 'int', |
36 | /* Indexes below here don't have TLBs and are used only for AT system | 49 | + '*cluster-id': 'int', |
37 | * instructions or for the first stage of an S12 page table walk. | 50 | '*core-id': 'int', |
38 | */ | 51 | '*thread-id': 'int' |
39 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit { | 52 | } |
40 | ARMMMUIdxBit_MUser = 1 << 0, | 53 | diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c |
41 | ARMMMUIdxBit_MPriv = 1 << 1, | 54 | index XXXXXXX..XXXXXXX 100644 |
42 | ARMMMUIdxBit_MNegPri = 1 << 2, | 55 | --- a/hw/core/machine-hmp-cmds.c |
43 | + ARMMMUIdxBit_MSUser = 1 << 3, | 56 | +++ b/hw/core/machine-hmp-cmds.c |
44 | + ARMMMUIdxBit_MSPriv = 1 << 4, | 57 | @@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) |
45 | + ARMMMUIdxBit_MSNegPri = 1 << 5, | 58 | if (c->has_die_id) { |
46 | } ARMMMUIdxBit; | 59 | monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); |
47 | 60 | } | |
48 | #define MMU_USER_IDX 0 | 61 | + if (c->has_cluster_id) { |
49 | @@ -XXX,XX +XXX,XX @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | 62 | + monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n", |
50 | case ARM_MMU_IDX_A: | 63 | + c->cluster_id); |
51 | return mmu_idx & 3; | 64 | + } |
52 | case ARM_MMU_IDX_M: | 65 | if (c->has_core_id) { |
53 | - return mmu_idx == ARMMMUIdx_MUser ? 0 : 1; | 66 | monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); |
54 | + return (mmu_idx == ARMMMUIdx_MUser || mmu_idx == ARMMMUIdx_MSUser) | 67 | } |
55 | + ? 0 : 1; | 68 | diff --git a/hw/core/machine.c b/hw/core/machine.c |
56 | default: | 69 | index XXXXXXX..XXXXXXX 100644 |
57 | g_assert_not_reached(); | 70 | --- a/hw/core/machine.c |
58 | } | 71 | +++ b/hw/core/machine.c |
59 | @@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) | 72 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, |
60 | */ | 73 | return; |
61 | if ((env->v7m.exception > 0 && env->v7m.exception <= 3) | 74 | } |
62 | || env->v7m.faultmask) { | 75 | |
63 | - return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); | 76 | + if (props->has_cluster_id && !slot->props.has_cluster_id) { |
64 | + mmu_idx = ARMMMUIdx_MNegPri; | 77 | + error_setg(errp, "cluster-id is not supported"); |
78 | + return; | ||
65 | + } | 79 | + } |
66 | + | 80 | + |
67 | + if (env->v7m.secure) { | 81 | if (props->has_socket_id && !slot->props.has_socket_id) { |
68 | + mmu_idx += ARMMMUIdx_MSUser; | 82 | error_setg(errp, "socket-id is not supported"); |
83 | return; | ||
84 | @@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine, | ||
85 | continue; | ||
69 | } | 86 | } |
70 | 87 | ||
71 | return arm_to_core_mmu_idx(mmu_idx); | 88 | + if (props->has_cluster_id && |
72 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 89 | + props->cluster_id != slot->props.cluster_id) { |
73 | index XXXXXXX..XXXXXXX 100644 | 90 | + continue; |
74 | --- a/target/arm/helper.c | 91 | + } |
75 | +++ b/target/arm/helper.c | 92 | + |
76 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | 93 | if (props->has_die_id && props->die_id != slot->props.die_id) { |
77 | case ARMMMUIdx_MPriv: | 94 | continue; |
78 | case ARMMMUIdx_MNegPri: | 95 | } |
79 | case ARMMMUIdx_MUser: | 96 | @@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu) |
80 | + case ARMMMUIdx_MSPriv: | 97 | } |
81 | + case ARMMMUIdx_MSNegPri: | 98 | g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); |
82 | + case ARMMMUIdx_MSUser: | 99 | } |
83 | return 1; | 100 | + if (cpu->props.has_cluster_id) { |
84 | default: | 101 | + if (s->len) { |
85 | g_assert_not_reached(); | 102 | + g_string_append_printf(s, ", "); |
86 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | 103 | + } |
87 | case ARMMMUIdx_S1E3: | 104 | + g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); |
88 | case ARMMMUIdx_S1SE0: | 105 | + } |
89 | case ARMMMUIdx_S1SE1: | 106 | if (cpu->props.has_core_id) { |
90 | + case ARMMMUIdx_MSPriv: | 107 | if (s->len) { |
91 | + case ARMMMUIdx_MSNegPri: | 108 | g_string_append_printf(s, ", "); |
92 | + case ARMMMUIdx_MSUser: | ||
93 | return true; | ||
94 | default: | ||
95 | g_assert_not_reached(); | ||
96 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env, | ||
97 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { | ||
98 | case R_V7M_MPU_CTRL_ENABLE_MASK: | ||
99 | /* Enabled, but not for HardFault and NMI */ | ||
100 | - return mmu_idx == ARMMMUIdx_MNegPri; | ||
101 | + return mmu_idx == ARMMMUIdx_MNegPri || | ||
102 | + mmu_idx == ARMMMUIdx_MSNegPri; | ||
103 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: | ||
104 | /* Enabled for all cases */ | ||
105 | return false; | ||
106 | -- | 109 | -- |
107 | 2.7.4 | 110 | 2.25.1 |
108 | |||
109 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Gavin Shan <gshan@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | The CPU topology isn't enabled on arm/virt machine yet, but we're |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | going to do it in next patch. After the CPU topology is enabled by |
5 | Message-id: 20170905131149.10669-6-famz@redhat.com | 5 | next patch, "thread-id=1" becomes invalid because the CPU core is |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | preferred on arm/virt machine. It means these two CPUs have 0/1 |
7 | as their core IDs, but their thread IDs are all 0. It will trigger | ||
8 | test failure as the following message indicates: | ||
9 | |||
10 | [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR | ||
11 | 1.48s killed by signal 6 SIGABRT | ||
12 | >>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \ | ||
13 | QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \ | ||
14 | QTEST_QEMU_BINARY=./qemu-system-aarch64 \ | ||
15 | QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \ | ||
16 | /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k | ||
17 | ―――――――――――――――――――――――――――――――――――――――――――――― | ||
18 | stderr: | ||
19 | qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found | ||
20 | |||
21 | This fixes the issue by providing comprehensive SMP configurations | ||
22 | in aarch64_numa_cpu(). The SMP configurations aren't used before | ||
23 | the CPU topology is enabled in next patch. | ||
24 | |||
25 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
26 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
27 | Message-id: 20220503140304.855514-3-gshan@redhat.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 29 | --- |
9 | hw/net/xilinx_axienet.c | 16 ++++------------ | 30 | tests/qtest/numa-test.c | 3 ++- |
10 | 1 file changed, 4 insertions(+), 12 deletions(-) | 31 | 1 file changed, 2 insertions(+), 1 deletion(-) |
11 | 32 | ||
12 | diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c | 33 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c |
13 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/net/xilinx_axienet.c | 35 | --- a/tests/qtest/numa-test.c |
15 | +++ b/hw/net/xilinx_axienet.c | 36 | +++ b/tests/qtest/numa-test.c |
16 | @@ -XXX,XX +XXX,XX @@ static void xilinx_enet_init(Object *obj) | 37 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) |
17 | XilinxAXIEnet *s = XILINX_AXI_ENET(obj); | 38 | QTestState *qts; |
18 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 39 | g_autofree char *cli = NULL; |
19 | 40 | ||
20 | - object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, | 41 | - cli = make_cli(data, "-machine smp.cpus=2 " |
21 | - (Object **) &s->tx_data_dev, | 42 | + cli = make_cli(data, "-machine " |
22 | - qdev_prop_allow_set_link_before_realize, | 43 | + "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " |
23 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | 44 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " |
24 | - &error_abort); | 45 | "-numa cpu,node-id=1,thread-id=0 " |
25 | - object_property_add_link(obj, "axistream-control-connected", | 46 | "-numa cpu,node-id=0,thread-id=1"); |
26 | - TYPE_STREAM_SLAVE, | ||
27 | - (Object **) &s->tx_control_dev, | ||
28 | - qdev_prop_allow_set_link_before_realize, | ||
29 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
30 | - &error_abort); | ||
31 | - | ||
32 | object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), | ||
33 | TYPE_XILINX_AXI_ENET_DATA_STREAM); | ||
34 | object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), | ||
35 | @@ -XXX,XX +XXX,XX @@ static Property xilinx_enet_properties[] = { | ||
36 | DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), | ||
37 | DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), | ||
38 | DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), | ||
39 | + DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, | ||
40 | + tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), | ||
41 | + DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, | ||
42 | + tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), | ||
43 | DEFINE_PROP_END_OF_LIST(), | ||
44 | }; | ||
45 | |||
46 | -- | 47 | -- |
47 | 2.7.4 | 48 | 2.25.1 |
48 | 49 | ||
49 | 50 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Gavin Shan <gshan@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | Currently, the SMP configuration isn't considered when the CPU |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | topology is populated. In this case, it's impossible to provide |
5 | Message-id: 20170905131149.10669-3-famz@redhat.com | 5 | the default CPU-to-NUMA mapping or association based on the socket |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | ID of the given CPU. |
7 | |||
8 | This takes account of SMP configuration when the CPU topology | ||
9 | is populated. The die ID for the given CPU isn't assigned since | ||
10 | it's not supported on arm/virt machine. Besides, the used SMP | ||
11 | configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted | ||
12 | to avoid testing failure | ||
13 | |||
14 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
15 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
16 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
17 | Message-id: 20220503140304.855514-4-gshan@redhat.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 19 | --- |
9 | hw/arm/armv7m.c | 8 ++------ | 20 | hw/arm/virt.c | 15 ++++++++++++++- |
10 | 1 file changed, 2 insertions(+), 6 deletions(-) | 21 | 1 file changed, 14 insertions(+), 1 deletion(-) |
11 | 22 | ||
12 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 23 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
13 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/arm/armv7m.c | 25 | --- a/hw/arm/virt.c |
15 | +++ b/hw/arm/armv7m.c | 26 | +++ b/hw/arm/virt.c |
16 | @@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj) | 27 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) |
17 | 28 | int n; | |
18 | /* Can't init the cpu here, we don't yet know which model to use */ | 29 | unsigned int max_cpus = ms->smp.max_cpus; |
19 | 30 | VirtMachineState *vms = VIRT_MACHINE(ms); | |
20 | - object_property_add_link(obj, "memory", | 31 | + MachineClass *mc = MACHINE_GET_CLASS(vms); |
21 | - TYPE_MEMORY_REGION, | 32 | |
22 | - (Object **)&s->board_memory, | 33 | if (ms->possible_cpus) { |
23 | - qdev_prop_allow_set_link_before_realize, | 34 | assert(ms->possible_cpus->len == max_cpus); |
24 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | 35 | @@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) |
25 | - &error_abort); | 36 | ms->possible_cpus->cpus[n].type = ms->cpu_type; |
26 | memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX); | 37 | ms->possible_cpus->cpus[n].arch_id = |
27 | 38 | virt_cpu_mp_affinity(vms, n); | |
28 | object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC); | 39 | + |
29 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | 40 | + assert(!mc->smp_props.dies_supported); |
30 | 41 | + ms->possible_cpus->cpus[n].props.has_socket_id = true; | |
31 | static Property armv7m_properties[] = { | 42 | + ms->possible_cpus->cpus[n].props.socket_id = |
32 | DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model), | 43 | + n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); |
33 | + DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | 44 | + ms->possible_cpus->cpus[n].props.has_cluster_id = true; |
34 | + MemoryRegion *), | 45 | + ms->possible_cpus->cpus[n].props.cluster_id = |
35 | DEFINE_PROP_END_OF_LIST(), | 46 | + (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; |
36 | }; | 47 | + ms->possible_cpus->cpus[n].props.has_core_id = true; |
37 | 48 | + ms->possible_cpus->cpus[n].props.core_id = | |
49 | + (n / ms->smp.threads) % ms->smp.cores; | ||
50 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | ||
51 | - ms->possible_cpus->cpus[n].props.thread_id = n; | ||
52 | + ms->possible_cpus->cpus[n].props.thread_id = | ||
53 | + n % ms->smp.threads; | ||
54 | } | ||
55 | return ms->possible_cpus; | ||
56 | } | ||
38 | -- | 57 | -- |
39 | 2.7.4 | 58 | 2.25.1 |
40 | |||
41 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Gavin Shan <gshan@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | In aarch64_numa_cpu(), the CPU and NUMA association is something |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | like below. Two threads in the same core/cluster/socket are |
5 | Message-id: 20170905131149.10669-2-famz@redhat.com | 5 | associated with two individual NUMA nodes, which is unreal as |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Igor Mammedov mentioned. We don't expect the association to break |
7 | NUMA-to-socket boundary, which matches with the real world. | ||
8 | |||
9 | NUMA-node socket cluster core thread | ||
10 | ------------------------------------------ | ||
11 | 0 0 0 0 0 | ||
12 | 1 0 0 0 1 | ||
13 | |||
14 | This corrects the topology for CPUs and their association with | ||
15 | NUMA nodes. After this patch is applied, the CPU and NUMA | ||
16 | association becomes something like below, which looks real. | ||
17 | Besides, socket/cluster/core/thread IDs are all checked when | ||
18 | the NUMA node IDs are verified. It helps to check if the CPU | ||
19 | topology is properly populated or not. | ||
20 | |||
21 | NUMA-node socket cluster core thread | ||
22 | ------------------------------------------ | ||
23 | 0 1 0 0 0 | ||
24 | 1 0 0 0 0 | ||
25 | |||
26 | Suggested-by: Igor Mammedov <imammedo@redhat.com> | ||
27 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
28 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
29 | Message-id: 20220503140304.855514-5-gshan@redhat.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 31 | --- |
9 | hw/arm/armv7m.c | 8 ++------ | 32 | tests/qtest/numa-test.c | 18 ++++++++++++------ |
10 | 1 file changed, 2 insertions(+), 6 deletions(-) | 33 | 1 file changed, 12 insertions(+), 6 deletions(-) |
11 | 34 | ||
12 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 35 | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c |
13 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/arm/armv7m.c | 37 | --- a/tests/qtest/numa-test.c |
15 | +++ b/hw/arm/armv7m.c | 38 | +++ b/tests/qtest/numa-test.c |
16 | @@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj) | 39 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) |
17 | BitBandState *s = BITBAND(obj); | 40 | g_autofree char *cli = NULL; |
18 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | 41 | |
19 | 42 | cli = make_cli(data, "-machine " | |
20 | - object_property_add_link(obj, "source-memory", | 43 | - "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 " |
21 | - TYPE_MEMORY_REGION, | 44 | + "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 " |
22 | - (Object **)&s->source_memory, | 45 | "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " |
23 | - qdev_prop_allow_set_link_before_realize, | 46 | - "-numa cpu,node-id=1,thread-id=0 " |
24 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | 47 | - "-numa cpu,node-id=0,thread-id=1"); |
25 | - &error_abort); | 48 | + "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 " |
26 | memory_region_init_io(&s->iomem, obj, &bitband_ops, s, | 49 | + "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0"); |
27 | "bitband", 0x02000000); | 50 | qts = qtest_init(cli); |
28 | sysbus_init_mmio(dev, &s->iomem); | 51 | cpus = get_cpus(qts, &resp); |
29 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | 52 | g_assert(cpus); |
30 | 53 | ||
31 | static Property bitband_properties[] = { | 54 | while ((e = qlist_pop(cpus))) { |
32 | DEFINE_PROP_UINT32("base", BitBandState, base, 0), | 55 | QDict *cpu, *props; |
33 | + DEFINE_PROP_LINK("source-memory", BitBandState, source_memory, | 56 | - int64_t thread, node; |
34 | + TYPE_MEMORY_REGION, MemoryRegion *), | 57 | + int64_t socket, cluster, core, thread, node; |
35 | DEFINE_PROP_END_OF_LIST(), | 58 | |
36 | }; | 59 | cpu = qobject_to(QDict, e); |
37 | 60 | g_assert(qdict_haskey(cpu, "props")); | |
61 | @@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data) | ||
62 | |||
63 | g_assert(qdict_haskey(props, "node-id")); | ||
64 | node = qdict_get_int(props, "node-id"); | ||
65 | + g_assert(qdict_haskey(props, "socket-id")); | ||
66 | + socket = qdict_get_int(props, "socket-id"); | ||
67 | + g_assert(qdict_haskey(props, "cluster-id")); | ||
68 | + cluster = qdict_get_int(props, "cluster-id"); | ||
69 | + g_assert(qdict_haskey(props, "core-id")); | ||
70 | + core = qdict_get_int(props, "core-id"); | ||
71 | g_assert(qdict_haskey(props, "thread-id")); | ||
72 | thread = qdict_get_int(props, "thread-id"); | ||
73 | |||
74 | - if (thread == 0) { | ||
75 | + if (socket == 0 && cluster == 0 && core == 0 && thread == 0) { | ||
76 | g_assert_cmpint(node, ==, 1); | ||
77 | - } else if (thread == 1) { | ||
78 | + } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) { | ||
79 | g_assert_cmpint(node, ==, 0); | ||
80 | } else { | ||
81 | g_assert(false); | ||
38 | -- | 82 | -- |
39 | 2.7.4 | 83 | 2.25.1 |
40 | |||
41 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Gavin Shan <gshan@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | When CPU-to-NUMA association isn't explicitly provided by users, |
4 | Message-id: 20170905131149.10669-4-famz@redhat.com | 4 | the default one is given by mc->get_default_cpu_node_id(). However, |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | the CPU topology isn't fully considered in the default association |
6 | and this causes CPU topology broken warnings on booting Linux guest. | ||
7 | |||
8 | For example, the following warning messages are observed when the | ||
9 | Linux guest is booted with the following command lines. | ||
10 | |||
11 | /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ | ||
12 | -accel kvm -machine virt,gic-version=host \ | ||
13 | -cpu host \ | ||
14 | -smp 6,sockets=2,cores=3,threads=1 \ | ||
15 | -m 1024M,slots=16,maxmem=64G \ | ||
16 | -object memory-backend-ram,id=mem0,size=128M \ | ||
17 | -object memory-backend-ram,id=mem1,size=128M \ | ||
18 | -object memory-backend-ram,id=mem2,size=128M \ | ||
19 | -object memory-backend-ram,id=mem3,size=128M \ | ||
20 | -object memory-backend-ram,id=mem4,size=128M \ | ||
21 | -object memory-backend-ram,id=mem4,size=384M \ | ||
22 | -numa node,nodeid=0,memdev=mem0 \ | ||
23 | -numa node,nodeid=1,memdev=mem1 \ | ||
24 | -numa node,nodeid=2,memdev=mem2 \ | ||
25 | -numa node,nodeid=3,memdev=mem3 \ | ||
26 | -numa node,nodeid=4,memdev=mem4 \ | ||
27 | -numa node,nodeid=5,memdev=mem5 | ||
28 | : | ||
29 | alternatives: patching kernel code | ||
30 | BUG: arch topology borken | ||
31 | the CLS domain not a subset of the MC domain | ||
32 | <the above error log repeats> | ||
33 | BUG: arch topology borken | ||
34 | the DIE domain not a subset of the NODE domain | ||
35 | |||
36 | With current implementation of mc->get_default_cpu_node_id(), | ||
37 | CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately. | ||
38 | That's incorrect because CPU#0/1/2 should be associated with same | ||
39 | NUMA node because they're seated in same socket. | ||
40 | |||
41 | This fixes the issue by considering the socket ID when the default | ||
42 | CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids(). | ||
43 | With this applied, no more CPU topology broken warnings are seen | ||
44 | from the Linux guest. The 6 CPUs are associated with NODE#0/1, but | ||
45 | there are no CPUs associated with NODE#2/3/4/5. | ||
46 | |||
47 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
48 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
49 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
50 | Message-id: 20220503140304.855514-6-gshan@redhat.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 51 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 52 | --- |
8 | hw/intc/arm_gicv3_its_kvm.c | 19 +++++++------------ | 53 | hw/arm/virt.c | 4 +++- |
9 | 1 file changed, 7 insertions(+), 12 deletions(-) | 54 | 1 file changed, 3 insertions(+), 1 deletion(-) |
10 | 55 | ||
11 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | 56 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
12 | index XXXXXXX..XXXXXXX 100644 | 57 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/intc/arm_gicv3_its_kvm.c | 58 | --- a/hw/arm/virt.c |
14 | +++ b/hw/intc/arm_gicv3_its_kvm.c | 59 | +++ b/hw/arm/virt.c |
15 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | 60 | @@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) |
16 | qemu_add_vm_change_state_handler(vm_change_state_handler, s); | 61 | |
62 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) | ||
63 | { | ||
64 | - return idx % ms->numa_state->num_nodes; | ||
65 | + int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; | ||
66 | + | ||
67 | + return socket_id % ms->numa_state->num_nodes; | ||
17 | } | 68 | } |
18 | 69 | ||
19 | -static void kvm_arm_its_init(Object *obj) | 70 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) |
20 | -{ | ||
21 | - GICv3ITSState *s = KVM_ARM_ITS(obj); | ||
22 | - | ||
23 | - object_property_add_link(obj, "parent-gicv3", | ||
24 | - "kvm-arm-gicv3", (Object **)&s->gicv3, | ||
25 | - object_property_allow_set_link, | ||
26 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
27 | - &error_abort); | ||
28 | -} | ||
29 | - | ||
30 | /** | ||
31 | * kvm_arm_its_pre_save - handles the saving of ITS registers. | ||
32 | * ITS tables are flushed into guest RAM separately and earlier, | ||
33 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s) | ||
34 | GITS_CTLR, &s->ctlr, true, &error_abort); | ||
35 | } | ||
36 | |||
37 | +static Property kvm_arm_its_props[] = { | ||
38 | + DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3", | ||
39 | + GICv3State *), | ||
40 | + DEFINE_PROP_END_OF_LIST(), | ||
41 | +}; | ||
42 | + | ||
43 | static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | ||
44 | { | ||
45 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
46 | GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); | ||
47 | |||
48 | dc->realize = kvm_arm_its_realize; | ||
49 | + dc->props = kvm_arm_its_props; | ||
50 | icc->send_msi = kvm_its_send_msi; | ||
51 | icc->pre_save = kvm_arm_its_pre_save; | ||
52 | icc->post_load = kvm_arm_its_post_load; | ||
53 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo kvm_arm_its_info = { | ||
54 | .name = TYPE_KVM_ARM_ITS, | ||
55 | .parent = TYPE_ARM_GICV3_ITS_COMMON, | ||
56 | .instance_size = sizeof(GICv3ITSState), | ||
57 | - .instance_init = kvm_arm_its_init, | ||
58 | .class_init = kvm_arm_its_class_init, | ||
59 | }; | ||
60 | |||
61 | -- | 71 | -- |
62 | 2.7.4 | 72 | 2.25.1 |
63 | |||
64 | diff view generated by jsdifflib |
1 | As part of ARMv8M, we need to add support for the PMSAv8 MPU | 1 | From: Gavin Shan <gshan@redhat.com> |
---|---|---|---|
2 | architecture. | ||
3 | 2 | ||
4 | PMSAv8 differs from PMSAv7 both in register/data layout (for instance | 3 | When the PPTT table is built, the CPU topology is re-calculated, but |
5 | using base and limit registers rather than base and size) and also in | 4 | it's unecessary because the CPU topology has been populated in |
6 | behaviour (for example it does not have subregions); rather than | 5 | virt_possible_cpu_arch_ids() on arm/virt machine. |
7 | trying to wedge it into the existing PMSAv7 code and data structures, | ||
8 | we define separate ones. | ||
9 | 6 | ||
10 | This commit adds the data structures which hold the state for a | 7 | This reworks build_pptt() to avoid by reusing the existing IDs in |
11 | PMSAv8 MPU and the register interface to it. The implementation of | 8 | ms->possible_cpus. Currently, the only user of build_pptt() is |
12 | the MPU behaviour will be added in a subsequent commit. | 9 | arm/virt machine. |
13 | 10 | ||
11 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
12 | Tested-by: Yanan Wang <wangyanan55@huawei.com> | ||
13 | Reviewed-by: Yanan Wang <wangyanan55@huawei.com> | ||
14 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
15 | Acked-by: Michael S. Tsirkin <mst@redhat.com> | ||
16 | Message-id: 20220503140304.855514-7-gshan@redhat.com | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Message-id: 1503414539-28762-2-git-send-email-peter.maydell@linaro.org | ||
17 | --- | 18 | --- |
18 | target/arm/cpu.h | 13 ++++++ | 19 | hw/acpi/aml-build.c | 111 +++++++++++++++++++------------------------- |
19 | hw/intc/armv7m_nvic.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++---- | 20 | 1 file changed, 48 insertions(+), 63 deletions(-) |
20 | target/arm/cpu.c | 36 ++++++++++----- | ||
21 | target/arm/machine.c | 29 +++++++++++- | ||
22 | 4 files changed, 180 insertions(+), 20 deletions(-) | ||
23 | 21 | ||
24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 22 | diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c |
25 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpu.h | 24 | --- a/hw/acpi/aml-build.c |
27 | +++ b/target/arm/cpu.h | 25 | +++ b/hw/acpi/aml-build.c |
28 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 26 | @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, |
29 | uint32_t rnr; | 27 | const char *oem_id, const char *oem_table_id) |
30 | } pmsav7; | 28 | { |
31 | 29 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
32 | + /* PMSAv8 MPU */ | 30 | - GQueue *list = g_queue_new(); |
33 | + struct { | 31 | - guint pptt_start = table_data->len; |
34 | + /* The PMSAv8 implementation also shares some PMSAv7 config | 32 | - guint parent_offset; |
35 | + * and state: | 33 | - guint length, i; |
36 | + * pmsav7.rnr (region number register) | 34 | - int uid = 0; |
37 | + * pmsav7_dregion (number of configured regions) | 35 | - int socket; |
38 | + */ | 36 | + CPUArchIdList *cpus = ms->possible_cpus; |
39 | + uint32_t *rbar; | 37 | + int64_t socket_id = -1, cluster_id = -1, core_id = -1; |
40 | + uint32_t *rlar; | 38 | + uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0; |
41 | + uint32_t mair0; | 39 | + uint32_t pptt_start = table_data->len; |
42 | + uint32_t mair1; | 40 | + int n; |
43 | + } pmsav8; | 41 | AcpiTable table = { .sig = "PPTT", .rev = 2, |
44 | + | 42 | .oem_id = oem_id, .oem_table_id = oem_table_id }; |
45 | void *nvic; | 43 | |
46 | const struct arm_boot_info *boot_info; | 44 | acpi_table_begin(&table, table_data); |
47 | /* Store GICv3CPUState to access from this struct */ | 45 | |
48 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 46 | - for (socket = 0; socket < ms->smp.sockets; socket++) { |
49 | index XXXXXXX..XXXXXXX 100644 | 47 | - g_queue_push_tail(list, |
50 | --- a/hw/intc/armv7m_nvic.c | 48 | - GUINT_TO_POINTER(table_data->len - pptt_start)); |
51 | +++ b/hw/intc/armv7m_nvic.c | 49 | - build_processor_hierarchy_node( |
52 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) | 50 | - table_data, |
53 | { | 51 | - /* |
54 | int region = cpu->env.pmsav7.rnr; | 52 | - * Physical package - represents the boundary |
55 | 53 | - * of a physical package | |
56 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | 54 | - */ |
57 | + /* PMSAv8M handling of the aliases is different from v7M: | 55 | - (1 << 0), |
58 | + * aliases A1, A2, A3 override the low two bits of the region | 56 | - 0, socket, NULL, 0); |
59 | + * number in MPU_RNR, and there is no 'region' field in the | 57 | - } |
60 | + * RBAR register. | 58 | - |
61 | + */ | 59 | - if (mc->smp_props.clusters_supported) { |
62 | + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | 60 | - length = g_queue_get_length(list); |
63 | + if (aliasno) { | 61 | - for (i = 0; i < length; i++) { |
64 | + region = deposit32(region, 0, 2, aliasno); | 62 | - int cluster; |
63 | - | ||
64 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
65 | - for (cluster = 0; cluster < ms->smp.clusters; cluster++) { | ||
66 | - g_queue_push_tail(list, | ||
67 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
68 | - build_processor_hierarchy_node( | ||
69 | - table_data, | ||
70 | - (0 << 0), /* not a physical package */ | ||
71 | - parent_offset, cluster, NULL, 0); | ||
72 | - } | ||
73 | + /* | ||
74 | + * This works with the assumption that cpus[n].props.*_id has been | ||
75 | + * sorted from top to down levels in mc->possible_cpu_arch_ids(). | ||
76 | + * Otherwise, the unexpected and duplicated containers will be | ||
77 | + * created. | ||
78 | + */ | ||
79 | + for (n = 0; n < cpus->len; n++) { | ||
80 | + if (cpus->cpus[n].props.socket_id != socket_id) { | ||
81 | + assert(cpus->cpus[n].props.socket_id > socket_id); | ||
82 | + socket_id = cpus->cpus[n].props.socket_id; | ||
83 | + cluster_id = -1; | ||
84 | + core_id = -1; | ||
85 | + socket_offset = table_data->len - pptt_start; | ||
86 | + build_processor_hierarchy_node(table_data, | ||
87 | + (1 << 0), /* Physical package */ | ||
88 | + 0, socket_id, NULL, 0); | ||
89 | } | ||
90 | - } | ||
91 | |||
92 | - length = g_queue_get_length(list); | ||
93 | - for (i = 0; i < length; i++) { | ||
94 | - int core; | ||
95 | - | ||
96 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); | ||
97 | - for (core = 0; core < ms->smp.cores; core++) { | ||
98 | - if (ms->smp.threads > 1) { | ||
99 | - g_queue_push_tail(list, | ||
100 | - GUINT_TO_POINTER(table_data->len - pptt_start)); | ||
101 | - build_processor_hierarchy_node( | ||
102 | - table_data, | ||
103 | - (0 << 0), /* not a physical package */ | ||
104 | - parent_offset, core, NULL, 0); | ||
105 | - } else { | ||
106 | - build_processor_hierarchy_node( | ||
107 | - table_data, | ||
108 | - (1 << 1) | /* ACPI Processor ID valid */ | ||
109 | - (1 << 3), /* Node is a Leaf */ | ||
110 | - parent_offset, uid++, NULL, 0); | ||
111 | + if (mc->smp_props.clusters_supported) { | ||
112 | + if (cpus->cpus[n].props.cluster_id != cluster_id) { | ||
113 | + assert(cpus->cpus[n].props.cluster_id > cluster_id); | ||
114 | + cluster_id = cpus->cpus[n].props.cluster_id; | ||
115 | + core_id = -1; | ||
116 | + cluster_offset = table_data->len - pptt_start; | ||
117 | + build_processor_hierarchy_node(table_data, | ||
118 | + (0 << 0), /* Not a physical package */ | ||
119 | + socket_offset, cluster_id, NULL, 0); | ||
120 | } | ||
121 | + } else { | ||
122 | + cluster_offset = socket_offset; | ||
123 | } | ||
124 | - } | ||
125 | |||
126 | - length = g_queue_get_length(list); | ||
127 | - for (i = 0; i < length; i++) { | ||
128 | - int thread; | ||
129 | + if (ms->smp.threads == 1) { | ||
130 | + build_processor_hierarchy_node(table_data, | ||
131 | + (1 << 1) | /* ACPI Processor ID valid */ | ||
132 | + (1 << 3), /* Node is a Leaf */ | ||
133 | + cluster_offset, n, NULL, 0); | ||
134 | + } else { | ||
135 | + if (cpus->cpus[n].props.core_id != core_id) { | ||
136 | + assert(cpus->cpus[n].props.core_id > core_id); | ||
137 | + core_id = cpus->cpus[n].props.core_id; | ||
138 | + core_offset = table_data->len - pptt_start; | ||
139 | + build_processor_hierarchy_node(table_data, | ||
140 | + (0 << 0), /* Not a physical package */ | ||
141 | + cluster_offset, core_id, NULL, 0); | ||
65 | + } | 142 | + } |
66 | + if (region >= cpu->pmsav7_dregion) { | 143 | |
67 | + return 0; | 144 | - parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); |
68 | + } | 145 | - for (thread = 0; thread < ms->smp.threads; thread++) { |
69 | + return cpu->env.pmsav8.rbar[region]; | 146 | - build_processor_hierarchy_node( |
70 | + } | 147 | - table_data, |
71 | + | 148 | + build_processor_hierarchy_node(table_data, |
72 | if (region >= cpu->pmsav7_dregion) { | 149 | (1 << 1) | /* ACPI Processor ID valid */ |
73 | return 0; | 150 | (1 << 2) | /* Processor is a Thread */ |
74 | } | 151 | (1 << 3), /* Node is a Leaf */ |
75 | return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); | 152 | - parent_offset, uid++, NULL, 0); |
76 | } | 153 | + core_offset, n, NULL, 0); |
77 | - case 0xda0: /* MPU_RASR */ | ||
78 | - case 0xda8: /* MPU_RASR_A1 */ | ||
79 | - case 0xdb0: /* MPU_RASR_A2 */ | ||
80 | - case 0xdb8: /* MPU_RASR_A3 */ | ||
81 | + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ | ||
82 | + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ | ||
83 | + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | ||
84 | + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | ||
85 | { | ||
86 | int region = cpu->env.pmsav7.rnr; | ||
87 | |||
88 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
89 | + /* PMSAv8M handling of the aliases is different from v7M: | ||
90 | + * aliases A1, A2, A3 override the low two bits of the region | ||
91 | + * number in MPU_RNR. | ||
92 | + */ | ||
93 | + int aliasno = (offset - 0xda0) / 8; /* 0..3 */ | ||
94 | + if (aliasno) { | ||
95 | + region = deposit32(region, 0, 2, aliasno); | ||
96 | + } | ||
97 | + if (region >= cpu->pmsav7_dregion) { | ||
98 | + return 0; | ||
99 | + } | ||
100 | + return cpu->env.pmsav8.rlar[region]; | ||
101 | + } | ||
102 | + | ||
103 | if (region >= cpu->pmsav7_dregion) { | ||
104 | return 0; | ||
105 | } | ||
106 | return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | | ||
107 | (cpu->env.pmsav7.drsr[region] & 0xffff); | ||
108 | } | ||
109 | + case 0xdc0: /* MPU_MAIR0 */ | ||
110 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
111 | + goto bad_offset; | ||
112 | + } | ||
113 | + return cpu->env.pmsav8.mair0; | ||
114 | + case 0xdc4: /* MPU_MAIR1 */ | ||
115 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
116 | + goto bad_offset; | ||
117 | + } | ||
118 | + return cpu->env.pmsav8.mair1; | ||
119 | default: | ||
120 | + bad_offset: | ||
121 | qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); | ||
122 | return 0; | ||
123 | } | ||
124 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
125 | { | ||
126 | int region; | ||
127 | |||
128 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
129 | + /* PMSAv8M handling of the aliases is different from v7M: | ||
130 | + * aliases A1, A2, A3 override the low two bits of the region | ||
131 | + * number in MPU_RNR, and there is no 'region' field in the | ||
132 | + * RBAR register. | ||
133 | + */ | ||
134 | + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | ||
135 | + | ||
136 | + region = cpu->env.pmsav7.rnr; | ||
137 | + if (aliasno) { | ||
138 | + region = deposit32(region, 0, 2, aliasno); | ||
139 | + } | ||
140 | + if (region >= cpu->pmsav7_dregion) { | ||
141 | + return; | ||
142 | + } | ||
143 | + cpu->env.pmsav8.rbar[region] = value; | ||
144 | + tlb_flush(CPU(cpu)); | ||
145 | + return; | ||
146 | + } | ||
147 | + | ||
148 | if (value & (1 << 4)) { | ||
149 | /* VALID bit means use the region number specified in this | ||
150 | * value and also update MPU_RNR.REGION with that value. | ||
151 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
152 | tlb_flush(CPU(cpu)); | ||
153 | break; | ||
154 | } | ||
155 | - case 0xda0: /* MPU_RASR */ | ||
156 | - case 0xda8: /* MPU_RASR_A1 */ | ||
157 | - case 0xdb0: /* MPU_RASR_A2 */ | ||
158 | - case 0xdb8: /* MPU_RASR_A3 */ | ||
159 | + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ | ||
160 | + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ | ||
161 | + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | ||
162 | + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | ||
163 | { | ||
164 | int region = cpu->env.pmsav7.rnr; | ||
165 | |||
166 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
167 | + /* PMSAv8M handling of the aliases is different from v7M: | ||
168 | + * aliases A1, A2, A3 override the low two bits of the region | ||
169 | + * number in MPU_RNR. | ||
170 | + */ | ||
171 | + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | ||
172 | + | ||
173 | + region = cpu->env.pmsav7.rnr; | ||
174 | + if (aliasno) { | ||
175 | + region = deposit32(region, 0, 2, aliasno); | ||
176 | + } | ||
177 | + if (region >= cpu->pmsav7_dregion) { | ||
178 | + return; | ||
179 | + } | ||
180 | + cpu->env.pmsav8.rlar[region] = value; | ||
181 | + tlb_flush(CPU(cpu)); | ||
182 | + return; | ||
183 | + } | ||
184 | + | ||
185 | if (region >= cpu->pmsav7_dregion) { | ||
186 | return; | ||
187 | } | ||
188 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
189 | tlb_flush(CPU(cpu)); | ||
190 | break; | ||
191 | } | ||
192 | + case 0xdc0: /* MPU_MAIR0 */ | ||
193 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
194 | + goto bad_offset; | ||
195 | + } | ||
196 | + if (cpu->pmsav7_dregion) { | ||
197 | + /* Register is RES0 if no MPU regions are implemented */ | ||
198 | + cpu->env.pmsav8.mair0 = value; | ||
199 | + } | ||
200 | + /* We don't need to do anything else because memory attributes | ||
201 | + * only affect cacheability, and we don't implement caching. | ||
202 | + */ | ||
203 | + break; | ||
204 | + case 0xdc4: /* MPU_MAIR1 */ | ||
205 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
206 | + goto bad_offset; | ||
207 | + } | ||
208 | + if (cpu->pmsav7_dregion) { | ||
209 | + /* Register is RES0 if no MPU regions are implemented */ | ||
210 | + cpu->env.pmsav8.mair1 = value; | ||
211 | + } | ||
212 | + /* We don't need to do anything else because memory attributes | ||
213 | + * only affect cacheability, and we don't implement caching. | ||
214 | + */ | ||
215 | + break; | ||
216 | case 0xf00: /* Software Triggered Interrupt Register */ | ||
217 | { | ||
218 | int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; | ||
219 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
220 | break; | ||
221 | } | ||
222 | default: | ||
223 | + bad_offset: | ||
224 | qemu_log_mask(LOG_GUEST_ERROR, | ||
225 | "NVIC: Bad write offset 0x%x\n", offset); | ||
226 | } | ||
227 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
228 | index XXXXXXX..XXXXXXX 100644 | ||
229 | --- a/target/arm/cpu.c | ||
230 | +++ b/target/arm/cpu.c | ||
231 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
232 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | ||
233 | #endif | ||
234 | |||
235 | - if (arm_feature(env, ARM_FEATURE_PMSA) && | ||
236 | - arm_feature(env, ARM_FEATURE_V7)) { | ||
237 | + if (arm_feature(env, ARM_FEATURE_PMSA)) { | ||
238 | if (cpu->pmsav7_dregion > 0) { | ||
239 | - memset(env->pmsav7.drbar, 0, | ||
240 | - sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | ||
241 | - memset(env->pmsav7.drsr, 0, | ||
242 | - sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | ||
243 | - memset(env->pmsav7.dracr, 0, | ||
244 | - sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | ||
245 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
246 | + memset(env->pmsav8.rbar, 0, | ||
247 | + sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); | ||
248 | + memset(env->pmsav8.rlar, 0, | ||
249 | + sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); | ||
250 | + } else if (arm_feature(env, ARM_FEATURE_V7)) { | ||
251 | + memset(env->pmsav7.drbar, 0, | ||
252 | + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | ||
253 | + memset(env->pmsav7.drsr, 0, | ||
254 | + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | ||
255 | + memset(env->pmsav7.dracr, 0, | ||
256 | + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | ||
257 | + } | ||
258 | } | ||
259 | env->pmsav7.rnr = 0; | ||
260 | + env->pmsav8.mair0 = 0; | ||
261 | + env->pmsav8.mair1 = 0; | ||
262 | } | ||
263 | |||
264 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | ||
265 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
266 | } | ||
267 | |||
268 | if (nr) { | ||
269 | - env->pmsav7.drbar = g_new0(uint32_t, nr); | ||
270 | - env->pmsav7.drsr = g_new0(uint32_t, nr); | ||
271 | - env->pmsav7.dracr = g_new0(uint32_t, nr); | ||
272 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
273 | + /* PMSAv8 */ | ||
274 | + env->pmsav8.rbar = g_new0(uint32_t, nr); | ||
275 | + env->pmsav8.rlar = g_new0(uint32_t, nr); | ||
276 | + } else { | ||
277 | + env->pmsav7.drbar = g_new0(uint32_t, nr); | ||
278 | + env->pmsav7.drsr = g_new0(uint32_t, nr); | ||
279 | + env->pmsav7.dracr = g_new0(uint32_t, nr); | ||
280 | + } | ||
281 | } | 154 | } |
282 | } | 155 | } |
283 | 156 | ||
284 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 157 | - g_queue_free(list); |
285 | index XXXXXXX..XXXXXXX 100644 | 158 | acpi_table_end(linker, &table); |
286 | --- a/target/arm/machine.c | ||
287 | +++ b/target/arm/machine.c | ||
288 | @@ -XXX,XX +XXX,XX @@ static bool pmsav7_needed(void *opaque) | ||
289 | CPUARMState *env = &cpu->env; | ||
290 | |||
291 | return arm_feature(env, ARM_FEATURE_PMSA) && | ||
292 | - arm_feature(env, ARM_FEATURE_V7); | ||
293 | + arm_feature(env, ARM_FEATURE_V7) && | ||
294 | + !arm_feature(env, ARM_FEATURE_V8); | ||
295 | } | 159 | } |
296 | 160 | ||
297 | static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) | ||
298 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav7_rnr = { | ||
299 | } | ||
300 | }; | ||
301 | |||
302 | +static bool pmsav8_needed(void *opaque) | ||
303 | +{ | ||
304 | + ARMCPU *cpu = opaque; | ||
305 | + CPUARMState *env = &cpu->env; | ||
306 | + | ||
307 | + return arm_feature(env, ARM_FEATURE_PMSA) && | ||
308 | + arm_feature(env, ARM_FEATURE_V8); | ||
309 | +} | ||
310 | + | ||
311 | +static const VMStateDescription vmstate_pmsav8 = { | ||
312 | + .name = "cpu/pmsav8", | ||
313 | + .version_id = 1, | ||
314 | + .minimum_version_id = 1, | ||
315 | + .needed = pmsav8_needed, | ||
316 | + .fields = (VMStateField[]) { | ||
317 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, | ||
318 | + vmstate_info_uint32, uint32_t), | ||
319 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, | ||
320 | + vmstate_info_uint32, uint32_t), | ||
321 | + VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), | ||
322 | + VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), | ||
323 | + VMSTATE_END_OF_LIST() | ||
324 | + } | ||
325 | +}; | ||
326 | + | ||
327 | static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | ||
328 | VMStateField *field) | ||
329 | { | ||
330 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = { | ||
331 | */ | ||
332 | &vmstate_pmsav7_rnr, | ||
333 | &vmstate_pmsav7, | ||
334 | + &vmstate_pmsav8, | ||
335 | NULL | ||
336 | } | ||
337 | }; | ||
338 | -- | 161 | -- |
339 | 2.7.4 | 162 | 2.25.1 |
340 | |||
341 | diff view generated by jsdifflib |