1 | Second ARM pull request of this week; this one has my next | 1 | The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df: |
---|---|---|---|
2 | set of v8M patches and a handful of more minor stuff from | ||
3 | other people. | ||
4 | 2 | ||
5 | thanks | 3 | Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100) |
6 | -- PMM | ||
7 | 4 | ||
8 | The following changes since commit 8ee5f9b3ecc94e3eb7a8235f4b2c3ec9024807f6: | 5 | are available in the Git repository at: |
9 | 6 | ||
10 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2017-09-07 10:45:18 +0100) | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702 |
11 | 8 | ||
12 | are available in the git repository at: | 9 | for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8: |
13 | 10 | ||
14 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170907 | 11 | target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100) |
15 | |||
16 | for you to fetch changes up to c99a55d38dd5b5131f3fcbbaf41828a09ee62544: | ||
17 | |||
18 | target/arm: Add Jazelle feature (2017-09-07 13:54:55 +0100) | ||
19 | 12 | ||
20 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
21 | target-arm: | 14 | target-arm queue: |
22 | * cleanups converting to DEFINE_PROP_LINK | 15 | * more MVE instructions |
23 | * allwinner-a10: mark as not user-creatable | 16 | * hw/gpio/gpio_pwr: use shutdown function for reboot |
24 | * initial patches working towards ARMv8M support | 17 | * target/arm: Check NaN mode before silencing NaN |
25 | * implement generating aborts on memory transaction failures | 18 | * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine |
26 | * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later | 19 | * hw/arm: Add basic power management to raspi. |
20 | * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc | ||
27 | 21 | ||
28 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
29 | Fam Zheng (6): | 23 | Joe Komlodi (1): |
30 | armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK | 24 | target/arm: Check NaN mode before silencing NaN |
31 | armv7m: Convert armv7m.memory to DEFINE_PROP_LINK | ||
32 | gicv3: Convert to DEFINE_PROP_LINK | ||
33 | xlnx_zynqmp: Convert to DEFINE_PROP_LINK | ||
34 | xilinx_axienet: Convert to DEFINE_PROP_LINK | ||
35 | xilinx_axidma: Convert to DEFINE_PROP_LINK | ||
36 | 25 | ||
37 | Peter Maydell (23): | 26 | Maxim Uvarov (1): |
38 | target/arm: Implement ARMv8M's PMSAv8 registers | 27 | hw/gpio/gpio_pwr: use shutdown function for reboot |
39 | target/arm: Implement new PMSAv8 behaviour | ||
40 | target/arm: Add state field, feature bit and migration for v8M secure state | ||
41 | target/arm: Register second AddressSpace for secure v8M CPUs | ||
42 | target/arm: Add MMU indexes for secure v8M | ||
43 | target/arm: Make BASEPRI register banked for v8M | ||
44 | target/arm: Make PRIMASK register banked for v8M | ||
45 | target/arm: Make FAULTMASK register banked for v8M | ||
46 | target/arm: Make CONTROL register banked for v8M | ||
47 | nvic: Add NS alias SCS region | ||
48 | target/arm: Make VTOR register banked for v8M | ||
49 | target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M | ||
50 | target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M | ||
51 | target/arm: Make MPU_RNR register banked for v8M | ||
52 | target/arm: Make MPU_CTRL register banked for v8M | ||
53 | target/arm: Make CCR register banked for v8M | ||
54 | target/arm: Make MMFAR banked for v8M | ||
55 | target/arm: Make CFSR register banked for v8M | ||
56 | target/arm: Move regime_is_secure() to target/arm/internals.h | ||
57 | target/arm: Implement BXNS, and banked stack pointers | ||
58 | boards.h: Define new flag ignore_memory_transaction_failures | ||
59 | hw/arm: Set ignore_memory_transaction_failures for most ARM boards | ||
60 | target/arm: Implement new do_transaction_failed hook | ||
61 | 28 | ||
62 | Portia Stephens (1): | 29 | Nolan Leake (1): |
63 | target/arm: Add Jazelle feature | 30 | hw/arm: Add basic power management to raspi. |
64 | 31 | ||
65 | Thomas Huth (1): | 32 | Patrick Venture (2): |
66 | hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false | 33 | docs/system/arm: Add quanta-q7l1-bmc reference |
34 | docs/system/arm: Add quanta-gbs-bmc reference | ||
67 | 35 | ||
68 | include/hw/boards.h | 11 ++ | 36 | Peter Maydell (18): |
69 | include/hw/intc/armv7m_nvic.h | 1 + | 37 | target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation |
70 | include/qom/cpu.h | 7 +- | 38 | target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH |
71 | target/arm/cpu.h | 101 ++++++++++++-- | 39 | target/arm: Make asimd_imm_const() public |
72 | target/arm/helper.h | 2 + | 40 | target/arm: Use asimd_imm_const for A64 decode |
73 | target/arm/internals.h | 36 +++++ | 41 | target/arm: Use dup_const() instead of bitfield_replicate() |
74 | target/arm/translate.h | 1 + | 42 | target/arm: Implement MVE logical immediate insns |
75 | hw/arm/allwinner-a10.c | 2 + | 43 | target/arm: Implement MVE vector shift left by immediate insns |
76 | hw/arm/armv7m.c | 16 +-- | 44 | target/arm: Implement MVE vector shift right by immediate insns |
77 | hw/arm/aspeed.c | 3 + | 45 | target/arm: Implement MVE VSHLL |
78 | hw/arm/collie.c | 1 + | 46 | target/arm: Implement MVE VSRI, VSLI |
79 | hw/arm/cubieboard.c | 1 + | 47 | target/arm: Implement MVE VSHRN, VRSHRN |
80 | hw/arm/digic_boards.c | 1 + | 48 | target/arm: Implement MVE saturating narrowing shifts |
81 | hw/arm/exynos4_boards.c | 2 + | 49 | target/arm: Implement MVE VSHLC |
82 | hw/arm/gumstix.c | 2 + | 50 | target/arm: Implement MVE VADDLV |
83 | hw/arm/highbank.c | 2 + | 51 | target/arm: Implement MVE long shifts by immediate |
84 | hw/arm/imx25_pdk.c | 1 + | 52 | target/arm: Implement MVE long shifts by register |
85 | hw/arm/integratorcp.c | 1 + | 53 | target/arm: Implement MVE shifts by immediate |
86 | hw/arm/kzm.c | 1 + | 54 | target/arm: Implement MVE shifts by register |
87 | hw/arm/mainstone.c | 1 + | ||
88 | hw/arm/musicpal.c | 1 + | ||
89 | hw/arm/netduino2.c | 1 + | ||
90 | hw/arm/nseries.c | 2 + | ||
91 | hw/arm/omap_sx1.c | 2 + | ||
92 | hw/arm/palm.c | 1 + | ||
93 | hw/arm/raspi.c | 1 + | ||
94 | hw/arm/realview.c | 4 + | ||
95 | hw/arm/sabrelite.c | 1 + | ||
96 | hw/arm/spitz.c | 4 + | ||
97 | hw/arm/stellaris.c | 2 + | ||
98 | hw/arm/tosa.c | 1 + | ||
99 | hw/arm/versatilepb.c | 2 + | ||
100 | hw/arm/vexpress.c | 1 + | ||
101 | hw/arm/xilinx_zynq.c | 1 + | ||
102 | hw/arm/xlnx-ep108.c | 2 + | ||
103 | hw/arm/xlnx-zynqmp.c | 7 +- | ||
104 | hw/arm/z2.c | 1 + | ||
105 | hw/dma/xilinx_axidma.c | 16 +-- | ||
106 | hw/intc/arm_gicv3_its_kvm.c | 19 +-- | ||
107 | hw/intc/armv7m_nvic.c | 291 ++++++++++++++++++++++++++++++++------ | ||
108 | hw/net/xilinx_axienet.c | 16 +-- | ||
109 | qom/cpu.c | 16 +++ | ||
110 | target/arm/cpu.c | 88 +++++++++--- | ||
111 | target/arm/helper.c | 315 +++++++++++++++++++++++++++++++++--------- | ||
112 | target/arm/machine.c | 105 ++++++++++++-- | ||
113 | target/arm/op_helper.c | 43 ++++++ | ||
114 | target/arm/translate.c | 54 +++++++- | ||
115 | scripts/device-crash-test | 1 - | ||
116 | 48 files changed, 978 insertions(+), 213 deletions(-) | ||
117 | 55 | ||
56 | Philippe Mathieu-Daudé (1): | ||
57 | tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine | ||
58 | |||
59 | docs/system/arm/aspeed.rst | 1 + | ||
60 | docs/system/arm/nuvoton.rst | 5 +- | ||
61 | include/hw/arm/bcm2835_peripherals.h | 3 +- | ||
62 | include/hw/misc/bcm2835_powermgt.h | 29 ++ | ||
63 | target/arm/helper-mve.h | 108 +++++++ | ||
64 | target/arm/translate.h | 41 +++ | ||
65 | target/arm/mve.decode | 177 ++++++++++- | ||
66 | target/arm/t32.decode | 71 ++++- | ||
67 | hw/arm/bcm2835_peripherals.c | 13 +- | ||
68 | hw/gpio/gpio_pwr.c | 2 +- | ||
69 | hw/misc/bcm2835_powermgt.c | 160 ++++++++++ | ||
70 | target/arm/helper-a64.c | 12 +- | ||
71 | target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++-- | ||
72 | target/arm/translate-a64.c | 86 +----- | ||
73 | target/arm/translate-mve.c | 261 +++++++++++++++- | ||
74 | target/arm/translate-neon.c | 81 ----- | ||
75 | target/arm/translate.c | 327 +++++++++++++++++++- | ||
76 | target/arm/vfp_helper.c | 24 +- | ||
77 | hw/misc/meson.build | 1 + | ||
78 | tests/acceptance/boot_linux_console.py | 43 +++ | ||
79 | 20 files changed, 1760 insertions(+), 209 deletions(-) | ||
80 | create mode 100644 include/hw/misc/bcm2835_powermgt.h | ||
81 | create mode 100644 hw/misc/bcm2835_powermgt.c | ||
82 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Fam Zheng <famz@redhat.com> | ||
2 | 1 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Message-id: 20170905131149.10669-2-famz@redhat.com | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | hw/arm/armv7m.c | 8 ++------ | ||
10 | 1 file changed, 2 insertions(+), 6 deletions(-) | ||
11 | |||
12 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/hw/arm/armv7m.c | ||
15 | +++ b/hw/arm/armv7m.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj) | ||
17 | BitBandState *s = BITBAND(obj); | ||
18 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | ||
19 | |||
20 | - object_property_add_link(obj, "source-memory", | ||
21 | - TYPE_MEMORY_REGION, | ||
22 | - (Object **)&s->source_memory, | ||
23 | - qdev_prop_allow_set_link_before_realize, | ||
24 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
25 | - &error_abort); | ||
26 | memory_region_init_io(&s->iomem, obj, &bitband_ops, s, | ||
27 | "bitband", 0x02000000); | ||
28 | sysbus_init_mmio(dev, &s->iomem); | ||
29 | @@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
30 | |||
31 | static Property bitband_properties[] = { | ||
32 | DEFINE_PROP_UINT32("base", BitBandState, base, 0), | ||
33 | + DEFINE_PROP_LINK("source-memory", BitBandState, source_memory, | ||
34 | + TYPE_MEMORY_REGION, MemoryRegion *), | ||
35 | DEFINE_PROP_END_OF_LIST(), | ||
36 | }; | ||
37 | |||
38 | -- | ||
39 | 2.7.4 | ||
40 | |||
41 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | Adds a line-item reference to the supported quanta-q71l-bmc aspeed |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | entry. |
5 | Message-id: 20170905131149.10669-6-famz@redhat.com | 5 | |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Patrick Venture <venture@google.com> |
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Message-id: 20210615192848.1065297-2-venture@google.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 10 | --- |
9 | hw/net/xilinx_axienet.c | 16 ++++------------ | 11 | docs/system/arm/aspeed.rst | 1 + |
10 | 1 file changed, 4 insertions(+), 12 deletions(-) | 12 | 1 file changed, 1 insertion(+) |
11 | 13 | ||
12 | diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/net/xilinx_axienet.c | 16 | --- a/docs/system/arm/aspeed.rst |
15 | +++ b/hw/net/xilinx_axienet.c | 17 | +++ b/docs/system/arm/aspeed.rst |
16 | @@ -XXX,XX +XXX,XX @@ static void xilinx_enet_init(Object *obj) | 18 | @@ -XXX,XX +XXX,XX @@ etc. |
17 | XilinxAXIEnet *s = XILINX_AXI_ENET(obj); | 19 | AST2400 SoC based machines : |
18 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 20 | |
19 | 21 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC | |
20 | - object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, | 22 | +- ``quanta-q71l-bmc`` OpenBMC Quanta BMC |
21 | - (Object **) &s->tx_data_dev, | 23 | |
22 | - qdev_prop_allow_set_link_before_realize, | 24 | AST2500 SoC based machines : |
23 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
24 | - &error_abort); | ||
25 | - object_property_add_link(obj, "axistream-control-connected", | ||
26 | - TYPE_STREAM_SLAVE, | ||
27 | - (Object **) &s->tx_control_dev, | ||
28 | - qdev_prop_allow_set_link_before_realize, | ||
29 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
30 | - &error_abort); | ||
31 | - | ||
32 | object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), | ||
33 | TYPE_XILINX_AXI_ENET_DATA_STREAM); | ||
34 | object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), | ||
35 | @@ -XXX,XX +XXX,XX @@ static Property xilinx_enet_properties[] = { | ||
36 | DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), | ||
37 | DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), | ||
38 | DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), | ||
39 | + DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, | ||
40 | + tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), | ||
41 | + DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, | ||
42 | + tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), | ||
43 | DEFINE_PROP_END_OF_LIST(), | ||
44 | }; | ||
45 | 25 | ||
46 | -- | 26 | -- |
47 | 2.7.4 | 27 | 2.20.1 |
48 | 28 | ||
49 | 29 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | Add line item reference to quanta-gbs-bmc machine. |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | |
5 | Message-id: 20170905131149.10669-5-famz@redhat.com | 5 | Signed-off-by: Patrick Venture <venture@google.com> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
7 | Message-id: 20210615192848.1065297-3-venture@google.com | ||
8 | [PMM: fixed underline Sphinx warning] | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 10 | --- |
9 | hw/arm/xlnx-zynqmp.c | 7 ++----- | 11 | docs/system/arm/nuvoton.rst | 5 +++-- |
10 | 1 file changed, 2 insertions(+), 5 deletions(-) | 12 | 1 file changed, 3 insertions(+), 2 deletions(-) |
11 | 13 | ||
12 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | 14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/arm/xlnx-zynqmp.c | 16 | --- a/docs/system/arm/nuvoton.rst |
15 | +++ b/hw/arm/xlnx-zynqmp.c | 17 | +++ b/docs/system/arm/nuvoton.rst |
16 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj) | 18 | @@ -XXX,XX +XXX,XX @@ |
17 | &error_abort); | 19 | -Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) |
18 | } | 20 | -===================================================== |
19 | 21 | +Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``) | |
20 | - object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION, | 22 | +================================================================ |
21 | - (Object **)&s->ddr_ram, | 23 | |
22 | - qdev_prop_allow_set_link_before_realize, | 24 | The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are |
23 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); | 25 | designed to be used as Baseboard Management Controllers (BMCs) in various |
24 | - | 26 | @@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip : |
25 | object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); | 27 | The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and |
26 | qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); | 28 | Hyperscale applications. The following machines are based on this chip : |
27 | 29 | ||
28 | @@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = { | 30 | +- ``quanta-gbs-bmc`` Quanta GBS server BMC |
29 | DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), | 31 | - ``quanta-gsj`` Quanta GSJ server BMC |
30 | DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), | 32 | |
31 | DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), | 33 | There are also two more SoCs, NPCM710 and NPCM705, which are single-core |
32 | + DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, | ||
33 | + MemoryRegion *), | ||
34 | DEFINE_PROP_END_OF_LIST() | ||
35 | }; | ||
36 | |||
37 | -- | 34 | -- |
38 | 2.7.4 | 35 | 2.20.1 |
39 | 36 | ||
40 | 37 | diff view generated by jsdifflib |
1 | As part of ARMv8M, we need to add support for the PMSAv8 MPU | 1 | From: Nolan Leake <nolan@sigbus.net> |
---|---|---|---|
2 | architecture. | 2 | |
3 | 3 | This is just enough to make reboot and poweroff work. Works for | |
4 | PMSAv8 differs from PMSAv7 both in register/data layout (for instance | 4 | linux, u-boot, and the arm trusted firmware. Not tested, but should |
5 | using base and limit registers rather than base and size) and also in | 5 | work for plan9, and bare-metal/hobby OSes, since they seem to generally |
6 | behaviour (for example it does not have subregions); rather than | 6 | do what linux does for reset. |
7 | trying to wedge it into the existing PMSAv7 code and data structures, | 7 | |
8 | we define separate ones. | 8 | The watchdog timer functionality is not yet implemented. |
9 | 9 | ||
10 | This commit adds the data structures which hold the state for a | 10 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64 |
11 | PMSAv8 MPU and the register interface to it. The implementation of | 11 | Signed-off-by: Nolan Leake <nolan@sigbus.net> |
12 | the MPU behaviour will be added in a subsequent commit. | 12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
13 | 13 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | |
14 | Message-id: 20210625210209.1870217-1-nolan@sigbus.net | ||
15 | [PMM: tweaked commit title; fixed region size to 0x200; | ||
16 | moved header file to include/] | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Message-id: 1503414539-28762-2-git-send-email-peter.maydell@linaro.org | ||
17 | --- | 18 | --- |
18 | target/arm/cpu.h | 13 ++++++ | 19 | include/hw/arm/bcm2835_peripherals.h | 3 +- |
19 | hw/intc/armv7m_nvic.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++---- | 20 | include/hw/misc/bcm2835_powermgt.h | 29 +++++ |
20 | target/arm/cpu.c | 36 ++++++++++----- | 21 | hw/arm/bcm2835_peripherals.c | 13 ++- |
21 | target/arm/machine.c | 29 +++++++++++- | 22 | hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++ |
22 | 4 files changed, 180 insertions(+), 20 deletions(-) | 23 | hw/misc/meson.build | 1 + |
23 | 24 | 5 files changed, 204 insertions(+), 2 deletions(-) | |
24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 25 | create mode 100644 include/hw/misc/bcm2835_powermgt.h |
26 | create mode 100644 hw/misc/bcm2835_powermgt.c | ||
27 | |||
28 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/cpu.h | 30 | --- a/include/hw/arm/bcm2835_peripherals.h |
27 | +++ b/target/arm/cpu.h | 31 | +++ b/include/hw/arm/bcm2835_peripherals.h |
28 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 32 | @@ -XXX,XX +XXX,XX @@ |
29 | uint32_t rnr; | 33 | #include "hw/misc/bcm2835_mphi.h" |
30 | } pmsav7; | 34 | #include "hw/misc/bcm2835_thermal.h" |
31 | 35 | #include "hw/misc/bcm2835_cprman.h" | |
32 | + /* PMSAv8 MPU */ | 36 | +#include "hw/misc/bcm2835_powermgt.h" |
33 | + struct { | 37 | #include "hw/sd/sdhci.h" |
34 | + /* The PMSAv8 implementation also shares some PMSAv7 config | 38 | #include "hw/sd/bcm2835_sdhost.h" |
35 | + * and state: | 39 | #include "hw/gpio/bcm2835_gpio.h" |
36 | + * pmsav7.rnr (region number register) | 40 | @@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState { |
37 | + * pmsav7_dregion (number of configured regions) | 41 | BCM2835MphiState mphi; |
38 | + */ | 42 | UnimplementedDeviceState txp; |
39 | + uint32_t *rbar; | 43 | UnimplementedDeviceState armtmr; |
40 | + uint32_t *rlar; | 44 | - UnimplementedDeviceState powermgt; |
41 | + uint32_t mair0; | 45 | + BCM2835PowerMgtState powermgt; |
42 | + uint32_t mair1; | 46 | BCM2835CprmanState cprman; |
43 | + } pmsav8; | 47 | PL011State uart0; |
44 | + | 48 | BCM2835AuxState aux; |
45 | void *nvic; | 49 | diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h |
46 | const struct arm_boot_info *boot_info; | 50 | new file mode 100644 |
47 | /* Store GICv3CPUState to access from this struct */ | 51 | index XXXXXXX..XXXXXXX |
48 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 52 | --- /dev/null |
53 | +++ b/include/hw/misc/bcm2835_powermgt.h | ||
54 | @@ -XXX,XX +XXX,XX @@ | ||
55 | +/* | ||
56 | + * BCM2835 Power Management emulation | ||
57 | + * | ||
58 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> | ||
59 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> | ||
60 | + * | ||
61 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
62 | + * See the COPYING file in the top-level directory. | ||
63 | + */ | ||
64 | + | ||
65 | +#ifndef BCM2835_POWERMGT_H | ||
66 | +#define BCM2835_POWERMGT_H | ||
67 | + | ||
68 | +#include "hw/sysbus.h" | ||
69 | +#include "qom/object.h" | ||
70 | + | ||
71 | +#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt" | ||
72 | +OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT) | ||
73 | + | ||
74 | +struct BCM2835PowerMgtState { | ||
75 | + SysBusDevice busdev; | ||
76 | + MemoryRegion iomem; | ||
77 | + | ||
78 | + uint32_t rstc; | ||
79 | + uint32_t rsts; | ||
80 | + uint32_t wdog; | ||
81 | +}; | ||
82 | + | ||
83 | +#endif | ||
84 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | 85 | index XXXXXXX..XXXXXXX 100644 |
50 | --- a/hw/intc/armv7m_nvic.c | 86 | --- a/hw/arm/bcm2835_peripherals.c |
51 | +++ b/hw/intc/armv7m_nvic.c | 87 | +++ b/hw/arm/bcm2835_peripherals.c |
52 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) | 88 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj) |
53 | { | 89 | |
54 | int region = cpu->env.pmsav7.rnr; | 90 | object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", |
55 | 91 | OBJECT(&s->gpu_bus_mr)); | |
56 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | 92 | + |
57 | + /* PMSAv8M handling of the aliases is different from v7M: | 93 | + /* Power Management */ |
58 | + * aliases A1, A2, A3 override the low two bits of the region | 94 | + object_initialize_child(obj, "powermgt", &s->powermgt, |
59 | + * number in MPU_RNR, and there is no 'region' field in the | 95 | + TYPE_BCM2835_POWERMGT); |
60 | + * RBAR register. | 96 | } |
61 | + */ | 97 | |
62 | + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | 98 | static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) |
63 | + if (aliasno) { | 99 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) |
64 | + region = deposit32(region, 0, 2, aliasno); | 100 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, |
101 | INTERRUPT_USB)); | ||
102 | |||
103 | + /* Power Management */ | ||
104 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) { | ||
105 | + return; | ||
106 | + } | ||
107 | + | ||
108 | + memory_region_add_subregion(&s->peri_mr, PM_OFFSET, | ||
109 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0)); | ||
110 | + | ||
111 | create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); | ||
112 | create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); | ||
113 | - create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); | ||
114 | create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); | ||
115 | create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); | ||
116 | create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); | ||
117 | diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c | ||
118 | new file mode 100644 | ||
119 | index XXXXXXX..XXXXXXX | ||
120 | --- /dev/null | ||
121 | +++ b/hw/misc/bcm2835_powermgt.c | ||
122 | @@ -XXX,XX +XXX,XX @@ | ||
123 | +/* | ||
124 | + * BCM2835 Power Management emulation | ||
125 | + * | ||
126 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> | ||
127 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> | ||
128 | + * | ||
129 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
130 | + * See the COPYING file in the top-level directory. | ||
131 | + */ | ||
132 | + | ||
133 | +#include "qemu/osdep.h" | ||
134 | +#include "qemu/log.h" | ||
135 | +#include "qemu/module.h" | ||
136 | +#include "hw/misc/bcm2835_powermgt.h" | ||
137 | +#include "migration/vmstate.h" | ||
138 | +#include "sysemu/runstate.h" | ||
139 | + | ||
140 | +#define PASSWORD 0x5a000000 | ||
141 | +#define PASSWORD_MASK 0xff000000 | ||
142 | + | ||
143 | +#define R_RSTC 0x1c | ||
144 | +#define V_RSTC_RESET 0x20 | ||
145 | +#define R_RSTS 0x20 | ||
146 | +#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */ | ||
147 | +#define R_WDOG 0x24 | ||
148 | + | ||
149 | +static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset, | ||
150 | + unsigned size) | ||
151 | +{ | ||
152 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | ||
153 | + uint32_t res = 0; | ||
154 | + | ||
155 | + switch (offset) { | ||
156 | + case R_RSTC: | ||
157 | + res = s->rstc; | ||
158 | + break; | ||
159 | + case R_RSTS: | ||
160 | + res = s->rsts; | ||
161 | + break; | ||
162 | + case R_WDOG: | ||
163 | + res = s->wdog; | ||
164 | + break; | ||
165 | + | ||
166 | + default: | ||
167 | + qemu_log_mask(LOG_UNIMP, | ||
168 | + "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx | ||
169 | + "\n", offset); | ||
170 | + res = 0; | ||
171 | + break; | ||
172 | + } | ||
173 | + | ||
174 | + return res; | ||
175 | +} | ||
176 | + | ||
177 | +static void bcm2835_powermgt_write(void *opaque, hwaddr offset, | ||
178 | + uint64_t value, unsigned size) | ||
179 | +{ | ||
180 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | ||
181 | + | ||
182 | + if ((value & PASSWORD_MASK) != PASSWORD) { | ||
183 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
184 | + "bcm2835_powermgt_write: Bad password 0x%"PRIx64 | ||
185 | + " at offset 0x%08"HWADDR_PRIx"\n", | ||
186 | + value, offset); | ||
187 | + return; | ||
188 | + } | ||
189 | + | ||
190 | + value = value & ~PASSWORD_MASK; | ||
191 | + | ||
192 | + switch (offset) { | ||
193 | + case R_RSTC: | ||
194 | + s->rstc = value; | ||
195 | + if (value & V_RSTC_RESET) { | ||
196 | + if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) { | ||
197 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | ||
198 | + } else { | ||
199 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
65 | + } | 200 | + } |
66 | + if (region >= cpu->pmsav7_dregion) { | ||
67 | + return 0; | ||
68 | + } | ||
69 | + return cpu->env.pmsav8.rbar[region]; | ||
70 | + } | 201 | + } |
71 | + | 202 | + break; |
72 | if (region >= cpu->pmsav7_dregion) { | 203 | + case R_RSTS: |
73 | return 0; | 204 | + qemu_log_mask(LOG_UNIMP, |
74 | } | 205 | + "bcm2835_powermgt_write: RSTS\n"); |
75 | return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); | 206 | + s->rsts = value; |
76 | } | 207 | + break; |
77 | - case 0xda0: /* MPU_RASR */ | 208 | + case R_WDOG: |
78 | - case 0xda8: /* MPU_RASR_A1 */ | 209 | + qemu_log_mask(LOG_UNIMP, |
79 | - case 0xdb0: /* MPU_RASR_A2 */ | 210 | + "bcm2835_powermgt_write: WDOG\n"); |
80 | - case 0xdb8: /* MPU_RASR_A3 */ | 211 | + s->wdog = value; |
81 | + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ | 212 | + break; |
82 | + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ | 213 | + |
83 | + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | 214 | + default: |
84 | + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | 215 | + qemu_log_mask(LOG_UNIMP, |
85 | { | 216 | + "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx |
86 | int region = cpu->env.pmsav7.rnr; | 217 | + "\n", offset); |
87 | 218 | + break; | |
88 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | 219 | + } |
89 | + /* PMSAv8M handling of the aliases is different from v7M: | 220 | +} |
90 | + * aliases A1, A2, A3 override the low two bits of the region | 221 | + |
91 | + * number in MPU_RNR. | 222 | +static const MemoryRegionOps bcm2835_powermgt_ops = { |
92 | + */ | 223 | + .read = bcm2835_powermgt_read, |
93 | + int aliasno = (offset - 0xda0) / 8; /* 0..3 */ | 224 | + .write = bcm2835_powermgt_write, |
94 | + if (aliasno) { | 225 | + .endianness = DEVICE_NATIVE_ENDIAN, |
95 | + region = deposit32(region, 0, 2, aliasno); | 226 | + .impl.min_access_size = 4, |
96 | + } | 227 | + .impl.max_access_size = 4, |
97 | + if (region >= cpu->pmsav7_dregion) { | 228 | +}; |
98 | + return 0; | 229 | + |
99 | + } | 230 | +static const VMStateDescription vmstate_bcm2835_powermgt = { |
100 | + return cpu->env.pmsav8.rlar[region]; | 231 | + .name = TYPE_BCM2835_POWERMGT, |
101 | + } | ||
102 | + | ||
103 | if (region >= cpu->pmsav7_dregion) { | ||
104 | return 0; | ||
105 | } | ||
106 | return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | | ||
107 | (cpu->env.pmsav7.drsr[region] & 0xffff); | ||
108 | } | ||
109 | + case 0xdc0: /* MPU_MAIR0 */ | ||
110 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
111 | + goto bad_offset; | ||
112 | + } | ||
113 | + return cpu->env.pmsav8.mair0; | ||
114 | + case 0xdc4: /* MPU_MAIR1 */ | ||
115 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
116 | + goto bad_offset; | ||
117 | + } | ||
118 | + return cpu->env.pmsav8.mair1; | ||
119 | default: | ||
120 | + bad_offset: | ||
121 | qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); | ||
122 | return 0; | ||
123 | } | ||
124 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
125 | { | ||
126 | int region; | ||
127 | |||
128 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
129 | + /* PMSAv8M handling of the aliases is different from v7M: | ||
130 | + * aliases A1, A2, A3 override the low two bits of the region | ||
131 | + * number in MPU_RNR, and there is no 'region' field in the | ||
132 | + * RBAR register. | ||
133 | + */ | ||
134 | + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | ||
135 | + | ||
136 | + region = cpu->env.pmsav7.rnr; | ||
137 | + if (aliasno) { | ||
138 | + region = deposit32(region, 0, 2, aliasno); | ||
139 | + } | ||
140 | + if (region >= cpu->pmsav7_dregion) { | ||
141 | + return; | ||
142 | + } | ||
143 | + cpu->env.pmsav8.rbar[region] = value; | ||
144 | + tlb_flush(CPU(cpu)); | ||
145 | + return; | ||
146 | + } | ||
147 | + | ||
148 | if (value & (1 << 4)) { | ||
149 | /* VALID bit means use the region number specified in this | ||
150 | * value and also update MPU_RNR.REGION with that value. | ||
151 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
152 | tlb_flush(CPU(cpu)); | ||
153 | break; | ||
154 | } | ||
155 | - case 0xda0: /* MPU_RASR */ | ||
156 | - case 0xda8: /* MPU_RASR_A1 */ | ||
157 | - case 0xdb0: /* MPU_RASR_A2 */ | ||
158 | - case 0xdb8: /* MPU_RASR_A3 */ | ||
159 | + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ | ||
160 | + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ | ||
161 | + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | ||
162 | + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | ||
163 | { | ||
164 | int region = cpu->env.pmsav7.rnr; | ||
165 | |||
166 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
167 | + /* PMSAv8M handling of the aliases is different from v7M: | ||
168 | + * aliases A1, A2, A3 override the low two bits of the region | ||
169 | + * number in MPU_RNR. | ||
170 | + */ | ||
171 | + int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | ||
172 | + | ||
173 | + region = cpu->env.pmsav7.rnr; | ||
174 | + if (aliasno) { | ||
175 | + region = deposit32(region, 0, 2, aliasno); | ||
176 | + } | ||
177 | + if (region >= cpu->pmsav7_dregion) { | ||
178 | + return; | ||
179 | + } | ||
180 | + cpu->env.pmsav8.rlar[region] = value; | ||
181 | + tlb_flush(CPU(cpu)); | ||
182 | + return; | ||
183 | + } | ||
184 | + | ||
185 | if (region >= cpu->pmsav7_dregion) { | ||
186 | return; | ||
187 | } | ||
188 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
189 | tlb_flush(CPU(cpu)); | ||
190 | break; | ||
191 | } | ||
192 | + case 0xdc0: /* MPU_MAIR0 */ | ||
193 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
194 | + goto bad_offset; | ||
195 | + } | ||
196 | + if (cpu->pmsav7_dregion) { | ||
197 | + /* Register is RES0 if no MPU regions are implemented */ | ||
198 | + cpu->env.pmsav8.mair0 = value; | ||
199 | + } | ||
200 | + /* We don't need to do anything else because memory attributes | ||
201 | + * only affect cacheability, and we don't implement caching. | ||
202 | + */ | ||
203 | + break; | ||
204 | + case 0xdc4: /* MPU_MAIR1 */ | ||
205 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
206 | + goto bad_offset; | ||
207 | + } | ||
208 | + if (cpu->pmsav7_dregion) { | ||
209 | + /* Register is RES0 if no MPU regions are implemented */ | ||
210 | + cpu->env.pmsav8.mair1 = value; | ||
211 | + } | ||
212 | + /* We don't need to do anything else because memory attributes | ||
213 | + * only affect cacheability, and we don't implement caching. | ||
214 | + */ | ||
215 | + break; | ||
216 | case 0xf00: /* Software Triggered Interrupt Register */ | ||
217 | { | ||
218 | int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; | ||
219 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
220 | break; | ||
221 | } | ||
222 | default: | ||
223 | + bad_offset: | ||
224 | qemu_log_mask(LOG_GUEST_ERROR, | ||
225 | "NVIC: Bad write offset 0x%x\n", offset); | ||
226 | } | ||
227 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
228 | index XXXXXXX..XXXXXXX 100644 | ||
229 | --- a/target/arm/cpu.c | ||
230 | +++ b/target/arm/cpu.c | ||
231 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
232 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | ||
233 | #endif | ||
234 | |||
235 | - if (arm_feature(env, ARM_FEATURE_PMSA) && | ||
236 | - arm_feature(env, ARM_FEATURE_V7)) { | ||
237 | + if (arm_feature(env, ARM_FEATURE_PMSA)) { | ||
238 | if (cpu->pmsav7_dregion > 0) { | ||
239 | - memset(env->pmsav7.drbar, 0, | ||
240 | - sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | ||
241 | - memset(env->pmsav7.drsr, 0, | ||
242 | - sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | ||
243 | - memset(env->pmsav7.dracr, 0, | ||
244 | - sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | ||
245 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
246 | + memset(env->pmsav8.rbar, 0, | ||
247 | + sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); | ||
248 | + memset(env->pmsav8.rlar, 0, | ||
249 | + sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); | ||
250 | + } else if (arm_feature(env, ARM_FEATURE_V7)) { | ||
251 | + memset(env->pmsav7.drbar, 0, | ||
252 | + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | ||
253 | + memset(env->pmsav7.drsr, 0, | ||
254 | + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | ||
255 | + memset(env->pmsav7.dracr, 0, | ||
256 | + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | ||
257 | + } | ||
258 | } | ||
259 | env->pmsav7.rnr = 0; | ||
260 | + env->pmsav8.mair0 = 0; | ||
261 | + env->pmsav8.mair1 = 0; | ||
262 | } | ||
263 | |||
264 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | ||
265 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
266 | } | ||
267 | |||
268 | if (nr) { | ||
269 | - env->pmsav7.drbar = g_new0(uint32_t, nr); | ||
270 | - env->pmsav7.drsr = g_new0(uint32_t, nr); | ||
271 | - env->pmsav7.dracr = g_new0(uint32_t, nr); | ||
272 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
273 | + /* PMSAv8 */ | ||
274 | + env->pmsav8.rbar = g_new0(uint32_t, nr); | ||
275 | + env->pmsav8.rlar = g_new0(uint32_t, nr); | ||
276 | + } else { | ||
277 | + env->pmsav7.drbar = g_new0(uint32_t, nr); | ||
278 | + env->pmsav7.drsr = g_new0(uint32_t, nr); | ||
279 | + env->pmsav7.dracr = g_new0(uint32_t, nr); | ||
280 | + } | ||
281 | } | ||
282 | } | ||
283 | |||
284 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
285 | index XXXXXXX..XXXXXXX 100644 | ||
286 | --- a/target/arm/machine.c | ||
287 | +++ b/target/arm/machine.c | ||
288 | @@ -XXX,XX +XXX,XX @@ static bool pmsav7_needed(void *opaque) | ||
289 | CPUARMState *env = &cpu->env; | ||
290 | |||
291 | return arm_feature(env, ARM_FEATURE_PMSA) && | ||
292 | - arm_feature(env, ARM_FEATURE_V7); | ||
293 | + arm_feature(env, ARM_FEATURE_V7) && | ||
294 | + !arm_feature(env, ARM_FEATURE_V8); | ||
295 | } | ||
296 | |||
297 | static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) | ||
298 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav7_rnr = { | ||
299 | } | ||
300 | }; | ||
301 | |||
302 | +static bool pmsav8_needed(void *opaque) | ||
303 | +{ | ||
304 | + ARMCPU *cpu = opaque; | ||
305 | + CPUARMState *env = &cpu->env; | ||
306 | + | ||
307 | + return arm_feature(env, ARM_FEATURE_PMSA) && | ||
308 | + arm_feature(env, ARM_FEATURE_V8); | ||
309 | +} | ||
310 | + | ||
311 | +static const VMStateDescription vmstate_pmsav8 = { | ||
312 | + .name = "cpu/pmsav8", | ||
313 | + .version_id = 1, | 232 | + .version_id = 1, |
314 | + .minimum_version_id = 1, | 233 | + .minimum_version_id = 1, |
315 | + .needed = pmsav8_needed, | ||
316 | + .fields = (VMStateField[]) { | 234 | + .fields = (VMStateField[]) { |
317 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, | 235 | + VMSTATE_UINT32(rstc, BCM2835PowerMgtState), |
318 | + vmstate_info_uint32, uint32_t), | 236 | + VMSTATE_UINT32(rsts, BCM2835PowerMgtState), |
319 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, | 237 | + VMSTATE_UINT32(wdog, BCM2835PowerMgtState), |
320 | + vmstate_info_uint32, uint32_t), | ||
321 | + VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), | ||
322 | + VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), | ||
323 | + VMSTATE_END_OF_LIST() | 238 | + VMSTATE_END_OF_LIST() |
324 | + } | 239 | + } |
325 | +}; | 240 | +}; |
326 | + | 241 | + |
327 | static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | 242 | +static void bcm2835_powermgt_init(Object *obj) |
328 | VMStateField *field) | 243 | +{ |
329 | { | 244 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj); |
330 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = { | 245 | + |
331 | */ | 246 | + memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s, |
332 | &vmstate_pmsav7_rnr, | 247 | + TYPE_BCM2835_POWERMGT, 0x200); |
333 | &vmstate_pmsav7, | 248 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); |
334 | + &vmstate_pmsav8, | 249 | +} |
335 | NULL | 250 | + |
336 | } | 251 | +static void bcm2835_powermgt_reset(DeviceState *dev) |
337 | }; | 252 | +{ |
253 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev); | ||
254 | + | ||
255 | + /* https://elinux.org/BCM2835_registers#PM */ | ||
256 | + s->rstc = 0x00000102; | ||
257 | + s->rsts = 0x00001000; | ||
258 | + s->wdog = 0x00000000; | ||
259 | +} | ||
260 | + | ||
261 | +static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data) | ||
262 | +{ | ||
263 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
264 | + | ||
265 | + dc->reset = bcm2835_powermgt_reset; | ||
266 | + dc->vmsd = &vmstate_bcm2835_powermgt; | ||
267 | +} | ||
268 | + | ||
269 | +static TypeInfo bcm2835_powermgt_info = { | ||
270 | + .name = TYPE_BCM2835_POWERMGT, | ||
271 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
272 | + .instance_size = sizeof(BCM2835PowerMgtState), | ||
273 | + .class_init = bcm2835_powermgt_class_init, | ||
274 | + .instance_init = bcm2835_powermgt_init, | ||
275 | +}; | ||
276 | + | ||
277 | +static void bcm2835_powermgt_register_types(void) | ||
278 | +{ | ||
279 | + type_register_static(&bcm2835_powermgt_info); | ||
280 | +} | ||
281 | + | ||
282 | +type_init(bcm2835_powermgt_register_types) | ||
283 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
284 | index XXXXXXX..XXXXXXX 100644 | ||
285 | --- a/hw/misc/meson.build | ||
286 | +++ b/hw/misc/meson.build | ||
287 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( | ||
288 | 'bcm2835_rng.c', | ||
289 | 'bcm2835_thermal.c', | ||
290 | 'bcm2835_cprman.c', | ||
291 | + 'bcm2835_powermgt.c', | ||
292 | )) | ||
293 | softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | ||
294 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c')) | ||
338 | -- | 295 | -- |
339 | 2.7.4 | 296 | 2.20.1 |
340 | 297 | ||
341 | 298 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | Add a test booting and quickly shutdown a raspi2 machine, |
4 | Message-id: 20170905131149.10669-4-famz@redhat.com | 4 | to test the power management model: |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | |
6 | (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd: | ||
7 | console: [ 0.000000] Booting Linux on physical CPU 0xf00 | ||
8 | console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019 | ||
9 | console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d | ||
10 | console: [ 0.000000] CPU: div instructions available: patching division code | ||
11 | console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache | ||
12 | console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B | ||
13 | ... | ||
14 | console: Boot successful. | ||
15 | console: cat /proc/cpuinfo | ||
16 | console: / # cat /proc/cpuinfo | ||
17 | ... | ||
18 | console: processor : 3 | ||
19 | console: model name : ARMv7 Processor rev 5 (v7l) | ||
20 | console: BogoMIPS : 125.00 | ||
21 | console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm | ||
22 | console: CPU implementer : 0x41 | ||
23 | console: CPU architecture: 7 | ||
24 | console: CPU variant : 0x0 | ||
25 | console: CPU part : 0xc07 | ||
26 | console: CPU revision : 5 | ||
27 | console: Hardware : BCM2835 | ||
28 | console: Revision : 0000 | ||
29 | console: Serial : 0000000000000000 | ||
30 | console: cat /proc/iomem | ||
31 | console: / # cat /proc/iomem | ||
32 | console: 00000000-3bffffff : System RAM | ||
33 | console: 00008000-00afffff : Kernel code | ||
34 | console: 00c00000-00d468ef : Kernel data | ||
35 | console: 3f006000-3f006fff : dwc_otg | ||
36 | console: 3f007000-3f007eff : /soc/dma@7e007000 | ||
37 | console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880 | ||
38 | console: 3f100000-3f100027 : /soc/watchdog@7e100000 | ||
39 | console: 3f101000-3f102fff : /soc/cprman@7e101000 | ||
40 | console: 3f200000-3f2000b3 : /soc/gpio@7e200000 | ||
41 | PASS (24.59 s) | ||
42 | RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 | ||
43 | JOB TIME : 25.02 s | ||
44 | |||
45 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
46 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | ||
47 | Message-id: 20210531113837.1689775-1-f4bug@amsat.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 48 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 49 | --- |
8 | hw/intc/arm_gicv3_its_kvm.c | 19 +++++++------------ | 50 | tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++ |
9 | 1 file changed, 7 insertions(+), 12 deletions(-) | 51 | 1 file changed, 43 insertions(+) |
10 | 52 | ||
11 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | 53 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py |
12 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/intc/arm_gicv3_its_kvm.c | 55 | --- a/tests/acceptance/boot_linux_console.py |
14 | +++ b/hw/intc/arm_gicv3_its_kvm.c | 56 | +++ b/tests/acceptance/boot_linux_console.py |
15 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | 57 | @@ -XXX,XX +XXX,XX @@ |
16 | qemu_add_vm_change_state_handler(vm_change_state_handler, s); | 58 | from avocado import skip |
17 | } | 59 | from avocado import skipUnless |
18 | 60 | from avocado_qemu import Test | |
19 | -static void kvm_arm_its_init(Object *obj) | 61 | +from avocado_qemu import exec_command |
20 | -{ | 62 | from avocado_qemu import exec_command_and_wait_for_pattern |
21 | - GICv3ITSState *s = KVM_ARM_ITS(obj); | 63 | from avocado_qemu import interrupt_interactive_console_until_pattern |
22 | - | 64 | from avocado_qemu import wait_for_console_pattern |
23 | - object_property_add_link(obj, "parent-gicv3", | 65 | @@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self): |
24 | - "kvm-arm-gicv3", (Object **)&s->gicv3, | 66 | """ |
25 | - object_property_allow_set_link, | 67 | self.do_test_arm_raspi2(0) |
26 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | 68 | |
27 | - &error_abort); | 69 | + def test_arm_raspi2_initrd(self): |
28 | -} | 70 | + """ |
29 | - | 71 | + :avocado: tags=arch:arm |
30 | /** | 72 | + :avocado: tags=machine:raspi2 |
31 | * kvm_arm_its_pre_save - handles the saving of ITS registers. | 73 | + """ |
32 | * ITS tables are flushed into guest RAM separately and earlier, | 74 | + deb_url = ('http://archive.raspberrypi.org/debian/' |
33 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s) | 75 | + 'pool/main/r/raspberrypi-firmware/' |
34 | GITS_CTLR, &s->ctlr, true, &error_abort); | 76 | + 'raspberrypi-kernel_1.20190215-1_armhf.deb') |
35 | } | 77 | + deb_hash = 'cd284220b32128c5084037553db3c482426f3972' |
36 | 78 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | |
37 | +static Property kvm_arm_its_props[] = { | 79 | + kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img') |
38 | + DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3", | 80 | + dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb') |
39 | + GICv3State *), | ||
40 | + DEFINE_PROP_END_OF_LIST(), | ||
41 | +}; | ||
42 | + | 81 | + |
43 | static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | 82 | + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' |
44 | { | 83 | + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' |
45 | DeviceClass *dc = DEVICE_CLASS(klass); | 84 | + 'arm/rootfs-armv7a.cpio.gz') |
46 | GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); | 85 | + initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' |
47 | 86 | + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) | |
48 | dc->realize = kvm_arm_its_realize; | 87 | + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') |
49 | + dc->props = kvm_arm_its_props; | 88 | + archive.gzip_uncompress(initrd_path_gz, initrd_path) |
50 | icc->send_msi = kvm_its_send_msi; | 89 | + |
51 | icc->pre_save = kvm_arm_its_pre_save; | 90 | + self.vm.set_console() |
52 | icc->post_load = kvm_arm_its_post_load; | 91 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + |
53 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo kvm_arm_its_info = { | 92 | + 'earlycon=pl011,0x3f201000 console=ttyAMA0 ' |
54 | .name = TYPE_KVM_ARM_ITS, | 93 | + 'panic=-1 noreboot ' + |
55 | .parent = TYPE_ARM_GICV3_ITS_COMMON, | 94 | + 'dwc_otg.fiq_fsm_enable=0') |
56 | .instance_size = sizeof(GICv3ITSState), | 95 | + self.vm.add_args('-kernel', kernel_path, |
57 | - .instance_init = kvm_arm_its_init, | 96 | + '-dtb', dtb_path, |
58 | .class_init = kvm_arm_its_class_init, | 97 | + '-initrd', initrd_path, |
59 | }; | 98 | + '-append', kernel_command_line, |
60 | 99 | + '-no-reboot') | |
100 | + self.vm.launch() | ||
101 | + self.wait_for_console_pattern('Boot successful.') | ||
102 | + | ||
103 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | ||
104 | + 'BCM2835') | ||
105 | + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', | ||
106 | + '/soc/cprman@7e101000') | ||
107 | + exec_command(self, 'halt') | ||
108 | + # Wait for VM to shut down gracefully | ||
109 | + self.vm.wait() | ||
110 | + | ||
111 | def test_arm_exynos4210_initrd(self): | ||
112 | """ | ||
113 | :avocado: tags=arch:arm | ||
61 | -- | 114 | -- |
62 | 2.7.4 | 115 | 2.20.1 |
63 | 116 | ||
64 | 117 | diff view generated by jsdifflib |
1 | From: Fam Zheng <famz@redhat.com> | 1 | From: Joe Komlodi <joe.komlodi@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | 3 | If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will |
5 | Message-id: 20170905131149.10669-3-famz@redhat.com | 5 | assert due to fpst->default_nan_mode being set. |
6 | |||
7 | To avoid this, we check to see what NaN mode we're running in before we call | ||
8 | floatxx_silence_nan(). | ||
9 | |||
10 | Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 15 | --- |
9 | hw/arm/armv7m.c | 8 ++------ | 16 | target/arm/helper-a64.c | 12 +++++++++--- |
10 | 1 file changed, 2 insertions(+), 6 deletions(-) | 17 | target/arm/vfp_helper.c | 24 ++++++++++++++++++------ |
18 | 2 files changed, 27 insertions(+), 9 deletions(-) | ||
11 | 19 | ||
12 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 20 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c |
13 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/arm/armv7m.c | 22 | --- a/target/arm/helper-a64.c |
15 | +++ b/hw/arm/armv7m.c | 23 | +++ b/target/arm/helper-a64.c |
16 | @@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj) | 24 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) |
17 | 25 | float16 nan = a; | |
18 | /* Can't init the cpu here, we don't yet know which model to use */ | 26 | if (float16_is_signaling_nan(a, fpst)) { |
19 | 27 | float_raise(float_flag_invalid, fpst); | |
20 | - object_property_add_link(obj, "memory", | 28 | - nan = float16_silence_nan(a, fpst); |
21 | - TYPE_MEMORY_REGION, | 29 | + if (!fpst->default_nan_mode) { |
22 | - (Object **)&s->board_memory, | 30 | + nan = float16_silence_nan(a, fpst); |
23 | - qdev_prop_allow_set_link_before_realize, | 31 | + } |
24 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | 32 | } |
25 | - &error_abort); | 33 | if (fpst->default_nan_mode) { |
26 | memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX); | 34 | nan = float16_default_nan(fpst); |
27 | 35 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) | |
28 | object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC); | 36 | float32 nan = a; |
29 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | 37 | if (float32_is_signaling_nan(a, fpst)) { |
30 | 38 | float_raise(float_flag_invalid, fpst); | |
31 | static Property armv7m_properties[] = { | 39 | - nan = float32_silence_nan(a, fpst); |
32 | DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model), | 40 | + if (!fpst->default_nan_mode) { |
33 | + DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, | 41 | + nan = float32_silence_nan(a, fpst); |
34 | + MemoryRegion *), | 42 | + } |
35 | DEFINE_PROP_END_OF_LIST(), | 43 | } |
36 | }; | 44 | if (fpst->default_nan_mode) { |
37 | 45 | nan = float32_default_nan(fpst); | |
46 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) | ||
47 | float64 nan = a; | ||
48 | if (float64_is_signaling_nan(a, fpst)) { | ||
49 | float_raise(float_flag_invalid, fpst); | ||
50 | - nan = float64_silence_nan(a, fpst); | ||
51 | + if (!fpst->default_nan_mode) { | ||
52 | + nan = float64_silence_nan(a, fpst); | ||
53 | + } | ||
54 | } | ||
55 | if (fpst->default_nan_mode) { | ||
56 | nan = float64_default_nan(fpst); | ||
57 | diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/target/arm/vfp_helper.c | ||
60 | +++ b/target/arm/vfp_helper.c | ||
61 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) | ||
62 | float16 nan = f16; | ||
63 | if (float16_is_signaling_nan(f16, fpst)) { | ||
64 | float_raise(float_flag_invalid, fpst); | ||
65 | - nan = float16_silence_nan(f16, fpst); | ||
66 | + if (!fpst->default_nan_mode) { | ||
67 | + nan = float16_silence_nan(f16, fpst); | ||
68 | + } | ||
69 | } | ||
70 | if (fpst->default_nan_mode) { | ||
71 | nan = float16_default_nan(fpst); | ||
72 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) | ||
73 | float32 nan = f32; | ||
74 | if (float32_is_signaling_nan(f32, fpst)) { | ||
75 | float_raise(float_flag_invalid, fpst); | ||
76 | - nan = float32_silence_nan(f32, fpst); | ||
77 | + if (!fpst->default_nan_mode) { | ||
78 | + nan = float32_silence_nan(f32, fpst); | ||
79 | + } | ||
80 | } | ||
81 | if (fpst->default_nan_mode) { | ||
82 | nan = float32_default_nan(fpst); | ||
83 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) | ||
84 | float64 nan = f64; | ||
85 | if (float64_is_signaling_nan(f64, fpst)) { | ||
86 | float_raise(float_flag_invalid, fpst); | ||
87 | - nan = float64_silence_nan(f64, fpst); | ||
88 | + if (!fpst->default_nan_mode) { | ||
89 | + nan = float64_silence_nan(f64, fpst); | ||
90 | + } | ||
91 | } | ||
92 | if (fpst->default_nan_mode) { | ||
93 | nan = float64_default_nan(fpst); | ||
94 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) | ||
95 | float16 nan = f16; | ||
96 | if (float16_is_signaling_nan(f16, s)) { | ||
97 | float_raise(float_flag_invalid, s); | ||
98 | - nan = float16_silence_nan(f16, s); | ||
99 | + if (!s->default_nan_mode) { | ||
100 | + nan = float16_silence_nan(f16, fpstp); | ||
101 | + } | ||
102 | } | ||
103 | if (s->default_nan_mode) { | ||
104 | nan = float16_default_nan(s); | ||
105 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) | ||
106 | float32 nan = f32; | ||
107 | if (float32_is_signaling_nan(f32, s)) { | ||
108 | float_raise(float_flag_invalid, s); | ||
109 | - nan = float32_silence_nan(f32, s); | ||
110 | + if (!s->default_nan_mode) { | ||
111 | + nan = float32_silence_nan(f32, fpstp); | ||
112 | + } | ||
113 | } | ||
114 | if (s->default_nan_mode) { | ||
115 | nan = float32_default_nan(s); | ||
116 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) | ||
117 | float64 nan = f64; | ||
118 | if (float64_is_signaling_nan(f64, s)) { | ||
119 | float_raise(float_flag_invalid, s); | ||
120 | - nan = float64_silence_nan(f64, s); | ||
121 | + if (!s->default_nan_mode) { | ||
122 | + nan = float64_silence_nan(f64, fpstp); | ||
123 | + } | ||
124 | } | ||
125 | if (s->default_nan_mode) { | ||
126 | nan = float64_default_nan(s); | ||
38 | -- | 127 | -- |
39 | 2.7.4 | 128 | 2.20.1 |
40 | 129 | ||
41 | 130 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Fam Zheng <famz@redhat.com> | ||
2 | 1 | ||
3 | Signed-off-by: Fam Zheng <famz@redhat.com> | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Message-id: 20170905131149.10669-7-famz@redhat.com | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | hw/dma/xilinx_axidma.c | 16 ++++------------ | ||
10 | 1 file changed, 4 insertions(+), 12 deletions(-) | ||
11 | |||
12 | diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/hw/dma/xilinx_axidma.c | ||
15 | +++ b/hw/dma/xilinx_axidma.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_init(Object *obj) | ||
17 | XilinxAXIDMA *s = XILINX_AXI_DMA(obj); | ||
18 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
19 | |||
20 | - object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, | ||
21 | - (Object **)&s->tx_data_dev, | ||
22 | - qdev_prop_allow_set_link_before_realize, | ||
23 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
24 | - &error_abort); | ||
25 | - object_property_add_link(obj, "axistream-control-connected", | ||
26 | - TYPE_STREAM_SLAVE, | ||
27 | - (Object **)&s->tx_control_dev, | ||
28 | - qdev_prop_allow_set_link_before_realize, | ||
29 | - OBJ_PROP_LINK_UNREF_ON_RELEASE, | ||
30 | - &error_abort); | ||
31 | - | ||
32 | object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), | ||
33 | TYPE_XILINX_AXI_DMA_DATA_STREAM); | ||
34 | object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), | ||
35 | @@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_init(Object *obj) | ||
36 | |||
37 | static Property axidma_properties[] = { | ||
38 | DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000), | ||
39 | + DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA, | ||
40 | + tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), | ||
41 | + DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA, | ||
42 | + tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), | ||
43 | DEFINE_PROP_END_OF_LIST(), | ||
44 | }; | ||
45 | |||
46 | -- | ||
47 | 2.7.4 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Thomas Huth <thuth@redhat.com> | ||
2 | 1 | ||
3 | QEMU currently exits unexpectedly when the user accidentially | ||
4 | tries to do something like this: | ||
5 | |||
6 | $ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic | ||
7 | QEMU 2.9.93 monitor - type 'help' for more information | ||
8 | (qemu) device_add allwinner-a10 | ||
9 | Unsupported NIC model: smc91c111 | ||
10 | |||
11 | Exiting just due to a "device_add" should not happen. Looking closer | ||
12 | at the the realize and instance_init function of this device also | ||
13 | reveals that it is using serial_hds and nd_table directly there, so | ||
14 | this device is clearly not creatable by the user and should be marked | ||
15 | accordingly. | ||
16 | |||
17 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
18 | Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> | ||
19 | Message-id: 1503416789-32080-1-git-send-email-thuth@redhat.com | ||
20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | hw/arm/allwinner-a10.c | 2 ++ | ||
24 | scripts/device-crash-test | 1 - | ||
25 | 2 files changed, 2 insertions(+), 1 deletion(-) | ||
26 | |||
27 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/hw/arm/allwinner-a10.c | ||
30 | +++ b/hw/arm/allwinner-a10.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_class_init(ObjectClass *oc, void *data) | ||
32 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
33 | |||
34 | dc->realize = aw_a10_realize; | ||
35 | + /* Reason: Uses serial_hds in realize and nd_table in instance_init */ | ||
36 | + dc->user_creatable = false; | ||
37 | } | ||
38 | |||
39 | static const TypeInfo aw_a10_type_info = { | ||
40 | diff --git a/scripts/device-crash-test b/scripts/device-crash-test | ||
41 | index XXXXXXX..XXXXXXX 100755 | ||
42 | --- a/scripts/device-crash-test | ||
43 | +++ b/scripts/device-crash-test | ||
44 | @@ -XXX,XX +XXX,XX @@ ERROR_WHITELIST = [ | ||
45 | {'log':r"Device [\w.,-]+ can not be dynamically instantiated"}, | ||
46 | {'log':r"Platform Bus: Can not fit MMIO region of size "}, | ||
47 | # other more specific errors we will ignore: | ||
48 | - {'device':'allwinner-a10', 'log':"Unsupported NIC model:"}, | ||
49 | {'device':'.*-spapr-cpu-core', 'log':r"CPU core type should be"}, | ||
50 | {'log':r"MSI(-X)? is not supported by interrupt controller"}, | ||
51 | {'log':r"pxb-pcie? devices cannot reside on a PCIe? bus"}, | ||
52 | -- | ||
53 | 2.7.4 | ||
54 | |||
55 | diff view generated by jsdifflib |
1 | Make the CCR register banked if v8M security extensions are enabled. | 1 | From: Maxim Uvarov <maxim.uvarov@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This is slightly more complicated than the other "add banking" | 3 | qemu has 2 type of functions: shutdown and reboot. Shutdown |
4 | patches because there is one bit in the register which is not | 4 | function has to be used for machine shutdown. Otherwise we cause |
5 | banked. We keep the live data in the NS copy of the register, | 5 | a reset with a bogus "cause" value, when we intended a shutdown. |
6 | and adjust it on register reads and writes. (Since we don't | ||
7 | currently implement the behaviour that the bit controls, there | ||
8 | is nowhere else that needs to care.) | ||
9 | 6 | ||
10 | This patch includes the enforcement of the bits which are newly | 7 | Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org> |
11 | RES1 in ARMv8M. | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org | ||
10 | [PMM: tweaked commit message] | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/gpio/gpio_pwr.c | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
12 | 15 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c |
14 | Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org | ||
15 | --- | ||
16 | target/arm/cpu.h | 2 +- | ||
17 | hw/intc/armv7m_nvic.c | 33 +++++++++++++++++++++++++++------ | ||
18 | target/arm/cpu.c | 12 +++++++++--- | ||
19 | target/arm/helper.c | 5 +++-- | ||
20 | target/arm/machine.c | 3 ++- | ||
21 | 5 files changed, 42 insertions(+), 13 deletions(-) | ||
22 | |||
23 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/cpu.h | 18 | --- a/hw/gpio/gpio_pwr.c |
26 | +++ b/target/arm/cpu.h | 19 | +++ b/hw/gpio/gpio_pwr.c |
27 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 20 | @@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level) |
28 | uint32_t vecbase[2]; | 21 | static void gpio_pwr_shutdown(void *opaque, int n, int level) |
29 | uint32_t basepri[2]; | 22 | { |
30 | uint32_t control[2]; | 23 | if (level) { |
31 | - uint32_t ccr; /* Configuration and Control */ | 24 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
32 | + uint32_t ccr[2]; /* Configuration and Control */ | 25 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
33 | uint32_t cfsr; /* Configurable Fault Status */ | ||
34 | uint32_t hfsr; /* HardFault Status */ | ||
35 | uint32_t dfsr; /* Debug Fault Status Register */ | ||
36 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/intc/armv7m_nvic.c | ||
39 | +++ b/hw/intc/armv7m_nvic.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
41 | /* TODO: Implement SLEEPONEXIT. */ | ||
42 | return 0; | ||
43 | case 0xd14: /* Configuration Control. */ | ||
44 | - return cpu->env.v7m.ccr; | ||
45 | + /* The BFHFNMIGN bit is the only non-banked bit; we | ||
46 | + * keep it in the non-secure copy of the register. | ||
47 | + */ | ||
48 | + val = cpu->env.v7m.ccr[attrs.secure]; | ||
49 | + val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; | ||
50 | + return val; | ||
51 | case 0xd24: /* System Handler Status. */ | ||
52 | val = 0; | ||
53 | if (s->vectors[ARMV7M_EXCP_MEM].active) { | ||
54 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
55 | R_V7M_CCR_USERSETMPEND_MASK | | ||
56 | R_V7M_CCR_NONBASETHRDENA_MASK); | ||
57 | |||
58 | - cpu->env.v7m.ccr = value; | ||
59 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
60 | + /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ | ||
61 | + value |= R_V7M_CCR_NONBASETHRDENA_MASK | ||
62 | + | R_V7M_CCR_STKALIGN_MASK; | ||
63 | + } | ||
64 | + if (attrs.secure) { | ||
65 | + /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ | ||
66 | + cpu->env.v7m.ccr[M_REG_NS] = | ||
67 | + (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) | ||
68 | + | (value & R_V7M_CCR_BFHFNMIGN_MASK); | ||
69 | + value &= ~R_V7M_CCR_BFHFNMIGN_MASK; | ||
70 | + } | ||
71 | + | ||
72 | + cpu->env.v7m.ccr[attrs.secure] = value; | ||
73 | break; | ||
74 | case 0xd24: /* System Handler Control. */ | ||
75 | s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; | ||
76 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
77 | } | 26 | } |
78 | } | 27 | } |
79 | 28 | ||
80 | -static bool nvic_user_access_ok(NVICState *s, hwaddr offset) | ||
81 | +static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs) | ||
82 | { | ||
83 | /* Return true if unprivileged access to this register is permitted. */ | ||
84 | switch (offset) { | ||
85 | case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ | ||
86 | - return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK; | ||
87 | + /* For access via STIR_NS it is the NS CCR.USERSETMPEND that | ||
88 | + * controls access even though the CPU is in Secure state (I_QDKX). | ||
89 | + */ | ||
90 | + return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; | ||
91 | default: | ||
92 | /* All other user accesses cause a BusFault unconditionally */ | ||
93 | return false; | ||
94 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, | ||
95 | unsigned i, startvec, end; | ||
96 | uint32_t val; | ||
97 | |||
98 | - if (attrs.user && !nvic_user_access_ok(s, addr)) { | ||
99 | + if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { | ||
100 | /* Generate BusFault for unprivileged accesses */ | ||
101 | return MEMTX_ERROR; | ||
102 | } | ||
103 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, | ||
104 | |||
105 | trace_nvic_sysreg_write(addr, value, size); | ||
106 | |||
107 | - if (attrs.user && !nvic_user_access_ok(s, addr)) { | ||
108 | + if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { | ||
109 | /* Generate BusFault for unprivileged accesses */ | ||
110 | return MEMTX_ERROR; | ||
111 | } | ||
112 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/target/arm/cpu.c | ||
115 | +++ b/target/arm/cpu.c | ||
116 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
117 | env->v7m.secure = true; | ||
118 | } | ||
119 | |||
120 | - /* The reset value of this bit is IMPDEF, but ARM recommends | ||
121 | + /* In v7M the reset value of this bit is IMPDEF, but ARM recommends | ||
122 | * that it resets to 1, so QEMU always does that rather than making | ||
123 | - * it dependent on CPU model. | ||
124 | + * it dependent on CPU model. In v8M it is RES1. | ||
125 | */ | ||
126 | - env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; | ||
127 | + env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; | ||
128 | + env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; | ||
129 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
130 | + /* in v8M the NONBASETHRDENA bit [0] is RES1 */ | ||
131 | + env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; | ||
132 | + env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; | ||
133 | + } | ||
134 | |||
135 | /* Unlike A/R profile, M profile defines the reset LR value */ | ||
136 | env->regs[14] = 0xffffffff; | ||
137 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
138 | index XXXXXXX..XXXXXXX 100644 | ||
139 | --- a/target/arm/helper.c | ||
140 | +++ b/target/arm/helper.c | ||
141 | @@ -XXX,XX +XXX,XX @@ static void v7m_push_stack(ARMCPU *cpu) | ||
142 | uint32_t xpsr = xpsr_read(env); | ||
143 | |||
144 | /* Align stack pointer if the guest wants that */ | ||
145 | - if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { | ||
146 | + if ((env->regs[13] & 4) && | ||
147 | + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { | ||
148 | env->regs[13] -= 4; | ||
149 | xpsr |= XPSR_SPREALIGN; | ||
150 | } | ||
151 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
152 | /* fall through */ | ||
153 | case 9: /* Return to Thread using Main stack */ | ||
154 | if (!rettobase && | ||
155 | - !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) { | ||
156 | + !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MASK)) { | ||
157 | ufault = true; | ||
158 | } | ||
159 | break; | ||
160 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
161 | index XXXXXXX..XXXXXXX 100644 | ||
162 | --- a/target/arm/machine.c | ||
163 | +++ b/target/arm/machine.c | ||
164 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
165 | VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), | ||
166 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | ||
167 | VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), | ||
168 | - VMSTATE_UINT32(env.v7m.ccr, ARMCPU), | ||
169 | + VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), | ||
170 | VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | ||
171 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), | ||
172 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), | ||
173 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
174 | VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), | ||
175 | VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), | ||
176 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), | ||
177 | + VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), | ||
178 | VMSTATE_END_OF_LIST() | ||
179 | } | ||
180 | }; | ||
181 | -- | 29 | -- |
182 | 2.7.4 | 30 | 2.20.1 |
183 | 31 | ||
184 | 32 | diff view generated by jsdifflib |
1 | Make the VTOR register banked if v8M security extensions are enabled. | 1 | In do_ldst(), the calculation of the offset needs to be based on the |
---|---|---|---|
2 | size of the memory access, not the size of the elements in the | ||
3 | vector. This meant we were getting it wrong for the widening and | ||
4 | narrowing variants of the various VLDR and VSTR insns. | ||
2 | 5 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-2-peter.maydell@linaro.org |
6 | --- | 9 | --- |
7 | target/arm/cpu.h | 2 +- | 10 | target/arm/translate-mve.c | 17 +++++++++-------- |
8 | hw/intc/armv7m_nvic.c | 13 +++++++------ | 11 | 1 file changed, 9 insertions(+), 8 deletions(-) |
9 | target/arm/helper.c | 2 +- | ||
10 | target/arm/machine.c | 3 ++- | ||
11 | 4 files changed, 11 insertions(+), 9 deletions(-) | ||
12 | 12 | ||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/translate-mve.c |
16 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/translate-mve.c |
17 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 17 | @@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s) |
18 | |||
19 | struct { | ||
20 | uint32_t other_sp; | ||
21 | - uint32_t vecbase; | ||
22 | + uint32_t vecbase[2]; | ||
23 | uint32_t basepri[2]; | ||
24 | uint32_t control[2]; | ||
25 | uint32_t ccr; /* Configuration and Control */ | ||
26 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/hw/intc/armv7m_nvic.c | ||
29 | +++ b/hw/intc/armv7m_nvic.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level) | ||
31 | } | 18 | } |
32 | } | 19 | } |
33 | 20 | ||
34 | -static uint32_t nvic_readl(NVICState *s, uint32_t offset) | 21 | -static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) |
35 | +static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 22 | +static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, |
23 | + unsigned msize) | ||
36 | { | 24 | { |
37 | ARMCPU *cpu = s->cpu; | 25 | TCGv_i32 addr; |
38 | uint32_t val; | 26 | uint32_t offset; |
39 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) | 27 | @@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) |
40 | /* ISRPREEMPT not implemented */ | 28 | return true; |
41 | return val; | ||
42 | case 0xd08: /* Vector Table Offset. */ | ||
43 | - return cpu->env.v7m.vecbase; | ||
44 | + return cpu->env.v7m.vecbase[attrs.secure]; | ||
45 | case 0xd0c: /* Application Interrupt/Reset Control. */ | ||
46 | return 0xfa050000 | (s->prigroup << 8); | ||
47 | case 0xd10: /* System Control. */ | ||
48 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) | ||
49 | } | 29 | } |
30 | |||
31 | - offset = a->imm << a->size; | ||
32 | + offset = a->imm << msize; | ||
33 | if (!a->a) { | ||
34 | offset = -offset; | ||
35 | } | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) | ||
37 | { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, | ||
38 | { NULL, NULL } | ||
39 | }; | ||
40 | - return do_ldst(s, a, ldstfns[a->size][a->l]); | ||
41 | + return do_ldst(s, a, ldstfns[a->size][a->l], a->size); | ||
50 | } | 42 | } |
51 | 43 | ||
52 | -static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | 44 | -#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ |
53 | +static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 45 | +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ |
54 | + MemTxAttrs attrs) | 46 | static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ |
47 | { \ | ||
48 | static MVEGenLdStFn * const ldstfns[2][2] = { \ | ||
49 | { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ | ||
50 | { NULL, gen_helper_mve_##ULD }, \ | ||
51 | }; \ | ||
52 | - return do_ldst(s, a, ldstfns[a->u][a->l]); \ | ||
53 | + return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ | ||
54 | } | ||
55 | |||
56 | -DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) | ||
57 | -DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) | ||
58 | -DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) | ||
59 | +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) | ||
60 | +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) | ||
61 | +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) | ||
62 | |||
63 | static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
55 | { | 64 | { |
56 | ARMCPU *cpu = s->cpu; | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) | ||
59 | } | ||
60 | break; | ||
61 | case 0xd08: /* Vector Table Offset. */ | ||
62 | - cpu->env.v7m.vecbase = value & 0xffffff80; | ||
63 | + cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; | ||
64 | break; | ||
65 | case 0xd0c: /* Application Interrupt/Reset Control. */ | ||
66 | if ((value >> 16) == 0x05fa) { | ||
67 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, | ||
68 | break; | ||
69 | default: | ||
70 | if (size == 4) { | ||
71 | - val = nvic_readl(s, offset); | ||
72 | + val = nvic_readl(s, offset, attrs); | ||
73 | } else { | ||
74 | qemu_log_mask(LOG_GUEST_ERROR, | ||
75 | "NVIC: Bad read of size %d at offset 0x%x\n", | ||
76 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, | ||
77 | return MEMTX_OK; | ||
78 | } | ||
79 | if (size == 4) { | ||
80 | - nvic_writel(s, offset, value); | ||
81 | + nvic_writel(s, offset, value, attrs); | ||
82 | return MEMTX_OK; | ||
83 | } | ||
84 | qemu_log_mask(LOG_GUEST_ERROR, | ||
85 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/target/arm/helper.c | ||
88 | +++ b/target/arm/helper.c | ||
89 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu) | ||
90 | CPUState *cs = CPU(cpu); | ||
91 | CPUARMState *env = &cpu->env; | ||
92 | MemTxResult result; | ||
93 | - hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; | ||
94 | + hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4; | ||
95 | uint32_t addr; | ||
96 | |||
97 | addr = address_space_ldl(cs->as, vec, | ||
98 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/target/arm/machine.c | ||
101 | +++ b/target/arm/machine.c | ||
102 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
103 | .minimum_version_id = 4, | ||
104 | .needed = m_needed, | ||
105 | .fields = (VMStateField[]) { | ||
106 | - VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), | ||
107 | + VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), | ||
108 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | ||
109 | VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), | ||
110 | VMSTATE_UINT32(env.v7m.ccr, ARMCPU), | ||
111 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
112 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | ||
113 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | ||
114 | VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), | ||
115 | + VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), | ||
116 | VMSTATE_END_OF_LIST() | ||
117 | } | ||
118 | }; | ||
119 | -- | 65 | -- |
120 | 2.7.4 | 66 | 2.20.1 |
121 | 67 | ||
122 | 68 | diff view generated by jsdifflib |
1 | Make the MPU_CTRL register banked if v8M security extensions are | 1 | The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH |
---|---|---|---|
2 | enabled. | 2 | insns had some bugs: |
3 | * the 32x32 multiply of elements was being done as 32x32->32, | ||
4 | not 32x32->64 | ||
5 | * we were incorrectly maintaining the accumulator in its full | ||
6 | 72-bit form across all 4 beats of the insn; in the pseudocode | ||
7 | it is squashed back into the 64 bits of the RdaHi:RdaLo | ||
8 | registers after each beat | ||
3 | 9 | ||
10 | In particular, fixing the second of these allows us to recast | ||
11 | the implementation to avoid 128-bit arithmetic entirely. | ||
12 | |||
13 | Since the element size here is always 4, we can also drop the | ||
14 | parameterization of ESIZE to make the code a little more readable. | ||
15 | |||
16 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org | 19 | Message-id: 20210628135835.6690-3-peter.maydell@linaro.org |
7 | --- | 20 | --- |
8 | target/arm/cpu.h | 2 +- | 21 | target/arm/mve_helper.c | 38 +++++++++++++++++++++----------------- |
9 | hw/intc/armv7m_nvic.c | 9 +++++---- | 22 | 1 file changed, 21 insertions(+), 17 deletions(-) |
10 | target/arm/helper.c | 5 +++-- | ||
11 | target/arm/machine.c | 3 ++- | ||
12 | 4 files changed, 11 insertions(+), 8 deletions(-) | ||
13 | 23 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 24 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 26 | --- a/target/arm/mve_helper.c |
17 | +++ b/target/arm/cpu.h | 27 | +++ b/target/arm/mve_helper.c |
18 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 28 | @@ -XXX,XX +XXX,XX @@ |
19 | uint32_t dfsr; /* Debug Fault Status Register */ | 29 | */ |
20 | uint32_t mmfar; /* MemManage Fault Address */ | 30 | |
21 | uint32_t bfar; /* BusFault Address */ | 31 | #include "qemu/osdep.h" |
22 | - unsigned mpu_ctrl; /* MPU_CTRL */ | 32 | -#include "qemu/int128.h" |
23 | + unsigned mpu_ctrl[2]; /* MPU_CTRL */ | 33 | #include "cpu.h" |
24 | int exception; | 34 | #include "internals.h" |
25 | uint32_t primask[2]; | 35 | #include "vec_internal.h" |
26 | uint32_t faultmask[2]; | 36 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) |
27 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 37 | DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) |
28 | index XXXXXXX..XXXXXXX 100644 | 38 | |
29 | --- a/hw/intc/armv7m_nvic.c | 39 | /* |
30 | +++ b/hw/intc/armv7m_nvic.c | 40 | - * Rounding multiply add long dual accumulate high: we must keep |
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 41 | - * a 72-bit internal accumulator value and return the top 64 bits. |
32 | return cpu->pmsav7_dregion << 8; | 42 | + * Rounding multiply add long dual accumulate high. In the pseudocode |
33 | break; | 43 | + * this is implemented with a 72-bit internal accumulator value of which |
34 | case 0xd94: /* MPU_CTRL */ | 44 | + * the top 64 bits are returned. We optimize this to avoid having to |
35 | - return cpu->env.v7m.mpu_ctrl; | 45 | + * use 128-bit arithmetic -- we can do this because the 74-bit accumulator |
36 | + return cpu->env.v7m.mpu_ctrl[attrs.secure]; | 46 | + * is squashed back into 64-bits after each beat. |
37 | case 0xd98: /* MPU_RNR */ | 47 | */ |
38 | return cpu->env.pmsav7.rnr[attrs.secure]; | 48 | -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \ |
39 | case 0xd9c: /* MPU_RBAR */ | 49 | +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ |
40 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 50 | uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ |
41 | qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " | 51 | void *vm, uint64_t a) \ |
42 | "UNPREDICTABLE\n"); | 52 | { \ |
43 | } | 53 | uint16_t mask = mve_element_mask(env); \ |
44 | - cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK | | 54 | unsigned e; \ |
45 | - R_V7M_MPU_CTRL_HFNMIENA_MASK | | 55 | TYPE *n = vn, *m = vm; \ |
46 | - R_V7M_MPU_CTRL_PRIVDEFENA_MASK); | 56 | - Int128 acc = int128_lshift(TO128(a), 8); \ |
47 | + cpu->env.v7m.mpu_ctrl[attrs.secure] | 57 | - for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ |
48 | + = value & (R_V7M_MPU_CTRL_ENABLE_MASK | | 58 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ |
49 | + R_V7M_MPU_CTRL_HFNMIENA_MASK | | 59 | if (mask & 1) { \ |
50 | + R_V7M_MPU_CTRL_PRIVDEFENA_MASK); | 60 | + LTYPE mul; \ |
51 | tlb_flush(CPU(cpu)); | 61 | if (e & 1) { \ |
52 | break; | 62 | - acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \ |
53 | case 0xd98: /* MPU_RNR */ | 63 | - m[H##ESIZE(e)])); \ |
54 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 64 | + mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ |
55 | index XXXXXXX..XXXXXXX 100644 | 65 | + if (SUB) { \ |
56 | --- a/target/arm/helper.c | 66 | + mul = -mul; \ |
57 | +++ b/target/arm/helper.c | 67 | + } \ |
58 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env, | 68 | } else { \ |
59 | ARMMMUIdx mmu_idx) | 69 | - acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \ |
60 | { | 70 | - m[H##ESIZE(e)])); \ |
61 | if (arm_feature(env, ARM_FEATURE_M)) { | 71 | + mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ |
62 | - switch (env->v7m.mpu_ctrl & | 72 | } \ |
63 | + switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & | 73 | - acc = int128_add(acc, int128_make64(1 << 7)); \ |
64 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { | 74 | + mul = (mul >> 8) + ((mul >> 7) & 1); \ |
65 | case R_V7M_MPU_CTRL_ENABLE_MASK: | 75 | + a += mul; \ |
66 | /* Enabled, but not for HardFault and NMI */ | 76 | } \ |
67 | @@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, | 77 | } \ |
78 | mve_advance_vpt(env); \ | ||
79 | - return int128_getlo(int128_rshift(acc, 8)); \ | ||
80 | + return a; \ | ||
68 | } | 81 | } |
69 | 82 | ||
70 | if (arm_feature(env, ARM_FEATURE_M)) { | 83 | -DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64) |
71 | - return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | 84 | -DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64) |
72 | + return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] | 85 | +DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) |
73 | + & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | 86 | +DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) |
74 | } else { | 87 | |
75 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | 88 | -DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64) |
76 | } | 89 | +DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) |
77 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 90 | |
78 | index XXXXXXX..XXXXXXX 100644 | 91 | -DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64) |
79 | --- a/target/arm/machine.c | 92 | -DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64) |
80 | +++ b/target/arm/machine.c | 93 | +DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) |
81 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 94 | +DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) |
82 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), | 95 | |
83 | VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), | 96 | /* Vector add across vector */ |
84 | VMSTATE_UINT32(env.v7m.bfar, ARMCPU), | 97 | #define DO_VADDV(OP, ESIZE, TYPE) \ |
85 | - VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), | ||
86 | + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), | ||
87 | VMSTATE_INT32(env.v7m.exception, ARMCPU), | ||
88 | VMSTATE_END_OF_LIST() | ||
89 | }, | ||
90 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
91 | 0, vmstate_info_uint32, uint32_t), | ||
92 | VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), | ||
93 | VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), | ||
94 | + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), | ||
95 | VMSTATE_END_OF_LIST() | ||
96 | } | ||
97 | }; | ||
98 | -- | 98 | -- |
99 | 2.7.4 | 99 | 2.20.1 |
100 | 100 | ||
101 | 101 | diff view generated by jsdifflib |
1 | Set the MachineClass flag ignore_memory_transaction_failures | 1 | The function asimd_imm_const() in translate-neon.c is an |
---|---|---|---|
2 | for almost all ARM boards. This means they retain the legacy | 2 | implementation of the pseudocode AdvSIMDExpandImm(), which we will |
3 | behaviour that accesses to unimplemented addresses will RAZ/WI | 3 | also want for MVE. Move the implementation to translate.c, with a |
4 | rather than aborting, when a subsequent commit adds support | 4 | prototype in translate.h. |
5 | for external aborts. | ||
6 | |||
7 | The exceptions are: | ||
8 | * virt -- we know that guests won't try to prod devices | ||
9 | that we don't describe in the device tree or ACPI tables | ||
10 | * mps2 -- this board was written to use unimplemented-device | ||
11 | for all the ranges with devices we don't yet handle | ||
12 | |||
13 | New boards should not set the flag, but instead be written | ||
14 | like the mps2. | ||
15 | 5 | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
18 | Message-id: 1504626814-23124-3-git-send-email-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-4-peter.maydell@linaro.org |
19 | For the Xilinx boards: | ||
20 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
21 | --- | 9 | --- |
22 | hw/arm/aspeed.c | 3 +++ | 10 | target/arm/translate.h | 16 ++++++++++ |
23 | hw/arm/collie.c | 1 + | 11 | target/arm/translate-neon.c | 63 ------------------------------------- |
24 | hw/arm/cubieboard.c | 1 + | 12 | target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++ |
25 | hw/arm/digic_boards.c | 1 + | 13 | 3 files changed, 73 insertions(+), 63 deletions(-) |
26 | hw/arm/exynos4_boards.c | 2 ++ | ||
27 | hw/arm/gumstix.c | 2 ++ | ||
28 | hw/arm/highbank.c | 2 ++ | ||
29 | hw/arm/imx25_pdk.c | 1 + | ||
30 | hw/arm/integratorcp.c | 1 + | ||
31 | hw/arm/kzm.c | 1 + | ||
32 | hw/arm/mainstone.c | 1 + | ||
33 | hw/arm/musicpal.c | 1 + | ||
34 | hw/arm/netduino2.c | 1 + | ||
35 | hw/arm/nseries.c | 2 ++ | ||
36 | hw/arm/omap_sx1.c | 2 ++ | ||
37 | hw/arm/palm.c | 1 + | ||
38 | hw/arm/raspi.c | 1 + | ||
39 | hw/arm/realview.c | 4 ++++ | ||
40 | hw/arm/sabrelite.c | 1 + | ||
41 | hw/arm/spitz.c | 4 ++++ | ||
42 | hw/arm/stellaris.c | 2 ++ | ||
43 | hw/arm/tosa.c | 1 + | ||
44 | hw/arm/versatilepb.c | 2 ++ | ||
45 | hw/arm/vexpress.c | 1 + | ||
46 | hw/arm/xilinx_zynq.c | 1 + | ||
47 | hw/arm/xlnx-ep108.c | 2 ++ | ||
48 | hw/arm/z2.c | 1 + | ||
49 | 27 files changed, 43 insertions(+) | ||
50 | 14 | ||
51 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 15 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
52 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
53 | --- a/hw/arm/aspeed.c | 17 | --- a/target/arm/translate.h |
54 | +++ b/hw/arm/aspeed.c | 18 | +++ b/target/arm/translate.h |
55 | @@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data) | 19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) |
56 | mc->no_floppy = 1; | 20 | return opc | s->be_data; |
57 | mc->no_cdrom = 1; | ||
58 | mc->no_parallel = 1; | ||
59 | + mc->ignore_memory_transaction_failures = true; | ||
60 | } | 21 | } |
61 | 22 | ||
62 | static const TypeInfo palmetto_bmc_type = { | 23 | +/** |
63 | @@ -XXX,XX +XXX,XX @@ static void ast2500_evb_class_init(ObjectClass *oc, void *data) | 24 | + * asimd_imm_const: Expand an encoded SIMD constant value |
64 | mc->no_floppy = 1; | 25 | + * |
65 | mc->no_cdrom = 1; | 26 | + * Expand a SIMD constant value. This is essentially the pseudocode |
66 | mc->no_parallel = 1; | 27 | + * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for |
67 | + mc->ignore_memory_transaction_failures = true; | 28 | + * VMVN and VBIC (when cmode < 14 && op == 1). |
29 | + * | ||
30 | + * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; | ||
31 | + * callers must catch this. | ||
32 | + * | ||
33 | + * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but | ||
34 | + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; | ||
35 | + * we produce an immediate constant value of 0 in these cases. | ||
36 | + */ | ||
37 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); | ||
38 | + | ||
39 | #endif /* TARGET_ARM_TRANSLATE_H */ | ||
40 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/translate-neon.c | ||
43 | +++ b/target/arm/translate-neon.c | ||
44 | @@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh) | ||
45 | DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs) | ||
46 | DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu) | ||
47 | |||
48 | -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
49 | -{ | ||
50 | - /* | ||
51 | - * Expand the encoded constant. | ||
52 | - * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. | ||
53 | - * We choose to not special-case this and will behave as if a | ||
54 | - * valid constant encoding of 0 had been given. | ||
55 | - * cmode = 15 op = 1 must UNDEF; we assume decode has handled that. | ||
56 | - */ | ||
57 | - switch (cmode) { | ||
58 | - case 0: case 1: | ||
59 | - /* no-op */ | ||
60 | - break; | ||
61 | - case 2: case 3: | ||
62 | - imm <<= 8; | ||
63 | - break; | ||
64 | - case 4: case 5: | ||
65 | - imm <<= 16; | ||
66 | - break; | ||
67 | - case 6: case 7: | ||
68 | - imm <<= 24; | ||
69 | - break; | ||
70 | - case 8: case 9: | ||
71 | - imm |= imm << 16; | ||
72 | - break; | ||
73 | - case 10: case 11: | ||
74 | - imm = (imm << 8) | (imm << 24); | ||
75 | - break; | ||
76 | - case 12: | ||
77 | - imm = (imm << 8) | 0xff; | ||
78 | - break; | ||
79 | - case 13: | ||
80 | - imm = (imm << 16) | 0xffff; | ||
81 | - break; | ||
82 | - case 14: | ||
83 | - if (op) { | ||
84 | - /* | ||
85 | - * This is the only case where the top and bottom 32 bits | ||
86 | - * of the encoded constant differ. | ||
87 | - */ | ||
88 | - uint64_t imm64 = 0; | ||
89 | - int n; | ||
90 | - | ||
91 | - for (n = 0; n < 8; n++) { | ||
92 | - if (imm & (1 << n)) { | ||
93 | - imm64 |= (0xffULL << (n * 8)); | ||
94 | - } | ||
95 | - } | ||
96 | - return imm64; | ||
97 | - } | ||
98 | - imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
99 | - break; | ||
100 | - case 15: | ||
101 | - imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
102 | - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
103 | - break; | ||
104 | - } | ||
105 | - if (op) { | ||
106 | - imm = ~imm; | ||
107 | - } | ||
108 | - return dup_const(MO_32, imm); | ||
109 | -} | ||
110 | - | ||
111 | static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
112 | GVecGen2iFn *fn) | ||
113 | { | ||
114 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
115 | index XXXXXXX..XXXXXXX 100644 | ||
116 | --- a/target/arm/translate.c | ||
117 | +++ b/target/arm/translate.c | ||
118 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) | ||
119 | a64_translate_init(); | ||
68 | } | 120 | } |
69 | 121 | ||
70 | static const TypeInfo ast2500_evb_type = { | 122 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) |
71 | @@ -XXX,XX +XXX,XX @@ static void romulus_bmc_class_init(ObjectClass *oc, void *data) | 123 | +{ |
72 | mc->no_floppy = 1; | 124 | + /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */ |
73 | mc->no_cdrom = 1; | 125 | + switch (cmode) { |
74 | mc->no_parallel = 1; | 126 | + case 0: case 1: |
75 | + mc->ignore_memory_transaction_failures = true; | 127 | + /* no-op */ |
76 | } | 128 | + break; |
77 | 129 | + case 2: case 3: | |
78 | static const TypeInfo romulus_bmc_type = { | 130 | + imm <<= 8; |
79 | diff --git a/hw/arm/collie.c b/hw/arm/collie.c | 131 | + break; |
80 | index XXXXXXX..XXXXXXX 100644 | 132 | + case 4: case 5: |
81 | --- a/hw/arm/collie.c | 133 | + imm <<= 16; |
82 | +++ b/hw/arm/collie.c | 134 | + break; |
83 | @@ -XXX,XX +XXX,XX @@ static void collie_machine_init(MachineClass *mc) | 135 | + case 6: case 7: |
136 | + imm <<= 24; | ||
137 | + break; | ||
138 | + case 8: case 9: | ||
139 | + imm |= imm << 16; | ||
140 | + break; | ||
141 | + case 10: case 11: | ||
142 | + imm = (imm << 8) | (imm << 24); | ||
143 | + break; | ||
144 | + case 12: | ||
145 | + imm = (imm << 8) | 0xff; | ||
146 | + break; | ||
147 | + case 13: | ||
148 | + imm = (imm << 16) | 0xffff; | ||
149 | + break; | ||
150 | + case 14: | ||
151 | + if (op) { | ||
152 | + /* | ||
153 | + * This is the only case where the top and bottom 32 bits | ||
154 | + * of the encoded constant differ. | ||
155 | + */ | ||
156 | + uint64_t imm64 = 0; | ||
157 | + int n; | ||
158 | + | ||
159 | + for (n = 0; n < 8; n++) { | ||
160 | + if (imm & (1 << n)) { | ||
161 | + imm64 |= (0xffULL << (n * 8)); | ||
162 | + } | ||
163 | + } | ||
164 | + return imm64; | ||
165 | + } | ||
166 | + imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
167 | + break; | ||
168 | + case 15: | ||
169 | + imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
170 | + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
171 | + break; | ||
172 | + } | ||
173 | + if (op) { | ||
174 | + imm = ~imm; | ||
175 | + } | ||
176 | + return dup_const(MO_32, imm); | ||
177 | +} | ||
178 | + | ||
179 | /* Generate a label used for skipping this instruction */ | ||
180 | void arm_gen_condlabel(DisasContext *s) | ||
84 | { | 181 | { |
85 | mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)"; | ||
86 | mc->init = collie_init; | ||
87 | + mc->ignore_memory_transaction_failures = true; | ||
88 | } | ||
89 | |||
90 | DEFINE_MACHINE("collie", collie_machine_init) | ||
91 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | ||
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/hw/arm/cubieboard.c | ||
94 | +++ b/hw/arm/cubieboard.c | ||
95 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_machine_init(MachineClass *mc) | ||
96 | mc->init = cubieboard_init; | ||
97 | mc->block_default_type = IF_IDE; | ||
98 | mc->units_per_default_bus = 1; | ||
99 | + mc->ignore_memory_transaction_failures = true; | ||
100 | } | ||
101 | |||
102 | DEFINE_MACHINE("cubieboard", cubieboard_machine_init) | ||
103 | diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/hw/arm/digic_boards.c | ||
106 | +++ b/hw/arm/digic_boards.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static void canon_a1100_machine_init(MachineClass *mc) | ||
108 | { | ||
109 | mc->desc = "Canon PowerShot A1100 IS"; | ||
110 | mc->init = &canon_a1100_init; | ||
111 | + mc->ignore_memory_transaction_failures = true; | ||
112 | } | ||
113 | |||
114 | DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init) | ||
115 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | ||
116 | index XXXXXXX..XXXXXXX 100644 | ||
117 | --- a/hw/arm/exynos4_boards.c | ||
118 | +++ b/hw/arm/exynos4_boards.c | ||
119 | @@ -XXX,XX +XXX,XX @@ static void nuri_class_init(ObjectClass *oc, void *data) | ||
120 | mc->desc = "Samsung NURI board (Exynos4210)"; | ||
121 | mc->init = nuri_init; | ||
122 | mc->max_cpus = EXYNOS4210_NCPUS; | ||
123 | + mc->ignore_memory_transaction_failures = true; | ||
124 | } | ||
125 | |||
126 | static const TypeInfo nuri_type = { | ||
127 | @@ -XXX,XX +XXX,XX @@ static void smdkc210_class_init(ObjectClass *oc, void *data) | ||
128 | mc->desc = "Samsung SMDKC210 board (Exynos4210)"; | ||
129 | mc->init = smdkc210_init; | ||
130 | mc->max_cpus = EXYNOS4210_NCPUS; | ||
131 | + mc->ignore_memory_transaction_failures = true; | ||
132 | } | ||
133 | |||
134 | static const TypeInfo smdkc210_type = { | ||
135 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | ||
136 | index XXXXXXX..XXXXXXX 100644 | ||
137 | --- a/hw/arm/gumstix.c | ||
138 | +++ b/hw/arm/gumstix.c | ||
139 | @@ -XXX,XX +XXX,XX @@ static void connex_class_init(ObjectClass *oc, void *data) | ||
140 | |||
141 | mc->desc = "Gumstix Connex (PXA255)"; | ||
142 | mc->init = connex_init; | ||
143 | + mc->ignore_memory_transaction_failures = true; | ||
144 | } | ||
145 | |||
146 | static const TypeInfo connex_type = { | ||
147 | @@ -XXX,XX +XXX,XX @@ static void verdex_class_init(ObjectClass *oc, void *data) | ||
148 | |||
149 | mc->desc = "Gumstix Verdex (PXA270)"; | ||
150 | mc->init = verdex_init; | ||
151 | + mc->ignore_memory_transaction_failures = true; | ||
152 | } | ||
153 | |||
154 | static const TypeInfo verdex_type = { | ||
155 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
156 | index XXXXXXX..XXXXXXX 100644 | ||
157 | --- a/hw/arm/highbank.c | ||
158 | +++ b/hw/arm/highbank.c | ||
159 | @@ -XXX,XX +XXX,XX @@ static void highbank_class_init(ObjectClass *oc, void *data) | ||
160 | mc->block_default_type = IF_IDE; | ||
161 | mc->units_per_default_bus = 1; | ||
162 | mc->max_cpus = 4; | ||
163 | + mc->ignore_memory_transaction_failures = true; | ||
164 | } | ||
165 | |||
166 | static const TypeInfo highbank_type = { | ||
167 | @@ -XXX,XX +XXX,XX @@ static void midway_class_init(ObjectClass *oc, void *data) | ||
168 | mc->block_default_type = IF_IDE; | ||
169 | mc->units_per_default_bus = 1; | ||
170 | mc->max_cpus = 4; | ||
171 | + mc->ignore_memory_transaction_failures = true; | ||
172 | } | ||
173 | |||
174 | static const TypeInfo midway_type = { | ||
175 | diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c | ||
176 | index XXXXXXX..XXXXXXX 100644 | ||
177 | --- a/hw/arm/imx25_pdk.c | ||
178 | +++ b/hw/arm/imx25_pdk.c | ||
179 | @@ -XXX,XX +XXX,XX @@ static void imx25_pdk_machine_init(MachineClass *mc) | ||
180 | { | ||
181 | mc->desc = "ARM i.MX25 PDK board (ARM926)"; | ||
182 | mc->init = imx25_pdk_init; | ||
183 | + mc->ignore_memory_transaction_failures = true; | ||
184 | } | ||
185 | |||
186 | DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init) | ||
187 | diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c | ||
188 | index XXXXXXX..XXXXXXX 100644 | ||
189 | --- a/hw/arm/integratorcp.c | ||
190 | +++ b/hw/arm/integratorcp.c | ||
191 | @@ -XXX,XX +XXX,XX @@ static void integratorcp_machine_init(MachineClass *mc) | ||
192 | { | ||
193 | mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; | ||
194 | mc->init = integratorcp_init; | ||
195 | + mc->ignore_memory_transaction_failures = true; | ||
196 | } | ||
197 | |||
198 | DEFINE_MACHINE("integratorcp", integratorcp_machine_init) | ||
199 | diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/hw/arm/kzm.c | ||
202 | +++ b/hw/arm/kzm.c | ||
203 | @@ -XXX,XX +XXX,XX @@ static void kzm_machine_init(MachineClass *mc) | ||
204 | { | ||
205 | mc->desc = "ARM KZM Emulation Baseboard (ARM1136)"; | ||
206 | mc->init = kzm_init; | ||
207 | + mc->ignore_memory_transaction_failures = true; | ||
208 | } | ||
209 | |||
210 | DEFINE_MACHINE("kzm", kzm_machine_init) | ||
211 | diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c | ||
212 | index XXXXXXX..XXXXXXX 100644 | ||
213 | --- a/hw/arm/mainstone.c | ||
214 | +++ b/hw/arm/mainstone.c | ||
215 | @@ -XXX,XX +XXX,XX @@ static void mainstone2_machine_init(MachineClass *mc) | ||
216 | { | ||
217 | mc->desc = "Mainstone II (PXA27x)"; | ||
218 | mc->init = mainstone_init; | ||
219 | + mc->ignore_memory_transaction_failures = true; | ||
220 | } | ||
221 | |||
222 | DEFINE_MACHINE("mainstone", mainstone2_machine_init) | ||
223 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
224 | index XXXXXXX..XXXXXXX 100644 | ||
225 | --- a/hw/arm/musicpal.c | ||
226 | +++ b/hw/arm/musicpal.c | ||
227 | @@ -XXX,XX +XXX,XX @@ static void musicpal_machine_init(MachineClass *mc) | ||
228 | { | ||
229 | mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; | ||
230 | mc->init = musicpal_init; | ||
231 | + mc->ignore_memory_transaction_failures = true; | ||
232 | } | ||
233 | |||
234 | DEFINE_MACHINE("musicpal", musicpal_machine_init) | ||
235 | diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c | ||
236 | index XXXXXXX..XXXXXXX 100644 | ||
237 | --- a/hw/arm/netduino2.c | ||
238 | +++ b/hw/arm/netduino2.c | ||
239 | @@ -XXX,XX +XXX,XX @@ static void netduino2_machine_init(MachineClass *mc) | ||
240 | { | ||
241 | mc->desc = "Netduino 2 Machine"; | ||
242 | mc->init = netduino2_init; | ||
243 | + mc->ignore_memory_transaction_failures = true; | ||
244 | } | ||
245 | |||
246 | DEFINE_MACHINE("netduino2", netduino2_machine_init) | ||
247 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
248 | index XXXXXXX..XXXXXXX 100644 | ||
249 | --- a/hw/arm/nseries.c | ||
250 | +++ b/hw/arm/nseries.c | ||
251 | @@ -XXX,XX +XXX,XX @@ static void n800_class_init(ObjectClass *oc, void *data) | ||
252 | mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)"; | ||
253 | mc->init = n800_init; | ||
254 | mc->default_boot_order = ""; | ||
255 | + mc->ignore_memory_transaction_failures = true; | ||
256 | } | ||
257 | |||
258 | static const TypeInfo n800_type = { | ||
259 | @@ -XXX,XX +XXX,XX @@ static void n810_class_init(ObjectClass *oc, void *data) | ||
260 | mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)"; | ||
261 | mc->init = n810_init; | ||
262 | mc->default_boot_order = ""; | ||
263 | + mc->ignore_memory_transaction_failures = true; | ||
264 | } | ||
265 | |||
266 | static const TypeInfo n810_type = { | ||
267 | diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c | ||
268 | index XXXXXXX..XXXXXXX 100644 | ||
269 | --- a/hw/arm/omap_sx1.c | ||
270 | +++ b/hw/arm/omap_sx1.c | ||
271 | @@ -XXX,XX +XXX,XX @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) | ||
272 | |||
273 | mc->desc = "Siemens SX1 (OMAP310) V2"; | ||
274 | mc->init = sx1_init_v2; | ||
275 | + mc->ignore_memory_transaction_failures = true; | ||
276 | } | ||
277 | |||
278 | static const TypeInfo sx1_machine_v2_type = { | ||
279 | @@ -XXX,XX +XXX,XX @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) | ||
280 | |||
281 | mc->desc = "Siemens SX1 (OMAP310) V1"; | ||
282 | mc->init = sx1_init_v1; | ||
283 | + mc->ignore_memory_transaction_failures = true; | ||
284 | } | ||
285 | |||
286 | static const TypeInfo sx1_machine_v1_type = { | ||
287 | diff --git a/hw/arm/palm.c b/hw/arm/palm.c | ||
288 | index XXXXXXX..XXXXXXX 100644 | ||
289 | --- a/hw/arm/palm.c | ||
290 | +++ b/hw/arm/palm.c | ||
291 | @@ -XXX,XX +XXX,XX @@ static void palmte_machine_init(MachineClass *mc) | ||
292 | { | ||
293 | mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)"; | ||
294 | mc->init = palmte_init; | ||
295 | + mc->ignore_memory_transaction_failures = true; | ||
296 | } | ||
297 | |||
298 | DEFINE_MACHINE("cheetah", palmte_machine_init) | ||
299 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
300 | index XXXXXXX..XXXXXXX 100644 | ||
301 | --- a/hw/arm/raspi.c | ||
302 | +++ b/hw/arm/raspi.c | ||
303 | @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) | ||
304 | mc->no_cdrom = 1; | ||
305 | mc->max_cpus = BCM2836_NCPUS; | ||
306 | mc->default_ram_size = 1024 * 1024 * 1024; | ||
307 | + mc->ignore_memory_transaction_failures = true; | ||
308 | }; | ||
309 | DEFINE_MACHINE("raspi2", raspi2_machine_init) | ||
310 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | ||
311 | index XXXXXXX..XXXXXXX 100644 | ||
312 | --- a/hw/arm/realview.c | ||
313 | +++ b/hw/arm/realview.c | ||
314 | @@ -XXX,XX +XXX,XX @@ static void realview_eb_class_init(ObjectClass *oc, void *data) | ||
315 | mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; | ||
316 | mc->init = realview_eb_init; | ||
317 | mc->block_default_type = IF_SCSI; | ||
318 | + mc->ignore_memory_transaction_failures = true; | ||
319 | } | ||
320 | |||
321 | static const TypeInfo realview_eb_type = { | ||
322 | @@ -XXX,XX +XXX,XX @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) | ||
323 | mc->init = realview_eb_mpcore_init; | ||
324 | mc->block_default_type = IF_SCSI; | ||
325 | mc->max_cpus = 4; | ||
326 | + mc->ignore_memory_transaction_failures = true; | ||
327 | } | ||
328 | |||
329 | static const TypeInfo realview_eb_mpcore_type = { | ||
330 | @@ -XXX,XX +XXX,XX @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data) | ||
331 | |||
332 | mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; | ||
333 | mc->init = realview_pb_a8_init; | ||
334 | + mc->ignore_memory_transaction_failures = true; | ||
335 | } | ||
336 | |||
337 | static const TypeInfo realview_pb_a8_type = { | ||
338 | @@ -XXX,XX +XXX,XX @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) | ||
339 | mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; | ||
340 | mc->init = realview_pbx_a9_init; | ||
341 | mc->max_cpus = 4; | ||
342 | + mc->ignore_memory_transaction_failures = true; | ||
343 | } | ||
344 | |||
345 | static const TypeInfo realview_pbx_a9_type = { | ||
346 | diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c | ||
347 | index XXXXXXX..XXXXXXX 100644 | ||
348 | --- a/hw/arm/sabrelite.c | ||
349 | +++ b/hw/arm/sabrelite.c | ||
350 | @@ -XXX,XX +XXX,XX @@ static void sabrelite_machine_init(MachineClass *mc) | ||
351 | mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; | ||
352 | mc->init = sabrelite_init; | ||
353 | mc->max_cpus = FSL_IMX6_NUM_CPUS; | ||
354 | + mc->ignore_memory_transaction_failures = true; | ||
355 | } | ||
356 | |||
357 | DEFINE_MACHINE("sabrelite", sabrelite_machine_init) | ||
358 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | ||
359 | index XXXXXXX..XXXXXXX 100644 | ||
360 | --- a/hw/arm/spitz.c | ||
361 | +++ b/hw/arm/spitz.c | ||
362 | @@ -XXX,XX +XXX,XX @@ static void akitapda_class_init(ObjectClass *oc, void *data) | ||
363 | |||
364 | mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; | ||
365 | mc->init = akita_init; | ||
366 | + mc->ignore_memory_transaction_failures = true; | ||
367 | } | ||
368 | |||
369 | static const TypeInfo akitapda_type = { | ||
370 | @@ -XXX,XX +XXX,XX @@ static void spitzpda_class_init(ObjectClass *oc, void *data) | ||
371 | mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)"; | ||
372 | mc->init = spitz_init; | ||
373 | mc->block_default_type = IF_IDE; | ||
374 | + mc->ignore_memory_transaction_failures = true; | ||
375 | } | ||
376 | |||
377 | static const TypeInfo spitzpda_type = { | ||
378 | @@ -XXX,XX +XXX,XX @@ static void borzoipda_class_init(ObjectClass *oc, void *data) | ||
379 | mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; | ||
380 | mc->init = borzoi_init; | ||
381 | mc->block_default_type = IF_IDE; | ||
382 | + mc->ignore_memory_transaction_failures = true; | ||
383 | } | ||
384 | |||
385 | static const TypeInfo borzoipda_type = { | ||
386 | @@ -XXX,XX +XXX,XX @@ static void terrierpda_class_init(ObjectClass *oc, void *data) | ||
387 | mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)"; | ||
388 | mc->init = terrier_init; | ||
389 | mc->block_default_type = IF_IDE; | ||
390 | + mc->ignore_memory_transaction_failures = true; | ||
391 | } | ||
392 | |||
393 | static const TypeInfo terrierpda_type = { | ||
394 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | ||
395 | index XXXXXXX..XXXXXXX 100644 | ||
396 | --- a/hw/arm/stellaris.c | ||
397 | +++ b/hw/arm/stellaris.c | ||
398 | @@ -XXX,XX +XXX,XX @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data) | ||
399 | |||
400 | mc->desc = "Stellaris LM3S811EVB"; | ||
401 | mc->init = lm3s811evb_init; | ||
402 | + mc->ignore_memory_transaction_failures = true; | ||
403 | } | ||
404 | |||
405 | static const TypeInfo lm3s811evb_type = { | ||
406 | @@ -XXX,XX +XXX,XX @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) | ||
407 | |||
408 | mc->desc = "Stellaris LM3S6965EVB"; | ||
409 | mc->init = lm3s6965evb_init; | ||
410 | + mc->ignore_memory_transaction_failures = true; | ||
411 | } | ||
412 | |||
413 | static const TypeInfo lm3s6965evb_type = { | ||
414 | diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c | ||
415 | index XXXXXXX..XXXXXXX 100644 | ||
416 | --- a/hw/arm/tosa.c | ||
417 | +++ b/hw/arm/tosa.c | ||
418 | @@ -XXX,XX +XXX,XX @@ static void tosapda_machine_init(MachineClass *mc) | ||
419 | mc->desc = "Sharp SL-6000 (Tosa) PDA (PXA255)"; | ||
420 | mc->init = tosa_init; | ||
421 | mc->block_default_type = IF_IDE; | ||
422 | + mc->ignore_memory_transaction_failures = true; | ||
423 | } | ||
424 | |||
425 | DEFINE_MACHINE("tosa", tosapda_machine_init) | ||
426 | diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c | ||
427 | index XXXXXXX..XXXXXXX 100644 | ||
428 | --- a/hw/arm/versatilepb.c | ||
429 | +++ b/hw/arm/versatilepb.c | ||
430 | @@ -XXX,XX +XXX,XX @@ static void versatilepb_class_init(ObjectClass *oc, void *data) | ||
431 | mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; | ||
432 | mc->init = vpb_init; | ||
433 | mc->block_default_type = IF_SCSI; | ||
434 | + mc->ignore_memory_transaction_failures = true; | ||
435 | } | ||
436 | |||
437 | static const TypeInfo versatilepb_type = { | ||
438 | @@ -XXX,XX +XXX,XX @@ static void versatileab_class_init(ObjectClass *oc, void *data) | ||
439 | mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; | ||
440 | mc->init = vab_init; | ||
441 | mc->block_default_type = IF_SCSI; | ||
442 | + mc->ignore_memory_transaction_failures = true; | ||
443 | } | ||
444 | |||
445 | static const TypeInfo versatileab_type = { | ||
446 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | ||
447 | index XXXXXXX..XXXXXXX 100644 | ||
448 | --- a/hw/arm/vexpress.c | ||
449 | +++ b/hw/arm/vexpress.c | ||
450 | @@ -XXX,XX +XXX,XX @@ static void vexpress_class_init(ObjectClass *oc, void *data) | ||
451 | mc->desc = "ARM Versatile Express"; | ||
452 | mc->init = vexpress_common_init; | ||
453 | mc->max_cpus = 4; | ||
454 | + mc->ignore_memory_transaction_failures = true; | ||
455 | } | ||
456 | |||
457 | static void vexpress_a9_class_init(ObjectClass *oc, void *data) | ||
458 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c | ||
459 | index XXXXXXX..XXXXXXX 100644 | ||
460 | --- a/hw/arm/xilinx_zynq.c | ||
461 | +++ b/hw/arm/xilinx_zynq.c | ||
462 | @@ -XXX,XX +XXX,XX @@ static void zynq_machine_init(MachineClass *mc) | ||
463 | mc->init = zynq_init; | ||
464 | mc->max_cpus = 1; | ||
465 | mc->no_sdcard = 1; | ||
466 | + mc->ignore_memory_transaction_failures = true; | ||
467 | } | ||
468 | |||
469 | DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) | ||
470 | diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c | ||
471 | index XXXXXXX..XXXXXXX 100644 | ||
472 | --- a/hw/arm/xlnx-ep108.c | ||
473 | +++ b/hw/arm/xlnx-ep108.c | ||
474 | @@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_init(MachineClass *mc) | ||
475 | mc->init = xlnx_ep108_init; | ||
476 | mc->block_default_type = IF_IDE; | ||
477 | mc->units_per_default_bus = 1; | ||
478 | + mc->ignore_memory_transaction_failures = true; | ||
479 | } | ||
480 | |||
481 | DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) | ||
482 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_init(MachineClass *mc) | ||
483 | mc->init = xlnx_ep108_init; | ||
484 | mc->block_default_type = IF_IDE; | ||
485 | mc->units_per_default_bus = 1; | ||
486 | + mc->ignore_memory_transaction_failures = true; | ||
487 | } | ||
488 | |||
489 | DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) | ||
490 | diff --git a/hw/arm/z2.c b/hw/arm/z2.c | ||
491 | index XXXXXXX..XXXXXXX 100644 | ||
492 | --- a/hw/arm/z2.c | ||
493 | +++ b/hw/arm/z2.c | ||
494 | @@ -XXX,XX +XXX,XX @@ static void z2_machine_init(MachineClass *mc) | ||
495 | { | ||
496 | mc->desc = "Zipit Z2 (PXA27x)"; | ||
497 | mc->init = z2_init; | ||
498 | + mc->ignore_memory_transaction_failures = true; | ||
499 | } | ||
500 | |||
501 | DEFINE_MACHINE("z2", z2_machine_init) | ||
502 | -- | 182 | -- |
503 | 2.7.4 | 183 | 2.20.1 |
504 | 184 | ||
505 | 185 | diff view generated by jsdifflib |
1 | Make the MPU_RNR register banked if v8M security extensions are | 1 | The A64 AdvSIMD modified-immediate grouping uses almost the same |
---|---|---|---|
2 | enabled. | 2 | constant encoding that A32 Neon does; reuse asimd_imm_const() (to |
3 | which we add the AArch64-specific case for cmode 15 op 1) instead of | ||
4 | reimplementing it all. | ||
3 | 5 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 1503414539-28762-15-git-send-email-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-5-peter.maydell@linaro.org |
7 | --- | 9 | --- |
8 | target/arm/cpu.h | 2 +- | 10 | target/arm/translate.h | 3 +- |
9 | hw/intc/armv7m_nvic.c | 18 +++++++++--------- | 11 | target/arm/translate-a64.c | 86 ++++---------------------------------- |
10 | target/arm/cpu.c | 3 ++- | 12 | target/arm/translate.c | 17 +++++++- |
11 | target/arm/helper.c | 6 +++--- | 13 | 3 files changed, 24 insertions(+), 82 deletions(-) |
12 | target/arm/machine.c | 13 +++++++++++-- | ||
13 | 5 files changed, 26 insertions(+), 16 deletions(-) | ||
14 | 14 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/translate.h |
18 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/translate.h |
19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) |
20 | uint32_t *drbar; | 20 | * VMVN and VBIC (when cmode < 14 && op == 1). |
21 | uint32_t *drsr; | 21 | * |
22 | uint32_t *dracr; | 22 | * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; |
23 | - uint32_t rnr; | 23 | - * callers must catch this. |
24 | + uint32_t rnr[2]; | 24 | + * callers must catch this; we return the 64-bit constant value defined |
25 | } pmsav7; | 25 | + * for AArch64. |
26 | 26 | * | |
27 | /* PMSAv8 MPU */ | 27 | * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but |
28 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 28 | * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; |
29 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/intc/armv7m_nvic.c | 31 | --- a/target/arm/translate-a64.c |
31 | +++ b/hw/intc/armv7m_nvic.c | 32 | +++ b/target/arm/translate-a64.c |
32 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 33 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) |
33 | case 0xd94: /* MPU_CTRL */ | 34 | { |
34 | return cpu->env.v7m.mpu_ctrl; | 35 | int rd = extract32(insn, 0, 5); |
35 | case 0xd98: /* MPU_RNR */ | 36 | int cmode = extract32(insn, 12, 4); |
36 | - return cpu->env.pmsav7.rnr; | 37 | - int cmode_3_1 = extract32(cmode, 1, 3); |
37 | + return cpu->env.pmsav7.rnr[attrs.secure]; | 38 | - int cmode_0 = extract32(cmode, 0, 1); |
38 | case 0xd9c: /* MPU_RBAR */ | 39 | int o2 = extract32(insn, 11, 1); |
39 | case 0xda4: /* MPU_RBAR_A1 */ | 40 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); |
40 | case 0xdac: /* MPU_RBAR_A2 */ | 41 | bool is_neg = extract32(insn, 29, 1); |
41 | case 0xdb4: /* MPU_RBAR_A3 */ | 42 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) |
42 | { | ||
43 | - int region = cpu->env.pmsav7.rnr; | ||
44 | + int region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
45 | |||
46 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
47 | /* PMSAv8M handling of the aliases is different from v7M: | ||
48 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
49 | case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | ||
50 | case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | ||
51 | { | ||
52 | - int region = cpu->env.pmsav7.rnr; | ||
53 | + int region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
54 | |||
55 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
56 | /* PMSAv8M handling of the aliases is different from v7M: | ||
57 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
58 | PRIu32 "/%" PRIu32 "\n", | ||
59 | value, cpu->pmsav7_dregion); | ||
60 | } else { | ||
61 | - cpu->env.pmsav7.rnr = value; | ||
62 | + cpu->env.pmsav7.rnr[attrs.secure] = value; | ||
63 | } | ||
64 | break; | ||
65 | case 0xd9c: /* MPU_RBAR */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
67 | */ | ||
68 | int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | ||
69 | |||
70 | - region = cpu->env.pmsav7.rnr; | ||
71 | + region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
72 | if (aliasno) { | ||
73 | region = deposit32(region, 0, 2, aliasno); | ||
74 | } | ||
75 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
76 | region, cpu->pmsav7_dregion); | ||
77 | return; | ||
78 | } | ||
79 | - cpu->env.pmsav7.rnr = region; | ||
80 | + cpu->env.pmsav7.rnr[attrs.secure] = region; | ||
81 | } else { | ||
82 | - region = cpu->env.pmsav7.rnr; | ||
83 | + region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
84 | } | ||
85 | |||
86 | if (region >= cpu->pmsav7_dregion) { | ||
87 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
88 | case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | ||
89 | case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | ||
90 | { | ||
91 | - int region = cpu->env.pmsav7.rnr; | ||
92 | + int region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
93 | |||
94 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
95 | /* PMSAv8M handling of the aliases is different from v7M: | ||
96 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
97 | */ | ||
98 | int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | ||
99 | |||
100 | - region = cpu->env.pmsav7.rnr; | ||
101 | + region = cpu->env.pmsav7.rnr[attrs.secure]; | ||
102 | if (aliasno) { | ||
103 | region = deposit32(region, 0, 2, aliasno); | ||
104 | } | ||
105 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/cpu.c | ||
108 | +++ b/target/arm/cpu.c | ||
109 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
110 | sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | ||
111 | } | ||
112 | } | ||
113 | - env->pmsav7.rnr = 0; | ||
114 | + env->pmsav7.rnr[M_REG_NS] = 0; | ||
115 | + env->pmsav7.rnr[M_REG_S] = 0; | ||
116 | env->pmsav8.mair0[M_REG_NS] = 0; | ||
117 | env->pmsav8.mair0[M_REG_S] = 0; | ||
118 | env->pmsav8.mair1[M_REG_NS] = 0; | ||
119 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/target/arm/helper.c | ||
122 | +++ b/target/arm/helper.c | ||
123 | @@ -XXX,XX +XXX,XX @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
124 | return 0; | ||
125 | } | ||
126 | |||
127 | - u32p += env->pmsav7.rnr; | ||
128 | + u32p += env->pmsav7.rnr[M_REG_NS]; | ||
129 | return *u32p; | ||
130 | } | ||
131 | |||
132 | @@ -XXX,XX +XXX,XX @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
133 | return; | 43 | return; |
134 | } | 44 | } |
135 | 45 | ||
136 | - u32p += env->pmsav7.rnr; | 46 | - /* See AdvSIMDExpandImm() in ARM ARM */ |
137 | + u32p += env->pmsav7.rnr[M_REG_NS]; | 47 | - switch (cmode_3_1) { |
138 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | 48 | - case 0: /* Replicate(Zeros(24):imm8, 2) */ |
139 | *u32p = value; | 49 | - case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ |
140 | } | 50 | - case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ |
141 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | 51 | - case 3: /* Replicate(imm8:Zeros(24), 2) */ |
142 | .resetfn = arm_cp_reset_ignore }, | 52 | - { |
143 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, | 53 | - int shift = cmode_3_1 * 8; |
144 | .access = PL1_RW, | 54 | - imm = bitfield_replicate(abcdefgh << shift, 32); |
145 | - .fieldoffset = offsetof(CPUARMState, pmsav7.rnr), | 55 | - break; |
146 | + .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), | 56 | - } |
147 | .writefn = pmsav7_rgnr_write, | 57 | - case 4: /* Replicate(Zeros(8):imm8, 4) */ |
148 | .resetfn = arm_cp_reset_ignore }, | 58 | - case 5: /* Replicate(imm8:Zeros(8), 4) */ |
149 | REGINFO_SENTINEL | 59 | - { |
150 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 60 | - int shift = (cmode_3_1 & 0x1) * 8; |
61 | - imm = bitfield_replicate(abcdefgh << shift, 16); | ||
62 | - break; | ||
63 | - } | ||
64 | - case 6: | ||
65 | - if (cmode_0) { | ||
66 | - /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | ||
67 | - imm = (abcdefgh << 16) | 0xffff; | ||
68 | - } else { | ||
69 | - /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | ||
70 | - imm = (abcdefgh << 8) | 0xff; | ||
71 | - } | ||
72 | - imm = bitfield_replicate(imm, 32); | ||
73 | - break; | ||
74 | - case 7: | ||
75 | - if (!cmode_0 && !is_neg) { | ||
76 | - imm = bitfield_replicate(abcdefgh, 8); | ||
77 | - } else if (!cmode_0 && is_neg) { | ||
78 | - int i; | ||
79 | - imm = 0; | ||
80 | - for (i = 0; i < 8; i++) { | ||
81 | - if ((abcdefgh) & (1 << i)) { | ||
82 | - imm |= 0xffULL << (i * 8); | ||
83 | - } | ||
84 | - } | ||
85 | - } else if (cmode_0) { | ||
86 | - if (is_neg) { | ||
87 | - imm = (abcdefgh & 0x3f) << 48; | ||
88 | - if (abcdefgh & 0x80) { | ||
89 | - imm |= 0x8000000000000000ULL; | ||
90 | - } | ||
91 | - if (abcdefgh & 0x40) { | ||
92 | - imm |= 0x3fc0000000000000ULL; | ||
93 | - } else { | ||
94 | - imm |= 0x4000000000000000ULL; | ||
95 | - } | ||
96 | - } else { | ||
97 | - if (o2) { | ||
98 | - /* FMOV (vector, immediate) - half-precision */ | ||
99 | - imm = vfp_expand_imm(MO_16, abcdefgh); | ||
100 | - /* now duplicate across the lanes */ | ||
101 | - imm = bitfield_replicate(imm, 16); | ||
102 | - } else { | ||
103 | - imm = (abcdefgh & 0x3f) << 19; | ||
104 | - if (abcdefgh & 0x80) { | ||
105 | - imm |= 0x80000000; | ||
106 | - } | ||
107 | - if (abcdefgh & 0x40) { | ||
108 | - imm |= 0x3e000000; | ||
109 | - } else { | ||
110 | - imm |= 0x40000000; | ||
111 | - } | ||
112 | - imm |= (imm << 32); | ||
113 | - } | ||
114 | - } | ||
115 | - } | ||
116 | - break; | ||
117 | - default: | ||
118 | - g_assert_not_reached(); | ||
119 | - } | ||
120 | - | ||
121 | - if (cmode_3_1 != 7 && is_neg) { | ||
122 | - imm = ~imm; | ||
123 | + if (cmode == 15 && o2 && !is_neg) { | ||
124 | + /* FMOV (vector, immediate) - half-precision */ | ||
125 | + imm = vfp_expand_imm(MO_16, abcdefgh); | ||
126 | + /* now duplicate across the lanes */ | ||
127 | + imm = bitfield_replicate(imm, 16); | ||
128 | + } else { | ||
129 | + imm = asimd_imm_const(abcdefgh, cmode, is_neg); | ||
130 | } | ||
131 | |||
132 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { | ||
133 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
151 | index XXXXXXX..XXXXXXX 100644 | 134 | index XXXXXXX..XXXXXXX 100644 |
152 | --- a/target/arm/machine.c | 135 | --- a/target/arm/translate.c |
153 | +++ b/target/arm/machine.c | 136 | +++ b/target/arm/translate.c |
154 | @@ -XXX,XX +XXX,XX @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) | 137 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) |
155 | { | 138 | case 14: |
156 | ARMCPU *cpu = opaque; | 139 | if (op) { |
157 | 140 | /* | |
158 | - return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; | 141 | - * This is the only case where the top and bottom 32 bits |
159 | + return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; | 142 | - * of the encoded constant differ. |
160 | } | 143 | + * This and cmode == 15 op == 1 are the only cases where |
161 | 144 | + * the top and bottom 32 bits of the encoded constant differ. | |
162 | static const VMStateDescription vmstate_pmsav7 = { | 145 | */ |
163 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav7_rnr = { | 146 | uint64_t imm64 = 0; |
164 | .minimum_version_id = 1, | 147 | int n; |
165 | .needed = pmsav7_rnr_needed, | 148 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) |
166 | .fields = (VMStateField[]) { | 149 | imm |= (imm << 8) | (imm << 16) | (imm << 24); |
167 | - VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), | 150 | break; |
168 | + VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), | 151 | case 15: |
169 | VMSTATE_END_OF_LIST() | 152 | + if (op) { |
170 | } | 153 | + /* Reserved encoding for AArch32; valid for AArch64 */ |
171 | }; | 154 | + uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; |
172 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = { | 155 | + if (imm & 0x80) { |
173 | } | 156 | + imm64 |= 0x8000000000000000ULL; |
174 | }; | 157 | + } |
175 | 158 | + if (imm & 0x40) { | |
176 | +static bool s_rnr_vmstate_validate(void *opaque, int version_id) | 159 | + imm64 |= 0x3fc0000000000000ULL; |
177 | +{ | 160 | + } else { |
178 | + ARMCPU *cpu = opaque; | 161 | + imm64 |= 0x4000000000000000ULL; |
179 | + | 162 | + } |
180 | + return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; | 163 | + return imm64; |
181 | +} | 164 | + } |
182 | + | 165 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) |
183 | static bool m_security_needed(void *opaque) | 166 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); |
184 | { | 167 | break; |
185 | ARMCPU *cpu = opaque; | ||
186 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
187 | 0, vmstate_info_uint32, uint32_t), | ||
188 | VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, | ||
189 | 0, vmstate_info_uint32, uint32_t), | ||
190 | + VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), | ||
191 | + VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), | ||
192 | VMSTATE_END_OF_LIST() | ||
193 | } | ||
194 | }; | ||
195 | -- | 168 | -- |
196 | 2.7.4 | 169 | 2.20.1 |
197 | 170 | ||
198 | 171 | diff view generated by jsdifflib |
1 | Make the CFSR register banked if v8M security extensions are enabled. | 1 | Use dup_const() instead of bitfield_replicate() in |
---|---|---|---|
2 | disas_simd_mod_imm(). | ||
2 | 3 | ||
3 | Not all the bits in this register are banked: the BFSR | 4 | (We can't replace the other use of bitfield_replicate() in this file, |
4 | bits [15:8] are shared between S and NS, and we store them | 5 | in logic_imm_decode_wmask(), because that location needs to handle 2 |
5 | in the NS copy of the register. | 6 | and 4 bit elements, which dup_const() cannot.) |
6 | 7 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org | 10 | Message-id: 20210628135835.6690-6-peter.maydell@linaro.org |
10 | --- | 11 | --- |
11 | target/arm/cpu.h | 7 ++++++- | 12 | target/arm/translate-a64.c | 2 +- |
12 | hw/intc/armv7m_nvic.c | 15 +++++++++++++-- | 13 | 1 file changed, 1 insertion(+), 1 deletion(-) |
13 | target/arm/helper.c | 18 +++++++++--------- | ||
14 | target/arm/machine.c | 3 ++- | ||
15 | 4 files changed, 30 insertions(+), 13 deletions(-) | ||
16 | 14 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/translate-a64.c |
20 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/translate-a64.c |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) |
22 | uint32_t basepri[2]; | 20 | /* FMOV (vector, immediate) - half-precision */ |
23 | uint32_t control[2]; | 21 | imm = vfp_expand_imm(MO_16, abcdefgh); |
24 | uint32_t ccr[2]; /* Configuration and Control */ | 22 | /* now duplicate across the lanes */ |
25 | - uint32_t cfsr; /* Configurable Fault Status */ | 23 | - imm = bitfield_replicate(imm, 16); |
26 | + uint32_t cfsr[2]; /* Configurable Fault Status */ | 24 | + imm = dup_const(MO_16, imm); |
27 | uint32_t hfsr; /* HardFault Status */ | 25 | } else { |
28 | uint32_t dfsr; /* Debug Fault Status Register */ | 26 | imm = asimd_imm_const(abcdefgh, cmode, is_neg); |
29 | uint32_t mmfar[2]; /* MemManage Fault Address */ | ||
30 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_CFSR, NOCP, 16 + 3, 1) | ||
31 | FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) | ||
32 | FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) | ||
33 | |||
34 | +/* V7M CFSR bit masks covering all of the subregister bits */ | ||
35 | +FIELD(V7M_CFSR, MMFSR, 0, 8) | ||
36 | +FIELD(V7M_CFSR, BFSR, 8, 8) | ||
37 | +FIELD(V7M_CFSR, UFSR, 16, 16) | ||
38 | + | ||
39 | /* V7M HFSR bits */ | ||
40 | FIELD(V7M_HFSR, VECTTBL, 1, 1) | ||
41 | FIELD(V7M_HFSR, FORCED, 30, 1) | ||
42 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/intc/armv7m_nvic.c | ||
45 | +++ b/hw/intc/armv7m_nvic.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
47 | } | ||
48 | return val; | ||
49 | case 0xd28: /* Configurable Fault Status. */ | ||
50 | - return cpu->env.v7m.cfsr; | ||
51 | + /* The BFSR bits [15:8] are shared between security states | ||
52 | + * and we store them in the NS copy | ||
53 | + */ | ||
54 | + val = cpu->env.v7m.cfsr[attrs.secure]; | ||
55 | + val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; | ||
56 | + return val; | ||
57 | case 0xd2c: /* Hard Fault Status. */ | ||
58 | return cpu->env.v7m.hfsr; | ||
59 | case 0xd30: /* Debug Fault Status. */ | ||
60 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
61 | nvic_irq_update(s); | ||
62 | break; | ||
63 | case 0xd28: /* Configurable Fault Status. */ | ||
64 | - cpu->env.v7m.cfsr &= ~value; /* W1C */ | ||
65 | + cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */ | ||
66 | + if (attrs.secure) { | ||
67 | + /* The BFSR bits [15:8] are shared between security states | ||
68 | + * and we store them in the NS copy. | ||
69 | + */ | ||
70 | + cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); | ||
71 | + } | ||
72 | break; | ||
73 | case 0xd2c: /* Hard Fault Status. */ | ||
74 | cpu->env.v7m.hfsr &= ~value; /* W1C */ | ||
75 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/helper.c | ||
78 | +++ b/target/arm/helper.c | ||
79 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
80 | /* Bad exception return: instead of popping the exception | ||
81 | * stack, directly take a usage fault on the current stack. | ||
82 | */ | ||
83 | - env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; | ||
84 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | ||
85 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
86 | v7m_exception_taken(cpu, type | 0xf0000000); | ||
87 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | ||
88 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
89 | if (return_to_handler != arm_v7m_is_handler_mode(env)) { | ||
90 | /* Take an INVPC UsageFault by pushing the stack again. */ | ||
91 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
92 | - env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; | ||
93 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | ||
94 | v7m_push_stack(cpu); | ||
95 | v7m_exception_taken(cpu, type | 0xf0000000); | ||
96 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " | ||
97 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
98 | switch (cs->exception_index) { | ||
99 | case EXCP_UDEF: | ||
100 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
101 | - env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; | ||
102 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; | ||
103 | break; | ||
104 | case EXCP_NOCP: | ||
105 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
106 | - env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; | ||
107 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; | ||
108 | break; | ||
109 | case EXCP_INVSTATE: | ||
110 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | ||
111 | - env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK; | ||
112 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; | ||
113 | break; | ||
114 | case EXCP_SWI: | ||
115 | /* The PC already points to the next instruction. */ | ||
116 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
117 | case 0x8: /* External Abort */ | ||
118 | switch (cs->exception_index) { | ||
119 | case EXCP_PREFETCH_ABORT: | ||
120 | - env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK; | ||
121 | + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK; | ||
122 | qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); | ||
123 | break; | ||
124 | case EXCP_DATA_ABORT: | ||
125 | - env->v7m.cfsr |= | ||
126 | + env->v7m.cfsr[M_REG_NS] |= | ||
127 | (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); | ||
128 | env->v7m.bfar = env->exception.vaddress; | ||
129 | qemu_log_mask(CPU_LOG_INT, | ||
130 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
131 | */ | ||
132 | switch (cs->exception_index) { | ||
133 | case EXCP_PREFETCH_ABORT: | ||
134 | - env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK; | ||
135 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; | ||
136 | qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); | ||
137 | break; | ||
138 | case EXCP_DATA_ABORT: | ||
139 | - env->v7m.cfsr |= | ||
140 | + env->v7m.cfsr[env->v7m.secure] |= | ||
141 | (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); | ||
142 | env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; | ||
143 | qemu_log_mask(CPU_LOG_INT, | ||
144 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
145 | index XXXXXXX..XXXXXXX 100644 | ||
146 | --- a/target/arm/machine.c | ||
147 | +++ b/target/arm/machine.c | ||
148 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
149 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | ||
150 | VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), | ||
151 | VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), | ||
152 | - VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | ||
153 | + VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), | ||
154 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), | ||
155 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), | ||
156 | VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), | ||
157 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
158 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), | ||
159 | VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), | ||
160 | VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), | ||
161 | + VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), | ||
162 | VMSTATE_END_OF_LIST() | ||
163 | } | 27 | } |
164 | }; | ||
165 | -- | 28 | -- |
166 | 2.7.4 | 29 | 2.20.1 |
167 | 30 | ||
168 | 31 | diff view generated by jsdifflib |
1 | Make the MMFAR register banked if v8M security extensions are | 1 | Implement the MVE logical-immediate insns (VMOV, VMVN, |
---|---|---|---|
2 | enabled. | 2 | VORR and VBIC). These have essentially the same encoding |
3 | as their Neon equivalents, and we implement the decode | ||
4 | in the same way. | ||
3 | 5 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-7-peter.maydell@linaro.org |
7 | --- | 9 | --- |
8 | target/arm/cpu.h | 2 +- | 10 | target/arm/helper-mve.h | 4 +++ |
9 | hw/intc/armv7m_nvic.c | 4 ++-- | 11 | target/arm/mve.decode | 17 +++++++++++++ |
10 | target/arm/helper.c | 4 ++-- | 12 | target/arm/mve_helper.c | 24 ++++++++++++++++++ |
11 | target/arm/machine.c | 3 ++- | 13 | target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++ |
12 | 4 files changed, 7 insertions(+), 6 deletions(-) | 14 | 4 files changed, 95 insertions(+) |
13 | 15 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 18 | --- a/target/arm/helper-mve.h |
17 | +++ b/target/arm/cpu.h | 19 | +++ b/target/arm/helper-mve.h |
18 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) |
19 | uint32_t cfsr; /* Configurable Fault Status */ | 21 | DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) |
20 | uint32_t hfsr; /* HardFault Status */ | 22 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
21 | uint32_t dfsr; /* Debug Fault Status Register */ | 23 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
22 | - uint32_t mmfar; /* MemManage Fault Address */ | 24 | + |
23 | + uint32_t mmfar[2]; /* MemManage Fault Address */ | 25 | +DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) |
24 | uint32_t bfar; /* BusFault Address */ | 26 | +DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) |
25 | unsigned mpu_ctrl[2]; /* MPU_CTRL */ | 27 | +DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) |
26 | int exception; | 28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
27 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/hw/intc/armv7m_nvic.c | 30 | --- a/target/arm/mve.decode |
30 | +++ b/hw/intc/armv7m_nvic.c | 31 | +++ b/target/arm/mve.decode |
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 32 | @@ -XXX,XX +XXX,XX @@ |
32 | case 0xd30: /* Debug Fault Status. */ | 33 | # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit |
33 | return cpu->env.v7m.dfsr; | 34 | %size_28 28:1 !function=plus_1 |
34 | case 0xd34: /* MMFAR MemManage Fault Address */ | 35 | |
35 | - return cpu->env.v7m.mmfar; | 36 | +# 1imm format immediate |
36 | + return cpu->env.v7m.mmfar[attrs.secure]; | 37 | +%imm_28_16_0 28:1 16:3 0:4 |
37 | case 0xd38: /* Bus Fault Address. */ | 38 | + |
38 | return cpu->env.v7m.bfar; | 39 | &vldr_vstr rn qd imm p a w size l u |
39 | case 0xd3c: /* Aux Fault Status. */ | 40 | &1op qd qm size |
40 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 41 | &2op qd qm qn size |
41 | cpu->env.v7m.dfsr &= ~value; /* W1C */ | 42 | &2scalar qd qn rm size |
42 | break; | 43 | +&1imm qd imm cmode op |
43 | case 0xd34: /* Mem Manage Address. */ | 44 | |
44 | - cpu->env.v7m.mmfar = value; | 45 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 |
45 | + cpu->env.v7m.mmfar[attrs.secure] = value; | 46 | # Note that both Rn and Qd are 3 bits only (no D bit) |
46 | return; | 47 | @@ -XXX,XX +XXX,XX @@ |
47 | case 0xd38: /* Bus Fault Address. */ | 48 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 |
48 | cpu->env.v7m.bfar = value; | 49 | @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \ |
49 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 50 | size=%size_28 |
51 | +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0 | ||
52 | |||
53 | # The _rev suffix indicates that Vn and Vm are reversed. This is | ||
54 | # the case for shifts. In the Arm ARM these insns are documented | ||
55 | @@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd | ||
56 | # Predicate operations | ||
57 | %mask_22_13 22:1 13:3 | ||
58 | VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
59 | + | ||
60 | +# Logical immediate operations (1 reg and modified-immediate) | ||
61 | + | ||
62 | +# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but | ||
63 | +# not in a way we can conveniently represent in decodetree without | ||
64 | +# a lot of repetition: | ||
65 | +# VORR: op=0, (cmode & 1) && cmode < 12 | ||
66 | +# VBIC: op=1, (cmode & 1) && cmode < 12 | ||
67 | +# VMOV: everything else | ||
68 | +# So we have a single decode line and check the cmode/op in the | ||
69 | +# trans function. | ||
70 | +Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
71 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | 72 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/target/arm/helper.c | 73 | --- a/target/arm/mve_helper.c |
52 | +++ b/target/arm/helper.c | 74 | +++ b/target/arm/mve_helper.c |
53 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 75 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG) |
54 | case EXCP_DATA_ABORT: | 76 | DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) |
55 | env->v7m.cfsr |= | 77 | DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) |
56 | (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); | 78 | |
57 | - env->v7m.mmfar = env->exception.vaddress; | 79 | +/* |
58 | + env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; | 80 | + * 1 operand immediates: Vda is destination and possibly also one source. |
59 | qemu_log_mask(CPU_LOG_INT, | 81 | + * All these insns work at 64-bit widths. |
60 | "...with CFSR.DACCVIOL and MMFAR 0x%x\n", | 82 | + */ |
61 | - env->v7m.mmfar); | 83 | +#define DO_1OP_IMM(OP, FN) \ |
62 | + env->v7m.mmfar[env->v7m.secure]); | 84 | + void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ |
63 | break; | 85 | + { \ |
64 | } | 86 | + uint64_t *da = vda; \ |
65 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); | 87 | + uint16_t mask = mve_element_mask(env); \ |
66 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 88 | + unsigned e; \ |
89 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ | ||
90 | + mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ | ||
91 | + } \ | ||
92 | + mve_advance_vpt(env); \ | ||
93 | + } | ||
94 | + | ||
95 | +#define DO_MOVI(N, I) (I) | ||
96 | +#define DO_ANDI(N, I) ((N) & (I)) | ||
97 | +#define DO_ORRI(N, I) ((N) | (I)) | ||
98 | + | ||
99 | +DO_1OP_IMM(vmovi, DO_MOVI) | ||
100 | +DO_1OP_IMM(vandi, DO_ANDI) | ||
101 | +DO_1OP_IMM(vorri, DO_ORRI) | ||
102 | + | ||
103 | #define DO_2OP(OP, ESIZE, TYPE, FN) \ | ||
104 | void HELPER(glue(mve_, OP))(CPUARMState *env, \ | ||
105 | void *vd, void *vn, void *vm) \ | ||
106 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | 107 | index XXXXXXX..XXXXXXX 100644 |
68 | --- a/target/arm/machine.c | 108 | --- a/target/arm/translate-mve.c |
69 | +++ b/target/arm/machine.c | 109 | +++ b/target/arm/translate-mve.c |
70 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 110 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); |
71 | VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | 111 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); |
72 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), | 112 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); |
73 | VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), | 113 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); |
74 | - VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), | 114 | +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); |
75 | + VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), | 115 | |
76 | VMSTATE_UINT32(env.v7m.bfar, ARMCPU), | 116 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ |
77 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), | 117 | static inline long mve_qreg_offset(unsigned reg) |
78 | VMSTATE_INT32(env.v7m.exception, ARMCPU), | 118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) |
79 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 119 | mve_update_eci(s); |
80 | VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), | 120 | return true; |
81 | VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), | 121 | } |
82 | VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), | 122 | + |
83 | + VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), | 123 | +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) |
84 | VMSTATE_END_OF_LIST() | 124 | +{ |
85 | } | 125 | + TCGv_ptr qd; |
86 | }; | 126 | + uint64_t imm; |
127 | + | ||
128 | + if (!dc_isar_feature(aa32_mve, s) || | ||
129 | + !mve_check_qreg_bank(s, a->qd) || | ||
130 | + !fn) { | ||
131 | + return false; | ||
132 | + } | ||
133 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
134 | + return true; | ||
135 | + } | ||
136 | + | ||
137 | + imm = asimd_imm_const(a->imm, a->cmode, a->op); | ||
138 | + | ||
139 | + qd = mve_qreg_ptr(a->qd); | ||
140 | + fn(cpu_env, qd, tcg_constant_i64(imm)); | ||
141 | + tcg_temp_free_ptr(qd); | ||
142 | + mve_update_eci(s); | ||
143 | + return true; | ||
144 | +} | ||
145 | + | ||
146 | +static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
147 | +{ | ||
148 | + /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ | ||
149 | + MVEGenOneOpImmFn *fn; | ||
150 | + | ||
151 | + if ((a->cmode & 1) && a->cmode < 12) { | ||
152 | + if (a->op) { | ||
153 | + /* | ||
154 | + * For op=1, the immediate will be inverted by asimd_imm_const(), | ||
155 | + * so the VBIC becomes a logical AND operation. | ||
156 | + */ | ||
157 | + fn = gen_helper_mve_vandi; | ||
158 | + } else { | ||
159 | + fn = gen_helper_mve_vorri; | ||
160 | + } | ||
161 | + } else { | ||
162 | + /* There is one unallocated cmode/op combination in this space */ | ||
163 | + if (a->cmode == 15 && a->op == 1) { | ||
164 | + return false; | ||
165 | + } | ||
166 | + /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ | ||
167 | + fn = gen_helper_mve_vmovi; | ||
168 | + } | ||
169 | + return do_1imm(s, a, fn); | ||
170 | +} | ||
87 | -- | 171 | -- |
88 | 2.7.4 | 172 | 2.20.1 |
89 | 173 | ||
90 | 174 | diff view generated by jsdifflib |
1 | If a v8M CPU supports the security extension then we need to | 1 | Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL |
---|---|---|---|
2 | give it two AddressSpaces, the same way we do already for | 2 | and VQSHLU. |
3 | an A profile core with EL3. | 3 | |
4 | The size-and-immediate encoding here is the same as Neon, and we | ||
5 | handle it the same way neon-dp.decode does. | ||
4 | 6 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 1503414539-28762-5-git-send-email-peter.maydell@linaro.org | 9 | Message-id: 20210628135835.6690-8-peter.maydell@linaro.org |
8 | --- | 10 | --- |
9 | target/arm/cpu.c | 13 ++++++------- | 11 | target/arm/helper-mve.h | 16 +++++++++++ |
10 | 1 file changed, 6 insertions(+), 7 deletions(-) | 12 | target/arm/mve.decode | 23 +++++++++++++++ |
11 | 13 | target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ | |
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++ |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | 4 files changed, 147 insertions(+) |
14 | --- a/target/arm/cpu.c | 16 | |
15 | +++ b/target/arm/cpu.c | 17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
16 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | init_cpreg_list(cpu); | 19 | --- a/target/arm/helper-mve.h |
18 | 20 | +++ b/target/arm/helper-mve.h | |
19 | #ifndef CONFIG_USER_ONLY | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
20 | - if (cpu->has_el3) { | 22 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) |
21 | - cs->num_ases = 2; | 23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) |
22 | - } else { | 24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) |
23 | - cs->num_ases = 1; | 25 | + |
24 | - } | 26 | +DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | - | 27 | +DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | - if (cpu->has_el3) { | 28 | +DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 29 | + |
28 | AddressSpace *as; | 30 | +DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
29 | 31 | +DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
30 | + cs->num_ases = 2; | 32 | +DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | + | 33 | + |
32 | if (!cpu->secure_memory) { | 34 | +DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | cpu->secure_memory = cs->memory; | 35 | +DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | } | 36 | +DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
35 | as = address_space_init_shareable(cpu->secure_memory, | 37 | + |
36 | "cpu-secure-memory"); | 38 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
37 | cpu_address_space_init(cs, as, ARMASIdx_S); | 39 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
38 | + } else { | 40 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
39 | + cs->num_ases = 1; | 41 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/mve.decode | ||
44 | +++ b/target/arm/mve.decode | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | &2op qd qm qn size | ||
47 | &2scalar qd qn rm size | ||
48 | &1imm qd imm cmode op | ||
49 | +&2shift qd qm shift size | ||
50 | |||
51 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
52 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
55 | @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
56 | |||
57 | +@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 | ||
58 | +@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
59 | +@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
60 | + | ||
61 | # Vector loads and stores | ||
62 | |||
63 | # Widening loads and narrowing stores: | ||
64 | @@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
65 | # So we have a single decode line and check the cmode/op in the | ||
66 | # trans function. | ||
67 | Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
68 | + | ||
69 | +# Shifts by immediate | ||
70 | + | ||
71 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
72 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
73 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
74 | + | ||
75 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
76 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
77 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
78 | + | ||
79 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
80 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
81 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
82 | + | ||
83 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
84 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
85 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
86 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/target/arm/mve_helper.c | ||
89 | +++ b/target/arm/mve_helper.c | ||
90 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) | ||
91 | WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) | ||
92 | #define DO_UQRSHL_OP(N, M, satp) \ | ||
93 | WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) | ||
94 | +#define DO_SUQSHL_OP(N, M, satp) \ | ||
95 | + WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) | ||
96 | |||
97 | DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) | ||
98 | DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) | ||
99 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t) | ||
100 | DO_VADDV(vaddvub, 1, uint8_t) | ||
101 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
102 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
103 | + | ||
104 | +/* Shifts by immediate */ | ||
105 | +#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
106 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
107 | + void *vm, uint32_t shift) \ | ||
108 | + { \ | ||
109 | + TYPE *d = vd, *m = vm; \ | ||
110 | + uint16_t mask = mve_element_mask(env); \ | ||
111 | + unsigned e; \ | ||
112 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
113 | + mergemask(&d[H##ESIZE(e)], \ | ||
114 | + FN(m[H##ESIZE(e)], shift), mask); \ | ||
115 | + } \ | ||
116 | + mve_advance_vpt(env); \ | ||
117 | + } | ||
118 | + | ||
119 | +#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ | ||
120 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
121 | + void *vm, uint32_t shift) \ | ||
122 | + { \ | ||
123 | + TYPE *d = vd, *m = vm; \ | ||
124 | + uint16_t mask = mve_element_mask(env); \ | ||
125 | + unsigned e; \ | ||
126 | + bool qc = false; \ | ||
127 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
128 | + bool sat = false; \ | ||
129 | + mergemask(&d[H##ESIZE(e)], \ | ||
130 | + FN(m[H##ESIZE(e)], shift, &sat), mask); \ | ||
131 | + qc |= sat & mask & 1; \ | ||
132 | + } \ | ||
133 | + if (qc) { \ | ||
134 | + env->vfp.qc[0] = qc; \ | ||
135 | + } \ | ||
136 | + mve_advance_vpt(env); \ | ||
137 | + } | ||
138 | + | ||
139 | +/* provide unsigned 2-op shift helpers for all sizes */ | ||
140 | +#define DO_2SHIFT_U(OP, FN) \ | ||
141 | + DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
142 | + DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
143 | + DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
144 | + | ||
145 | +#define DO_2SHIFT_SAT_U(OP, FN) \ | ||
146 | + DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
147 | + DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ | ||
148 | + DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) | ||
149 | +#define DO_2SHIFT_SAT_S(OP, FN) \ | ||
150 | + DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ | ||
151 | + DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ | ||
152 | + DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
153 | + | ||
154 | +DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
155 | +DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
156 | +DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
157 | +DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
158 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
159 | index XXXXXXX..XXXXXXX 100644 | ||
160 | --- a/target/arm/translate-mve.c | ||
161 | +++ b/target/arm/translate-mve.c | ||
162 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
163 | typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
164 | typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
165 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
166 | +typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
167 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
168 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
169 | typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
170 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
40 | } | 171 | } |
41 | + | 172 | return do_1imm(s, a, fn); |
42 | cpu_address_space_init(cs, | 173 | } |
43 | address_space_init_shareable(cs->memory, | 174 | + |
44 | "cpu-memory"), | 175 | +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, |
176 | + bool negateshift) | ||
177 | +{ | ||
178 | + TCGv_ptr qd, qm; | ||
179 | + int shift = a->shift; | ||
180 | + | ||
181 | + if (!dc_isar_feature(aa32_mve, s) || | ||
182 | + !mve_check_qreg_bank(s, a->qd | a->qm) || | ||
183 | + !fn) { | ||
184 | + return false; | ||
185 | + } | ||
186 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
187 | + return true; | ||
188 | + } | ||
189 | + | ||
190 | + /* | ||
191 | + * When we handle a right shift insn using a left-shift helper | ||
192 | + * which permits a negative shift count to indicate a right-shift, | ||
193 | + * we must negate the shift count. | ||
194 | + */ | ||
195 | + if (negateshift) { | ||
196 | + shift = -shift; | ||
197 | + } | ||
198 | + | ||
199 | + qd = mve_qreg_ptr(a->qd); | ||
200 | + qm = mve_qreg_ptr(a->qm); | ||
201 | + fn(cpu_env, qd, qm, tcg_constant_i32(shift)); | ||
202 | + tcg_temp_free_ptr(qd); | ||
203 | + tcg_temp_free_ptr(qm); | ||
204 | + mve_update_eci(s); | ||
205 | + return true; | ||
206 | +} | ||
207 | + | ||
208 | +#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ | ||
209 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
210 | + { \ | ||
211 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
212 | + gen_helper_mve_##FN##b, \ | ||
213 | + gen_helper_mve_##FN##h, \ | ||
214 | + gen_helper_mve_##FN##w, \ | ||
215 | + NULL, \ | ||
216 | + }; \ | ||
217 | + return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ | ||
218 | + } | ||
219 | + | ||
220 | +DO_2SHIFT(VSHLI, vshli_u, false) | ||
221 | +DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
222 | +DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
223 | +DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
45 | -- | 224 | -- |
46 | 2.7.4 | 225 | 2.20.1 |
47 | 226 | ||
48 | 227 | diff view generated by jsdifflib |
1 | Move the regime_is_secure() utility function to internals.h; | 1 | Implement the MVE vector shift right by immediate insns VSHRI and |
---|---|---|---|
2 | we are going to want to call it from translate.c. | 2 | VRSHRI. As with Neon, we implement these by using helper functions |
3 | which perform left shifts but allow negative shift counts to indicate | ||
4 | right shifts. | ||
3 | 5 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 1503414539-28762-20-git-send-email-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-9-peter.maydell@linaro.org |
7 | --- | 9 | --- |
8 | target/arm/internals.h | 26 ++++++++++++++++++++++++++ | 10 | target/arm/helper-mve.h | 12 ++++++++++++ |
9 | target/arm/helper.c | 26 -------------------------- | 11 | target/arm/translate.h | 20 ++++++++++++++++++++ |
10 | 2 files changed, 26 insertions(+), 26 deletions(-) | 12 | target/arm/mve.decode | 28 ++++++++++++++++++++++++++++ |
13 | target/arm/mve_helper.c | 7 +++++++ | ||
14 | target/arm/translate-mve.c | 5 +++++ | ||
15 | target/arm/translate-neon.c | 18 ------------------ | ||
16 | 6 files changed, 72 insertions(+), 18 deletions(-) | ||
11 | 17 | ||
12 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
13 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/internals.h | 20 | --- a/target/arm/helper-mve.h |
15 | +++ b/target/arm/internals.h | 21 | +++ b/target/arm/helper-mve.h |
16 | @@ -XXX,XX +XXX,XX @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) | 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) |
17 | } | 23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) |
24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
25 | |||
26 | +DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
29 | + | ||
30 | DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
34 | DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
35 | DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
36 | DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
37 | + | ||
38 | +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | + | ||
42 | +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
43 | +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
44 | +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
45 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate.h | ||
48 | +++ b/target/arm/translate.h | ||
49 | @@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x) | ||
50 | return x * 2 + 1; | ||
18 | } | 51 | } |
19 | 52 | ||
20 | +/* Return true if this address translation regime is secure */ | 53 | +static inline int rsub_64(DisasContext *s, int x) |
21 | +static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
22 | +{ | 54 | +{ |
23 | + switch (mmu_idx) { | 55 | + return 64 - x; |
24 | + case ARMMMUIdx_S12NSE0: | ||
25 | + case ARMMMUIdx_S12NSE1: | ||
26 | + case ARMMMUIdx_S1NSE0: | ||
27 | + case ARMMMUIdx_S1NSE1: | ||
28 | + case ARMMMUIdx_S1E2: | ||
29 | + case ARMMMUIdx_S2NS: | ||
30 | + case ARMMMUIdx_MPriv: | ||
31 | + case ARMMMUIdx_MNegPri: | ||
32 | + case ARMMMUIdx_MUser: | ||
33 | + return false; | ||
34 | + case ARMMMUIdx_S1E3: | ||
35 | + case ARMMMUIdx_S1SE0: | ||
36 | + case ARMMMUIdx_S1SE1: | ||
37 | + case ARMMMUIdx_MSPriv: | ||
38 | + case ARMMMUIdx_MSNegPri: | ||
39 | + case ARMMMUIdx_MSUser: | ||
40 | + return true; | ||
41 | + default: | ||
42 | + g_assert_not_reached(); | ||
43 | + } | ||
44 | +} | 56 | +} |
45 | + | 57 | + |
46 | #endif | 58 | +static inline int rsub_32(DisasContext *s, int x) |
47 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 59 | +{ |
60 | + return 32 - x; | ||
61 | +} | ||
62 | + | ||
63 | +static inline int rsub_16(DisasContext *s, int x) | ||
64 | +{ | ||
65 | + return 16 - x; | ||
66 | +} | ||
67 | + | ||
68 | +static inline int rsub_8(DisasContext *s, int x) | ||
69 | +{ | ||
70 | + return 8 - x; | ||
71 | +} | ||
72 | + | ||
73 | static inline int arm_dc_feature(DisasContext *dc, int feature) | ||
74 | { | ||
75 | return (dc->features & (1ULL << feature)) != 0; | ||
76 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
48 | index XXXXXXX..XXXXXXX 100644 | 77 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/target/arm/helper.c | 78 | --- a/target/arm/mve.decode |
50 | +++ b/target/arm/helper.c | 79 | +++ b/target/arm/mve.decode |
51 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | 80 | @@ -XXX,XX +XXX,XX @@ |
52 | } | 81 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
82 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
83 | |||
84 | +# Right shifts are encoded as N - shift, where N is the element size in bits. | ||
85 | +%rshift_i5 16:5 !function=rsub_32 | ||
86 | +%rshift_i4 16:4 !function=rsub_16 | ||
87 | +%rshift_i3 16:3 !function=rsub_8 | ||
88 | + | ||
89 | +@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
90 | + size=0 shift=%rshift_i3 | ||
91 | +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
92 | + size=1 shift=%rshift_i4 | ||
93 | +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
94 | + size=2 shift=%rshift_i5 | ||
95 | + | ||
96 | # Vector loads and stores | ||
97 | |||
98 | # Widening loads and narrowing stores: | ||
99 | @@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
100 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
101 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
102 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
103 | + | ||
104 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
105 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
106 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
107 | + | ||
108 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
109 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
110 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
111 | + | ||
112 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
113 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
114 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
115 | + | ||
116 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
117 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
118 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
119 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/target/arm/mve_helper.c | ||
122 | +++ b/target/arm/mve_helper.c | ||
123 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
124 | DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
125 | DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
126 | DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
127 | +#define DO_2SHIFT_S(OP, FN) \ | ||
128 | + DO_2SHIFT(OP##b, 1, int8_t, FN) \ | ||
129 | + DO_2SHIFT(OP##h, 2, int16_t, FN) \ | ||
130 | + DO_2SHIFT(OP##w, 4, int32_t, FN) | ||
131 | |||
132 | #define DO_2SHIFT_SAT_U(OP, FN) \ | ||
133 | DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
134 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
135 | DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
136 | |||
137 | DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
138 | +DO_2SHIFT_S(vshli_s, DO_VSHLS) | ||
139 | DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
140 | DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
141 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
142 | +DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
143 | +DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
144 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
145 | index XXXXXXX..XXXXXXX 100644 | ||
146 | --- a/target/arm/translate-mve.c | ||
147 | +++ b/target/arm/translate-mve.c | ||
148 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false) | ||
149 | DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
150 | DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
151 | DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
152 | +/* These right shifts use a left-shift helper with negated shift count */ | ||
153 | +DO_2SHIFT(VSHRI_S, vshli_s, true) | ||
154 | +DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
155 | +DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
156 | +DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
157 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
158 | index XXXXXXX..XXXXXXX 100644 | ||
159 | --- a/target/arm/translate-neon.c | ||
160 | +++ b/target/arm/translate-neon.c | ||
161 | @@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x) | ||
162 | return x + 1; | ||
53 | } | 163 | } |
54 | 164 | ||
55 | -/* Return true if this address translation regime is secure */ | 165 | -static inline int rsub_64(DisasContext *s, int x) |
56 | -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
57 | -{ | 166 | -{ |
58 | - switch (mmu_idx) { | 167 | - return 64 - x; |
59 | - case ARMMMUIdx_S12NSE0: | ||
60 | - case ARMMMUIdx_S12NSE1: | ||
61 | - case ARMMMUIdx_S1NSE0: | ||
62 | - case ARMMMUIdx_S1NSE1: | ||
63 | - case ARMMMUIdx_S1E2: | ||
64 | - case ARMMMUIdx_S2NS: | ||
65 | - case ARMMMUIdx_MPriv: | ||
66 | - case ARMMMUIdx_MNegPri: | ||
67 | - case ARMMMUIdx_MUser: | ||
68 | - return false; | ||
69 | - case ARMMMUIdx_S1E3: | ||
70 | - case ARMMMUIdx_S1SE0: | ||
71 | - case ARMMMUIdx_S1SE1: | ||
72 | - case ARMMMUIdx_MSPriv: | ||
73 | - case ARMMMUIdx_MSNegPri: | ||
74 | - case ARMMMUIdx_MSUser: | ||
75 | - return true; | ||
76 | - default: | ||
77 | - g_assert_not_reached(); | ||
78 | - } | ||
79 | -} | 168 | -} |
80 | - | 169 | - |
81 | /* Return the SCTLR value which controls this address translation regime */ | 170 | -static inline int rsub_32(DisasContext *s, int x) |
82 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | 171 | -{ |
172 | - return 32 - x; | ||
173 | -} | ||
174 | -static inline int rsub_16(DisasContext *s, int x) | ||
175 | -{ | ||
176 | - return 16 - x; | ||
177 | -} | ||
178 | -static inline int rsub_8(DisasContext *s, int x) | ||
179 | -{ | ||
180 | - return 8 - x; | ||
181 | -} | ||
182 | - | ||
183 | static inline int neon_3same_fp_size(DisasContext *s, int x) | ||
83 | { | 184 | { |
185 | /* Convert 0==fp32, 1==fp16 into a MO_* value */ | ||
84 | -- | 186 | -- |
85 | 2.7.4 | 187 | 2.20.1 |
86 | 188 | ||
87 | 189 | diff view generated by jsdifflib |
1 | Make the FAULTMASK register banked if v8M security extensions are enabled. | 1 | Implement the MVE VHLL (vector shift left long) insn. This has two |
---|---|---|---|
2 | 2 | encodings: the T1 encoding is the usual shift-by-immediate format, | |
3 | Note that we do not yet implement the functionality of the new | 3 | and the T2 encoding is a special case where the shift count is always |
4 | AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to | 4 | equal to the element size. |
5 | be restricted). | ||
6 | |||
7 | This patch includes the code to determine for v8M which copy | ||
8 | of FAULTMASK should be updated on exception exit; further | ||
9 | changes will be required to the exception exit code in general | ||
10 | to support v8M, so this is just a small piece of that. | ||
11 | |||
12 | The v8M ARM ARM introduces a notation where individual paragraphs | ||
13 | are labelled with R (for rule) or I (for information) followed | ||
14 | by a random group of subscript letters. In comments where we want | ||
15 | to refer to a particular part of the manual we use this convention, | ||
16 | which should be more stable across document revisions than using | ||
17 | section or page numbers. | ||
18 | 5 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
21 | Message-id: 1503414539-28762-9-git-send-email-peter.maydell@linaro.org | 8 | Message-id: 20210628135835.6690-10-peter.maydell@linaro.org |
22 | --- | 9 | --- |
23 | target/arm/cpu.h | 14 ++++++++++++-- | 10 | target/arm/helper-mve.h | 9 +++++++ |
24 | hw/intc/armv7m_nvic.c | 9 ++++++++- | 11 | target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++--- |
25 | target/arm/helper.c | 20 ++++++++++++++++---- | 12 | target/arm/mve_helper.c | 32 +++++++++++++++++++++++ |
26 | target/arm/machine.c | 5 +++-- | 13 | target/arm/translate-mve.c | 15 +++++++++++ |
27 | 4 files changed, 39 insertions(+), 9 deletions(-) | 14 | 4 files changed, 105 insertions(+), 4 deletions(-) |
28 | 15 | ||
29 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
30 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/target/arm/cpu.h | 18 | --- a/target/arm/helper-mve.h |
32 | +++ b/target/arm/cpu.h | 19 | +++ b/target/arm/helper-mve.h |
33 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | unsigned mpu_ctrl; /* MPU_CTRL */ | 21 | DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
35 | int exception; | 22 | DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
36 | uint32_t primask[2]; | 23 | DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
37 | - uint32_t faultmask; | 24 | + |
38 | + uint32_t faultmask[2]; | 25 | +DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
39 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | 26 | +DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
40 | } v7m; | 27 | +DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
41 | 28 | +DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
42 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | 29 | +DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
43 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | 30 | +DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
44 | */ | 31 | +DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
45 | int armv7m_nvic_complete_irq(void *opaque, int irq); | 32 | +DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
46 | +/** | 33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
47 | + * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
48 | + * @opaque: the NVIC | ||
49 | + * | ||
50 | + * Returns: the raw execution priority as defined by the v8M architecture. | ||
51 | + * This is the execution priority minus the effects of AIRCR.PRIS, | ||
52 | + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
53 | + * (v8M ARM ARM I_PKLD.) | ||
54 | + */ | ||
55 | +int armv7m_nvic_raw_execution_priority(void *opaque); | ||
56 | |||
57 | /* Interface for defining coprocessor registers. | ||
58 | * Registers are defined in tables of arm_cp_reginfo structs | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) | ||
60 | * we're in a HardFault or NMI handler. | ||
61 | */ | ||
62 | if ((env->v7m.exception > 0 && env->v7m.exception <= 3) | ||
63 | - || env->v7m.faultmask) { | ||
64 | + || env->v7m.faultmask[env->v7m.secure]) { | ||
65 | mmu_idx = ARMMMUIdx_MNegPri; | ||
66 | } | ||
67 | |||
68 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
70 | --- a/hw/intc/armv7m_nvic.c | 35 | --- a/target/arm/mve.decode |
71 | +++ b/hw/intc/armv7m_nvic.c | 36 | +++ b/target/arm/mve.decode |
72 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | 37 | @@ -XXX,XX +XXX,XX @@ |
73 | CPUARMState *env = &s->cpu->env; | 38 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
74 | int running; | 39 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 |
75 | 40 | ||
76 | - if (env->v7m.faultmask) { | 41 | +@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 |
77 | + if (env->v7m.faultmask[env->v7m.secure]) { | 42 | +@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
78 | running = -1; | 43 | +# VSHLL encoding T2 where shift == esize |
79 | } else if (env->v7m.primask[env->v7m.secure]) { | 44 | +@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \ |
80 | running = 0; | 45 | + qd=%qd qm=%qm size=0 shift=8 |
81 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_can_take_pending_exception(void *opaque) | 46 | +@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \ |
82 | return nvic_exec_prio(s) > nvic_pending_prio(s); | 47 | + qd=%qd qm=%qm size=1 shift=16 |
83 | } | 48 | + |
84 | 49 | # Right shifts are encoded as N - shift, where N is the element size in bits. | |
85 | +int armv7m_nvic_raw_execution_priority(void *opaque) | 50 | %rshift_i5 16:5 !function=rsub_32 |
51 | %rshift_i4 16:4 !function=rsub_16 | ||
52 | @@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
53 | VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
54 | VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op | ||
55 | |||
56 | -VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
57 | -VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
58 | +# The VSHLL T2 encoding is not a @2op pattern, but is here because it | ||
59 | +# overlaps what would be size=0b11 VMULH/VRMULH | ||
86 | +{ | 60 | +{ |
87 | + NVICState *s = opaque; | 61 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b |
88 | + | 62 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h |
89 | + return s->exception_prio; | 63 | |
64 | -VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
65 | -VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
66 | + VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
90 | +} | 67 | +} |
91 | + | 68 | + |
92 | /* caller must call nvic_irq_update() after this */ | 69 | +{ |
93 | static void set_prio(NVICState *s, unsigned irq, uint8_t prio) | 70 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b |
94 | { | 71 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h |
95 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 72 | + |
73 | + VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
74 | +} | ||
75 | + | ||
76 | +{ | ||
77 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
78 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
79 | + | ||
80 | + VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
81 | +} | ||
82 | + | ||
83 | +{ | ||
84 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
85 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
86 | + | ||
87 | + VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
88 | +} | ||
89 | |||
90 | VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
91 | VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
92 | @@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
93 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
94 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
95 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
96 | + | ||
97 | +# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file | ||
98 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b | ||
99 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h | ||
100 | + | ||
101 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b | ||
102 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h | ||
103 | + | ||
104 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | ||
105 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
106 | + | ||
107 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | ||
108 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
109 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | 110 | index XXXXXXX..XXXXXXX 100644 |
97 | --- a/target/arm/helper.c | 111 | --- a/target/arm/mve_helper.c |
98 | +++ b/target/arm/helper.c | 112 | +++ b/target/arm/mve_helper.c |
99 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 113 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) |
100 | } | 114 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) |
101 | 115 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | |
102 | if (env->v7m.exception != ARMV7M_EXCP_NMI) { | 116 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) |
103 | - /* Auto-clear FAULTMASK on return from other than NMI */ | 117 | + |
104 | - env->v7m.faultmask = 0; | 118 | +/* |
105 | + /* Auto-clear FAULTMASK on return from other than NMI. | 119 | + * Long shifts taking half-sized inputs from top or bottom of the input |
106 | + * If the security extension is implemented then this only | 120 | + * vector and producing a double-width result. ESIZE, TYPE are for |
107 | + * happens if the raw execution priority is >= 0; the | 121 | + * the input, and LESIZE, LTYPE for the output. |
108 | + * value of the ES bit in the exception return value indicates | 122 | + * Unlike the normal shift helpers, we do not handle negative shift counts, |
109 | + * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) | 123 | + * because the long shift is strictly left-only. |
110 | + */ | 124 | + */ |
111 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 125 | +#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ |
112 | + int es = type & 1; | 126 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
113 | + if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { | 127 | + void *vm, uint32_t shift) \ |
114 | + env->v7m.faultmask[es] = 0; | 128 | + { \ |
115 | + } | 129 | + LTYPE *d = vd; \ |
116 | + } else { | 130 | + TYPE *m = vm; \ |
117 | + env->v7m.faultmask[M_REG_NS] = 0; | 131 | + uint16_t mask = mve_element_mask(env); \ |
118 | + } | 132 | + unsigned le; \ |
119 | } | 133 | + assert(shift <= 16); \ |
120 | 134 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | |
121 | switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { | 135 | + LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ |
122 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 136 | + mergemask(&d[H##LESIZE(le)], r, mask); \ |
123 | case 18: /* BASEPRI_MAX */ | 137 | + } \ |
124 | return env->v7m.basepri[env->v7m.secure]; | 138 | + mve_advance_vpt(env); \ |
125 | case 19: /* FAULTMASK */ | 139 | + } |
126 | - return env->v7m.faultmask; | 140 | + |
127 | + return env->v7m.faultmask[env->v7m.secure]; | 141 | +#define DO_VSHLL_ALL(OP, TOP) \ |
128 | default: | 142 | + DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ |
129 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" | 143 | + DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ |
130 | " register %d\n", reg); | 144 | + DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ |
131 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | 145 | + DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ |
132 | } | 146 | + |
133 | break; | 147 | +DO_VSHLL_ALL(vshllb, false) |
134 | case 19: /* FAULTMASK */ | 148 | +DO_VSHLL_ALL(vshllt, true) |
135 | - env->v7m.faultmask = val & 1; | 149 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
136 | + env->v7m.faultmask[env->v7m.secure] = val & 1; | ||
137 | break; | ||
138 | case 20: /* CONTROL */ | ||
139 | /* Writing to the SPSEL bit only has an effect if we are in | ||
140 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
141 | index XXXXXXX..XXXXXXX 100644 | 150 | index XXXXXXX..XXXXXXX 100644 |
142 | --- a/target/arm/machine.c | 151 | --- a/target/arm/translate-mve.c |
143 | +++ b/target/arm/machine.c | 152 | +++ b/target/arm/translate-mve.c |
144 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = { | 153 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true) |
145 | .version_id = 1, | 154 | DO_2SHIFT(VSHRI_U, vshli_u, true) |
146 | .minimum_version_id = 1, | 155 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) |
147 | .fields = (VMStateField[]) { | 156 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) |
148 | - VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), | 157 | + |
149 | + VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), | 158 | +#define DO_VSHLL(INSN, FN) \ |
150 | VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), | 159 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
151 | VMSTATE_END_OF_LIST() | 160 | + { \ |
152 | } | 161 | + static MVEGenTwoOpShiftFn * const fns[] = { \ |
153 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 162 | + gen_helper_mve_##FN##b, \ |
154 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), | 163 | + gen_helper_mve_##FN##h, \ |
155 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | 164 | + }; \ |
156 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | 165 | + return do_2shift(s, a, fns[a->size], false); \ |
157 | + VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | 166 | + } |
158 | VMSTATE_END_OF_LIST() | 167 | + |
159 | } | 168 | +DO_VSHLL(VSHLL_BS, vshllbs) |
160 | }; | 169 | +DO_VSHLL(VSHLL_BU, vshllbu) |
161 | @@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | 170 | +DO_VSHLL(VSHLL_TS, vshllts) |
162 | * transferred using the vmstate_m_faultmask_primask subsection. | 171 | +DO_VSHLL(VSHLL_TU, vshlltu) |
163 | */ | ||
164 | if (val & CPSR_F) { | ||
165 | - env->v7m.faultmask = 1; | ||
166 | + env->v7m.faultmask[M_REG_NS] = 1; | ||
167 | } | ||
168 | if (val & CPSR_I) { | ||
169 | env->v7m.primask[M_REG_NS] = 1; | ||
170 | -- | 172 | -- |
171 | 2.7.4 | 173 | 2.20.1 |
172 | 174 | ||
173 | 175 | diff view generated by jsdifflib |
1 | Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security | 1 | Implement the MVE VSRI and VSLI insns, which perform a |
---|---|---|---|
2 | extensions are enabled. | 2 | shift-and-insert operation. |
3 | |||
4 | We can freely add more items to vmstate_m_security without | ||
5 | breaking migration compatibility, because no CPU currently | ||
6 | has the ARM_FEATURE_M_SECURITY bit enabled and so this | ||
7 | subsection is not yet used by anything. | ||
8 | 3 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org | 6 | Message-id: 20210628135835.6690-11-peter.maydell@linaro.org |
12 | --- | 7 | --- |
13 | target/arm/cpu.h | 4 ++-- | 8 | target/arm/helper-mve.h | 8 ++++++++ |
14 | hw/intc/armv7m_nvic.c | 8 ++++---- | 9 | target/arm/mve.decode | 9 ++++++++ |
15 | target/arm/cpu.c | 26 ++++++++++++++++++++------ | 10 | target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++ |
16 | target/arm/helper.c | 11 ++++++----- | 11 | target/arm/translate-mve.c | 3 +++ |
17 | target/arm/machine.c | 12 ++++++++---- | 12 | 4 files changed, 62 insertions(+) |
18 | 5 files changed, 40 insertions(+), 21 deletions(-) | ||
19 | 13 | ||
20 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
21 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/cpu.h | 16 | --- a/target/arm/helper-mve.h |
23 | +++ b/target/arm/cpu.h | 17 | +++ b/target/arm/helper-mve.h |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | * pmsav7.rnr (region number register) | 19 | DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | * pmsav7_dregion (number of configured regions) | 20 | DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | */ | 21 | DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | - uint32_t *rbar; | 22 | + |
29 | - uint32_t *rlar; | 23 | +DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | + uint32_t *rbar[2]; | 24 | +DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | + uint32_t *rlar[2]; | 25 | +DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | uint32_t mair0[2]; | 26 | + |
33 | uint32_t mair1[2]; | 27 | +DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | } pmsav8; | 28 | +DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
35 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 29 | +DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
36 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/hw/intc/armv7m_nvic.c | 32 | --- a/target/arm/mve.decode |
38 | +++ b/hw/intc/armv7m_nvic.c | 33 | +++ b/target/arm/mve.decode |
39 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 34 | @@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h |
40 | if (region >= cpu->pmsav7_dregion) { | 35 | |
41 | return 0; | 36 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b |
42 | } | 37 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h |
43 | - return cpu->env.pmsav8.rbar[region]; | 38 | + |
44 | + return cpu->env.pmsav8.rbar[attrs.secure][region]; | 39 | +# Shift-and-insert |
45 | } | 40 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b |
46 | 41 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h | |
47 | if (region >= cpu->pmsav7_dregion) { | 42 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w |
48 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 43 | + |
49 | if (region >= cpu->pmsav7_dregion) { | 44 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b |
50 | return 0; | 45 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h |
51 | } | 46 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w |
52 | - return cpu->env.pmsav8.rlar[region]; | 47 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
53 | + return cpu->env.pmsav8.rlar[attrs.secure][region]; | ||
54 | } | ||
55 | |||
56 | if (region >= cpu->pmsav7_dregion) { | ||
57 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
58 | if (region >= cpu->pmsav7_dregion) { | ||
59 | return; | ||
60 | } | ||
61 | - cpu->env.pmsav8.rbar[region] = value; | ||
62 | + cpu->env.pmsav8.rbar[attrs.secure][region] = value; | ||
63 | tlb_flush(CPU(cpu)); | ||
64 | return; | ||
65 | } | ||
66 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
67 | if (region >= cpu->pmsav7_dregion) { | ||
68 | return; | ||
69 | } | ||
70 | - cpu->env.pmsav8.rlar[region] = value; | ||
71 | + cpu->env.pmsav8.rlar[attrs.secure][region] = value; | ||
72 | tlb_flush(CPU(cpu)); | ||
73 | return; | ||
74 | } | ||
75 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
77 | --- a/target/arm/cpu.c | 49 | --- a/target/arm/mve_helper.c |
78 | +++ b/target/arm/cpu.c | 50 | +++ b/target/arm/mve_helper.c |
79 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 51 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) |
80 | if (arm_feature(env, ARM_FEATURE_PMSA)) { | 52 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) |
81 | if (cpu->pmsav7_dregion > 0) { | 53 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) |
82 | if (arm_feature(env, ARM_FEATURE_V8)) { | 54 | |
83 | - memset(env->pmsav8.rbar, 0, | 55 | +/* Shift-and-insert; we always work with 64 bits at a time */ |
84 | - sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); | 56 | +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ |
85 | - memset(env->pmsav8.rlar, 0, | 57 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
86 | - sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); | 58 | + void *vm, uint32_t shift) \ |
87 | + memset(env->pmsav8.rbar[M_REG_NS], 0, | 59 | + { \ |
88 | + sizeof(*env->pmsav8.rbar[M_REG_NS]) | 60 | + uint64_t *d = vd, *m = vm; \ |
89 | + * cpu->pmsav7_dregion); | 61 | + uint16_t mask; \ |
90 | + memset(env->pmsav8.rlar[M_REG_NS], 0, | 62 | + uint64_t shiftmask; \ |
91 | + sizeof(*env->pmsav8.rlar[M_REG_NS]) | 63 | + unsigned e; \ |
92 | + * cpu->pmsav7_dregion); | 64 | + if (shift == 0 || shift == ESIZE * 8) { \ |
93 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 65 | + /* \ |
94 | + memset(env->pmsav8.rbar[M_REG_S], 0, | 66 | + * Only VSLI can shift by 0; only VSRI can shift by <dt>. \ |
95 | + sizeof(*env->pmsav8.rbar[M_REG_S]) | 67 | + * The generic logic would give the right answer for 0 but \ |
96 | + * cpu->pmsav7_dregion); | 68 | + * fails for <dt>. \ |
97 | + memset(env->pmsav8.rlar[M_REG_S], 0, | 69 | + */ \ |
98 | + sizeof(*env->pmsav8.rlar[M_REG_S]) | 70 | + goto done; \ |
99 | + * cpu->pmsav7_dregion); | 71 | + } \ |
100 | + } | 72 | + assert(shift < ESIZE * 8); \ |
101 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | 73 | + mask = mve_element_mask(env); \ |
102 | memset(env->pmsav7.drbar, 0, | 74 | + /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ |
103 | sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | 75 | + shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ |
104 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 76 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ |
105 | if (nr) { | 77 | + uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ |
106 | if (arm_feature(env, ARM_FEATURE_V8)) { | 78 | + (d[H8(e)] & ~shiftmask); \ |
107 | /* PMSAv8 */ | 79 | + mergemask(&d[H8(e)], r, mask); \ |
108 | - env->pmsav8.rbar = g_new0(uint32_t, nr); | 80 | + } \ |
109 | - env->pmsav8.rlar = g_new0(uint32_t, nr); | 81 | +done: \ |
110 | + env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); | 82 | + mve_advance_vpt(env); \ |
111 | + env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); | 83 | + } |
112 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 84 | + |
113 | + env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); | 85 | +#define DO_SHL(N, SHIFT) ((N) << (SHIFT)) |
114 | + env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); | 86 | +#define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) |
115 | + } | 87 | +#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) |
116 | } else { | 88 | +#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) |
117 | env->pmsav7.drbar = g_new0(uint32_t, nr); | 89 | + |
118 | env->pmsav7.drsr = g_new0(uint32_t, nr); | 90 | +DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) |
119 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 91 | +DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) |
92 | +DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) | ||
93 | +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) | ||
94 | +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) | ||
95 | +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | ||
96 | + | ||
97 | /* | ||
98 | * Long shifts taking half-sized inputs from top or bottom of the input | ||
99 | * vector and producing a double-width result. ESIZE, TYPE are for | ||
100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
120 | index XXXXXXX..XXXXXXX 100644 | 101 | index XXXXXXX..XXXXXXX 100644 |
121 | --- a/target/arm/helper.c | 102 | --- a/target/arm/translate-mve.c |
122 | +++ b/target/arm/helper.c | 103 | +++ b/target/arm/translate-mve.c |
123 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | 104 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true) |
124 | { | 105 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) |
125 | ARMCPU *cpu = arm_env_get_cpu(env); | 106 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) |
126 | bool is_user = regime_is_user(env, mmu_idx); | 107 | |
127 | + uint32_t secure = regime_is_secure(env, mmu_idx); | 108 | +DO_2SHIFT(VSRI, vsri, false) |
128 | int n; | 109 | +DO_2SHIFT(VSLI, vsli, false) |
129 | int matchregion = -1; | 110 | + |
130 | bool hit = false; | 111 | #define DO_VSHLL(INSN, FN) \ |
131 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | 112 | static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ |
132 | * with bits [4:0] all zeroes, but the limit address is bits | 113 | { \ |
133 | * [31:5] from the register with bits [4:0] all ones. | ||
134 | */ | ||
135 | - uint32_t base = env->pmsav8.rbar[n] & ~0x1f; | ||
136 | - uint32_t limit = env->pmsav8.rlar[n] | 0x1f; | ||
137 | + uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; | ||
138 | + uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | ||
139 | |||
140 | - if (!(env->pmsav8.rlar[n] & 0x1)) { | ||
141 | + if (!(env->pmsav8.rlar[secure][n] & 0x1)) { | ||
142 | /* Region disabled */ | ||
143 | continue; | ||
144 | } | ||
145 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | ||
146 | /* hit using the background region */ | ||
147 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | ||
148 | } else { | ||
149 | - uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2); | ||
150 | - uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1); | ||
151 | + uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); | ||
152 | + uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | ||
153 | |||
154 | if (m_is_system_region(env, address)) { | ||
155 | /* System space is always execute never */ | ||
156 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
157 | index XXXXXXX..XXXXXXX 100644 | ||
158 | --- a/target/arm/machine.c | ||
159 | +++ b/target/arm/machine.c | ||
160 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = { | ||
161 | .minimum_version_id = 1, | ||
162 | .needed = pmsav8_needed, | ||
163 | .fields = (VMStateField[]) { | ||
164 | - VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, | ||
165 | - vmstate_info_uint32, uint32_t), | ||
166 | - VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, | ||
167 | - vmstate_info_uint32, uint32_t), | ||
168 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, | ||
169 | + 0, vmstate_info_uint32, uint32_t), | ||
170 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, | ||
171 | + 0, vmstate_info_uint32, uint32_t), | ||
172 | VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), | ||
173 | VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), | ||
174 | VMSTATE_END_OF_LIST() | ||
175 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
176 | VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), | ||
177 | VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), | ||
178 | VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), | ||
179 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, | ||
180 | + 0, vmstate_info_uint32, uint32_t), | ||
181 | + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, | ||
182 | + 0, vmstate_info_uint32, uint32_t), | ||
183 | VMSTATE_END_OF_LIST() | ||
184 | } | ||
185 | }; | ||
186 | -- | 114 | -- |
187 | 2.7.4 | 115 | 2.20.1 |
188 | 116 | ||
189 | 117 | diff view generated by jsdifflib |
1 | Implement the new do_transaction_failed hook for ARM, which should | 1 | Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN. |
---|---|---|---|
2 | cause the CPU to take a prefetch abort or data abort. | 2 | |
3 | do_urshr() is borrowed from sve_helper.c. | ||
3 | 4 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 7 | Message-id: 20210628135835.6690-12-peter.maydell@linaro.org |
7 | Message-id: 1504626814-23124-4-git-send-email-peter.maydell@linaro.org | ||
8 | --- | 8 | --- |
9 | target/arm/internals.h | 10 ++++++++++ | 9 | target/arm/helper-mve.h | 10 ++++++++++ |
10 | target/arm/cpu.c | 1 + | 10 | target/arm/mve.decode | 11 +++++++++++ |
11 | target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ | 11 | target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++ |
12 | 3 files changed, 54 insertions(+) | 12 | target/arm/translate-mve.c | 15 ++++++++++++++ |
13 | 4 files changed, 76 insertions(+) | ||
13 | 14 | ||
14 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/internals.h | 17 | --- a/target/arm/helper-mve.h |
17 | +++ b/target/arm/internals.h | 18 | +++ b/target/arm/helper-mve.h |
18 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
19 | MMUAccessType access_type, | 20 | DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
20 | int mmu_idx, uintptr_t retaddr); | 21 | DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
21 | 22 | DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
22 | +/* arm_cpu_do_transaction_failed: handle a memory system error response | 23 | + |
23 | + * (eg "no device/memory present at address") by raising an external abort | 24 | +DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | + * exception | 25 | +DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | +DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | + | ||
29 | +DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
30 | +DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/mve.decode | ||
36 | +++ b/target/arm/mve.decode | ||
37 | @@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | ||
38 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
39 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
40 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
41 | + | ||
42 | +# Narrowing shifts (which only support b and h sizes) | ||
43 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
44 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
45 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
46 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
47 | + | ||
48 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
49 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
50 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
51 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/mve_helper.c | ||
55 | +++ b/target/arm/mve_helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | ||
57 | |||
58 | DO_VSHLL_ALL(vshllb, false) | ||
59 | DO_VSHLL_ALL(vshllt, true) | ||
60 | + | ||
61 | +/* | ||
62 | + * Narrowing right shifts, taking a double sized input, shifting it | ||
63 | + * and putting the result in either the top or bottom half of the output. | ||
64 | + * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. | ||
25 | + */ | 65 | + */ |
26 | +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | 66 | +#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ |
27 | + vaddr addr, unsigned size, | 67 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
28 | + MMUAccessType access_type, | 68 | + void *vm, uint32_t shift) \ |
29 | + int mmu_idx, MemTxAttrs attrs, | 69 | + { \ |
30 | + MemTxResult response, uintptr_t retaddr); | 70 | + LTYPE *m = vm; \ |
31 | + | 71 | + TYPE *d = vd; \ |
32 | /* Call the EL change hook if one has been registered */ | 72 | + uint16_t mask = mve_element_mask(env); \ |
33 | static inline void arm_call_el_change_hook(ARMCPU *cpu) | 73 | + unsigned le; \ |
34 | { | 74 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ |
35 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 75 | + TYPE r = FN(m[H##LESIZE(le)], shift); \ |
36 | index XXXXXXX..XXXXXXX 100644 | 76 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ |
37 | --- a/target/arm/cpu.c | 77 | + } \ |
38 | +++ b/target/arm/cpu.c | 78 | + mve_advance_vpt(env); \ |
39 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) | ||
40 | #else | ||
41 | cc->do_interrupt = arm_cpu_do_interrupt; | ||
42 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; | ||
43 | + cc->do_transaction_failed = arm_cpu_do_transaction_failed; | ||
44 | cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; | ||
45 | cc->asidx_from_attrs = arm_asidx_from_attrs; | ||
46 | cc->vmsd = &vmstate_arm_cpu; | ||
47 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/op_helper.c | ||
50 | +++ b/target/arm/op_helper.c | ||
51 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | ||
52 | deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); | ||
53 | } | ||
54 | |||
55 | +/* arm_cpu_do_transaction_failed: handle a memory system error response | ||
56 | + * (eg "no device/memory present at address") by raising an external abort | ||
57 | + * exception | ||
58 | + */ | ||
59 | +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | ||
60 | + vaddr addr, unsigned size, | ||
61 | + MMUAccessType access_type, | ||
62 | + int mmu_idx, MemTxAttrs attrs, | ||
63 | + MemTxResult response, uintptr_t retaddr) | ||
64 | +{ | ||
65 | + ARMCPU *cpu = ARM_CPU(cs); | ||
66 | + CPUARMState *env = &cpu->env; | ||
67 | + uint32_t fsr, fsc; | ||
68 | + ARMMMUFaultInfo fi = {}; | ||
69 | + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); | ||
70 | + | ||
71 | + if (retaddr) { | ||
72 | + /* now we have a real cpu fault */ | ||
73 | + cpu_restore_state(cs, retaddr); | ||
74 | + } | 79 | + } |
75 | + | 80 | + |
76 | + /* The EA bit in syndromes and fault status registers is an | 81 | +#define DO_VSHRN_ALL(OP, FN) \ |
77 | + * IMPDEF classification of external aborts. ARM implementations | 82 | + DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ |
78 | + * usually use this to indicate AXI bus Decode error (0) or | 83 | + DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ |
79 | + * Slave error (1); in QEMU we follow that. | 84 | + DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ |
80 | + */ | 85 | + DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) |
81 | + fi.ea = (response != MEMTX_DECODE_ERROR); | ||
82 | + | 86 | + |
83 | + /* The fault status register format depends on whether we're using | 87 | +static inline uint64_t do_urshr(uint64_t x, unsigned sh) |
84 | + * the LPAE long descriptor format, or the short descriptor format. | 88 | +{ |
85 | + */ | 89 | + if (likely(sh < 64)) { |
86 | + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { | 90 | + return (x >> sh) + ((x >> (sh - 1)) & 1); |
87 | + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ | 91 | + } else if (sh == 64) { |
88 | + fsr = (fi.ea << 12) | (1 << 9) | 0x10; | 92 | + return x >> 63; |
89 | + } else { | 93 | + } else { |
90 | + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ | 94 | + return 0; |
91 | + fsr = (fi.ea << 12) | 0x8; | ||
92 | + } | 95 | + } |
93 | + fsc = 0x10; | ||
94 | + | ||
95 | + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); | ||
96 | +} | 96 | +} |
97 | + | 97 | + |
98 | #endif /* !defined(CONFIG_USER_ONLY) */ | 98 | +DO_VSHRN_ALL(vshrn, DO_SHR) |
99 | 99 | +DO_VSHRN_ALL(vrshrn, do_urshr) | |
100 | uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) | 100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/target/arm/translate-mve.c | ||
103 | +++ b/target/arm/translate-mve.c | ||
104 | @@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs) | ||
105 | DO_VSHLL(VSHLL_BU, vshllbu) | ||
106 | DO_VSHLL(VSHLL_TS, vshllts) | ||
107 | DO_VSHLL(VSHLL_TU, vshlltu) | ||
108 | + | ||
109 | +#define DO_2SHIFT_N(INSN, FN) \ | ||
110 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
111 | + { \ | ||
112 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
113 | + gen_helper_mve_##FN##b, \ | ||
114 | + gen_helper_mve_##FN##h, \ | ||
115 | + }; \ | ||
116 | + return do_2shift(s, a, fns[a->size], false); \ | ||
117 | + } | ||
118 | + | ||
119 | +DO_2SHIFT_N(VSHRNB, vshrnb) | ||
120 | +DO_2SHIFT_N(VSHRNT, vshrnt) | ||
121 | +DO_2SHIFT_N(VRSHRNB, vrshrnb) | ||
122 | +DO_2SHIFT_N(VRSHRNT, vrshrnt) | ||
101 | -- | 123 | -- |
102 | 2.7.4 | 124 | 2.20.1 |
103 | 125 | ||
104 | 126 | diff view generated by jsdifflib |
1 | For v8M the range 0xe002e000..0xe002efff is an alias region which | 1 | Implement the MVE saturating shift-right-and-narrow insns |
---|---|---|---|
2 | for secure accesses behaves like a NonSecure access to the main | 2 | VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN. |
3 | SCS region. (For nonsecure accesses including when the security | 3 | |
4 | extension is not implemented, it is RAZ/WI.) | 4 | do_srshr() is borrowed from sve_helper.c. |
5 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 1503414539-28762-11-git-send-email-peter.maydell@linaro.org | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20210628135835.6690-13-peter.maydell@linaro.org | ||
8 | --- | 9 | --- |
9 | include/hw/intc/armv7m_nvic.h | 1 + | 10 | target/arm/helper-mve.h | 30 +++++++++++ |
10 | hw/intc/armv7m_nvic.c | 66 ++++++++++++++++++++++++++++++++++++++++++- | 11 | target/arm/mve.decode | 28 ++++++++++ |
11 | 2 files changed, 66 insertions(+), 1 deletion(-) | 12 | target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++ |
12 | 13 | target/arm/translate-mve.c | 12 +++++ | |
13 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | 14 | 4 files changed, 174 insertions(+) |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | |
15 | --- a/include/hw/intc/armv7m_nvic.h | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
16 | +++ b/include/hw/intc/armv7m_nvic.h | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | @@ -XXX,XX +XXX,XX @@ typedef struct NVICState { | 18 | --- a/target/arm/helper-mve.h |
18 | int exception_prio; /* group prio of the highest prio active exception */ | 19 | +++ b/target/arm/helper-mve.h |
19 | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
20 | MemoryRegion sysregmem; | 21 | DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
21 | + MemoryRegion sysreg_ns_mem; | 22 | DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | MemoryRegion container; | 23 | DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | 24 | + | |
24 | uint32_t num_irq; | 25 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 26 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | index XXXXXXX..XXXXXXX 100644 | 27 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | --- a/hw/intc/armv7m_nvic.c | 28 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | +++ b/hw/intc/armv7m_nvic.c | 29 | + |
29 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_sysreg_ops = { | 30 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | .endianness = DEVICE_NATIVE_ENDIAN, | 31 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | }; | 32 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | 33 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
33 | +static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, | 34 | + |
34 | + uint64_t value, unsigned size, | 35 | +DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
35 | + MemTxAttrs attrs) | 36 | +DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
37 | +DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
38 | +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | + | ||
40 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
42 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
43 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
44 | + | ||
45 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
46 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
47 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
48 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
49 | + | ||
50 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
51 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
52 | +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
53 | +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
54 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/arm/mve.decode | ||
57 | +++ b/target/arm/mve.decode | ||
58 | @@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
59 | VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
60 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
61 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
62 | + | ||
63 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b | ||
64 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h | ||
65 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b | ||
66 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h | ||
67 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b | ||
68 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h | ||
69 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b | ||
70 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h | ||
71 | + | ||
72 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
73 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
74 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
75 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
76 | + | ||
77 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b | ||
78 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h | ||
79 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b | ||
80 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h | ||
81 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b | ||
82 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h | ||
83 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b | ||
84 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h | ||
85 | + | ||
86 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
87 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
88 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
89 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
90 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/target/arm/mve_helper.c | ||
93 | +++ b/target/arm/mve_helper.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh) | ||
95 | } | ||
96 | } | ||
97 | |||
98 | +static inline int64_t do_srshr(int64_t x, unsigned sh) | ||
36 | +{ | 99 | +{ |
37 | + if (attrs.secure) { | 100 | + if (likely(sh < 64)) { |
38 | + /* S accesses to the alias act like NS accesses to the real region */ | 101 | + return (x >> sh) + ((x >> (sh - 1)) & 1); |
39 | + attrs.secure = 0; | ||
40 | + return nvic_sysreg_write(opaque, addr, value, size, attrs); | ||
41 | + } else { | 102 | + } else { |
42 | + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ | 103 | + /* Rounding the sign bit always produces 0. */ |
43 | + if (attrs.user) { | 104 | + return 0; |
44 | + return MEMTX_ERROR; | ||
45 | + } | ||
46 | + return MEMTX_OK; | ||
47 | + } | 105 | + } |
48 | +} | 106 | +} |
49 | + | 107 | + |
50 | +static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, | 108 | DO_VSHRN_ALL(vshrn, DO_SHR) |
51 | + uint64_t *data, unsigned size, | 109 | DO_VSHRN_ALL(vrshrn, do_urshr) |
52 | + MemTxAttrs attrs) | 110 | + |
111 | +static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, | ||
112 | + bool *satp) | ||
53 | +{ | 113 | +{ |
54 | + if (attrs.secure) { | 114 | + if (val > max) { |
55 | + /* S accesses to the alias act like NS accesses to the real region */ | 115 | + *satp = true; |
56 | + attrs.secure = 0; | 116 | + return max; |
57 | + return nvic_sysreg_read(opaque, addr, data, size, attrs); | 117 | + } else if (val < min) { |
118 | + *satp = true; | ||
119 | + return min; | ||
58 | + } else { | 120 | + } else { |
59 | + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ | 121 | + return val; |
60 | + if (attrs.user) { | ||
61 | + return MEMTX_ERROR; | ||
62 | + } | ||
63 | + *data = 0; | ||
64 | + return MEMTX_OK; | ||
65 | + } | 122 | + } |
66 | +} | 123 | +} |
67 | + | 124 | + |
68 | +static const MemoryRegionOps nvic_sysreg_ns_ops = { | 125 | +/* Saturating narrowing right shifts */ |
69 | + .read_with_attrs = nvic_sysreg_ns_read, | 126 | +#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ |
70 | + .write_with_attrs = nvic_sysreg_ns_write, | 127 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
71 | + .endianness = DEVICE_NATIVE_ENDIAN, | 128 | + void *vm, uint32_t shift) \ |
72 | +}; | 129 | + { \ |
73 | + | 130 | + LTYPE *m = vm; \ |
74 | static int nvic_post_load(void *opaque, int version_id) | 131 | + TYPE *d = vd; \ |
75 | { | 132 | + uint16_t mask = mve_element_mask(env); \ |
76 | NVICState *s = opaque; | 133 | + bool qc = false; \ |
77 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | 134 | + unsigned le; \ |
78 | NVICState *s = NVIC(dev); | 135 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ |
79 | SysBusDevice *systick_sbd; | 136 | + bool sat = false; \ |
80 | Error *err = NULL; | 137 | + TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ |
81 | + int regionlen; | 138 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ |
82 | 139 | + qc |= sat && (mask & 1 << (TOP * ESIZE)); \ | |
83 | s->cpu = ARM_CPU(qemu_get_cpu(0)); | 140 | + } \ |
84 | assert(s->cpu); | 141 | + if (qc) { \ |
85 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | 142 | + env->vfp.qc[0] = qc; \ |
86 | * 0xd00..0xd3c - SCS registers | 143 | + } \ |
87 | * 0xd40..0xeff - Reserved or Not implemented | 144 | + mve_advance_vpt(env); \ |
88 | * 0xf00 - STIR | ||
89 | + * | ||
90 | + * Some registers within this space are banked between security states. | ||
91 | + * In v8M there is a second range 0xe002e000..0xe002efff which is the | ||
92 | + * NonSecure alias SCS; secure accesses to this behave like NS accesses | ||
93 | + * to the main SCS range, and non-secure accesses (including when | ||
94 | + * the security extension is not implemented) are RAZ/WI. | ||
95 | + * Note that both the main SCS range and the alias range are defined | ||
96 | + * to be exempt from memory attribution (R_BLJT) and so the memory | ||
97 | + * transaction attribute always matches the current CPU security | ||
98 | + * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops | ||
99 | + * wrappers we change attrs.secure to indicate the NS access; so | ||
100 | + * generally code determining which banked register to use should | ||
101 | + * use attrs.secure; code determining actual behaviour of the system | ||
102 | + * should use env->v7m.secure. | ||
103 | */ | ||
104 | - memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); | ||
105 | + regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; | ||
106 | + memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); | ||
107 | /* The system register region goes at the bottom of the priority | ||
108 | * stack as it covers the whole page. | ||
109 | */ | ||
110 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | ||
111 | sysbus_mmio_get_region(systick_sbd, 0), | ||
112 | 1); | ||
113 | |||
114 | + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { | ||
115 | + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), | ||
116 | + &nvic_sysreg_ns_ops, s, | ||
117 | + "nvic_sysregs_ns", 0x1000); | ||
118 | + memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); | ||
119 | + } | 145 | + } |
120 | + | 146 | + |
121 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); | 147 | +#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ |
122 | } | 148 | + DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ |
123 | 149 | + DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) | |
150 | + | ||
151 | +#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ | ||
152 | + DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ | ||
153 | + DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) | ||
154 | + | ||
155 | +#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ | ||
156 | + DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ | ||
157 | + DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) | ||
158 | + | ||
159 | +#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ | ||
160 | + DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ | ||
161 | + DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) | ||
162 | + | ||
163 | +#define DO_SHRN_SB(N, M, SATP) \ | ||
164 | + do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) | ||
165 | +#define DO_SHRN_UB(N, M, SATP) \ | ||
166 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) | ||
167 | +#define DO_SHRUN_B(N, M, SATP) \ | ||
168 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) | ||
169 | + | ||
170 | +#define DO_SHRN_SH(N, M, SATP) \ | ||
171 | + do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) | ||
172 | +#define DO_SHRN_UH(N, M, SATP) \ | ||
173 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) | ||
174 | +#define DO_SHRUN_H(N, M, SATP) \ | ||
175 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) | ||
176 | + | ||
177 | +#define DO_RSHRN_SB(N, M, SATP) \ | ||
178 | + do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) | ||
179 | +#define DO_RSHRN_UB(N, M, SATP) \ | ||
180 | + do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) | ||
181 | +#define DO_RSHRUN_B(N, M, SATP) \ | ||
182 | + do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) | ||
183 | + | ||
184 | +#define DO_RSHRN_SH(N, M, SATP) \ | ||
185 | + do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) | ||
186 | +#define DO_RSHRN_UH(N, M, SATP) \ | ||
187 | + do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) | ||
188 | +#define DO_RSHRUN_H(N, M, SATP) \ | ||
189 | + do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) | ||
190 | + | ||
191 | +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) | ||
192 | +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) | ||
193 | +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) | ||
194 | +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) | ||
195 | +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) | ||
196 | +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) | ||
197 | + | ||
198 | +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) | ||
199 | +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) | ||
200 | +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) | ||
201 | +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) | ||
202 | +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) | ||
203 | +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) | ||
204 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
205 | index XXXXXXX..XXXXXXX 100644 | ||
206 | --- a/target/arm/translate-mve.c | ||
207 | +++ b/target/arm/translate-mve.c | ||
208 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb) | ||
209 | DO_2SHIFT_N(VSHRNT, vshrnt) | ||
210 | DO_2SHIFT_N(VRSHRNB, vrshrnb) | ||
211 | DO_2SHIFT_N(VRSHRNT, vrshrnt) | ||
212 | +DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) | ||
213 | +DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) | ||
214 | +DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) | ||
215 | +DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) | ||
216 | +DO_2SHIFT_N(VQSHRUNB, vqshrunb) | ||
217 | +DO_2SHIFT_N(VQSHRUNT, vqshrunt) | ||
218 | +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) | ||
219 | +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) | ||
220 | +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) | ||
221 | +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) | ||
222 | +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) | ||
223 | +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | ||
124 | -- | 224 | -- |
125 | 2.7.4 | 225 | 2.20.1 |
126 | 226 | ||
127 | 227 | diff view generated by jsdifflib |
1 | Define a new MachineClass field ignore_memory_transaction_failures. | 1 | Implement the MVE VSHLC insn, which performs a shift left of the |
---|---|---|---|
2 | If this is flag is true then the CPU will ignore memory transaction | 2 | entire vector with carry in bits provided from a general purpose |
3 | failures which should cause the CPU to take an exception due to an | 3 | register and carry out bits written back to that register. |
4 | access to an unassigned physical address; the transaction will | ||
5 | instead return zero (for a read) or be ignored (for a write). This | ||
6 | should be set only by legacy board models which rely on the old | ||
7 | RAZ/WI behaviour for handling devices that QEMU does not yet model. | ||
8 | New board models should instead use "unimplemented-device" for all | ||
9 | memory ranges where the guest will attempt to probe for a device that | ||
10 | QEMU doesn't implement and a stub device is required. | ||
11 | |||
12 | We need this for ARM boards, where we're about to implement support for | ||
13 | generating external aborts on memory transaction failures. Too many | ||
14 | of our legacy board models rely on the RAZ/WI behaviour and we | ||
15 | would break currently working guests when their "probe for device" | ||
16 | code provoked an external abort rather than a RAZ. | ||
17 | 4 | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
20 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 7 | Message-id: 20210628135835.6690-14-peter.maydell@linaro.org |
21 | Message-id: 1504626814-23124-2-git-send-email-peter.maydell@linaro.org | ||
22 | --- | 8 | --- |
23 | include/hw/boards.h | 11 +++++++++++ | 9 | target/arm/helper-mve.h | 2 ++ |
24 | include/qom/cpu.h | 7 ++++++- | 10 | target/arm/mve.decode | 2 ++ |
25 | qom/cpu.c | 16 ++++++++++++++++ | 11 | target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++ |
26 | 3 files changed, 33 insertions(+), 1 deletion(-) | 12 | target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++ |
13 | 4 files changed, 72 insertions(+) | ||
27 | 14 | ||
28 | diff --git a/include/hw/boards.h b/include/hw/boards.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
29 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/include/hw/boards.h | 17 | --- a/target/arm/helper-mve.h |
31 | +++ b/include/hw/boards.h | 18 | +++ b/target/arm/helper-mve.h |
32 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | * size than the target architecture's minimum. (Attempting to create | 20 | DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | * such a CPU will fail.) Note that changing this is a migration | 21 | DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
35 | * compatibility break for the machine. | 22 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
36 | + * @ignore_memory_transaction_failures: | 23 | + |
37 | + * If this is flag is true then the CPU will ignore memory transaction | 24 | +DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) |
38 | + * failures which should cause the CPU to take an exception due to an | 25 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
39 | + * access to an unassigned physical address; the transaction will instead | ||
40 | + * return zero (for a read) or be ignored (for a write). This should be | ||
41 | + * set only by legacy board models which rely on the old RAZ/WI behaviour | ||
42 | + * for handling devices that QEMU does not yet model. New board models | ||
43 | + * should instead use "unimplemented-device" for all memory ranges where | ||
44 | + * the guest will attempt to probe for a device that QEMU doesn't | ||
45 | + * implement and a stub device is required. | ||
46 | */ | ||
47 | struct MachineClass { | ||
48 | /*< private >*/ | ||
49 | @@ -XXX,XX +XXX,XX @@ struct MachineClass { | ||
50 | bool rom_file_has_mr; | ||
51 | int minimum_page_bits; | ||
52 | bool has_hotpluggable_cpus; | ||
53 | + bool ignore_memory_transaction_failures; | ||
54 | int numa_mem_align_shift; | ||
55 | void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes, | ||
56 | int nb_nodes, ram_addr_t size); | ||
57 | diff --git a/include/qom/cpu.h b/include/qom/cpu.h | ||
58 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
59 | --- a/include/qom/cpu.h | 27 | --- a/target/arm/mve.decode |
60 | +++ b/include/qom/cpu.h | 28 | +++ b/target/arm/mve.decode |
61 | @@ -XXX,XX +XXX,XX @@ struct qemu_work_item; | 29 | @@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b |
62 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes | 30 | VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h |
63 | * to @trace_dstate). | 31 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b |
64 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). | 32 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h |
65 | + * @ignore_memory_transaction_failures: Cached copy of the MachineState | ||
66 | + * flag of the same name: allows the board to suppress calling of the | ||
67 | + * CPU do_transaction_failed hook function. | ||
68 | * | ||
69 | * State of one CPU core or thread. | ||
70 | */ | ||
71 | @@ -XXX,XX +XXX,XX @@ struct CPUState { | ||
72 | */ | ||
73 | bool throttle_thread_scheduled; | ||
74 | |||
75 | + bool ignore_memory_transaction_failures; | ||
76 | + | 33 | + |
77 | /* Note that this is accessed at the start of every TB via a negative | 34 | +VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd |
78 | offset from AREG0. Leave this field at the end so as to make the | 35 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
79 | (absolute value) offset as small as possible. This reduces code | ||
80 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, | ||
81 | { | ||
82 | CPUClass *cc = CPU_GET_CLASS(cpu); | ||
83 | |||
84 | - if (cc->do_transaction_failed) { | ||
85 | + if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { | ||
86 | cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, | ||
87 | mmu_idx, attrs, response, retaddr); | ||
88 | } | ||
89 | diff --git a/qom/cpu.c b/qom/cpu.c | ||
90 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
91 | --- a/qom/cpu.c | 37 | --- a/target/arm/mve_helper.c |
92 | +++ b/qom/cpu.c | 38 | +++ b/target/arm/mve_helper.c |
93 | @@ -XXX,XX +XXX,XX @@ | 39 | @@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) |
94 | #include "exec/cpu-common.h" | 40 | DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) |
95 | #include "qemu/error-report.h" | 41 | DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) |
96 | #include "sysemu/sysemu.h" | 42 | DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) |
97 | +#include "hw/boards.h" | ||
98 | #include "hw/qdev-properties.h" | ||
99 | #include "trace-root.h" | ||
100 | |||
101 | @@ -XXX,XX +XXX,XX @@ static void cpu_common_parse_features(const char *typename, char *features, | ||
102 | static void cpu_common_realizefn(DeviceState *dev, Error **errp) | ||
103 | { | ||
104 | CPUState *cpu = CPU(dev); | ||
105 | + Object *machine = qdev_get_machine(); | ||
106 | + | 43 | + |
107 | + /* qdev_get_machine() can return something that's not TYPE_MACHINE | 44 | +uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, |
108 | + * if this is one of the user-only emulators; in that case there's | 45 | + uint32_t shift) |
109 | + * no need to check the ignore_memory_transaction_failures board flag. | 46 | +{ |
47 | + uint32_t *d = vd; | ||
48 | + uint16_t mask = mve_element_mask(env); | ||
49 | + unsigned e; | ||
50 | + uint32_t r; | ||
51 | + | ||
52 | + /* | ||
53 | + * For each 32-bit element, we shift it left, bringing in the | ||
54 | + * low 'shift' bits of rdm at the bottom. Bits shifted out at | ||
55 | + * the top become the new rdm, if the predicate mask permits. | ||
56 | + * The final rdm value is returned to update the register. | ||
57 | + * shift == 0 here means "shift by 32 bits". | ||
110 | + */ | 58 | + */ |
111 | + if (object_dynamic_cast(machine, TYPE_MACHINE)) { | 59 | + if (shift == 0) { |
112 | + ObjectClass *oc = object_get_class(machine); | 60 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { |
113 | + MachineClass *mc = MACHINE_CLASS(oc); | 61 | + r = rdm; |
62 | + if (mask & 1) { | ||
63 | + rdm = d[H4(e)]; | ||
64 | + } | ||
65 | + mergemask(&d[H4(e)], r, mask); | ||
66 | + } | ||
67 | + } else { | ||
68 | + uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); | ||
114 | + | 69 | + |
115 | + if (mc) { | 70 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { |
116 | + cpu->ignore_memory_transaction_failures = | 71 | + r = (d[H4(e)] << shift) | (rdm & shiftmask); |
117 | + mc->ignore_memory_transaction_failures; | 72 | + if (mask & 1) { |
73 | + rdm = d[H4(e)] >> (32 - shift); | ||
74 | + } | ||
75 | + mergemask(&d[H4(e)], r, mask); | ||
118 | + } | 76 | + } |
119 | + } | 77 | + } |
120 | 78 | + mve_advance_vpt(env); | |
121 | if (dev->hotplugged) { | 79 | + return rdm; |
122 | cpu_synchronize_post_init(cpu); | 80 | +} |
81 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/target/arm/translate-mve.c | ||
84 | +++ b/target/arm/translate-mve.c | ||
85 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) | ||
86 | DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) | ||
87 | DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) | ||
88 | DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | ||
89 | + | ||
90 | +static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) | ||
91 | +{ | ||
92 | + /* | ||
93 | + * Whole Vector Left Shift with Carry. The carry is taken | ||
94 | + * from a general purpose register and written back there. | ||
95 | + * An imm of 0 means "shift by 32". | ||
96 | + */ | ||
97 | + TCGv_ptr qd; | ||
98 | + TCGv_i32 rdm; | ||
99 | + | ||
100 | + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { | ||
101 | + return false; | ||
102 | + } | ||
103 | + if (a->rdm == 13 || a->rdm == 15) { | ||
104 | + /* CONSTRAINED UNPREDICTABLE: we UNDEF */ | ||
105 | + return false; | ||
106 | + } | ||
107 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
108 | + return true; | ||
109 | + } | ||
110 | + | ||
111 | + qd = mve_qreg_ptr(a->qd); | ||
112 | + rdm = load_reg(s, a->rdm); | ||
113 | + gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); | ||
114 | + store_reg(s, a->rdm, rdm); | ||
115 | + tcg_temp_free_ptr(qd); | ||
116 | + mve_update_eci(s); | ||
117 | + return true; | ||
118 | +} | ||
123 | -- | 119 | -- |
124 | 2.7.4 | 120 | 2.20.1 |
125 | 121 | ||
126 | 122 | diff view generated by jsdifflib |
1 | Implement the behavioural side of the new PMSAv8 specification. | 1 | Implement the MVE VADDLV insn; this is similar to VADDV, except |
---|---|---|---|
2 | that it accumulates 32-bit elements into a 64-bit accumulator | ||
3 | stored in a pair of general-purpose registers. | ||
2 | 4 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 1503414539-28762-3-git-send-email-peter.maydell@linaro.org | 7 | Message-id: 20210628135835.6690-15-peter.maydell@linaro.org |
6 | --- | 8 | --- |
7 | target/arm/helper.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++++- | 9 | target/arm/helper-mve.h | 3 ++ |
8 | 1 file changed, 110 insertions(+), 1 deletion(-) | 10 | target/arm/mve.decode | 6 +++- |
11 | target/arm/mve_helper.c | 19 ++++++++++++ | ||
12 | target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++ | ||
13 | 4 files changed, 90 insertions(+), 1 deletion(-) | ||
9 | 14 | ||
10 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
11 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/target/arm/helper.c | 17 | --- a/target/arm/helper-mve.h |
13 | +++ b/target/arm/helper.c | 18 | +++ b/target/arm/helper-mve.h |
14 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) |
15 | return !(*prot & (1 << access_type)); | 20 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
21 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
22 | |||
23 | +DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) | ||
24 | +DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) | ||
25 | + | ||
26 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
27 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
28 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/mve.decode | ||
32 | +++ b/target/arm/mve.decode | ||
33 | @@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
34 | VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
35 | |||
36 | # Vector add across vector | ||
37 | -VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | ||
38 | +{ | ||
39 | + VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | ||
40 | + VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \ | ||
41 | + rdahi=%rdahi rdalo=%rdalo | ||
42 | +} | ||
43 | |||
44 | # Predicate operations | ||
45 | %mask_22_13 22:1 13:3 | ||
46 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/mve_helper.c | ||
49 | +++ b/target/arm/mve_helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t) | ||
51 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
52 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
53 | |||
54 | +#define DO_VADDLV(OP, TYPE, LTYPE) \ | ||
55 | + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ | ||
56 | + uint64_t ra) \ | ||
57 | + { \ | ||
58 | + uint16_t mask = mve_element_mask(env); \ | ||
59 | + unsigned e; \ | ||
60 | + TYPE *m = vm; \ | ||
61 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
62 | + if (mask & 1) { \ | ||
63 | + ra += (LTYPE)m[H4(e)]; \ | ||
64 | + } \ | ||
65 | + } \ | ||
66 | + mve_advance_vpt(env); \ | ||
67 | + return ra; \ | ||
68 | + } \ | ||
69 | + | ||
70 | +DO_VADDLV(vaddlv_s, int32_t, int64_t) | ||
71 | +DO_VADDLV(vaddlv_u, uint32_t, uint64_t) | ||
72 | + | ||
73 | /* Shifts by immediate */ | ||
74 | #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
75 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
76 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/arm/translate-mve.c | ||
79 | +++ b/target/arm/translate-mve.c | ||
80 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) | ||
81 | return true; | ||
16 | } | 82 | } |
17 | 83 | ||
18 | +static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | 84 | +static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) |
19 | + MMUAccessType access_type, ARMMMUIdx mmu_idx, | ||
20 | + hwaddr *phys_ptr, int *prot, uint32_t *fsr) | ||
21 | +{ | 85 | +{ |
22 | + ARMCPU *cpu = arm_env_get_cpu(env); | 86 | + /* |
23 | + bool is_user = regime_is_user(env, mmu_idx); | 87 | + * Vector Add Long Across Vector: accumulate the 32-bit |
24 | + int n; | 88 | + * elements of the vector into a 64-bit result stored in |
25 | + int matchregion = -1; | 89 | + * a pair of general-purpose registers. |
26 | + bool hit = false; | 90 | + * No need to check Qm's bank: it is only 3 bits in decode. |
91 | + */ | ||
92 | + TCGv_ptr qm; | ||
93 | + TCGv_i64 rda; | ||
94 | + TCGv_i32 rdalo, rdahi; | ||
27 | + | 95 | + |
28 | + *phys_ptr = address; | 96 | + if (!dc_isar_feature(aa32_mve, s)) { |
29 | + *prot = 0; | 97 | + return false; |
30 | + | 98 | + } |
31 | + /* Unlike the ARM ARM pseudocode, we don't need to check whether this | 99 | + /* |
32 | + * was an exception vector read from the vector table (which is always | 100 | + * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related |
33 | + * done using the default system address map), because those accesses | 101 | + * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. |
34 | + * are done in arm_v7m_load_vector(), which always does a direct | ||
35 | + * read using address_space_ldl(), rather than going via this function. | ||
36 | + */ | 102 | + */ |
37 | + if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | 103 | + if (a->rdahi == 13 || a->rdahi == 15) { |
38 | + hit = true; | 104 | + return false; |
39 | + } else if (m_is_ppb_region(env, address)) { | ||
40 | + hit = true; | ||
41 | + } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { | ||
42 | + hit = true; | ||
43 | + } else { | ||
44 | + for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | ||
45 | + /* region search */ | ||
46 | + /* Note that the base address is bits [31:5] from the register | ||
47 | + * with bits [4:0] all zeroes, but the limit address is bits | ||
48 | + * [31:5] from the register with bits [4:0] all ones. | ||
49 | + */ | ||
50 | + uint32_t base = env->pmsav8.rbar[n] & ~0x1f; | ||
51 | + uint32_t limit = env->pmsav8.rlar[n] | 0x1f; | ||
52 | + | ||
53 | + if (!(env->pmsav8.rlar[n] & 0x1)) { | ||
54 | + /* Region disabled */ | ||
55 | + continue; | ||
56 | + } | ||
57 | + | ||
58 | + if (address < base || address > limit) { | ||
59 | + continue; | ||
60 | + } | ||
61 | + | ||
62 | + if (hit) { | ||
63 | + /* Multiple regions match -- always a failure (unlike | ||
64 | + * PMSAv7 where highest-numbered-region wins) | ||
65 | + */ | ||
66 | + *fsr = 0x00d; /* permission fault */ | ||
67 | + return true; | ||
68 | + } | ||
69 | + | ||
70 | + matchregion = n; | ||
71 | + hit = true; | ||
72 | + | ||
73 | + if (base & ~TARGET_PAGE_MASK) { | ||
74 | + qemu_log_mask(LOG_UNIMP, | ||
75 | + "MPU_RBAR[%d]: No support for MPU region base" | ||
76 | + "address of 0x%" PRIx32 ". Minimum alignment is " | ||
77 | + "%d\n", | ||
78 | + n, base, TARGET_PAGE_BITS); | ||
79 | + continue; | ||
80 | + } | ||
81 | + if ((limit + 1) & ~TARGET_PAGE_MASK) { | ||
82 | + qemu_log_mask(LOG_UNIMP, | ||
83 | + "MPU_RBAR[%d]: No support for MPU region limit" | ||
84 | + "address of 0x%" PRIx32 ". Minimum alignment is " | ||
85 | + "%d\n", | ||
86 | + n, limit, TARGET_PAGE_BITS); | ||
87 | + continue; | ||
88 | + } | ||
89 | + } | ||
90 | + } | 105 | + } |
91 | + | 106 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { |
92 | + if (!hit) { | ||
93 | + /* background fault */ | ||
94 | + *fsr = 0; | ||
95 | + return true; | 107 | + return true; |
96 | + } | 108 | + } |
97 | + | 109 | + |
98 | + if (matchregion == -1) { | 110 | + /* |
99 | + /* hit using the background region */ | 111 | + * This insn is subject to beat-wise execution. Partial execution |
100 | + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | 112 | + * of an A=0 (no-accumulate) insn which does not execute the first |
113 | + * beat must start with the current value of RdaHi:RdaLo, not zero. | ||
114 | + */ | ||
115 | + if (a->a || mve_skip_first_beat(s)) { | ||
116 | + /* Accumulate input from RdaHi:RdaLo */ | ||
117 | + rda = tcg_temp_new_i64(); | ||
118 | + rdalo = load_reg(s, a->rdalo); | ||
119 | + rdahi = load_reg(s, a->rdahi); | ||
120 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
121 | + tcg_temp_free_i32(rdalo); | ||
122 | + tcg_temp_free_i32(rdahi); | ||
101 | + } else { | 123 | + } else { |
102 | + uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2); | 124 | + /* Accumulate starting at zero */ |
103 | + uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1); | 125 | + rda = tcg_const_i64(0); |
104 | + | ||
105 | + if (m_is_system_region(env, address)) { | ||
106 | + /* System space is always execute never */ | ||
107 | + xn = 1; | ||
108 | + } | ||
109 | + | ||
110 | + *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | ||
111 | + if (*prot && !xn) { | ||
112 | + *prot |= PAGE_EXEC; | ||
113 | + } | ||
114 | + /* We don't need to look the attribute up in the MAIR0/MAIR1 | ||
115 | + * registers because that only tells us about cacheability. | ||
116 | + */ | ||
117 | + } | 126 | + } |
118 | + | 127 | + |
119 | + *fsr = 0x00d; /* Permission fault */ | 128 | + qm = mve_qreg_ptr(a->qm); |
120 | + return !(*prot & (1 << access_type)); | 129 | + if (a->u) { |
130 | + gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); | ||
131 | + } else { | ||
132 | + gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); | ||
133 | + } | ||
134 | + tcg_temp_free_ptr(qm); | ||
135 | + | ||
136 | + rdalo = tcg_temp_new_i32(); | ||
137 | + rdahi = tcg_temp_new_i32(); | ||
138 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
139 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
140 | + store_reg(s, a->rdalo, rdalo); | ||
141 | + store_reg(s, a->rdahi, rdahi); | ||
142 | + tcg_temp_free_i64(rda); | ||
143 | + mve_update_eci(s); | ||
144 | + return true; | ||
121 | +} | 145 | +} |
122 | + | 146 | + |
123 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, | 147 | static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) |
124 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | 148 | { |
125 | hwaddr *phys_ptr, int *prot, uint32_t *fsr) | 149 | TCGv_ptr qd; |
126 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
127 | bool ret; | ||
128 | *page_size = TARGET_PAGE_SIZE; | ||
129 | |||
130 | - if (arm_feature(env, ARM_FEATURE_V7)) { | ||
131 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
132 | + /* PMSAv8 */ | ||
133 | + ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | ||
134 | + phys_ptr, prot, fsr); | ||
135 | + } else if (arm_feature(env, ARM_FEATURE_V7)) { | ||
136 | /* PMSAv7 */ | ||
137 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | ||
138 | phys_ptr, prot, fsr); | ||
139 | -- | 150 | -- |
140 | 2.7.4 | 151 | 2.20.1 |
141 | 152 | ||
142 | 153 | diff view generated by jsdifflib |
1 | From: Portia Stephens <portia.stephens@xilinx.com> | 1 | The MVE extension to v8.1M includes some new shift instructions which |
---|---|---|---|
2 | 2 | sit entirely within the non-coprocessor part of the encoding space | |
3 | This adds a feature bit indicating support of the (trivial) Jazelle | 3 | and which operate only on general-purpose registers. They take up |
4 | implementation if ARM_FEATURE_V6 is set or if the processor is arm926 | 4 | the space which was previously UNPREDICTABLE MOVS and ORRS encodings |
5 | or arm1026. This fixes the issue that any BXJ instruction will | 5 | with Rm == 13 or 15. |
6 | result in an illegal_op. BXJ instructions will now check if the | 6 | |
7 | architecture supports ARM_FEATURE_JAZELLE. | 7 | Implement the long shifts by immediate, which perform shifts on a |
8 | 8 | pair of general-purpose registers treated as a 64-bit quantity, with | |
9 | Signed-off-by: Portia Stephens <portia.stephens@xilinx.com> | 9 | an immediate shift count between 1 and 32. |
10 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 10 | |
11 | Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com | 11 | Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for |
12 | [PMM: edited commit message and comment text a bit] | 12 | the Rm==13,15 case, we need to explicitly emit code to UNDEF for the |
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | cases where v8.1M now requires that. (Trying to change MOVS and ORRS |
14 | is too difficult, because the functions that generate the code are | ||
15 | shared between a dozen different kinds of arithmetic or logical | ||
16 | instruction for all A32, T16 and T32 encodings, and for some insns | ||
17 | and some encodings Rm==13,15 are valid.) | ||
18 | |||
19 | We make the helper functions we need for UQSHLL and SQSHLL take | ||
20 | a 32-bit value which the helper casts to int8_t because we'll need | ||
21 | these helpers also for the shift-by-register insns, where the shift | ||
22 | count might be < 0 or > 32. | ||
23 | |||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-id: 20210628135835.6690-16-peter.maydell@linaro.org | ||
15 | --- | 27 | --- |
16 | target/arm/cpu.h | 1 + | 28 | target/arm/helper-mve.h | 3 ++ |
17 | target/arm/cpu.c | 3 +++ | 29 | target/arm/translate.h | 1 + |
18 | target/arm/translate.c | 2 +- | 30 | target/arm/t32.decode | 28 +++++++++++++ |
19 | 3 files changed, 5 insertions(+), 1 deletion(-) | 31 | target/arm/mve_helper.c | 10 +++++ |
20 | 32 | target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++ | |
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 33 | 5 files changed, 132 insertions(+) |
22 | index XXXXXXX..XXXXXXX 100644 | 34 | |
23 | --- a/target/arm/cpu.h | 35 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
24 | +++ b/target/arm/cpu.h | 36 | index XXXXXXX..XXXXXXX 100644 |
25 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 37 | --- a/target/arm/helper-mve.h |
26 | ARM_FEATURE_PMU, /* has PMU support */ | 38 | +++ b/target/arm/helper-mve.h |
27 | ARM_FEATURE_VBAR, /* has cp15 VBAR */ | 39 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ | 40 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
29 | + ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ | 41 | |
30 | }; | 42 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) |
31 | 43 | + | |
32 | static inline int arm_feature(CPUARMState *env, int feature) | 44 | +DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
33 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 45 | +DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
34 | index XXXXXXX..XXXXXXX 100644 | 46 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
35 | --- a/target/arm/cpu.c | 47 | index XXXXXXX..XXXXXXX 100644 |
36 | +++ b/target/arm/cpu.c | 48 | --- a/target/arm/translate.h |
37 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 49 | +++ b/target/arm/translate.h |
38 | } | 50 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); |
39 | if (arm_feature(env, ARM_FEATURE_V6)) { | 51 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); |
40 | set_feature(env, ARM_FEATURE_V5); | 52 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); |
41 | + set_feature(env, ARM_FEATURE_JAZELLE); | 53 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); |
42 | if (!arm_feature(env, ARM_FEATURE_M)) { | 54 | +typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); |
43 | set_feature(env, ARM_FEATURE_AUXCR); | 55 | |
44 | } | 56 | /** |
45 | @@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj) | 57 | * arm_tbflags_from_tb: |
46 | set_feature(&cpu->env, ARM_FEATURE_VFP); | 58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode |
47 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | 59 | index XXXXXXX..XXXXXXX 100644 |
48 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | 60 | --- a/target/arm/t32.decode |
49 | + set_feature(&cpu->env, ARM_FEATURE_JAZELLE); | 61 | +++ b/target/arm/t32.decode |
50 | cpu->midr = 0x41069265; | 62 | @@ -XXX,XX +XXX,XX @@ |
51 | cpu->reset_fpsid = 0x41011090; | 63 | &mcr !extern cp opc1 crn crm opc2 rt |
52 | cpu->ctr = 0x1dd20d2; | 64 | &mcrr !extern cp opc1 crm rt rt2 |
53 | @@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj) | 65 | |
54 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | 66 | +&mve_shl_ri rdalo rdahi shim |
55 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | 67 | + |
56 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | 68 | +# rdahi: bits [3:1] from insn, bit 0 is 1 |
57 | + set_feature(&cpu->env, ARM_FEATURE_JAZELLE); | 69 | +# rdalo: bits [3:1] from insn, bit 0 is 0 |
58 | cpu->midr = 0x4106a262; | 70 | +%rdahi_9 9:3 !function=times_2_plus_1 |
59 | cpu->reset_fpsid = 0x410110a0; | 71 | +%rdalo_17 17:3 !function=times_2 |
60 | cpu->ctr = 0x1dd20d2; | 72 | + |
73 | # Data-processing (register) | ||
74 | |||
75 | %imm5_12_6 12:3 6:2 | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ | ||
78 | &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 | ||
79 | |||
80 | +@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ | ||
81 | + &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
82 | + | ||
83 | { | ||
84 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
85 | AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi | ||
86 | } | ||
87 | BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
88 | { | ||
89 | + # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS | ||
90 | + # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE | ||
91 | + # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that | ||
92 | + # they explicitly call unallocated_encoding() for cases that must UNDEF | ||
93 | + # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting | ||
94 | + # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
95 | + # handling them as r13 and r15 accesses with the same semantics as A32). | ||
96 | + [ | ||
97 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
98 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
99 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
100 | + | ||
101 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
102 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
103 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
104 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
105 | + ] | ||
106 | + | ||
107 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | ||
108 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | ||
109 | } | ||
110 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/target/arm/mve_helper.c | ||
113 | +++ b/target/arm/mve_helper.c | ||
114 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
115 | mve_advance_vpt(env); | ||
116 | return rdm; | ||
117 | } | ||
118 | + | ||
119 | +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
120 | +{ | ||
121 | + return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
122 | +} | ||
123 | + | ||
124 | +uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
125 | +{ | ||
126 | + return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
127 | +} | ||
61 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 128 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
62 | index XXXXXXX..XXXXXXX 100644 | 129 | index XXXXXXX..XXXXXXX 100644 |
63 | --- a/target/arm/translate.c | 130 | --- a/target/arm/translate.c |
64 | +++ b/target/arm/translate.c | 131 | +++ b/target/arm/translate.c |
65 | @@ -XXX,XX +XXX,XX @@ | 132 | @@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a) |
66 | #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) | 133 | return true; |
67 | /* currently all emulated v5 cores are also v5TE, so don't bother */ | 134 | } |
68 | #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) | 135 | |
69 | -#define ENABLE_ARCH_5J 0 | 136 | +/* |
70 | +#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE) | 137 | + * v8.1M MVE wide-shifts |
71 | #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) | 138 | + */ |
72 | #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) | 139 | +static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a, |
73 | #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) | 140 | + WideShiftImmFn *fn) |
141 | +{ | ||
142 | + TCGv_i64 rda; | ||
143 | + TCGv_i32 rdalo, rdahi; | ||
144 | + | ||
145 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
146 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
147 | + return false; | ||
148 | + } | ||
149 | + if (a->rdahi == 15) { | ||
150 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ | ||
151 | + return false; | ||
152 | + } | ||
153 | + if (!dc_isar_feature(aa32_mve, s) || | ||
154 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
155 | + a->rdahi == 13) { | ||
156 | + /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */ | ||
157 | + unallocated_encoding(s); | ||
158 | + return true; | ||
159 | + } | ||
160 | + | ||
161 | + if (a->shim == 0) { | ||
162 | + a->shim = 32; | ||
163 | + } | ||
164 | + | ||
165 | + rda = tcg_temp_new_i64(); | ||
166 | + rdalo = load_reg(s, a->rdalo); | ||
167 | + rdahi = load_reg(s, a->rdahi); | ||
168 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
169 | + | ||
170 | + fn(rda, rda, a->shim); | ||
171 | + | ||
172 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
173 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
174 | + store_reg(s, a->rdalo, rdalo); | ||
175 | + store_reg(s, a->rdahi, rdahi); | ||
176 | + tcg_temp_free_i64(rda); | ||
177 | + | ||
178 | + return true; | ||
179 | +} | ||
180 | + | ||
181 | +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
182 | +{ | ||
183 | + return do_mve_shl_ri(s, a, tcg_gen_sari_i64); | ||
184 | +} | ||
185 | + | ||
186 | +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
187 | +{ | ||
188 | + return do_mve_shl_ri(s, a, tcg_gen_shli_i64); | ||
189 | +} | ||
190 | + | ||
191 | +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
192 | +{ | ||
193 | + return do_mve_shl_ri(s, a, tcg_gen_shri_i64); | ||
194 | +} | ||
195 | + | ||
196 | +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
197 | +{ | ||
198 | + gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
199 | +} | ||
200 | + | ||
201 | +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
202 | +{ | ||
203 | + return do_mve_shl_ri(s, a, gen_mve_sqshll); | ||
204 | +} | ||
205 | + | ||
206 | +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
207 | +{ | ||
208 | + gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
209 | +} | ||
210 | + | ||
211 | +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
212 | +{ | ||
213 | + return do_mve_shl_ri(s, a, gen_mve_uqshll); | ||
214 | +} | ||
215 | + | ||
216 | +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
217 | +{ | ||
218 | + return do_mve_shl_ri(s, a, gen_srshr64_i64); | ||
219 | +} | ||
220 | + | ||
221 | +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
222 | +{ | ||
223 | + return do_mve_shl_ri(s, a, gen_urshr64_i64); | ||
224 | +} | ||
225 | + | ||
226 | /* | ||
227 | * Multiply and multiply accumulate | ||
228 | */ | ||
74 | -- | 229 | -- |
75 | 2.7.4 | 230 | 2.20.1 |
76 | 231 | ||
77 | 232 | diff view generated by jsdifflib |
1 | Make the CONTROL register banked if v8M security extensions are enabled. | 1 | Implement the MVE long shifts by register, which perform shifts on a |
---|---|---|---|
2 | pair of general-purpose registers treated as a 64-bit quantity, with | ||
3 | the shift count in another general-purpose register, which might be | ||
4 | either positive or negative. | ||
5 | |||
6 | Like the long-shifts-by-immediate, these encodings sit in the space | ||
7 | that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15. | ||
8 | Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and | ||
9 | also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases), | ||
10 | we have to move the CSEL pattern into the same decodetree group. | ||
2 | 11 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 1503414539-28762-10-git-send-email-peter.maydell@linaro.org | 14 | Message-id: 20210628135835.6690-17-peter.maydell@linaro.org |
6 | --- | 15 | --- |
7 | target/arm/cpu.h | 5 +++-- | 16 | target/arm/helper-mve.h | 6 +++ |
8 | target/arm/helper.c | 21 +++++++++++---------- | 17 | target/arm/translate.h | 1 + |
9 | target/arm/machine.c | 3 ++- | 18 | target/arm/t32.decode | 16 +++++-- |
10 | target/arm/translate.c | 2 +- | 19 | target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++ |
11 | 4 files changed, 17 insertions(+), 14 deletions(-) | 20 | target/arm/translate.c | 69 ++++++++++++++++++++++++++++++ |
12 | 21 | 5 files changed, 182 insertions(+), 3 deletions(-) | |
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 22 | |
14 | index XXXXXXX..XXXXXXX 100644 | 23 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | --- a/target/arm/cpu.h | 24 | index XXXXXXX..XXXXXXX 100644 |
16 | +++ b/target/arm/cpu.h | 25 | --- a/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 26 | +++ b/target/arm/helper-mve.h |
18 | uint32_t other_sp; | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
19 | uint32_t vecbase; | 28 | |
20 | uint32_t basepri[2]; | 29 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) |
21 | - uint32_t control; | 30 | |
22 | + uint32_t control[2]; | 31 | +DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) |
23 | uint32_t ccr; /* Configuration and Control */ | 32 | +DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
24 | uint32_t cfsr; /* Configurable Fault Status */ | 33 | DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
25 | uint32_t hfsr; /* HardFault Status */ | 34 | DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
26 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_v7m_is_handler_mode(CPUARMState *env) | 35 | +DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) |
27 | static inline int arm_current_el(CPUARMState *env) | 36 | +DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) |
28 | { | 37 | +DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) |
29 | if (arm_feature(env, ARM_FEATURE_M)) { | 38 | +DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) |
30 | - return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); | 39 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
31 | + return arm_v7m_is_handler_mode(env) || | 40 | index XXXXXXX..XXXXXXX 100644 |
32 | + !(env->v7m.control[env->v7m.secure] & 1); | 41 | --- a/target/arm/translate.h |
33 | } | 42 | +++ b/target/arm/translate.h |
34 | 43 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | |
35 | if (is_a64(env)) { | 44 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); |
36 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 45 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); |
37 | index XXXXXXX..XXXXXXX 100644 | 46 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); |
38 | --- a/target/arm/helper.c | 47 | +typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); |
39 | +++ b/target/arm/helper.c | 48 | |
40 | @@ -XXX,XX +XXX,XX @@ static uint32_t v7m_pop(CPUARMState *env) | 49 | /** |
41 | static void switch_v7m_sp(CPUARMState *env, bool new_spsel) | 50 | * arm_tbflags_from_tb: |
42 | { | 51 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode |
43 | uint32_t tmp; | 52 | index XXXXXXX..XXXXXXX 100644 |
44 | - bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; | 53 | --- a/target/arm/t32.decode |
45 | + uint32_t old_control = env->v7m.control[env->v7m.secure]; | 54 | +++ b/target/arm/t32.decode |
46 | + bool old_spsel = old_control & R_V7M_CONTROL_SPSEL_MASK; | 55 | @@ -XXX,XX +XXX,XX @@ |
47 | 56 | &mcrr !extern cp opc1 crm rt rt2 | |
48 | if (old_spsel != new_spsel) { | 57 | |
49 | tmp = env->v7m.other_sp; | 58 | &mve_shl_ri rdalo rdahi shim |
50 | env->v7m.other_sp = env->regs[13]; | 59 | +&mve_shl_rr rdalo rdahi rm |
51 | env->regs[13] = tmp; | 60 | |
52 | 61 | # rdahi: bits [3:1] from insn, bit 0 is 1 | |
53 | - env->v7m.control = deposit32(env->v7m.control, | 62 | # rdalo: bits [3:1] from insn, bit 0 is 0 |
54 | + env->v7m.control[env->v7m.secure] = deposit32(old_control, | 63 | @@ -XXX,XX +XXX,XX @@ |
55 | R_V7M_CONTROL_SPSEL_SHIFT, | 64 | |
56 | R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); | 65 | @mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ |
57 | } | 66 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 |
58 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 67 | +@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ |
59 | } | 68 | + &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 |
60 | 69 | ||
61 | lr = 0xfffffff1; | 70 | { |
62 | - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { | 71 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi |
63 | + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { | 72 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi |
64 | lr |= 4; | 73 | URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri |
65 | } | 74 | SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri |
66 | if (!arm_v7m_is_handler_mode(env)) { | 75 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri |
67 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 76 | + |
68 | return xpsr_read(env) & mask; | 77 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr |
69 | break; | 78 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr |
70 | case 20: /* CONTROL */ | 79 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr |
71 | - return env->v7m.control; | 80 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr |
72 | + return env->v7m.control[env->v7m.secure]; | 81 | + UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr |
73 | } | 82 | + SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr |
74 | 83 | ] | |
75 | if (el == 0) { | 84 | |
76 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 85 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi |
77 | 86 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | |
78 | switch (reg) { | 87 | + |
79 | case 8: /* MSP */ | 88 | + # v8.1M CSEL and friends |
80 | - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? | 89 | + CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 |
81 | + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? | 90 | } |
82 | env->v7m.other_sp : env->regs[13]; | 91 | { |
83 | case 9: /* PSP */ | 92 | MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi |
84 | - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? | 93 | @@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi |
85 | + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? | 94 | } |
86 | env->regs[13] : env->v7m.other_sp; | 95 | RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi |
87 | case 16: /* PRIMASK */ | 96 | |
88 | return env->v7m.primask[env->v7m.secure]; | 97 | -# v8.1M CSEL and friends |
89 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | 98 | -CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 |
90 | } | 99 | - |
91 | break; | 100 | # Data-processing (register-shifted register) |
92 | case 8: /* MSP */ | 101 | |
93 | - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { | 102 | MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ |
94 | + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { | 103 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
95 | env->v7m.other_sp = val; | 104 | index XXXXXXX..XXXXXXX 100644 |
96 | } else { | 105 | --- a/target/arm/mve_helper.c |
97 | env->regs[13] = val; | 106 | +++ b/target/arm/mve_helper.c |
98 | } | 107 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, |
99 | break; | 108 | return rdm; |
100 | case 9: /* PSP */ | 109 | } |
101 | - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { | 110 | |
102 | + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { | 111 | +uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) |
103 | env->regs[13] = val; | 112 | +{ |
104 | } else { | 113 | + return do_sqrshl_d(n, -(int8_t)shift, false, NULL); |
105 | env->v7m.other_sp = val; | 114 | +} |
106 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | 115 | + |
107 | if (!arm_v7m_is_handler_mode(env)) { | 116 | +uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) |
108 | switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); | 117 | +{ |
109 | } | 118 | + return do_uqrshl_d(n, (int8_t)shift, false, NULL); |
110 | - env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK; | 119 | +} |
111 | - env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK; | 120 | + |
112 | + env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; | 121 | uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) |
113 | + env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; | 122 | { |
114 | break; | 123 | return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); |
115 | default: | 124 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) |
116 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" | 125 | { |
117 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 126 | return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); |
118 | index XXXXXXX..XXXXXXX 100644 | 127 | } |
119 | --- a/target/arm/machine.c | 128 | + |
120 | +++ b/target/arm/machine.c | 129 | +uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) |
121 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | 130 | +{ |
122 | .fields = (VMStateField[]) { | 131 | + return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); |
123 | VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), | 132 | +} |
124 | VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | 133 | + |
125 | - VMSTATE_UINT32(env.v7m.control, ARMCPU), | 134 | +uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) |
126 | + VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), | 135 | +{ |
127 | VMSTATE_UINT32(env.v7m.ccr, ARMCPU), | 136 | + return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); |
128 | VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | 137 | +} |
129 | VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), | 138 | + |
130 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | 139 | +/* Operate on 64-bit values, but saturate at 48 bits */ |
131 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | 140 | +static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, |
132 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | 141 | + bool round, uint32_t *sat) |
133 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | 142 | +{ |
134 | + VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), | 143 | + if (shift <= -48) { |
135 | VMSTATE_END_OF_LIST() | 144 | + /* Rounding the sign bit always produces 0. */ |
136 | } | 145 | + if (round) { |
137 | }; | 146 | + return 0; |
147 | + } | ||
148 | + return src >> 63; | ||
149 | + } else if (shift < 0) { | ||
150 | + if (round) { | ||
151 | + src >>= -shift - 1; | ||
152 | + return (src >> 1) + (src & 1); | ||
153 | + } | ||
154 | + return src >> -shift; | ||
155 | + } else if (shift < 48) { | ||
156 | + int64_t val = src << shift; | ||
157 | + int64_t extval = sextract64(val, 0, 48); | ||
158 | + if (!sat || val == extval) { | ||
159 | + return extval; | ||
160 | + } | ||
161 | + } else if (!sat || src == 0) { | ||
162 | + return 0; | ||
163 | + } | ||
164 | + | ||
165 | + *sat = 1; | ||
166 | + return (1ULL << 47) - (src >= 0); | ||
167 | +} | ||
168 | + | ||
169 | +/* Operate on 64-bit values, but saturate at 48 bits */ | ||
170 | +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, | ||
171 | + bool round, uint32_t *sat) | ||
172 | +{ | ||
173 | + uint64_t val, extval; | ||
174 | + | ||
175 | + if (shift <= -(48 + round)) { | ||
176 | + return 0; | ||
177 | + } else if (shift < 0) { | ||
178 | + if (round) { | ||
179 | + val = src >> (-shift - 1); | ||
180 | + val = (val >> 1) + (val & 1); | ||
181 | + } else { | ||
182 | + val = src >> -shift; | ||
183 | + } | ||
184 | + extval = extract64(val, 0, 48); | ||
185 | + if (!sat || val == extval) { | ||
186 | + return extval; | ||
187 | + } | ||
188 | + } else if (shift < 48) { | ||
189 | + uint64_t val = src << shift; | ||
190 | + uint64_t extval = extract64(val, 0, 48); | ||
191 | + if (!sat || val == extval) { | ||
192 | + return extval; | ||
193 | + } | ||
194 | + } else if (!sat || src == 0) { | ||
195 | + return 0; | ||
196 | + } | ||
197 | + | ||
198 | + *sat = 1; | ||
199 | + return MAKE_64BIT_MASK(0, 48); | ||
200 | +} | ||
201 | + | ||
202 | +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
203 | +{ | ||
204 | + return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); | ||
205 | +} | ||
206 | + | ||
207 | +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
208 | +{ | ||
209 | + return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
210 | +} | ||
138 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 211 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
139 | index XXXXXXX..XXXXXXX 100644 | 212 | index XXXXXXX..XXXXXXX 100644 |
140 | --- a/target/arm/translate.c | 213 | --- a/target/arm/translate.c |
141 | +++ b/target/arm/translate.c | 214 | +++ b/target/arm/translate.c |
142 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | 215 | @@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) |
143 | if (xpsr & XPSR_EXCP) { | 216 | return do_mve_shl_ri(s, a, gen_urshr64_i64); |
144 | mode = "handler"; | 217 | } |
145 | } else { | 218 | |
146 | - if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { | 219 | +static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn) |
147 | + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { | 220 | +{ |
148 | mode = "unpriv-thread"; | 221 | + TCGv_i64 rda; |
149 | } else { | 222 | + TCGv_i32 rdalo, rdahi; |
150 | mode = "priv-thread"; | 223 | + |
224 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
225 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
226 | + return false; | ||
227 | + } | ||
228 | + if (a->rdahi == 15) { | ||
229 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ | ||
230 | + return false; | ||
231 | + } | ||
232 | + if (!dc_isar_feature(aa32_mve, s) || | ||
233 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
234 | + a->rdahi == 13 || a->rm == 13 || a->rm == 15 || | ||
235 | + a->rm == a->rdahi || a->rm == a->rdalo) { | ||
236 | + /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */ | ||
237 | + unallocated_encoding(s); | ||
238 | + return true; | ||
239 | + } | ||
240 | + | ||
241 | + rda = tcg_temp_new_i64(); | ||
242 | + rdalo = load_reg(s, a->rdalo); | ||
243 | + rdahi = load_reg(s, a->rdahi); | ||
244 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
245 | + | ||
246 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ | ||
247 | + fn(rda, cpu_env, rda, cpu_R[a->rm]); | ||
248 | + | ||
249 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
250 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
251 | + store_reg(s, a->rdalo, rdalo); | ||
252 | + store_reg(s, a->rdahi, rdahi); | ||
253 | + tcg_temp_free_i64(rda); | ||
254 | + | ||
255 | + return true; | ||
256 | +} | ||
257 | + | ||
258 | +static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
259 | +{ | ||
260 | + return do_mve_shl_rr(s, a, gen_helper_mve_ushll); | ||
261 | +} | ||
262 | + | ||
263 | +static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
264 | +{ | ||
265 | + return do_mve_shl_rr(s, a, gen_helper_mve_sshrl); | ||
266 | +} | ||
267 | + | ||
268 | +static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
269 | +{ | ||
270 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll); | ||
271 | +} | ||
272 | + | ||
273 | +static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
274 | +{ | ||
275 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl); | ||
276 | +} | ||
277 | + | ||
278 | +static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
279 | +{ | ||
280 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48); | ||
281 | +} | ||
282 | + | ||
283 | +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
284 | +{ | ||
285 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); | ||
286 | +} | ||
287 | + | ||
288 | /* | ||
289 | * Multiply and multiply accumulate | ||
290 | */ | ||
151 | -- | 291 | -- |
152 | 2.7.4 | 292 | 2.20.1 |
153 | 293 | ||
154 | 294 | diff view generated by jsdifflib |
1 | As the first step in implementing ARM v8M's security extension: | 1 | Implement the MVE shifts by immediate, which perform shifts |
---|---|---|---|
2 | * add a new feature bit ARM_FEATURE_M_SECURITY | 2 | on a single general-purpose register. |
3 | * add the CPU state field that indicates whether the CPU is | 3 | |
4 | currently in the secure state | 4 | These patterns overlap with the long-shift-by-immediates, |
5 | * add a migration subsection for this new state | 5 | so we have to rearrange the grouping a little here. |
6 | (we will add the Secure copies of banked register state | ||
7 | to this subsection in later patches) | ||
8 | * add a #define for the one new-in-v8M exception type | ||
9 | * make the CPU debug log print S/NS status | ||
10 | 6 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Message-id: 1503414539-28762-4-git-send-email-peter.maydell@linaro.org | 9 | Message-id: 20210628135835.6690-18-peter.maydell@linaro.org |
14 | --- | 10 | --- |
15 | target/arm/cpu.h | 3 +++ | 11 | target/arm/helper-mve.h | 3 ++ |
16 | target/arm/cpu.c | 4 ++++ | 12 | target/arm/translate.h | 1 + |
17 | target/arm/machine.c | 20 ++++++++++++++++++++ | 13 | target/arm/t32.decode | 31 ++++++++++++++----- |
18 | target/arm/translate.c | 8 +++++++- | 14 | target/arm/mve_helper.c | 10 ++++++ |
19 | 4 files changed, 34 insertions(+), 1 deletion(-) | 15 | target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++-- |
20 | 16 | 5 files changed, 104 insertions(+), 9 deletions(-) | |
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | |
22 | index XXXXXXX..XXXXXXX 100644 | 18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
23 | --- a/target/arm/cpu.h | 19 | index XXXXXXX..XXXXXXX 100644 |
24 | +++ b/target/arm/cpu.h | 20 | --- a/target/arm/helper-mve.h |
21 | +++ b/target/arm/helper-mve.h | ||
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
23 | DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
24 | DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
25 | DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
26 | + | ||
27 | +DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
28 | +DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
29 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate.h | ||
32 | +++ b/target/arm/translate.h | ||
33 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
34 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
35 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
36 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
37 | +typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | ||
38 | |||
39 | /** | ||
40 | * arm_tbflags_from_tb: | ||
41 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/t32.decode | ||
44 | +++ b/target/arm/t32.decode | ||
25 | @@ -XXX,XX +XXX,XX @@ | 45 | @@ -XXX,XX +XXX,XX @@ |
26 | #define ARMV7M_EXCP_MEM 4 | 46 | |
27 | #define ARMV7M_EXCP_BUS 5 | 47 | &mve_shl_ri rdalo rdahi shim |
28 | #define ARMV7M_EXCP_USAGE 6 | 48 | &mve_shl_rr rdalo rdahi rm |
29 | +#define ARMV7M_EXCP_SECURE 7 | 49 | +&mve_sh_ri rda shim |
30 | #define ARMV7M_EXCP_SVC 11 | 50 | |
31 | #define ARMV7M_EXCP_DEBUG 12 | 51 | # rdahi: bits [3:1] from insn, bit 0 is 1 |
32 | #define ARMV7M_EXCP_PENDSV 14 | 52 | # rdalo: bits [3:1] from insn, bit 0 is 0 |
33 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 53 | @@ -XXX,XX +XXX,XX @@ |
34 | int exception; | 54 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 |
35 | uint32_t primask; | 55 | @mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ |
36 | uint32_t faultmask; | 56 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 |
37 | + uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | 57 | +@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ |
38 | } v7m; | 58 | + &mve_sh_ri shim=%imm5_12_6 |
39 | 59 | ||
40 | /* Information associated with an exception about to be taken: | 60 | { |
41 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | 61 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi |
42 | ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ | 62 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi |
43 | ARM_FEATURE_PMU, /* has PMU support */ | 63 | # the rest fall through (where ORR_rrri and MOV_rxri will end up |
44 | ARM_FEATURE_VBAR, /* has cp15 VBAR */ | 64 | # handling them as r13 and r15 accesses with the same semantics as A32). |
45 | + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ | 65 | [ |
46 | }; | 66 | - LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri |
47 | 67 | - LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | |
48 | static inline int arm_feature(CPUARMState *env, int feature) | 68 | - ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri |
49 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 69 | + { |
50 | index XXXXXXX..XXXXXXX 100644 | 70 | + UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri |
51 | --- a/target/arm/cpu.c | 71 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri |
52 | +++ b/target/arm/cpu.c | 72 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri |
53 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 73 | + } |
54 | uint32_t initial_pc; /* Loaded from 0x4 */ | 74 | |
55 | uint8_t *rom; | 75 | - UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri |
56 | 76 | - URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | |
57 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 77 | - SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri |
58 | + env->v7m.secure = true; | 78 | - SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri |
59 | + } | 79 | + { |
60 | + | 80 | + URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri |
61 | /* The reset value of this bit is IMPDEF, but ARM recommends | 81 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri |
62 | * that it resets to 1, so QEMU always does that rather than making | 82 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri |
63 | * it dependent on CPU model. | 83 | + } |
64 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 84 | + |
65 | index XXXXXXX..XXXXXXX 100644 | 85 | + { |
66 | --- a/target/arm/machine.c | 86 | + SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri |
67 | +++ b/target/arm/machine.c | 87 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri |
68 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = { | 88 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri |
69 | } | 89 | + } |
70 | }; | 90 | + |
71 | 91 | + { | |
72 | +static bool m_security_needed(void *opaque) | 92 | + SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri |
73 | +{ | 93 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri |
74 | + ARMCPU *cpu = opaque; | 94 | + } |
75 | + CPUARMState *env = &cpu->env; | 95 | |
76 | + | 96 | LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr |
77 | + return arm_feature(env, ARM_FEATURE_M_SECURITY); | 97 | ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr |
78 | +} | 98 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
79 | + | 99 | index XXXXXXX..XXXXXXX 100644 |
80 | +static const VMStateDescription vmstate_m_security = { | 100 | --- a/target/arm/mve_helper.c |
81 | + .name = "cpu/m-security", | 101 | +++ b/target/arm/mve_helper.c |
82 | + .version_id = 1, | 102 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) |
83 | + .minimum_version_id = 1, | 103 | { |
84 | + .needed = m_security_needed, | 104 | return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); |
85 | + .fields = (VMStateField[]) { | 105 | } |
86 | + VMSTATE_UINT32(env.v7m.secure, ARMCPU), | 106 | + |
87 | + VMSTATE_END_OF_LIST() | 107 | +uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) |
88 | + } | 108 | +{ |
89 | +}; | 109 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); |
90 | + | 110 | +} |
91 | static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | 111 | + |
92 | VMStateField *field) | 112 | +uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) |
93 | { | 113 | +{ |
94 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = { | 114 | + return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); |
95 | &vmstate_pmsav7_rnr, | 115 | +} |
96 | &vmstate_pmsav7, | ||
97 | &vmstate_pmsav8, | ||
98 | + &vmstate_m_security, | ||
99 | NULL | ||
100 | } | ||
101 | }; | ||
102 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 116 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
103 | index XXXXXXX..XXXXXXX 100644 | 117 | index XXXXXXX..XXXXXXX 100644 |
104 | --- a/target/arm/translate.c | 118 | --- a/target/arm/translate.c |
105 | +++ b/target/arm/translate.c | 119 | +++ b/target/arm/translate.c |
106 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | 120 | @@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) |
107 | if (arm_feature(env, ARM_FEATURE_M)) { | 121 | |
108 | uint32_t xpsr = xpsr_read(env); | 122 | static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) |
109 | const char *mode; | 123 | { |
110 | + const char *ns_status = ""; | 124 | - TCGv_i32 t = tcg_temp_new_i32(); |
111 | + | 125 | + TCGv_i32 t; |
112 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 126 | |
113 | + ns_status = env->v7m.secure ? "S " : "NS "; | 127 | + /* Handle shift by the input size for the benefit of trans_SRSHR_ri */ |
114 | + } | 128 | + if (sh == 32) { |
115 | 129 | + tcg_gen_movi_i32(d, 0); | |
116 | if (xpsr & XPSR_EXCP) { | 130 | + return; |
117 | mode = "handler"; | 131 | + } |
118 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | 132 | + t = tcg_temp_new_i32(); |
119 | } | 133 | tcg_gen_extract_i32(t, a, sh - 1, 1); |
120 | } | 134 | tcg_gen_sari_i32(d, a, sh); |
121 | 135 | tcg_gen_add_i32(d, d, t); | |
122 | - cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", | 136 | @@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) |
123 | + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", | 137 | |
124 | xpsr, | 138 | static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) |
125 | xpsr & XPSR_N ? 'N' : '-', | 139 | { |
126 | xpsr & XPSR_Z ? 'Z' : '-', | 140 | - TCGv_i32 t = tcg_temp_new_i32(); |
127 | xpsr & XPSR_C ? 'C' : '-', | 141 | + TCGv_i32 t; |
128 | xpsr & XPSR_V ? 'V' : '-', | 142 | |
129 | xpsr & XPSR_T ? 'T' : 'A', | 143 | + /* Handle shift by the input size for the benefit of trans_URSHR_ri */ |
130 | + ns_status, | 144 | + if (sh == 32) { |
131 | mode); | 145 | + tcg_gen_extract_i32(d, a, sh - 1, 1); |
132 | } else { | 146 | + return; |
133 | uint32_t psr = cpsr_read(env); | 147 | + } |
148 | + t = tcg_temp_new_i32(); | ||
149 | tcg_gen_extract_i32(t, a, sh - 1, 1); | ||
150 | tcg_gen_shri_i32(d, a, sh); | ||
151 | tcg_gen_add_i32(d, d, t); | ||
152 | @@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
153 | return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); | ||
154 | } | ||
155 | |||
156 | +static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn) | ||
157 | +{ | ||
158 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
159 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
160 | + return false; | ||
161 | + } | ||
162 | + if (!dc_isar_feature(aa32_mve, s) || | ||
163 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
164 | + a->rda == 13 || a->rda == 15) { | ||
165 | + /* These rda cases are UNPREDICTABLE; we choose to UNDEF */ | ||
166 | + unallocated_encoding(s); | ||
167 | + return true; | ||
168 | + } | ||
169 | + | ||
170 | + if (a->shim == 0) { | ||
171 | + a->shim = 32; | ||
172 | + } | ||
173 | + fn(cpu_R[a->rda], cpu_R[a->rda], a->shim); | ||
174 | + | ||
175 | + return true; | ||
176 | +} | ||
177 | + | ||
178 | +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
179 | +{ | ||
180 | + return do_mve_sh_ri(s, a, gen_urshr32_i32); | ||
181 | +} | ||
182 | + | ||
183 | +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
184 | +{ | ||
185 | + return do_mve_sh_ri(s, a, gen_srshr32_i32); | ||
186 | +} | ||
187 | + | ||
188 | +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) | ||
189 | +{ | ||
190 | + gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift)); | ||
191 | +} | ||
192 | + | ||
193 | +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
194 | +{ | ||
195 | + return do_mve_sh_ri(s, a, gen_mve_sqshl); | ||
196 | +} | ||
197 | + | ||
198 | +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) | ||
199 | +{ | ||
200 | + gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift)); | ||
201 | +} | ||
202 | + | ||
203 | +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
204 | +{ | ||
205 | + return do_mve_sh_ri(s, a, gen_mve_uqshl); | ||
206 | +} | ||
207 | + | ||
208 | /* | ||
209 | * Multiply and multiply accumulate | ||
210 | */ | ||
134 | -- | 211 | -- |
135 | 2.7.4 | 212 | 2.20.1 |
136 | 213 | ||
137 | 214 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Now that MPU lookups can return different results for v8M | ||
2 | when the CPU is in secure vs non-secure state, we need to | ||
3 | have separate MMU indexes; add the secure counterparts | ||
4 | to the existing three M profile MMU indexes. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 1503414539-28762-6-git-send-email-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/cpu.h | 19 +++++++++++++++++-- | ||
11 | target/arm/helper.c | 9 ++++++++- | ||
12 | 2 files changed, 25 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | ||
19 | * Execution priority negative (this is like privileged, but the | ||
20 | * MPU HFNMIENA bit means that it may have different access permission | ||
21 | * check results to normal privileged code, so can't share a TLB). | ||
22 | + * If the CPU supports the v8M Security Extension then there are also: | ||
23 | + * Secure User | ||
24 | + * Secure Privileged | ||
25 | + * Secure, execution priority negative | ||
26 | * | ||
27 | * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code | ||
28 | * are not quite the same -- different CPU types (most notably M profile | ||
29 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx { | ||
30 | ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, | ||
31 | ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, | ||
32 | ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, | ||
33 | + ARMMMUIdx_MSUser = 3 | ARM_MMU_IDX_M, | ||
34 | + ARMMMUIdx_MSPriv = 4 | ARM_MMU_IDX_M, | ||
35 | + ARMMMUIdx_MSNegPri = 5 | ARM_MMU_IDX_M, | ||
36 | /* Indexes below here don't have TLBs and are used only for AT system | ||
37 | * instructions or for the first stage of an S12 page table walk. | ||
38 | */ | ||
39 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit { | ||
40 | ARMMMUIdxBit_MUser = 1 << 0, | ||
41 | ARMMMUIdxBit_MPriv = 1 << 1, | ||
42 | ARMMMUIdxBit_MNegPri = 1 << 2, | ||
43 | + ARMMMUIdxBit_MSUser = 1 << 3, | ||
44 | + ARMMMUIdxBit_MSPriv = 1 << 4, | ||
45 | + ARMMMUIdxBit_MSNegPri = 1 << 5, | ||
46 | } ARMMMUIdxBit; | ||
47 | |||
48 | #define MMU_USER_IDX 0 | ||
49 | @@ -XXX,XX +XXX,XX @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | ||
50 | case ARM_MMU_IDX_A: | ||
51 | return mmu_idx & 3; | ||
52 | case ARM_MMU_IDX_M: | ||
53 | - return mmu_idx == ARMMMUIdx_MUser ? 0 : 1; | ||
54 | + return (mmu_idx == ARMMMUIdx_MUser || mmu_idx == ARMMMUIdx_MSUser) | ||
55 | + ? 0 : 1; | ||
56 | default: | ||
57 | g_assert_not_reached(); | ||
58 | } | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) | ||
60 | */ | ||
61 | if ((env->v7m.exception > 0 && env->v7m.exception <= 3) | ||
62 | || env->v7m.faultmask) { | ||
63 | - return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); | ||
64 | + mmu_idx = ARMMMUIdx_MNegPri; | ||
65 | + } | ||
66 | + | ||
67 | + if (env->v7m.secure) { | ||
68 | + mmu_idx += ARMMMUIdx_MSUser; | ||
69 | } | ||
70 | |||
71 | return arm_to_core_mmu_idx(mmu_idx); | ||
72 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/target/arm/helper.c | ||
75 | +++ b/target/arm/helper.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
77 | case ARMMMUIdx_MPriv: | ||
78 | case ARMMMUIdx_MNegPri: | ||
79 | case ARMMMUIdx_MUser: | ||
80 | + case ARMMMUIdx_MSPriv: | ||
81 | + case ARMMMUIdx_MSNegPri: | ||
82 | + case ARMMMUIdx_MSUser: | ||
83 | return 1; | ||
84 | default: | ||
85 | g_assert_not_reached(); | ||
86 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
87 | case ARMMMUIdx_S1E3: | ||
88 | case ARMMMUIdx_S1SE0: | ||
89 | case ARMMMUIdx_S1SE1: | ||
90 | + case ARMMMUIdx_MSPriv: | ||
91 | + case ARMMMUIdx_MSNegPri: | ||
92 | + case ARMMMUIdx_MSUser: | ||
93 | return true; | ||
94 | default: | ||
95 | g_assert_not_reached(); | ||
96 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env, | ||
97 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { | ||
98 | case R_V7M_MPU_CTRL_ENABLE_MASK: | ||
99 | /* Enabled, but not for HardFault and NMI */ | ||
100 | - return mmu_idx == ARMMMUIdx_MNegPri; | ||
101 | + return mmu_idx == ARMMMUIdx_MNegPri || | ||
102 | + mmu_idx == ARMMMUIdx_MSNegPri; | ||
103 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: | ||
104 | /* Enabled for all cases */ | ||
105 | return false; | ||
106 | -- | ||
107 | 2.7.4 | ||
108 | |||
109 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Make the BASEPRI register banked if v8M security extensions are enabled. | ||
2 | 1 | ||
3 | Note that we do not yet implement the functionality of the new | ||
4 | AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to | ||
5 | be restricted). | ||
6 | |||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 1503414539-28762-7-git-send-email-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/cpu.h | 14 +++++++++++++- | ||
12 | hw/intc/armv7m_nvic.c | 4 ++-- | ||
13 | target/arm/helper.c | 10 ++++++---- | ||
14 | target/arm/machine.c | 3 ++- | ||
15 | 4 files changed, 23 insertions(+), 8 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpu.h | ||
20 | +++ b/target/arm/cpu.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | #define ARMV7M_EXCP_PENDSV 14 | ||
23 | #define ARMV7M_EXCP_SYSTICK 15 | ||
24 | |||
25 | +/* For M profile, some registers are banked secure vs non-secure; | ||
26 | + * these are represented as a 2-element array where the first element | ||
27 | + * is the non-secure copy and the second is the secure copy. | ||
28 | + * When the CPU does not have implement the security extension then | ||
29 | + * only the first element is used. | ||
30 | + * This means that the copy for the current security state can be | ||
31 | + * accessed via env->registerfield[env->v7m.secure] (whether the security | ||
32 | + * extension is implemented or not). | ||
33 | + */ | ||
34 | +#define M_REG_NS 0 | ||
35 | +#define M_REG_S 1 | ||
36 | + | ||
37 | /* ARM-specific interrupt pending bits. */ | ||
38 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | ||
39 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 | ||
40 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
41 | struct { | ||
42 | uint32_t other_sp; | ||
43 | uint32_t vecbase; | ||
44 | - uint32_t basepri; | ||
45 | + uint32_t basepri[2]; | ||
46 | uint32_t control; | ||
47 | uint32_t ccr; /* Configuration and Control */ | ||
48 | uint32_t cfsr; /* Configurable Fault Status */ | ||
49 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/hw/intc/armv7m_nvic.c | ||
52 | +++ b/hw/intc/armv7m_nvic.c | ||
53 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | ||
54 | running = -1; | ||
55 | } else if (env->v7m.primask) { | ||
56 | running = 0; | ||
57 | - } else if (env->v7m.basepri > 0) { | ||
58 | - running = env->v7m.basepri & nvic_gprio_mask(s); | ||
59 | + } else if (env->v7m.basepri[env->v7m.secure] > 0) { | ||
60 | + running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); | ||
61 | } else { | ||
62 | running = NVIC_NOEXC_PRIO; /* lower than any possible priority */ | ||
63 | } | ||
64 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/helper.c | ||
67 | +++ b/target/arm/helper.c | ||
68 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
69 | return env->v7m.primask; | ||
70 | case 17: /* BASEPRI */ | ||
71 | case 18: /* BASEPRI_MAX */ | ||
72 | - return env->v7m.basepri; | ||
73 | + return env->v7m.basepri[env->v7m.secure]; | ||
74 | case 19: /* FAULTMASK */ | ||
75 | return env->v7m.faultmask; | ||
76 | default: | ||
77 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
78 | env->v7m.primask = val & 1; | ||
79 | break; | ||
80 | case 17: /* BASEPRI */ | ||
81 | - env->v7m.basepri = val & 0xff; | ||
82 | + env->v7m.basepri[env->v7m.secure] = val & 0xff; | ||
83 | break; | ||
84 | case 18: /* BASEPRI_MAX */ | ||
85 | val &= 0xff; | ||
86 | - if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | ||
87 | - env->v7m.basepri = val; | ||
88 | + if (val != 0 && (val < env->v7m.basepri[env->v7m.secure] | ||
89 | + || env->v7m.basepri[env->v7m.secure] == 0)) { | ||
90 | + env->v7m.basepri[env->v7m.secure] = val; | ||
91 | + } | ||
92 | break; | ||
93 | case 19: /* FAULTMASK */ | ||
94 | env->v7m.faultmask = val & 1; | ||
95 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | ||
97 | --- a/target/arm/machine.c | ||
98 | +++ b/target/arm/machine.c | ||
99 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
100 | .needed = m_needed, | ||
101 | .fields = (VMStateField[]) { | ||
102 | VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), | ||
103 | - VMSTATE_UINT32(env.v7m.basepri, ARMCPU), | ||
104 | + VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), | ||
105 | VMSTATE_UINT32(env.v7m.control, ARMCPU), | ||
106 | VMSTATE_UINT32(env.v7m.ccr, ARMCPU), | ||
107 | VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), | ||
108 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
109 | .needed = m_security_needed, | ||
110 | .fields = (VMStateField[]) { | ||
111 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), | ||
112 | + VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | ||
113 | VMSTATE_END_OF_LIST() | ||
114 | } | ||
115 | }; | ||
116 | -- | ||
117 | 2.7.4 | ||
118 | |||
119 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Make the PRIMASK register banked if v8M security extensions are enabled. | ||
2 | 1 | ||
3 | Note that we do not yet implement the functionality of the new | ||
4 | AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to | ||
5 | be restricted). | ||
6 | |||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 1503414539-28762-8-git-send-email-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/cpu.h | 2 +- | ||
12 | hw/intc/armv7m_nvic.c | 2 +- | ||
13 | target/arm/helper.c | 4 ++-- | ||
14 | target/arm/machine.c | 9 +++++++-- | ||
15 | 4 files changed, 11 insertions(+), 6 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpu.h | ||
20 | +++ b/target/arm/cpu.h | ||
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
22 | uint32_t bfar; /* BusFault Address */ | ||
23 | unsigned mpu_ctrl; /* MPU_CTRL */ | ||
24 | int exception; | ||
25 | - uint32_t primask; | ||
26 | + uint32_t primask[2]; | ||
27 | uint32_t faultmask; | ||
28 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ | ||
29 | } v7m; | ||
30 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/intc/armv7m_nvic.c | ||
33 | +++ b/hw/intc/armv7m_nvic.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | ||
35 | |||
36 | if (env->v7m.faultmask) { | ||
37 | running = -1; | ||
38 | - } else if (env->v7m.primask) { | ||
39 | + } else if (env->v7m.primask[env->v7m.secure]) { | ||
40 | running = 0; | ||
41 | } else if (env->v7m.basepri[env->v7m.secure] > 0) { | ||
42 | running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); | ||
43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/helper.c | ||
46 | +++ b/target/arm/helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
48 | return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? | ||
49 | env->regs[13] : env->v7m.other_sp; | ||
50 | case 16: /* PRIMASK */ | ||
51 | - return env->v7m.primask; | ||
52 | + return env->v7m.primask[env->v7m.secure]; | ||
53 | case 17: /* BASEPRI */ | ||
54 | case 18: /* BASEPRI_MAX */ | ||
55 | return env->v7m.basepri[env->v7m.secure]; | ||
56 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
57 | } | ||
58 | break; | ||
59 | case 16: /* PRIMASK */ | ||
60 | - env->v7m.primask = val & 1; | ||
61 | + env->v7m.primask[env->v7m.secure] = val & 1; | ||
62 | break; | ||
63 | case 17: /* BASEPRI */ | ||
64 | env->v7m.basepri[env->v7m.secure] = val & 0xff; | ||
65 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/machine.c | ||
68 | +++ b/target/arm/machine.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = { | ||
70 | .minimum_version_id = 1, | ||
71 | .fields = (VMStateField[]) { | ||
72 | VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), | ||
73 | - VMSTATE_UINT32(env.v7m.primask, ARMCPU), | ||
74 | + VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), | ||
75 | VMSTATE_END_OF_LIST() | ||
76 | } | ||
77 | }; | ||
78 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
79 | .fields = (VMStateField[]) { | ||
80 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), | ||
81 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | ||
82 | + VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | ||
83 | VMSTATE_END_OF_LIST() | ||
84 | } | ||
85 | }; | ||
86 | @@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | ||
87 | * differences are that the T bit is not in the same place, the | ||
88 | * primask/faultmask info may be in the CPSR I and F bits, and | ||
89 | * we do not want the mode bits. | ||
90 | + * We know that this cleanup happened before v8M, so there | ||
91 | + * is no complication with banked primask/faultmask. | ||
92 | */ | ||
93 | uint32_t newval = val; | ||
94 | |||
95 | + assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); | ||
96 | + | ||
97 | newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); | ||
98 | if (val & CPSR_T) { | ||
99 | newval |= XPSR_T; | ||
100 | @@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size, | ||
101 | env->v7m.faultmask = 1; | ||
102 | } | ||
103 | if (val & CPSR_I) { | ||
104 | - env->v7m.primask = 1; | ||
105 | + env->v7m.primask[M_REG_NS] = 1; | ||
106 | } | ||
107 | val = newval; | ||
108 | } | ||
109 | -- | ||
110 | 2.7.4 | ||
111 | |||
112 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security | ||
2 | extensions are enabled. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 1503414539-28762-13-git-send-email-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/cpu.h | 4 ++-- | ||
9 | hw/intc/armv7m_nvic.c | 8 ++++---- | ||
10 | target/arm/cpu.c | 6 ++++-- | ||
11 | target/arm/machine.c | 6 ++++-- | ||
12 | 4 files changed, 14 insertions(+), 10 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
19 | */ | ||
20 | uint32_t *rbar; | ||
21 | uint32_t *rlar; | ||
22 | - uint32_t mair0; | ||
23 | - uint32_t mair1; | ||
24 | + uint32_t mair0[2]; | ||
25 | + uint32_t mair1[2]; | ||
26 | } pmsav8; | ||
27 | |||
28 | void *nvic; | ||
29 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/intc/armv7m_nvic.c | ||
32 | +++ b/hw/intc/armv7m_nvic.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
34 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
35 | goto bad_offset; | ||
36 | } | ||
37 | - return cpu->env.pmsav8.mair0; | ||
38 | + return cpu->env.pmsav8.mair0[attrs.secure]; | ||
39 | case 0xdc4: /* MPU_MAIR1 */ | ||
40 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
41 | goto bad_offset; | ||
42 | } | ||
43 | - return cpu->env.pmsav8.mair1; | ||
44 | + return cpu->env.pmsav8.mair1[attrs.secure]; | ||
45 | default: | ||
46 | bad_offset: | ||
47 | qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); | ||
48 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
49 | } | ||
50 | if (cpu->pmsav7_dregion) { | ||
51 | /* Register is RES0 if no MPU regions are implemented */ | ||
52 | - cpu->env.pmsav8.mair0 = value; | ||
53 | + cpu->env.pmsav8.mair0[attrs.secure] = value; | ||
54 | } | ||
55 | /* We don't need to do anything else because memory attributes | ||
56 | * only affect cacheability, and we don't implement caching. | ||
57 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
58 | } | ||
59 | if (cpu->pmsav7_dregion) { | ||
60 | /* Register is RES0 if no MPU regions are implemented */ | ||
61 | - cpu->env.pmsav8.mair1 = value; | ||
62 | + cpu->env.pmsav8.mair1[attrs.secure] = value; | ||
63 | } | ||
64 | /* We don't need to do anything else because memory attributes | ||
65 | * only affect cacheability, and we don't implement caching. | ||
66 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/cpu.c | ||
69 | +++ b/target/arm/cpu.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
71 | } | ||
72 | } | ||
73 | env->pmsav7.rnr = 0; | ||
74 | - env->pmsav8.mair0 = 0; | ||
75 | - env->pmsav8.mair1 = 0; | ||
76 | + env->pmsav8.mair0[M_REG_NS] = 0; | ||
77 | + env->pmsav8.mair0[M_REG_S] = 0; | ||
78 | + env->pmsav8.mair1[M_REG_NS] = 0; | ||
79 | + env->pmsav8.mair1[M_REG_S] = 0; | ||
80 | } | ||
81 | |||
82 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | ||
83 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/target/arm/machine.c | ||
86 | +++ b/target/arm/machine.c | ||
87 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = { | ||
88 | vmstate_info_uint32, uint32_t), | ||
89 | VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, | ||
90 | vmstate_info_uint32, uint32_t), | ||
91 | - VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), | ||
92 | - VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), | ||
93 | + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), | ||
94 | + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), | ||
95 | VMSTATE_END_OF_LIST() | ||
96 | } | ||
97 | }; | ||
98 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
99 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | ||
100 | VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), | ||
101 | VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), | ||
102 | + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), | ||
103 | + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), | ||
104 | VMSTATE_END_OF_LIST() | ||
105 | } | ||
106 | }; | ||
107 | -- | ||
108 | 2.7.4 | ||
109 | |||
110 | diff view generated by jsdifflib |
1 | Implement the BXNS v8M instruction, which is like BX but will do a | 1 | Implement the MVE shifts by register, which perform |
---|---|---|---|
2 | jump-and-switch-to-NonSecure if the branch target address has bit 0 | 2 | shifts on a single general-purpose register. |
3 | clear. | ||
4 | |||
5 | This is the first piece of code which implements "switch to the | ||
6 | other security state", so the commit also includes the code to | ||
7 | switch the stack pointers around, which is the only complicated | ||
8 | part of switching security state. | ||
9 | |||
10 | BLXNS is more complicated than just "BXNS but set the link register", | ||
11 | so we leave it for a separate commit. | ||
12 | 3 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 1503414539-28762-21-git-send-email-peter.maydell@linaro.org | 6 | Message-id: 20210628135835.6690-19-peter.maydell@linaro.org |
16 | --- | 7 | --- |
17 | target/arm/cpu.h | 13 +++++++++ | 8 | target/arm/helper-mve.h | 2 ++ |
18 | target/arm/helper.h | 2 ++ | 9 | target/arm/translate.h | 1 + |
19 | target/arm/translate.h | 1 + | 10 | target/arm/t32.decode | 18 ++++++++++++++---- |
20 | target/arm/helper.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ | 11 | target/arm/mve_helper.c | 10 ++++++++++ |
21 | target/arm/machine.c | 2 ++ | 12 | target/arm/translate.c | 30 ++++++++++++++++++++++++++++++ |
22 | target/arm/translate.c | 42 ++++++++++++++++++++++++++- | 13 | 5 files changed, 57 insertions(+), 4 deletions(-) |
23 | 6 files changed, 138 insertions(+), 1 deletion(-) | ||
24 | 14 | ||
25 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
26 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/helper-mve.h |
28 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/helper-mve.h |
29 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) |
30 | } cp15; | 20 | |
31 | 21 | DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | |
32 | struct { | 22 | DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) |
33 | + /* M profile has up to 4 stack pointers: | 23 | +DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32) |
34 | + * a Main Stack Pointer and a Process Stack Pointer for each | 24 | +DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32) |
35 | + * of the Secure and Non-Secure states. (If the CPU doesn't support | ||
36 | + * the security extension then it has only two SPs.) | ||
37 | + * In QEMU we always store the currently active SP in regs[13], | ||
38 | + * and the non-active SP for the current security state in | ||
39 | + * v7m.other_sp. The stack pointers for the inactive security state | ||
40 | + * are stored in other_ss_msp and other_ss_psp. | ||
41 | + * switch_v7m_security_state() is responsible for rearranging them | ||
42 | + * when we change security state. | ||
43 | + */ | ||
44 | uint32_t other_sp; | ||
45 | + uint32_t other_ss_msp; | ||
46 | + uint32_t other_ss_psp; | ||
47 | uint32_t vecbase[2]; | ||
48 | uint32_t basepri[2]; | ||
49 | uint32_t control[2]; | ||
50 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/target/arm/helper.h | ||
53 | +++ b/target/arm/helper.h | ||
54 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(cpsr_read, i32, env) | ||
55 | DEF_HELPER_3(v7m_msr, void, env, i32, i32) | ||
56 | DEF_HELPER_2(v7m_mrs, i32, env, i32) | ||
57 | |||
58 | +DEF_HELPER_2(v7m_bxns, void, env, i32) | ||
59 | + | ||
60 | DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) | ||
61 | DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) | ||
62 | DEF_HELPER_2(get_cp_reg, i32, env, ptr) | ||
63 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 25 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
64 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
65 | --- a/target/arm/translate.h | 27 | --- a/target/arm/translate.h |
66 | +++ b/target/arm/translate.h | 28 | +++ b/target/arm/translate.h |
67 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 29 | @@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); |
68 | int vec_len; | 30 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); |
69 | int vec_stride; | 31 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); |
70 | bool v7m_handler_mode; | 32 | typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); |
71 | + bool v8m_secure; /* true if v8M and we're in Secure mode */ | 33 | +typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); |
72 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI | 34 | |
73 | * so that top level loop can generate correct syndrome information. | 35 | /** |
74 | */ | 36 | * arm_tbflags_from_tb: |
75 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 37 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode |
76 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
77 | --- a/target/arm/helper.c | 39 | --- a/target/arm/t32.decode |
78 | +++ b/target/arm/helper.c | 40 | +++ b/target/arm/t32.decode |
79 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 41 | @@ -XXX,XX +XXX,XX @@ |
80 | return 0; | 42 | &mve_shl_ri rdalo rdahi shim |
43 | &mve_shl_rr rdalo rdahi rm | ||
44 | &mve_sh_ri rda shim | ||
45 | +&mve_sh_rr rda rm | ||
46 | |||
47 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
48 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
51 | @mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ | ||
52 | &mve_sh_ri shim=%imm5_12_6 | ||
53 | +@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr | ||
54 | |||
55 | { | ||
56 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
57 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
58 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
59 | } | ||
60 | |||
61 | - LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
62 | - ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
63 | - UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
64 | - SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
65 | + { | ||
66 | + UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr | ||
67 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
68 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
69 | + } | ||
70 | + | ||
71 | + { | ||
72 | + SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr | ||
73 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
74 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
75 | + } | ||
76 | + | ||
77 | UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr | ||
78 | SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr | ||
79 | ] | ||
80 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/arm/mve_helper.c | ||
83 | +++ b/target/arm/mve_helper.c | ||
84 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
85 | { | ||
86 | return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
81 | } | 87 | } |
82 | 88 | + | |
83 | +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | 89 | +uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) |
84 | +{ | 90 | +{ |
85 | + /* translate.c should never generate calls here in user-only mode */ | 91 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); |
86 | + g_assert_not_reached(); | ||
87 | +} | 92 | +} |
88 | + | 93 | + |
89 | void switch_mode(CPUARMState *env, int mode) | 94 | +uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) |
90 | { | ||
91 | ARMCPU *cpu = arm_env_get_cpu(env); | ||
92 | @@ -XXX,XX +XXX,XX @@ static uint32_t v7m_pop(CPUARMState *env) | ||
93 | return val; | ||
94 | } | ||
95 | |||
96 | +/* Return true if we're using the process stack pointer (not the MSP) */ | ||
97 | +static bool v7m_using_psp(CPUARMState *env) | ||
98 | +{ | 95 | +{ |
99 | + /* Handler mode always uses the main stack; for thread mode | 96 | + return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); |
100 | + * the CONTROL.SPSEL bit determines the answer. | ||
101 | + * Note that in v7M it is not possible to be in Handler mode with | ||
102 | + * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. | ||
103 | + */ | ||
104 | + return !arm_v7m_is_handler_mode(env) && | ||
105 | + env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; | ||
106 | +} | 97 | +} |
107 | + | ||
108 | /* Switch to V7M main or process stack pointer. */ | ||
109 | static void switch_v7m_sp(CPUARMState *env, bool new_spsel) | ||
110 | { | ||
111 | @@ -XXX,XX +XXX,XX @@ static void switch_v7m_sp(CPUARMState *env, bool new_spsel) | ||
112 | } | ||
113 | } | ||
114 | |||
115 | +/* Switch M profile security state between NS and S */ | ||
116 | +static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) | ||
117 | +{ | ||
118 | + uint32_t new_ss_msp, new_ss_psp; | ||
119 | + | ||
120 | + if (env->v7m.secure == new_secstate) { | ||
121 | + return; | ||
122 | + } | ||
123 | + | ||
124 | + /* All the banked state is accessed by looking at env->v7m.secure | ||
125 | + * except for the stack pointer; rearrange the SP appropriately. | ||
126 | + */ | ||
127 | + new_ss_msp = env->v7m.other_ss_msp; | ||
128 | + new_ss_psp = env->v7m.other_ss_psp; | ||
129 | + | ||
130 | + if (v7m_using_psp(env)) { | ||
131 | + env->v7m.other_ss_psp = env->regs[13]; | ||
132 | + env->v7m.other_ss_msp = env->v7m.other_sp; | ||
133 | + } else { | ||
134 | + env->v7m.other_ss_msp = env->regs[13]; | ||
135 | + env->v7m.other_ss_psp = env->v7m.other_sp; | ||
136 | + } | ||
137 | + | ||
138 | + env->v7m.secure = new_secstate; | ||
139 | + | ||
140 | + if (v7m_using_psp(env)) { | ||
141 | + env->regs[13] = new_ss_psp; | ||
142 | + env->v7m.other_sp = new_ss_msp; | ||
143 | + } else { | ||
144 | + env->regs[13] = new_ss_msp; | ||
145 | + env->v7m.other_sp = new_ss_psp; | ||
146 | + } | ||
147 | +} | ||
148 | + | ||
149 | +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | ||
150 | +{ | ||
151 | + /* Handle v7M BXNS: | ||
152 | + * - if the return value is a magic value, do exception return (like BX) | ||
153 | + * - otherwise bit 0 of the return value is the target security state | ||
154 | + */ | ||
155 | + if (dest >= 0xff000000) { | ||
156 | + /* This is an exception return magic value; put it where | ||
157 | + * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. | ||
158 | + * Note that if we ever add gen_ss_advance() singlestep support to | ||
159 | + * M profile this should count as an "instruction execution complete" | ||
160 | + * event (compare gen_bx_excret_final_code()). | ||
161 | + */ | ||
162 | + env->regs[15] = dest & ~1; | ||
163 | + env->thumb = dest & 1; | ||
164 | + HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); | ||
165 | + /* notreached */ | ||
166 | + } | ||
167 | + | ||
168 | + /* translate.c should have made BXNS UNDEF unless we're secure */ | ||
169 | + assert(env->v7m.secure); | ||
170 | + | ||
171 | + switch_v7m_security_state(env, dest & 1); | ||
172 | + env->thumb = 1; | ||
173 | + env->regs[15] = dest & ~1; | ||
174 | +} | ||
175 | + | ||
176 | static uint32_t arm_v7m_load_vector(ARMCPU *cpu) | ||
177 | { | ||
178 | CPUState *cs = CPU(cpu); | ||
179 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
180 | index XXXXXXX..XXXXXXX 100644 | ||
181 | --- a/target/arm/machine.c | ||
182 | +++ b/target/arm/machine.c | ||
183 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = { | ||
184 | .needed = m_security_needed, | ||
185 | .fields = (VMStateField[]) { | ||
186 | VMSTATE_UINT32(env.v7m.secure, ARMCPU), | ||
187 | + VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), | ||
188 | + VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), | ||
189 | VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), | ||
190 | VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), | ||
191 | VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), | ||
192 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 98 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
193 | index XXXXXXX..XXXXXXX 100644 | 99 | index XXXXXXX..XXXXXXX 100644 |
194 | --- a/target/arm/translate.c | 100 | --- a/target/arm/translate.c |
195 | +++ b/target/arm/translate.c | 101 | +++ b/target/arm/translate.c |
196 | @@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s) | 102 | @@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) |
197 | gen_exception_internal(EXCP_EXCEPTION_EXIT); | 103 | return do_mve_sh_ri(s, a, gen_mve_uqshl); |
198 | } | 104 | } |
199 | 105 | ||
200 | +static inline void gen_bxns(DisasContext *s, int rm) | 106 | +static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn) |
201 | +{ | 107 | +{ |
202 | + TCGv_i32 var = load_reg(s, rm); | 108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
109 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
110 | + return false; | ||
111 | + } | ||
112 | + if (!dc_isar_feature(aa32_mve, s) || | ||
113 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
114 | + a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 || | ||
115 | + a->rm == a->rda) { | ||
116 | + /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */ | ||
117 | + unallocated_encoding(s); | ||
118 | + return true; | ||
119 | + } | ||
203 | + | 120 | + |
204 | + /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory | 121 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ |
205 | + * we need to sync state before calling it, but: | 122 | + fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]); |
206 | + * - we don't need to do gen_set_pc_im() because the bxns helper will | 123 | + return true; |
207 | + * always set the PC itself | ||
208 | + * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE | ||
209 | + * unless it's outside an IT block or the last insn in an IT block, | ||
210 | + * so we know that condexec == 0 (already set at the top of the TB) | ||
211 | + * is correct in the non-UNPREDICTABLE cases, and we can choose | ||
212 | + * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise. | ||
213 | + */ | ||
214 | + gen_helper_v7m_bxns(cpu_env, var); | ||
215 | + tcg_temp_free_i32(var); | ||
216 | + s->is_jmp = DISAS_EXIT; | ||
217 | +} | 124 | +} |
218 | + | 125 | + |
219 | /* Variant of store_reg which uses branch&exchange logic when storing | 126 | +static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a) |
220 | to r15 in ARM architecture v7 and above. The source must be a temporary | 127 | +{ |
221 | and will be marked as dead. */ | 128 | + return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr); |
222 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | 129 | +} |
223 | */ | 130 | + |
224 | bool link = insn & (1 << 7); | 131 | +static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a) |
225 | 132 | +{ | |
226 | - if (insn & 7) { | 133 | + return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl); |
227 | + if (insn & 3) { | 134 | +} |
228 | goto undef; | 135 | + |
229 | } | 136 | /* |
230 | if (link) { | 137 | * Multiply and multiply accumulate |
231 | ARCH(5); | 138 | */ |
232 | } | ||
233 | + if ((insn & 4)) { | ||
234 | + /* BXNS/BLXNS: only exists for v8M with the | ||
235 | + * security extensions, and always UNDEF if NonSecure. | ||
236 | + * We don't implement these in the user-only mode | ||
237 | + * either (in theory you can use them from Secure User | ||
238 | + * mode but they are too tied in to system emulation.) | ||
239 | + */ | ||
240 | + if (!s->v8m_secure || IS_USER_ONLY) { | ||
241 | + goto undef; | ||
242 | + } | ||
243 | + if (link) { | ||
244 | + /* BLXNS: not yet implemented */ | ||
245 | + goto undef; | ||
246 | + } else { | ||
247 | + gen_bxns(s, rm); | ||
248 | + } | ||
249 | + break; | ||
250 | + } | ||
251 | + /* BLX/BX */ | ||
252 | tmp = load_reg(s, rm); | ||
253 | if (link) { | ||
254 | val = (uint32_t)s->pc | 1; | ||
255 | @@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) | ||
256 | dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); | ||
257 | dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags); | ||
258 | dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags); | ||
259 | + dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && | ||
260 | + regime_is_secure(env, dc->mmu_idx); | ||
261 | dc->cp_regs = cpu->cp_regs; | ||
262 | dc->features = env->features; | ||
263 | |||
264 | -- | 139 | -- |
265 | 2.7.4 | 140 | 2.20.1 |
266 | 141 | ||
267 | 142 | diff view generated by jsdifflib |