[Qemu-devel] [PULL 00/31] target-arm queue
[Qemu-devel] [PULL v2 00/23] target-arm queue
1
Second ARM pull request of this week; this one has my next
1
v2: dropped patches that add the microbit nRF51 non-volatile memories
2
set of v8M patches and a handful of more minor stuff from
2
and the test case for them.
3
other people.
4
3
5
thanks
4
thanks
6
-- PMM
5
-- PMM
7
6
8
The following changes since commit 8ee5f9b3ecc94e3eb7a8235f4b2c3ec9024807f6:
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7
10
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2017-09-07 10:45:18 +0100)
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The following changes since commit 3a183e330dbd7dbcac3841737ac874979552cca2:
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9
12
are available in the git repository at:
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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging (2019-01-28 16:26:47 +0000)
13
11
14
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170907
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are available in the Git repository at:
15
13
16
for you to fetch changes up to c99a55d38dd5b5131f3fcbbaf41828a09ee62544:
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190129
17
15
18
target/arm: Add Jazelle feature (2017-09-07 13:54:55 +0100)
16
for you to fetch changes up to 46f5abc0a2566ac3dc954eeb62fd625f0eaca120:
17
18
gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index (2019-01-29 11:46:06 +0000)
19
19
20
----------------------------------------------------------------
20
----------------------------------------------------------------
21
target-arm:
21
target-arm queue:
22
* cleanups converting to DEFINE_PROP_LINK
22
* Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f4a4)
23
* allwinner-a10: mark as not user-creatable
23
* v8m: Ensure IDAU is respected if SAU is disabled
24
* initial patches working towards ARMv8M support
24
* gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
25
* implement generating aborts on memory transaction failures
25
* exec.c: Use correct attrs in cpu_memory_rw_debug()
26
* make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later
26
* accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
27
* target/arm: Don't clear supported PMU events when initializing PMCEID1
28
* memory: add memory_region_flush_rom_device()
29
* microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
30
* tests/microbit-test: extend testing of microbit devices
31
* checkpatch: Don't emit spurious warnings about block comments
32
* aspeed/smc: misc bug fixes
33
* xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
34
* xlnx-zynqmp: Realize cluster after putting RPUs in it
35
* accel/tcg: Add cluster number to TCG TB hash so differently configured
36
CPUs don't pick up cached TBs for the wrong kind of CPU
27
37
28
----------------------------------------------------------------
38
----------------------------------------------------------------
29
Fam Zheng (6):
39
Aaron Lindsay OS (1):
30
armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK
40
target/arm: Don't clear supported PMU events when initializing PMCEID1
31
armv7m: Convert armv7m.memory to DEFINE_PROP_LINK
32
gicv3: Convert to DEFINE_PROP_LINK
33
xlnx_zynqmp: Convert to DEFINE_PROP_LINK
34
xilinx_axienet: Convert to DEFINE_PROP_LINK
35
xilinx_axidma: Convert to DEFINE_PROP_LINK
36
41
37
Peter Maydell (23):
42
Cédric Le Goater (4):
38
target/arm: Implement ARMv8M's PMSAv8 registers
43
aspeed/smc: fix default read value
39
target/arm: Implement new PMSAv8 behaviour
44
aspeed/smc: define registers for all possible CS
40
target/arm: Add state field, feature bit and migration for v8M secure state
45
aspeed/smc: Add dummy data register
41
target/arm: Register second AddressSpace for secure v8M CPUs
46
aspeed/smc: snoop SPI transfers to fake dummy cycles
42
target/arm: Add MMU indexes for secure v8M
43
target/arm: Make BASEPRI register banked for v8M
44
target/arm: Make PRIMASK register banked for v8M
45
target/arm: Make FAULTMASK register banked for v8M
46
target/arm: Make CONTROL register banked for v8M
47
nvic: Add NS alias SCS region
48
target/arm: Make VTOR register banked for v8M
49
target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
50
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
51
target/arm: Make MPU_RNR register banked for v8M
52
target/arm: Make MPU_CTRL register banked for v8M
53
target/arm: Make CCR register banked for v8M
54
target/arm: Make MMFAR banked for v8M
55
target/arm: Make CFSR register banked for v8M
56
target/arm: Move regime_is_secure() to target/arm/internals.h
57
target/arm: Implement BXNS, and banked stack pointers
58
boards.h: Define new flag ignore_memory_transaction_failures
59
hw/arm: Set ignore_memory_transaction_failures for most ARM boards
60
target/arm: Implement new do_transaction_failed hook
61
47
62
Portia Stephens (1):
48
Julia Suvorova (3):
63
target/arm: Add Jazelle feature
49
tests/libqtest: Introduce qtest_init_with_serial()
50
tests/microbit-test: Make test independent of global_qtest
51
tests/microbit-test: Check nRF51 UART functionality
64
52
65
Thomas Huth (1):
53
Luc Michel (1):
66
hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false
54
gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
67
55
68
include/hw/boards.h | 11 ++
56
Peter Maydell (8):
69
include/hw/intc/armv7m_nvic.h | 1 +
57
exec.c: Use correct attrs in cpu_memory_rw_debug()
70
include/qom/cpu.h | 7 +-
58
accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
71
target/arm/cpu.h | 101 ++++++++++++--
59
checkpatch: Don't emit spurious warnings about block comments
72
target/arm/helper.h | 2 +
60
xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
73
target/arm/internals.h | 36 +++++
61
hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
74
target/arm/translate.h | 1 +
62
qom/cpu: Add cluster_index to CPUState
75
hw/arm/allwinner-a10.c | 2 +
63
accel/tcg: Add cluster number to TCG TB hash
76
hw/arm/armv7m.c | 16 +--
64
gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index
77
hw/arm/aspeed.c | 3 +
78
hw/arm/collie.c | 1 +
79
hw/arm/cubieboard.c | 1 +
80
hw/arm/digic_boards.c | 1 +
81
hw/arm/exynos4_boards.c | 2 +
82
hw/arm/gumstix.c | 2 +
83
hw/arm/highbank.c | 2 +
84
hw/arm/imx25_pdk.c | 1 +
85
hw/arm/integratorcp.c | 1 +
86
hw/arm/kzm.c | 1 +
87
hw/arm/mainstone.c | 1 +
88
hw/arm/musicpal.c | 1 +
89
hw/arm/netduino2.c | 1 +
90
hw/arm/nseries.c | 2 +
91
hw/arm/omap_sx1.c | 2 +
92
hw/arm/palm.c | 1 +
93
hw/arm/raspi.c | 1 +
94
hw/arm/realview.c | 4 +
95
hw/arm/sabrelite.c | 1 +
96
hw/arm/spitz.c | 4 +
97
hw/arm/stellaris.c | 2 +
98
hw/arm/tosa.c | 1 +
99
hw/arm/versatilepb.c | 2 +
100
hw/arm/vexpress.c | 1 +
101
hw/arm/xilinx_zynq.c | 1 +
102
hw/arm/xlnx-ep108.c | 2 +
103
hw/arm/xlnx-zynqmp.c | 7 +-
104
hw/arm/z2.c | 1 +
105
hw/dma/xilinx_axidma.c | 16 +--
106
hw/intc/arm_gicv3_its_kvm.c | 19 +--
107
hw/intc/armv7m_nvic.c | 291 ++++++++++++++++++++++++++++++++------
108
hw/net/xilinx_axienet.c | 16 +--
109
qom/cpu.c | 16 +++
110
target/arm/cpu.c | 88 +++++++++---
111
target/arm/helper.c | 315 +++++++++++++++++++++++++++++++++---------
112
target/arm/machine.c | 105 ++++++++++++--
113
target/arm/op_helper.c | 43 ++++++
114
target/arm/translate.c | 54 +++++++-
115
scripts/device-crash-test | 1 -
116
48 files changed, 978 insertions(+), 213 deletions(-)
117
65
66
Richard Henderson (1):
67
target/arm: Fix validation of 32-bit address spaces for aa32
68
69
Stefan Hajnoczi (3):
70
tests/microbit-test: add TWI stub device test
71
MAINTAINERS: update microbit ARM board files
72
memory: add memory_region_flush_rom_device()
73
74
Steffen Görtz (1):
75
arm: Stub out NRF51 TWI magnetometer/accelerometer detection
76
77
Thomas Roth (1):
78
target/arm: v8m: Ensure IDAU is respected if SAU is disabled
79
80
hw/i2c/Makefile.objs | 1 +
81
include/exec/exec-all.h | 4 +-
82
include/exec/memory.h | 18 +++
83
include/hw/arm/nrf51.h | 2 +
84
include/hw/arm/nrf51_soc.h | 1 +
85
include/hw/cpu/cluster.h | 24 +++
86
include/hw/i2c/microbit_i2c.h | 42 +++++
87
include/hw/ssi/aspeed_smc.h | 3 +
88
include/qom/cpu.h | 7 +
89
target/arm/cpu.h | 11 +-
90
tests/libqtest.h | 11 ++
91
accel/tcg/cpu-exec.c | 3 +
92
accel/tcg/translate-all.c | 3 +
93
accel/tcg/user-exec.c | 66 ++++++--
94
exec.c | 19 ++-
95
gdbstub.c | 120 ++++++---------
96
hw/arm/microbit.c | 16 ++
97
hw/arm/xlnx-zynqmp.c | 9 +-
98
hw/cpu/cluster.c | 46 ++++++
99
hw/i2c/microbit_i2c.c | 127 +++++++++++++++
100
hw/ssi/aspeed_smc.c | 128 ++++++++++++++-
101
qom/cpu.c | 1 +
102
target/arm/cpu.c | 3 +-
103
target/arm/helper.c | 67 ++++----
104
tests/libqtest.c | 25 +++
105
tests/microbit-test.c | 350 +++++++++++++++++++++++++++++-------------
106
MAINTAINERS | 8 +-
107
scripts/checkpatch.pl | 2 +-
108
28 files changed, 874 insertions(+), 243 deletions(-)
109
create mode 100644 include/hw/i2c/microbit_i2c.h
110
create mode 100644 hw/i2c/microbit_i2c.c
111
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/31] armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK
Deleted patch
1
From: Fam Zheng <famz@redhat.com>
2
1
3
Signed-off-by: Fam Zheng <famz@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20170905131149.10669-2-famz@redhat.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/arm/armv7m.c | 8 ++------
10
1 file changed, 2 insertions(+), 6 deletions(-)
11
12
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/arm/armv7m.c
15
+++ b/hw/arm/armv7m.c
16
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
17
BitBandState *s = BITBAND(obj);
18
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
19
20
- object_property_add_link(obj, "source-memory",
21
- TYPE_MEMORY_REGION,
22
- (Object **)&s->source_memory,
23
- qdev_prop_allow_set_link_before_realize,
24
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
25
- &error_abort);
26
memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
27
"bitband", 0x02000000);
28
sysbus_init_mmio(dev, &s->iomem);
29
@@ -XXX,XX +XXX,XX @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
30
31
static Property bitband_properties[] = {
32
DEFINE_PROP_UINT32("base", BitBandState, base, 0),
33
+ DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
34
+ TYPE_MEMORY_REGION, MemoryRegion *),
35
DEFINE_PROP_END_OF_LIST(),
36
};
37
38
--
39
2.7.4
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/31] armv7m: Convert armv7m.memory to DEFINE_PROP_LINK
Deleted patch
1
From: Fam Zheng <famz@redhat.com>
2
1
3
Signed-off-by: Fam Zheng <famz@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20170905131149.10669-3-famz@redhat.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/arm/armv7m.c | 8 ++------
10
1 file changed, 2 insertions(+), 6 deletions(-)
11
12
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/arm/armv7m.c
15
+++ b/hw/arm/armv7m.c
16
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
17
18
/* Can't init the cpu here, we don't yet know which model to use */
19
20
- object_property_add_link(obj, "memory",
21
- TYPE_MEMORY_REGION,
22
- (Object **)&s->board_memory,
23
- qdev_prop_allow_set_link_before_realize,
24
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
25
- &error_abort);
26
memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
27
28
object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC);
29
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
30
31
static Property armv7m_properties[] = {
32
DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
33
+ DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
34
+ MemoryRegion *),
35
DEFINE_PROP_END_OF_LIST(),
36
};
37
38
--
39
2.7.4
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/31] gicv3: Convert to DEFINE_PROP_LINK
Deleted patch
1
From: Fam Zheng <famz@redhat.com>
2
1
3
Signed-off-by: Fam Zheng <famz@redhat.com>
4
Message-id: 20170905131149.10669-4-famz@redhat.com
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/intc/arm_gicv3_its_kvm.c | 19 +++++++------------
9
1 file changed, 7 insertions(+), 12 deletions(-)
10
11
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/arm_gicv3_its_kvm.c
14
+++ b/hw/intc/arm_gicv3_its_kvm.c
15
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
16
qemu_add_vm_change_state_handler(vm_change_state_handler, s);
17
}
18
19
-static void kvm_arm_its_init(Object *obj)
20
-{
21
- GICv3ITSState *s = KVM_ARM_ITS(obj);
22
-
23
- object_property_add_link(obj, "parent-gicv3",
24
- "kvm-arm-gicv3", (Object **)&s->gicv3,
25
- object_property_allow_set_link,
26
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
27
- &error_abort);
28
-}
29
-
30
/**
31
* kvm_arm_its_pre_save - handles the saving of ITS registers.
32
* ITS tables are flushed into guest RAM separately and earlier,
33
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
34
GITS_CTLR, &s->ctlr, true, &error_abort);
35
}
36
37
+static Property kvm_arm_its_props[] = {
38
+ DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3",
39
+ GICv3State *),
40
+ DEFINE_PROP_END_OF_LIST(),
41
+};
42
+
43
static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
44
{
45
DeviceClass *dc = DEVICE_CLASS(klass);
46
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
47
48
dc->realize = kvm_arm_its_realize;
49
+ dc->props = kvm_arm_its_props;
50
icc->send_msi = kvm_its_send_msi;
51
icc->pre_save = kvm_arm_its_pre_save;
52
icc->post_load = kvm_arm_its_post_load;
53
@@ -XXX,XX +XXX,XX @@ static const TypeInfo kvm_arm_its_info = {
54
.name = TYPE_KVM_ARM_ITS,
55
.parent = TYPE_ARM_GICV3_ITS_COMMON,
56
.instance_size = sizeof(GICv3ITSState),
57
- .instance_init = kvm_arm_its_init,
58
.class_init = kvm_arm_its_class_init,
59
};
60
61
--
62
2.7.4
63
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/31] xlnx_zynqmp: Convert to DEFINE_PROP_LINK
Deleted patch
1
From: Fam Zheng <famz@redhat.com>
2
1
3
Signed-off-by: Fam Zheng <famz@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20170905131149.10669-5-famz@redhat.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/arm/xlnx-zynqmp.c | 7 ++-----
10
1 file changed, 2 insertions(+), 5 deletions(-)
11
12
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/arm/xlnx-zynqmp.c
15
+++ b/hw/arm/xlnx-zynqmp.c
16
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
17
&error_abort);
18
}
19
20
- object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
21
- (Object **)&s->ddr_ram,
22
- qdev_prop_allow_set_link_before_realize,
23
- OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
24
-
25
object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
26
qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
27
28
@@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = {
29
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
30
DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
31
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
32
+ DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
33
+ MemoryRegion *),
34
DEFINE_PROP_END_OF_LIST()
35
};
36
37
--
38
2.7.4
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/31] xilinx_axienet: Convert to DEFINE_PROP_LINK
Deleted patch
1
From: Fam Zheng <famz@redhat.com>
2
1
3
Signed-off-by: Fam Zheng <famz@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20170905131149.10669-6-famz@redhat.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/net/xilinx_axienet.c | 16 ++++------------
10
1 file changed, 4 insertions(+), 12 deletions(-)
11
12
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/net/xilinx_axienet.c
15
+++ b/hw/net/xilinx_axienet.c
16
@@ -XXX,XX +XXX,XX @@ static void xilinx_enet_init(Object *obj)
17
XilinxAXIEnet *s = XILINX_AXI_ENET(obj);
18
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
19
20
- object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
21
- (Object **) &s->tx_data_dev,
22
- qdev_prop_allow_set_link_before_realize,
23
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
24
- &error_abort);
25
- object_property_add_link(obj, "axistream-control-connected",
26
- TYPE_STREAM_SLAVE,
27
- (Object **) &s->tx_control_dev,
28
- qdev_prop_allow_set_link_before_realize,
29
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
30
- &error_abort);
31
-
32
object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
33
TYPE_XILINX_AXI_ENET_DATA_STREAM);
34
object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
35
@@ -XXX,XX +XXX,XX @@ static Property xilinx_enet_properties[] = {
36
DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000),
37
DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
38
DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
39
+ DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet,
40
+ tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
41
+ DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet,
42
+ tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
43
DEFINE_PROP_END_OF_LIST(),
44
};
45
46
--
47
2.7.4
48
49
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/31] xilinx_axidma: Convert to DEFINE_PROP_LINK
Deleted patch
1
From: Fam Zheng <famz@redhat.com>
2
1
3
Signed-off-by: Fam Zheng <famz@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20170905131149.10669-7-famz@redhat.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/dma/xilinx_axidma.c | 16 ++++------------
10
1 file changed, 4 insertions(+), 12 deletions(-)
11
12
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/dma/xilinx_axidma.c
15
+++ b/hw/dma/xilinx_axidma.c
16
@@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_init(Object *obj)
17
XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
18
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
19
20
- object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
21
- (Object **)&s->tx_data_dev,
22
- qdev_prop_allow_set_link_before_realize,
23
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
24
- &error_abort);
25
- object_property_add_link(obj, "axistream-control-connected",
26
- TYPE_STREAM_SLAVE,
27
- (Object **)&s->tx_control_dev,
28
- qdev_prop_allow_set_link_before_realize,
29
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
30
- &error_abort);
31
-
32
object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
33
TYPE_XILINX_AXI_DMA_DATA_STREAM);
34
object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
35
@@ -XXX,XX +XXX,XX @@ static void xilinx_axidma_init(Object *obj)
36
37
static Property axidma_properties[] = {
38
DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
39
+ DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
40
+ tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
41
+ DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
42
+ tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
43
DEFINE_PROP_END_OF_LIST(),
44
};
45
46
--
47
2.7.4
48
49
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/31] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false
Deleted patch
1
From: Thomas Huth <thuth@redhat.com>
2
1
3
QEMU currently exits unexpectedly when the user accidentially
4
tries to do something like this:
5
6
$ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic
7
QEMU 2.9.93 monitor - type 'help' for more information
8
(qemu) device_add allwinner-a10
9
Unsupported NIC model: smc91c111
10
11
Exiting just due to a "device_add" should not happen. Looking closer
12
at the the realize and instance_init function of this device also
13
reveals that it is using serial_hds and nd_table directly there, so
14
this device is clearly not creatable by the user and should be marked
15
accordingly.
16
17
Signed-off-by: Thomas Huth <thuth@redhat.com>
18
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
19
Message-id: 1503416789-32080-1-git-send-email-thuth@redhat.com
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/arm/allwinner-a10.c | 2 ++
24
scripts/device-crash-test | 1 -
25
2 files changed, 2 insertions(+), 1 deletion(-)
26
27
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/allwinner-a10.c
30
+++ b/hw/arm/allwinner-a10.c
31
@@ -XXX,XX +XXX,XX @@ static void aw_a10_class_init(ObjectClass *oc, void *data)
32
DeviceClass *dc = DEVICE_CLASS(oc);
33
34
dc->realize = aw_a10_realize;
35
+ /* Reason: Uses serial_hds in realize and nd_table in instance_init */
36
+ dc->user_creatable = false;
37
}
38
39
static const TypeInfo aw_a10_type_info = {
40
diff --git a/scripts/device-crash-test b/scripts/device-crash-test
41
index XXXXXXX..XXXXXXX 100755
42
--- a/scripts/device-crash-test
43
+++ b/scripts/device-crash-test
44
@@ -XXX,XX +XXX,XX @@ ERROR_WHITELIST = [
45
{'log':r"Device [\w.,-]+ can not be dynamically instantiated"},
46
{'log':r"Platform Bus: Can not fit MMIO region of size "},
47
# other more specific errors we will ignore:
48
- {'device':'allwinner-a10', 'log':"Unsupported NIC model:"},
49
{'device':'.*-spapr-cpu-core', 'log':r"CPU core type should be"},
50
{'log':r"MSI(-X)? is not supported by interrupt controller"},
51
{'log':r"pxb-pcie? devices cannot reside on a PCIe? bus"},
52
--
53
2.7.4
54
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/31] target/arm: Implement ARMv8M's PMSAv8 registers
Deleted patch
1
As part of ARMv8M, we need to add support for the PMSAv8 MPU
2
architecture.
3
1
4
PMSAv8 differs from PMSAv7 both in register/data layout (for instance
5
using base and limit registers rather than base and size) and also in
6
behaviour (for example it does not have subregions); rather than
7
trying to wedge it into the existing PMSAv7 code and data structures,
8
we define separate ones.
9
10
This commit adds the data structures which hold the state for a
11
PMSAv8 MPU and the register interface to it. The implementation of
12
the MPU behaviour will be added in a subsequent commit.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 1503414539-28762-2-git-send-email-peter.maydell@linaro.org
17
---
18
target/arm/cpu.h | 13 ++++++
19
hw/intc/armv7m_nvic.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++----
20
target/arm/cpu.c | 36 ++++++++++-----
21
target/arm/machine.c | 29 +++++++++++-
22
4 files changed, 180 insertions(+), 20 deletions(-)
23
24
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpu.h
27
+++ b/target/arm/cpu.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
29
uint32_t rnr;
30
} pmsav7;
31
32
+ /* PMSAv8 MPU */
33
+ struct {
34
+ /* The PMSAv8 implementation also shares some PMSAv7 config
35
+ * and state:
36
+ * pmsav7.rnr (region number register)
37
+ * pmsav7_dregion (number of configured regions)
38
+ */
39
+ uint32_t *rbar;
40
+ uint32_t *rlar;
41
+ uint32_t mair0;
42
+ uint32_t mair1;
43
+ } pmsav8;
44
+
45
void *nvic;
46
const struct arm_boot_info *boot_info;
47
/* Store GICv3CPUState to access from this struct */
48
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/intc/armv7m_nvic.c
51
+++ b/hw/intc/armv7m_nvic.c
52
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
53
{
54
int region = cpu->env.pmsav7.rnr;
55
56
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
57
+ /* PMSAv8M handling of the aliases is different from v7M:
58
+ * aliases A1, A2, A3 override the low two bits of the region
59
+ * number in MPU_RNR, and there is no 'region' field in the
60
+ * RBAR register.
61
+ */
62
+ int aliasno = (offset - 0xd9c) / 8; /* 0..3 */
63
+ if (aliasno) {
64
+ region = deposit32(region, 0, 2, aliasno);
65
+ }
66
+ if (region >= cpu->pmsav7_dregion) {
67
+ return 0;
68
+ }
69
+ return cpu->env.pmsav8.rbar[region];
70
+ }
71
+
72
if (region >= cpu->pmsav7_dregion) {
73
return 0;
74
}
75
return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
76
}
77
- case 0xda0: /* MPU_RASR */
78
- case 0xda8: /* MPU_RASR_A1 */
79
- case 0xdb0: /* MPU_RASR_A2 */
80
- case 0xdb8: /* MPU_RASR_A3 */
81
+ case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
82
+ case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
83
+ case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
84
+ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
85
{
86
int region = cpu->env.pmsav7.rnr;
87
88
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
89
+ /* PMSAv8M handling of the aliases is different from v7M:
90
+ * aliases A1, A2, A3 override the low two bits of the region
91
+ * number in MPU_RNR.
92
+ */
93
+ int aliasno = (offset - 0xda0) / 8; /* 0..3 */
94
+ if (aliasno) {
95
+ region = deposit32(region, 0, 2, aliasno);
96
+ }
97
+ if (region >= cpu->pmsav7_dregion) {
98
+ return 0;
99
+ }
100
+ return cpu->env.pmsav8.rlar[region];
101
+ }
102
+
103
if (region >= cpu->pmsav7_dregion) {
104
return 0;
105
}
106
return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) |
107
(cpu->env.pmsav7.drsr[region] & 0xffff);
108
}
109
+ case 0xdc0: /* MPU_MAIR0 */
110
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
111
+ goto bad_offset;
112
+ }
113
+ return cpu->env.pmsav8.mair0;
114
+ case 0xdc4: /* MPU_MAIR1 */
115
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
116
+ goto bad_offset;
117
+ }
118
+ return cpu->env.pmsav8.mair1;
119
default:
120
+ bad_offset:
121
qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
122
return 0;
123
}
124
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
125
{
126
int region;
127
128
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
129
+ /* PMSAv8M handling of the aliases is different from v7M:
130
+ * aliases A1, A2, A3 override the low two bits of the region
131
+ * number in MPU_RNR, and there is no 'region' field in the
132
+ * RBAR register.
133
+ */
134
+ int aliasno = (offset - 0xd9c) / 8; /* 0..3 */
135
+
136
+ region = cpu->env.pmsav7.rnr;
137
+ if (aliasno) {
138
+ region = deposit32(region, 0, 2, aliasno);
139
+ }
140
+ if (region >= cpu->pmsav7_dregion) {
141
+ return;
142
+ }
143
+ cpu->env.pmsav8.rbar[region] = value;
144
+ tlb_flush(CPU(cpu));
145
+ return;
146
+ }
147
+
148
if (value & (1 << 4)) {
149
/* VALID bit means use the region number specified in this
150
* value and also update MPU_RNR.REGION with that value.
151
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
152
tlb_flush(CPU(cpu));
153
break;
154
}
155
- case 0xda0: /* MPU_RASR */
156
- case 0xda8: /* MPU_RASR_A1 */
157
- case 0xdb0: /* MPU_RASR_A2 */
158
- case 0xdb8: /* MPU_RASR_A3 */
159
+ case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
160
+ case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
161
+ case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
162
+ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
163
{
164
int region = cpu->env.pmsav7.rnr;
165
166
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
167
+ /* PMSAv8M handling of the aliases is different from v7M:
168
+ * aliases A1, A2, A3 override the low two bits of the region
169
+ * number in MPU_RNR.
170
+ */
171
+ int aliasno = (offset - 0xd9c) / 8; /* 0..3 */
172
+
173
+ region = cpu->env.pmsav7.rnr;
174
+ if (aliasno) {
175
+ region = deposit32(region, 0, 2, aliasno);
176
+ }
177
+ if (region >= cpu->pmsav7_dregion) {
178
+ return;
179
+ }
180
+ cpu->env.pmsav8.rlar[region] = value;
181
+ tlb_flush(CPU(cpu));
182
+ return;
183
+ }
184
+
185
if (region >= cpu->pmsav7_dregion) {
186
return;
187
}
188
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
189
tlb_flush(CPU(cpu));
190
break;
191
}
192
+ case 0xdc0: /* MPU_MAIR0 */
193
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
194
+ goto bad_offset;
195
+ }
196
+ if (cpu->pmsav7_dregion) {
197
+ /* Register is RES0 if no MPU regions are implemented */
198
+ cpu->env.pmsav8.mair0 = value;
199
+ }
200
+ /* We don't need to do anything else because memory attributes
201
+ * only affect cacheability, and we don't implement caching.
202
+ */
203
+ break;
204
+ case 0xdc4: /* MPU_MAIR1 */
205
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
206
+ goto bad_offset;
207
+ }
208
+ if (cpu->pmsav7_dregion) {
209
+ /* Register is RES0 if no MPU regions are implemented */
210
+ cpu->env.pmsav8.mair1 = value;
211
+ }
212
+ /* We don't need to do anything else because memory attributes
213
+ * only affect cacheability, and we don't implement caching.
214
+ */
215
+ break;
216
case 0xf00: /* Software Triggered Interrupt Register */
217
{
218
int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
219
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
220
break;
221
}
222
default:
223
+ bad_offset:
224
qemu_log_mask(LOG_GUEST_ERROR,
225
"NVIC: Bad write offset 0x%x\n", offset);
226
}
227
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/target/arm/cpu.c
230
+++ b/target/arm/cpu.c
231
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
232
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
233
#endif
234
235
- if (arm_feature(env, ARM_FEATURE_PMSA) &&
236
- arm_feature(env, ARM_FEATURE_V7)) {
237
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
238
if (cpu->pmsav7_dregion > 0) {
239
- memset(env->pmsav7.drbar, 0,
240
- sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
241
- memset(env->pmsav7.drsr, 0,
242
- sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
243
- memset(env->pmsav7.dracr, 0,
244
- sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
245
+ if (arm_feature(env, ARM_FEATURE_V8)) {
246
+ memset(env->pmsav8.rbar, 0,
247
+ sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion);
248
+ memset(env->pmsav8.rlar, 0,
249
+ sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion);
250
+ } else if (arm_feature(env, ARM_FEATURE_V7)) {
251
+ memset(env->pmsav7.drbar, 0,
252
+ sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
253
+ memset(env->pmsav7.drsr, 0,
254
+ sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
255
+ memset(env->pmsav7.dracr, 0,
256
+ sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
257
+ }
258
}
259
env->pmsav7.rnr = 0;
260
+ env->pmsav8.mair0 = 0;
261
+ env->pmsav8.mair1 = 0;
262
}
263
264
set_flush_to_zero(1, &env->vfp.standard_fp_status);
265
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
266
}
267
268
if (nr) {
269
- env->pmsav7.drbar = g_new0(uint32_t, nr);
270
- env->pmsav7.drsr = g_new0(uint32_t, nr);
271
- env->pmsav7.dracr = g_new0(uint32_t, nr);
272
+ if (arm_feature(env, ARM_FEATURE_V8)) {
273
+ /* PMSAv8 */
274
+ env->pmsav8.rbar = g_new0(uint32_t, nr);
275
+ env->pmsav8.rlar = g_new0(uint32_t, nr);
276
+ } else {
277
+ env->pmsav7.drbar = g_new0(uint32_t, nr);
278
+ env->pmsav7.drsr = g_new0(uint32_t, nr);
279
+ env->pmsav7.dracr = g_new0(uint32_t, nr);
280
+ }
281
}
282
}
283
284
diff --git a/target/arm/machine.c b/target/arm/machine.c
285
index XXXXXXX..XXXXXXX 100644
286
--- a/target/arm/machine.c
287
+++ b/target/arm/machine.c
288
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_needed(void *opaque)
289
CPUARMState *env = &cpu->env;
290
291
return arm_feature(env, ARM_FEATURE_PMSA) &&
292
- arm_feature(env, ARM_FEATURE_V7);
293
+ arm_feature(env, ARM_FEATURE_V7) &&
294
+ !arm_feature(env, ARM_FEATURE_V8);
295
}
296
297
static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
298
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav7_rnr = {
299
}
300
};
301
302
+static bool pmsav8_needed(void *opaque)
303
+{
304
+ ARMCPU *cpu = opaque;
305
+ CPUARMState *env = &cpu->env;
306
+
307
+ return arm_feature(env, ARM_FEATURE_PMSA) &&
308
+ arm_feature(env, ARM_FEATURE_V8);
309
+}
310
+
311
+static const VMStateDescription vmstate_pmsav8 = {
312
+ .name = "cpu/pmsav8",
313
+ .version_id = 1,
314
+ .minimum_version_id = 1,
315
+ .needed = pmsav8_needed,
316
+ .fields = (VMStateField[]) {
317
+ VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0,
318
+ vmstate_info_uint32, uint32_t),
319
+ VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0,
320
+ vmstate_info_uint32, uint32_t),
321
+ VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU),
322
+ VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU),
323
+ VMSTATE_END_OF_LIST()
324
+ }
325
+};
326
+
327
static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
328
VMStateField *field)
329
{
330
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = {
331
*/
332
&vmstate_pmsav7_rnr,
333
&vmstate_pmsav7,
334
+ &vmstate_pmsav8,
335
NULL
336
}
337
};
338
--
339
2.7.4
340
341
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/31] target/arm: Implement new PMSAv8 behaviour
Deleted patch
1
Implement the behavioural side of the new PMSAv8 specification.
2
1
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1503414539-28762-3-git-send-email-peter.maydell@linaro.org
6
---
7
target/arm/helper.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++++-
8
1 file changed, 110 insertions(+), 1 deletion(-)
9
10
diff --git a/target/arm/helper.c b/target/arm/helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/arm/helper.c
13
+++ b/target/arm/helper.c
14
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
15
return !(*prot & (1 << access_type));
16
}
17
18
+static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
19
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
20
+ hwaddr *phys_ptr, int *prot, uint32_t *fsr)
21
+{
22
+ ARMCPU *cpu = arm_env_get_cpu(env);
23
+ bool is_user = regime_is_user(env, mmu_idx);
24
+ int n;
25
+ int matchregion = -1;
26
+ bool hit = false;
27
+
28
+ *phys_ptr = address;
29
+ *prot = 0;
30
+
31
+ /* Unlike the ARM ARM pseudocode, we don't need to check whether this
32
+ * was an exception vector read from the vector table (which is always
33
+ * done using the default system address map), because those accesses
34
+ * are done in arm_v7m_load_vector(), which always does a direct
35
+ * read using address_space_ldl(), rather than going via this function.
36
+ */
37
+ if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
38
+ hit = true;
39
+ } else if (m_is_ppb_region(env, address)) {
40
+ hit = true;
41
+ } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
42
+ hit = true;
43
+ } else {
44
+ for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
45
+ /* region search */
46
+ /* Note that the base address is bits [31:5] from the register
47
+ * with bits [4:0] all zeroes, but the limit address is bits
48
+ * [31:5] from the register with bits [4:0] all ones.
49
+ */
50
+ uint32_t base = env->pmsav8.rbar[n] & ~0x1f;
51
+ uint32_t limit = env->pmsav8.rlar[n] | 0x1f;
52
+
53
+ if (!(env->pmsav8.rlar[n] & 0x1)) {
54
+ /* Region disabled */
55
+ continue;
56
+ }
57
+
58
+ if (address < base || address > limit) {
59
+ continue;
60
+ }
61
+
62
+ if (hit) {
63
+ /* Multiple regions match -- always a failure (unlike
64
+ * PMSAv7 where highest-numbered-region wins)
65
+ */
66
+ *fsr = 0x00d; /* permission fault */
67
+ return true;
68
+ }
69
+
70
+ matchregion = n;
71
+ hit = true;
72
+
73
+ if (base & ~TARGET_PAGE_MASK) {
74
+ qemu_log_mask(LOG_UNIMP,
75
+ "MPU_RBAR[%d]: No support for MPU region base"
76
+ "address of 0x%" PRIx32 ". Minimum alignment is "
77
+ "%d\n",
78
+ n, base, TARGET_PAGE_BITS);
79
+ continue;
80
+ }
81
+ if ((limit + 1) & ~TARGET_PAGE_MASK) {
82
+ qemu_log_mask(LOG_UNIMP,
83
+ "MPU_RBAR[%d]: No support for MPU region limit"
84
+ "address of 0x%" PRIx32 ". Minimum alignment is "
85
+ "%d\n",
86
+ n, limit, TARGET_PAGE_BITS);
87
+ continue;
88
+ }
89
+ }
90
+ }
91
+
92
+ if (!hit) {
93
+ /* background fault */
94
+ *fsr = 0;
95
+ return true;
96
+ }
97
+
98
+ if (matchregion == -1) {
99
+ /* hit using the background region */
100
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
101
+ } else {
102
+ uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2);
103
+ uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1);
104
+
105
+ if (m_is_system_region(env, address)) {
106
+ /* System space is always execute never */
107
+ xn = 1;
108
+ }
109
+
110
+ *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
111
+ if (*prot && !xn) {
112
+ *prot |= PAGE_EXEC;
113
+ }
114
+ /* We don't need to look the attribute up in the MAIR0/MAIR1
115
+ * registers because that only tells us about cacheability.
116
+ */
117
+ }
118
+
119
+ *fsr = 0x00d; /* Permission fault */
120
+ return !(*prot & (1 << access_type));
121
+}
122
+
123
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
124
MMUAccessType access_type, ARMMMUIdx mmu_idx,
125
hwaddr *phys_ptr, int *prot, uint32_t *fsr)
126
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
127
bool ret;
128
*page_size = TARGET_PAGE_SIZE;
129
130
- if (arm_feature(env, ARM_FEATURE_V7)) {
131
+ if (arm_feature(env, ARM_FEATURE_V8)) {
132
+ /* PMSAv8 */
133
+ ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
134
+ phys_ptr, prot, fsr);
135
+ } else if (arm_feature(env, ARM_FEATURE_V7)) {
136
/* PMSAv7 */
137
ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
138
phys_ptr, prot, fsr);
139
--
140
2.7.4
141
142
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/31] target/arm: Add state field, feature bit and migration for v8M secure state
Deleted patch
1
As the first step in implementing ARM v8M's security extension:
2
* add a new feature bit ARM_FEATURE_M_SECURITY
3
* add the CPU state field that indicates whether the CPU is
4
currently in the secure state
5
* add a migration subsection for this new state
6
(we will add the Secure copies of banked register state
7
to this subsection in later patches)
8
* add a #define for the one new-in-v8M exception type
9
* make the CPU debug log print S/NS status
10
1
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 1503414539-28762-4-git-send-email-peter.maydell@linaro.org
14
---
15
target/arm/cpu.h | 3 +++
16
target/arm/cpu.c | 4 ++++
17
target/arm/machine.c | 20 ++++++++++++++++++++
18
target/arm/translate.c | 8 +++++++-
19
4 files changed, 34 insertions(+), 1 deletion(-)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@
26
#define ARMV7M_EXCP_MEM 4
27
#define ARMV7M_EXCP_BUS 5
28
#define ARMV7M_EXCP_USAGE 6
29
+#define ARMV7M_EXCP_SECURE 7
30
#define ARMV7M_EXCP_SVC 11
31
#define ARMV7M_EXCP_DEBUG 12
32
#define ARMV7M_EXCP_PENDSV 14
33
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
34
int exception;
35
uint32_t primask;
36
uint32_t faultmask;
37
+ uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
38
} v7m;
39
40
/* Information associated with an exception about to be taken:
41
@@ -XXX,XX +XXX,XX @@ enum arm_features {
42
ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
43
ARM_FEATURE_PMU, /* has PMU support */
44
ARM_FEATURE_VBAR, /* has cp15 VBAR */
45
+ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
46
};
47
48
static inline int arm_feature(CPUARMState *env, int feature)
49
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/cpu.c
52
+++ b/target/arm/cpu.c
53
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
54
uint32_t initial_pc; /* Loaded from 0x4 */
55
uint8_t *rom;
56
57
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
58
+ env->v7m.secure = true;
59
+ }
60
+
61
/* The reset value of this bit is IMPDEF, but ARM recommends
62
* that it resets to 1, so QEMU always does that rather than making
63
* it dependent on CPU model.
64
diff --git a/target/arm/machine.c b/target/arm/machine.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/machine.c
67
+++ b/target/arm/machine.c
68
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
69
}
70
};
71
72
+static bool m_security_needed(void *opaque)
73
+{
74
+ ARMCPU *cpu = opaque;
75
+ CPUARMState *env = &cpu->env;
76
+
77
+ return arm_feature(env, ARM_FEATURE_M_SECURITY);
78
+}
79
+
80
+static const VMStateDescription vmstate_m_security = {
81
+ .name = "cpu/m-security",
82
+ .version_id = 1,
83
+ .minimum_version_id = 1,
84
+ .needed = m_security_needed,
85
+ .fields = (VMStateField[]) {
86
+ VMSTATE_UINT32(env.v7m.secure, ARMCPU),
87
+ VMSTATE_END_OF_LIST()
88
+ }
89
+};
90
+
91
static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
92
VMStateField *field)
93
{
94
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = {
95
&vmstate_pmsav7_rnr,
96
&vmstate_pmsav7,
97
&vmstate_pmsav8,
98
+ &vmstate_m_security,
99
NULL
100
}
101
};
102
diff --git a/target/arm/translate.c b/target/arm/translate.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate.c
105
+++ b/target/arm/translate.c
106
@@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
107
if (arm_feature(env, ARM_FEATURE_M)) {
108
uint32_t xpsr = xpsr_read(env);
109
const char *mode;
110
+ const char *ns_status = "";
111
+
112
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
113
+ ns_status = env->v7m.secure ? "S " : "NS ";
114
+ }
115
116
if (xpsr & XPSR_EXCP) {
117
mode = "handler";
118
@@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
119
}
120
}
121
122
- cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n",
123
+ cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
124
xpsr,
125
xpsr & XPSR_N ? 'N' : '-',
126
xpsr & XPSR_Z ? 'Z' : '-',
127
xpsr & XPSR_C ? 'C' : '-',
128
xpsr & XPSR_V ? 'V' : '-',
129
xpsr & XPSR_T ? 'T' : 'A',
130
+ ns_status,
131
mode);
132
} else {
133
uint32_t psr = cpsr_read(env);
134
--
135
2.7.4
136
137
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/31] target/arm: Register second AddressSpace for secure v8M CPUs
Deleted patch
1
If a v8M CPU supports the security extension then we need to
2
give it two AddressSpaces, the same way we do already for
3
an A profile core with EL3.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 1503414539-28762-5-git-send-email-peter.maydell@linaro.org
8
---
9
target/arm/cpu.c | 13 ++++++-------
10
1 file changed, 6 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
17
init_cpreg_list(cpu);
18
19
#ifndef CONFIG_USER_ONLY
20
- if (cpu->has_el3) {
21
- cs->num_ases = 2;
22
- } else {
23
- cs->num_ases = 1;
24
- }
25
-
26
- if (cpu->has_el3) {
27
+ if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
28
AddressSpace *as;
29
30
+ cs->num_ases = 2;
31
+
32
if (!cpu->secure_memory) {
33
cpu->secure_memory = cs->memory;
34
}
35
as = address_space_init_shareable(cpu->secure_memory,
36
"cpu-secure-memory");
37
cpu_address_space_init(cs, as, ARMASIdx_S);
38
+ } else {
39
+ cs->num_ases = 1;
40
}
41
+
42
cpu_address_space_init(cs,
43
address_space_init_shareable(cs->memory,
44
"cpu-memory"),
45
--
46
2.7.4
47
48
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/31] target/arm: Add MMU indexes for secure v8M
Deleted patch
1
Now that MPU lookups can return different results for v8M
2
when the CPU is in secure vs non-secure state, we need to
3
have separate MMU indexes; add the secure counterparts
4
to the existing three M profile MMU indexes.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1503414539-28762-6-git-send-email-peter.maydell@linaro.org
9
---
10
target/arm/cpu.h | 19 +++++++++++++++++--
11
target/arm/helper.c | 9 ++++++++-
12
2 files changed, 25 insertions(+), 3 deletions(-)
13
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
19
* Execution priority negative (this is like privileged, but the
20
* MPU HFNMIENA bit means that it may have different access permission
21
* check results to normal privileged code, so can't share a TLB).
22
+ * If the CPU supports the v8M Security Extension then there are also:
23
+ * Secure User
24
+ * Secure Privileged
25
+ * Secure, execution priority negative
26
*
27
* The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
28
* are not quite the same -- different CPU types (most notably M profile
29
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
30
ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
31
ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
32
ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M,
33
+ ARMMMUIdx_MSUser = 3 | ARM_MMU_IDX_M,
34
+ ARMMMUIdx_MSPriv = 4 | ARM_MMU_IDX_M,
35
+ ARMMMUIdx_MSNegPri = 5 | ARM_MMU_IDX_M,
36
/* Indexes below here don't have TLBs and are used only for AT system
37
* instructions or for the first stage of an S12 page table walk.
38
*/
39
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
40
ARMMMUIdxBit_MUser = 1 << 0,
41
ARMMMUIdxBit_MPriv = 1 << 1,
42
ARMMMUIdxBit_MNegPri = 1 << 2,
43
+ ARMMMUIdxBit_MSUser = 1 << 3,
44
+ ARMMMUIdxBit_MSPriv = 1 << 4,
45
+ ARMMMUIdxBit_MSNegPri = 1 << 5,
46
} ARMMMUIdxBit;
47
48
#define MMU_USER_IDX 0
49
@@ -XXX,XX +XXX,XX @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
50
case ARM_MMU_IDX_A:
51
return mmu_idx & 3;
52
case ARM_MMU_IDX_M:
53
- return mmu_idx == ARMMMUIdx_MUser ? 0 : 1;
54
+ return (mmu_idx == ARMMMUIdx_MUser || mmu_idx == ARMMMUIdx_MSUser)
55
+ ? 0 : 1;
56
default:
57
g_assert_not_reached();
58
}
59
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
60
*/
61
if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
62
|| env->v7m.faultmask) {
63
- return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri);
64
+ mmu_idx = ARMMMUIdx_MNegPri;
65
+ }
66
+
67
+ if (env->v7m.secure) {
68
+ mmu_idx += ARMMMUIdx_MSUser;
69
}
70
71
return arm_to_core_mmu_idx(mmu_idx);
72
diff --git a/target/arm/helper.c b/target/arm/helper.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/helper.c
75
+++ b/target/arm/helper.c
76
@@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
77
case ARMMMUIdx_MPriv:
78
case ARMMMUIdx_MNegPri:
79
case ARMMMUIdx_MUser:
80
+ case ARMMMUIdx_MSPriv:
81
+ case ARMMMUIdx_MSNegPri:
82
+ case ARMMMUIdx_MSUser:
83
return 1;
84
default:
85
g_assert_not_reached();
86
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
87
case ARMMMUIdx_S1E3:
88
case ARMMMUIdx_S1SE0:
89
case ARMMMUIdx_S1SE1:
90
+ case ARMMMUIdx_MSPriv:
91
+ case ARMMMUIdx_MSNegPri:
92
+ case ARMMMUIdx_MSUser:
93
return true;
94
default:
95
g_assert_not_reached();
96
@@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env,
97
(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
98
case R_V7M_MPU_CTRL_ENABLE_MASK:
99
/* Enabled, but not for HardFault and NMI */
100
- return mmu_idx == ARMMMUIdx_MNegPri;
101
+ return mmu_idx == ARMMMUIdx_MNegPri ||
102
+ mmu_idx == ARMMMUIdx_MSNegPri;
103
case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
104
/* Enabled for all cases */
105
return false;
106
--
107
2.7.4
108
109
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/31] target/arm: Make BASEPRI register banked for v8M
Deleted patch
1
Make the BASEPRI register banked if v8M security extensions are enabled.
2
1
3
Note that we do not yet implement the functionality of the new
4
AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to
5
be restricted).
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 1503414539-28762-7-git-send-email-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 14 +++++++++++++-
12
hw/intc/armv7m_nvic.c | 4 ++--
13
target/arm/helper.c | 10 ++++++----
14
target/arm/machine.c | 3 ++-
15
4 files changed, 23 insertions(+), 8 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@
22
#define ARMV7M_EXCP_PENDSV 14
23
#define ARMV7M_EXCP_SYSTICK 15
24
25
+/* For M profile, some registers are banked secure vs non-secure;
26
+ * these are represented as a 2-element array where the first element
27
+ * is the non-secure copy and the second is the secure copy.
28
+ * When the CPU does not have implement the security extension then
29
+ * only the first element is used.
30
+ * This means that the copy for the current security state can be
31
+ * accessed via env->registerfield[env->v7m.secure] (whether the security
32
+ * extension is implemented or not).
33
+ */
34
+#define M_REG_NS 0
35
+#define M_REG_S 1
36
+
37
/* ARM-specific interrupt pending bits. */
38
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
39
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
40
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
41
struct {
42
uint32_t other_sp;
43
uint32_t vecbase;
44
- uint32_t basepri;
45
+ uint32_t basepri[2];
46
uint32_t control;
47
uint32_t ccr; /* Configuration and Control */
48
uint32_t cfsr; /* Configurable Fault Status */
49
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/intc/armv7m_nvic.c
52
+++ b/hw/intc/armv7m_nvic.c
53
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
54
running = -1;
55
} else if (env->v7m.primask) {
56
running = 0;
57
- } else if (env->v7m.basepri > 0) {
58
- running = env->v7m.basepri & nvic_gprio_mask(s);
59
+ } else if (env->v7m.basepri[env->v7m.secure] > 0) {
60
+ running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
61
} else {
62
running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
63
}
64
diff --git a/target/arm/helper.c b/target/arm/helper.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/helper.c
67
+++ b/target/arm/helper.c
68
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
69
return env->v7m.primask;
70
case 17: /* BASEPRI */
71
case 18: /* BASEPRI_MAX */
72
- return env->v7m.basepri;
73
+ return env->v7m.basepri[env->v7m.secure];
74
case 19: /* FAULTMASK */
75
return env->v7m.faultmask;
76
default:
77
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
78
env->v7m.primask = val & 1;
79
break;
80
case 17: /* BASEPRI */
81
- env->v7m.basepri = val & 0xff;
82
+ env->v7m.basepri[env->v7m.secure] = val & 0xff;
83
break;
84
case 18: /* BASEPRI_MAX */
85
val &= 0xff;
86
- if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
87
- env->v7m.basepri = val;
88
+ if (val != 0 && (val < env->v7m.basepri[env->v7m.secure]
89
+ || env->v7m.basepri[env->v7m.secure] == 0)) {
90
+ env->v7m.basepri[env->v7m.secure] = val;
91
+ }
92
break;
93
case 19: /* FAULTMASK */
94
env->v7m.faultmask = val & 1;
95
diff --git a/target/arm/machine.c b/target/arm/machine.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/arm/machine.c
98
+++ b/target/arm/machine.c
99
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
100
.needed = m_needed,
101
.fields = (VMStateField[]) {
102
VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
103
- VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
104
+ VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
105
VMSTATE_UINT32(env.v7m.control, ARMCPU),
106
VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
107
VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
108
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
109
.needed = m_security_needed,
110
.fields = (VMStateField[]) {
111
VMSTATE_UINT32(env.v7m.secure, ARMCPU),
112
+ VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
113
VMSTATE_END_OF_LIST()
114
}
115
};
116
--
117
2.7.4
118
119
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/31] target/arm: Make PRIMASK register banked for v8M
Deleted patch
1
Make the PRIMASK register banked if v8M security extensions are enabled.
2
1
3
Note that we do not yet implement the functionality of the new
4
AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to
5
be restricted).
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 1503414539-28762-8-git-send-email-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 2 +-
12
hw/intc/armv7m_nvic.c | 2 +-
13
target/arm/helper.c | 4 ++--
14
target/arm/machine.c | 9 +++++++--
15
4 files changed, 11 insertions(+), 6 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
22
uint32_t bfar; /* BusFault Address */
23
unsigned mpu_ctrl; /* MPU_CTRL */
24
int exception;
25
- uint32_t primask;
26
+ uint32_t primask[2];
27
uint32_t faultmask;
28
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
29
} v7m;
30
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/armv7m_nvic.c
33
+++ b/hw/intc/armv7m_nvic.c
34
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
35
36
if (env->v7m.faultmask) {
37
running = -1;
38
- } else if (env->v7m.primask) {
39
+ } else if (env->v7m.primask[env->v7m.secure]) {
40
running = 0;
41
} else if (env->v7m.basepri[env->v7m.secure] > 0) {
42
running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/helper.c
46
+++ b/target/arm/helper.c
47
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
48
return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?
49
env->regs[13] : env->v7m.other_sp;
50
case 16: /* PRIMASK */
51
- return env->v7m.primask;
52
+ return env->v7m.primask[env->v7m.secure];
53
case 17: /* BASEPRI */
54
case 18: /* BASEPRI_MAX */
55
return env->v7m.basepri[env->v7m.secure];
56
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
57
}
58
break;
59
case 16: /* PRIMASK */
60
- env->v7m.primask = val & 1;
61
+ env->v7m.primask[env->v7m.secure] = val & 1;
62
break;
63
case 17: /* BASEPRI */
64
env->v7m.basepri[env->v7m.secure] = val & 0xff;
65
diff --git a/target/arm/machine.c b/target/arm/machine.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/machine.c
68
+++ b/target/arm/machine.c
69
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = {
70
.minimum_version_id = 1,
71
.fields = (VMStateField[]) {
72
VMSTATE_UINT32(env.v7m.faultmask, ARMCPU),
73
- VMSTATE_UINT32(env.v7m.primask, ARMCPU),
74
+ VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU),
75
VMSTATE_END_OF_LIST()
76
}
77
};
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
79
.fields = (VMStateField[]) {
80
VMSTATE_UINT32(env.v7m.secure, ARMCPU),
81
VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
82
+ VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
83
VMSTATE_END_OF_LIST()
84
}
85
};
86
@@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
87
* differences are that the T bit is not in the same place, the
88
* primask/faultmask info may be in the CPSR I and F bits, and
89
* we do not want the mode bits.
90
+ * We know that this cleanup happened before v8M, so there
91
+ * is no complication with banked primask/faultmask.
92
*/
93
uint32_t newval = val;
94
95
+ assert(!arm_feature(env, ARM_FEATURE_M_SECURITY));
96
+
97
newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE);
98
if (val & CPSR_T) {
99
newval |= XPSR_T;
100
@@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
101
env->v7m.faultmask = 1;
102
}
103
if (val & CPSR_I) {
104
- env->v7m.primask = 1;
105
+ env->v7m.primask[M_REG_NS] = 1;
106
}
107
val = newval;
108
}
109
--
110
2.7.4
111
112
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/31] target/arm: Make FAULTMASK register banked for v8M
Deleted patch
1
Make the FAULTMASK register banked if v8M security extensions are enabled.
2
1
3
Note that we do not yet implement the functionality of the new
4
AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to
5
be restricted).
6
7
This patch includes the code to determine for v8M which copy
8
of FAULTMASK should be updated on exception exit; further
9
changes will be required to the exception exit code in general
10
to support v8M, so this is just a small piece of that.
11
12
The v8M ARM ARM introduces a notation where individual paragraphs
13
are labelled with R (for rule) or I (for information) followed
14
by a random group of subscript letters. In comments where we want
15
to refer to a particular part of the manual we use this convention,
16
which should be more stable across document revisions than using
17
section or page numbers.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 1503414539-28762-9-git-send-email-peter.maydell@linaro.org
22
---
23
target/arm/cpu.h | 14 ++++++++++++--
24
hw/intc/armv7m_nvic.c | 9 ++++++++-
25
target/arm/helper.c | 20 ++++++++++++++++----
26
target/arm/machine.c | 5 +++--
27
4 files changed, 39 insertions(+), 9 deletions(-)
28
29
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu.h
32
+++ b/target/arm/cpu.h
33
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
34
unsigned mpu_ctrl; /* MPU_CTRL */
35
int exception;
36
uint32_t primask[2];
37
- uint32_t faultmask;
38
+ uint32_t faultmask[2];
39
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
40
} v7m;
41
42
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
43
* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
44
*/
45
int armv7m_nvic_complete_irq(void *opaque, int irq);
46
+/**
47
+ * armv7m_nvic_raw_execution_priority: return the raw execution priority
48
+ * @opaque: the NVIC
49
+ *
50
+ * Returns: the raw execution priority as defined by the v8M architecture.
51
+ * This is the execution priority minus the effects of AIRCR.PRIS,
52
+ * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
53
+ * (v8M ARM ARM I_PKLD.)
54
+ */
55
+int armv7m_nvic_raw_execution_priority(void *opaque);
56
57
/* Interface for defining coprocessor registers.
58
* Registers are defined in tables of arm_cp_reginfo structs
59
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
60
* we're in a HardFault or NMI handler.
61
*/
62
if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
63
- || env->v7m.faultmask) {
64
+ || env->v7m.faultmask[env->v7m.secure]) {
65
mmu_idx = ARMMMUIdx_MNegPri;
66
}
67
68
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/intc/armv7m_nvic.c
71
+++ b/hw/intc/armv7m_nvic.c
72
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
73
CPUARMState *env = &s->cpu->env;
74
int running;
75
76
- if (env->v7m.faultmask) {
77
+ if (env->v7m.faultmask[env->v7m.secure]) {
78
running = -1;
79
} else if (env->v7m.primask[env->v7m.secure]) {
80
running = 0;
81
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_can_take_pending_exception(void *opaque)
82
return nvic_exec_prio(s) > nvic_pending_prio(s);
83
}
84
85
+int armv7m_nvic_raw_execution_priority(void *opaque)
86
+{
87
+ NVICState *s = opaque;
88
+
89
+ return s->exception_prio;
90
+}
91
+
92
/* caller must call nvic_irq_update() after this */
93
static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
94
{
95
diff --git a/target/arm/helper.c b/target/arm/helper.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/arm/helper.c
98
+++ b/target/arm/helper.c
99
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
100
}
101
102
if (env->v7m.exception != ARMV7M_EXCP_NMI) {
103
- /* Auto-clear FAULTMASK on return from other than NMI */
104
- env->v7m.faultmask = 0;
105
+ /* Auto-clear FAULTMASK on return from other than NMI.
106
+ * If the security extension is implemented then this only
107
+ * happens if the raw execution priority is >= 0; the
108
+ * value of the ES bit in the exception return value indicates
109
+ * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
110
+ */
111
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
112
+ int es = type & 1;
113
+ if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
114
+ env->v7m.faultmask[es] = 0;
115
+ }
116
+ } else {
117
+ env->v7m.faultmask[M_REG_NS] = 0;
118
+ }
119
}
120
121
switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {
122
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
123
case 18: /* BASEPRI_MAX */
124
return env->v7m.basepri[env->v7m.secure];
125
case 19: /* FAULTMASK */
126
- return env->v7m.faultmask;
127
+ return env->v7m.faultmask[env->v7m.secure];
128
default:
129
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special"
130
" register %d\n", reg);
131
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
132
}
133
break;
134
case 19: /* FAULTMASK */
135
- env->v7m.faultmask = val & 1;
136
+ env->v7m.faultmask[env->v7m.secure] = val & 1;
137
break;
138
case 20: /* CONTROL */
139
/* Writing to the SPSEL bit only has an effect if we are in
140
diff --git a/target/arm/machine.c b/target/arm/machine.c
141
index XXXXXXX..XXXXXXX 100644
142
--- a/target/arm/machine.c
143
+++ b/target/arm/machine.c
144
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_faultmask_primask = {
145
.version_id = 1,
146
.minimum_version_id = 1,
147
.fields = (VMStateField[]) {
148
- VMSTATE_UINT32(env.v7m.faultmask, ARMCPU),
149
+ VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU),
150
VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU),
151
VMSTATE_END_OF_LIST()
152
}
153
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
154
VMSTATE_UINT32(env.v7m.secure, ARMCPU),
155
VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
156
VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
157
+ VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
158
VMSTATE_END_OF_LIST()
159
}
160
};
161
@@ -XXX,XX +XXX,XX @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
162
* transferred using the vmstate_m_faultmask_primask subsection.
163
*/
164
if (val & CPSR_F) {
165
- env->v7m.faultmask = 1;
166
+ env->v7m.faultmask[M_REG_NS] = 1;
167
}
168
if (val & CPSR_I) {
169
env->v7m.primask[M_REG_NS] = 1;
170
--
171
2.7.4
172
173
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/31] target/arm: Make CONTROL register banked for v8M
Deleted patch
1
Make the CONTROL register banked if v8M security extensions are enabled.
2
1
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1503414539-28762-10-git-send-email-peter.maydell@linaro.org
6
---
7
target/arm/cpu.h | 5 +++--
8
target/arm/helper.c | 21 +++++++++++----------
9
target/arm/machine.c | 3 ++-
10
target/arm/translate.c | 2 +-
11
4 files changed, 17 insertions(+), 14 deletions(-)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
18
uint32_t other_sp;
19
uint32_t vecbase;
20
uint32_t basepri[2];
21
- uint32_t control;
22
+ uint32_t control[2];
23
uint32_t ccr; /* Configuration and Control */
24
uint32_t cfsr; /* Configurable Fault Status */
25
uint32_t hfsr; /* HardFault Status */
26
@@ -XXX,XX +XXX,XX @@ static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
27
static inline int arm_current_el(CPUARMState *env)
28
{
29
if (arm_feature(env, ARM_FEATURE_M)) {
30
- return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1);
31
+ return arm_v7m_is_handler_mode(env) ||
32
+ !(env->v7m.control[env->v7m.secure] & 1);
33
}
34
35
if (is_a64(env)) {
36
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/helper.c
39
+++ b/target/arm/helper.c
40
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_pop(CPUARMState *env)
41
static void switch_v7m_sp(CPUARMState *env, bool new_spsel)
42
{
43
uint32_t tmp;
44
- bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK;
45
+ uint32_t old_control = env->v7m.control[env->v7m.secure];
46
+ bool old_spsel = old_control & R_V7M_CONTROL_SPSEL_MASK;
47
48
if (old_spsel != new_spsel) {
49
tmp = env->v7m.other_sp;
50
env->v7m.other_sp = env->regs[13];
51
env->regs[13] = tmp;
52
53
- env->v7m.control = deposit32(env->v7m.control,
54
+ env->v7m.control[env->v7m.secure] = deposit32(old_control,
55
R_V7M_CONTROL_SPSEL_SHIFT,
56
R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);
57
}
58
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
59
}
60
61
lr = 0xfffffff1;
62
- if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
63
+ if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
64
lr |= 4;
65
}
66
if (!arm_v7m_is_handler_mode(env)) {
67
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
68
return xpsr_read(env) & mask;
69
break;
70
case 20: /* CONTROL */
71
- return env->v7m.control;
72
+ return env->v7m.control[env->v7m.secure];
73
}
74
75
if (el == 0) {
76
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
77
78
switch (reg) {
79
case 8: /* MSP */
80
- return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?
81
+ return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
82
env->v7m.other_sp : env->regs[13];
83
case 9: /* PSP */
84
- return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ?
85
+ return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
86
env->regs[13] : env->v7m.other_sp;
87
case 16: /* PRIMASK */
88
return env->v7m.primask[env->v7m.secure];
89
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
90
}
91
break;
92
case 8: /* MSP */
93
- if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
94
+ if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
95
env->v7m.other_sp = val;
96
} else {
97
env->regs[13] = val;
98
}
99
break;
100
case 9: /* PSP */
101
- if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
102
+ if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
103
env->regs[13] = val;
104
} else {
105
env->v7m.other_sp = val;
106
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
107
if (!arm_v7m_is_handler_mode(env)) {
108
switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
109
}
110
- env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;
111
- env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK;
112
+ env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
113
+ env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
114
break;
115
default:
116
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
117
diff --git a/target/arm/machine.c b/target/arm/machine.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/arm/machine.c
120
+++ b/target/arm/machine.c
121
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
122
.fields = (VMStateField[]) {
123
VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
124
VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
125
- VMSTATE_UINT32(env.v7m.control, ARMCPU),
126
+ VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
127
VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
128
VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
129
VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
130
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
131
VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
132
VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
133
VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
134
+ VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),
135
VMSTATE_END_OF_LIST()
136
}
137
};
138
diff --git a/target/arm/translate.c b/target/arm/translate.c
139
index XXXXXXX..XXXXXXX 100644
140
--- a/target/arm/translate.c
141
+++ b/target/arm/translate.c
142
@@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
143
if (xpsr & XPSR_EXCP) {
144
mode = "handler";
145
} else {
146
- if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) {
147
+ if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
148
mode = "unpriv-thread";
149
} else {
150
mode = "priv-thread";
151
--
152
2.7.4
153
154
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/31] nvic: Add NS alias SCS region
Deleted patch
1
For v8M the range 0xe002e000..0xe002efff is an alias region which
2
for secure accesses behaves like a NonSecure access to the main
3
SCS region. (For nonsecure accesses including when the security
4
extension is not implemented, it is RAZ/WI.)
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1503414539-28762-11-git-send-email-peter.maydell@linaro.org
8
---
9
include/hw/intc/armv7m_nvic.h | 1 +
10
hw/intc/armv7m_nvic.c | 66 ++++++++++++++++++++++++++++++++++++++++++-
11
2 files changed, 66 insertions(+), 1 deletion(-)
12
13
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/armv7m_nvic.h
16
+++ b/include/hw/intc/armv7m_nvic.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
18
int exception_prio; /* group prio of the highest prio active exception */
19
20
MemoryRegion sysregmem;
21
+ MemoryRegion sysreg_ns_mem;
22
MemoryRegion container;
23
24
uint32_t num_irq;
25
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/intc/armv7m_nvic.c
28
+++ b/hw/intc/armv7m_nvic.c
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_sysreg_ops = {
30
.endianness = DEVICE_NATIVE_ENDIAN,
31
};
32
33
+static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
34
+ uint64_t value, unsigned size,
35
+ MemTxAttrs attrs)
36
+{
37
+ if (attrs.secure) {
38
+ /* S accesses to the alias act like NS accesses to the real region */
39
+ attrs.secure = 0;
40
+ return nvic_sysreg_write(opaque, addr, value, size, attrs);
41
+ } else {
42
+ /* NS attrs are RAZ/WI for privileged, and BusFault for user */
43
+ if (attrs.user) {
44
+ return MEMTX_ERROR;
45
+ }
46
+ return MEMTX_OK;
47
+ }
48
+}
49
+
50
+static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
51
+ uint64_t *data, unsigned size,
52
+ MemTxAttrs attrs)
53
+{
54
+ if (attrs.secure) {
55
+ /* S accesses to the alias act like NS accesses to the real region */
56
+ attrs.secure = 0;
57
+ return nvic_sysreg_read(opaque, addr, data, size, attrs);
58
+ } else {
59
+ /* NS attrs are RAZ/WI for privileged, and BusFault for user */
60
+ if (attrs.user) {
61
+ return MEMTX_ERROR;
62
+ }
63
+ *data = 0;
64
+ return MEMTX_OK;
65
+ }
66
+}
67
+
68
+static const MemoryRegionOps nvic_sysreg_ns_ops = {
69
+ .read_with_attrs = nvic_sysreg_ns_read,
70
+ .write_with_attrs = nvic_sysreg_ns_write,
71
+ .endianness = DEVICE_NATIVE_ENDIAN,
72
+};
73
+
74
static int nvic_post_load(void *opaque, int version_id)
75
{
76
NVICState *s = opaque;
77
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
78
NVICState *s = NVIC(dev);
79
SysBusDevice *systick_sbd;
80
Error *err = NULL;
81
+ int regionlen;
82
83
s->cpu = ARM_CPU(qemu_get_cpu(0));
84
assert(s->cpu);
85
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
86
* 0xd00..0xd3c - SCS registers
87
* 0xd40..0xeff - Reserved or Not implemented
88
* 0xf00 - STIR
89
+ *
90
+ * Some registers within this space are banked between security states.
91
+ * In v8M there is a second range 0xe002e000..0xe002efff which is the
92
+ * NonSecure alias SCS; secure accesses to this behave like NS accesses
93
+ * to the main SCS range, and non-secure accesses (including when
94
+ * the security extension is not implemented) are RAZ/WI.
95
+ * Note that both the main SCS range and the alias range are defined
96
+ * to be exempt from memory attribution (R_BLJT) and so the memory
97
+ * transaction attribute always matches the current CPU security
98
+ * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
99
+ * wrappers we change attrs.secure to indicate the NS access; so
100
+ * generally code determining which banked register to use should
101
+ * use attrs.secure; code determining actual behaviour of the system
102
+ * should use env->v7m.secure.
103
*/
104
- memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000);
105
+ regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000;
106
+ memory_region_init(&s->container, OBJECT(s), "nvic", regionlen);
107
/* The system register region goes at the bottom of the priority
108
* stack as it covers the whole page.
109
*/
110
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
111
sysbus_mmio_get_region(systick_sbd, 0),
112
1);
113
114
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
115
+ memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
116
+ &nvic_sysreg_ns_ops, s,
117
+ "nvic_sysregs_ns", 0x1000);
118
+ memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem);
119
+ }
120
+
121
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
122
}
123
124
--
125
2.7.4
126
127
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/31] target/arm: Make VTOR register banked for v8M
Deleted patch
1
Make the VTOR register banked if v8M security extensions are enabled.
2
1
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org
6
---
7
target/arm/cpu.h | 2 +-
8
hw/intc/armv7m_nvic.c | 13 +++++++------
9
target/arm/helper.c | 2 +-
10
target/arm/machine.c | 3 ++-
11
4 files changed, 11 insertions(+), 9 deletions(-)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
18
19
struct {
20
uint32_t other_sp;
21
- uint32_t vecbase;
22
+ uint32_t vecbase[2];
23
uint32_t basepri[2];
24
uint32_t control[2];
25
uint32_t ccr; /* Configuration and Control */
26
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/intc/armv7m_nvic.c
29
+++ b/hw/intc/armv7m_nvic.c
30
@@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level)
31
}
32
}
33
34
-static uint32_t nvic_readl(NVICState *s, uint32_t offset)
35
+static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
36
{
37
ARMCPU *cpu = s->cpu;
38
uint32_t val;
39
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
40
/* ISRPREEMPT not implemented */
41
return val;
42
case 0xd08: /* Vector Table Offset. */
43
- return cpu->env.v7m.vecbase;
44
+ return cpu->env.v7m.vecbase[attrs.secure];
45
case 0xd0c: /* Application Interrupt/Reset Control. */
46
return 0xfa050000 | (s->prigroup << 8);
47
case 0xd10: /* System Control. */
48
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
49
}
50
}
51
52
-static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
53
+static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
54
+ MemTxAttrs attrs)
55
{
56
ARMCPU *cpu = s->cpu;
57
58
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
59
}
60
break;
61
case 0xd08: /* Vector Table Offset. */
62
- cpu->env.v7m.vecbase = value & 0xffffff80;
63
+ cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;
64
break;
65
case 0xd0c: /* Application Interrupt/Reset Control. */
66
if ((value >> 16) == 0x05fa) {
67
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
68
break;
69
default:
70
if (size == 4) {
71
- val = nvic_readl(s, offset);
72
+ val = nvic_readl(s, offset, attrs);
73
} else {
74
qemu_log_mask(LOG_GUEST_ERROR,
75
"NVIC: Bad read of size %d at offset 0x%x\n",
76
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
77
return MEMTX_OK;
78
}
79
if (size == 4) {
80
- nvic_writel(s, offset, value);
81
+ nvic_writel(s, offset, value, attrs);
82
return MEMTX_OK;
83
}
84
qemu_log_mask(LOG_GUEST_ERROR,
85
diff --git a/target/arm/helper.c b/target/arm/helper.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/target/arm/helper.c
88
+++ b/target/arm/helper.c
89
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu)
90
CPUState *cs = CPU(cpu);
91
CPUARMState *env = &cpu->env;
92
MemTxResult result;
93
- hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4;
94
+ hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4;
95
uint32_t addr;
96
97
addr = address_space_ldl(cs->as, vec,
98
diff --git a/target/arm/machine.c b/target/arm/machine.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/machine.c
101
+++ b/target/arm/machine.c
102
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
103
.minimum_version_id = 4,
104
.needed = m_needed,
105
.fields = (VMStateField[]) {
106
- VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
107
+ VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),
108
VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
109
VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
110
VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
111
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
112
VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
113
VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
114
VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),
115
+ VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
116
VMSTATE_END_OF_LIST()
117
}
118
};
119
--
120
2.7.4
121
122
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/31] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
Deleted patch
1
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security
2
extensions are enabled.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1503414539-28762-13-git-send-email-peter.maydell@linaro.org
7
---
8
target/arm/cpu.h | 4 ++--
9
hw/intc/armv7m_nvic.c | 8 ++++----
10
target/arm/cpu.c | 6 ++++--
11
target/arm/machine.c | 6 ++++--
12
4 files changed, 14 insertions(+), 10 deletions(-)
13
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
19
*/
20
uint32_t *rbar;
21
uint32_t *rlar;
22
- uint32_t mair0;
23
- uint32_t mair1;
24
+ uint32_t mair0[2];
25
+ uint32_t mair1[2];
26
} pmsav8;
27
28
void *nvic;
29
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/intc/armv7m_nvic.c
32
+++ b/hw/intc/armv7m_nvic.c
33
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
34
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
35
goto bad_offset;
36
}
37
- return cpu->env.pmsav8.mair0;
38
+ return cpu->env.pmsav8.mair0[attrs.secure];
39
case 0xdc4: /* MPU_MAIR1 */
40
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
41
goto bad_offset;
42
}
43
- return cpu->env.pmsav8.mair1;
44
+ return cpu->env.pmsav8.mair1[attrs.secure];
45
default:
46
bad_offset:
47
qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
48
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
49
}
50
if (cpu->pmsav7_dregion) {
51
/* Register is RES0 if no MPU regions are implemented */
52
- cpu->env.pmsav8.mair0 = value;
53
+ cpu->env.pmsav8.mair0[attrs.secure] = value;
54
}
55
/* We don't need to do anything else because memory attributes
56
* only affect cacheability, and we don't implement caching.
57
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
58
}
59
if (cpu->pmsav7_dregion) {
60
/* Register is RES0 if no MPU regions are implemented */
61
- cpu->env.pmsav8.mair1 = value;
62
+ cpu->env.pmsav8.mair1[attrs.secure] = value;
63
}
64
/* We don't need to do anything else because memory attributes
65
* only affect cacheability, and we don't implement caching.
66
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/cpu.c
69
+++ b/target/arm/cpu.c
70
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
71
}
72
}
73
env->pmsav7.rnr = 0;
74
- env->pmsav8.mair0 = 0;
75
- env->pmsav8.mair1 = 0;
76
+ env->pmsav8.mair0[M_REG_NS] = 0;
77
+ env->pmsav8.mair0[M_REG_S] = 0;
78
+ env->pmsav8.mair1[M_REG_NS] = 0;
79
+ env->pmsav8.mair1[M_REG_S] = 0;
80
}
81
82
set_flush_to_zero(1, &env->vfp.standard_fp_status);
83
diff --git a/target/arm/machine.c b/target/arm/machine.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/machine.c
86
+++ b/target/arm/machine.c
87
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
88
vmstate_info_uint32, uint32_t),
89
VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0,
90
vmstate_info_uint32, uint32_t),
91
- VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU),
92
- VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU),
93
+ VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
94
+ VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
95
VMSTATE_END_OF_LIST()
96
}
97
};
98
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
99
VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
100
VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),
101
VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
102
+ VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),
103
+ VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),
104
VMSTATE_END_OF_LIST()
105
}
106
};
107
--
108
2.7.4
109
110
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/31] target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Deleted patch
1
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security
2
extensions are enabled.
3
1
4
We can freely add more items to vmstate_m_security without
5
breaking migration compatibility, because no CPU currently
6
has the ARM_FEATURE_M_SECURITY bit enabled and so this
7
subsection is not yet used by anything.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
12
---
13
target/arm/cpu.h | 4 ++--
14
hw/intc/armv7m_nvic.c | 8 ++++----
15
target/arm/cpu.c | 26 ++++++++++++++++++++------
16
target/arm/helper.c | 11 ++++++-----
17
target/arm/machine.c | 12 ++++++++----
18
5 files changed, 40 insertions(+), 21 deletions(-)
19
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
23
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
25
* pmsav7.rnr (region number register)
26
* pmsav7_dregion (number of configured regions)
27
*/
28
- uint32_t *rbar;
29
- uint32_t *rlar;
30
+ uint32_t *rbar[2];
31
+ uint32_t *rlar[2];
32
uint32_t mair0[2];
33
uint32_t mair1[2];
34
} pmsav8;
35
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/intc/armv7m_nvic.c
38
+++ b/hw/intc/armv7m_nvic.c
39
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
40
if (region >= cpu->pmsav7_dregion) {
41
return 0;
42
}
43
- return cpu->env.pmsav8.rbar[region];
44
+ return cpu->env.pmsav8.rbar[attrs.secure][region];
45
}
46
47
if (region >= cpu->pmsav7_dregion) {
48
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
49
if (region >= cpu->pmsav7_dregion) {
50
return 0;
51
}
52
- return cpu->env.pmsav8.rlar[region];
53
+ return cpu->env.pmsav8.rlar[attrs.secure][region];
54
}
55
56
if (region >= cpu->pmsav7_dregion) {
57
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
58
if (region >= cpu->pmsav7_dregion) {
59
return;
60
}
61
- cpu->env.pmsav8.rbar[region] = value;
62
+ cpu->env.pmsav8.rbar[attrs.secure][region] = value;
63
tlb_flush(CPU(cpu));
64
return;
65
}
66
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
67
if (region >= cpu->pmsav7_dregion) {
68
return;
69
}
70
- cpu->env.pmsav8.rlar[region] = value;
71
+ cpu->env.pmsav8.rlar[attrs.secure][region] = value;
72
tlb_flush(CPU(cpu));
73
return;
74
}
75
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/cpu.c
78
+++ b/target/arm/cpu.c
79
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
80
if (arm_feature(env, ARM_FEATURE_PMSA)) {
81
if (cpu->pmsav7_dregion > 0) {
82
if (arm_feature(env, ARM_FEATURE_V8)) {
83
- memset(env->pmsav8.rbar, 0,
84
- sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion);
85
- memset(env->pmsav8.rlar, 0,
86
- sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion);
87
+ memset(env->pmsav8.rbar[M_REG_NS], 0,
88
+ sizeof(*env->pmsav8.rbar[M_REG_NS])
89
+ * cpu->pmsav7_dregion);
90
+ memset(env->pmsav8.rlar[M_REG_NS], 0,
91
+ sizeof(*env->pmsav8.rlar[M_REG_NS])
92
+ * cpu->pmsav7_dregion);
93
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
94
+ memset(env->pmsav8.rbar[M_REG_S], 0,
95
+ sizeof(*env->pmsav8.rbar[M_REG_S])
96
+ * cpu->pmsav7_dregion);
97
+ memset(env->pmsav8.rlar[M_REG_S], 0,
98
+ sizeof(*env->pmsav8.rlar[M_REG_S])
99
+ * cpu->pmsav7_dregion);
100
+ }
101
} else if (arm_feature(env, ARM_FEATURE_V7)) {
102
memset(env->pmsav7.drbar, 0,
103
sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
104
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
105
if (nr) {
106
if (arm_feature(env, ARM_FEATURE_V8)) {
107
/* PMSAv8 */
108
- env->pmsav8.rbar = g_new0(uint32_t, nr);
109
- env->pmsav8.rlar = g_new0(uint32_t, nr);
110
+ env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
111
+ env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
112
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
113
+ env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
114
+ env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
115
+ }
116
} else {
117
env->pmsav7.drbar = g_new0(uint32_t, nr);
118
env->pmsav7.drsr = g_new0(uint32_t, nr);
119
diff --git a/target/arm/helper.c b/target/arm/helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/helper.c
122
+++ b/target/arm/helper.c
123
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
124
{
125
ARMCPU *cpu = arm_env_get_cpu(env);
126
bool is_user = regime_is_user(env, mmu_idx);
127
+ uint32_t secure = regime_is_secure(env, mmu_idx);
128
int n;
129
int matchregion = -1;
130
bool hit = false;
131
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
132
* with bits [4:0] all zeroes, but the limit address is bits
133
* [31:5] from the register with bits [4:0] all ones.
134
*/
135
- uint32_t base = env->pmsav8.rbar[n] & ~0x1f;
136
- uint32_t limit = env->pmsav8.rlar[n] | 0x1f;
137
+ uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
138
+ uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
139
140
- if (!(env->pmsav8.rlar[n] & 0x1)) {
141
+ if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
142
/* Region disabled */
143
continue;
144
}
145
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
146
/* hit using the background region */
147
get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
148
} else {
149
- uint32_t ap = extract32(env->pmsav8.rbar[matchregion], 1, 2);
150
- uint32_t xn = extract32(env->pmsav8.rbar[matchregion], 0, 1);
151
+ uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
152
+ uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
153
154
if (m_is_system_region(env, address)) {
155
/* System space is always execute never */
156
diff --git a/target/arm/machine.c b/target/arm/machine.c
157
index XXXXXXX..XXXXXXX 100644
158
--- a/target/arm/machine.c
159
+++ b/target/arm/machine.c
160
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
161
.minimum_version_id = 1,
162
.needed = pmsav8_needed,
163
.fields = (VMStateField[]) {
164
- VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0,
165
- vmstate_info_uint32, uint32_t),
166
- VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0,
167
- vmstate_info_uint32, uint32_t),
168
+ VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion,
169
+ 0, vmstate_info_uint32, uint32_t),
170
+ VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion,
171
+ 0, vmstate_info_uint32, uint32_t),
172
VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
173
VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
174
VMSTATE_END_OF_LIST()
175
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
176
VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
177
VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),
178
VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),
179
+ VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion,
180
+ 0, vmstate_info_uint32, uint32_t),
181
+ VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion,
182
+ 0, vmstate_info_uint32, uint32_t),
183
VMSTATE_END_OF_LIST()
184
}
185
};
186
--
187
2.7.4
188
189
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/31] target/arm: Make MPU_RNR register banked for v8M
Deleted patch
1
Make the MPU_RNR register banked if v8M security extensions are
2
enabled.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1503414539-28762-15-git-send-email-peter.maydell@linaro.org
7
---
8
target/arm/cpu.h | 2 +-
9
hw/intc/armv7m_nvic.c | 18 +++++++++---------
10
target/arm/cpu.c | 3 ++-
11
target/arm/helper.c | 6 +++---
12
target/arm/machine.c | 13 +++++++++++--
13
5 files changed, 26 insertions(+), 16 deletions(-)
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
20
uint32_t *drbar;
21
uint32_t *drsr;
22
uint32_t *dracr;
23
- uint32_t rnr;
24
+ uint32_t rnr[2];
25
} pmsav7;
26
27
/* PMSAv8 MPU */
28
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/intc/armv7m_nvic.c
31
+++ b/hw/intc/armv7m_nvic.c
32
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
33
case 0xd94: /* MPU_CTRL */
34
return cpu->env.v7m.mpu_ctrl;
35
case 0xd98: /* MPU_RNR */
36
- return cpu->env.pmsav7.rnr;
37
+ return cpu->env.pmsav7.rnr[attrs.secure];
38
case 0xd9c: /* MPU_RBAR */
39
case 0xda4: /* MPU_RBAR_A1 */
40
case 0xdac: /* MPU_RBAR_A2 */
41
case 0xdb4: /* MPU_RBAR_A3 */
42
{
43
- int region = cpu->env.pmsav7.rnr;
44
+ int region = cpu->env.pmsav7.rnr[attrs.secure];
45
46
if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
47
/* PMSAv8M handling of the aliases is different from v7M:
48
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
49
case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
50
case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
51
{
52
- int region = cpu->env.pmsav7.rnr;
53
+ int region = cpu->env.pmsav7.rnr[attrs.secure];
54
55
if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
56
/* PMSAv8M handling of the aliases is different from v7M:
57
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
58
PRIu32 "/%" PRIu32 "\n",
59
value, cpu->pmsav7_dregion);
60
} else {
61
- cpu->env.pmsav7.rnr = value;
62
+ cpu->env.pmsav7.rnr[attrs.secure] = value;
63
}
64
break;
65
case 0xd9c: /* MPU_RBAR */
66
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
67
*/
68
int aliasno = (offset - 0xd9c) / 8; /* 0..3 */
69
70
- region = cpu->env.pmsav7.rnr;
71
+ region = cpu->env.pmsav7.rnr[attrs.secure];
72
if (aliasno) {
73
region = deposit32(region, 0, 2, aliasno);
74
}
75
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
76
region, cpu->pmsav7_dregion);
77
return;
78
}
79
- cpu->env.pmsav7.rnr = region;
80
+ cpu->env.pmsav7.rnr[attrs.secure] = region;
81
} else {
82
- region = cpu->env.pmsav7.rnr;
83
+ region = cpu->env.pmsav7.rnr[attrs.secure];
84
}
85
86
if (region >= cpu->pmsav7_dregion) {
87
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
88
case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
89
case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
90
{
91
- int region = cpu->env.pmsav7.rnr;
92
+ int region = cpu->env.pmsav7.rnr[attrs.secure];
93
94
if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
95
/* PMSAv8M handling of the aliases is different from v7M:
96
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
97
*/
98
int aliasno = (offset - 0xd9c) / 8; /* 0..3 */
99
100
- region = cpu->env.pmsav7.rnr;
101
+ region = cpu->env.pmsav7.rnr[attrs.secure];
102
if (aliasno) {
103
region = deposit32(region, 0, 2, aliasno);
104
}
105
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/target/arm/cpu.c
108
+++ b/target/arm/cpu.c
109
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
110
sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
111
}
112
}
113
- env->pmsav7.rnr = 0;
114
+ env->pmsav7.rnr[M_REG_NS] = 0;
115
+ env->pmsav7.rnr[M_REG_S] = 0;
116
env->pmsav8.mair0[M_REG_NS] = 0;
117
env->pmsav8.mair0[M_REG_S] = 0;
118
env->pmsav8.mair1[M_REG_NS] = 0;
119
diff --git a/target/arm/helper.c b/target/arm/helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/helper.c
122
+++ b/target/arm/helper.c
123
@@ -XXX,XX +XXX,XX @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
124
return 0;
125
}
126
127
- u32p += env->pmsav7.rnr;
128
+ u32p += env->pmsav7.rnr[M_REG_NS];
129
return *u32p;
130
}
131
132
@@ -XXX,XX +XXX,XX @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
133
return;
134
}
135
136
- u32p += env->pmsav7.rnr;
137
+ u32p += env->pmsav7.rnr[M_REG_NS];
138
tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
139
*u32p = value;
140
}
141
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
142
.resetfn = arm_cp_reset_ignore },
143
{ .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
144
.access = PL1_RW,
145
- .fieldoffset = offsetof(CPUARMState, pmsav7.rnr),
146
+ .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
147
.writefn = pmsav7_rgnr_write,
148
.resetfn = arm_cp_reset_ignore },
149
REGINFO_SENTINEL
150
diff --git a/target/arm/machine.c b/target/arm/machine.c
151
index XXXXXXX..XXXXXXX 100644
152
--- a/target/arm/machine.c
153
+++ b/target/arm/machine.c
154
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
155
{
156
ARMCPU *cpu = opaque;
157
158
- return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion;
159
+ return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion;
160
}
161
162
static const VMStateDescription vmstate_pmsav7 = {
163
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav7_rnr = {
164
.minimum_version_id = 1,
165
.needed = pmsav7_rnr_needed,
166
.fields = (VMStateField[]) {
167
- VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU),
168
+ VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU),
169
VMSTATE_END_OF_LIST()
170
}
171
};
172
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
173
}
174
};
175
176
+static bool s_rnr_vmstate_validate(void *opaque, int version_id)
177
+{
178
+ ARMCPU *cpu = opaque;
179
+
180
+ return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion;
181
+}
182
+
183
static bool m_security_needed(void *opaque)
184
{
185
ARMCPU *cpu = opaque;
186
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
187
0, vmstate_info_uint32, uint32_t),
188
VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion,
189
0, vmstate_info_uint32, uint32_t),
190
+ VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),
191
+ VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
192
VMSTATE_END_OF_LIST()
193
}
194
};
195
--
196
2.7.4
197
198
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/31] target/arm: Make MPU_CTRL register banked for v8M
Deleted patch
1
Make the MPU_CTRL register banked if v8M security extensions are
2
enabled.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
7
---
8
target/arm/cpu.h | 2 +-
9
hw/intc/armv7m_nvic.c | 9 +++++----
10
target/arm/helper.c | 5 +++--
11
target/arm/machine.c | 3 ++-
12
4 files changed, 11 insertions(+), 8 deletions(-)
13
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
19
uint32_t dfsr; /* Debug Fault Status Register */
20
uint32_t mmfar; /* MemManage Fault Address */
21
uint32_t bfar; /* BusFault Address */
22
- unsigned mpu_ctrl; /* MPU_CTRL */
23
+ unsigned mpu_ctrl[2]; /* MPU_CTRL */
24
int exception;
25
uint32_t primask[2];
26
uint32_t faultmask[2];
27
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/intc/armv7m_nvic.c
30
+++ b/hw/intc/armv7m_nvic.c
31
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
32
return cpu->pmsav7_dregion << 8;
33
break;
34
case 0xd94: /* MPU_CTRL */
35
- return cpu->env.v7m.mpu_ctrl;
36
+ return cpu->env.v7m.mpu_ctrl[attrs.secure];
37
case 0xd98: /* MPU_RNR */
38
return cpu->env.pmsav7.rnr[attrs.secure];
39
case 0xd9c: /* MPU_RBAR */
40
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
41
qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "
42
"UNPREDICTABLE\n");
43
}
44
- cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
45
- R_V7M_MPU_CTRL_HFNMIENA_MASK |
46
- R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
47
+ cpu->env.v7m.mpu_ctrl[attrs.secure]
48
+ = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
49
+ R_V7M_MPU_CTRL_HFNMIENA_MASK |
50
+ R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
51
tlb_flush(CPU(cpu));
52
break;
53
case 0xd98: /* MPU_RNR */
54
diff --git a/target/arm/helper.c b/target/arm/helper.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/helper.c
57
+++ b/target/arm/helper.c
58
@@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env,
59
ARMMMUIdx mmu_idx)
60
{
61
if (arm_feature(env, ARM_FEATURE_M)) {
62
- switch (env->v7m.mpu_ctrl &
63
+ switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
64
(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
65
case R_V7M_MPU_CTRL_ENABLE_MASK:
66
/* Enabled, but not for HardFault and NMI */
67
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu,
68
}
69
70
if (arm_feature(env, ARM_FEATURE_M)) {
71
- return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
72
+ return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
73
+ & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
74
} else {
75
return regime_sctlr(env, mmu_idx) & SCTLR_BR;
76
}
77
diff --git a/target/arm/machine.c b/target/arm/machine.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/machine.c
80
+++ b/target/arm/machine.c
81
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
82
VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
83
VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
84
VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
85
- VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU),
86
+ VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),
87
VMSTATE_INT32(env.v7m.exception, ARMCPU),
88
VMSTATE_END_OF_LIST()
89
},
90
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
91
0, vmstate_info_uint32, uint32_t),
92
VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),
93
VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
94
+ VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
95
VMSTATE_END_OF_LIST()
96
}
97
};
98
--
99
2.7.4
100
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/31] target/arm: Make CCR register banked for v8M
Deleted patch
1
Make the CCR register banked if v8M security extensions are enabled.
2
1
3
This is slightly more complicated than the other "add banking"
4
patches because there is one bit in the register which is not
5
banked. We keep the live data in the NS copy of the register,
6
and adjust it on register reads and writes. (Since we don't
7
currently implement the behaviour that the bit controls, there
8
is nowhere else that needs to care.)
9
10
This patch includes the enforcement of the bits which are newly
11
RES1 in ARMv8M.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org
15
---
16
target/arm/cpu.h | 2 +-
17
hw/intc/armv7m_nvic.c | 33 +++++++++++++++++++++++++++------
18
target/arm/cpu.c | 12 +++++++++---
19
target/arm/helper.c | 5 +++--
20
target/arm/machine.c | 3 ++-
21
5 files changed, 42 insertions(+), 13 deletions(-)
22
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
28
uint32_t vecbase[2];
29
uint32_t basepri[2];
30
uint32_t control[2];
31
- uint32_t ccr; /* Configuration and Control */
32
+ uint32_t ccr[2]; /* Configuration and Control */
33
uint32_t cfsr; /* Configurable Fault Status */
34
uint32_t hfsr; /* HardFault Status */
35
uint32_t dfsr; /* Debug Fault Status Register */
36
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/intc/armv7m_nvic.c
39
+++ b/hw/intc/armv7m_nvic.c
40
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
41
/* TODO: Implement SLEEPONEXIT. */
42
return 0;
43
case 0xd14: /* Configuration Control. */
44
- return cpu->env.v7m.ccr;
45
+ /* The BFHFNMIGN bit is the only non-banked bit; we
46
+ * keep it in the non-secure copy of the register.
47
+ */
48
+ val = cpu->env.v7m.ccr[attrs.secure];
49
+ val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
50
+ return val;
51
case 0xd24: /* System Handler Status. */
52
val = 0;
53
if (s->vectors[ARMV7M_EXCP_MEM].active) {
54
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
55
R_V7M_CCR_USERSETMPEND_MASK |
56
R_V7M_CCR_NONBASETHRDENA_MASK);
57
58
- cpu->env.v7m.ccr = value;
59
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
60
+ /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
61
+ value |= R_V7M_CCR_NONBASETHRDENA_MASK
62
+ | R_V7M_CCR_STKALIGN_MASK;
63
+ }
64
+ if (attrs.secure) {
65
+ /* the BFHFNMIGN bit is not banked; keep that in the NS copy */
66
+ cpu->env.v7m.ccr[M_REG_NS] =
67
+ (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK)
68
+ | (value & R_V7M_CCR_BFHFNMIGN_MASK);
69
+ value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
70
+ }
71
+
72
+ cpu->env.v7m.ccr[attrs.secure] = value;
73
break;
74
case 0xd24: /* System Handler Control. */
75
s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
76
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
77
}
78
}
79
80
-static bool nvic_user_access_ok(NVICState *s, hwaddr offset)
81
+static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs)
82
{
83
/* Return true if unprivileged access to this register is permitted. */
84
switch (offset) {
85
case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */
86
- return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK;
87
+ /* For access via STIR_NS it is the NS CCR.USERSETMPEND that
88
+ * controls access even though the CPU is in Secure state (I_QDKX).
89
+ */
90
+ return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK;
91
default:
92
/* All other user accesses cause a BusFault unconditionally */
93
return false;
94
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
95
unsigned i, startvec, end;
96
uint32_t val;
97
98
- if (attrs.user && !nvic_user_access_ok(s, addr)) {
99
+ if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) {
100
/* Generate BusFault for unprivileged accesses */
101
return MEMTX_ERROR;
102
}
103
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
104
105
trace_nvic_sysreg_write(addr, value, size);
106
107
- if (attrs.user && !nvic_user_access_ok(s, addr)) {
108
+ if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) {
109
/* Generate BusFault for unprivileged accesses */
110
return MEMTX_ERROR;
111
}
112
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/target/arm/cpu.c
115
+++ b/target/arm/cpu.c
116
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
117
env->v7m.secure = true;
118
}
119
120
- /* The reset value of this bit is IMPDEF, but ARM recommends
121
+ /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
122
* that it resets to 1, so QEMU always does that rather than making
123
- * it dependent on CPU model.
124
+ * it dependent on CPU model. In v8M it is RES1.
125
*/
126
- env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
127
+ env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
128
+ env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
129
+ if (arm_feature(env, ARM_FEATURE_V8)) {
130
+ /* in v8M the NONBASETHRDENA bit [0] is RES1 */
131
+ env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
132
+ env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
133
+ }
134
135
/* Unlike A/R profile, M profile defines the reset LR value */
136
env->regs[14] = 0xffffffff;
137
diff --git a/target/arm/helper.c b/target/arm/helper.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/target/arm/helper.c
140
+++ b/target/arm/helper.c
141
@@ -XXX,XX +XXX,XX @@ static void v7m_push_stack(ARMCPU *cpu)
142
uint32_t xpsr = xpsr_read(env);
143
144
/* Align stack pointer if the guest wants that */
145
- if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {
146
+ if ((env->regs[13] & 4) &&
147
+ (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) {
148
env->regs[13] -= 4;
149
xpsr |= XPSR_SPREALIGN;
150
}
151
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
152
/* fall through */
153
case 9: /* Return to Thread using Main stack */
154
if (!rettobase &&
155
- !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) {
156
+ !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MASK)) {
157
ufault = true;
158
}
159
break;
160
diff --git a/target/arm/machine.c b/target/arm/machine.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/arm/machine.c
163
+++ b/target/arm/machine.c
164
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
165
VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),
166
VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
167
VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
168
- VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
169
+ VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU),
170
VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
171
VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
172
VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
173
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
174
VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),
175
VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
176
VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
177
+ VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
178
VMSTATE_END_OF_LIST()
179
}
180
};
181
--
182
2.7.4
183
184
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/31] target/arm: Make MMFAR banked for v8M
Deleted patch
1
Make the MMFAR register banked if v8M security extensions are
2
enabled.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org
7
---
8
target/arm/cpu.h | 2 +-
9
hw/intc/armv7m_nvic.c | 4 ++--
10
target/arm/helper.c | 4 ++--
11
target/arm/machine.c | 3 ++-
12
4 files changed, 7 insertions(+), 6 deletions(-)
13
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
19
uint32_t cfsr; /* Configurable Fault Status */
20
uint32_t hfsr; /* HardFault Status */
21
uint32_t dfsr; /* Debug Fault Status Register */
22
- uint32_t mmfar; /* MemManage Fault Address */
23
+ uint32_t mmfar[2]; /* MemManage Fault Address */
24
uint32_t bfar; /* BusFault Address */
25
unsigned mpu_ctrl[2]; /* MPU_CTRL */
26
int exception;
27
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/intc/armv7m_nvic.c
30
+++ b/hw/intc/armv7m_nvic.c
31
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
32
case 0xd30: /* Debug Fault Status. */
33
return cpu->env.v7m.dfsr;
34
case 0xd34: /* MMFAR MemManage Fault Address */
35
- return cpu->env.v7m.mmfar;
36
+ return cpu->env.v7m.mmfar[attrs.secure];
37
case 0xd38: /* Bus Fault Address. */
38
return cpu->env.v7m.bfar;
39
case 0xd3c: /* Aux Fault Status. */
40
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
41
cpu->env.v7m.dfsr &= ~value; /* W1C */
42
break;
43
case 0xd34: /* Mem Manage Address. */
44
- cpu->env.v7m.mmfar = value;
45
+ cpu->env.v7m.mmfar[attrs.secure] = value;
46
return;
47
case 0xd38: /* Bus Fault Address. */
48
cpu->env.v7m.bfar = value;
49
diff --git a/target/arm/helper.c b/target/arm/helper.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/helper.c
52
+++ b/target/arm/helper.c
53
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
54
case EXCP_DATA_ABORT:
55
env->v7m.cfsr |=
56
(R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);
57
- env->v7m.mmfar = env->exception.vaddress;
58
+ env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress;
59
qemu_log_mask(CPU_LOG_INT,
60
"...with CFSR.DACCVIOL and MMFAR 0x%x\n",
61
- env->v7m.mmfar);
62
+ env->v7m.mmfar[env->v7m.secure]);
63
break;
64
}
65
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
66
diff --git a/target/arm/machine.c b/target/arm/machine.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/machine.c
69
+++ b/target/arm/machine.c
70
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
71
VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
72
VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
73
VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
74
- VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
75
+ VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU),
76
VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
77
VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),
78
VMSTATE_INT32(env.v7m.exception, ARMCPU),
79
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
80
VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
81
VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
82
VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
83
+ VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),
84
VMSTATE_END_OF_LIST()
85
}
86
};
87
--
88
2.7.4
89
90
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/31] target/arm: Make CFSR register banked for v8M
Deleted patch
1
Make the CFSR register banked if v8M security extensions are enabled.
2
1
3
Not all the bits in this register are banked: the BFSR
4
bits [15:8] are shared between S and NS, and we store them
5
in the NS copy of the register.
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 7 ++++++-
12
hw/intc/armv7m_nvic.c | 15 +++++++++++++--
13
target/arm/helper.c | 18 +++++++++---------
14
target/arm/machine.c | 3 ++-
15
4 files changed, 30 insertions(+), 13 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
22
uint32_t basepri[2];
23
uint32_t control[2];
24
uint32_t ccr[2]; /* Configuration and Control */
25
- uint32_t cfsr; /* Configurable Fault Status */
26
+ uint32_t cfsr[2]; /* Configurable Fault Status */
27
uint32_t hfsr; /* HardFault Status */
28
uint32_t dfsr; /* Debug Fault Status Register */
29
uint32_t mmfar[2]; /* MemManage Fault Address */
30
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
31
FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
32
FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
33
34
+/* V7M CFSR bit masks covering all of the subregister bits */
35
+FIELD(V7M_CFSR, MMFSR, 0, 8)
36
+FIELD(V7M_CFSR, BFSR, 8, 8)
37
+FIELD(V7M_CFSR, UFSR, 16, 16)
38
+
39
/* V7M HFSR bits */
40
FIELD(V7M_HFSR, VECTTBL, 1, 1)
41
FIELD(V7M_HFSR, FORCED, 30, 1)
42
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/intc/armv7m_nvic.c
45
+++ b/hw/intc/armv7m_nvic.c
46
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
47
}
48
return val;
49
case 0xd28: /* Configurable Fault Status. */
50
- return cpu->env.v7m.cfsr;
51
+ /* The BFSR bits [15:8] are shared between security states
52
+ * and we store them in the NS copy
53
+ */
54
+ val = cpu->env.v7m.cfsr[attrs.secure];
55
+ val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
56
+ return val;
57
case 0xd2c: /* Hard Fault Status. */
58
return cpu->env.v7m.hfsr;
59
case 0xd30: /* Debug Fault Status. */
60
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
61
nvic_irq_update(s);
62
break;
63
case 0xd28: /* Configurable Fault Status. */
64
- cpu->env.v7m.cfsr &= ~value; /* W1C */
65
+ cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */
66
+ if (attrs.secure) {
67
+ /* The BFSR bits [15:8] are shared between security states
68
+ * and we store them in the NS copy.
69
+ */
70
+ cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
71
+ }
72
break;
73
case 0xd2c: /* Hard Fault Status. */
74
cpu->env.v7m.hfsr &= ~value; /* W1C */
75
diff --git a/target/arm/helper.c b/target/arm/helper.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/helper.c
78
+++ b/target/arm/helper.c
79
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
80
/* Bad exception return: instead of popping the exception
81
* stack, directly take a usage fault on the current stack.
82
*/
83
- env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK;
84
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
85
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
86
v7m_exception_taken(cpu, type | 0xf0000000);
87
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
88
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
89
if (return_to_handler != arm_v7m_is_handler_mode(env)) {
90
/* Take an INVPC UsageFault by pushing the stack again. */
91
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
92
- env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK;
93
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
94
v7m_push_stack(cpu);
95
v7m_exception_taken(cpu, type | 0xf0000000);
96
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "
97
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
98
switch (cs->exception_index) {
99
case EXCP_UDEF:
100
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
101
- env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;
102
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
103
break;
104
case EXCP_NOCP:
105
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
106
- env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;
107
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
108
break;
109
case EXCP_INVSTATE:
110
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
111
- env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK;
112
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
113
break;
114
case EXCP_SWI:
115
/* The PC already points to the next instruction. */
116
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
117
case 0x8: /* External Abort */
118
switch (cs->exception_index) {
119
case EXCP_PREFETCH_ABORT:
120
- env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK;
121
+ env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK;
122
qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n");
123
break;
124
case EXCP_DATA_ABORT:
125
- env->v7m.cfsr |=
126
+ env->v7m.cfsr[M_REG_NS] |=
127
(R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
128
env->v7m.bfar = env->exception.vaddress;
129
qemu_log_mask(CPU_LOG_INT,
130
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
131
*/
132
switch (cs->exception_index) {
133
case EXCP_PREFETCH_ABORT:
134
- env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK;
135
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
136
qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n");
137
break;
138
case EXCP_DATA_ABORT:
139
- env->v7m.cfsr |=
140
+ env->v7m.cfsr[env->v7m.secure] |=
141
(R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);
142
env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress;
143
qemu_log_mask(CPU_LOG_INT,
144
diff --git a/target/arm/machine.c b/target/arm/machine.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/machine.c
147
+++ b/target/arm/machine.c
148
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
149
VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
150
VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
151
VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU),
152
- VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
153
+ VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU),
154
VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
155
VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
156
VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU),
157
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
158
VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
159
VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
160
VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),
161
+ VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),
162
VMSTATE_END_OF_LIST()
163
}
164
};
165
--
166
2.7.4
167
168
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/31] target/arm: Move regime_is_secure() to target/arm/internals.h
Deleted patch
1
Move the regime_is_secure() utility function to internals.h;
2
we are going to want to call it from translate.c.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1503414539-28762-20-git-send-email-peter.maydell@linaro.org
7
---
8
target/arm/internals.h | 26 ++++++++++++++++++++++++++
9
target/arm/helper.c | 26 --------------------------
10
2 files changed, 26 insertions(+), 26 deletions(-)
11
12
diff --git a/target/arm/internals.h b/target/arm/internals.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/internals.h
15
+++ b/target/arm/internals.h
16
@@ -XXX,XX +XXX,XX @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
17
}
18
}
19
20
+/* Return true if this address translation regime is secure */
21
+static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
22
+{
23
+ switch (mmu_idx) {
24
+ case ARMMMUIdx_S12NSE0:
25
+ case ARMMMUIdx_S12NSE1:
26
+ case ARMMMUIdx_S1NSE0:
27
+ case ARMMMUIdx_S1NSE1:
28
+ case ARMMMUIdx_S1E2:
29
+ case ARMMMUIdx_S2NS:
30
+ case ARMMMUIdx_MPriv:
31
+ case ARMMMUIdx_MNegPri:
32
+ case ARMMMUIdx_MUser:
33
+ return false;
34
+ case ARMMMUIdx_S1E3:
35
+ case ARMMMUIdx_S1SE0:
36
+ case ARMMMUIdx_S1SE1:
37
+ case ARMMMUIdx_MSPriv:
38
+ case ARMMMUIdx_MSNegPri:
39
+ case ARMMMUIdx_MSUser:
40
+ return true;
41
+ default:
42
+ g_assert_not_reached();
43
+ }
44
+}
45
+
46
#endif
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/helper.c
50
+++ b/target/arm/helper.c
51
@@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
52
}
53
}
54
55
-/* Return true if this address translation regime is secure */
56
-static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
57
-{
58
- switch (mmu_idx) {
59
- case ARMMMUIdx_S12NSE0:
60
- case ARMMMUIdx_S12NSE1:
61
- case ARMMMUIdx_S1NSE0:
62
- case ARMMMUIdx_S1NSE1:
63
- case ARMMMUIdx_S1E2:
64
- case ARMMMUIdx_S2NS:
65
- case ARMMMUIdx_MPriv:
66
- case ARMMMUIdx_MNegPri:
67
- case ARMMMUIdx_MUser:
68
- return false;
69
- case ARMMMUIdx_S1E3:
70
- case ARMMMUIdx_S1SE0:
71
- case ARMMMUIdx_S1SE1:
72
- case ARMMMUIdx_MSPriv:
73
- case ARMMMUIdx_MSNegPri:
74
- case ARMMMUIdx_MSUser:
75
- return true;
76
- default:
77
- g_assert_not_reached();
78
- }
79
-}
80
-
81
/* Return the SCTLR value which controls this address translation regime */
82
static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
83
{
84
--
85
2.7.4
86
87
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/31] target/arm: Implement BXNS, and banked stack pointers
Deleted patch
1
Implement the BXNS v8M instruction, which is like BX but will do a
2
jump-and-switch-to-NonSecure if the branch target address has bit 0
3
clear.
4
1
5
This is the first piece of code which implements "switch to the
6
other security state", so the commit also includes the code to
7
switch the stack pointers around, which is the only complicated
8
part of switching security state.
9
10
BLXNS is more complicated than just "BXNS but set the link register",
11
so we leave it for a separate commit.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 1503414539-28762-21-git-send-email-peter.maydell@linaro.org
16
---
17
target/arm/cpu.h | 13 +++++++++
18
target/arm/helper.h | 2 ++
19
target/arm/translate.h | 1 +
20
target/arm/helper.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++
21
target/arm/machine.c | 2 ++
22
target/arm/translate.c | 42 ++++++++++++++++++++++++++-
23
6 files changed, 138 insertions(+), 1 deletion(-)
24
25
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/cpu.h
28
+++ b/target/arm/cpu.h
29
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
30
} cp15;
31
32
struct {
33
+ /* M profile has up to 4 stack pointers:
34
+ * a Main Stack Pointer and a Process Stack Pointer for each
35
+ * of the Secure and Non-Secure states. (If the CPU doesn't support
36
+ * the security extension then it has only two SPs.)
37
+ * In QEMU we always store the currently active SP in regs[13],
38
+ * and the non-active SP for the current security state in
39
+ * v7m.other_sp. The stack pointers for the inactive security state
40
+ * are stored in other_ss_msp and other_ss_psp.
41
+ * switch_v7m_security_state() is responsible for rearranging them
42
+ * when we change security state.
43
+ */
44
uint32_t other_sp;
45
+ uint32_t other_ss_msp;
46
+ uint32_t other_ss_psp;
47
uint32_t vecbase[2];
48
uint32_t basepri[2];
49
uint32_t control[2];
50
diff --git a/target/arm/helper.h b/target/arm/helper.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/helper.h
53
+++ b/target/arm/helper.h
54
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(cpsr_read, i32, env)
55
DEF_HELPER_3(v7m_msr, void, env, i32, i32)
56
DEF_HELPER_2(v7m_mrs, i32, env, i32)
57
58
+DEF_HELPER_2(v7m_bxns, void, env, i32)
59
+
60
DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)
61
DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
62
DEF_HELPER_2(get_cp_reg, i32, env, ptr)
63
diff --git a/target/arm/translate.h b/target/arm/translate.h
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/translate.h
66
+++ b/target/arm/translate.h
67
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
68
int vec_len;
69
int vec_stride;
70
bool v7m_handler_mode;
71
+ bool v8m_secure; /* true if v8M and we're in Secure mode */
72
/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
73
* so that top level loop can generate correct syndrome information.
74
*/
75
diff --git a/target/arm/helper.c b/target/arm/helper.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/helper.c
78
+++ b/target/arm/helper.c
79
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
80
return 0;
81
}
82
83
+void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
84
+{
85
+ /* translate.c should never generate calls here in user-only mode */
86
+ g_assert_not_reached();
87
+}
88
+
89
void switch_mode(CPUARMState *env, int mode)
90
{
91
ARMCPU *cpu = arm_env_get_cpu(env);
92
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_pop(CPUARMState *env)
93
return val;
94
}
95
96
+/* Return true if we're using the process stack pointer (not the MSP) */
97
+static bool v7m_using_psp(CPUARMState *env)
98
+{
99
+ /* Handler mode always uses the main stack; for thread mode
100
+ * the CONTROL.SPSEL bit determines the answer.
101
+ * Note that in v7M it is not possible to be in Handler mode with
102
+ * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
103
+ */
104
+ return !arm_v7m_is_handler_mode(env) &&
105
+ env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;
106
+}
107
+
108
/* Switch to V7M main or process stack pointer. */
109
static void switch_v7m_sp(CPUARMState *env, bool new_spsel)
110
{
111
@@ -XXX,XX +XXX,XX @@ static void switch_v7m_sp(CPUARMState *env, bool new_spsel)
112
}
113
}
114
115
+/* Switch M profile security state between NS and S */
116
+static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
117
+{
118
+ uint32_t new_ss_msp, new_ss_psp;
119
+
120
+ if (env->v7m.secure == new_secstate) {
121
+ return;
122
+ }
123
+
124
+ /* All the banked state is accessed by looking at env->v7m.secure
125
+ * except for the stack pointer; rearrange the SP appropriately.
126
+ */
127
+ new_ss_msp = env->v7m.other_ss_msp;
128
+ new_ss_psp = env->v7m.other_ss_psp;
129
+
130
+ if (v7m_using_psp(env)) {
131
+ env->v7m.other_ss_psp = env->regs[13];
132
+ env->v7m.other_ss_msp = env->v7m.other_sp;
133
+ } else {
134
+ env->v7m.other_ss_msp = env->regs[13];
135
+ env->v7m.other_ss_psp = env->v7m.other_sp;
136
+ }
137
+
138
+ env->v7m.secure = new_secstate;
139
+
140
+ if (v7m_using_psp(env)) {
141
+ env->regs[13] = new_ss_psp;
142
+ env->v7m.other_sp = new_ss_msp;
143
+ } else {
144
+ env->regs[13] = new_ss_msp;
145
+ env->v7m.other_sp = new_ss_psp;
146
+ }
147
+}
148
+
149
+void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
150
+{
151
+ /* Handle v7M BXNS:
152
+ * - if the return value is a magic value, do exception return (like BX)
153
+ * - otherwise bit 0 of the return value is the target security state
154
+ */
155
+ if (dest >= 0xff000000) {
156
+ /* This is an exception return magic value; put it where
157
+ * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
158
+ * Note that if we ever add gen_ss_advance() singlestep support to
159
+ * M profile this should count as an "instruction execution complete"
160
+ * event (compare gen_bx_excret_final_code()).
161
+ */
162
+ env->regs[15] = dest & ~1;
163
+ env->thumb = dest & 1;
164
+ HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT);
165
+ /* notreached */
166
+ }
167
+
168
+ /* translate.c should have made BXNS UNDEF unless we're secure */
169
+ assert(env->v7m.secure);
170
+
171
+ switch_v7m_security_state(env, dest & 1);
172
+ env->thumb = 1;
173
+ env->regs[15] = dest & ~1;
174
+}
175
+
176
static uint32_t arm_v7m_load_vector(ARMCPU *cpu)
177
{
178
CPUState *cs = CPU(cpu);
179
diff --git a/target/arm/machine.c b/target/arm/machine.c
180
index XXXXXXX..XXXXXXX 100644
181
--- a/target/arm/machine.c
182
+++ b/target/arm/machine.c
183
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_security = {
184
.needed = m_security_needed,
185
.fields = (VMStateField[]) {
186
VMSTATE_UINT32(env.v7m.secure, ARMCPU),
187
+ VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU),
188
+ VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU),
189
VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
190
VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
191
VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
192
diff --git a/target/arm/translate.c b/target/arm/translate.c
193
index XXXXXXX..XXXXXXX 100644
194
--- a/target/arm/translate.c
195
+++ b/target/arm/translate.c
196
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
197
gen_exception_internal(EXCP_EXCEPTION_EXIT);
198
}
199
200
+static inline void gen_bxns(DisasContext *s, int rm)
201
+{
202
+ TCGv_i32 var = load_reg(s, rm);
203
+
204
+ /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
205
+ * we need to sync state before calling it, but:
206
+ * - we don't need to do gen_set_pc_im() because the bxns helper will
207
+ * always set the PC itself
208
+ * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
209
+ * unless it's outside an IT block or the last insn in an IT block,
210
+ * so we know that condexec == 0 (already set at the top of the TB)
211
+ * is correct in the non-UNPREDICTABLE cases, and we can choose
212
+ * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
213
+ */
214
+ gen_helper_v7m_bxns(cpu_env, var);
215
+ tcg_temp_free_i32(var);
216
+ s->is_jmp = DISAS_EXIT;
217
+}
218
+
219
/* Variant of store_reg which uses branch&exchange logic when storing
220
to r15 in ARM architecture v7 and above. The source must be a temporary
221
and will be marked as dead. */
222
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
223
*/
224
bool link = insn & (1 << 7);
225
226
- if (insn & 7) {
227
+ if (insn & 3) {
228
goto undef;
229
}
230
if (link) {
231
ARCH(5);
232
}
233
+ if ((insn & 4)) {
234
+ /* BXNS/BLXNS: only exists for v8M with the
235
+ * security extensions, and always UNDEF if NonSecure.
236
+ * We don't implement these in the user-only mode
237
+ * either (in theory you can use them from Secure User
238
+ * mode but they are too tied in to system emulation.)
239
+ */
240
+ if (!s->v8m_secure || IS_USER_ONLY) {
241
+ goto undef;
242
+ }
243
+ if (link) {
244
+ /* BLXNS: not yet implemented */
245
+ goto undef;
246
+ } else {
247
+ gen_bxns(s, rm);
248
+ }
249
+ break;
250
+ }
251
+ /* BLX/BX */
252
tmp = load_reg(s, rm);
253
if (link) {
254
val = (uint32_t)s->pc | 1;
255
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
256
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
257
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
258
dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
259
+ dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
260
+ regime_is_secure(env, dc->mmu_idx);
261
dc->cp_regs = cpu->cp_regs;
262
dc->features = env->features;
263
264
--
265
2.7.4
266
267
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/31] boards.h: Define new flag ignore_memory_transaction_failures
Deleted patch
1
Define a new MachineClass field ignore_memory_transaction_failures.
2
If this is flag is true then the CPU will ignore memory transaction
3
failures which should cause the CPU to take an exception due to an
4
access to an unassigned physical address; the transaction will
5
instead return zero (for a read) or be ignored (for a write). This
6
should be set only by legacy board models which rely on the old
7
RAZ/WI behaviour for handling devices that QEMU does not yet model.
8
New board models should instead use "unimplemented-device" for all
9
memory ranges where the guest will attempt to probe for a device that
10
QEMU doesn't implement and a stub device is required.
11
1
12
We need this for ARM boards, where we're about to implement support for
13
generating external aborts on memory transaction failures. Too many
14
of our legacy board models rely on the RAZ/WI behaviour and we
15
would break currently working guests when their "probe for device"
16
code provoked an external abort rather than a RAZ.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
21
Message-id: 1504626814-23124-2-git-send-email-peter.maydell@linaro.org
22
---
23
include/hw/boards.h | 11 +++++++++++
24
include/qom/cpu.h | 7 ++++++-
25
qom/cpu.c | 16 ++++++++++++++++
26
3 files changed, 33 insertions(+), 1 deletion(-)
27
28
diff --git a/include/hw/boards.h b/include/hw/boards.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/boards.h
31
+++ b/include/hw/boards.h
32
@@ -XXX,XX +XXX,XX @@ typedef struct {
33
* size than the target architecture's minimum. (Attempting to create
34
* such a CPU will fail.) Note that changing this is a migration
35
* compatibility break for the machine.
36
+ * @ignore_memory_transaction_failures:
37
+ * If this is flag is true then the CPU will ignore memory transaction
38
+ * failures which should cause the CPU to take an exception due to an
39
+ * access to an unassigned physical address; the transaction will instead
40
+ * return zero (for a read) or be ignored (for a write). This should be
41
+ * set only by legacy board models which rely on the old RAZ/WI behaviour
42
+ * for handling devices that QEMU does not yet model. New board models
43
+ * should instead use "unimplemented-device" for all memory ranges where
44
+ * the guest will attempt to probe for a device that QEMU doesn't
45
+ * implement and a stub device is required.
46
*/
47
struct MachineClass {
48
/*< private >*/
49
@@ -XXX,XX +XXX,XX @@ struct MachineClass {
50
bool rom_file_has_mr;
51
int minimum_page_bits;
52
bool has_hotpluggable_cpus;
53
+ bool ignore_memory_transaction_failures;
54
int numa_mem_align_shift;
55
void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes,
56
int nb_nodes, ram_addr_t size);
57
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/qom/cpu.h
60
+++ b/include/qom/cpu.h
61
@@ -XXX,XX +XXX,XX @@ struct qemu_work_item;
62
* @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
63
* to @trace_dstate).
64
* @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
65
+ * @ignore_memory_transaction_failures: Cached copy of the MachineState
66
+ * flag of the same name: allows the board to suppress calling of the
67
+ * CPU do_transaction_failed hook function.
68
*
69
* State of one CPU core or thread.
70
*/
71
@@ -XXX,XX +XXX,XX @@ struct CPUState {
72
*/
73
bool throttle_thread_scheduled;
74
75
+ bool ignore_memory_transaction_failures;
76
+
77
/* Note that this is accessed at the start of every TB via a negative
78
offset from AREG0. Leave this field at the end so as to make the
79
(absolute value) offset as small as possible. This reduces code
80
@@ -XXX,XX +XXX,XX @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
81
{
82
CPUClass *cc = CPU_GET_CLASS(cpu);
83
84
- if (cc->do_transaction_failed) {
85
+ if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
86
cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
87
mmu_idx, attrs, response, retaddr);
88
}
89
diff --git a/qom/cpu.c b/qom/cpu.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/qom/cpu.c
92
+++ b/qom/cpu.c
93
@@ -XXX,XX +XXX,XX @@
94
#include "exec/cpu-common.h"
95
#include "qemu/error-report.h"
96
#include "sysemu/sysemu.h"
97
+#include "hw/boards.h"
98
#include "hw/qdev-properties.h"
99
#include "trace-root.h"
100
101
@@ -XXX,XX +XXX,XX @@ static void cpu_common_parse_features(const char *typename, char *features,
102
static void cpu_common_realizefn(DeviceState *dev, Error **errp)
103
{
104
CPUState *cpu = CPU(dev);
105
+ Object *machine = qdev_get_machine();
106
+
107
+ /* qdev_get_machine() can return something that's not TYPE_MACHINE
108
+ * if this is one of the user-only emulators; in that case there's
109
+ * no need to check the ignore_memory_transaction_failures board flag.
110
+ */
111
+ if (object_dynamic_cast(machine, TYPE_MACHINE)) {
112
+ ObjectClass *oc = object_get_class(machine);
113
+ MachineClass *mc = MACHINE_CLASS(oc);
114
+
115
+ if (mc) {
116
+ cpu->ignore_memory_transaction_failures =
117
+ mc->ignore_memory_transaction_failures;
118
+ }
119
+ }
120
121
if (dev->hotplugged) {
122
cpu_synchronize_post_init(cpu);
123
--
124
2.7.4
125
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/31] hw/arm: Set ignore_memory_transaction_failures for most ARM boards
Deleted patch
1
Set the MachineClass flag ignore_memory_transaction_failures
2
for almost all ARM boards. This means they retain the legacy
3
behaviour that accesses to unimplemented addresses will RAZ/WI
4
rather than aborting, when a subsequent commit adds support
5
for external aborts.
6
1
7
The exceptions are:
8
* virt -- we know that guests won't try to prod devices
9
that we don't describe in the device tree or ACPI tables
10
* mps2 -- this board was written to use unimplemented-device
11
for all the ranges with devices we don't yet handle
12
13
New boards should not set the flag, but instead be written
14
like the mps2.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
18
Message-id: 1504626814-23124-3-git-send-email-peter.maydell@linaro.org
19
For the Xilinx boards:
20
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
21
---
22
hw/arm/aspeed.c | 3 +++
23
hw/arm/collie.c | 1 +
24
hw/arm/cubieboard.c | 1 +
25
hw/arm/digic_boards.c | 1 +
26
hw/arm/exynos4_boards.c | 2 ++
27
hw/arm/gumstix.c | 2 ++
28
hw/arm/highbank.c | 2 ++
29
hw/arm/imx25_pdk.c | 1 +
30
hw/arm/integratorcp.c | 1 +
31
hw/arm/kzm.c | 1 +
32
hw/arm/mainstone.c | 1 +
33
hw/arm/musicpal.c | 1 +
34
hw/arm/netduino2.c | 1 +
35
hw/arm/nseries.c | 2 ++
36
hw/arm/omap_sx1.c | 2 ++
37
hw/arm/palm.c | 1 +
38
hw/arm/raspi.c | 1 +
39
hw/arm/realview.c | 4 ++++
40
hw/arm/sabrelite.c | 1 +
41
hw/arm/spitz.c | 4 ++++
42
hw/arm/stellaris.c | 2 ++
43
hw/arm/tosa.c | 1 +
44
hw/arm/versatilepb.c | 2 ++
45
hw/arm/vexpress.c | 1 +
46
hw/arm/xilinx_zynq.c | 1 +
47
hw/arm/xlnx-ep108.c | 2 ++
48
hw/arm/z2.c | 1 +
49
27 files changed, 43 insertions(+)
50
51
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/aspeed.c
54
+++ b/hw/arm/aspeed.c
55
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
56
mc->no_floppy = 1;
57
mc->no_cdrom = 1;
58
mc->no_parallel = 1;
59
+ mc->ignore_memory_transaction_failures = true;
60
}
61
62
static const TypeInfo palmetto_bmc_type = {
63
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_class_init(ObjectClass *oc, void *data)
64
mc->no_floppy = 1;
65
mc->no_cdrom = 1;
66
mc->no_parallel = 1;
67
+ mc->ignore_memory_transaction_failures = true;
68
}
69
70
static const TypeInfo ast2500_evb_type = {
71
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_class_init(ObjectClass *oc, void *data)
72
mc->no_floppy = 1;
73
mc->no_cdrom = 1;
74
mc->no_parallel = 1;
75
+ mc->ignore_memory_transaction_failures = true;
76
}
77
78
static const TypeInfo romulus_bmc_type = {
79
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/arm/collie.c
82
+++ b/hw/arm/collie.c
83
@@ -XXX,XX +XXX,XX @@ static void collie_machine_init(MachineClass *mc)
84
{
85
mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)";
86
mc->init = collie_init;
87
+ mc->ignore_memory_transaction_failures = true;
88
}
89
90
DEFINE_MACHINE("collie", collie_machine_init)
91
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/arm/cubieboard.c
94
+++ b/hw/arm/cubieboard.c
95
@@ -XXX,XX +XXX,XX @@ static void cubieboard_machine_init(MachineClass *mc)
96
mc->init = cubieboard_init;
97
mc->block_default_type = IF_IDE;
98
mc->units_per_default_bus = 1;
99
+ mc->ignore_memory_transaction_failures = true;
100
}
101
102
DEFINE_MACHINE("cubieboard", cubieboard_machine_init)
103
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/hw/arm/digic_boards.c
106
+++ b/hw/arm/digic_boards.c
107
@@ -XXX,XX +XXX,XX @@ static void canon_a1100_machine_init(MachineClass *mc)
108
{
109
mc->desc = "Canon PowerShot A1100 IS";
110
mc->init = &canon_a1100_init;
111
+ mc->ignore_memory_transaction_failures = true;
112
}
113
114
DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init)
115
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/arm/exynos4_boards.c
118
+++ b/hw/arm/exynos4_boards.c
119
@@ -XXX,XX +XXX,XX @@ static void nuri_class_init(ObjectClass *oc, void *data)
120
mc->desc = "Samsung NURI board (Exynos4210)";
121
mc->init = nuri_init;
122
mc->max_cpus = EXYNOS4210_NCPUS;
123
+ mc->ignore_memory_transaction_failures = true;
124
}
125
126
static const TypeInfo nuri_type = {
127
@@ -XXX,XX +XXX,XX @@ static void smdkc210_class_init(ObjectClass *oc, void *data)
128
mc->desc = "Samsung SMDKC210 board (Exynos4210)";
129
mc->init = smdkc210_init;
130
mc->max_cpus = EXYNOS4210_NCPUS;
131
+ mc->ignore_memory_transaction_failures = true;
132
}
133
134
static const TypeInfo smdkc210_type = {
135
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
136
index XXXXXXX..XXXXXXX 100644
137
--- a/hw/arm/gumstix.c
138
+++ b/hw/arm/gumstix.c
139
@@ -XXX,XX +XXX,XX @@ static void connex_class_init(ObjectClass *oc, void *data)
140
141
mc->desc = "Gumstix Connex (PXA255)";
142
mc->init = connex_init;
143
+ mc->ignore_memory_transaction_failures = true;
144
}
145
146
static const TypeInfo connex_type = {
147
@@ -XXX,XX +XXX,XX @@ static void verdex_class_init(ObjectClass *oc, void *data)
148
149
mc->desc = "Gumstix Verdex (PXA270)";
150
mc->init = verdex_init;
151
+ mc->ignore_memory_transaction_failures = true;
152
}
153
154
static const TypeInfo verdex_type = {
155
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
156
index XXXXXXX..XXXXXXX 100644
157
--- a/hw/arm/highbank.c
158
+++ b/hw/arm/highbank.c
159
@@ -XXX,XX +XXX,XX @@ static void highbank_class_init(ObjectClass *oc, void *data)
160
mc->block_default_type = IF_IDE;
161
mc->units_per_default_bus = 1;
162
mc->max_cpus = 4;
163
+ mc->ignore_memory_transaction_failures = true;
164
}
165
166
static const TypeInfo highbank_type = {
167
@@ -XXX,XX +XXX,XX @@ static void midway_class_init(ObjectClass *oc, void *data)
168
mc->block_default_type = IF_IDE;
169
mc->units_per_default_bus = 1;
170
mc->max_cpus = 4;
171
+ mc->ignore_memory_transaction_failures = true;
172
}
173
174
static const TypeInfo midway_type = {
175
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/arm/imx25_pdk.c
178
+++ b/hw/arm/imx25_pdk.c
179
@@ -XXX,XX +XXX,XX @@ static void imx25_pdk_machine_init(MachineClass *mc)
180
{
181
mc->desc = "ARM i.MX25 PDK board (ARM926)";
182
mc->init = imx25_pdk_init;
183
+ mc->ignore_memory_transaction_failures = true;
184
}
185
186
DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init)
187
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
188
index XXXXXXX..XXXXXXX 100644
189
--- a/hw/arm/integratorcp.c
190
+++ b/hw/arm/integratorcp.c
191
@@ -XXX,XX +XXX,XX @@ static void integratorcp_machine_init(MachineClass *mc)
192
{
193
mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
194
mc->init = integratorcp_init;
195
+ mc->ignore_memory_transaction_failures = true;
196
}
197
198
DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
199
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/arm/kzm.c
202
+++ b/hw/arm/kzm.c
203
@@ -XXX,XX +XXX,XX @@ static void kzm_machine_init(MachineClass *mc)
204
{
205
mc->desc = "ARM KZM Emulation Baseboard (ARM1136)";
206
mc->init = kzm_init;
207
+ mc->ignore_memory_transaction_failures = true;
208
}
209
210
DEFINE_MACHINE("kzm", kzm_machine_init)
211
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/hw/arm/mainstone.c
214
+++ b/hw/arm/mainstone.c
215
@@ -XXX,XX +XXX,XX @@ static void mainstone2_machine_init(MachineClass *mc)
216
{
217
mc->desc = "Mainstone II (PXA27x)";
218
mc->init = mainstone_init;
219
+ mc->ignore_memory_transaction_failures = true;
220
}
221
222
DEFINE_MACHINE("mainstone", mainstone2_machine_init)
223
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
224
index XXXXXXX..XXXXXXX 100644
225
--- a/hw/arm/musicpal.c
226
+++ b/hw/arm/musicpal.c
227
@@ -XXX,XX +XXX,XX @@ static void musicpal_machine_init(MachineClass *mc)
228
{
229
mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)";
230
mc->init = musicpal_init;
231
+ mc->ignore_memory_transaction_failures = true;
232
}
233
234
DEFINE_MACHINE("musicpal", musicpal_machine_init)
235
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
236
index XXXXXXX..XXXXXXX 100644
237
--- a/hw/arm/netduino2.c
238
+++ b/hw/arm/netduino2.c
239
@@ -XXX,XX +XXX,XX @@ static void netduino2_machine_init(MachineClass *mc)
240
{
241
mc->desc = "Netduino 2 Machine";
242
mc->init = netduino2_init;
243
+ mc->ignore_memory_transaction_failures = true;
244
}
245
246
DEFINE_MACHINE("netduino2", netduino2_machine_init)
247
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
248
index XXXXXXX..XXXXXXX 100644
249
--- a/hw/arm/nseries.c
250
+++ b/hw/arm/nseries.c
251
@@ -XXX,XX +XXX,XX @@ static void n800_class_init(ObjectClass *oc, void *data)
252
mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)";
253
mc->init = n800_init;
254
mc->default_boot_order = "";
255
+ mc->ignore_memory_transaction_failures = true;
256
}
257
258
static const TypeInfo n800_type = {
259
@@ -XXX,XX +XXX,XX @@ static void n810_class_init(ObjectClass *oc, void *data)
260
mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)";
261
mc->init = n810_init;
262
mc->default_boot_order = "";
263
+ mc->ignore_memory_transaction_failures = true;
264
}
265
266
static const TypeInfo n810_type = {
267
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/hw/arm/omap_sx1.c
270
+++ b/hw/arm/omap_sx1.c
271
@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
272
273
mc->desc = "Siemens SX1 (OMAP310) V2";
274
mc->init = sx1_init_v2;
275
+ mc->ignore_memory_transaction_failures = true;
276
}
277
278
static const TypeInfo sx1_machine_v2_type = {
279
@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
280
281
mc->desc = "Siemens SX1 (OMAP310) V1";
282
mc->init = sx1_init_v1;
283
+ mc->ignore_memory_transaction_failures = true;
284
}
285
286
static const TypeInfo sx1_machine_v1_type = {
287
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
288
index XXXXXXX..XXXXXXX 100644
289
--- a/hw/arm/palm.c
290
+++ b/hw/arm/palm.c
291
@@ -XXX,XX +XXX,XX @@ static void palmte_machine_init(MachineClass *mc)
292
{
293
mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)";
294
mc->init = palmte_init;
295
+ mc->ignore_memory_transaction_failures = true;
296
}
297
298
DEFINE_MACHINE("cheetah", palmte_machine_init)
299
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
300
index XXXXXXX..XXXXXXX 100644
301
--- a/hw/arm/raspi.c
302
+++ b/hw/arm/raspi.c
303
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
304
mc->no_cdrom = 1;
305
mc->max_cpus = BCM2836_NCPUS;
306
mc->default_ram_size = 1024 * 1024 * 1024;
307
+ mc->ignore_memory_transaction_failures = true;
308
};
309
DEFINE_MACHINE("raspi2", raspi2_machine_init)
310
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
311
index XXXXXXX..XXXXXXX 100644
312
--- a/hw/arm/realview.c
313
+++ b/hw/arm/realview.c
314
@@ -XXX,XX +XXX,XX @@ static void realview_eb_class_init(ObjectClass *oc, void *data)
315
mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
316
mc->init = realview_eb_init;
317
mc->block_default_type = IF_SCSI;
318
+ mc->ignore_memory_transaction_failures = true;
319
}
320
321
static const TypeInfo realview_eb_type = {
322
@@ -XXX,XX +XXX,XX @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
323
mc->init = realview_eb_mpcore_init;
324
mc->block_default_type = IF_SCSI;
325
mc->max_cpus = 4;
326
+ mc->ignore_memory_transaction_failures = true;
327
}
328
329
static const TypeInfo realview_eb_mpcore_type = {
330
@@ -XXX,XX +XXX,XX @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
331
332
mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
333
mc->init = realview_pb_a8_init;
334
+ mc->ignore_memory_transaction_failures = true;
335
}
336
337
static const TypeInfo realview_pb_a8_type = {
338
@@ -XXX,XX +XXX,XX @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
339
mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
340
mc->init = realview_pbx_a9_init;
341
mc->max_cpus = 4;
342
+ mc->ignore_memory_transaction_failures = true;
343
}
344
345
static const TypeInfo realview_pbx_a9_type = {
346
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
347
index XXXXXXX..XXXXXXX 100644
348
--- a/hw/arm/sabrelite.c
349
+++ b/hw/arm/sabrelite.c
350
@@ -XXX,XX +XXX,XX @@ static void sabrelite_machine_init(MachineClass *mc)
351
mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)";
352
mc->init = sabrelite_init;
353
mc->max_cpus = FSL_IMX6_NUM_CPUS;
354
+ mc->ignore_memory_transaction_failures = true;
355
}
356
357
DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
358
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/hw/arm/spitz.c
361
+++ b/hw/arm/spitz.c
362
@@ -XXX,XX +XXX,XX @@ static void akitapda_class_init(ObjectClass *oc, void *data)
363
364
mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
365
mc->init = akita_init;
366
+ mc->ignore_memory_transaction_failures = true;
367
}
368
369
static const TypeInfo akitapda_type = {
370
@@ -XXX,XX +XXX,XX @@ static void spitzpda_class_init(ObjectClass *oc, void *data)
371
mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
372
mc->init = spitz_init;
373
mc->block_default_type = IF_IDE;
374
+ mc->ignore_memory_transaction_failures = true;
375
}
376
377
static const TypeInfo spitzpda_type = {
378
@@ -XXX,XX +XXX,XX @@ static void borzoipda_class_init(ObjectClass *oc, void *data)
379
mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
380
mc->init = borzoi_init;
381
mc->block_default_type = IF_IDE;
382
+ mc->ignore_memory_transaction_failures = true;
383
}
384
385
static const TypeInfo borzoipda_type = {
386
@@ -XXX,XX +XXX,XX @@ static void terrierpda_class_init(ObjectClass *oc, void *data)
387
mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
388
mc->init = terrier_init;
389
mc->block_default_type = IF_IDE;
390
+ mc->ignore_memory_transaction_failures = true;
391
}
392
393
static const TypeInfo terrierpda_type = {
394
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
395
index XXXXXXX..XXXXXXX 100644
396
--- a/hw/arm/stellaris.c
397
+++ b/hw/arm/stellaris.c
398
@@ -XXX,XX +XXX,XX @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)
399
400
mc->desc = "Stellaris LM3S811EVB";
401
mc->init = lm3s811evb_init;
402
+ mc->ignore_memory_transaction_failures = true;
403
}
404
405
static const TypeInfo lm3s811evb_type = {
406
@@ -XXX,XX +XXX,XX @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
407
408
mc->desc = "Stellaris LM3S6965EVB";
409
mc->init = lm3s6965evb_init;
410
+ mc->ignore_memory_transaction_failures = true;
411
}
412
413
static const TypeInfo lm3s6965evb_type = {
414
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
415
index XXXXXXX..XXXXXXX 100644
416
--- a/hw/arm/tosa.c
417
+++ b/hw/arm/tosa.c
418
@@ -XXX,XX +XXX,XX @@ static void tosapda_machine_init(MachineClass *mc)
419
mc->desc = "Sharp SL-6000 (Tosa) PDA (PXA255)";
420
mc->init = tosa_init;
421
mc->block_default_type = IF_IDE;
422
+ mc->ignore_memory_transaction_failures = true;
423
}
424
425
DEFINE_MACHINE("tosa", tosapda_machine_init)
426
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
427
index XXXXXXX..XXXXXXX 100644
428
--- a/hw/arm/versatilepb.c
429
+++ b/hw/arm/versatilepb.c
430
@@ -XXX,XX +XXX,XX @@ static void versatilepb_class_init(ObjectClass *oc, void *data)
431
mc->desc = "ARM Versatile/PB (ARM926EJ-S)";
432
mc->init = vpb_init;
433
mc->block_default_type = IF_SCSI;
434
+ mc->ignore_memory_transaction_failures = true;
435
}
436
437
static const TypeInfo versatilepb_type = {
438
@@ -XXX,XX +XXX,XX @@ static void versatileab_class_init(ObjectClass *oc, void *data)
439
mc->desc = "ARM Versatile/AB (ARM926EJ-S)";
440
mc->init = vab_init;
441
mc->block_default_type = IF_SCSI;
442
+ mc->ignore_memory_transaction_failures = true;
443
}
444
445
static const TypeInfo versatileab_type = {
446
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
447
index XXXXXXX..XXXXXXX 100644
448
--- a/hw/arm/vexpress.c
449
+++ b/hw/arm/vexpress.c
450
@@ -XXX,XX +XXX,XX @@ static void vexpress_class_init(ObjectClass *oc, void *data)
451
mc->desc = "ARM Versatile Express";
452
mc->init = vexpress_common_init;
453
mc->max_cpus = 4;
454
+ mc->ignore_memory_transaction_failures = true;
455
}
456
457
static void vexpress_a9_class_init(ObjectClass *oc, void *data)
458
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
459
index XXXXXXX..XXXXXXX 100644
460
--- a/hw/arm/xilinx_zynq.c
461
+++ b/hw/arm/xilinx_zynq.c
462
@@ -XXX,XX +XXX,XX @@ static void zynq_machine_init(MachineClass *mc)
463
mc->init = zynq_init;
464
mc->max_cpus = 1;
465
mc->no_sdcard = 1;
466
+ mc->ignore_memory_transaction_failures = true;
467
}
468
469
DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
470
diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
471
index XXXXXXX..XXXXXXX 100644
472
--- a/hw/arm/xlnx-ep108.c
473
+++ b/hw/arm/xlnx-ep108.c
474
@@ -XXX,XX +XXX,XX @@ static void xlnx_ep108_machine_init(MachineClass *mc)
475
mc->init = xlnx_ep108_init;
476
mc->block_default_type = IF_IDE;
477
mc->units_per_default_bus = 1;
478
+ mc->ignore_memory_transaction_failures = true;
479
}
480
481
DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init)
482
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_init(MachineClass *mc)
483
mc->init = xlnx_ep108_init;
484
mc->block_default_type = IF_IDE;
485
mc->units_per_default_bus = 1;
486
+ mc->ignore_memory_transaction_failures = true;
487
}
488
489
DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init)
490
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
491
index XXXXXXX..XXXXXXX 100644
492
--- a/hw/arm/z2.c
493
+++ b/hw/arm/z2.c
494
@@ -XXX,XX +XXX,XX @@ static void z2_machine_init(MachineClass *mc)
495
{
496
mc->desc = "Zipit Z2 (PXA27x)";
497
mc->init = z2_init;
498
+ mc->ignore_memory_transaction_failures = true;
499
}
500
501
DEFINE_MACHINE("z2", z2_machine_init)
502
--
503
2.7.4
504
505
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/31] target/arm: Implement new do_transaction_failed hook
Deleted patch
1
Implement the new do_transaction_failed hook for ARM, which should
2
cause the CPU to take a prefetch abort or data abort.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Message-id: 1504626814-23124-4-git-send-email-peter.maydell@linaro.org
8
---
9
target/arm/internals.h | 10 ++++++++++
10
target/arm/cpu.c | 1 +
11
target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++
12
3 files changed, 54 insertions(+)
13
14
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/internals.h
17
+++ b/target/arm/internals.h
18
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
19
MMUAccessType access_type,
20
int mmu_idx, uintptr_t retaddr);
21
22
+/* arm_cpu_do_transaction_failed: handle a memory system error response
23
+ * (eg "no device/memory present at address") by raising an external abort
24
+ * exception
25
+ */
26
+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
27
+ vaddr addr, unsigned size,
28
+ MMUAccessType access_type,
29
+ int mmu_idx, MemTxAttrs attrs,
30
+ MemTxResult response, uintptr_t retaddr);
31
+
32
/* Call the EL change hook if one has been registered */
33
static inline void arm_call_el_change_hook(ARMCPU *cpu)
34
{
35
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu.c
38
+++ b/target/arm/cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
40
#else
41
cc->do_interrupt = arm_cpu_do_interrupt;
42
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
43
+ cc->do_transaction_failed = arm_cpu_do_transaction_failed;
44
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
45
cc->asidx_from_attrs = arm_asidx_from_attrs;
46
cc->vmsd = &vmstate_arm_cpu;
47
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/op_helper.c
50
+++ b/target/arm/op_helper.c
51
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
52
deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi);
53
}
54
55
+/* arm_cpu_do_transaction_failed: handle a memory system error response
56
+ * (eg "no device/memory present at address") by raising an external abort
57
+ * exception
58
+ */
59
+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
60
+ vaddr addr, unsigned size,
61
+ MMUAccessType access_type,
62
+ int mmu_idx, MemTxAttrs attrs,
63
+ MemTxResult response, uintptr_t retaddr)
64
+{
65
+ ARMCPU *cpu = ARM_CPU(cs);
66
+ CPUARMState *env = &cpu->env;
67
+ uint32_t fsr, fsc;
68
+ ARMMMUFaultInfo fi = {};
69
+ ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
70
+
71
+ if (retaddr) {
72
+ /* now we have a real cpu fault */
73
+ cpu_restore_state(cs, retaddr);
74
+ }
75
+
76
+ /* The EA bit in syndromes and fault status registers is an
77
+ * IMPDEF classification of external aborts. ARM implementations
78
+ * usually use this to indicate AXI bus Decode error (0) or
79
+ * Slave error (1); in QEMU we follow that.
80
+ */
81
+ fi.ea = (response != MEMTX_DECODE_ERROR);
82
+
83
+ /* The fault status register format depends on whether we're using
84
+ * the LPAE long descriptor format, or the short descriptor format.
85
+ */
86
+ if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
87
+ /* long descriptor form, STATUS 0b010000: synchronous ext abort */
88
+ fsr = (fi.ea << 12) | (1 << 9) | 0x10;
89
+ } else {
90
+ /* short descriptor form, FSR 0b01000 : synchronous ext abort */
91
+ fsr = (fi.ea << 12) | 0x8;
92
+ }
93
+ fsc = 0x10;
94
+
95
+ deliver_fault(cpu, addr, access_type, fsr, fsc, &fi);
96
+}
97
+
98
#endif /* !defined(CONFIG_USER_ONLY) */
99
100
uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
101
--
102
2.7.4
103
104
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature
Deleted patch
1
From: Portia Stephens <portia.stephens@xilinx.com>
2
1
3
This adds a feature bit indicating support of the (trivial) Jazelle
4
implementation if ARM_FEATURE_V6 is set or if the processor is arm926
5
or arm1026. This fixes the issue that any BXJ instruction will
6
result in an illegal_op. BXJ instructions will now check if the
7
architecture supports ARM_FEATURE_JAZELLE.
8
9
Signed-off-by: Portia Stephens <portia.stephens@xilinx.com>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11
Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com
12
[PMM: edited commit message and comment text a bit]
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/cpu.h | 1 +
17
target/arm/cpu.c | 3 +++
18
target/arm/translate.c | 2 +-
19
3 files changed, 5 insertions(+), 1 deletion(-)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@ enum arm_features {
26
ARM_FEATURE_PMU, /* has PMU support */
27
ARM_FEATURE_VBAR, /* has cp15 VBAR */
28
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
29
+ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
30
};
31
32
static inline int arm_feature(CPUARMState *env, int feature)
33
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.c
36
+++ b/target/arm/cpu.c
37
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
38
}
39
if (arm_feature(env, ARM_FEATURE_V6)) {
40
set_feature(env, ARM_FEATURE_V5);
41
+ set_feature(env, ARM_FEATURE_JAZELLE);
42
if (!arm_feature(env, ARM_FEATURE_M)) {
43
set_feature(env, ARM_FEATURE_AUXCR);
44
}
45
@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
46
set_feature(&cpu->env, ARM_FEATURE_VFP);
47
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
48
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
49
+ set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
50
cpu->midr = 0x41069265;
51
cpu->reset_fpsid = 0x41011090;
52
cpu->ctr = 0x1dd20d2;
53
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
54
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
55
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
56
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
57
+ set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
58
cpu->midr = 0x4106a262;
59
cpu->reset_fpsid = 0x410110a0;
60
cpu->ctr = 0x1dd20d2;
61
diff --git a/target/arm/translate.c b/target/arm/translate.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/translate.c
64
+++ b/target/arm/translate.c
65
@@ -XXX,XX +XXX,XX @@
66
#define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
67
/* currently all emulated v5 cores are also v5TE, so don't bother */
68
#define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
69
-#define ENABLE_ARCH_5J 0
70
+#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE)
71
#define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
72
#define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
73
#define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
74
--
75
2.7.4
76
77
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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