| 1 | Third time's the charm... | 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: |
|---|---|---|---|
| 2 | we were using uninitialized data for the guarded bit when | ||
| 3 | combining stage 1 and stage 2 attrs. | ||
| 2 | 4 | ||
| 5 | thanks | ||
| 3 | -- PMM | 6 | -- PMM |
| 4 | 7 | ||
| 5 | The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278: | 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: |
| 6 | 9 | ||
| 7 | Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100) | 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) |
| 8 | 11 | ||
| 9 | are available in the git repository at: | 12 | are available in the Git repository at: |
| 10 | 13 | ||
| 11 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 |
| 12 | 15 | ||
| 13 | for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c: | 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: |
| 14 | 17 | ||
| 15 | arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100) | 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) |
| 16 | 19 | ||
| 17 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 18 | target-arm: | 21 | target-arm: Fix bug where we weren't initializing |
| 19 | * collection of M profile cleanups and minor bugfixes | 22 | guarded bit state when combining S1/S2 attrs |
| 20 | * loader: handle ELF files with overlapping zero-init data | ||
| 21 | * virt: allow PMU instantiation with userspace irqchip | ||
| 22 | * wdt_aspeed: Add support for the reset width register | ||
| 23 | * cpu: Define new cpu_transaction_failed() hook | ||
| 24 | * Mark some SoC devices as not user-creatable | ||
| 25 | * arm: Fix aa64 ldp register writeback | ||
| 26 | * arm_gicv3_kvm: Fix compile warning | ||
| 27 | 23 | ||
| 28 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 29 | Andrew Jeffery (2): | 25 | Richard Henderson (2): |
| 30 | watchdog: wdt_aspeed: Add support for the reset width register | 26 | target/arm: PTE bit GP only applies to stage1 |
| 31 | aspeed_soc: Propagate silicon-rev to watchdog | 27 | target/arm: Copy guarded bit in combine_cacheattrs |
| 32 | 28 | ||
| 33 | Andrew Jones (4): | 29 | target/arm/ptw.c | 11 ++++++----- |
| 34 | hw/arm/virt: add pmu interrupt state | 30 | 1 file changed, 6 insertions(+), 5 deletions(-) |
| 35 | target/arm/kvm: pmu: split init and set-irq stages | ||
| 36 | hw/arm/virt: allow pmu instantiation with userspace irqchip | ||
| 37 | target/arm/kvm: pmu: improve error handling | ||
| 38 | |||
| 39 | Peter Maydell (22): | ||
| 40 | target/arm: Use MMUAccessType enum rather than int | ||
| 41 | target/arm: Don't trap WFI/WFE for M profile | ||
| 42 | target/arm: Consolidate PMSA handling in get_phys_addr() | ||
| 43 | target/arm: Tighten up Thumb decode where new v8M insns will be | ||
| 44 | hw/intc/armv7m_nvic.c: Remove out of date comment | ||
| 45 | target/arm: Remove incorrect comment about MPU_CTRL | ||
| 46 | target/arm: Fix outdated comment about exception exit | ||
| 47 | target/arm: Define and use XPSR bit masks | ||
| 48 | target/arm: Don't store M profile PRIMASK and FAULTMASK in daif | ||
| 49 | target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR | ||
| 50 | target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR | ||
| 51 | target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed | ||
| 52 | target/arm: Create and use new function arm_v7m_is_handler_mode() | ||
| 53 | armv7m_nvic.h: Move from include/hw/arm to include/hw/intc | ||
| 54 | nvic: Implement "user accesses BusFault" SCS region behaviour | ||
| 55 | loader: Handle ELF files with overlapping zero-initialized data | ||
| 56 | loader: Ignore zero-sized ELF segments | ||
| 57 | memory.h: Move MemTxResult type to memattrs.h | ||
| 58 | cpu: Define new cpu_transaction_failed() hook | ||
| 59 | cputlb: Support generating CPU exceptions on memory transaction failures | ||
| 60 | target/arm: Factor out fault delivery code | ||
| 61 | target/arm: Allow deliver_fault() caller to specify EA bit | ||
| 62 | |||
| 63 | Philippe Mathieu-Daudé (1): | ||
| 64 | hw/arm: use defined type name instead of hard-coded string | ||
| 65 | |||
| 66 | Pranith Kumar (1): | ||
| 67 | arm_gicv3_kvm: Fix compile warning | ||
| 68 | |||
| 69 | Richard Henderson (1): | ||
| 70 | target/arm: Fix aa64 ldp register writeback | ||
| 71 | |||
| 72 | Thomas Huth (2): | ||
| 73 | hw/arm/aspeed_soc: Mark devices as user_creatable = false | ||
| 74 | hw/arm/digic: Mark device with user_creatable = false | ||
| 75 | |||
| 76 | include/exec/memattrs.h | 10 +++ | ||
| 77 | include/exec/memory.h | 10 --- | ||
| 78 | include/hw/arm/armv7m.h | 2 +- | ||
| 79 | include/hw/elf_ops.h | 72 +++++++++++++++++-- | ||
| 80 | include/hw/{arm => intc}/armv7m_nvic.h | 0 | ||
| 81 | include/hw/watchdog/wdt_aspeed.h | 2 + | ||
| 82 | include/qom/cpu.h | 22 ++++++ | ||
| 83 | softmmu_template.h | 4 +- | ||
| 84 | target/arm/cpu.h | 56 +++++++++++---- | ||
| 85 | target/arm/internals.h | 5 +- | ||
| 86 | target/arm/kvm_arm.h | 9 ++- | ||
| 87 | accel/tcg/cputlb.c | 32 ++++++++- | ||
| 88 | hw/arm/armv7m.c | 4 +- | ||
| 89 | hw/arm/aspeed_soc.c | 4 ++ | ||
| 90 | hw/arm/digic.c | 2 + | ||
| 91 | hw/arm/exynos4210.c | 4 +- | ||
| 92 | hw/arm/highbank.c | 11 +-- | ||
| 93 | hw/arm/realview.c | 6 +- | ||
| 94 | hw/arm/vexpress.c | 6 +- | ||
| 95 | hw/arm/virt.c | 12 +++- | ||
| 96 | hw/arm/xilinx_zynq.c | 14 ++-- | ||
| 97 | hw/intc/arm_gicv3_kvm.c | 2 +- | ||
| 98 | hw/intc/armv7m_nvic.c | 68 +++++++++++------- | ||
| 99 | hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++--- | ||
| 100 | target/arm/cpu.c | 7 +- | ||
| 101 | target/arm/helper.c | 124 ++++++++++++++++----------------- | ||
| 102 | target/arm/kvm.c | 6 +- | ||
| 103 | target/arm/kvm32.c | 8 ++- | ||
| 104 | target/arm/kvm64.c | 63 ++++++++++------- | ||
| 105 | target/arm/machine.c | 54 +++++++++++++- | ||
| 106 | target/arm/op_helper.c | 121 +++++++++++++++++--------------- | ||
| 107 | target/arm/translate-a64.c | 29 ++++---- | ||
| 108 | target/arm/translate.c | 106 +++++++++++++++++++++------- | ||
| 109 | 33 files changed, 677 insertions(+), 291 deletions(-) | ||
| 110 | rename include/hw/{arm => intc}/armv7m_nvic.h (100%) | ||
| 111 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Only perform the extract of GP during the stage1 walk. | ||
| 4 | |||
| 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 10 +++++----- | ||
| 12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 19 | result->f.attrs.secure = false; | ||
| 20 | } | ||
| 21 | |||
| 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (regime_is_stage2(mmu_idx)) { | ||
| 28 | result->cacheattrs.is_s2_format = true; | ||
| 29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 31 | assert(attrindx <= 7); | ||
| 32 | result->cacheattrs.is_s2_format = false; | ||
| 33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
| 34 | + | ||
| 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 38 | + } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | The guarded bit comes from the stage1 walk. | ||
| 4 | |||
| 5 | Fixes: Coverity CID 1507929 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 1 + | ||
| 12 | 1 file changed, 1 insertion(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, | ||
| 19 | |||
| 20 | assert(!s1.is_s2_format); | ||
| 21 | ret.is_s2_format = false; | ||
| 22 | + ret.guarded = s1.guarded; | ||
| 23 | |||
| 24 | if (s1.attrs == 0xf0) { | ||
| 25 | tagged = true; | ||
| 26 | -- | ||
| 27 | 2.34.1 | diff view generated by jsdifflib |