1 | Third time's the charm... | 1 | The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a: |
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2 | 2 | ||
3 | -- PMM | 3 | Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000) |
4 | 4 | ||
5 | The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278: | 5 | are available in the Git repository at: |
6 | 6 | ||
7 | Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100) | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328 |
8 | 8 | ||
9 | are available in the git repository at: | 9 | for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a: |
10 | 10 | ||
11 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2 | 11 | target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100) |
12 | |||
13 | for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c: | ||
14 | |||
15 | arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100) | ||
16 | 12 | ||
17 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
18 | target-arm: | 14 | target-arm queue: |
19 | * collection of M profile cleanups and minor bugfixes | 15 | * fix part of the "TCG-disabled builds are broken" issue |
20 | * loader: handle ELF files with overlapping zero-init data | ||
21 | * virt: allow PMU instantiation with userspace irqchip | ||
22 | * wdt_aspeed: Add support for the reset width register | ||
23 | * cpu: Define new cpu_transaction_failed() hook | ||
24 | * Mark some SoC devices as not user-creatable | ||
25 | * arm: Fix aa64 ldp register writeback | ||
26 | * arm_gicv3_kvm: Fix compile warning | ||
27 | 16 | ||
28 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
29 | Andrew Jeffery (2): | 18 | Philippe Mathieu-Daudé (1): |
30 | watchdog: wdt_aspeed: Add support for the reset width register | 19 | target/arm/gdbstub: Only advertise M-profile features if TCG available |
31 | aspeed_soc: Propagate silicon-rev to watchdog | ||
32 | 20 | ||
33 | Andrew Jones (4): | 21 | target/arm/gdbstub.c | 5 +++-- |
34 | hw/arm/virt: add pmu interrupt state | 22 | 1 file changed, 3 insertions(+), 2 deletions(-) |
35 | target/arm/kvm: pmu: split init and set-irq stages | ||
36 | hw/arm/virt: allow pmu instantiation with userspace irqchip | ||
37 | target/arm/kvm: pmu: improve error handling | ||
38 | 23 | ||
39 | Peter Maydell (22): | ||
40 | target/arm: Use MMUAccessType enum rather than int | ||
41 | target/arm: Don't trap WFI/WFE for M profile | ||
42 | target/arm: Consolidate PMSA handling in get_phys_addr() | ||
43 | target/arm: Tighten up Thumb decode where new v8M insns will be | ||
44 | hw/intc/armv7m_nvic.c: Remove out of date comment | ||
45 | target/arm: Remove incorrect comment about MPU_CTRL | ||
46 | target/arm: Fix outdated comment about exception exit | ||
47 | target/arm: Define and use XPSR bit masks | ||
48 | target/arm: Don't store M profile PRIMASK and FAULTMASK in daif | ||
49 | target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR | ||
50 | target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR | ||
51 | target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed | ||
52 | target/arm: Create and use new function arm_v7m_is_handler_mode() | ||
53 | armv7m_nvic.h: Move from include/hw/arm to include/hw/intc | ||
54 | nvic: Implement "user accesses BusFault" SCS region behaviour | ||
55 | loader: Handle ELF files with overlapping zero-initialized data | ||
56 | loader: Ignore zero-sized ELF segments | ||
57 | memory.h: Move MemTxResult type to memattrs.h | ||
58 | cpu: Define new cpu_transaction_failed() hook | ||
59 | cputlb: Support generating CPU exceptions on memory transaction failures | ||
60 | target/arm: Factor out fault delivery code | ||
61 | target/arm: Allow deliver_fault() caller to specify EA bit | ||
62 | |||
63 | Philippe Mathieu-Daudé (1): | ||
64 | hw/arm: use defined type name instead of hard-coded string | ||
65 | |||
66 | Pranith Kumar (1): | ||
67 | arm_gicv3_kvm: Fix compile warning | ||
68 | |||
69 | Richard Henderson (1): | ||
70 | target/arm: Fix aa64 ldp register writeback | ||
71 | |||
72 | Thomas Huth (2): | ||
73 | hw/arm/aspeed_soc: Mark devices as user_creatable = false | ||
74 | hw/arm/digic: Mark device with user_creatable = false | ||
75 | |||
76 | include/exec/memattrs.h | 10 +++ | ||
77 | include/exec/memory.h | 10 --- | ||
78 | include/hw/arm/armv7m.h | 2 +- | ||
79 | include/hw/elf_ops.h | 72 +++++++++++++++++-- | ||
80 | include/hw/{arm => intc}/armv7m_nvic.h | 0 | ||
81 | include/hw/watchdog/wdt_aspeed.h | 2 + | ||
82 | include/qom/cpu.h | 22 ++++++ | ||
83 | softmmu_template.h | 4 +- | ||
84 | target/arm/cpu.h | 56 +++++++++++---- | ||
85 | target/arm/internals.h | 5 +- | ||
86 | target/arm/kvm_arm.h | 9 ++- | ||
87 | accel/tcg/cputlb.c | 32 ++++++++- | ||
88 | hw/arm/armv7m.c | 4 +- | ||
89 | hw/arm/aspeed_soc.c | 4 ++ | ||
90 | hw/arm/digic.c | 2 + | ||
91 | hw/arm/exynos4210.c | 4 +- | ||
92 | hw/arm/highbank.c | 11 +-- | ||
93 | hw/arm/realview.c | 6 +- | ||
94 | hw/arm/vexpress.c | 6 +- | ||
95 | hw/arm/virt.c | 12 +++- | ||
96 | hw/arm/xilinx_zynq.c | 14 ++-- | ||
97 | hw/intc/arm_gicv3_kvm.c | 2 +- | ||
98 | hw/intc/armv7m_nvic.c | 68 +++++++++++------- | ||
99 | hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++--- | ||
100 | target/arm/cpu.c | 7 +- | ||
101 | target/arm/helper.c | 124 ++++++++++++++++----------------- | ||
102 | target/arm/kvm.c | 6 +- | ||
103 | target/arm/kvm32.c | 8 ++- | ||
104 | target/arm/kvm64.c | 63 ++++++++++------- | ||
105 | target/arm/machine.c | 54 +++++++++++++- | ||
106 | target/arm/op_helper.c | 121 +++++++++++++++++--------------- | ||
107 | target/arm/translate-a64.c | 29 ++++---- | ||
108 | target/arm/translate.c | 106 +++++++++++++++++++++------- | ||
109 | 33 files changed, 677 insertions(+), 291 deletions(-) | ||
110 | rename include/hw/{arm => intc}/armv7m_nvic.h (100%) | ||
111 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Cortex-M profile is only emulable from TCG accelerator. Restrict | ||
4 | the GDBstub features to its availability in order to avoid a link | ||
5 | error when TCG is not enabled: | ||
6 | |||
7 | Undefined symbols for architecture arm64: | ||
8 | "_arm_v7m_get_sp_ptr", referenced from: | ||
9 | _m_sysreg_get in target_arm_gdbstub.c.o | ||
10 | "_arm_v7m_mrs_control", referenced from: | ||
11 | _arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o | ||
12 | ld: symbol(s) not found for architecture arm64 | ||
13 | clang: error: linker command failed with exit code 1 (use -v to see invocation) | ||
14 | |||
15 | Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext") | ||
16 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
19 | Message-id: 20230322142902.69511-3-philmd@linaro.org | ||
20 | [PMM: add #include since I cherry-picked this patch from the series] | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | target/arm/gdbstub.c | 5 +++-- | ||
24 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
25 | |||
26 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/gdbstub.c | ||
29 | +++ b/target/arm/gdbstub.c | ||
30 | @@ -XXX,XX +XXX,XX @@ | ||
31 | #include "cpu.h" | ||
32 | #include "exec/gdbstub.h" | ||
33 | #include "gdbstub/helpers.h" | ||
34 | +#include "sysemu/tcg.h" | ||
35 | #include "internals.h" | ||
36 | #include "cpregs.h" | ||
37 | |||
38 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
39 | 2, "arm-vfp-sysregs.xml", 0); | ||
40 | } | ||
41 | } | ||
42 | - if (cpu_isar_feature(aa32_mve, cpu)) { | ||
43 | + if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) { | ||
44 | gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, | ||
45 | 1, "arm-m-profile-mve.xml", 0); | ||
46 | } | ||
47 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
48 | arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), | ||
49 | "system-registers.xml", 0); | ||
50 | |||
51 | - if (arm_feature(env, ARM_FEATURE_M)) { | ||
52 | + if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { | ||
53 | gdb_register_coprocessor(cs, | ||
54 | arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, | ||
55 | arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), | ||
56 | -- | ||
57 | 2.34.1 | ||
58 | |||
59 | diff view generated by jsdifflib |