[Qemu-devel] [PULL 00/33] target-arm queue
[PULL 0/3] target-arm queue
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Third time's the charm...
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
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-- PMM
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-- PMM
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The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c:
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100)
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm:
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target-arm queue:
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* collection of M profile cleanups and minor bugfixes
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* Fix KVM SVE ID register probe code
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* loader: handle ELF files with overlapping zero-init data
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* virt: allow PMU instantiation with userspace irqchip
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* wdt_aspeed: Add support for the reset width register
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* cpu: Define new cpu_transaction_failed() hook
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* Mark some SoC devices as not user-creatable
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* arm: Fix aa64 ldp register writeback
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* arm_gicv3_kvm: Fix compile warning
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jeffery (2):
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Richard Henderson (3):
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watchdog: wdt_aspeed: Add support for the reset width register
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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aspeed_soc: Propagate silicon-rev to watchdog
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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target/arm: Move sve probe inside kvm >= 4.15 branch
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Andrew Jones (4):
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target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
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hw/arm/virt: add pmu interrupt state
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1 file changed, 22 insertions(+), 23 deletions(-)
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target/arm/kvm: pmu: split init and set-irq stages
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hw/arm/virt: allow pmu instantiation with userspace irqchip
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target/arm/kvm: pmu: improve error handling
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Peter Maydell (22):
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target/arm: Use MMUAccessType enum rather than int
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target/arm: Don't trap WFI/WFE for M profile
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target/arm: Consolidate PMSA handling in get_phys_addr()
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target/arm: Tighten up Thumb decode where new v8M insns will be
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hw/intc/armv7m_nvic.c: Remove out of date comment
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target/arm: Remove incorrect comment about MPU_CTRL
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target/arm: Fix outdated comment about exception exit
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target/arm: Define and use XPSR bit masks
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target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
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target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
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target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
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target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
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target/arm: Create and use new function arm_v7m_is_handler_mode()
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armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
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nvic: Implement "user accesses BusFault" SCS region behaviour
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loader: Handle ELF files with overlapping zero-initialized data
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loader: Ignore zero-sized ELF segments
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memory.h: Move MemTxResult type to memattrs.h
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cpu: Define new cpu_transaction_failed() hook
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cputlb: Support generating CPU exceptions on memory transaction failures
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target/arm: Factor out fault delivery code
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target/arm: Allow deliver_fault() caller to specify EA bit
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Philippe Mathieu-Daudé (1):
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hw/arm: use defined type name instead of hard-coded string
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Pranith Kumar (1):
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arm_gicv3_kvm: Fix compile warning
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Richard Henderson (1):
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target/arm: Fix aa64 ldp register writeback
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Thomas Huth (2):
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hw/arm/aspeed_soc: Mark devices as user_creatable = false
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hw/arm/digic: Mark device with user_creatable = false
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include/exec/memattrs.h | 10 +++
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include/exec/memory.h | 10 ---
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include/hw/arm/armv7m.h | 2 +-
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include/hw/elf_ops.h | 72 +++++++++++++++++--
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include/hw/{arm => intc}/armv7m_nvic.h | 0
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include/hw/watchdog/wdt_aspeed.h | 2 +
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include/qom/cpu.h | 22 ++++++
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softmmu_template.h | 4 +-
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target/arm/cpu.h | 56 +++++++++++----
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target/arm/internals.h | 5 +-
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target/arm/kvm_arm.h | 9 ++-
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accel/tcg/cputlb.c | 32 ++++++++-
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hw/arm/armv7m.c | 4 +-
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hw/arm/aspeed_soc.c | 4 ++
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hw/arm/digic.c | 2 +
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hw/arm/exynos4210.c | 4 +-
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hw/arm/highbank.c | 11 +--
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hw/arm/realview.c | 6 +-
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hw/arm/vexpress.c | 6 +-
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hw/arm/virt.c | 12 +++-
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hw/arm/xilinx_zynq.c | 14 ++--
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hw/intc/arm_gicv3_kvm.c | 2 +-
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hw/intc/armv7m_nvic.c | 68 +++++++++++-------
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hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++---
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target/arm/cpu.c | 7 +-
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target/arm/helper.c | 124 ++++++++++++++++-----------------
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target/arm/kvm.c | 6 +-
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target/arm/kvm32.c | 8 ++-
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target/arm/kvm64.c | 63 ++++++++++-------
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target/arm/machine.c | 54 +++++++++++++-
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target/arm/op_helper.c | 121 +++++++++++++++++---------------
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target/arm/translate-a64.c | 29 ++++----
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target/arm/translate.c | 106 +++++++++++++++++++++-------
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33 files changed, 677 insertions(+), 291 deletions(-)
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rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
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diff view generated by jsdifflib
New patch
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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From: Richard Henderson <richard.henderson@linaro.org>
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Indication for support for SVE will not depend on whether we
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perform the query on the main kvm_state or the temp vcpu.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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+ sve_supported = kvm_arm_sve_supported();
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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--
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2.25.1
diff view generated by jsdifflib
New patch
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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From: Richard Henderson <richard.henderson@linaro.org>
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 27 +++++++++++++--------------
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1 file changed, 13 insertions(+), 14 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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- * Ask for Pointer Authentication if supported. We can't play the
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- * SVE trick of synthesising the ID reg as KVM won't tell us
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- * whether we have the architected or IMPDEF version of PAuth, so
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- * we have to use the actual ID regs.
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
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+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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+ /*
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+ * Ask for Pointer Authentication if supported, so that we get
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+ * the unsanitized field values for AA64ISAR1_EL1.
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*/
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if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.id_aa64pfr0;
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.id_aa64pfr0 = t;
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-
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, so we only read it here, rather than together with all
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- * the other ID registers earlier.
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.25.1
diff view generated by jsdifflib
New patch
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
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From: Richard Henderson <richard.henderson@linaro.org>
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The test for the IF block indicates no ID registers are exposed, much
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less host support for SVE. Move the SVE probe into the ELSE block.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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- }
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- if (sve_supported) {
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- /*
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- * There is a range of kernels between kernel commit 73433762fcae
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- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, which resulted in an error rather than RAZ.
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- * So only read the register if we set KVM_ARM_VCPU_SVE above.
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- */
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- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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- ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ if (sve_supported) {
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+ /*
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+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
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+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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+ * enabled SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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+ */
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+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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+ ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ }
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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