1
Third time's the charm...
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
2
ethernet device failed 'make check' on big-endian hosts.
2
3
3
-- PMM
4
-- PMM
4
5
5
The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
6
7
7
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
8
9
9
are available in the git repository at:
10
are available in the Git repository at:
10
11
11
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
12
13
13
for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c:
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
14
15
15
arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100)
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
16
17
17
----------------------------------------------------------------
18
----------------------------------------------------------------
18
target-arm:
19
target-arm queue:
19
* collection of M profile cleanups and minor bugfixes
20
* Correctly initialize MDCR_EL2.HPMN
20
* loader: handle ELF files with overlapping zero-init data
21
* versal: Use nr_apu_cpus in favor of hard coding 2
21
* virt: allow PMU instantiation with userspace irqchip
22
* accel/tcg: Add URL of clang bug to comment about our workaround
22
* wdt_aspeed: Add support for the reset width register
23
* Add support for FEAT_DIT, Data Independent Timing
23
* cpu: Define new cpu_transaction_failed() hook
24
* Remove GPIO from unimplemented NPCM7XX
24
* Mark some SoC devices as not user-creatable
25
* Fix SCR RES1 handling
25
* arm: Fix aa64 ldp register writeback
26
* Don't migrate CPUARMState.features
26
* arm_gicv3_kvm: Fix compile warning
27
27
28
----------------------------------------------------------------
28
----------------------------------------------------------------
29
Andrew Jeffery (2):
29
Aaron Lindsay (1):
30
watchdog: wdt_aspeed: Add support for the reset width register
30
target/arm: Don't migrate CPUARMState.features
31
aspeed_soc: Propagate silicon-rev to watchdog
32
31
33
Andrew Jones (4):
32
Daniel Müller (1):
34
hw/arm/virt: add pmu interrupt state
33
target/arm: Correctly initialize MDCR_EL2.HPMN
35
target/arm/kvm: pmu: split init and set-irq stages
36
hw/arm/virt: allow pmu instantiation with userspace irqchip
37
target/arm/kvm: pmu: improve error handling
38
34
39
Peter Maydell (22):
35
Edgar E. Iglesias (1):
40
target/arm: Use MMUAccessType enum rather than int
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
41
target/arm: Don't trap WFI/WFE for M profile
42
target/arm: Consolidate PMSA handling in get_phys_addr()
43
target/arm: Tighten up Thumb decode where new v8M insns will be
44
hw/intc/armv7m_nvic.c: Remove out of date comment
45
target/arm: Remove incorrect comment about MPU_CTRL
46
target/arm: Fix outdated comment about exception exit
47
target/arm: Define and use XPSR bit masks
48
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
49
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
50
target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
51
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
52
target/arm: Create and use new function arm_v7m_is_handler_mode()
53
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
54
nvic: Implement "user accesses BusFault" SCS region behaviour
55
loader: Handle ELF files with overlapping zero-initialized data
56
loader: Ignore zero-sized ELF segments
57
memory.h: Move MemTxResult type to memattrs.h
58
cpu: Define new cpu_transaction_failed() hook
59
cputlb: Support generating CPU exceptions on memory transaction failures
60
target/arm: Factor out fault delivery code
61
target/arm: Allow deliver_fault() caller to specify EA bit
62
37
63
Philippe Mathieu-Daudé (1):
38
Hao Wu (1):
64
hw/arm: use defined type name instead of hard-coded string
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
65
40
66
Pranith Kumar (1):
41
Mike Nawrocki (1):
67
arm_gicv3_kvm: Fix compile warning
42
target/arm: Fix SCR RES1 handling
68
43
69
Richard Henderson (1):
44
Peter Maydell (2):
70
target/arm: Fix aa64 ldp register writeback
45
arm: Update infocenter.arm.com URLs
46
accel/tcg: Add URL of clang bug to comment about our workaround
71
47
72
Thomas Huth (2):
48
Rebecca Cran (4):
73
hw/arm/aspeed_soc: Mark devices as user_creatable = false
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
74
hw/arm/digic: Mark device with user_creatable = false
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
75
53
76
include/exec/memattrs.h | 10 +++
54
include/hw/dma/pl080.h | 7 ++--
77
include/exec/memory.h | 10 ---
55
include/hw/misc/arm_integrator_debug.h | 2 +-
78
include/hw/arm/armv7m.h | 2 +-
56
include/hw/ssi/pl022.h | 5 ++-
79
include/hw/elf_ops.h | 72 +++++++++++++++++--
57
target/arm/cpu.h | 17 ++++++++
80
include/hw/{arm => intc}/armv7m_nvic.h | 0
58
target/arm/internals.h | 6 +++
81
include/hw/watchdog/wdt_aspeed.h | 2 +
59
accel/tcg/cpu-exec.c | 25 +++++++++---
82
include/qom/cpu.h | 22 ++++++
60
hw/arm/aspeed_ast2600.c | 2 +-
83
softmmu_template.h | 4 +-
61
hw/arm/musca.c | 4 +-
84
target/arm/cpu.h | 56 +++++++++++----
62
hw/arm/npcm7xx.c | 8 ----
85
target/arm/internals.h | 5 +-
63
hw/arm/xlnx-versal.c | 4 +-
86
target/arm/kvm_arm.h | 9 ++-
64
hw/misc/arm_integrator_debug.c | 2 +-
87
accel/tcg/cputlb.c | 32 ++++++++-
65
hw/timer/arm_timer.c | 7 ++--
88
hw/arm/armv7m.c | 4 +-
66
target/arm/cpu.c | 4 ++
89
hw/arm/aspeed_soc.c | 4 ++
67
target/arm/cpu64.c | 5 +++
90
hw/arm/digic.c | 2 +
68
target/arm/helper-a64.c | 27 +++++++++++--
91
hw/arm/exynos4210.c | 4 +-
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
92
hw/arm/highbank.c | 11 +--
70
target/arm/machine.c | 2 +-
93
hw/arm/realview.c | 6 +-
71
target/arm/op_helper.c | 9 +----
94
hw/arm/vexpress.c | 6 +-
72
target/arm/translate-a64.c | 12 ++++++
95
hw/arm/virt.c | 12 +++-
73
19 files changed, 164 insertions(+), 55 deletions(-)
96
hw/arm/xilinx_zynq.c | 14 ++--
97
hw/intc/arm_gicv3_kvm.c | 2 +-
98
hw/intc/armv7m_nvic.c | 68 +++++++++++-------
99
hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++---
100
target/arm/cpu.c | 7 +-
101
target/arm/helper.c | 124 ++++++++++++++++-----------------
102
target/arm/kvm.c | 6 +-
103
target/arm/kvm32.c | 8 ++-
104
target/arm/kvm64.c | 63 ++++++++++-------
105
target/arm/machine.c | 54 +++++++++++++-
106
target/arm/op_helper.c | 121 +++++++++++++++++---------------
107
target/arm/translate-a64.c | 29 ++++----
108
target/arm/translate.c | 106 +++++++++++++++++++++-------
109
33 files changed, 677 insertions(+), 291 deletions(-)
110
rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
111
74
diff view generated by jsdifflib