[Qemu-devel] [PULL 00/33] target-arm queue
[PULL v2 00/29] target-arm queue
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Third time's the charm...
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v2: drop pvpanic-pci patches.
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-- PMM
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
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are available in the Git repository at:
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are available in the git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c:
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm:
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target-arm queue:
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* collection of M profile cleanups and minor bugfixes
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* Implement IMPDEF pauth algorithm
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* loader: handle ELF files with overlapping zero-init data
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* Support ARMv8.4-SEL2
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* virt: allow PMU instantiation with userspace irqchip
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* wdt_aspeed: Add support for the reset width register
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* cpu: Define new cpu_transaction_failed() hook
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* Mark some SoC devices as not user-creatable
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* docs: Build and install all the docs in a single manual
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* arm: Fix aa64 ldp register writeback
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* arm_gicv3_kvm: Fix compile warning
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jeffery (2):
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Gan Qixin (1):
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watchdog: wdt_aspeed: Add support for the reset width register
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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aspeed_soc: Propagate silicon-rev to watchdog
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Andrew Jones (4):
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Peter Maydell (1):
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hw/arm/virt: add pmu interrupt state
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docs: Build and install all the docs in a single manual
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target/arm/kvm: pmu: split init and set-irq stages
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hw/arm/virt: allow pmu instantiation with userspace irqchip
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target/arm/kvm: pmu: improve error handling
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Peter Maydell (22):
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target/arm: Use MMUAccessType enum rather than int
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target/arm: Don't trap WFI/WFE for M profile
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target/arm: Consolidate PMSA handling in get_phys_addr()
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target/arm: Tighten up Thumb decode where new v8M insns will be
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hw/intc/armv7m_nvic.c: Remove out of date comment
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target/arm: Remove incorrect comment about MPU_CTRL
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target/arm: Fix outdated comment about exception exit
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target/arm: Define and use XPSR bit masks
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target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
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target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
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target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
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target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
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target/arm: Create and use new function arm_v7m_is_handler_mode()
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armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
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nvic: Implement "user accesses BusFault" SCS region behaviour
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loader: Handle ELF files with overlapping zero-initialized data
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loader: Ignore zero-sized ELF segments
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memory.h: Move MemTxResult type to memattrs.h
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cpu: Define new cpu_transaction_failed() hook
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cputlb: Support generating CPU exceptions on memory transaction failures
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target/arm: Factor out fault delivery code
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target/arm: Allow deliver_fault() caller to specify EA bit
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Philippe Mathieu-Daudé (1):
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Philippe Mathieu-Daudé (1):
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hw/arm: use defined type name instead of hard-coded string
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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Pranith Kumar (1):
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Richard Henderson (7):
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arm_gicv3_kvm: Fix compile warning
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target/arm: Implement an IMPDEF pauth algorithm
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target/arm: Add cpu properties to control pauth
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target/arm: Use object_property_add_bool for "sve" property
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target/arm: Introduce PREDDESC field definitions
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target/arm: Update PFIRST, PNEXT for pred_desc
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm: Update REV, PUNPK for pred_desc
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Richard Henderson (1):
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Rémi Denis-Courmont (19):
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target/arm: Fix aa64 ldp register writeback
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target/arm: remove redundant tests
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target/arm: add arm_is_el2_enabled() helper
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target/arm: use arm_is_el2_enabled() where applicable
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target/arm: use arm_hcr_el2_eff() where applicable
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target/arm: factor MDCR_EL2 common handling
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target/arm: Define isar_feature function to test for presence of SEL2
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target/arm: add 64-bit S-EL2 to EL exception table
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target/arm: add MMU stage 1 for Secure EL2
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target/arm: add ARMv8.4-SEL2 system registers
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target/arm: handle VMID change in secure state
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target/arm: do S1_ptw_translate() before address space lookup
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target/arm: translate NS bit in page-walks
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target/arm: generalize 2-stage page-walk condition
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target/arm: secure stage 2 translation regime
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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target/arm: revector to run-time pick target EL
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target/arm: Implement SCR_EL2.EEL2
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target/arm: enable Secure EL2 in max CPU
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target/arm: refactor vae1_tlbmask()
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Thomas Huth (2):
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docs/conf.py | 46 ++++-
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hw/arm/aspeed_soc: Mark devices as user_creatable = false
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docs/devel/conf.py | 15 --
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hw/arm/digic: Mark device with user_creatable = false
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docs/index.html.in | 17 --
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docs/interop/conf.py | 28 ---
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docs/meson.build | 64 +++---
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docs/specs/conf.py | 16 --
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docs/system/arm/cpu-features.rst | 21 ++
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docs/system/conf.py | 28 ---
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docs/tools/conf.py | 37 ----
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docs/user/conf.py | 15 --
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include/qemu/xxhash.h | 98 +++++++++
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target/arm/cpu-param.h | 2 +-
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target/arm/cpu.h | 107 ++++++++--
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target/arm/internals.h | 45 +++++
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target/arm/cpu.c | 23 ++-
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target/arm/cpu64.c | 65 ++++--
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target/arm/helper-a64.c | 8 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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target/arm/m_helper.c | 2 +-
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target/arm/monitor.c | 1 +
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target/arm/op_helper.c | 4 +-
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target/arm/pauth_helper.c | 27 ++-
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target/arm/sve_helper.c | 33 ++--
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target/arm/tlb_helper.c | 3 +
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target/arm/translate-a64.c | 4 +
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target/arm/translate-sve.c | 31 ++-
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target/arm/translate.c | 36 +++-
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tests/qtest/arm-cpu-features.c | 13 ++
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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include/exec/memattrs.h | 10 +++
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include/exec/memory.h | 10 ---
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include/hw/arm/armv7m.h | 2 +-
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include/hw/elf_ops.h | 72 +++++++++++++++++--
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include/hw/{arm => intc}/armv7m_nvic.h | 0
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include/hw/watchdog/wdt_aspeed.h | 2 +
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include/qom/cpu.h | 22 ++++++
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softmmu_template.h | 4 +-
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target/arm/cpu.h | 56 +++++++++++----
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target/arm/internals.h | 5 +-
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target/arm/kvm_arm.h | 9 ++-
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accel/tcg/cputlb.c | 32 ++++++++-
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hw/arm/armv7m.c | 4 +-
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hw/arm/aspeed_soc.c | 4 ++
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hw/arm/digic.c | 2 +
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hw/arm/exynos4210.c | 4 +-
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hw/arm/highbank.c | 11 +--
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hw/arm/realview.c | 6 +-
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hw/arm/vexpress.c | 6 +-
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hw/arm/virt.c | 12 +++-
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hw/arm/xilinx_zynq.c | 14 ++--
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hw/intc/arm_gicv3_kvm.c | 2 +-
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hw/intc/armv7m_nvic.c | 68 +++++++++++-------
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hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++---
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target/arm/cpu.c | 7 +-
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target/arm/helper.c | 124 ++++++++++++++++-----------------
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target/arm/kvm.c | 6 +-
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target/arm/kvm32.c | 8 ++-
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target/arm/kvm64.c | 63 ++++++++++-------
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target/arm/machine.c | 54 +++++++++++++-
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target/arm/op_helper.c | 121 +++++++++++++++++---------------
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target/arm/translate-a64.c | 29 ++++----
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target/arm/translate.c | 106 +++++++++++++++++++++-------
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33 files changed, 677 insertions(+), 291 deletions(-)
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rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
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diff view generated by jsdifflib

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