[Qemu-devel] [PULL 00/33] target-arm queue
[Qemu-devel] [PULL 00/17] target-arm queue
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Third time's the charm...
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v2: dropped a couple of cadence_gem changes to ID regs that
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caused new clang sanitizer warnings.
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-- PMM
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-- PMM
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The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c:
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100)
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm:
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target-arm queue:
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* collection of M profile cleanups and minor bugfixes
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* loader: handle ELF files with overlapping zero-init data
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* virt: allow PMU instantiation with userspace irqchip
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* target/arm: Define fields of ISAR registers
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* wdt_aspeed: Add support for the reset width register
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* target/arm: Align cortex-r5 id_isar0
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* cpu: Define new cpu_transaction_failed() hook
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* target/arm: Fix cortex-a7 id_isar0
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* Mark some SoC devices as not user-creatable
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* net/cadence_gem: Fix various bugs, add support for new
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* arm: Fix aa64 ldp register writeback
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features that will be used by the Xilinx Versal board
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* arm_gicv3_kvm: Fix compile warning
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jeffery (2):
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Aaron Lindsay (2):
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watchdog: wdt_aspeed: Add support for the reset width register
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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aspeed_soc: Propagate silicon-rev to watchdog
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target/arm: Mask PMOVSR writes based on supported counters
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Andrew Jones (4):
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Edgar E. Iglesias (8):
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hw/arm/virt: add pmu interrupt state
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net: cadence_gem: Disable TSU feature bit
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target/arm/kvm: pmu: split init and set-irq stages
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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hw/arm/virt: allow pmu instantiation with userspace irqchip
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net: cadence_gem: Add macro with max number of descriptor words
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target/arm/kvm: pmu: improve error handling
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Peter Maydell (22):
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Jerome Forissier (1):
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target/arm: Use MMUAccessType enum rather than int
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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target/arm: Don't trap WFI/WFE for M profile
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target/arm: Consolidate PMSA handling in get_phys_addr()
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target/arm: Tighten up Thumb decode where new v8M insns will be
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hw/intc/armv7m_nvic.c: Remove out of date comment
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target/arm: Remove incorrect comment about MPU_CTRL
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target/arm: Fix outdated comment about exception exit
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target/arm: Define and use XPSR bit masks
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target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
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target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
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target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
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target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
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target/arm: Create and use new function arm_v7m_is_handler_mode()
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armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
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nvic: Implement "user accesses BusFault" SCS region behaviour
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loader: Handle ELF files with overlapping zero-initialized data
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loader: Ignore zero-sized ELF segments
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memory.h: Move MemTxResult type to memattrs.h
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cpu: Define new cpu_transaction_failed() hook
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cputlb: Support generating CPU exceptions on memory transaction failures
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target/arm: Factor out fault delivery code
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target/arm: Allow deliver_fault() caller to specify EA bit
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Philippe Mathieu-Daudé (1):
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Peter Maydell (2):
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hw/arm: use defined type name instead of hard-coded string
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Pranith Kumar (1):
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Richard Henderson (4):
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arm_gicv3_kvm: Fix compile warning
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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Richard Henderson (1):
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include/hw/net/cadence_gem.h | 7 +-
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target/arm: Fix aa64 ldp register writeback
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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Thomas Huth (2):
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hw/arm/aspeed_soc: Mark devices as user_creatable = false
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hw/arm/digic: Mark device with user_creatable = false
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include/exec/memattrs.h | 10 +++
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include/exec/memory.h | 10 ---
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include/hw/arm/armv7m.h | 2 +-
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include/hw/elf_ops.h | 72 +++++++++++++++++--
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include/hw/{arm => intc}/armv7m_nvic.h | 0
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include/hw/watchdog/wdt_aspeed.h | 2 +
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include/qom/cpu.h | 22 ++++++
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softmmu_template.h | 4 +-
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target/arm/cpu.h | 56 +++++++++++----
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target/arm/internals.h | 5 +-
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target/arm/kvm_arm.h | 9 ++-
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accel/tcg/cputlb.c | 32 ++++++++-
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hw/arm/armv7m.c | 4 +-
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hw/arm/aspeed_soc.c | 4 ++
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hw/arm/digic.c | 2 +
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hw/arm/exynos4210.c | 4 +-
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hw/arm/highbank.c | 11 +--
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hw/arm/realview.c | 6 +-
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hw/arm/vexpress.c | 6 +-
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hw/arm/virt.c | 12 +++-
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hw/arm/xilinx_zynq.c | 14 ++--
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hw/intc/arm_gicv3_kvm.c | 2 +-
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hw/intc/armv7m_nvic.c | 68 +++++++++++-------
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hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++---
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target/arm/cpu.c | 7 +-
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target/arm/helper.c | 124 ++++++++++++++++-----------------
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target/arm/kvm.c | 6 +-
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target/arm/kvm32.c | 8 ++-
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target/arm/kvm64.c | 63 ++++++++++-------
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target/arm/machine.c | 54 +++++++++++++-
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target/arm/op_helper.c | 121 +++++++++++++++++---------------
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target/arm/translate-a64.c | 29 ++++----
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target/arm/translate.c | 106 +++++++++++++++++++++-------
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33 files changed, 677 insertions(+), 291 deletions(-)
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rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
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diff view generated by jsdifflib

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