[Qemu-devel] [PULL 00/36] target-arm queue
[PULL 0/2] target-arm queue
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Try #2, with the compile failure in kvm32.c fixed
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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(trivial change, not resending patches)
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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for you to fetch changes up to 0b8095ec9e924dc00636ab2069d88dec6592a75d:
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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arm_gicv3_kvm: Fix compile warning (2017-09-04 15:21:56 +0100)
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm:
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target-arm: Fix bug where we weren't initializing
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* collection of M profile cleanups and minor bugfixes
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guarded bit state when combining S1/S2 attrs
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* loader: handle ELF files with overlapping zero-init data
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* virt: allow PMU instantiation with userspace irqchip
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* wdt_aspeed: Add support for the reset width register
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* cpu: Define new cpu_transaction_failed() hook
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* arm: Support generating CPU exceptions on memory
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transaction failures (bus faults)
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* Mark some SoC devices as not user-creatable
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* arm: Fix aa64 ldp register writeback
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* arm_gicv3_kvm: Fix compile warning
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jeffery (2):
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Richard Henderson (2):
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watchdog: wdt_aspeed: Add support for the reset width register
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target/arm: PTE bit GP only applies to stage1
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aspeed_soc: Propagate silicon-rev to watchdog
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target/arm: Copy guarded bit in combine_cacheattrs
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Andrew Jones (4):
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target/arm/ptw.c | 11 ++++++-----
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hw/arm/virt: add pmu interrupt state
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1 file changed, 6 insertions(+), 5 deletions(-)
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target/arm/kvm: pmu: split init and set-irq stages
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hw/arm/virt: allow pmu instantiation with userspace irqchip
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target/arm/kvm: pmu: improve error handling
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Peter Maydell (25):
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target/arm: Use MMUAccessType enum rather than int
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target/arm: Don't trap WFI/WFE for M profile
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target/arm: Consolidate PMSA handling in get_phys_addr()
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target/arm: Tighten up Thumb decode where new v8M insns will be
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hw/intc/armv7m_nvic.c: Remove out of date comment
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target/arm: Remove incorrect comment about MPU_CTRL
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target/arm: Fix outdated comment about exception exit
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target/arm: Define and use XPSR bit masks
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target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
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target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
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target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
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target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
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target/arm: Create and use new function arm_v7m_is_handler_mode()
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armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
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nvic: Implement "user accesses BusFault" SCS region behaviour
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loader: Handle ELF files with overlapping zero-initialized data
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loader: Ignore zero-sized ELF segments
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memory.h: Move MemTxResult type to memattrs.h
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cpu: Define new cpu_transaction_failed() hook
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cputlb: Support generating CPU exceptions on memory transaction failures
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boards.h: Define new flag ignore_memory_transaction_failures
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hw/arm: Set ignore_memory_transaction_failures for most ARM boards
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target/arm: Factor out fault delivery code
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target/arm: Allow deliver_fault() caller to specify EA bit
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target/arm: Implement new do_transaction_failed hook
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Philippe Mathieu-Daudé (1):
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hw/arm: use defined type name instead of hard-coded string
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Pranith Kumar (1):
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arm_gicv3_kvm: Fix compile warning
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Richard Henderson (1):
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target/arm: Fix aa64 ldp register writeback
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Thomas Huth (2):
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hw/arm/aspeed_soc: Mark devices as user_creatable = false
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hw/arm/digic: Mark device with user_creatable = false
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include/exec/memattrs.h | 10 +++
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include/exec/memory.h | 10 ---
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include/hw/arm/armv7m.h | 2 +-
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include/hw/boards.h | 11 +++
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include/hw/elf_ops.h | 72 +++++++++++++--
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include/hw/{arm => intc}/armv7m_nvic.h | 0
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include/hw/watchdog/wdt_aspeed.h | 2 +
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include/qom/cpu.h | 27 ++++++
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softmmu_template.h | 4 +-
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target/arm/cpu.h | 56 +++++++++---
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target/arm/internals.h | 15 +++-
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target/arm/kvm_arm.h | 9 +-
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accel/tcg/cputlb.c | 32 ++++++-
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hw/arm/armv7m.c | 4 +-
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hw/arm/aspeed.c | 3 +
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hw/arm/aspeed_soc.c | 4 +
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hw/arm/collie.c | 1 +
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hw/arm/cubieboard.c | 1 +
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hw/arm/digic.c | 2 +
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hw/arm/digic_boards.c | 1 +
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hw/arm/exynos4210.c | 4 +-
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hw/arm/exynos4_boards.c | 2 +
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hw/arm/gumstix.c | 2 +
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hw/arm/highbank.c | 13 ++-
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hw/arm/imx25_pdk.c | 1 +
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hw/arm/integratorcp.c | 1 +
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hw/arm/kzm.c | 1 +
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hw/arm/mainstone.c | 1 +
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hw/arm/musicpal.c | 1 +
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hw/arm/netduino2.c | 1 +
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hw/arm/nseries.c | 2 +
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hw/arm/omap_sx1.c | 2 +
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hw/arm/palm.c | 1 +
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hw/arm/raspi.c | 1 +
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hw/arm/realview.c | 10 ++-
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hw/arm/sabrelite.c | 1 +
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hw/arm/spitz.c | 4 +
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hw/arm/stellaris.c | 2 +
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hw/arm/tosa.c | 1 +
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hw/arm/versatilepb.c | 2 +
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hw/arm/vexpress.c | 7 +-
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hw/arm/virt.c | 12 ++-
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hw/arm/xilinx_zynq.c | 15 ++--
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hw/arm/xlnx-ep108.c | 2 +
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hw/arm/z2.c | 1 +
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hw/intc/arm_gicv3_kvm.c | 2 +-
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hw/intc/armv7m_nvic.c | 68 +++++++++-----
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hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++---
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qom/cpu.c | 7 ++
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target/arm/cpu.c | 8 +-
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target/arm/helper.c | 124 ++++++++++++-------------
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target/arm/kvm.c | 6 +-
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target/arm/kvm32.c | 8 +-
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target/arm/kvm64.c | 63 +++++++------
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target/arm/machine.c | 54 ++++++++++-
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target/arm/op_helper.c | 160 ++++++++++++++++++++++-----------
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target/arm/translate-a64.c | 29 +++---
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target/arm/translate.c | 106 ++++++++++++++++------
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58 files changed, 795 insertions(+), 289 deletions(-)
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rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
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diff view generated by jsdifflib
New patch
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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