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Try #2, with the compile failure in kvm32.c fixed
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The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
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(trivial change, not resending patches)
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thanks
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Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
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-- PMM
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The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
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are available in the Git repository at:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
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are available in the git repository at:
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for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-1
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target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
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for you to fetch changes up to 0b8095ec9e924dc00636ab2069d88dec6592a75d:
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arm_gicv3_kvm: Fix compile warning (2017-09-04 15:21:56 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm:
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target-arm queue:
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* collection of M profile cleanups and minor bugfixes
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* fix part of the "TCG-disabled builds are broken" issue
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* loader: handle ELF files with overlapping zero-init data
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* virt: allow PMU instantiation with userspace irqchip
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* wdt_aspeed: Add support for the reset width register
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* cpu: Define new cpu_transaction_failed() hook
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* arm: Support generating CPU exceptions on memory
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transaction failures (bus faults)
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* Mark some SoC devices as not user-creatable
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* arm: Fix aa64 ldp register writeback
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* arm_gicv3_kvm: Fix compile warning
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jeffery (2):
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Philippe Mathieu-Daudé (1):
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watchdog: wdt_aspeed: Add support for the reset width register
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target/arm/gdbstub: Only advertise M-profile features if TCG available
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aspeed_soc: Propagate silicon-rev to watchdog
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Andrew Jones (4):
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target/arm/gdbstub.c | 5 +++--
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hw/arm/virt: add pmu interrupt state
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1 file changed, 3 insertions(+), 2 deletions(-)
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target/arm/kvm: pmu: split init and set-irq stages
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hw/arm/virt: allow pmu instantiation with userspace irqchip
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target/arm/kvm: pmu: improve error handling
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Peter Maydell (25):
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target/arm: Use MMUAccessType enum rather than int
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target/arm: Don't trap WFI/WFE for M profile
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target/arm: Consolidate PMSA handling in get_phys_addr()
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target/arm: Tighten up Thumb decode where new v8M insns will be
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hw/intc/armv7m_nvic.c: Remove out of date comment
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target/arm: Remove incorrect comment about MPU_CTRL
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target/arm: Fix outdated comment about exception exit
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target/arm: Define and use XPSR bit masks
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target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
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target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
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target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
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target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
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target/arm: Create and use new function arm_v7m_is_handler_mode()
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armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
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nvic: Implement "user accesses BusFault" SCS region behaviour
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loader: Handle ELF files with overlapping zero-initialized data
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loader: Ignore zero-sized ELF segments
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memory.h: Move MemTxResult type to memattrs.h
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cpu: Define new cpu_transaction_failed() hook
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cputlb: Support generating CPU exceptions on memory transaction failures
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boards.h: Define new flag ignore_memory_transaction_failures
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hw/arm: Set ignore_memory_transaction_failures for most ARM boards
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target/arm: Factor out fault delivery code
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target/arm: Allow deliver_fault() caller to specify EA bit
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target/arm: Implement new do_transaction_failed hook
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Philippe Mathieu-Daudé (1):
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hw/arm: use defined type name instead of hard-coded string
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Pranith Kumar (1):
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arm_gicv3_kvm: Fix compile warning
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Richard Henderson (1):
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target/arm: Fix aa64 ldp register writeback
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Thomas Huth (2):
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hw/arm/aspeed_soc: Mark devices as user_creatable = false
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hw/arm/digic: Mark device with user_creatable = false
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include/exec/memattrs.h | 10 +++
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include/exec/memory.h | 10 ---
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include/hw/arm/armv7m.h | 2 +-
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include/hw/boards.h | 11 +++
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include/hw/elf_ops.h | 72 +++++++++++++--
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include/hw/{arm => intc}/armv7m_nvic.h | 0
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include/hw/watchdog/wdt_aspeed.h | 2 +
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include/qom/cpu.h | 27 ++++++
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softmmu_template.h | 4 +-
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target/arm/cpu.h | 56 +++++++++---
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target/arm/internals.h | 15 +++-
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target/arm/kvm_arm.h | 9 +-
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accel/tcg/cputlb.c | 32 ++++++-
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hw/arm/armv7m.c | 4 +-
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hw/arm/aspeed.c | 3 +
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hw/arm/aspeed_soc.c | 4 +
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hw/arm/collie.c | 1 +
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hw/arm/cubieboard.c | 1 +
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hw/arm/digic.c | 2 +
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hw/arm/digic_boards.c | 1 +
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hw/arm/exynos4210.c | 4 +-
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hw/arm/exynos4_boards.c | 2 +
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hw/arm/gumstix.c | 2 +
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hw/arm/highbank.c | 13 ++-
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hw/arm/imx25_pdk.c | 1 +
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hw/arm/integratorcp.c | 1 +
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hw/arm/kzm.c | 1 +
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hw/arm/mainstone.c | 1 +
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hw/arm/musicpal.c | 1 +
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hw/arm/netduino2.c | 1 +
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hw/arm/nseries.c | 2 +
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hw/arm/omap_sx1.c | 2 +
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hw/arm/palm.c | 1 +
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hw/arm/raspi.c | 1 +
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hw/arm/realview.c | 10 ++-
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hw/arm/sabrelite.c | 1 +
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hw/arm/spitz.c | 4 +
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hw/arm/stellaris.c | 2 +
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hw/arm/tosa.c | 1 +
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hw/arm/versatilepb.c | 2 +
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hw/arm/vexpress.c | 7 +-
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hw/arm/virt.c | 12 ++-
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hw/arm/xilinx_zynq.c | 15 ++--
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hw/arm/xlnx-ep108.c | 2 +
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hw/arm/z2.c | 1 +
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hw/intc/arm_gicv3_kvm.c | 2 +-
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hw/intc/armv7m_nvic.c | 68 +++++++++-----
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hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++---
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qom/cpu.c | 7 ++
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target/arm/cpu.c | 8 +-
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target/arm/helper.c | 124 ++++++++++++-------------
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target/arm/kvm.c | 6 +-
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target/arm/kvm32.c | 8 +-
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target/arm/kvm64.c | 63 +++++++------
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target/arm/machine.c | 54 ++++++++++-
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target/arm/op_helper.c | 160 ++++++++++++++++++++++-----------
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target/arm/translate-a64.c | 29 +++---
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target/arm/translate.c | 106 ++++++++++++++++------
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58 files changed, 795 insertions(+), 289 deletions(-)
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rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
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diff view generated by jsdifflib
New patch
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From: Philippe Mathieu-Daudé <philmd@linaro.org>
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Cortex-M profile is only emulable from TCG accelerator. Restrict
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the GDBstub features to its availability in order to avoid a link
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error when TCG is not enabled:
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Undefined symbols for architecture arm64:
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"_arm_v7m_get_sp_ptr", referenced from:
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_m_sysreg_get in target_arm_gdbstub.c.o
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"_arm_v7m_mrs_control", referenced from:
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_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
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ld: symbol(s) not found for architecture arm64
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clang: error: linker command failed with exit code 1 (use -v to see invocation)
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Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Message-id: 20230322142902.69511-3-philmd@linaro.org
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[PMM: add #include since I cherry-picked this patch from the series]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/gdbstub.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/gdbstub.c
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+++ b/target/arm/gdbstub.c
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@@ -XXX,XX +XXX,XX @@
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "gdbstub/helpers.h"
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+#include "sysemu/tcg.h"
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#include "internals.h"
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#include "cpregs.h"
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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2, "arm-vfp-sysregs.xml", 0);
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}
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}
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- if (cpu_isar_feature(aa32_mve, cpu)) {
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+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
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gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
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1, "arm-m-profile-mve.xml", 0);
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}
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
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"system-registers.xml", 0);
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- if (arm_feature(env, ARM_FEATURE_M)) {
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+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
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gdb_register_coprocessor(cs,
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arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
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arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
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--
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2.34.1
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diff view generated by jsdifflib