[Qemu-devel] [PULL 00/36] target-arm queue
[PULL v2 00/57] target-arm queue
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Try #2, with the compile failure in kvm32.c fixed
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Squashed in a trivial fix for 32-bit hosts:
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(trivial change, not resending patches)
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2
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thanks
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--- a/target/arm/mve_helper.c
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+++ b/target/arm/mve_helper.c
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@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
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acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
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m[H##ESIZE(e)])); \
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} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
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} \
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} \
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mve_advance_vpt(env); \
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-- PMM
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-- PMM
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The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
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The following changes since commit 53f306f316549d20c76886903181413d20842423:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
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24
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for you to fetch changes up to 0b8095ec9e924dc00636ab2069d88dec6592a75d:
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for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
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arm_gicv3_kvm: Fix compile warning (2017-09-04 15:21:56 +0100)
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docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
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28
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm:
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target-arm queue:
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* collection of M profile cleanups and minor bugfixes
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* Don't require 'virt' board to be compiled in for ACPI GHES code
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* loader: handle ELF files with overlapping zero-init data
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* docs: Document which architecture extensions we emulate
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* virt: allow PMU instantiation with userspace irqchip
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* Fix bugs in M-profile FPCXT_NS accesses
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* wdt_aspeed: Add support for the reset width register
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* First slice of MVE patches
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* cpu: Define new cpu_transaction_failed() hook
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* Implement MTE3
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* arm: Support generating CPU exceptions on memory
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* docs/system: arm: Add nRF boards description
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transaction failures (bus faults)
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* Mark some SoC devices as not user-creatable
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* arm: Fix aa64 ldp register writeback
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* arm_gicv3_kvm: Fix compile warning
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37
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jeffery (2):
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Alexandre Iooss (1):
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watchdog: wdt_aspeed: Add support for the reset width register
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docs/system: arm: Add nRF boards description
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aspeed_soc: Propagate silicon-rev to watchdog
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Andrew Jones (4):
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Peter Collingbourne (1):
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hw/arm/virt: add pmu interrupt state
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target/arm: Implement MTE3
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target/arm/kvm: pmu: split init and set-irq stages
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hw/arm/virt: allow pmu instantiation with userspace irqchip
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target/arm/kvm: pmu: improve error handling
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Peter Maydell (25):
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Peter Maydell (55):
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target/arm: Use MMUAccessType enum rather than int
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hw/acpi: Provide stub version of acpi_ghes_record_errors()
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target/arm: Don't trap WFI/WFE for M profile
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hw/acpi: Provide function acpi_ghes_present()
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target/arm: Consolidate PMSA handling in get_phys_addr()
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target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
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target/arm: Tighten up Thumb decode where new v8M insns will be
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docs/system/arm: Document which architecture extensions we emulate
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hw/intc/armv7m_nvic.c: Remove out of date comment
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target/arm/translate-vfp.c: Whitespace fixes
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target/arm: Remove incorrect comment about MPU_CTRL
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target/arm: Handle FPU being disabled in FPCXT_NS accesses
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target/arm: Fix outdated comment about exception exit
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target/arm: Don't NOCP fault for FPCXT_NS accesses
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target/arm: Define and use XPSR bit masks
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target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
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target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
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target/arm: Factor FP context update code out into helper function
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target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
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target/arm: Split vfp_access_check() into A and M versions
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target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
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target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
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target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
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target/arm: Create and use new function arm_v7m_is_handler_mode()
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target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
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armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
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target/arm: Implement MVE VCLZ
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nvic: Implement "user accesses BusFault" SCS region behaviour
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target/arm: Implement MVE VCLS
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loader: Handle ELF files with overlapping zero-initialized data
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target/arm: Implement MVE VREV16, VREV32, VREV64
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loader: Ignore zero-sized ELF segments
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target/arm: Implement MVE VMVN (register)
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memory.h: Move MemTxResult type to memattrs.h
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target/arm: Implement MVE VABS
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cpu: Define new cpu_transaction_failed() hook
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target/arm: Implement MVE VNEG
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cputlb: Support generating CPU exceptions on memory transaction failures
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tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
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boards.h: Define new flag ignore_memory_transaction_failures
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target/arm: Implement MVE VDUP
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hw/arm: Set ignore_memory_transaction_failures for most ARM boards
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target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
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target/arm: Factor out fault delivery code
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target/arm: Implement MVE VADD, VSUB, VMUL
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target/arm: Allow deliver_fault() caller to specify EA bit
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target/arm: Implement MVE VMULH
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target/arm: Implement new do_transaction_failed hook
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target/arm: Implement MVE VRMULH
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target/arm: Implement MVE VMAX, VMIN
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target/arm: Implement MVE VABD
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target/arm: Implement MVE VHADD, VHSUB
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target/arm: Implement MVE VMULL
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target/arm: Implement MVE VMLALDAV
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target/arm: Implement MVE VMLSLDAV
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target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
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target/arm: Implement MVE VADD (scalar)
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target/arm: Implement MVE VSUB, VMUL (scalar)
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target/arm: Implement MVE VHADD, VHSUB (scalar)
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target/arm: Implement MVE VBRSR
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target/arm: Implement MVE VPST
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target/arm: Implement MVE VQADD and VQSUB
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target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
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target/arm: Implement MVE VQDMULL scalar
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target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
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target/arm: Implement MVE VQADD, VQSUB (vector)
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target/arm: Implement MVE VQSHL (vector)
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target/arm: Implement MVE VQRSHL
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target/arm: Implement MVE VSHL insn
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target/arm: Implement MVE VRSHL
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target/arm: Implement MVE VQDMLADH and VQRDMLADH
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target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
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target/arm: Implement MVE VQDMULL (vector)
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target/arm: Implement MVE VRHADD
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target/arm: Implement MVE VADC, VSBC
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target/arm: Implement MVE VCADD
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target/arm: Implement MVE VHCADD
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target/arm: Implement MVE VADDV
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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
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Philippe Mathieu-Daudé (1):
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docs/system/arm/emulation.rst | 103 ++++
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hw/arm: use defined type name instead of hard-coded string
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docs/system/arm/nrf.rst | 51 ++
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docs/system/target-arm.rst | 7 +
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include/hw/acpi/ghes.h | 9 +
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include/tcg/tcg-op.h | 8 +
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include/tcg/tcg.h | 1 -
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target/arm/helper-mve.h | 357 +++++++++++++
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target/arm/helper.h | 2 +
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target/arm/internals.h | 11 +
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target/arm/translate-a32.h | 3 +
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target/arm/translate.h | 10 +
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target/arm/m-nocp.decode | 24 +
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target/arm/mve.decode | 240 +++++++++
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target/arm/vfp.decode | 14 -
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hw/acpi/ghes-stub.c | 22 +
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hw/acpi/ghes.c | 17 +
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target/arm/cpu64.c | 2 +-
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target/arm/kvm64.c | 6 +-
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target/arm/mte_helper.c | 82 +--
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target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
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target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
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target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
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target/arm/translate-vfp.c | 741 +++++++-------------------
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tcg/tcg-op-gvec.c | 20 +-
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MAINTAINERS | 1 +
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hw/acpi/meson.build | 6 +-
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target/arm/meson.build | 1 +
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27 files changed, 3578 insertions(+), 629 deletions(-)
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create mode 100644 docs/system/arm/emulation.rst
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create mode 100644 docs/system/arm/nrf.rst
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create mode 100644 target/arm/helper-mve.h
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create mode 100644 hw/acpi/ghes-stub.c
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create mode 100644 target/arm/mve_helper.c
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135
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Pranith Kumar (1):
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arm_gicv3_kvm: Fix compile warning
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Richard Henderson (1):
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target/arm: Fix aa64 ldp register writeback
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Thomas Huth (2):
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hw/arm/aspeed_soc: Mark devices as user_creatable = false
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hw/arm/digic: Mark device with user_creatable = false
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include/exec/memattrs.h | 10 +++
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include/exec/memory.h | 10 ---
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include/hw/arm/armv7m.h | 2 +-
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include/hw/boards.h | 11 +++
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include/hw/elf_ops.h | 72 +++++++++++++--
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include/hw/{arm => intc}/armv7m_nvic.h | 0
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include/hw/watchdog/wdt_aspeed.h | 2 +
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include/qom/cpu.h | 27 ++++++
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softmmu_template.h | 4 +-
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target/arm/cpu.h | 56 +++++++++---
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target/arm/internals.h | 15 +++-
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target/arm/kvm_arm.h | 9 +-
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accel/tcg/cputlb.c | 32 ++++++-
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hw/arm/armv7m.c | 4 +-
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hw/arm/aspeed.c | 3 +
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hw/arm/aspeed_soc.c | 4 +
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hw/arm/collie.c | 1 +
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hw/arm/cubieboard.c | 1 +
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hw/arm/digic.c | 2 +
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hw/arm/digic_boards.c | 1 +
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hw/arm/exynos4210.c | 4 +-
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hw/arm/exynos4_boards.c | 2 +
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hw/arm/gumstix.c | 2 +
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hw/arm/highbank.c | 13 ++-
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hw/arm/imx25_pdk.c | 1 +
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hw/arm/integratorcp.c | 1 +
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hw/arm/kzm.c | 1 +
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hw/arm/mainstone.c | 1 +
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hw/arm/musicpal.c | 1 +
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hw/arm/netduino2.c | 1 +
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hw/arm/nseries.c | 2 +
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hw/arm/omap_sx1.c | 2 +
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hw/arm/palm.c | 1 +
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hw/arm/raspi.c | 1 +
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hw/arm/realview.c | 10 ++-
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hw/arm/sabrelite.c | 1 +
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hw/arm/spitz.c | 4 +
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hw/arm/stellaris.c | 2 +
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hw/arm/tosa.c | 1 +
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hw/arm/versatilepb.c | 2 +
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hw/arm/vexpress.c | 7 +-
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hw/arm/virt.c | 12 ++-
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hw/arm/xilinx_zynq.c | 15 ++--
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hw/arm/xlnx-ep108.c | 2 +
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hw/arm/z2.c | 1 +
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hw/intc/arm_gicv3_kvm.c | 2 +-
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hw/intc/armv7m_nvic.c | 68 +++++++++-----
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hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++---
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qom/cpu.c | 7 ++
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target/arm/cpu.c | 8 +-
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target/arm/helper.c | 124 ++++++++++++-------------
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target/arm/kvm.c | 6 +-
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target/arm/kvm32.c | 8 +-
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target/arm/kvm64.c | 63 +++++++------
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target/arm/machine.c | 54 ++++++++++-
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target/arm/op_helper.c | 160 ++++++++++++++++++++++-----------
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target/arm/translate-a64.c | 29 +++---
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target/arm/translate.c | 106 ++++++++++++++++------
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58 files changed, 795 insertions(+), 289 deletions(-)
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rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
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