[Qemu-devel] [PULL 00/36] target-arm queue
[PULL v2 00/29] target-arm queue
1
Try #2, with the compile failure in kvm32.c fixed
1
v2: drop pvpanic-pci patches.
2
(trivial change, not resending patches)
3
2
4
thanks
3
The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
5
-- PMM
6
4
7
The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
5
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
8
6
9
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
7
are available in the Git repository at:
10
8
11
are available in the git repository at:
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
12
10
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-1
11
for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
14
12
15
for you to fetch changes up to 0b8095ec9e924dc00636ab2069d88dec6592a75d:
13
docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
16
17
arm_gicv3_kvm: Fix compile warning (2017-09-04 15:21:56 +0100)
18
14
19
----------------------------------------------------------------
15
----------------------------------------------------------------
20
target-arm:
16
target-arm queue:
21
* collection of M profile cleanups and minor bugfixes
17
* Implement IMPDEF pauth algorithm
22
* loader: handle ELF files with overlapping zero-init data
18
* Support ARMv8.4-SEL2
23
* virt: allow PMU instantiation with userspace irqchip
19
* Fix bug where we were truncating predicate vector lengths in SVE insns
24
* wdt_aspeed: Add support for the reset width register
20
* npcm7xx_adc-test: Fix memleak in adc_qom_set
25
* cpu: Define new cpu_transaction_failed() hook
21
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
26
* arm: Support generating CPU exceptions on memory
22
* docs: Build and install all the docs in a single manual
27
transaction failures (bus faults)
28
* Mark some SoC devices as not user-creatable
29
* arm: Fix aa64 ldp register writeback
30
* arm_gicv3_kvm: Fix compile warning
31
23
32
----------------------------------------------------------------
24
----------------------------------------------------------------
33
Andrew Jeffery (2):
25
Gan Qixin (1):
34
watchdog: wdt_aspeed: Add support for the reset width register
26
npcm7xx_adc-test: Fix memleak in adc_qom_set
35
aspeed_soc: Propagate silicon-rev to watchdog
36
27
37
Andrew Jones (4):
28
Peter Maydell (1):
38
hw/arm/virt: add pmu interrupt state
29
docs: Build and install all the docs in a single manual
39
target/arm/kvm: pmu: split init and set-irq stages
40
hw/arm/virt: allow pmu instantiation with userspace irqchip
41
target/arm/kvm: pmu: improve error handling
42
43
Peter Maydell (25):
44
target/arm: Use MMUAccessType enum rather than int
45
target/arm: Don't trap WFI/WFE for M profile
46
target/arm: Consolidate PMSA handling in get_phys_addr()
47
target/arm: Tighten up Thumb decode where new v8M insns will be
48
hw/intc/armv7m_nvic.c: Remove out of date comment
49
target/arm: Remove incorrect comment about MPU_CTRL
50
target/arm: Fix outdated comment about exception exit
51
target/arm: Define and use XPSR bit masks
52
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
53
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
54
target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
55
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
56
target/arm: Create and use new function arm_v7m_is_handler_mode()
57
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
58
nvic: Implement "user accesses BusFault" SCS region behaviour
59
loader: Handle ELF files with overlapping zero-initialized data
60
loader: Ignore zero-sized ELF segments
61
memory.h: Move MemTxResult type to memattrs.h
62
cpu: Define new cpu_transaction_failed() hook
63
cputlb: Support generating CPU exceptions on memory transaction failures
64
boards.h: Define new flag ignore_memory_transaction_failures
65
hw/arm: Set ignore_memory_transaction_failures for most ARM boards
66
target/arm: Factor out fault delivery code
67
target/arm: Allow deliver_fault() caller to specify EA bit
68
target/arm: Implement new do_transaction_failed hook
69
30
70
Philippe Mathieu-Daudé (1):
31
Philippe Mathieu-Daudé (1):
71
hw/arm: use defined type name instead of hard-coded string
32
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
72
33
73
Pranith Kumar (1):
34
Richard Henderson (7):
74
arm_gicv3_kvm: Fix compile warning
35
target/arm: Implement an IMPDEF pauth algorithm
36
target/arm: Add cpu properties to control pauth
37
target/arm: Use object_property_add_bool for "sve" property
38
target/arm: Introduce PREDDESC field definitions
39
target/arm: Update PFIRST, PNEXT for pred_desc
40
target/arm: Update ZIP, UZP, TRN for pred_desc
41
target/arm: Update REV, PUNPK for pred_desc
75
42
76
Richard Henderson (1):
43
Rémi Denis-Courmont (19):
77
target/arm: Fix aa64 ldp register writeback
44
target/arm: remove redundant tests
45
target/arm: add arm_is_el2_enabled() helper
46
target/arm: use arm_is_el2_enabled() where applicable
47
target/arm: use arm_hcr_el2_eff() where applicable
48
target/arm: factor MDCR_EL2 common handling
49
target/arm: Define isar_feature function to test for presence of SEL2
50
target/arm: add 64-bit S-EL2 to EL exception table
51
target/arm: add MMU stage 1 for Secure EL2
52
target/arm: add ARMv8.4-SEL2 system registers
53
target/arm: handle VMID change in secure state
54
target/arm: do S1_ptw_translate() before address space lookup
55
target/arm: translate NS bit in page-walks
56
target/arm: generalize 2-stage page-walk condition
57
target/arm: secure stage 2 translation regime
58
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
59
target/arm: revector to run-time pick target EL
60
target/arm: Implement SCR_EL2.EEL2
61
target/arm: enable Secure EL2 in max CPU
62
target/arm: refactor vae1_tlbmask()
78
63
79
Thomas Huth (2):
64
docs/conf.py | 46 ++++-
80
hw/arm/aspeed_soc: Mark devices as user_creatable = false
65
docs/devel/conf.py | 15 --
81
hw/arm/digic: Mark device with user_creatable = false
66
docs/index.html.in | 17 --
67
docs/interop/conf.py | 28 ---
68
docs/meson.build | 64 +++---
69
docs/specs/conf.py | 16 --
70
docs/system/arm/cpu-features.rst | 21 ++
71
docs/system/conf.py | 28 ---
72
docs/tools/conf.py | 37 ----
73
docs/user/conf.py | 15 --
74
include/qemu/xxhash.h | 98 +++++++++
75
target/arm/cpu-param.h | 2 +-
76
target/arm/cpu.h | 107 ++++++++--
77
target/arm/internals.h | 45 +++++
78
target/arm/cpu.c | 23 ++-
79
target/arm/cpu64.c | 65 ++++--
80
target/arm/helper-a64.c | 8 +-
81
target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
82
target/arm/m_helper.c | 2 +-
83
target/arm/monitor.c | 1 +
84
target/arm/op_helper.c | 4 +-
85
target/arm/pauth_helper.c | 27 ++-
86
target/arm/sve_helper.c | 33 ++--
87
target/arm/tlb_helper.c | 3 +
88
target/arm/translate-a64.c | 4 +
89
target/arm/translate-sve.c | 31 ++-
90
target/arm/translate.c | 36 +++-
91
tests/qtest/arm-cpu-features.c | 13 ++
92
tests/qtest/npcm7xx_adc-test.c | 1 +
93
.gitlab-ci.yml | 4 +-
94
30 files changed, 770 insertions(+), 438 deletions(-)
95
delete mode 100644 docs/devel/conf.py
96
delete mode 100644 docs/index.html.in
97
delete mode 100644 docs/interop/conf.py
98
delete mode 100644 docs/specs/conf.py
99
delete mode 100644 docs/system/conf.py
100
delete mode 100644 docs/tools/conf.py
101
delete mode 100644 docs/user/conf.py
82
102
83
include/exec/memattrs.h | 10 +++
84
include/exec/memory.h | 10 ---
85
include/hw/arm/armv7m.h | 2 +-
86
include/hw/boards.h | 11 +++
87
include/hw/elf_ops.h | 72 +++++++++++++--
88
include/hw/{arm => intc}/armv7m_nvic.h | 0
89
include/hw/watchdog/wdt_aspeed.h | 2 +
90
include/qom/cpu.h | 27 ++++++
91
softmmu_template.h | 4 +-
92
target/arm/cpu.h | 56 +++++++++---
93
target/arm/internals.h | 15 +++-
94
target/arm/kvm_arm.h | 9 +-
95
accel/tcg/cputlb.c | 32 ++++++-
96
hw/arm/armv7m.c | 4 +-
97
hw/arm/aspeed.c | 3 +
98
hw/arm/aspeed_soc.c | 4 +
99
hw/arm/collie.c | 1 +
100
hw/arm/cubieboard.c | 1 +
101
hw/arm/digic.c | 2 +
102
hw/arm/digic_boards.c | 1 +
103
hw/arm/exynos4210.c | 4 +-
104
hw/arm/exynos4_boards.c | 2 +
105
hw/arm/gumstix.c | 2 +
106
hw/arm/highbank.c | 13 ++-
107
hw/arm/imx25_pdk.c | 1 +
108
hw/arm/integratorcp.c | 1 +
109
hw/arm/kzm.c | 1 +
110
hw/arm/mainstone.c | 1 +
111
hw/arm/musicpal.c | 1 +
112
hw/arm/netduino2.c | 1 +
113
hw/arm/nseries.c | 2 +
114
hw/arm/omap_sx1.c | 2 +
115
hw/arm/palm.c | 1 +
116
hw/arm/raspi.c | 1 +
117
hw/arm/realview.c | 10 ++-
118
hw/arm/sabrelite.c | 1 +
119
hw/arm/spitz.c | 4 +
120
hw/arm/stellaris.c | 2 +
121
hw/arm/tosa.c | 1 +
122
hw/arm/versatilepb.c | 2 +
123
hw/arm/vexpress.c | 7 +-
124
hw/arm/virt.c | 12 ++-
125
hw/arm/xilinx_zynq.c | 15 ++--
126
hw/arm/xlnx-ep108.c | 2 +
127
hw/arm/z2.c | 1 +
128
hw/intc/arm_gicv3_kvm.c | 2 +-
129
hw/intc/armv7m_nvic.c | 68 +++++++++-----
130
hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++---
131
qom/cpu.c | 7 ++
132
target/arm/cpu.c | 8 +-
133
target/arm/helper.c | 124 ++++++++++++-------------
134
target/arm/kvm.c | 6 +-
135
target/arm/kvm32.c | 8 +-
136
target/arm/kvm64.c | 63 +++++++------
137
target/arm/machine.c | 54 ++++++++++-
138
target/arm/op_helper.c | 160 ++++++++++++++++++++++-----------
139
target/arm/translate-a64.c | 29 +++---
140
target/arm/translate.c | 106 ++++++++++++++++------
141
58 files changed, 795 insertions(+), 289 deletions(-)
142
rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
143
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.