[Qemu-devel] [PULL 00/36] target-arm queue
[Qemu-devel] [PULL 00/37] target-arm queue
1
Try #2, with the compile failure in kvm32.c fixed
1
First target-arm pullreq of the 4.0 series; most of this
2
(trivial change, not resending patches)
2
is Mao's cleanups that finally let us drop sysbus::init;
3
the most interesting user-visible feature is RTH's patches
4
adding some v8.1 and v8.2 architecture features.
3
5
4
thanks
6
thanks
5
-- PMM
7
-- PMM
6
8
7
The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
9
The following changes since commit 6145a6d84b3bf0f25935b88543febe076c61b0f4:
8
10
9
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
11
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181212' into staging (2018-12-13 13:06:09 +0000)
10
12
11
are available in the git repository at:
13
are available in the Git repository at:
12
14
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-1
15
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181213
14
16
15
for you to fetch changes up to 0b8095ec9e924dc00636ab2069d88dec6592a75d:
17
for you to fetch changes up to 2d7137c10fafefe40a0a049ff8a7bd78b66e661f:
16
18
17
arm_gicv3_kvm: Fix compile warning (2017-09-04 15:21:56 +0100)
19
target/arm: Implement the ARMv8.1-LOR extension (2018-12-13 14:41:24 +0000)
18
20
19
----------------------------------------------------------------
21
----------------------------------------------------------------
20
target-arm:
22
target-arm queue:
21
* collection of M profile cleanups and minor bugfixes
23
* Convert various devices from sysbus init to instance_init
22
* loader: handle ELF files with overlapping zero-init data
24
* Remove the now unused sysbus init support entirely
23
* virt: allow PMU instantiation with userspace irqchip
25
* Allow AArch64 processors to boot from a kernel placed over 4GB
24
* wdt_aspeed: Add support for the reset width register
26
* hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link()
25
* cpu: Define new cpu_transaction_failed() hook
27
* versal: minor fixes to virtio-mmio instantation
26
* arm: Support generating CPU exceptions on memory
28
* arm: Implement the ARMv8.1-HPD extension
27
transaction failures (bus faults)
29
* arm: Implement the ARMv8.2-AA32HPD extension
28
* Mark some SoC devices as not user-creatable
30
* arm: Implement the ARMv8.1-LOR extension (as the trivial
29
* arm: Fix aa64 ldp register writeback
31
"no limited ordering regions provided" minimum)
30
* arm_gicv3_kvm: Fix compile warning
31
32
32
----------------------------------------------------------------
33
----------------------------------------------------------------
33
Andrew Jeffery (2):
34
Edgar E. Iglesias (4):
34
watchdog: wdt_aspeed: Add support for the reset width register
35
hw/arm: versal: Remove bogus virtio-mmio creation
35
aspeed_soc: Propagate silicon-rev to watchdog
36
hw/arm: versal: Reduce number of virtio-mmio instances
37
hw/arm: versal: Use IRQs 111 - 118 for virtio-mmio
38
hw/arm: versal: Correct the nr of IRQs to 192
36
39
37
Andrew Jones (4):
40
Li Qiang (1):
38
hw/arm/virt: add pmu interrupt state
41
hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link()
39
target/arm/kvm: pmu: split init and set-irq stages
40
hw/arm/virt: allow pmu instantiation with userspace irqchip
41
target/arm/kvm: pmu: improve error handling
42
42
43
Peter Maydell (25):
43
Mao Zhongyi (21):
44
target/arm: Use MMUAccessType enum rather than int
44
musicpal: Convert sysbus init function to realize function
45
target/arm: Don't trap WFI/WFE for M profile
45
block/noenand: Convert sysbus init function to realize function
46
target/arm: Consolidate PMSA handling in get_phys_addr()
46
char/grlib_apbuart: Convert sysbus init function to realize function
47
target/arm: Tighten up Thumb decode where new v8M insns will be
47
core/empty_slot: Convert sysbus init function to realize function
48
hw/intc/armv7m_nvic.c: Remove out of date comment
48
display/g364fb: Convert sysbus init function to realize function
49
target/arm: Remove incorrect comment about MPU_CTRL
49
dma/puv3_dma: Convert sysbus init function to realize function
50
target/arm: Fix outdated comment about exception exit
50
gpio/puv3_gpio: Convert sysbus init function to realize function
51
target/arm: Define and use XPSR bit masks
51
milkymist-softusb: Convert sysbus init function to realize function
52
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
52
input/pl050: Convert sysbus init function to realize function
53
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
53
intc/puv3_intc: Convert sysbus init function to realize function
54
target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
54
milkymist-hpdmc: Convert sysbus init function to realize function
55
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
55
milkymist-pfpu: Convert sysbus init function to realize function
56
target/arm: Create and use new function arm_v7m_is_handler_mode()
56
puv3_pm.c: Convert sysbus init function to realize function
57
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
57
nvram/ds1225y: Convert sysbus init function to realize function
58
nvic: Implement "user accesses BusFault" SCS region behaviour
58
pci-bridge/dec: Convert sysbus init function to realize function
59
loader: Handle ELF files with overlapping zero-initialized data
59
timer/etraxfs_timer: Convert sysbus init function to realize function
60
loader: Ignore zero-sized ELF segments
60
timer/grlib_gptimer: Convert sysbus init function to realize function
61
memory.h: Move MemTxResult type to memattrs.h
61
timer/puv3_ost: Convert sysbus init function to realize function
62
cpu: Define new cpu_transaction_failed() hook
62
usb/tusb6010: Convert sysbus init function to realize function
63
cputlb: Support generating CPU exceptions on memory transaction failures
63
xen_backend: remove xen_sysdev_init() function
64
boards.h: Define new flag ignore_memory_transaction_failures
64
core/sysbus: remove the SysBusDeviceClass::init path
65
hw/arm: Set ignore_memory_transaction_failures for most ARM boards
66
target/arm: Factor out fault delivery code
67
target/arm: Allow deliver_fault() caller to specify EA bit
68
target/arm: Implement new do_transaction_failed hook
69
65
70
Philippe Mathieu-Daudé (1):
66
Peter Maydell (1):
71
hw/arm: use defined type name instead of hard-coded string
67
target/arm: Move id_aa64mmfr* to ARMISARegisters
72
68
73
Pranith Kumar (1):
69
Ricardo Perez Blanco (1):
74
arm_gicv3_kvm: Fix compile warning
70
Allow AArch64 processors to boot from a kernel placed over 4GB
75
71
76
Richard Henderson (1):
72
Richard Henderson (9):
77
target/arm: Fix aa64 ldp register writeback
73
target/arm: Add HCR_EL2 bits up to ARMv8.5
74
target/arm: Add SCR_EL3 bits up to ARMv8.5
75
target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el
76
target/arm: Tidy scr_write
77
target/arm: Implement the ARMv8.1-HPD extension
78
target/arm: Implement the ARMv8.2-AA32HPD extension
79
target/arm: Introduce arm_hcr_el2_eff
80
target/arm: Use arm_hcr_el2_eff more places
81
target/arm: Implement the ARMv8.1-LOR extension
78
82
79
Thomas Huth (2):
83
include/hw/arm/xlnx-versal.h | 8 +-
80
hw/arm/aspeed_soc: Mark devices as user_creatable = false
84
include/hw/sysbus.h | 3 -
81
hw/arm/digic: Mark device with user_creatable = false
85
target/arm/cpu.h | 141 ++++++++++++++++-----------
86
target/arm/internals.h | 3 +-
87
hw/arm/boot.c | 35 ++++---
88
hw/arm/musicpal.c | 11 +--
89
hw/arm/xlnx-versal-virt.c | 7 +-
90
hw/block/onenand.c | 16 ++--
91
hw/char/grlib_apbuart.c | 12 +--
92
hw/core/empty_slot.c | 9 +-
93
hw/core/sysbus.c | 15 +--
94
hw/display/g364fb.c | 9 +-
95
hw/dma/puv3_dma.c | 10 +-
96
hw/gpio/puv3_gpio.c | 29 +++---
97
hw/input/milkymist-softusb.c | 16 ++--
98
hw/input/pl050.c | 11 +--
99
hw/intc/arm_gicv3_cpuif.c | 21 ++--
100
hw/intc/puv3_intc.c | 11 +--
101
hw/misc/milkymist-hpdmc.c | 9 +-
102
hw/misc/milkymist-pfpu.c | 12 +--
103
hw/misc/puv3_pm.c | 10 +-
104
hw/nvram/ds1225y.c | 12 +--
105
hw/pci-bridge/dec.c | 12 +--
106
hw/timer/etraxfs_timer.c | 14 +--
107
hw/timer/grlib_gptimer.c | 11 +--
108
hw/timer/puv3_ost.c | 13 ++-
109
hw/usb/tusb6010.c | 8 +-
110
hw/xen/xen_backend.c | 7 --
111
target/arm/cpu.c | 4 +
112
target/arm/cpu64.c | 11 ++-
113
target/arm/helper.c | 222 ++++++++++++++++++++++++++++++++++++-------
114
target/arm/kvm64.c | 4 +
115
target/arm/op_helper.c | 14 ++-
116
target/arm/translate-a64.c | 12 +++
117
34 files changed, 456 insertions(+), 286 deletions(-)
82
118
83
include/exec/memattrs.h | 10 +++
84
include/exec/memory.h | 10 ---
85
include/hw/arm/armv7m.h | 2 +-
86
include/hw/boards.h | 11 +++
87
include/hw/elf_ops.h | 72 +++++++++++++--
88
include/hw/{arm => intc}/armv7m_nvic.h | 0
89
include/hw/watchdog/wdt_aspeed.h | 2 +
90
include/qom/cpu.h | 27 ++++++
91
softmmu_template.h | 4 +-
92
target/arm/cpu.h | 56 +++++++++---
93
target/arm/internals.h | 15 +++-
94
target/arm/kvm_arm.h | 9 +-
95
accel/tcg/cputlb.c | 32 ++++++-
96
hw/arm/armv7m.c | 4 +-
97
hw/arm/aspeed.c | 3 +
98
hw/arm/aspeed_soc.c | 4 +
99
hw/arm/collie.c | 1 +
100
hw/arm/cubieboard.c | 1 +
101
hw/arm/digic.c | 2 +
102
hw/arm/digic_boards.c | 1 +
103
hw/arm/exynos4210.c | 4 +-
104
hw/arm/exynos4_boards.c | 2 +
105
hw/arm/gumstix.c | 2 +
106
hw/arm/highbank.c | 13 ++-
107
hw/arm/imx25_pdk.c | 1 +
108
hw/arm/integratorcp.c | 1 +
109
hw/arm/kzm.c | 1 +
110
hw/arm/mainstone.c | 1 +
111
hw/arm/musicpal.c | 1 +
112
hw/arm/netduino2.c | 1 +
113
hw/arm/nseries.c | 2 +
114
hw/arm/omap_sx1.c | 2 +
115
hw/arm/palm.c | 1 +
116
hw/arm/raspi.c | 1 +
117
hw/arm/realview.c | 10 ++-
118
hw/arm/sabrelite.c | 1 +
119
hw/arm/spitz.c | 4 +
120
hw/arm/stellaris.c | 2 +
121
hw/arm/tosa.c | 1 +
122
hw/arm/versatilepb.c | 2 +
123
hw/arm/vexpress.c | 7 +-
124
hw/arm/virt.c | 12 ++-
125
hw/arm/xilinx_zynq.c | 15 ++--
126
hw/arm/xlnx-ep108.c | 2 +
127
hw/arm/z2.c | 1 +
128
hw/intc/arm_gicv3_kvm.c | 2 +-
129
hw/intc/armv7m_nvic.c | 68 +++++++++-----
130
hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++---
131
qom/cpu.c | 7 ++
132
target/arm/cpu.c | 8 +-
133
target/arm/helper.c | 124 ++++++++++++-------------
134
target/arm/kvm.c | 6 +-
135
target/arm/kvm32.c | 8 +-
136
target/arm/kvm64.c | 63 +++++++------
137
target/arm/machine.c | 54 ++++++++++-
138
target/arm/op_helper.c | 160 ++++++++++++++++++++++-----------
139
target/arm/translate-a64.c | 29 +++---
140
target/arm/translate.c | 106 ++++++++++++++++------
141
58 files changed, 795 insertions(+), 289 deletions(-)
142
rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
143
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 01/37] hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link()
1
From: Li Qiang <liq3ea@gmail.com>
1
2
3
The third argument of object_property_set_link() is the name of
4
property, not related with the QOM type name, using the constant
5
string instead.
6
7
Signed-off-by: Li Qiang <liq3ea@gmail.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 1542880825-2604-1-git-send-email-liq3ea@gmail.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/musicpal.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/musicpal.c
19
+++ b/hw/arm/musicpal.c
20
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
21
dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO);
22
s = SYS_BUS_DEVICE(dev);
23
object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev),
24
- TYPE_WM8750, NULL);
25
+ "wm8750", NULL);
26
qdev_init_nofail(dev);
27
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
28
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
29
--
30
2.19.2
31
32
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 02/37] Allow AArch64 processors to boot from a kernel placed over 4GB
1
From: Ricardo Perez Blanco <ricardo.perez_blanco@nokia.com>
1
2
3
Architecturally, it's possible for an AArch64 machine to have
4
all of its RAM over the 4GB mark, but our kernel/initrd loading
5
code in boot.c assumes that the upper half of the addresses
6
to load these images to is always zero. Write the whole 64 bit
7
address into the bootloader code fragment, not just the low half.
8
9
Note that, currently, none of the existing QEMU machines have
10
their main memory over 4GBs, so this was not a user-visible bug.
11
12
Signed-off-by: Ricardo Perez Blanco <ricardo.perez_blanco@nokia.com>
13
[PMM: revised commit message and tweaked some long lines]
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/boot.c | 35 ++++++++++++++++++++++-------------
18
1 file changed, 22 insertions(+), 13 deletions(-)
19
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
23
+++ b/hw/arm/boot.c
24
@@ -XXX,XX +XXX,XX @@ typedef enum {
25
FIXUP_TERMINATOR, /* end of insns */
26
FIXUP_BOARDID, /* overwrite with board ID number */
27
FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
28
- FIXUP_ARGPTR, /* overwrite with pointer to kernel args */
29
- FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */
30
+ FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
31
+ FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
32
+ FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
33
+ FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
34
FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
35
FIXUP_BOOTREG, /* overwrite with boot register address */
36
FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
37
@@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup bootloader_aarch64[] = {
38
{ 0xaa1f03e3 }, /* mov x3, xzr */
39
{ 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
40
{ 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
41
- { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */
42
- { 0 }, /* .word @DTB Higher 32-bits */
43
- { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */
44
- { 0 }, /* .word @Kernel Entry Higher 32-bits */
45
+ { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */
46
+ { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */
47
+ { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */
48
+ { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */
49
{ 0, FIXUP_TERMINATOR }
50
};
51
52
@@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup bootloader[] = {
53
{ 0xe59f2004 }, /* ldr r2, [pc, #4] */
54
{ 0xe59ff004 }, /* ldr pc, [pc, #4] */
55
{ 0, FIXUP_BOARDID },
56
- { 0, FIXUP_ARGPTR },
57
- { 0, FIXUP_ENTRYPOINT },
58
+ { 0, FIXUP_ARGPTR_LO },
59
+ { 0, FIXUP_ENTRYPOINT_LO },
60
{ 0, FIXUP_TERMINATOR }
61
};
62
63
@@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr,
64
break;
65
case FIXUP_BOARDID:
66
case FIXUP_BOARD_SETUP:
67
- case FIXUP_ARGPTR:
68
- case FIXUP_ENTRYPOINT:
69
+ case FIXUP_ARGPTR_LO:
70
+ case FIXUP_ARGPTR_HI:
71
+ case FIXUP_ENTRYPOINT_LO:
72
+ case FIXUP_ENTRYPOINT_HI:
73
case FIXUP_GIC_CPU_IF:
74
case FIXUP_BOOTREG:
75
case FIXUP_DSB:
76
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
77
/* Place the DTB after the initrd in memory with alignment. */
78
info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
79
align);
80
- fixupcontext[FIXUP_ARGPTR] = info->dtb_start;
81
+ fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start;
82
+ fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32;
83
} else {
84
- fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR;
85
+ fixupcontext[FIXUP_ARGPTR_LO] =
86
+ info->loader_start + KERNEL_ARGS_ADDR;
87
+ fixupcontext[FIXUP_ARGPTR_HI] =
88
+ (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
89
if (info->ram_size >= (1ULL << 32)) {
90
error_report("RAM size must be less than 4GB to boot"
91
" Linux kernel using ATAGS (try passing a device tree"
92
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
93
exit(1);
94
}
95
}
96
- fixupcontext[FIXUP_ENTRYPOINT] = entry;
97
+ fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
98
+ fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
99
100
write_bootloader("bootloader", info->loader_start,
101
primary_loader, fixupcontext, as);
102
--
103
2.19.2
104
105
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 03/37] musicpal: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
mv88w8618_wlan_class_init().
5
6
Cc: jan.kiszka@web.de
7
Cc: peter.maydell@linaro.org
8
Cc: qemu-arm@nongnu.org
9
10
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
11
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20181130093852.20739-2-maozhongyi@cmss.chinamobile.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/musicpal.c | 9 ++++-----
17
1 file changed, 4 insertions(+), 5 deletions(-)
18
19
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/musicpal.c
22
+++ b/hw/arm/musicpal.c
23
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mv88w8618_wlan_ops = {
24
.endianness = DEVICE_NATIVE_ENDIAN,
25
};
26
27
-static int mv88w8618_wlan_init(SysBusDevice *dev)
28
+static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp)
29
{
30
MemoryRegion *iomem = g_new(MemoryRegion, 1);
31
32
memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL,
33
"musicpal-wlan", MP_WLAN_SIZE);
34
- sysbus_init_mmio(dev, iomem);
35
- return 0;
36
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem);
37
}
38
39
/* GPIO register offsets */
40
@@ -XXX,XX +XXX,XX @@ DEFINE_MACHINE("musicpal", musicpal_machine_init)
41
42
static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data)
43
{
44
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
45
+ DeviceClass *dc = DEVICE_CLASS(klass);
46
47
- sdc->init = mv88w8618_wlan_init;
48
+ dc->realize = mv88w8618_wlan_realize;
49
}
50
51
static const TypeInfo mv88w8618_wlan_info = {
52
--
53
2.19.2
54
55
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 04/37] block/noenand: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
onenand_class_init().
5
6
Cc: kwolf@redhat.com
7
Cc: mreitz@redhat.com
8
Cc: qemu-block@nongnu.org
9
10
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
11
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20181130093852.20739-3-maozhongyi@cmss.chinamobile.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/block/onenand.c | 16 +++++++---------
17
1 file changed, 7 insertions(+), 9 deletions(-)
18
19
diff --git a/hw/block/onenand.c b/hw/block/onenand.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/block/onenand.c
22
+++ b/hw/block/onenand.c
23
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps onenand_ops = {
24
.endianness = DEVICE_NATIVE_ENDIAN,
25
};
26
27
-static int onenand_initfn(SysBusDevice *sbd)
28
+static void onenand_realize(DeviceState *dev, Error **errp)
29
{
30
- DeviceState *dev = DEVICE(sbd);
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
32
OneNANDState *s = ONE_NAND(dev);
33
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
34
void *ram;
35
@@ -XXX,XX +XXX,XX @@ static int onenand_initfn(SysBusDevice *sbd)
36
0xff, size + (size >> 5));
37
} else {
38
if (blk_is_read_only(s->blk)) {
39
- error_report("Can't use a read-only drive");
40
- return -1;
41
+ error_setg(errp, "Can't use a read-only drive");
42
+ return;
43
}
44
blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
45
BLK_PERM_ALL, &local_err);
46
if (local_err) {
47
- error_report_err(local_err);
48
- return -1;
49
+ error_propagate(errp, local_err);
50
+ return;
51
}
52
s->blk_cur = s->blk;
53
}
54
@@ -XXX,XX +XXX,XX @@ static int onenand_initfn(SysBusDevice *sbd)
55
| ((s->id.dev & 0xff) << 8)
56
| (s->id.ver & 0xff),
57
&vmstate_onenand, s);
58
- return 0;
59
}
60
61
static Property onenand_properties[] = {
62
@@ -XXX,XX +XXX,XX @@ static Property onenand_properties[] = {
63
static void onenand_class_init(ObjectClass *klass, void *data)
64
{
65
DeviceClass *dc = DEVICE_CLASS(klass);
66
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
67
68
- k->init = onenand_initfn;
69
+ dc->realize = onenand_realize;
70
dc->reset = onenand_system_reset;
71
dc->props = onenand_properties;
72
}
73
--
74
2.19.2
75
76
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 05/37] char/grlib_apbuart: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
grlib_apbuart_class_init().
5
6
Cc: chouteau@adacore.com
7
Cc: marcandre.lureau@redhat.com
8
Cc: pbonzini@redhat.com
9
10
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
11
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20181130093852.20739-4-maozhongyi@cmss.chinamobile.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/char/grlib_apbuart.c | 12 +++++-------
17
1 file changed, 5 insertions(+), 7 deletions(-)
18
19
diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/char/grlib_apbuart.c
22
+++ b/hw/char/grlib_apbuart.c
23
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps grlib_apbuart_ops = {
24
.endianness = DEVICE_NATIVE_ENDIAN,
25
};
26
27
-static int grlib_apbuart_init(SysBusDevice *dev)
28
+static void grlib_apbuart_realize(DeviceState *dev, Error **errp)
29
{
30
UART *uart = GRLIB_APB_UART(dev);
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
32
33
qemu_chr_fe_set_handlers(&uart->chr,
34
grlib_apbuart_can_receive,
35
@@ -XXX,XX +XXX,XX @@ static int grlib_apbuart_init(SysBusDevice *dev)
36
grlib_apbuart_event,
37
NULL, uart, NULL, true);
38
39
- sysbus_init_irq(dev, &uart->irq);
40
+ sysbus_init_irq(sbd, &uart->irq);
41
42
memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
43
"uart", UART_REG_SIZE);
44
45
- sysbus_init_mmio(dev, &uart->iomem);
46
-
47
- return 0;
48
+ sysbus_init_mmio(sbd, &uart->iomem);
49
}
50
51
static void grlib_apbuart_reset(DeviceState *d)
52
@@ -XXX,XX +XXX,XX @@ static Property grlib_apbuart_properties[] = {
53
static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
54
{
55
DeviceClass *dc = DEVICE_CLASS(klass);
56
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
57
58
- k->init = grlib_apbuart_init;
59
+ dc->realize = grlib_apbuart_realize;
60
dc->reset = grlib_apbuart_reset;
61
dc->props = grlib_apbuart_properties;
62
}
63
--
64
2.19.2
65
66
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 06/37] core/empty_slot: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
empty_slot_class_init().
5
6
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
7
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20181130093852.20739-5-maozhongyi@cmss.chinamobile.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/core/empty_slot.c | 9 ++++-----
14
1 file changed, 4 insertions(+), 5 deletions(-)
15
16
diff --git a/hw/core/empty_slot.c b/hw/core/empty_slot.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/core/empty_slot.c
19
+++ b/hw/core/empty_slot.c
20
@@ -XXX,XX +XXX,XX @@ void empty_slot_init(hwaddr addr, uint64_t slot_size)
21
}
22
}
23
24
-static int empty_slot_init1(SysBusDevice *dev)
25
+static void empty_slot_realize(DeviceState *dev, Error **errp)
26
{
27
EmptySlot *s = EMPTY_SLOT(dev);
28
29
memory_region_init_io(&s->iomem, OBJECT(s), &empty_slot_ops, s,
30
"empty-slot", s->size);
31
- sysbus_init_mmio(dev, &s->iomem);
32
- return 0;
33
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
34
}
35
36
static void empty_slot_class_init(ObjectClass *klass, void *data)
37
{
38
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
39
+ DeviceClass *dc = DEVICE_CLASS(klass);
40
41
- k->init = empty_slot_init1;
42
+ dc->realize = empty_slot_realize;
43
}
44
45
static const TypeInfo empty_slot_info = {
46
--
47
2.19.2
48
49
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 07/37] display/g364fb: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
g364fb_sysbus_class_init().
5
6
Cc: pbonzini@redhat.com
7
Cc: kraxel@redhat.com
8
Cc: f4bug@amsat.org
9
Cc: alistair.francis@wdc.com
10
11
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
12
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20181130093852.20739-6-maozhongyi@cmss.chinamobile.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/display/g364fb.c | 9 +++------
19
1 file changed, 3 insertions(+), 6 deletions(-)
20
21
diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/display/g364fb.c
24
+++ b/hw/display/g364fb.c
25
@@ -XXX,XX +XXX,XX @@ typedef struct {
26
G364State g364;
27
} G364SysBusState;
28
29
-static int g364fb_sysbus_init(SysBusDevice *sbd)
30
+static void g364fb_sysbus_realize(DeviceState *dev, Error **errp)
31
{
32
- DeviceState *dev = DEVICE(sbd);
33
G364SysBusState *sbs = G364(dev);
34
G364State *s = &sbs->g364;
35
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
36
37
g364fb_init(dev, s);
38
sysbus_init_irq(sbd, &s->irq);
39
sysbus_init_mmio(sbd, &s->mem_ctrl);
40
sysbus_init_mmio(sbd, &s->mem_vram);
41
-
42
- return 0;
43
}
44
45
static void g364fb_sysbus_reset(DeviceState *d)
46
@@ -XXX,XX +XXX,XX @@ static Property g364fb_sysbus_properties[] = {
47
static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
48
{
49
DeviceClass *dc = DEVICE_CLASS(klass);
50
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
51
52
- k->init = g364fb_sysbus_init;
53
+ dc->realize = g364fb_sysbus_realize;
54
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
55
dc->desc = "G364 framebuffer";
56
dc->reset = g364fb_sysbus_reset;
57
--
58
2.19.2
59
60
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 08/37] dma/puv3_dma: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
puv3_dma_class_init().
5
6
Cc: gxt@mprc.pku.edu.cn
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-7-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/dma/puv3_dma.c | 10 ++++------
16
1 file changed, 4 insertions(+), 6 deletions(-)
17
18
diff --git a/hw/dma/puv3_dma.c b/hw/dma/puv3_dma.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/dma/puv3_dma.c
21
+++ b/hw/dma/puv3_dma.c
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps puv3_dma_ops = {
23
.endianness = DEVICE_NATIVE_ENDIAN,
24
};
25
26
-static int puv3_dma_init(SysBusDevice *dev)
27
+static void puv3_dma_realize(DeviceState *dev, Error **errp)
28
{
29
PUV3DMAState *s = PUV3_DMA(dev);
30
int i;
31
@@ -XXX,XX +XXX,XX @@ static int puv3_dma_init(SysBusDevice *dev)
32
33
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
34
PUV3_REGS_OFFSET);
35
- sysbus_init_mmio(dev, &s->iomem);
36
-
37
- return 0;
38
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
39
}
40
41
static void puv3_dma_class_init(ObjectClass *klass, void *data)
42
{
43
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
44
+ DeviceClass *dc = DEVICE_CLASS(klass);
45
46
- sdc->init = puv3_dma_init;
47
+ dc->realize = puv3_dma_realize;
48
}
49
50
static const TypeInfo puv3_dma_info = {
51
--
52
2.19.2
53
54
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 09/37] gpio/puv3_gpio: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
puv3_gpio_class_init().
5
6
Cc: gxt@mprc.pku.edu.cn
7
Cc: peter.maydell@linaro.org
8
9
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
10
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-8-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/gpio/puv3_gpio.c | 29 ++++++++++++++---------------
16
1 file changed, 14 insertions(+), 15 deletions(-)
17
18
diff --git a/hw/gpio/puv3_gpio.c b/hw/gpio/puv3_gpio.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/gpio/puv3_gpio.c
21
+++ b/hw/gpio/puv3_gpio.c
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps puv3_gpio_ops = {
23
.endianness = DEVICE_NATIVE_ENDIAN,
24
};
25
26
-static int puv3_gpio_init(SysBusDevice *dev)
27
+static void puv3_gpio_realize(DeviceState *dev, Error **errp)
28
{
29
PUV3GPIOState *s = PUV3_GPIO(dev);
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
31
32
s->reg_GPLR = 0;
33
s->reg_GPDR = 0;
34
35
/* FIXME: these irqs not handled yet */
36
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]);
37
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]);
38
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]);
39
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]);
40
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]);
41
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]);
42
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]);
43
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
44
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
45
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW0]);
46
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW1]);
47
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW2]);
48
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW3]);
49
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW4]);
50
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW5]);
51
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW6]);
52
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW7]);
53
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOHIGH]);
54
55
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio",
56
PUV3_REGS_OFFSET);
57
- sysbus_init_mmio(dev, &s->iomem);
58
-
59
- return 0;
60
+ sysbus_init_mmio(sbd, &s->iomem);
61
}
62
63
static void puv3_gpio_class_init(ObjectClass *klass, void *data)
64
{
65
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
66
+ DeviceClass *dc = DEVICE_CLASS(klass);
67
68
- sdc->init = puv3_gpio_init;
69
+ dc->realize = puv3_gpio_realize;
70
}
71
72
static const TypeInfo puv3_gpio_info = {
73
--
74
2.19.2
75
76
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 10/37] milkymist-softusb: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
milkymist_softusb_class_init().
5
6
Cc: michael@walle.cc
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-9-maozhongyi@cmss.chinamobile.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/input/milkymist-softusb.c | 16 +++++++---------
15
1 file changed, 7 insertions(+), 9 deletions(-)
16
17
diff --git a/hw/input/milkymist-softusb.c b/hw/input/milkymist-softusb.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/input/milkymist-softusb.c
20
+++ b/hw/input/milkymist-softusb.c
21
@@ -XXX,XX +XXX,XX @@ static void milkymist_softusb_reset(DeviceState *d)
22
s->regs[R_CTRL] = CTRL_RESET;
23
}
24
25
-static int milkymist_softusb_init(SysBusDevice *dev)
26
+static void milkymist_softusb_realize(DeviceState *dev, Error **errp)
27
{
28
MilkymistSoftUsbState *s = MILKYMIST_SOFTUSB(dev);
29
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
30
31
- sysbus_init_irq(dev, &s->irq);
32
+ sysbus_init_irq(sbd, &s->irq);
33
34
memory_region_init_io(&s->regs_region, OBJECT(s), &softusb_mmio_ops, s,
35
"milkymist-softusb", R_MAX * 4);
36
- sysbus_init_mmio(dev, &s->regs_region);
37
+ sysbus_init_mmio(sbd, &s->regs_region);
38
39
/* register pmem and dmem */
40
memory_region_init_ram_nomigrate(&s->pmem, OBJECT(s), "milkymist-softusb.pmem",
41
s->pmem_size, &error_fatal);
42
vmstate_register_ram_global(&s->pmem);
43
s->pmem_ptr = memory_region_get_ram_ptr(&s->pmem);
44
- sysbus_init_mmio(dev, &s->pmem);
45
+ sysbus_init_mmio(sbd, &s->pmem);
46
memory_region_init_ram_nomigrate(&s->dmem, OBJECT(s), "milkymist-softusb.dmem",
47
s->dmem_size, &error_fatal);
48
vmstate_register_ram_global(&s->dmem);
49
s->dmem_ptr = memory_region_get_ram_ptr(&s->dmem);
50
- sysbus_init_mmio(dev, &s->dmem);
51
+ sysbus_init_mmio(sbd, &s->dmem);
52
53
hid_init(&s->hid_kbd, HID_KEYBOARD, softusb_kbd_hid_datain);
54
hid_init(&s->hid_mouse, HID_MOUSE, softusb_mouse_hid_datain);
55
-
56
- return 0;
57
}
58
59
static const VMStateDescription vmstate_milkymist_softusb = {
60
@@ -XXX,XX +XXX,XX @@ static Property milkymist_softusb_properties[] = {
61
static void milkymist_softusb_class_init(ObjectClass *klass, void *data)
62
{
63
DeviceClass *dc = DEVICE_CLASS(klass);
64
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
65
66
- k->init = milkymist_softusb_init;
67
+ dc->realize = milkymist_softusb_realize;
68
dc->reset = milkymist_softusb_reset;
69
dc->vmsd = &vmstate_milkymist_softusb;
70
dc->props = milkymist_softusb_properties;
71
--
72
2.19.2
73
74
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 11/37] input/pl050: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
pl050_class_init().
5
6
Cc: peter.maydell@linaro.org
7
Cc: qemu-arm@nongnu.org
8
9
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
10
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-10-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/input/pl050.c | 11 +++++------
16
1 file changed, 5 insertions(+), 6 deletions(-)
17
18
diff --git a/hw/input/pl050.c b/hw/input/pl050.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/input/pl050.c
21
+++ b/hw/input/pl050.c
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pl050_ops = {
23
.endianness = DEVICE_NATIVE_ENDIAN,
24
};
25
26
-static int pl050_initfn(SysBusDevice *dev)
27
+static void pl050_realize(DeviceState *dev, Error **errp)
28
{
29
PL050State *s = PL050(dev);
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
31
32
memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000);
33
- sysbus_init_mmio(dev, &s->iomem);
34
- sysbus_init_irq(dev, &s->irq);
35
+ sysbus_init_mmio(sbd, &s->iomem);
36
+ sysbus_init_irq(sbd, &s->irq);
37
if (s->is_mouse) {
38
s->dev = ps2_mouse_init(pl050_update, s);
39
} else {
40
s->dev = ps2_kbd_init(pl050_update, s);
41
}
42
- return 0;
43
}
44
45
static void pl050_keyboard_init(Object *obj)
46
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pl050_mouse_info = {
47
static void pl050_class_init(ObjectClass *oc, void *data)
48
{
49
DeviceClass *dc = DEVICE_CLASS(oc);
50
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(oc);
51
52
- sdc->init = pl050_initfn;
53
+ dc->realize = pl050_realize;
54
dc->vmsd = &vmstate_pl050;
55
}
56
57
--
58
2.19.2
59
60
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 12/37] intc/puv3_intc: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
puv3_intc_class_init().
5
6
Cc: gxt@mprc.pku.edu.cn
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-11-maozhongyi@cmss.chinamobile.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/intc/puv3_intc.c | 11 ++++-------
15
1 file changed, 4 insertions(+), 7 deletions(-)
16
17
diff --git a/hw/intc/puv3_intc.c b/hw/intc/puv3_intc.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/puv3_intc.c
20
+++ b/hw/intc/puv3_intc.c
21
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps puv3_intc_ops = {
22
.endianness = DEVICE_NATIVE_ENDIAN,
23
};
24
25
-static int puv3_intc_init(SysBusDevice *sbd)
26
+static void puv3_intc_realize(DeviceState *dev, Error **errp)
27
{
28
- DeviceState *dev = DEVICE(sbd);
29
PUV3INTCState *s = PUV3_INTC(dev);
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
31
32
qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR);
33
sysbus_init_irq(sbd, &s->parent_irq);
34
@@ -XXX,XX +XXX,XX @@ static int puv3_intc_init(SysBusDevice *sbd)
35
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
36
PUV3_REGS_OFFSET);
37
sysbus_init_mmio(sbd, &s->iomem);
38
-
39
- return 0;
40
}
41
42
static void puv3_intc_class_init(ObjectClass *klass, void *data)
43
{
44
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
45
-
46
- sdc->init = puv3_intc_init;
47
+ DeviceClass *dc = DEVICE_CLASS(klass);
48
+ dc->realize = puv3_intc_realize;
49
}
50
51
static const TypeInfo puv3_intc_info = {
52
--
53
2.19.2
54
55
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 13/37] milkymist-hpdmc: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
milkymist_hpdmc_class_init().
5
6
Cc: gxt@mprc.pku.edu.cn
7
Cc: michael@walle.cc
8
9
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
10
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-12-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/misc/milkymist-hpdmc.c | 9 +++------
16
1 file changed, 3 insertions(+), 6 deletions(-)
17
18
diff --git a/hw/misc/milkymist-hpdmc.c b/hw/misc/milkymist-hpdmc.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/milkymist-hpdmc.c
21
+++ b/hw/misc/milkymist-hpdmc.c
22
@@ -XXX,XX +XXX,XX @@ static void milkymist_hpdmc_reset(DeviceState *d)
23
| IODELAY_PLL2_LOCKED;
24
}
25
26
-static int milkymist_hpdmc_init(SysBusDevice *dev)
27
+static void milkymist_hpdmc_realize(DeviceState *dev, Error **errp)
28
{
29
MilkymistHpdmcState *s = MILKYMIST_HPDMC(dev);
30
31
memory_region_init_io(&s->regs_region, OBJECT(dev), &hpdmc_mmio_ops, s,
32
"milkymist-hpdmc", R_MAX * 4);
33
- sysbus_init_mmio(dev, &s->regs_region);
34
-
35
- return 0;
36
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs_region);
37
}
38
39
static const VMStateDescription vmstate_milkymist_hpdmc = {
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_milkymist_hpdmc = {
41
static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data)
42
{
43
DeviceClass *dc = DEVICE_CLASS(klass);
44
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
45
46
- k->init = milkymist_hpdmc_init;
47
+ dc->realize = milkymist_hpdmc_realize;
48
dc->reset = milkymist_hpdmc_reset;
49
dc->vmsd = &vmstate_milkymist_hpdmc;
50
}
51
--
52
2.19.2
53
54
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 14/37] milkymist-pfpu: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
milkymist_pfpu_class_init().
5
6
Cc: michael@walle.cc
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-13-maozhongyi@cmss.chinamobile.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/misc/milkymist-pfpu.c | 12 +++++-------
15
1 file changed, 5 insertions(+), 7 deletions(-)
16
17
diff --git a/hw/misc/milkymist-pfpu.c b/hw/misc/milkymist-pfpu.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/milkymist-pfpu.c
20
+++ b/hw/misc/milkymist-pfpu.c
21
@@ -XXX,XX +XXX,XX @@ static void milkymist_pfpu_reset(DeviceState *d)
22
}
23
}
24
25
-static int milkymist_pfpu_init(SysBusDevice *dev)
26
+static void milkymist_pfpu_realize(DeviceState *dev, Error **errp)
27
{
28
MilkymistPFPUState *s = MILKYMIST_PFPU(dev);
29
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
30
31
- sysbus_init_irq(dev, &s->irq);
32
+ sysbus_init_irq(sbd, &s->irq);
33
34
memory_region_init_io(&s->regs_region, OBJECT(dev), &pfpu_mmio_ops, s,
35
"milkymist-pfpu", MICROCODE_END * 4);
36
- sysbus_init_mmio(dev, &s->regs_region);
37
-
38
- return 0;
39
+ sysbus_init_mmio(sbd, &s->regs_region);
40
}
41
42
static const VMStateDescription vmstate_milkymist_pfpu = {
43
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_milkymist_pfpu = {
44
static void milkymist_pfpu_class_init(ObjectClass *klass, void *data)
45
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
47
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
48
49
- k->init = milkymist_pfpu_init;
50
+ dc->realize = milkymist_pfpu_realize;
51
dc->reset = milkymist_pfpu_reset;
52
dc->vmsd = &vmstate_milkymist_pfpu;
53
}
54
--
55
2.19.2
56
57
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 15/37] puv3_pm.c: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
puv3_pm_class_init().
5
6
Cc: gxt@mprc.pku.edu.cn
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-14-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/misc/puv3_pm.c | 10 ++++------
16
1 file changed, 4 insertions(+), 6 deletions(-)
17
18
diff --git a/hw/misc/puv3_pm.c b/hw/misc/puv3_pm.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/puv3_pm.c
21
+++ b/hw/misc/puv3_pm.c
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps puv3_pm_ops = {
23
.endianness = DEVICE_NATIVE_ENDIAN,
24
};
25
26
-static int puv3_pm_init(SysBusDevice *dev)
27
+static void puv3_pm_realize(DeviceState *dev, Error **errp)
28
{
29
PUV3PMState *s = PUV3_PM(dev);
30
31
@@ -XXX,XX +XXX,XX @@ static int puv3_pm_init(SysBusDevice *dev)
32
33
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
34
PUV3_REGS_OFFSET);
35
- sysbus_init_mmio(dev, &s->iomem);
36
-
37
- return 0;
38
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
39
}
40
41
static void puv3_pm_class_init(ObjectClass *klass, void *data)
42
{
43
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
44
+ DeviceClass *dc = DEVICE_CLASS(klass);
45
46
- sdc->init = puv3_pm_init;
47
+ dc->realize = puv3_pm_realize;
48
}
49
50
static const TypeInfo puv3_pm_info = {
51
--
52
2.19.2
53
54
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 16/37] nvram/ds1225y: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
nvram_sysbus_class_init().
5
6
Cc: pbonzini@redhat.com
7
Cc: marcandre.lureau@redhat.com
8
9
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
10
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-15-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/nvram/ds1225y.c | 12 +++++-------
16
1 file changed, 5 insertions(+), 7 deletions(-)
17
18
diff --git a/hw/nvram/ds1225y.c b/hw/nvram/ds1225y.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/nvram/ds1225y.c
21
+++ b/hw/nvram/ds1225y.c
22
@@ -XXX,XX +XXX,XX @@
23
#include "qemu/osdep.h"
24
#include "hw/sysbus.h"
25
#include "trace.h"
26
+#include "qemu/error-report.h"
27
28
typedef struct {
29
MemoryRegion iomem;
30
@@ -XXX,XX +XXX,XX @@ typedef struct {
31
NvRamState nvram;
32
} SysBusNvRamState;
33
34
-static int nvram_sysbus_initfn(SysBusDevice *dev)
35
+static void nvram_sysbus_realize(DeviceState *dev, Error **errp)
36
{
37
SysBusNvRamState *sys = DS1225Y(dev);
38
NvRamState *s = &sys->nvram;
39
@@ -XXX,XX +XXX,XX @@ static int nvram_sysbus_initfn(SysBusDevice *dev)
40
41
memory_region_init_io(&s->iomem, OBJECT(s), &nvram_ops, s,
42
"nvram", s->chip_size);
43
- sysbus_init_mmio(dev, &s->iomem);
44
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
45
46
/* Read current file */
47
file = s->filename ? fopen(s->filename, "rb") : NULL;
48
if (file) {
49
/* Read nvram contents */
50
if (fread(s->contents, s->chip_size, 1, file) != 1) {
51
- printf("nvram_sysbus_initfn: short read\n");
52
+ error_report("nvram_sysbus_realize: short read");
53
}
54
fclose(file);
55
}
56
nvram_post_load(s, 0);
57
-
58
- return 0;
59
}
60
61
static Property nvram_sysbus_properties[] = {
62
@@ -XXX,XX +XXX,XX @@ static Property nvram_sysbus_properties[] = {
63
static void nvram_sysbus_class_init(ObjectClass *klass, void *data)
64
{
65
DeviceClass *dc = DEVICE_CLASS(klass);
66
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
67
68
- k->init = nvram_sysbus_initfn;
69
+ dc->realize = nvram_sysbus_realize;
70
dc->vmsd = &vmstate_nvram;
71
dc->props = nvram_sysbus_properties;
72
}
73
--
74
2.19.2
75
76
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 17/37] pci-bridge/dec: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
pci_dec_21154_device_class_init().
5
6
Cc: david@gibson.dropbear.id.au
7
Cc: mst@redhat.com
8
Cc: marcel.apfelbaum@gmail.com
9
Cc: qemu-ppc@nongnu.org
10
11
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
12
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
13
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
14
Acked-by: David Gibson <david@gibson.dropbear.id.au>
15
Message-id: 20181130093852.20739-16-maozhongyi@cmss.chinamobile.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/pci-bridge/dec.c | 12 ++++++------
19
1 file changed, 6 insertions(+), 6 deletions(-)
20
21
diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/pci-bridge/dec.c
24
+++ b/hw/pci-bridge/dec.c
25
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
26
return pci_bridge_get_sec_bus(br);
27
}
28
29
-static int pci_dec_21154_device_init(SysBusDevice *dev)
30
+static void pci_dec_21154_device_realize(DeviceState *dev, Error **errp)
31
{
32
PCIHostState *phb;
33
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
34
35
phb = PCI_HOST_BRIDGE(dev);
36
37
@@ -XXX,XX +XXX,XX @@ static int pci_dec_21154_device_init(SysBusDevice *dev)
38
dev, "pci-conf-idx", 0x1000);
39
memory_region_init_io(&phb->data_mem, OBJECT(dev), &pci_host_data_le_ops,
40
dev, "pci-data-idx", 0x1000);
41
- sysbus_init_mmio(dev, &phb->conf_mem);
42
- sysbus_init_mmio(dev, &phb->data_mem);
43
- return 0;
44
+ sysbus_init_mmio(sbd, &phb->conf_mem);
45
+ sysbus_init_mmio(sbd, &phb->data_mem);
46
}
47
48
static void dec_21154_pci_host_realize(PCIDevice *d, Error **errp)
49
@@ -XXX,XX +XXX,XX @@ static const TypeInfo dec_21154_pci_host_info = {
50
51
static void pci_dec_21154_device_class_init(ObjectClass *klass, void *data)
52
{
53
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
54
+ DeviceClass *dc = DEVICE_CLASS(klass);
55
56
- sdc->init = pci_dec_21154_device_init;
57
+ dc->realize = pci_dec_21154_device_realize;
58
}
59
60
static const TypeInfo pci_dec_21154_device_info = {
61
--
62
2.19.2
63
64
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 18/37] timer/etraxfs_timer: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
etraxfs_timer_class_init().
5
6
Cc: edgar.iglesias@gmail.com
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Message-id: 20181130093852.20739-17-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/timer/etraxfs_timer.c | 14 +++++++-------
16
1 file changed, 7 insertions(+), 7 deletions(-)
17
18
diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/timer/etraxfs_timer.c
21
+++ b/hw/timer/etraxfs_timer.c
22
@@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_reset(void *opaque)
23
qemu_irq_lower(t->irq);
24
}
25
26
-static int etraxfs_timer_init(SysBusDevice *dev)
27
+static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
28
{
29
ETRAXTimerState *t = ETRAX_TIMER(dev);
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
31
32
t->bh_t0 = qemu_bh_new(timer0_hit, t);
33
t->bh_t1 = qemu_bh_new(timer1_hit, t);
34
@@ -XXX,XX +XXX,XX @@ static int etraxfs_timer_init(SysBusDevice *dev)
35
t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT);
36
t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT);
37
38
- sysbus_init_irq(dev, &t->irq);
39
- sysbus_init_irq(dev, &t->nmi);
40
+ sysbus_init_irq(sbd, &t->irq);
41
+ sysbus_init_irq(sbd, &t->nmi);
42
43
memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
44
"etraxfs-timer", 0x5c);
45
- sysbus_init_mmio(dev, &t->mmio);
46
+ sysbus_init_mmio(sbd, &t->mmio);
47
qemu_register_reset(etraxfs_timer_reset, t);
48
- return 0;
49
}
50
51
static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
52
{
53
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
54
+ DeviceClass *dc = DEVICE_CLASS(klass);
55
56
- sdc->init = etraxfs_timer_init;
57
+ dc->realize = etraxfs_timer_realize;
58
}
59
60
static const TypeInfo etraxfs_timer_info = {
61
--
62
2.19.2
63
64
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 19/37] timer/grlib_gptimer: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
grlib_gptimer_class_init().
5
6
Cc: chouteau@adacore.com
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-18-maozhongyi@cmss.chinamobile.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/timer/grlib_gptimer.c | 11 +++++------
15
1 file changed, 5 insertions(+), 6 deletions(-)
16
17
diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/timer/grlib_gptimer.c
20
+++ b/hw/timer/grlib_gptimer.c
21
@@ -XXX,XX +XXX,XX @@ static void grlib_gptimer_reset(DeviceState *d)
22
}
23
}
24
25
-static int grlib_gptimer_init(SysBusDevice *dev)
26
+static void grlib_gptimer_realize(DeviceState *dev, Error **errp)
27
{
28
GPTimerUnit *unit = GRLIB_GPTIMER(dev);
29
unsigned int i;
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
31
32
assert(unit->nr_timers > 0);
33
assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
34
@@ -XXX,XX +XXX,XX @@ static int grlib_gptimer_init(SysBusDevice *dev)
35
timer->id = i;
36
37
/* One IRQ line for each timer */
38
- sysbus_init_irq(dev, &timer->irq);
39
+ sysbus_init_irq(sbd, &timer->irq);
40
41
ptimer_set_freq(timer->ptimer, unit->freq_hz);
42
}
43
@@ -XXX,XX +XXX,XX @@ static int grlib_gptimer_init(SysBusDevice *dev)
44
unit, "gptimer",
45
UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
46
47
- sysbus_init_mmio(dev, &unit->iomem);
48
- return 0;
49
+ sysbus_init_mmio(sbd, &unit->iomem);
50
}
51
52
static Property grlib_gptimer_properties[] = {
53
@@ -XXX,XX +XXX,XX @@ static Property grlib_gptimer_properties[] = {
54
static void grlib_gptimer_class_init(ObjectClass *klass, void *data)
55
{
56
DeviceClass *dc = DEVICE_CLASS(klass);
57
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
58
59
- k->init = grlib_gptimer_init;
60
+ dc->realize = grlib_gptimer_realize;
61
dc->reset = grlib_gptimer_reset;
62
dc->props = grlib_gptimer_properties;
63
}
64
--
65
2.19.2
66
67
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 20/37] timer/puv3_ost: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
puv3_ost_class_init().
5
6
Cc: gxt@mprc.pku.edu.cn
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-19-maozhongyi@cmss.chinamobile.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/timer/puv3_ost.c | 13 ++++++-------
15
1 file changed, 6 insertions(+), 7 deletions(-)
16
17
diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/timer/puv3_ost.c
20
+++ b/hw/timer/puv3_ost.c
21
@@ -XXX,XX +XXX,XX @@ static void puv3_ost_tick(void *opaque)
22
}
23
}
24
25
-static int puv3_ost_init(SysBusDevice *dev)
26
+static void puv3_ost_realize(DeviceState *dev, Error **errp)
27
{
28
PUV3OSTState *s = PUV3_OST(dev);
29
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
30
31
s->reg_OIER = 0;
32
s->reg_OSSR = 0;
33
s->reg_OSMR0 = 0;
34
s->reg_OSCR = 0;
35
36
- sysbus_init_irq(dev, &s->irq);
37
+ sysbus_init_irq(sbd, &s->irq);
38
39
s->bh = qemu_bh_new(puv3_ost_tick, s);
40
s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
41
@@ -XXX,XX +XXX,XX @@ static int puv3_ost_init(SysBusDevice *dev)
42
43
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
44
PUV3_REGS_OFFSET);
45
- sysbus_init_mmio(dev, &s->iomem);
46
-
47
- return 0;
48
+ sysbus_init_mmio(sbd, &s->iomem);
49
}
50
51
static void puv3_ost_class_init(ObjectClass *klass, void *data)
52
{
53
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
54
+ DeviceClass *dc = DEVICE_CLASS(klass);
55
56
- sdc->init = puv3_ost_init;
57
+ dc->realize = puv3_ost_realize;
58
}
59
60
static const TypeInfo puv3_ost_info = {
61
--
62
2.19.2
63
64
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 21/37] usb/tusb6010: Convert sysbus init function to realize function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Use DeviceClass rather than SysBusDeviceClass in
4
tusb6010_class_init().
5
6
Cc: kraxel@redhat.com
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Message-id: 20181130093852.20739-20-maozhongyi@cmss.chinamobile.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/usb/tusb6010.c | 8 +++-----
14
1 file changed, 3 insertions(+), 5 deletions(-)
15
16
diff --git a/hw/usb/tusb6010.c b/hw/usb/tusb6010.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/usb/tusb6010.c
19
+++ b/hw/usb/tusb6010.c
20
@@ -XXX,XX +XXX,XX @@ static void tusb6010_reset(DeviceState *dev)
21
musb_reset(s->musb);
22
}
23
24
-static int tusb6010_init(SysBusDevice *sbd)
25
+static void tusb6010_realize(DeviceState *dev, Error **errp)
26
{
27
- DeviceState *dev = DEVICE(sbd);
28
TUSBState *s = TUSB(dev);
29
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
30
31
s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
32
s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
33
@@ -XXX,XX +XXX,XX @@ static int tusb6010_init(SysBusDevice *sbd)
34
sysbus_init_irq(sbd, &s->irq);
35
qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
36
s->musb = musb_init(dev, 1);
37
- return 0;
38
}
39
40
static void tusb6010_class_init(ObjectClass *klass, void *data)
41
{
42
DeviceClass *dc = DEVICE_CLASS(klass);
43
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
44
45
- k->init = tusb6010_init;
46
+ dc->realize = tusb6010_realize;
47
dc->reset = tusb6010_reset;
48
}
49
50
--
51
2.19.2
52
53
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 22/37] xen_backend: remove xen_sysdev_init() function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
The init function doesn't do anything at all, so we
4
just omit it.
5
6
Cc: sstabellini@kernel.org
7
Cc: anthony.perard@citrix.com
8
Cc: xen-devel@lists.xenproject.org
9
Cc: peter.maydell@linaro.org
10
11
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
12
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
13
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
14
Message-id: 20181130093852.20739-21-maozhongyi@cmss.chinamobile.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/xen/xen_backend.c | 7 -------
18
1 file changed, 7 deletions(-)
19
20
diff --git a/hw/xen/xen_backend.c b/hw/xen/xen_backend.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/xen/xen_backend.c
23
+++ b/hw/xen/xen_backend.c
24
@@ -XXX,XX +XXX,XX @@ static const TypeInfo xensysbus_info = {
25
}
26
};
27
28
-static int xen_sysdev_init(SysBusDevice *dev)
29
-{
30
- return 0;
31
-}
32
-
33
static Property xen_sysdev_properties[] = {
34
{/* end of property list */},
35
};
36
@@ -XXX,XX +XXX,XX @@ static Property xen_sysdev_properties[] = {
37
static void xen_sysdev_class_init(ObjectClass *klass, void *data)
38
{
39
DeviceClass *dc = DEVICE_CLASS(klass);
40
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
41
42
- k->init = xen_sysdev_init;
43
dc->props = xen_sysdev_properties;
44
dc->bus_type = TYPE_XENSYSBUS;
45
}
46
--
47
2.19.2
48
49
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 23/37] core/sysbus: remove the SysBusDeviceClass::init path
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
2
3
Currently, all sysbus devices have been converted to realize(),
4
so remove this path.
5
6
Cc: ehabkost@redhat.com
7
Cc: thuth@redhat.com
8
Cc: pbonzini@redhat.com
9
Cc: armbru@redhat.com
10
Cc: peter.maydell@linaro.org
11
Cc: richard.henderson@linaro.org
12
Cc: alistair.francis@wdc.com
13
14
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
15
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
16
Message-id: 20181130093852.20739-22-maozhongyi@cmss.chinamobile.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/sysbus.h | 3 ---
21
hw/core/sysbus.c | 15 +++++----------
22
2 files changed, 5 insertions(+), 13 deletions(-)
23
24
diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/sysbus.h
27
+++ b/include/hw/sysbus.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct SysBusDevice SysBusDevice;
29
typedef struct SysBusDeviceClass {
30
/*< private >*/
31
DeviceClass parent_class;
32
- /*< public >*/
33
-
34
- int (*init)(SysBusDevice *dev);
35
36
/*
37
* Let the sysbus device format its own non-PIO, non-MMIO unit address.
38
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/core/sysbus.c
41
+++ b/hw/core/sysbus.c
42
@@ -XXX,XX +XXX,XX @@ void sysbus_init_ioports(SysBusDevice *dev, uint32_t ioport, uint32_t size)
43
}
44
}
45
46
-/* TODO remove once all sysbus devices have been converted to realize */
47
+/* The purpose of preserving this empty realize function
48
+ * is to prevent the parent_realize field of some subclasses
49
+ * from being set to NULL to break the normal init/realize
50
+ * of some devices.
51
+ */
52
static void sysbus_realize(DeviceState *dev, Error **errp)
53
{
54
- SysBusDevice *sd = SYS_BUS_DEVICE(dev);
55
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_GET_CLASS(sd);
56
-
57
- if (!sbc->init) {
58
- return;
59
- }
60
- if (sbc->init(sd) < 0) {
61
- error_setg(errp, "Device initialization failed");
62
- }
63
}
64
65
DeviceState *sysbus_create_varargs(const char *name,
66
--
67
2.19.2
68
69
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 24/37] hw/arm: versal: Remove bogus virtio-mmio creation
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
2
3
Remove bogus virtio-mmio creation. This was an accidental
4
left-over an experiment.
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20181129163655.20370-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/xlnx-versal-virt.c | 1 -
13
1 file changed, 1 deletion(-)
14
15
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-versal-virt.c
18
+++ b/hw/arm/xlnx-versal-virt.c
19
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
20
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
21
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
22
memory_region_add_subregion(&s->soc.mr_ps, base, mr);
23
- sysbus_create_simple("virtio-mmio", base, pic_irq);
24
}
25
26
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
27
--
28
2.19.2
29
30
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 25/37] hw/arm: versal: Reduce number of virtio-mmio instances
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
2
3
Reduce number of virtio-mmio instances. This is in preparation
4
for correcting the interrupt setup for Versal.
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20181129163655.20370-3-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/xlnx-versal-virt.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xlnx-versal-virt.c
17
+++ b/hw/arm/xlnx-versal-virt.c
18
@@ -XXX,XX +XXX,XX @@ static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
19
return board->fdt;
20
}
21
22
-#define NUM_VIRTIO_TRANSPORT 32
23
+#define NUM_VIRTIO_TRANSPORT 8
24
static void create_virtio_regions(VersalVirt *s)
25
{
26
int virtio_mmio_size = 0x200;
27
--
28
2.19.2
29
30
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 26/37] hw/arm: versal: Use IRQs 111 - 118 for virtio-mmio
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
2
3
Use IRQs 111 - 118 for virtio-mmio. The interrupts we're currently
4
using 160+ are not available in the Versal GIC.
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20181129163655.20370-4-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/xlnx-versal.h | 6 +++---
12
hw/arm/xlnx-versal-virt.c | 4 ++--
13
2 files changed, 5 insertions(+), 5 deletions(-)
14
15
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/xlnx-versal.h
18
+++ b/include/hw/arm/xlnx-versal.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
20
#define VERSAL_GEM1_IRQ_0 58
21
#define VERSAL_GEM1_WAKE_IRQ_0 59
22
23
-/* Architecturally eserved IRQs suitable for virtualization. */
24
-#define VERSAL_RSVD_HIGH_IRQ_FIRST 160
25
-#define VERSAL_RSVD_HIGH_IRQ_LAST 255
26
+/* Architecturally reserved IRQs suitable for virtualization. */
27
+#define VERSAL_RSVD_IRQ_FIRST 111
28
+#define VERSAL_RSVD_IRQ_LAST 118
29
30
#define MM_TOP_RSVD 0xa0000000U
31
#define MM_TOP_RSVD_SIZE 0x4000000
32
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/xlnx-versal-virt.c
35
+++ b/hw/arm/xlnx-versal-virt.c
36
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
37
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
38
char *name = g_strdup_printf("virtio%d", i);;
39
hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
40
- int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
41
+ int irq = VERSAL_RSVD_IRQ_FIRST + i;
42
MemoryRegion *mr;
43
DeviceState *dev;
44
qemu_irq pic_irq;
45
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
46
47
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
48
hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
49
- int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
50
+ int irq = VERSAL_RSVD_IRQ_FIRST + i;
51
char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
52
53
qemu_fdt_add_subnode(s->fdt, name);
54
--
55
2.19.2
56
57
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 27/37] hw/arm: versal: Correct the nr of IRQs to 192
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
2
3
Correct the nr of IRQs to 192.
4
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20181129163655.20370-5-edgar.iglesias@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
include/hw/arm/xlnx-versal.h | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/xlnx-versal.h
16
+++ b/include/hw/arm/xlnx-versal.h
17
@@ -XXX,XX +XXX,XX @@
18
#define XLNX_VERSAL_NR_ACPUS 2
19
#define XLNX_VERSAL_NR_UARTS 2
20
#define XLNX_VERSAL_NR_GEMS 2
21
-#define XLNX_VERSAL_NR_IRQS 256
22
+#define XLNX_VERSAL_NR_IRQS 192
23
24
typedef struct Versal {
25
/*< private >*/
26
--
27
2.19.2
28
29
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 28/37] target/arm: Move id_aa64mmfr* to ARMISARegisters
1
At the same time, define the fields for these registers,
2
and use those defines in arm_pamax().
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20181203203839.757-2-richard.henderson@linaro.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
[PMM: fixed up typo (s/achf/ahcf/) belatedly spotted by RTH]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 26 ++++++++++++++++++++++++--
11
target/arm/internals.h | 3 ++-
12
target/arm/cpu64.c | 6 +++---
13
target/arm/helper.c | 4 ++--
14
target/arm/kvm64.c | 4 ++++
15
5 files changed, 35 insertions(+), 8 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
22
uint64_t id_aa64isar1;
23
uint64_t id_aa64pfr0;
24
uint64_t id_aa64pfr1;
25
+ uint64_t id_aa64mmfr0;
26
+ uint64_t id_aa64mmfr1;
27
} isar;
28
uint32_t midr;
29
uint32_t revidr;
30
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
31
uint64_t id_aa64dfr1;
32
uint64_t id_aa64afr0;
33
uint64_t id_aa64afr1;
34
- uint64_t id_aa64mmfr0;
35
- uint64_t id_aa64mmfr1;
36
uint32_t dbgdidr;
37
uint32_t clidr;
38
uint64_t mp_affinity; /* MP ID without feature bits */
39
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, GIC, 24, 4)
40
FIELD(ID_AA64PFR0, RAS, 28, 4)
41
FIELD(ID_AA64PFR0, SVE, 32, 4)
42
43
+FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
44
+FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
45
+FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
46
+FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
47
+FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
48
+FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
49
+FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
50
+FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
51
+FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
52
+FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
53
+FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
54
+FIELD(ID_AA64MMFR0, EXS, 44, 4)
55
+
56
+FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
57
+FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
58
+FIELD(ID_AA64MMFR1, VH, 8, 4)
59
+FIELD(ID_AA64MMFR1, HPDS, 12, 4)
60
+FIELD(ID_AA64MMFR1, LO, 16, 4)
61
+FIELD(ID_AA64MMFR1, PAN, 20, 4)
62
+FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
63
+FIELD(ID_AA64MMFR1, XNX, 28, 4)
64
+
65
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
66
67
/* If adding a feature bit which corresponds to a Linux ELF
68
diff --git a/target/arm/internals.h b/target/arm/internals.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/internals.h
71
+++ b/target/arm/internals.h
72
@@ -XXX,XX +XXX,XX @@ static inline unsigned int arm_pamax(ARMCPU *cpu)
73
[4] = 44,
74
[5] = 48,
75
};
76
- unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
77
+ unsigned int parange =
78
+ FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
79
80
/* id_aa64mmfr0 is a read-only register so values outside of the
81
* supported mappings can be considered an implementation error. */
82
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/cpu64.c
85
+++ b/target/arm/cpu64.c
86
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
87
cpu->pmceid0 = 0x00000000;
88
cpu->pmceid1 = 0x00000000;
89
cpu->isar.id_aa64isar0 = 0x00011120;
90
- cpu->id_aa64mmfr0 = 0x00001124;
91
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
92
cpu->dbgdidr = 0x3516d000;
93
cpu->clidr = 0x0a200023;
94
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
95
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
96
cpu->isar.id_aa64pfr0 = 0x00002222;
97
cpu->id_aa64dfr0 = 0x10305106;
98
cpu->isar.id_aa64isar0 = 0x00011120;
99
- cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
100
+ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
101
cpu->dbgdidr = 0x3516d000;
102
cpu->clidr = 0x0a200023;
103
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
104
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
105
cpu->pmceid0 = 0x00000000;
106
cpu->pmceid1 = 0x00000000;
107
cpu->isar.id_aa64isar0 = 0x00011120;
108
- cpu->id_aa64mmfr0 = 0x00001124;
109
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
110
cpu->dbgdidr = 0x3516d000;
111
cpu->clidr = 0x0a200023;
112
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
113
diff --git a/target/arm/helper.c b/target/arm/helper.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/arm/helper.c
116
+++ b/target/arm/helper.c
117
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
118
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
119
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
120
.access = PL1_R, .type = ARM_CP_CONST,
121
- .resetvalue = cpu->id_aa64mmfr0 },
122
+ .resetvalue = cpu->isar.id_aa64mmfr0 },
123
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
124
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
125
.access = PL1_R, .type = ARM_CP_CONST,
126
- .resetvalue = cpu->id_aa64mmfr1 },
127
+ .resetvalue = cpu->isar.id_aa64mmfr1 },
128
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
129
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
130
.access = PL1_R, .type = ARM_CP_CONST,
131
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/kvm64.c
134
+++ b/target/arm/kvm64.c
135
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
136
ARM64_SYS_REG(3, 0, 0, 6, 0));
137
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
138
ARM64_SYS_REG(3, 0, 0, 6, 1));
139
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
140
+ ARM64_SYS_REG(3, 0, 0, 7, 0));
141
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
142
+ ARM64_SYS_REG(3, 0, 0, 7, 1));
143
144
/*
145
* Note that if AArch32 support is not present in the host,
146
--
147
2.19.2
148
149
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 29/37] target/arm: Add HCR_EL2 bits up to ARMv8.5
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Post v8.3 bits taken from SysReg_v85_xml-00bet8.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181203203839.757-3-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 22 +++++++++++++++++++++-
11
1 file changed, 21 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
18
#define HCR_TIDCP (1ULL << 20)
19
#define HCR_TACR (1ULL << 21)
20
#define HCR_TSW (1ULL << 22)
21
-#define HCR_TPC (1ULL << 23)
22
+#define HCR_TPCP (1ULL << 23)
23
#define HCR_TPU (1ULL << 24)
24
#define HCR_TTLB (1ULL << 25)
25
#define HCR_TVM (1ULL << 26)
26
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
27
#define HCR_CD (1ULL << 32)
28
#define HCR_ID (1ULL << 33)
29
#define HCR_E2H (1ULL << 34)
30
+#define HCR_TLOR (1ULL << 35)
31
+#define HCR_TERR (1ULL << 36)
32
+#define HCR_TEA (1ULL << 37)
33
+#define HCR_MIOCNCE (1ULL << 38)
34
+#define HCR_APK (1ULL << 40)
35
+#define HCR_API (1ULL << 41)
36
+#define HCR_NV (1ULL << 42)
37
+#define HCR_NV1 (1ULL << 43)
38
+#define HCR_AT (1ULL << 44)
39
+#define HCR_NV2 (1ULL << 45)
40
+#define HCR_FWB (1ULL << 46)
41
+#define HCR_FIEN (1ULL << 47)
42
+#define HCR_TID4 (1ULL << 49)
43
+#define HCR_TICAB (1ULL << 50)
44
+#define HCR_TOCU (1ULL << 52)
45
+#define HCR_TTLBIS (1ULL << 54)
46
+#define HCR_TTLBOS (1ULL << 55)
47
+#define HCR_ATA (1ULL << 56)
48
+#define HCR_DCT (1ULL << 57)
49
+
50
/*
51
* When we actually implement ARMv8.1-VHE we should add HCR_E2H to
52
* HCR_MASK and then clear it again if the feature bit is not set in
53
--
54
2.19.2
55
56
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Post v8.4 bits taken from SysReg_v85_xml-00bet8.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181203203839.757-4-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 10 ++++++++++
11
1 file changed, 10 insertions(+)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
18
#define SCR_ST (1U << 11)
19
#define SCR_TWI (1U << 12)
20
#define SCR_TWE (1U << 13)
21
+#define SCR_TLOR (1U << 14)
22
+#define SCR_TERR (1U << 15)
23
+#define SCR_APK (1U << 16)
24
+#define SCR_API (1U << 17)
25
+#define SCR_EEL2 (1U << 18)
26
+#define SCR_EASE (1U << 19)
27
+#define SCR_NMEA (1U << 20)
28
+#define SCR_FIEN (1U << 21)
29
+#define SCR_ENSCXT (1U << 25)
30
+#define SCR_ATA (1U << 26)
31
#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
32
#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
33
34
--
35
2.19.2
36
37
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 31/37] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The enable for TGE has already occurred within arm_hcr_el2_amo
4
and friends. Moreover, when E2H is also set, the sense is
5
supposed to be reversed, which has also already occurred within
6
the helpers.
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20181203203839.757-5-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper.c | 3 ---
14
1 file changed, 3 deletions(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
21
break;
22
};
23
24
- /* If HCR.TGE is set then HCR is treated as being 1 */
25
- hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
26
-
27
/* Perform a table-lookup for the target EL given the current state */
28
target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
29
30
--
31
2.19.2
32
33
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Because EL3 has a fixed execution mode, we can properly decide
4
which of the bits are RES{0,1}.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20181203203839.757-8-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 2 --
12
target/arm/helper.c | 14 +++++++++-----
13
2 files changed, 9 insertions(+), 7 deletions(-)
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
20
#define SCR_FIEN (1U << 21)
21
#define SCR_ENSCXT (1U << 25)
22
#define SCR_ATA (1U << 26)
23
-#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
24
-#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
25
26
/* Return the current FPSCR value. */
27
uint32_t vfp_get_fpscr(CPUARMState *env);
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
33
34
static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
35
{
36
- /* We only mask off bits that are RES0 both for AArch64 and AArch32.
37
- * For bits that vary between AArch32/64, code needs to check the
38
- * current execution mode before directly using the feature bit.
39
- */
40
- uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
41
+ /* Begin with base v8.0 state. */
42
+ uint32_t valid_mask = 0x3fff;
43
+
44
+ if (arm_el_is_aa64(env, 3)) {
45
+ value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
46
+ valid_mask &= ~SCR_NET;
47
+ } else {
48
+ valid_mask &= ~(SCR_RW | SCR_ST);
49
+ }
50
51
if (!arm_feature(env, ARM_FEATURE_EL2)) {
52
valid_mask &= ~SCR_HCE;
53
--
54
2.19.2
55
56
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD extension
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply
4
interpret the bits as if ARMv8.1-HPD is present without checking.
5
We will need a slightly different check for hpd for aarch32.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20181203203839.757-10-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu64.c | 4 ++++
13
target/arm/helper.c | 27 ++++++++++++++++++++-------
14
2 files changed, 24 insertions(+), 7 deletions(-)
15
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu64.c
19
+++ b/target/arm/cpu64.c
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
21
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
22
cpu->isar.id_aa64pfr0 = t;
23
24
+ t = cpu->isar.id_aa64mmfr1;
25
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
26
+ cpu->isar.id_aa64mmfr1 = t;
27
+
28
/* Replicate the same data to the 32-bit id registers. */
29
u = cpu->isar.id_isar5;
30
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
31
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/helper.c
34
+++ b/target/arm/helper.c
35
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
36
bool ttbr1_valid = true;
37
uint64_t descaddrmask;
38
bool aarch64 = arm_el_is_aa64(env, el);
39
+ bool hpd = false;
40
41
/* TODO:
42
* This code does not handle the different format TCR for VTCR_EL2.
43
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
44
if (tg == 2) { /* 16KB pages */
45
stride = 11;
46
}
47
+ if (aarch64) {
48
+ if (el > 1) {
49
+ hpd = extract64(tcr->raw_tcr, 24, 1);
50
+ } else {
51
+ hpd = extract64(tcr->raw_tcr, 41, 1);
52
+ }
53
+ }
54
} else {
55
/* We should only be here if TTBR1 is valid */
56
assert(ttbr1_valid);
57
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
58
if (tg == 1) { /* 16KB pages */
59
stride = 11;
60
}
61
+ if (aarch64) {
62
+ hpd = extract64(tcr->raw_tcr, 42, 1);
63
+ }
64
}
65
66
/* Here we should have set up all the parameters for the translation:
67
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
68
descaddr = descriptor & descaddrmask;
69
70
if ((descriptor & 2) && (level < 3)) {
71
- /* Table entry. The top five bits are attributes which may
72
+ /* Table entry. The top five bits are attributes which may
73
* propagate down through lower levels of the table (and
74
* which are all arranged so that 0 means "no effect", so
75
* we can gather them up by ORing in the bits at each level).
76
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
77
break;
78
}
79
/* Merge in attributes from table descriptors */
80
- attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
81
- attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
82
+ attrs |= nstable << 3; /* NS */
83
+ if (hpd) {
84
+ /* HPD disables all the table attributes except NSTable. */
85
+ break;
86
+ }
87
+ attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
88
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
89
* means "force PL1 access only", which means forcing AP[1] to 0.
90
*/
91
- if (extract32(tableattrs, 2, 1)) {
92
- attrs &= ~(1 << 4);
93
- }
94
- attrs |= nstable << 3; /* NS */
95
+ attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */
96
+ attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */
97
break;
98
}
99
/* Here descaddr is the final physical address, and attributes
100
--
101
2.19.2
102
103
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 34/37] target/arm: Implement the ARMv8.2-AA32HPD extension
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The bulk of the work here, beyond base HPD, is defining the
4
TTBCR2 register. In addition we must check TTBCR.T2E, which
5
is not present (RES0) for AArch64.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20181203203839.757-11-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 9 +++++++++
13
target/arm/cpu.c | 4 ++++
14
target/arm/helper.c | 37 +++++++++++++++++++++++++++++--------
15
3 files changed, 42 insertions(+), 8 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4)
22
FIELD(ID_ISAR6, SB, 12, 4)
23
FIELD(ID_ISAR6, SPECRES, 16, 4)
24
25
+FIELD(ID_MMFR4, SPECSEI, 0, 4)
26
+FIELD(ID_MMFR4, AC2, 4, 4)
27
+FIELD(ID_MMFR4, XNX, 8, 4)
28
+FIELD(ID_MMFR4, CNP, 12, 4)
29
+FIELD(ID_MMFR4, HPDS, 16, 4)
30
+FIELD(ID_MMFR4, LSM, 20, 4)
31
+FIELD(ID_MMFR4, CCIDX, 24, 4)
32
+FIELD(ID_MMFR4, EVT, 28, 4)
33
+
34
FIELD(ID_AA64ISAR0, AES, 4, 4)
35
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
36
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
37
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu.c
40
+++ b/target/arm/cpu.c
41
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
42
t = cpu->isar.id_isar6;
43
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
44
cpu->isar.id_isar6 = t;
45
+
46
+ t = cpu->id_mmfr4;
47
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
48
+ cpu->id_mmfr4 = t;
49
}
50
#endif
51
}
52
diff --git a/target/arm/helper.c b/target/arm/helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/helper.c
55
+++ b/target/arm/helper.c
56
@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
57
uint64_t value)
58
{
59
ARMCPU *cpu = arm_env_get_cpu(env);
60
+ TCR *tcr = raw_ptr(env, ri);
61
62
if (arm_feature(env, ARM_FEATURE_LPAE)) {
63
/* With LPAE the TTBCR could result in a change of ASID
64
@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
65
*/
66
tlb_flush(CPU(cpu));
67
}
68
+ /* Preserve the high half of TCR_EL1, set via TTBCR2. */
69
+ value = deposit64(tcr->raw_tcr, 0, 32, value);
70
vmsa_ttbcr_raw_write(env, ri, value);
71
}
72
73
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
74
REGINFO_SENTINEL
75
};
76
77
+/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
78
+ * qemu tlbs nor adjusting cached masks.
79
+ */
80
+static const ARMCPRegInfo ttbcr2_reginfo = {
81
+ .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
82
+ .access = PL1_RW, .type = ARM_CP_ALIAS,
83
+ .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
84
+ offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
85
+};
86
+
87
static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
88
uint64_t value)
89
{
90
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
91
} else {
92
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
93
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
94
+ /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
95
+ if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) {
96
+ define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
97
+ }
98
}
99
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
100
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
101
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
102
if (tg == 2) { /* 16KB pages */
103
stride = 11;
104
}
105
- if (aarch64) {
106
- if (el > 1) {
107
- hpd = extract64(tcr->raw_tcr, 24, 1);
108
- } else {
109
- hpd = extract64(tcr->raw_tcr, 41, 1);
110
- }
111
+ if (aarch64 && el > 1) {
112
+ hpd = extract64(tcr->raw_tcr, 24, 1);
113
+ } else {
114
+ hpd = extract64(tcr->raw_tcr, 41, 1);
115
+ }
116
+ if (!aarch64) {
117
+ /* For aarch32, hpd0 is not enabled without t2e as well. */
118
+ hpd &= extract64(tcr->raw_tcr, 6, 1);
119
}
120
} else {
121
/* We should only be here if TTBR1 is valid */
122
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
123
if (tg == 1) { /* 16KB pages */
124
stride = 11;
125
}
126
- if (aarch64) {
127
- hpd = extract64(tcr->raw_tcr, 42, 1);
128
+ hpd = extract64(tcr->raw_tcr, 42, 1);
129
+ if (!aarch64) {
130
+ /* For aarch32, hpd1 is not enabled without t2e as well. */
131
+ hpd &= extract64(tcr->raw_tcr, 6, 1);
132
}
133
}
134
135
--
136
2.19.2
137
138
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 35/37] target/arm: Introduce arm_hcr_el2_eff
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Replace arm_hcr_el2_{fmo,imo,amo} with a more general routine
4
that also takes SCR_EL3.NS (aka arm_is_secure_below_el3) into
5
account, as documented for the plethora of bits in HCR_EL2.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20181210150501.7990-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 67 +++++++++------------------------------
13
hw/intc/arm_gicv3_cpuif.c | 21 ++++++------
14
target/arm/helper.c | 66 ++++++++++++++++++++++++++++++++------
15
3 files changed, 83 insertions(+), 71 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure(CPUARMState *env)
22
}
23
#endif
24
25
+/**
26
+ * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
27
+ * E.g. when in secure state, fields in HCR_EL2 are suppressed,
28
+ * "for all purposes other than a direct read or write access of HCR_EL2."
29
+ * Not included here is HCR_RW.
30
+ */
31
+uint64_t arm_hcr_el2_eff(CPUARMState *env);
32
+
33
/* Return true if the specified exception level is running in AArch64 state. */
34
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
35
{
36
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu);
37
# define TARGET_VIRT_ADDR_SPACE_BITS 32
38
#endif
39
40
-/**
41
- * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO.
42
- * Depending on the values of HCR_EL2.E2H and TGE, this may be
43
- * "behaves as 1 for all purposes other than direct read/write" or
44
- * "behaves as 0 for all purposes other than direct read/write"
45
- */
46
-static inline bool arm_hcr_el2_imo(CPUARMState *env)
47
-{
48
- switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
49
- case HCR_TGE:
50
- return true;
51
- case HCR_TGE | HCR_E2H:
52
- return false;
53
- default:
54
- return env->cp15.hcr_el2 & HCR_IMO;
55
- }
56
-}
57
-
58
-/**
59
- * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO.
60
- */
61
-static inline bool arm_hcr_el2_fmo(CPUARMState *env)
62
-{
63
- switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
64
- case HCR_TGE:
65
- return true;
66
- case HCR_TGE | HCR_E2H:
67
- return false;
68
- default:
69
- return env->cp15.hcr_el2 & HCR_FMO;
70
- }
71
-}
72
-
73
-/**
74
- * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO.
75
- */
76
-static inline bool arm_hcr_el2_amo(CPUARMState *env)
77
-{
78
- switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
79
- case HCR_TGE:
80
- return true;
81
- case HCR_TGE | HCR_E2H:
82
- return false;
83
- default:
84
- return env->cp15.hcr_el2 & HCR_AMO;
85
- }
86
-}
87
-
88
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
89
unsigned int target_el)
90
{
91
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
92
bool secure = arm_is_secure(env);
93
bool pstate_unmasked;
94
int8_t unmasked = 0;
95
+ uint64_t hcr_el2;
96
97
/* Don't take exceptions if they target a lower EL.
98
* This check should catch any exceptions that would not be taken but left
99
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
100
return false;
101
}
102
103
+ hcr_el2 = arm_hcr_el2_eff(env);
104
+
105
switch (excp_idx) {
106
case EXCP_FIQ:
107
pstate_unmasked = !(env->daif & PSTATE_F);
108
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
109
break;
110
111
case EXCP_VFIQ:
112
- if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TGE)) {
113
+ if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
114
/* VFIQs are only taken when hypervized and non-secure. */
115
return false;
116
}
117
return !(env->daif & PSTATE_F);
118
case EXCP_VIRQ:
119
- if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TGE)) {
120
+ if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
121
/* VIRQs are only taken when hypervized and non-secure. */
122
return false;
123
}
124
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
125
* to the CPSR.F setting otherwise we further assess the state
126
* below.
127
*/
128
- hcr = arm_hcr_el2_fmo(env);
129
+ hcr = hcr_el2 & HCR_FMO;
130
scr = (env->cp15.scr_el3 & SCR_FIQ);
131
132
/* When EL3 is 32-bit, the SCR.FW bit controls whether the
133
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
134
* when setting the target EL, so it does not have a further
135
* affect here.
136
*/
137
- hcr = arm_hcr_el2_imo(env);
138
+ hcr = hcr_el2 & HCR_IMO;
139
scr = false;
140
break;
141
default:
142
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/hw/intc/arm_gicv3_cpuif.c
145
+++ b/hw/intc/arm_gicv3_cpuif.c
146
@@ -XXX,XX +XXX,XX @@ static bool icv_access(CPUARMState *env, int hcr_flags)
147
* * access if NS EL1 and either IMO or FMO == 1:
148
* CTLR, DIR, PMR, RPR
149
*/
150
- bool flagmatch = ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) ||
151
- ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env));
152
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
153
+ bool flagmatch = hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO);
154
155
return flagmatch && arm_current_el(env) == 1
156
&& !arm_is_secure_below_el3(env);
157
@@ -XXX,XX +XXX,XX @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
158
/* No need to include !IsSecure in route_*_to_el2 as it's only
159
* tested in cases where we know !IsSecure is true.
160
*/
161
- route_fiq_to_el2 = arm_hcr_el2_fmo(env);
162
- route_irq_to_el2 = arm_hcr_el2_imo(env);
163
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
164
+ route_fiq_to_el2 = hcr_el2 & HCR_FMO;
165
+ route_irq_to_el2 = hcr_el2 & HCR_IMO;
166
167
switch (arm_current_el(env)) {
168
case 3:
169
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env,
170
if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) {
171
switch (el) {
172
case 1:
173
- if (arm_is_secure_below_el3(env) ||
174
- (arm_hcr_el2_imo(env) == 0 && arm_hcr_el2_fmo(env) == 0)) {
175
+ /* Note that arm_hcr_el2_eff takes secure state into account. */
176
+ if ((arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) == 0) {
177
r = CP_ACCESS_TRAP_EL3;
178
}
179
break;
180
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gicv3_dir_access(CPUARMState *env,
181
static CPAccessResult gicv3_sgi_access(CPUARMState *env,
182
const ARMCPRegInfo *ri, bool isread)
183
{
184
- if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) &&
185
- arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) {
186
+ if (arm_current_el(env) == 1 &&
187
+ (arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) != 0) {
188
/* Takes priority over a possible EL3 trap */
189
return CP_ACCESS_TRAP_EL2;
190
}
191
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env,
192
if (env->cp15.scr_el3 & SCR_FIQ) {
193
switch (el) {
194
case 1:
195
- if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) {
196
+ if ((arm_hcr_el2_eff(env) & HCR_FMO) == 0) {
197
r = CP_ACCESS_TRAP_EL3;
198
}
199
break;
200
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gicv3_irq_access(CPUARMState *env,
201
if (env->cp15.scr_el3 & SCR_IRQ) {
202
switch (el) {
203
case 1:
204
- if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) {
205
+ if ((arm_hcr_el2_eff(env) & HCR_IMO) == 0) {
206
r = CP_ACCESS_TRAP_EL3;
207
}
208
break;
209
diff --git a/target/arm/helper.c b/target/arm/helper.c
210
index XXXXXXX..XXXXXXX 100644
211
--- a/target/arm/helper.c
212
+++ b/target/arm/helper.c
213
@@ -XXX,XX +XXX,XX @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
214
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
215
{
216
CPUState *cs = ENV_GET_CPU(env);
217
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
218
uint64_t ret = 0;
219
220
- if (arm_hcr_el2_imo(env)) {
221
+ if (hcr_el2 & HCR_IMO) {
222
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
223
ret |= CPSR_I;
224
}
225
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
226
}
227
}
228
229
- if (arm_hcr_el2_fmo(env)) {
230
+ if (hcr_el2 & HCR_FMO) {
231
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
232
ret |= CPSR_F;
233
}
234
@@ -XXX,XX +XXX,XX @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
235
hcr_write(env, NULL, value);
236
}
237
238
+/*
239
+ * Return the effective value of HCR_EL2.
240
+ * Bits that are not included here:
241
+ * RW (read from SCR_EL3.RW as needed)
242
+ */
243
+uint64_t arm_hcr_el2_eff(CPUARMState *env)
244
+{
245
+ uint64_t ret = env->cp15.hcr_el2;
246
+
247
+ if (arm_is_secure_below_el3(env)) {
248
+ /*
249
+ * "This register has no effect if EL2 is not enabled in the
250
+ * current Security state". This is ARMv8.4-SecEL2 speak for
251
+ * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
252
+ *
253
+ * Prior to that, the language was "In an implementation that
254
+ * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
255
+ * as if this field is 0 for all purposes other than a direct
256
+ * read or write access of HCR_EL2". With lots of enumeration
257
+ * on a per-field basis. In current QEMU, this is condition
258
+ * is arm_is_secure_below_el3.
259
+ *
260
+ * Since the v8.4 language applies to the entire register, and
261
+ * appears to be backward compatible, use that.
262
+ */
263
+ ret = 0;
264
+ } else if (ret & HCR_TGE) {
265
+ /* These bits are up-to-date as of ARMv8.4. */
266
+ if (ret & HCR_E2H) {
267
+ ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
268
+ HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
269
+ HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
270
+ HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE);
271
+ } else {
272
+ ret |= HCR_FMO | HCR_IMO | HCR_AMO;
273
+ }
274
+ ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
275
+ HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
276
+ HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
277
+ HCR_TLOR);
278
+ }
279
+
280
+ return ret;
281
+}
282
+
283
static const ARMCPRegInfo el2_cp_reginfo[] = {
284
{ .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
285
.type = ARM_CP_IO,
286
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
287
uint32_t cur_el, bool secure)
288
{
289
CPUARMState *env = cs->env_ptr;
290
- int rw;
291
- int scr;
292
- int hcr;
293
+ bool rw;
294
+ bool scr;
295
+ bool hcr;
296
int target_el;
297
/* Is the highest EL AArch64? */
298
- int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
299
+ bool is64 = arm_feature(env, ARM_FEATURE_AARCH64);
300
+ uint64_t hcr_el2;
301
302
if (arm_feature(env, ARM_FEATURE_EL3)) {
303
rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
304
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
305
rw = is64;
306
}
307
308
+ hcr_el2 = arm_hcr_el2_eff(env);
309
switch (excp_idx) {
310
case EXCP_IRQ:
311
scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
312
- hcr = arm_hcr_el2_imo(env);
313
+ hcr = hcr_el2 & HCR_IMO;
314
break;
315
case EXCP_FIQ:
316
scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
317
- hcr = arm_hcr_el2_fmo(env);
318
+ hcr = hcr_el2 & HCR_FMO;
319
break;
320
default:
321
scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
322
- hcr = arm_hcr_el2_amo(env);
323
+ hcr = hcr_el2 & HCR_AMO;
324
break;
325
};
326
327
--
328
2.19.2
329
330
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 36/37] target/arm: Use arm_hcr_el2_eff more places
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Since arm_hcr_el2_eff includes a check against
4
arm_is_secure_below_el3, we can often remove a
5
nearby check against secure state.
6
7
In some cases, sort the call to arm_hcr_el2_eff
8
to the end of a short-circuit logical sequence.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20181210150501.7990-3-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/helper.c | 12 +++++-------
16
target/arm/op_helper.c | 14 ++++++--------
17
2 files changed, 11 insertions(+), 15 deletions(-)
18
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
22
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
24
int el = arm_current_el(env);
25
bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) ||
26
(env->cp15.mdcr_el2 & MDCR_TDE) ||
27
- (env->cp15.hcr_el2 & HCR_TGE);
28
+ (arm_hcr_el2_eff(env) & HCR_TGE);
29
30
if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) {
31
return CP_ACCESS_TRAP_EL2;
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
33
int el = arm_current_el(env);
34
bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) ||
35
(env->cp15.mdcr_el2 & MDCR_TDE) ||
36
- (env->cp15.hcr_el2 & HCR_TGE);
37
+ (arm_hcr_el2_eff(env) & HCR_TGE);
38
39
if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) {
40
return CP_ACCESS_TRAP_EL2;
41
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
42
int el = arm_current_el(env);
43
bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) ||
44
(env->cp15.mdcr_el2 & MDCR_TDE) ||
45
- (env->cp15.hcr_el2 & HCR_TGE);
46
+ (arm_hcr_el2_eff(env) & HCR_TGE);
47
48
if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) {
49
return CP_ACCESS_TRAP_EL2;
50
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
51
if (disabled) {
52
/* route_to_el2 */
53
return (arm_feature(env, ARM_FEATURE_EL2)
54
- && !arm_is_secure(env)
55
- && (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1);
56
+ && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1);
57
}
58
59
/* Check CPACR.FPEN. */
60
@@ -XXX,XX +XXX,XX @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
61
* and CPS are treated as illegal mode changes.
62
*/
63
if (write_type == CPSRWriteByInstr &&
64
- (env->cp15.hcr_el2 & HCR_TGE) &&
65
(env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
66
- !arm_is_secure_below_el3(env)) {
67
+ (arm_hcr_el2_eff(env) & HCR_TGE)) {
68
return 1;
69
}
70
return 0;
71
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/op_helper.c
74
+++ b/target/arm/op_helper.c
75
@@ -XXX,XX +XXX,XX @@ void raise_exception(CPUARMState *env, uint32_t excp,
76
{
77
CPUState *cs = CPU(arm_env_get_cpu(env));
78
79
- if ((env->cp15.hcr_el2 & HCR_TGE) &&
80
- target_el == 1 && !arm_is_secure(env)) {
81
+ if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
82
/*
83
* Redirect NS EL1 exceptions to NS EL2. These are reported with
84
* their original syndrome register value, with the exception of
85
@@ -XXX,XX +XXX,XX @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
86
* No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
87
* bits will be zero indicating no trap.
88
*/
89
- if (cur_el < 2 && !arm_is_secure(env)) {
90
- mask = (is_wfe) ? HCR_TWE : HCR_TWI;
91
- if (env->cp15.hcr_el2 & mask) {
92
+ if (cur_el < 2) {
93
+ mask = is_wfe ? HCR_TWE : HCR_TWI;
94
+ if (arm_hcr_el2_eff(env) & mask) {
95
return 2;
96
}
97
}
98
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
99
exception_target_el(env));
100
}
101
102
- if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
103
+ if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) {
104
/* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
105
* We also want an EL2 guest to be able to forbid its EL1 from
106
* making PSCI calls into QEMU's "firmware" via HCR.TSC.
107
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env)
108
goto illegal_return;
109
}
110
111
- if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE)
112
- && !arm_is_secure_below_el3(env)) {
113
+ if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
114
goto illegal_return;
115
}
116
117
--
118
2.19.2
119
120
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 37/37] target/arm: Implement the ARMv8.1-LOR extension
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Provide a trivial implementation with zero limited ordering regions,
4
which causes the LDLAR and STLLR instructions to devolve into the
5
LDAR and STLR instructions from the base ARMv8.0 instruction set.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20181210150501.7990-4-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 5 +++
13
target/arm/cpu64.c | 1 +
14
target/arm/helper.c | 75 ++++++++++++++++++++++++++++++++++++++
15
target/arm/translate-a64.c | 12 ++++++
16
4 files changed, 93 insertions(+)
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
23
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
24
}
25
26
+static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
27
+{
28
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
29
+}
30
+
31
/*
32
* Forward to the above feature tests given an ARMCPU pointer.
33
*/
34
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/cpu64.c
37
+++ b/target/arm/cpu64.c
38
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
39
40
t = cpu->isar.id_aa64mmfr1;
41
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
42
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
43
cpu->isar.id_aa64mmfr1 = t;
44
45
/* Replicate the same data to the 32-bit id registers. */
46
diff --git a/target/arm/helper.c b/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/helper.c
49
+++ b/target/arm/helper.c
50
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
51
{
52
/* Begin with base v8.0 state. */
53
uint32_t valid_mask = 0x3fff;
54
+ ARMCPU *cpu = arm_env_get_cpu(env);
55
56
if (arm_el_is_aa64(env, 3)) {
57
value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
58
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
59
valid_mask &= ~SCR_SMD;
60
}
61
}
62
+ if (cpu_isar_feature(aa64_lor, cpu)) {
63
+ valid_mask |= SCR_TLOR;
64
+ }
65
66
/* Clear all-context RES0 bits. */
67
value &= valid_mask;
68
@@ -XXX,XX +XXX,XX @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
69
*/
70
valid_mask &= ~HCR_TSC;
71
}
72
+ if (cpu_isar_feature(aa64_lor, cpu)) {
73
+ valid_mask |= HCR_TLOR;
74
+ }
75
76
/* Clear RES0 bits. */
77
value &= valid_mask;
78
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
79
return pfr0;
80
}
81
82
+/* Shared logic between LORID and the rest of the LOR* registers.
83
+ * Secure state has already been delt with.
84
+ */
85
+static CPAccessResult access_lor_ns(CPUARMState *env)
86
+{
87
+ int el = arm_current_el(env);
88
+
89
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) {
90
+ return CP_ACCESS_TRAP_EL2;
91
+ }
92
+ if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) {
93
+ return CP_ACCESS_TRAP_EL3;
94
+ }
95
+ return CP_ACCESS_OK;
96
+}
97
+
98
+static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,
99
+ bool isread)
100
+{
101
+ if (arm_is_secure_below_el3(env)) {
102
+ /* Access ok in secure mode. */
103
+ return CP_ACCESS_OK;
104
+ }
105
+ return access_lor_ns(env);
106
+}
107
+
108
+static CPAccessResult access_lor_other(CPUARMState *env,
109
+ const ARMCPRegInfo *ri, bool isread)
110
+{
111
+ if (arm_is_secure_below_el3(env)) {
112
+ /* Access denied in secure mode. */
113
+ return CP_ACCESS_TRAP;
114
+ }
115
+ return access_lor_ns(env);
116
+}
117
+
118
void register_cp_regs_for_features(ARMCPU *cpu)
119
{
120
/* Register all the coprocessor registers based on feature bits */
121
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
122
define_one_arm_cp_reg(cpu, &sctlr);
123
}
124
125
+ if (cpu_isar_feature(aa64_lor, cpu)) {
126
+ /*
127
+ * A trivial implementation of ARMv8.1-LOR leaves all of these
128
+ * registers fixed at 0, which indicates that there are zero
129
+ * supported Limited Ordering regions.
130
+ */
131
+ static const ARMCPRegInfo lor_reginfo[] = {
132
+ { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
133
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
134
+ .access = PL1_RW, .accessfn = access_lor_other,
135
+ .type = ARM_CP_CONST, .resetvalue = 0 },
136
+ { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
137
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
138
+ .access = PL1_RW, .accessfn = access_lor_other,
139
+ .type = ARM_CP_CONST, .resetvalue = 0 },
140
+ { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
141
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
142
+ .access = PL1_RW, .accessfn = access_lor_other,
143
+ .type = ARM_CP_CONST, .resetvalue = 0 },
144
+ { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
145
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
146
+ .access = PL1_RW, .accessfn = access_lor_other,
147
+ .type = ARM_CP_CONST, .resetvalue = 0 },
148
+ { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
149
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
150
+ .access = PL1_R, .accessfn = access_lorid,
151
+ .type = ARM_CP_CONST, .resetvalue = 0 },
152
+ REGINFO_SENTINEL
153
+ };
154
+ define_arm_cp_regs(cpu, lor_reginfo);
155
+ }
156
+
157
if (cpu_isar_feature(aa64_sve, cpu)) {
158
define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
159
if (arm_feature(env, ARM_FEATURE_EL2)) {
160
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/arm/translate-a64.c
163
+++ b/target/arm/translate-a64.c
164
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
165
}
166
return;
167
168
+ case 0x8: /* STLLR */
169
+ if (!dc_isar_feature(aa64_lor, s)) {
170
+ break;
171
+ }
172
+ /* StoreLORelease is the same as Store-Release for QEMU. */
173
+ /* fall through */
174
case 0x9: /* STLR */
175
/* Generate ISS for non-exclusive accesses including LASR. */
176
if (rn == 31) {
177
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
178
disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
179
return;
180
181
+ case 0xc: /* LDLAR */
182
+ if (!dc_isar_feature(aa64_lor, s)) {
183
+ break;
184
+ }
185
+ /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
186
+ /* fall through */
187
case 0xd: /* LDAR */
188
/* Generate ISS for non-exclusive accesses including LASR. */
189
if (rn == 31) {
190
--
191
2.19.2
192
193
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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