First arm pullreq of the 2.11 cycle. I know I still have some

more stuff on my queue to review, but 36 patches is big enough

as it is; I expect I'll do another pull later this week.

The following changes since commit 32f0f68bb77289b75a82925f712bb52e16eac3ba:

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging (2017-09-01 17:28:54 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904

for you to fetch changes up to 1e35c4ce33a94cf78dbf639695cb877ef35920b0:

arm_gicv3_kvm: Fix compile warning (2017-09-04 12:09:32 +0100)

target-arm:

* collection of M profile cleanups and minor bugfixes

* loader: handle ELF files with overlapping zero-init data

* virt: allow PMU instantiation with userspace irqchip

* wdt_aspeed: Add support for the reset width register

* cpu: Define new cpu_transaction_failed() hook

* arm: Support generating CPU exceptions on memory

transaction failures (bus faults)

* Mark some SoC devices as not user-creatable

* arm: Fix aa64 ldp register writeback

* arm_gicv3_kvm: Fix compile warning

Andrew Jeffery (2):

watchdog: wdt_aspeed: Add support for the reset width register

aspeed_soc: Propagate silicon-rev to watchdog

Andrew Jones (4):

hw/arm/virt: add pmu interrupt state

target/arm/kvm: pmu: split init and set-irq stages

hw/arm/virt: allow pmu instantiation with userspace irqchip

target/arm/kvm: pmu: improve error handling

Peter Maydell (25):

target/arm: Use MMUAccessType enum rather than int

target/arm: Don't trap WFI/WFE for M profile

target/arm: Consolidate PMSA handling in get_phys_addr()

target/arm: Tighten up Thumb decode where new v8M insns will be

hw/intc/armv7m_nvic.c: Remove out of date comment

target/arm: Remove incorrect comment about MPU_CTRL

target/arm: Fix outdated comment about exception exit

target/arm: Define and use XPSR bit masks

target/arm: Don't store M profile PRIMASK and FAULTMASK in daif

target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR

target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR

target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed

target/arm: Create and use new function arm_v7m_is_handler_mode()

armv7m_nvic.h: Move from include/hw/arm to include/hw/intc

nvic: Implement "user accesses BusFault" SCS region behaviour

loader: Handle ELF files with overlapping zero-initialized data

loader: Ignore zero-sized ELF segments

memory.h: Move MemTxResult type to memattrs.h

cpu: Define new cpu_transaction_failed() hook

cputlb: Support generating CPU exceptions on memory transaction failures

boards.h: Define new flag ignore_memory_transaction_failures

hw/arm: Set ignore_memory_transaction_failures for most ARM boards

target/arm: Factor out fault delivery code

target/arm: Allow deliver_fault() caller to specify EA bit

target/arm: Implement new do_transaction_failed hook

hw/arm: use defined type name instead of hard-coded string

Pranith Kumar (1):

arm_gicv3_kvm: Fix compile warning

Move the in-kernel-irqchip test to only guard the set-irq

stage, not the init stage of the PMU. Also add the PMU to

the KVM device irq line synchronization to enable its use.

Reviewed-by: Christoffer Dall <cdall@linaro.org>

Message-id: 1500471597-2517-4-git-send-email-drjones@redhat.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

hw/arm/virt.c | 3 ++-

target/arm/kvm.c | 6 +++++-

target/arm/kvm64.c | 3 +--

3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)

return;

}

if (kvm_enabled()) {

- if (!kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ))) {

+ if (kvm_irqchip_in_kernel() &&

+ !kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ))) {

return;

}

if (!kvm_arm_pmu_init(cpu)) {

diff --git a/target/arm/kvm.c b/target/arm/kvm.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/kvm.c

+++ b/target/arm/kvm.c

@@ -XXX,XX +XXX,XX @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)

switched_level &= ~KVM_ARM_DEV_EL1_PTIMER;

}

- /* XXX PMU IRQ is missing */

+ if (switched_level & KVM_ARM_DEV_PMU) {

+ qemu_set_irq(cpu->pmu_interrupt,

+ !!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU));

+ switched_level &= ~KVM_ARM_DEV_PMU;

+ }

if (switched_level) {

qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n",

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/kvm64.c

+++ b/target/arm/kvm64.c

@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)

if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {

cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;

}

- if (!kvm_irqchip_in_kernel() ||

- !kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {

+ if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {

cpu->has_pmu = false;

}

if (cpu->has_pmu) {

2.7.4

From: Andrew Jones <drjones@redhat.com>

If a KVM PMU init or set-irq attr call fails we just silently stop

the PMU DT node generation. The only way they could fail, though,

is if the attr's respective KVM has-attr call fails. But that should

never happen if KVM advertises the PMU capability, because both

attrs have been available since the capability was introduced. Let's

just abort if this should-never-happen stuff does happen, because,

if it does, then something is obviously horribly wrong.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: Christoffer Dall <cdall@linaro.org>

Message-id: 1500471597-2517-5-git-send-email-drjones@redhat.com

target/arm/kvm_arm.h | 15 ++++-----------

hw/arm/virt.c | 9 +++------

target/arm/kvm32.c | 3 +--

target/arm/kvm64.c | 28 ++++++++++++++++++++--------

4 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h

--- a/target/arm/kvm_arm.h

+++ b/target/arm/kvm_arm.h

@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu);

int kvm_arm_vgic_probe(void);

-int kvm_arm_pmu_set_irq(CPUState *cs, int irq);

-int kvm_arm_pmu_init(CPUState *cs);

+void kvm_arm_pmu_set_irq(CPUState *cs, int irq);

+void kvm_arm_pmu_init(CPUState *cs);

#else

@@ -XXX,XX +XXX,XX @@ static inline int kvm_arm_vgic_probe(void)

return 0;

-static inline int kvm_arm_pmu_set_irq(CPUState *cs, int irq)

-{

- return 0;

-}

-

-static inline int kvm_arm_pmu_init(CPUState *cs)

-{

- return 0;

-}

+static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}

+static inline void kvm_arm_pmu_init(CPUState *cs) {}

#endif

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)

return;

}

if (kvm_enabled()) {

- if (kvm_irqchip_in_kernel() &&

- !kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ))) {

- return;

- }

- if (!kvm_arm_pmu_init(cpu)) {

- return;

+ if (kvm_irqchip_in_kernel()) {

+ kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));

}

+ kvm_arm_pmu_init(cpu);

}

-int kvm_arm_pmu_set_irq(CPUState *cs, int irq)

+void kvm_arm_pmu_set_irq(CPUState *cs, int irq)

{

qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);

- return 0;

}

int kvm_arm_pmu_init(CPUState *cs)

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/kvm64.c

+++ b/target/arm/kvm64.c

@@ -XXX,XX +XXX,XX @@ static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr)

err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);

if (err != 0) {

+ error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err));

return false;

err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr);

- if (err < 0) {

- fprintf(stderr, "KVM_SET_DEVICE_ATTR failed: %s\n",

- strerror(-err));

- abort();

+ if (err != 0) {

+ error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err));

+ return false;

return true;

}

-int kvm_arm_pmu_init(CPUState *cs)

+void kvm_arm_pmu_init(CPUState *cs)

{

struct kvm_device_attr attr = {

.group = KVM_ARM_VCPU_PMU_V3_CTRL,

.attr = KVM_ARM_VCPU_PMU_V3_INIT,

};

- return kvm_arm_pmu_set_attr(cs, &attr);

+ if (!ARM_CPU(cs)->has_pmu) {

+ return;

+ }

+ if (!kvm_arm_pmu_set_attr(cs, &attr)) {

+ error_report("failed to init PMU");

+ abort();

+ }

}

-int kvm_arm_pmu_set_irq(CPUState *cs, int irq)

+void kvm_arm_pmu_set_irq(CPUState *cs, int irq)

{

struct kvm_device_attr attr = {

.group = KVM_ARM_VCPU_PMU_V3_CTRL,

@@ -XXX,XX +XXX,XX @@ int kvm_arm_pmu_set_irq(CPUState *cs, int irq)

.attr = KVM_ARM_VCPU_PMU_V3_IRQ,

};

- return kvm_arm_pmu_set_attr(cs, &attr);

+ if (!ARM_CPU(cs)->has_pmu) {

+ return;

+ }

+ if (!kvm_arm_pmu_set_attr(cs, &attr)) {

+ error_report("failed to set irq for PMU");

+ abort();

+ }

}

static inline void set_feature(uint64_t *features, int feature)

2.7.4

In the ARM get_phys_addr() code, switch to using the MMUAccessType

enum and its MMU_* values rather than int and literal 0/1/2.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1501692241-23310-2-git-send-email-peter.maydell@linaro.org

target/arm/internals.h | 3 ++-

target/arm/helper.c | 30 +++++++++++++++---------------

2 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h

--- a/target/arm/internals.h

+++ b/target/arm/internals.h

@@ -XXX,XX +XXX,XX @@ struct ARMMMUFaultInfo {

};

/* Do a page table walk and add page to TLB if possible */

-bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,

+bool arm_tlb_fill(CPUState *cpu, vaddr address,

+ MMUAccessType access_type, int mmu_idx,

uint32_t *fsr, ARMMMUFaultInfo *fi);

/* Return true if the stage 1 translation regime is using LPAE format page

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

#ifndef CONFIG_USER_ONLY

static bool get_phys_addr(CPUARMState *env, target_ulong address,

- int access_type, ARMMMUIdx mmu_idx,

+ MMUAccessType access_type, ARMMMUIdx mmu_idx,

hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

target_ulong *page_size, uint32_t *fsr,

ARMMMUFaultInfo *fi);

static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

- int access_type, ARMMMUIdx mmu_idx,

+ MMUAccessType access_type, ARMMMUIdx mmu_idx,

hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

target_ulong *page_size_ptr, uint32_t *fsr,

ARMMMUFaultInfo *fi);

@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,

}

static uint64_t do_ats_write(CPUARMState *env, uint64_t value,

- int access_type, ARMMMUIdx mmu_idx)

+ MMUAccessType access_type, ARMMMUIdx mmu_idx)

{

hwaddr phys_addr;

target_ulong page_size;

@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,

static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

{

- int access_type = ri->opc2 & 1;

+ MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

uint64_t par64;

ARMMMUIdx mmu_idx;

int el = arm_current_el(env);

@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,

uint64_t value)

{

- int access_type = ri->opc2 & 1;

+ MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

uint64_t par64;

par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);

@@ -XXX,XX +XXX,XX @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,

static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,

uint64_t value)

{

- int access_type = ri->opc2 & 1;

+ MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

ARMMMUIdx mmu_idx;

int secure = arm_is_secure_below_el3(env);

@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,

}

static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,

- int access_type, ARMMMUIdx mmu_idx,

+ MMUAccessType access_type, ARMMMUIdx mmu_idx,

hwaddr *phys_ptr, int *prot,

target_ulong *page_size, uint32_t *fsr,

ARMMMUFaultInfo *fi)

@@ -XXX,XX +XXX,XX @@ do_fault:

}

static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,

- int access_type, ARMMMUIdx mmu_idx,

+ MMUAccessType access_type, ARMMMUIdx mmu_idx,

hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

target_ulong *page_size, uint32_t *fsr,

ARMMMUFaultInfo *fi)

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,

if (pxn && !regime_is_user(env, mmu_idx)) {

xn = 1;

}

- if (xn && access_type == 2)

+ if (xn && access_type == MMU_INST_FETCH)

goto do_fault;

if (arm_feature(env, ARM_FEATURE_V6K) &&

@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,

}

static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

- int access_type, ARMMMUIdx mmu_idx,

+ MMUAccessType access_type, ARMMMUIdx mmu_idx,

hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

target_ulong *page_size_ptr, uint32_t *fsr,

ARMMMUFaultInfo *fi)

@@ -XXX,XX +XXX,XX @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address)

}

static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,

- int access_type, ARMMMUIdx mmu_idx,

+ MMUAccessType access_type, ARMMMUIdx mmu_idx,

hwaddr *phys_ptr, int *prot, uint32_t *fsr)

{

ARMCPU *cpu = arm_env_get_cpu(env);

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,

}

static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

- int access_type, ARMMMUIdx mmu_idx,

+ MMUAccessType access_type, ARMMMUIdx mmu_idx,

hwaddr *phys_ptr, int *prot, uint32_t *fsr)

{

int n;

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

return true;

}

- if (access_type == 2) {

+ if (access_type == MMU_INST_FETCH) {

mask = env->cp15.pmsav5_insn_ap;

} else {

mask = env->cp15.pmsav5_data_ap;

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

* @fsr: set to the DFSR/IFSR value on failure

*/

static bool get_phys_addr(CPUARMState *env, target_ulong address,

- int access_type, ARMMMUIdx mmu_idx,

+ MMUAccessType access_type, ARMMMUIdx mmu_idx,

hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

target_ulong *page_size, uint32_t *fsr,

ARMMMUFaultInfo *fi)

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,

* fsr with ARM DFSR/IFSR fault register format value on failure.

*/

bool arm_tlb_fill(CPUState *cs, vaddr address,

- int access_type, int mmu_idx, uint32_t *fsr,

+ MMUAccessType access_type, int mmu_idx, uint32_t *fsr,

ARMMMUFaultInfo *fi)

{

ARMCPU *cpu = ARM_CPU(cs);

2.7.4

From: Pranith Kumar <bobby.prani@gmail.com>

Fix the following warning:

/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses]

if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {

^ ~

/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses after the '!' to evaluate the bitwise operator first

if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {

^

/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses around left hand side expression to silence this warning

if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {

^

This logic error meant we were not setting the PTZ

bit when we should -- luckily as the comment suggests

this wouldn't have had any effects beyond making GIC

initialization take a little longer.

Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>

Message-id: 20170829173226.7625-1-bobby.prani@gmail.com

Cc: qemu-stable@nongnu.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/intc/arm_gicv3_kvm.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c

--- a/hw/intc/arm_gicv3_kvm.c

+++ b/hw/intc/arm_gicv3_kvm.c

@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_put(GICv3State *s)

kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true);

reg64 = c->gicr_pendbaser;

- if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {

+ if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {

/* Setting PTZ is advised if LPIs are disabled, to reduce

* GIC initialization time.

*/

2.7.4

From: Richard Henderson <richard.henderson@linaro.org>

For "ldp x0, x1, [x0]", if the second load is on a second page and

the second page is unmapped, the exception would be raised with x0

already modified. This means the instruction couldn't be restarted.

Cc: qemu-arm@nongnu.org

Cc: qemu-stable@nongnu.org

Reported-by: Andrew <andrew@fubar.geek.nz>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20170825224833.4463-1-richard.henderson@linaro.org

Fixes: https://bugs.launchpad.net/qemu/+bug/1713066

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

[PMM: tweaked comment format]

target/arm/translate-a64.c | 29 +++++++++++++++++------------

1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)

} else {

do_fp_st(s, rt, tcg_addr, size);

}

- } else {

- TCGv_i64 tcg_rt = cpu_reg(s, rt);

- if (is_load) {

- do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,

- false, 0, false, false);

- } else {

- do_gpr_st(s, tcg_rt, tcg_addr, size,

- false, 0, false, false);

- }

- tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);

- if (is_vector) {

+ tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);

if (is_load) {

do_fp_ld(s, rt2, tcg_addr, size);

} else {

do_fp_st(s, rt2, tcg_addr, size);

}

} else {

+ TCGv_i64 tcg_rt = cpu_reg(s, rt);

TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);

+

if (is_load) {

+ TCGv_i64 tmp = tcg_temp_new_i64();

+

+ /* Do not modify tcg_rt before recognizing any exception

+ * from the second load.

+ */

+ do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false,

+ false, 0, false, false);

+ tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);

do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false,

false, 0, false, false);

+

+ tcg_gen_mov_i64(tcg_rt, tmp);

+ tcg_temp_free_i64(tmp);

} else {

+ do_gpr_st(s, tcg_rt, tcg_addr, size,

+ false, 0, false, false);

+ tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);

do_gpr_st(s, tcg_rt2, tcg_addr, size,

false, 0, false, false);

}

2.7.4

hw/arm/armv7m.c | 4 ++--

hw/arm/exynos4210.c | 4 ++--

hw/arm/highbank.c | 11 +++++++----

hw/arm/realview.c | 6 ++++--

hw/arm/vexpress.c | 6 ++++--

hw/arm/xilinx_zynq.c | 14 ++++++++------

6 files changed, 27 insertions(+), 18 deletions(-)

diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c

--- a/hw/arm/armv7m.c

+++ b/hw/arm/armv7m.c

@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)

&error_abort);

memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);

- object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");

+ object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC);

qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());

object_property_add_alias(obj, "num-irq",

OBJECT(&s->nvic), "num-irq", &error_abort);

@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,

cpu_model = "cortex-m3";

- armv7m = qdev_create(NULL, "armv7m");

+ armv7m = qdev_create(NULL, TYPE_ARMV7M);

qdev_prop_set_uint32(armv7m, "num-irq", num_irq);

qdev_prop_set_string(armv7m, "cpu-model", cpu_model);

object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/exynos4210.c

+++ b/hw/arm/exynos4210.c

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/arm.h"

#include "hw/loader.h"

#include "hw/arm/exynos4210.h"

-#include "hw/sd/sd.h"

+#include "hw/sd/sdhci.h"

#include "hw/usb/hcd-ehci.h"

#define EXYNOS4210_CHIPID_ADDR 0x10000000

@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)

BlockBackend *blk;

DriveInfo *di;

- dev = qdev_create(NULL, "generic-sdhci");

+ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);

qdev_prop_set_uint32(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);

qdev_init_nofail(dev);