[Qemu-devel] [PULL 0/7] target-arm queue
[Qemu-devel] [PULL v2 0/6] target-arm queue
1
ARM queue for 2.10: all M profile bugfixes...
1
Respin to fix some accidental wrong Author lines, no content
2
changes.
2
3
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 25dd0e77898c3e10796d4cbeb35e8af5ba6ce975:
6
The following changes since commit 0bbba1665ca2e7f1c80d4797077fe57bad58898e:
7
7
8
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging (2017-07-31 11:27:43 +0100)
8
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-october-2018-part-4' into staging (2018-10-30 10:45:49 +0000)
9
9
10
are available in the git repository at:
10
are available in the Git repository at:
11
11
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170731
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181030
13
13
14
for you to fetch changes up to 89cbc3778a3d61761e2231e740269218c9a8a41d:
14
for you to fetch changes up to 1f5a65a188210509bfb0c025fc91635c8436b98a:
15
15
16
hw/mps2_scc: fix incorrect properties (2017-07-31 13:11:56 +0100)
16
tests/boot-serial-test: Add microbit board testcase (2018-10-30 13:20:18 +0000)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* fix broken properties on MPS2 SCC device
20
* microbit: Add the UART to our nRF51 SoC model
21
* fix MPU trace handling of write vs exec
21
* Add a virtual Xilinx Versal board "xlnx-versal-virt"
22
* fix MPU M profile bugs:
22
* hw/arm/virt: Set VIRT_COMPAT_3_0 compat
23
- not handling system space or PPB region correctly
24
- not resetting state
25
- not migrating MPU_RNR
26
23
27
----------------------------------------------------------------
24
----------------------------------------------------------------
28
Peter Maydell (6):
25
Edgar E. Iglesias (2):
29
target/arm: Correct MPU trace handling of write vs execute
26
hw/arm: versal: Add a model of Xilinx Versal SoC
30
target/arm: Don't do MPU lookups for addresses in M profile PPB region
27
hw/arm: versal: Add a virtual Xilinx Versal board
31
target/arm: Don't allow guest to make System space executable for M profile
32
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
33
target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset
34
target/arm: Migrate MPU_RNR register state for M profile cores
35
28
36
Philippe Mathieu-Daudé (1):
29
Eric Auger (1):
37
hw/mps2_scc: fix incorrect properties
30
hw/arm/virt: Set VIRT_COMPAT_3_0 compat
38
31
39
target/arm/cpu.h | 3 +--
32
Julia Suvorova (3):
40
hw/intc/armv7m_nvic.c | 14 +++++-----
33
hw/char: Implement nRF51 SoC UART
41
hw/misc/mps2-scc.c | 4 +--
34
hw/arm/nrf51_soc: Connect UART to nRF51 SoC
42
target/arm/cpu.c | 14 ++++++++++
35
tests/boot-serial-test: Add microbit board testcase
43
target/arm/helper.c | 71 ++++++++++++++++++++++++++++++++++-----------------
44
target/arm/machine.c | 30 +++++++++++++++++++++-
45
6 files changed, 101 insertions(+), 35 deletions(-)
46
36
37
hw/arm/Makefile.objs | 1 +
38
hw/char/Makefile.objs | 1 +
39
include/hw/arm/nrf51_soc.h | 3 +
40
include/hw/arm/xlnx-versal.h | 122 +++++++++
41
include/hw/char/nrf51_uart.h | 78 ++++++
42
hw/arm/microbit.c | 2 +
43
hw/arm/nrf51_soc.c | 20 ++
44
hw/arm/virt.c | 4 +
45
hw/arm/xlnx-versal-virt.c | 493 ++++++++++++++++++++++++++++++++++++
46
hw/arm/xlnx-versal.c | 323 +++++++++++++++++++++++
47
hw/char/nrf51_uart.c | 330 ++++++++++++++++++++++++
48
tests/boot-serial-test.c | 19 ++
49
default-configs/aarch64-softmmu.mak | 1 +
50
hw/char/trace-events | 4 +
51
14 files changed, 1401 insertions(+)
52
create mode 100644 include/hw/arm/xlnx-versal.h
53
create mode 100644 include/hw/char/nrf51_uart.h
54
create mode 100644 hw/arm/xlnx-versal-virt.c
55
create mode 100644 hw/arm/xlnx-versal.c
56
create mode 100644 hw/char/nrf51_uart.c
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/7] target/arm: Correct MPU trace handling of write vs execute
Deleted patch
1
Correct off-by-one bug in the PSMAv7 MPU tracing where it would print
2
a write access as "reading", an insn fetch as "writing", and a read
3
access as "execute".
4
1
5
Since we have an MMUAccessType enum now, we can make the code clearer
6
in the process by using that rather than the raw 0/1/2 values.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <rth@twiddle.net>
10
Message-id: 1500906792-18010-1-git-send-email-peter.maydell@linaro.org
11
---
12
target/arm/helper.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
20
phys_ptr, prot, fsr);
21
qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32
22
" mmu_idx %u -> %s (prot %c%c%c)\n",
23
- access_type == 1 ? "reading" :
24
- (access_type == 2 ? "writing" : "execute"),
25
+ access_type == MMU_DATA_LOAD ? "reading" :
26
+ (access_type == MMU_DATA_STORE ? "writing" : "execute"),
27
(uint32_t)address, mmu_idx,
28
ret ? "Miss" : "Hit",
29
*prot & PAGE_READ ? 'r' : '-',
30
--
31
2.7.4
32
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/7] target/arm: Don't do MPU lookups for addresses in M profile PPB region
Deleted patch
1
The M profile PMSAv7 specification says that if the address being looked
2
up is in the PPB region (0xe0000000 - 0xe00fffff) then we do not use
3
the MPU regions but always use the default memory map. Implement this
4
(we were previously behaving like an R profile PMSAv7, which does not
5
special case this).
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 1501153150-19984-2-git-send-email-peter.maydell@linaro.org
10
---
11
target/arm/helper.c | 17 ++++++++++++++++-
12
1 file changed, 16 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu,
19
}
20
}
21
22
+static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
23
+{
24
+ /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
25
+ return arm_feature(env, ARM_FEATURE_M) &&
26
+ extract32(address, 20, 12) == 0xe00;
27
+}
28
+
29
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
30
int access_type, ARMMMUIdx mmu_idx,
31
hwaddr *phys_ptr, int *prot, uint32_t *fsr)
32
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
33
*phys_ptr = address;
34
*prot = 0;
35
36
- if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
37
+ if (regime_translation_disabled(env, mmu_idx) ||
38
+ m_is_ppb_region(env, address)) {
39
+ /* MPU disabled or M profile PPB access: use default memory map.
40
+ * The other case which uses the default memory map in the
41
+ * v7M ARM ARM pseudocode is exception vector reads from the vector
42
+ * table. In QEMU those accesses are done in arm_v7m_load_vector(),
43
+ * which always does a direct read using address_space_ldl(), rather
44
+ * than going via this function, so we don't need to check that here.
45
+ */
46
get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
47
} else { /* MPU enabled */
48
for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
49
--
50
2.7.4
51
52
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/7] target/arm: Don't allow guest to make System space executable for M profile
Deleted patch
1
For an M profile v7PMSA, the system space (0xe0000000 - 0xffffffff) can
2
never be executable, even if the guest tries to set the MPU registers
3
up that way. Enforce this restriction.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 1501153150-19984-3-git-send-email-peter.maydell@linaro.org
8
---
9
target/arm/helper.c | 16 +++++++++++++++-
10
1 file changed, 15 insertions(+), 1 deletion(-)
11
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.c
15
+++ b/target/arm/helper.c
16
@@ -XXX,XX +XXX,XX @@ static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
17
extract32(address, 20, 12) == 0xe00;
18
}
19
20
+static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
21
+{
22
+ /* True if address is in the M profile system region
23
+ * 0xe0000000 - 0xffffffff
24
+ */
25
+ return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
26
+}
27
+
28
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
29
int access_type, ARMMMUIdx mmu_idx,
30
hwaddr *phys_ptr, int *prot, uint32_t *fsr)
31
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
32
get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
33
} else { /* a MPU hit! */
34
uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
35
+ uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
36
+
37
+ if (m_is_system_region(env, address)) {
38
+ /* System space is always execute never */
39
+ xn = 1;
40
+ }
41
42
if (is_user) { /* User mode AP bit decoding */
43
switch (ap) {
44
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
45
}
46
47
/* execute never */
48
- if (env->pmsav7.dracr[n] & (1 << 12)) {
49
+ if (xn) {
50
*prot &= ~PAGE_EXEC;
51
}
52
}
53
--
54
2.7.4
55
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/7] target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
Deleted patch
1
Almost all of the PMSAv7 state is in the pmsav7 substruct of
2
the ARM CPU state structure. The exception is the region
3
number register, which is in cp15.c6_rgnr. This exception
4
is a bit odd for M profile, which otherwise generally does
5
not store state in the cp15 substruct.
6
1
7
Rename cp15.c6_rgnr to pmsav7.rnr accordingly.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 1501153150-19984-4-git-send-email-peter.maydell@linaro.org
12
---
13
target/arm/cpu.h | 3 +--
14
hw/intc/armv7m_nvic.c | 14 +++++++-------
15
target/arm/helper.c | 6 +++---
16
target/arm/machine.c | 2 +-
17
4 files changed, 12 insertions(+), 13 deletions(-)
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
22
+++ b/target/arm/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
24
uint64_t par_el[4];
25
};
26
27
- uint32_t c6_rgnr;
28
-
29
uint32_t c9_insn; /* Cache lockdown registers. */
30
uint32_t c9_data;
31
uint64_t c9_pmcr; /* performance monitor control register */
32
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
33
uint32_t *drbar;
34
uint32_t *drsr;
35
uint32_t *dracr;
36
+ uint32_t rnr;
37
} pmsav7;
38
39
void *nvic;
40
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/intc/armv7m_nvic.c
43
+++ b/hw/intc/armv7m_nvic.c
44
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
45
case 0xd94: /* MPU_CTRL */
46
return cpu->env.v7m.mpu_ctrl;
47
case 0xd98: /* MPU_RNR */
48
- return cpu->env.cp15.c6_rgnr;
49
+ return cpu->env.pmsav7.rnr;
50
case 0xd9c: /* MPU_RBAR */
51
case 0xda4: /* MPU_RBAR_A1 */
52
case 0xdac: /* MPU_RBAR_A2 */
53
case 0xdb4: /* MPU_RBAR_A3 */
54
{
55
- int region = cpu->env.cp15.c6_rgnr;
56
+ int region = cpu->env.pmsav7.rnr;
57
58
if (region >= cpu->pmsav7_dregion) {
59
return 0;
60
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
61
case 0xdb0: /* MPU_RASR_A2 */
62
case 0xdb8: /* MPU_RASR_A3 */
63
{
64
- int region = cpu->env.cp15.c6_rgnr;
65
+ int region = cpu->env.pmsav7.rnr;
66
67
if (region >= cpu->pmsav7_dregion) {
68
return 0;
69
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
70
PRIu32 "/%" PRIu32 "\n",
71
value, cpu->pmsav7_dregion);
72
} else {
73
- cpu->env.cp15.c6_rgnr = value;
74
+ cpu->env.pmsav7.rnr = value;
75
}
76
break;
77
case 0xd9c: /* MPU_RBAR */
78
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
79
region, cpu->pmsav7_dregion);
80
return;
81
}
82
- cpu->env.cp15.c6_rgnr = region;
83
+ cpu->env.pmsav7.rnr = region;
84
} else {
85
- region = cpu->env.cp15.c6_rgnr;
86
+ region = cpu->env.pmsav7.rnr;
87
}
88
89
if (region >= cpu->pmsav7_dregion) {
90
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
91
case 0xdb0: /* MPU_RASR_A2 */
92
case 0xdb8: /* MPU_RASR_A3 */
93
{
94
- int region = cpu->env.cp15.c6_rgnr;
95
+ int region = cpu->env.pmsav7.rnr;
96
97
if (region >= cpu->pmsav7_dregion) {
98
return;
99
diff --git a/target/arm/helper.c b/target/arm/helper.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/helper.c
102
+++ b/target/arm/helper.c
103
@@ -XXX,XX +XXX,XX @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
104
return 0;
105
}
106
107
- u32p += env->cp15.c6_rgnr;
108
+ u32p += env->pmsav7.rnr;
109
return *u32p;
110
}
111
112
@@ -XXX,XX +XXX,XX @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
113
return;
114
}
115
116
- u32p += env->cp15.c6_rgnr;
117
+ u32p += env->pmsav7.rnr;
118
tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
119
*u32p = value;
120
}
121
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
122
.readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
123
{ .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
124
.access = PL1_RW,
125
- .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
126
+ .fieldoffset = offsetof(CPUARMState, pmsav7.rnr),
127
.writefn = pmsav7_rgnr_write },
128
REGINFO_SENTINEL
129
};
130
diff --git a/target/arm/machine.c b/target/arm/machine.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/target/arm/machine.c
133
+++ b/target/arm/machine.c
134
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
135
{
136
ARMCPU *cpu = opaque;
137
138
- return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
139
+ return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion;
140
}
141
142
static const VMStateDescription vmstate_pmsav7 = {
143
--
144
2.7.4
145
146
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/7] target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset
Deleted patch
1
When the PMSAv7 implementation was originally added it was for R profile
2
CPUs only, and reset was handled using the cpreg .resetfn hooks.
3
Unfortunately for M profile cores this doesn't work, because they do
4
not register any cpregs. Move the reset handling into arm_cpu_reset(),
5
where it will work for both R profile and M profile cores.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 1501153150-19984-5-git-send-email-peter.maydell@linaro.org
10
---
11
target/arm/cpu.c | 14 ++++++++++++++
12
target/arm/helper.c | 28 ++++++++++++----------------
13
2 files changed, 26 insertions(+), 16 deletions(-)
14
15
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.c
18
+++ b/target/arm/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
20
21
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
22
#endif
23
+
24
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
25
+ arm_feature(env, ARM_FEATURE_V7)) {
26
+ if (cpu->pmsav7_dregion > 0) {
27
+ memset(env->pmsav7.drbar, 0,
28
+ sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
29
+ memset(env->pmsav7.drsr, 0,
30
+ sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
31
+ memset(env->pmsav7.dracr, 0,
32
+ sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
33
+ }
34
+ env->pmsav7.rnr = 0;
35
+ }
36
+
37
set_flush_to_zero(1, &env->vfp.standard_fp_status);
38
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
39
set_default_nan_mode(1, &env->vfp.standard_fp_status);
40
diff --git a/target/arm/helper.c b/target/arm/helper.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/helper.c
43
+++ b/target/arm/helper.c
44
@@ -XXX,XX +XXX,XX @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
45
*u32p = value;
46
}
47
48
-static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
49
-{
50
- ARMCPU *cpu = arm_env_get_cpu(env);
51
- uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
52
-
53
- if (!u32p) {
54
- return;
55
- }
56
-
57
- memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
58
-}
59
-
60
static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
61
uint64_t value)
62
{
63
@@ -XXX,XX +XXX,XX @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
64
}
65
66
static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
67
+ /* Reset for all these registers is handled in arm_cpu_reset(),
68
+ * because the PMSAv7 is also used by M-profile CPUs, which do
69
+ * not register cpregs but still need the state to be reset.
70
+ */
71
{ .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
72
.access = PL1_RW, .type = ARM_CP_NO_RAW,
73
.fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
74
- .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
75
+ .readfn = pmsav7_read, .writefn = pmsav7_write,
76
+ .resetfn = arm_cp_reset_ignore },
77
{ .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
78
.access = PL1_RW, .type = ARM_CP_NO_RAW,
79
.fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
80
- .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
81
+ .readfn = pmsav7_read, .writefn = pmsav7_write,
82
+ .resetfn = arm_cp_reset_ignore },
83
{ .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
84
.access = PL1_RW, .type = ARM_CP_NO_RAW,
85
.fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
86
- .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
87
+ .readfn = pmsav7_read, .writefn = pmsav7_write,
88
+ .resetfn = arm_cp_reset_ignore },
89
{ .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
90
.access = PL1_RW,
91
.fieldoffset = offsetof(CPUARMState, pmsav7.rnr),
92
- .writefn = pmsav7_rgnr_write },
93
+ .writefn = pmsav7_rgnr_write,
94
+ .resetfn = arm_cp_reset_ignore },
95
REGINFO_SENTINEL
96
};
97
98
--
99
2.7.4
100
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 6/7] target/arm: Migrate MPU_RNR register state for M profile cores
Deleted patch
1
The PMSAv7 region number register is migrated for R profile
2
cores using the cpreg scheme, but M profile doesn't use
3
cpregs, and so we weren't migrating the MPU_RNR register state
4
at all. Fix that by adding a migration subsection for the
5
M profile case.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 1501153150-19984-6-git-send-email-peter.maydell@linaro.org
10
---
11
target/arm/machine.c | 28 ++++++++++++++++++++++++++++
12
1 file changed, 28 insertions(+)
13
14
diff --git a/target/arm/machine.c b/target/arm/machine.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/machine.c
17
+++ b/target/arm/machine.c
18
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav7 = {
19
}
20
};
21
22
+static bool pmsav7_rnr_needed(void *opaque)
23
+{
24
+ ARMCPU *cpu = opaque;
25
+ CPUARMState *env = &cpu->env;
26
+
27
+ /* For R profile cores pmsav7.rnr is migrated via the cpreg
28
+ * "RGNR" definition in helper.h. For M profile we have to
29
+ * migrate it separately.
30
+ */
31
+ return arm_feature(env, ARM_FEATURE_M);
32
+}
33
+
34
+static const VMStateDescription vmstate_pmsav7_rnr = {
35
+ .name = "cpu/pmsav7-rnr",
36
+ .version_id = 1,
37
+ .minimum_version_id = 1,
38
+ .needed = pmsav7_rnr_needed,
39
+ .fields = (VMStateField[]) {
40
+ VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU),
41
+ VMSTATE_END_OF_LIST()
42
+ }
43
+};
44
+
45
static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
46
VMStateField *field)
47
{
48
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = {
49
&vmstate_iwmmxt,
50
&vmstate_m,
51
&vmstate_thumb2ee,
52
+ /* pmsav7_rnr must come before pmsav7 so that we have the
53
+ * region number before we test it in the VMSTATE_VALIDATE
54
+ * in vmstate_pmsav7.
55
+ */
56
+ &vmstate_pmsav7_rnr,
57
&vmstate_pmsav7,
58
NULL
59
}
60
--
61
2.7.4
62
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 7/7] hw/mps2_scc: fix incorrect properties
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20170729234930.725-1-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/misc/mps2-scc.c | 4 ++--
9
1 file changed, 2 insertions(+), 2 deletions(-)
10
11
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/misc/mps2-scc.c
14
+++ b/hw/misc/mps2-scc.c
15
@@ -XXX,XX +XXX,XX @@ static Property mps2_scc_properties[] = {
16
/* Values for various read-only ID registers (which are specific
17
* to the board model or FPGA image)
18
*/
19
- DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, aid, 0),
20
+ DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
21
DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
22
- DEFINE_PROP_UINT32("scc-id", MPS2SCC, aid, 0),
23
+ DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
24
/* These are the initial settings for the source clocks on the board.
25
* In hardware they can be configured via a config file read by the
26
* motherboard configuration controller to suit the FPGA image.
27
--
28
2.7.4
29
30
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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