[Qemu-devel] [PULL 0/4] target-arm queue
[Qemu-devel] [PULL 00/33] target-arm queue
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ARM queue, mostly bug fixes to go into rc0.
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Third time's the charm...
2
The integratorcp and fsl_imx* changes are migration
3
compat breakers but that's ok for these boards.
4
2
5
thanks
6
-- PMM
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-- PMM
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4
5
The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
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6
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The following changes since commit ce1d20aac8533357650774c2c240e30de87dc122:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
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11
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-24' into staging (2017-07-24 16:20:47 +0100)
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8
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are available in the git repository at:
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are available in the git repository at:
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10
15
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170724
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2
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17
for you to fetch changes up to b2d1b0507d1b80f23da12dd8aab56944fe380a09:
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for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c:
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14
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integratorcp: Don't migrate flash using vmstate_register_ram_global() (2017-07-24 17:59:28 +0100)
15
arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100)
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16
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
18
target-arm:
23
* fix a TCG temporary leak in aarch64 rev16
19
* collection of M profile cleanups and minor bugfixes
24
* fsl_imx*: migrate the ROM contents
20
* loader: handle ELF files with overlapping zero-init data
25
* integratorcp: don't use vmstate_register_ram_global for flash
21
* virt: allow PMU instantiation with userspace irqchip
26
* mps2: Correctly set parent bus for SCC device
22
* wdt_aspeed: Add support for the reset width register
23
* cpu: Define new cpu_transaction_failed() hook
24
* Mark some SoC devices as not user-creatable
25
* arm: Fix aa64 ldp register writeback
26
* arm_gicv3_kvm: Fix compile warning
27
27
28
----------------------------------------------------------------
28
----------------------------------------------------------------
29
Emilio G. Cota (1):
29
Andrew Jeffery (2):
30
target/arm: fix TCG temp leak in aarch64 rev16
30
watchdog: wdt_aspeed: Add support for the reset width register
31
aspeed_soc: Propagate silicon-rev to watchdog
31
32
32
Peter Maydell (3):
33
Andrew Jones (4):
33
fsl_imx*: Migrate ROM contents
34
hw/arm/virt: add pmu interrupt state
34
mps2: Correctly set parent bus for SCC device
35
target/arm/kvm: pmu: split init and set-irq stages
35
integratorcp: Don't migrate flash using vmstate_register_ram_global()
36
hw/arm/virt: allow pmu instantiation with userspace irqchip
37
target/arm/kvm: pmu: improve error handling
36
38
37
hw/arm/fsl-imx25.c | 4 ++--
39
Peter Maydell (22):
38
hw/arm/fsl-imx31.c | 4 ++--
40
target/arm: Use MMUAccessType enum rather than int
39
hw/arm/fsl-imx6.c | 4 ++--
41
target/arm: Don't trap WFI/WFE for M profile
40
hw/arm/integratorcp.c | 3 +--
42
target/arm: Consolidate PMSA handling in get_phys_addr()
41
hw/arm/mps2.c | 2 +-
43
target/arm: Tighten up Thumb decode where new v8M insns will be
42
target/arm/translate-a64.c | 1 +
44
hw/intc/armv7m_nvic.c: Remove out of date comment
43
6 files changed, 9 insertions(+), 9 deletions(-)
45
target/arm: Remove incorrect comment about MPU_CTRL
46
target/arm: Fix outdated comment about exception exit
47
target/arm: Define and use XPSR bit masks
48
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
49
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
50
target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
51
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
52
target/arm: Create and use new function arm_v7m_is_handler_mode()
53
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
54
nvic: Implement "user accesses BusFault" SCS region behaviour
55
loader: Handle ELF files with overlapping zero-initialized data
56
loader: Ignore zero-sized ELF segments
57
memory.h: Move MemTxResult type to memattrs.h
58
cpu: Define new cpu_transaction_failed() hook
59
cputlb: Support generating CPU exceptions on memory transaction failures
60
target/arm: Factor out fault delivery code
61
target/arm: Allow deliver_fault() caller to specify EA bit
44
62
63
Philippe Mathieu-Daudé (1):
64
hw/arm: use defined type name instead of hard-coded string
65
66
Pranith Kumar (1):
67
arm_gicv3_kvm: Fix compile warning
68
69
Richard Henderson (1):
70
target/arm: Fix aa64 ldp register writeback
71
72
Thomas Huth (2):
73
hw/arm/aspeed_soc: Mark devices as user_creatable = false
74
hw/arm/digic: Mark device with user_creatable = false
75
76
include/exec/memattrs.h | 10 +++
77
include/exec/memory.h | 10 ---
78
include/hw/arm/armv7m.h | 2 +-
79
include/hw/elf_ops.h | 72 +++++++++++++++++--
80
include/hw/{arm => intc}/armv7m_nvic.h | 0
81
include/hw/watchdog/wdt_aspeed.h | 2 +
82
include/qom/cpu.h | 22 ++++++
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softmmu_template.h | 4 +-
84
target/arm/cpu.h | 56 +++++++++++----
85
target/arm/internals.h | 5 +-
86
target/arm/kvm_arm.h | 9 ++-
87
accel/tcg/cputlb.c | 32 ++++++++-
88
hw/arm/armv7m.c | 4 +-
89
hw/arm/aspeed_soc.c | 4 ++
90
hw/arm/digic.c | 2 +
91
hw/arm/exynos4210.c | 4 +-
92
hw/arm/highbank.c | 11 +--
93
hw/arm/realview.c | 6 +-
94
hw/arm/vexpress.c | 6 +-
95
hw/arm/virt.c | 12 +++-
96
hw/arm/xilinx_zynq.c | 14 ++--
97
hw/intc/arm_gicv3_kvm.c | 2 +-
98
hw/intc/armv7m_nvic.c | 68 +++++++++++-------
99
hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++++++++---
100
target/arm/cpu.c | 7 +-
101
target/arm/helper.c | 124 ++++++++++++++++-----------------
102
target/arm/kvm.c | 6 +-
103
target/arm/kvm32.c | 8 ++-
104
target/arm/kvm64.c | 63 ++++++++++-------
105
target/arm/machine.c | 54 +++++++++++++-
106
target/arm/op_helper.c | 121 +++++++++++++++++---------------
107
target/arm/translate-a64.c | 29 ++++----
108
target/arm/translate.c | 106 +++++++++++++++++++++-------
109
33 files changed, 677 insertions(+), 291 deletions(-)
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rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
111
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/4] target/arm: fix TCG temp leak in aarch64 rev16
Deleted patch
1
From: "Emilio G. Cota" <cota@braap.org>
2
1
3
Fix a TCG temporary leak in the new aarch64 rev16 handling.
4
5
Signed-off-by: Emilio G. Cota <cota@braap.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/translate-a64.c | 1 +
10
1 file changed, 1 insertion(+)
11
12
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate-a64.c
15
+++ b/target/arm/translate-a64.c
16
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
17
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
18
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
19
20
+ tcg_temp_free_i64(mask);
21
tcg_temp_free_i64(tcg_tmp);
22
}
23
24
--
25
2.7.4
26
27
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/4] fsl_imx*: Migrate ROM contents
Deleted patch
1
The fsl-imx* boards accidentally forgot to register the ROM memory
2
regions for migration. This used to require a manual step of calling
3
vmstate_register_ram(), but following commits
4
1cfe48c1ce21..b08199c6fbea194 we can use memory_region_init_rom() to
5
have it do the migration for us.
6
1
7
This is a migration break, but the migration code currently does not
8
handle the case of having two RAM regions which were not registered
9
for migration, and so prior to this commit a migration load would
10
always fail with:
11
"qemu-system-arm: Length mismatch: 0x4000 in != 0x18000: Invalid argument"
12
13
NB: migration appears at this point to be broken for this board
14
anyway -- it succeeds but the destination hangs; probably some
15
device in the system does not yet support migration.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Message-id: 1500309775-18361-1-git-send-email-peter.maydell@linaro.org
19
---
20
hw/arm/fsl-imx25.c | 4 ++--
21
hw/arm/fsl-imx31.c | 4 ++--
22
hw/arm/fsl-imx6.c | 4 ++--
23
3 files changed, 6 insertions(+), 6 deletions(-)
24
25
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/fsl-imx25.c
28
+++ b/hw/arm/fsl-imx25.c
29
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
30
}
31
32
/* initialize 2 x 16 KB ROM */
33
- memory_region_init_rom_nomigrate(&s->rom[0], NULL,
34
+ memory_region_init_rom(&s->rom[0], NULL,
35
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
36
if (err) {
37
error_propagate(errp, err);
38
@@ -XXX,XX +XXX,XX @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
39
}
40
memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
41
&s->rom[0]);
42
- memory_region_init_rom_nomigrate(&s->rom[1], NULL,
43
+ memory_region_init_rom(&s->rom[1], NULL,
44
"imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
45
if (err) {
46
error_propagate(errp, err);
47
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/arm/fsl-imx31.c
50
+++ b/hw/arm/fsl-imx31.c
51
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
52
}
53
54
/* On a real system, the first 16k is a `secure boot rom' */
55
- memory_region_init_rom_nomigrate(&s->secure_rom, NULL, "imx31.secure_rom",
56
+ memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
57
FSL_IMX31_SECURE_ROM_SIZE, &err);
58
if (err) {
59
error_propagate(errp, err);
60
@@ -XXX,XX +XXX,XX @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
61
&s->secure_rom);
62
63
/* There is also a 16k ROM */
64
- memory_region_init_rom_nomigrate(&s->rom, NULL, "imx31.rom",
65
+ memory_region_init_rom(&s->rom, NULL, "imx31.rom",
66
FSL_IMX31_ROM_SIZE, &err);
67
if (err) {
68
error_propagate(errp, err);
69
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/arm/fsl-imx6.c
72
+++ b/hw/arm/fsl-imx6.c
73
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
74
FSL_IMX6_ENET_MAC_1588_IRQ));
75
76
/* ROM memory */
77
- memory_region_init_rom_nomigrate(&s->rom, NULL, "imx6.rom",
78
+ memory_region_init_rom(&s->rom, NULL, "imx6.rom",
79
FSL_IMX6_ROM_SIZE, &err);
80
if (err) {
81
error_propagate(errp, err);
82
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
83
&s->rom);
84
85
/* CAAM memory */
86
- memory_region_init_rom_nomigrate(&s->caam, NULL, "imx6.caam",
87
+ memory_region_init_rom(&s->caam, NULL, "imx6.caam",
88
FSL_IMX6_CAAM_MEM_SIZE, &err);
89
if (err) {
90
error_propagate(errp, err);
91
--
92
2.7.4
93
94
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/4] mps2: Correctly set parent bus for SCC device
Deleted patch
1
A cut-and-paste error meant that instead of setting the
2
qdev parent bus for the SCC device we were setting it
3
twice for the ARMv7M container device. Fix this bug.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Message-id: 1500634509-28011-1-git-send-email-peter.maydell@linaro.org
7
---
8
hw/arm/mps2.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/mps2.c
14
+++ b/hw/arm/mps2.c
15
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
16
17
object_initialize(&mms->scc, sizeof(mms->scc), TYPE_MPS2_SCC);
18
sccdev = DEVICE(&mms->scc);
19
- qdev_set_parent_bus(armv7m, sysbus_get_default());
20
+ qdev_set_parent_bus(sccdev, sysbus_get_default());
21
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
22
qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008);
23
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
24
--
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2.7.4
26
27
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/4] integratorcp: Don't migrate flash using vmstate_register_ram_global()
Deleted patch
1
Instead of migrating the flash by creating the memory region
2
with memory_region_init_ram_nomigrate() and then calling
3
vmstate_register_ram_global(), just use memory_region_init_ram(),
4
which now handles migration registration automatically.
5
1
6
This is a migration compatibility break for the integratorcp
7
board, because the RAM region's migration name changes to
8
include the device path. This is OK because we don't guarantee
9
migration compatibility for this board.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 1500310341-28931-1-git-send-email-peter.maydell@linaro.org
13
---
14
hw/arm/integratorcp.c | 3 +--
15
1 file changed, 1 insertion(+), 2 deletions(-)
16
17
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/integratorcp.c
20
+++ b/hw/arm/integratorcp.c
21
@@ -XXX,XX +XXX,XX @@ static void integratorcm_init(Object *obj)
22
s->cm_init = 0x00000112;
23
s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
24
1000);
25
- memory_region_init_ram_nomigrate(&s->flash, obj, "integrator.flash", 0x100000,
26
+ memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
27
&error_fatal);
28
- vmstate_register_ram_global(&s->flash);
29
30
memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
31
"integratorcm", 0x00800000);
32
--
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2.7.4
34
35
diff view generated by jsdifflib

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