A surprisingly short target-arm queue, but no point in holding

onto these waiting for more code to arrive :-)

The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:

Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711

for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:

target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)

* v7M: ignore writes to CONTROL.SPSEL from Thread mode

* KVM: Enable in-kernel timers with user space gic

* aspeed: Register all watchdogs

* hw/misc: Add Exynos4210 Pseudo Random Number Generator

Alexander Graf (1):

ARM: KVM: Enable in-kernel timers with user space gic

Joel Stanley (1):

aspeed: Register all watchdogs

Krzysztof Kozlowski (1):

hw/misc: Add Exynos4210 Pseudo Random Number Generator

Peter Maydell (1):

target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode

hw/misc/Makefile.objs | 2 +-

include/hw/arm/aspeed_soc.h | 4 +-

include/sysemu/kvm.h | 11 ++

target/arm/cpu.h | 3 +

accel/kvm/kvm-all.c | 5 +

accel/stubs/kvm-stub.c | 5 +

hw/arm/aspeed_soc.c | 25 ++--

hw/arm/exynos4210.c | 4 +

hw/intc/arm_gic.c | 7 ++

hw/misc/exynos4210_rng.c | 277 ++++++++++++++++++++++++++++++++++++++++++++

target/arm/helper.c | 13 ++-

target/arm/kvm.c | 51 ++++++++

12 files changed, 394 insertions(+), 13 deletions(-)

create mode 100644 hw/misc/exynos4210_rng.c

For v7M, writes to the CONTROL register are only permitted for

privileged code. However even if the code is privileged, the

write must not affect the SPSEL bit in the CONTROL register

if the CPU is in Thread mode (as documented in the pseudocode

for the MSR instruction). Implement this, instead of permitting

SPSEL to be written in all cases.

This was causing mbed applications not to run, because the

RTX RTOS they use relies on this behaviour.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 1498820791-8130-1-git-send-email-peter.maydell@linaro.org

target/arm/helper.c | 13 ++++++++++---

1 file changed, 10 insertions(+), 3 deletions(-)

@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)

}

break;

case 20: /* CONTROL */

- switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);

- env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK |

- R_V7M_CONTROL_NPRIV_MASK);

+ /* Writing to the SPSEL bit only has an effect if we are in

+ * thread mode; other bits can be updated by any privileged code.

+ * switch_v7m_sp() deals with updating the SPSEL bit in

+ * env->v7m.control, so we only need update the others.

+ */

+ if (env->v7m.exception == 0) {

+ switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);

+ }

+ env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;

+ env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK;

break;

default:

qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"

2.7.4

From: Joel Stanley <joel@jms.id.au>

The ast2400 contains two and the ast2500 contains three watchdogs.

Add this information to the AspeedSoCInfo and realise the correct number

of watchdogs for that each SoC type.

Signed-off-by: Joel Stanley <joel@jms.id.au>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Tested-by: Cédric Le Goater <clg@kaod.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/arm/aspeed_soc.h | 4 +++-

hw/arm/aspeed_soc.c | 25 +++++++++++++++++--------

2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/aspeed_soc.h

+++ b/include/hw/arm/aspeed_soc.h

@@ -XXX,XX +XXX,XX @@

#include "hw/net/ftgmac100.h"

#define ASPEED_SPIS_NUM 2

+#define ASPEED_WDTS_NUM 3

typedef struct AspeedSoCState {

/*< private >*/

@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {

AspeedSMCState fmc;

AspeedSMCState spi[ASPEED_SPIS_NUM];

AspeedSDMCState sdmc;

- AspeedWDTState wdt;

+ AspeedWDTState wdt[ASPEED_WDTS_NUM];

FTGMAC100State ftgmac100;

} AspeedSoCState;

@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {

const hwaddr *spi_bases;

const char *fmc_typename;

const char **spi_typename;

+ int wdts_num;

} AspeedSoCInfo;

typedef struct AspeedSoCClass {

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_soc.c

+++ b/hw/arm/aspeed_soc.c

@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {

.spi_bases = aspeed_soc_ast2400_spi_bases,

.fmc_typename = "aspeed.smc.fmc",

.spi_typename = aspeed_soc_ast2400_typenames,

+ .wdts_num = 2,

}, {

.name = "ast2400-a1",

.cpu_model = "arm926",

@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {

.spi_bases = aspeed_soc_ast2400_spi_bases,

.fmc_typename = "aspeed.smc.fmc",

.spi_typename = aspeed_soc_ast2400_typenames,

+ .wdts_num = 2,

}, {

.name = "ast2400",

.cpu_model = "arm926",

@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {

.spi_bases = aspeed_soc_ast2400_spi_bases,

.fmc_typename = "aspeed.smc.fmc",

.spi_typename = aspeed_soc_ast2400_typenames,

+ .wdts_num = 2,

}, {

.name = "ast2500-a1",

.cpu_model = "arm1176",

@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {

.spi_bases = aspeed_soc_ast2500_spi_bases,

.fmc_typename = "aspeed.smc.ast2500-fmc",

.spi_typename = aspeed_soc_ast2500_typenames,

+ .wdts_num = 3,

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)

object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),

"ram-size", &error_abort);

- object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);

- object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);

- qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());

+ for (i = 0; i < sc->info->wdts_num; i++) {

+ object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);

+ object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);

+ qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());

+ }

object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);

object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)

sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);

/* Watch dog */

- object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);

- if (err) {

- error_propagate(errp, err);

- return;

+ for (i = 0; i < sc->info->wdts_num; i++) {

+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);

+ if (err) {

+ error_propagate(errp, err);

+ return;

+ }

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,

+ ASPEED_SOC_WDT_BASE + i * 0x20);

}

- sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);

/* Net */

qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);

2.7.4

From: Alexander Graf <agraf@suse.de>

When running with KVM enabled, you can choose between emulating the

gic in kernel or user space. If the kernel supports in-kernel virtualization

of the interrupt controller, it will default to that. If not, if will

default to user space emulation.

Unfortunately when running in user mode gic emulation, we miss out on

interrupt events which are only available from kernel space, such as the timer.

This patch leverages the new kernel/user space pending line synchronization for

timer events. It does not handle PMU events yet.

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

void *el_change_hook_opaque;

int32_t node_id; /* NUMA node this CPU belongs to */

+ /* Used to synchronize KVM and QEMU in-kernel device levels */

+ uint8_t device_irq_level;

};

static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)

diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c

--- a/accel/kvm/kvm-all.c

+++ b/accel/kvm/kvm-all.c

@@ -XXX,XX +XXX,XX @@ int kvm_has_intx_set_mask(void)

return kvm_state->intx_set_mask;

+bool kvm_arm_supports_user_irq(void)

+{

+ return kvm_check_extension(kvm_state, KVM_CAP_ARM_USER_IRQ);

+}

#ifdef KVM_CAP_SET_GUEST_DEBUG

struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *cpu,

target_ulong pc)

diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/stubs/kvm-stub.c

+++ b/accel/stubs/kvm-stub.c

@@ -XXX,XX +XXX,XX @@ void kvm_init_cpu_signals(CPUState *cpu)

abort();