[Qemu-devel] [PULL 0/4] target-arm queue
[PULL v2 00/29] target-arm queue
1
A surprisingly short target-arm queue, but no point in holding
1
v2: drop pvpanic-pci patches.
2
onto these waiting for more code to arrive :-)
3
2
4
thanks
3
The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
5
-- PMM
6
4
7
The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:
5
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
8
6
9
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)
7
are available in the Git repository at:
10
8
11
are available in the git repository at:
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
12
10
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711
11
for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
14
12
15
for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:
13
docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
16
17
target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)
18
14
19
----------------------------------------------------------------
15
----------------------------------------------------------------
20
target-arm queue:
16
target-arm queue:
21
* v7M: ignore writes to CONTROL.SPSEL from Thread mode
17
* Implement IMPDEF pauth algorithm
22
* KVM: Enable in-kernel timers with user space gic
18
* Support ARMv8.4-SEL2
23
* aspeed: Register all watchdogs
19
* Fix bug where we were truncating predicate vector lengths in SVE insns
24
* hw/misc: Add Exynos4210 Pseudo Random Number Generator
20
* npcm7xx_adc-test: Fix memleak in adc_qom_set
21
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
22
* docs: Build and install all the docs in a single manual
25
23
26
----------------------------------------------------------------
24
----------------------------------------------------------------
27
Alexander Graf (1):
25
Gan Qixin (1):
28
ARM: KVM: Enable in-kernel timers with user space gic
26
npcm7xx_adc-test: Fix memleak in adc_qom_set
29
30
Joel Stanley (1):
31
aspeed: Register all watchdogs
32
33
Krzysztof Kozlowski (1):
34
hw/misc: Add Exynos4210 Pseudo Random Number Generator
35
27
36
Peter Maydell (1):
28
Peter Maydell (1):
37
target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
29
docs: Build and install all the docs in a single manual
38
30
39
hw/misc/Makefile.objs | 2 +-
31
Philippe Mathieu-Daudé (1):
40
include/hw/arm/aspeed_soc.h | 4 +-
32
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
41
include/sysemu/kvm.h | 11 ++
42
target/arm/cpu.h | 3 +
43
accel/kvm/kvm-all.c | 5 +
44
accel/stubs/kvm-stub.c | 5 +
45
hw/arm/aspeed_soc.c | 25 ++--
46
hw/arm/exynos4210.c | 4 +
47
hw/intc/arm_gic.c | 7 ++
48
hw/misc/exynos4210_rng.c | 277 ++++++++++++++++++++++++++++++++++++++++++++
49
target/arm/helper.c | 13 ++-
50
target/arm/kvm.c | 51 ++++++++
51
12 files changed, 394 insertions(+), 13 deletions(-)
52
create mode 100644 hw/misc/exynos4210_rng.c
53
33
34
Richard Henderson (7):
35
target/arm: Implement an IMPDEF pauth algorithm
36
target/arm: Add cpu properties to control pauth
37
target/arm: Use object_property_add_bool for "sve" property
38
target/arm: Introduce PREDDESC field definitions
39
target/arm: Update PFIRST, PNEXT for pred_desc
40
target/arm: Update ZIP, UZP, TRN for pred_desc
41
target/arm: Update REV, PUNPK for pred_desc
42
43
Rémi Denis-Courmont (19):
44
target/arm: remove redundant tests
45
target/arm: add arm_is_el2_enabled() helper
46
target/arm: use arm_is_el2_enabled() where applicable
47
target/arm: use arm_hcr_el2_eff() where applicable
48
target/arm: factor MDCR_EL2 common handling
49
target/arm: Define isar_feature function to test for presence of SEL2
50
target/arm: add 64-bit S-EL2 to EL exception table
51
target/arm: add MMU stage 1 for Secure EL2
52
target/arm: add ARMv8.4-SEL2 system registers
53
target/arm: handle VMID change in secure state
54
target/arm: do S1_ptw_translate() before address space lookup
55
target/arm: translate NS bit in page-walks
56
target/arm: generalize 2-stage page-walk condition
57
target/arm: secure stage 2 translation regime
58
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
59
target/arm: revector to run-time pick target EL
60
target/arm: Implement SCR_EL2.EEL2
61
target/arm: enable Secure EL2 in max CPU
62
target/arm: refactor vae1_tlbmask()
63
64
docs/conf.py | 46 ++++-
65
docs/devel/conf.py | 15 --
66
docs/index.html.in | 17 --
67
docs/interop/conf.py | 28 ---
68
docs/meson.build | 64 +++---
69
docs/specs/conf.py | 16 --
70
docs/system/arm/cpu-features.rst | 21 ++
71
docs/system/conf.py | 28 ---
72
docs/tools/conf.py | 37 ----
73
docs/user/conf.py | 15 --
74
include/qemu/xxhash.h | 98 +++++++++
75
target/arm/cpu-param.h | 2 +-
76
target/arm/cpu.h | 107 ++++++++--
77
target/arm/internals.h | 45 +++++
78
target/arm/cpu.c | 23 ++-
79
target/arm/cpu64.c | 65 ++++--
80
target/arm/helper-a64.c | 8 +-
81
target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
82
target/arm/m_helper.c | 2 +-
83
target/arm/monitor.c | 1 +
84
target/arm/op_helper.c | 4 +-
85
target/arm/pauth_helper.c | 27 ++-
86
target/arm/sve_helper.c | 33 ++--
87
target/arm/tlb_helper.c | 3 +
88
target/arm/translate-a64.c | 4 +
89
target/arm/translate-sve.c | 31 ++-
90
target/arm/translate.c | 36 +++-
91
tests/qtest/arm-cpu-features.c | 13 ++
92
tests/qtest/npcm7xx_adc-test.c | 1 +
93
.gitlab-ci.yml | 4 +-
94
30 files changed, 770 insertions(+), 438 deletions(-)
95
delete mode 100644 docs/devel/conf.py
96
delete mode 100644 docs/index.html.in
97
delete mode 100644 docs/interop/conf.py
98
delete mode 100644 docs/specs/conf.py
99
delete mode 100644 docs/system/conf.py
100
delete mode 100644 docs/tools/conf.py
101
delete mode 100644 docs/user/conf.py
102
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/4] hw/misc: Add Exynos4210 Pseudo Random Number Generator
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
Add emulation for Exynos4210 Pseudo Random Number Generator which could
4
work on fixed seeds or with seeds provided by True Random Number
5
Generator block inside the SoC.
6
7
Implement only the fixed seeds part of it in polling mode (no
8
interrupts).
9
10
Emulation tested with two independent Linux kernel exynos-rng drivers:
11
1. New kcapi-rng interface (targeting Linux v4.12),
12
2. Old hwrng inteface
13
# echo "exynos" > /sys/class/misc/hw_random/rng_current
14
# dd if=/dev/hwrng of=/dev/null bs=1 count=16
15
16
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
17
Message-id: 20170425180609.11004-1-krzk@kernel.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
[PMM: wrapped a few overlong lines; more efficient implementation
20
of exynos4210_rng_seed_ready()]
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/misc/Makefile.objs | 2 +-
24
hw/arm/exynos4210.c | 4 +
25
hw/misc/exynos4210_rng.c | 277 +++++++++++++++++++++++++++++++++++++++++++++++
26
3 files changed, 282 insertions(+), 1 deletion(-)
27
create mode 100644 hw/misc/exynos4210_rng.c
28
29
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/misc/Makefile.objs
32
+++ b/hw/misc/Makefile.objs
33
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IVSHMEM) += ivshmem.o
34
obj-$(CONFIG_REALVIEW) += arm_sysctl.o
35
obj-$(CONFIG_NSERIES) += cbus.o
36
obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
37
-obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o
38
+obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o exynos4210_rng.o
39
obj-$(CONFIG_IMX) += imx_ccm.o
40
obj-$(CONFIG_IMX) += imx31_ccm.o
41
obj-$(CONFIG_IMX) += imx25_ccm.o
42
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/exynos4210.c
45
+++ b/hw/arm/exynos4210.c
46
@@ -XXX,XX +XXX,XX @@
47
/* Clock controller SFR base address */
48
#define EXYNOS4210_CLK_BASE_ADDR 0x10030000
49
50
+/* PRNG/HASH SFR base address */
51
+#define EXYNOS4210_RNG_BASE_ADDR 0x10830400
52
+
53
/* Display controllers (FIMD) */
54
#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
55
56
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
57
sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
58
59
sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
60
+ sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
61
62
/* PWM */
63
sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
64
diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210_rng.c
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/hw/misc/exynos4210_rng.c
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * Exynos4210 Pseudo Random Nubmer Generator Emulation
72
+ *
73
+ * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
74
+ *
75
+ * This program is free software; you can redistribute it and/or modify it
76
+ * under the terms of the GNU General Public License as published by the
77
+ * Free Software Foundation; either version 2 of the License, or
78
+ * (at your option) any later version.
79
+ *
80
+ * This program is distributed in the hope that it will be useful, but WITHOUT
81
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
82
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
83
+ * for more details.
84
+ *
85
+ * You should have received a copy of the GNU General Public License along
86
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
87
+ */
88
+
89
+#include "qemu/osdep.h"
90
+#include "crypto/random.h"
91
+#include "hw/sysbus.h"
92
+#include "qemu/log.h"
93
+
94
+#define DEBUG_EXYNOS_RNG 0
95
+
96
+#define DPRINTF(fmt, ...) \
97
+ do { \
98
+ if (DEBUG_EXYNOS_RNG) { \
99
+ printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \
100
+ } \
101
+ } while (0)
102
+
103
+#define TYPE_EXYNOS4210_RNG "exynos4210.rng"
104
+#define EXYNOS4210_RNG(obj) \
105
+ OBJECT_CHECK(Exynos4210RngState, (obj), TYPE_EXYNOS4210_RNG)
106
+
107
+/*
108
+ * Exynos4220, PRNG, only polling mode is supported.
109
+ */
110
+
111
+/* RNG_CONTROL_1 register bitfields, reset value: 0x0 */
112
+#define EXYNOS4210_RNG_CONTROL_1_PRNG 0x8
113
+#define EXYNOS4210_RNG_CONTROL_1_START_INIT BIT(4)
114
+/* RNG_STATUS register bitfields, reset value: 0x1 */
115
+#define EXYNOS4210_RNG_STATUS_PRNG_ERROR BIT(7)
116
+#define EXYNOS4210_RNG_STATUS_PRNG_DONE BIT(5)
117
+#define EXYNOS4210_RNG_STATUS_MSG_DONE BIT(4)
118
+#define EXYNOS4210_RNG_STATUS_PARTIAL_DONE BIT(3)
119
+#define EXYNOS4210_RNG_STATUS_PRNG_BUSY BIT(2)
120
+#define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1)
121
+#define EXYNOS4210_RNG_STATUS_BUFFER_READY BIT(0)
122
+#define EXYNOS4210_RNG_STATUS_WRITE_MASK (EXYNOS4210_RNG_STATUS_PRNG_DONE \
123
+ | EXYNOS4210_RNG_STATUS_MSG_DONE \
124
+ | EXYNOS4210_RNG_STATUS_PARTIAL_DONE)
125
+
126
+#define EXYNOS4210_RNG_CONTROL_1 0x0
127
+#define EXYNOS4210_RNG_STATUS 0x10
128
+#define EXYNOS4210_RNG_SEED_IN 0x140
129
+#define EXYNOS4210_RNG_SEED_IN_OFFSET(n) (EXYNOS4210_RNG_SEED_IN + (n * 0x4))
130
+#define EXYNOS4210_RNG_PRNG 0x160
131
+#define EXYNOS4210_RNG_PRNG_OFFSET(n) (EXYNOS4210_RNG_PRNG + (n * 0x4))
132
+
133
+#define EXYNOS4210_RNG_PRNG_NUM 5
134
+
135
+#define EXYNOS4210_RNG_REGS_MEM_SIZE 0x200
136
+
137
+typedef struct Exynos4210RngState {
138
+ SysBusDevice parent_obj;
139
+ MemoryRegion iomem;
140
+
141
+ int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM];
142
+ /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */
143
+ uint32_t seed_set;
144
+
145
+ /* Register values */
146
+ uint32_t reg_control;
147
+ uint32_t reg_status;
148
+} Exynos4210RngState;
149
+
150
+static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s)
151
+{
152
+ uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM);
153
+
154
+ /* Return true if all the seed-set bits are set. */
155
+ return (s->seed_set & mask) == mask;
156
+}
157
+
158
+static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i,
159
+ uint64_t val)
160
+{
161
+ /*
162
+ * We actually ignore the seed and always generate true random numbers.
163
+ * Theoretically this should not match the device as Exynos has
164
+ * a Pseudo Random Number Generator but testing shown that it always
165
+ * generates random numbers regardless of the seed value.
166
+ */
167
+ s->seed_set |= BIT(i);
168
+
169
+ /* If all seeds were written, update the status to reflect it */
170
+ if (exynos4210_rng_seed_ready(s)) {
171
+ s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
172
+ } else {
173
+ s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
174
+ }
175
+}
176
+
177
+static void exynos4210_rng_run_engine(Exynos4210RngState *s)
178
+{
179
+ Error *err = NULL;
180
+ int ret;
181
+
182
+ /* Seed set? */
183
+ if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) {
184
+ goto out;
185
+ }
186
+
187
+ /* PRNG engine chosen? */
188
+ if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) {
189
+ goto out;
190
+ }
191
+
192
+ /* PRNG engine started? */
193
+ if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) {
194
+ goto out;
195
+ }
196
+
197
+ /* Get randoms */
198
+ ret = qcrypto_random_bytes((uint8_t *)s->randr_value,
199
+ sizeof(s->randr_value), &err);
200
+ if (!ret) {
201
+ /* Notify that PRNG is ready */
202
+ s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE;
203
+ } else {
204
+ error_report_err(err);
205
+ }
206
+
207
+out:
208
+ /* Always clear start engine bit */
209
+ s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT;
210
+}
211
+
212
+static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset,
213
+ unsigned size)
214
+{
215
+ Exynos4210RngState *s = (Exynos4210RngState *)opaque;
216
+ uint32_t val = 0;
217
+
218
+ assert(size == 4);
219
+
220
+ switch (offset) {
221
+ case EXYNOS4210_RNG_CONTROL_1:
222
+ val = s->reg_control;
223
+ break;
224
+
225
+ case EXYNOS4210_RNG_STATUS:
226
+ val = s->reg_status;
227
+ break;
228
+
229
+ case EXYNOS4210_RNG_PRNG_OFFSET(0):
230
+ case EXYNOS4210_RNG_PRNG_OFFSET(1):
231
+ case EXYNOS4210_RNG_PRNG_OFFSET(2):
232
+ case EXYNOS4210_RNG_PRNG_OFFSET(3):
233
+ case EXYNOS4210_RNG_PRNG_OFFSET(4):
234
+ val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4];
235
+ DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n",
236
+ offset, val);
237
+ break;
238
+
239
+ default:
240
+ qemu_log_mask(LOG_GUEST_ERROR,
241
+ "%s: bad read offset 0x%" HWADDR_PRIx "\n",
242
+ __func__, offset);
243
+ }
244
+
245
+ return val;
246
+}
247
+
248
+static void exynos4210_rng_write(void *opaque, hwaddr offset,
249
+ uint64_t val, unsigned size)
250
+{
251
+ Exynos4210RngState *s = (Exynos4210RngState *)opaque;
252
+
253
+ assert(size == 4);
254
+
255
+ switch (offset) {
256
+ case EXYNOS4210_RNG_CONTROL_1:
257
+ DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val);
258
+ s->reg_control = val;
259
+ exynos4210_rng_run_engine(s);
260
+ break;
261
+
262
+ case EXYNOS4210_RNG_STATUS:
263
+ /* For clearing status fields */
264
+ s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK;
265
+ s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK;
266
+ break;
267
+
268
+ case EXYNOS4210_RNG_SEED_IN_OFFSET(0):
269
+ case EXYNOS4210_RNG_SEED_IN_OFFSET(1):
270
+ case EXYNOS4210_RNG_SEED_IN_OFFSET(2):
271
+ case EXYNOS4210_RNG_SEED_IN_OFFSET(3):
272
+ case EXYNOS4210_RNG_SEED_IN_OFFSET(4):
273
+ exynos4210_rng_set_seed(s,
274
+ (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4,
275
+ val);
276
+ break;
277
+
278
+ default:
279
+ qemu_log_mask(LOG_GUEST_ERROR,
280
+ "%s: bad write offset 0x%" HWADDR_PRIx "\n",
281
+ __func__, offset);
282
+ }
283
+}
284
+
285
+static const MemoryRegionOps exynos4210_rng_ops = {
286
+ .read = exynos4210_rng_read,
287
+ .write = exynos4210_rng_write,
288
+ .endianness = DEVICE_NATIVE_ENDIAN,
289
+};
290
+
291
+static void exynos4210_rng_reset(DeviceState *dev)
292
+{
293
+ Exynos4210RngState *s = EXYNOS4210_RNG(dev);
294
+
295
+ s->reg_control = 0;
296
+ s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY;
297
+ memset(s->randr_value, 0, sizeof(s->randr_value));
298
+ s->seed_set = 0;
299
+}
300
+
301
+static void exynos4210_rng_init(Object *obj)
302
+{
303
+ Exynos4210RngState *s = EXYNOS4210_RNG(obj);
304
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
305
+
306
+ memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s,
307
+ TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE);
308
+ sysbus_init_mmio(dev, &s->iomem);
309
+}
310
+
311
+static const VMStateDescription exynos4210_rng_vmstate = {
312
+ .name = TYPE_EXYNOS4210_RNG,
313
+ .version_id = 1,
314
+ .minimum_version_id = 1,
315
+ .fields = (VMStateField[]) {
316
+ VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState,
317
+ EXYNOS4210_RNG_PRNG_NUM),
318
+ VMSTATE_UINT32(seed_set, Exynos4210RngState),
319
+ VMSTATE_UINT32(reg_status, Exynos4210RngState),
320
+ VMSTATE_UINT32(reg_control, Exynos4210RngState),
321
+ VMSTATE_END_OF_LIST()
322
+ }
323
+};
324
+
325
+static void exynos4210_rng_class_init(ObjectClass *klass, void *data)
326
+{
327
+ DeviceClass *dc = DEVICE_CLASS(klass);
328
+
329
+ dc->reset = exynos4210_rng_reset;
330
+ dc->vmsd = &exynos4210_rng_vmstate;
331
+}
332
+
333
+static const TypeInfo exynos4210_rng_info = {
334
+ .name = TYPE_EXYNOS4210_RNG,
335
+ .parent = TYPE_SYS_BUS_DEVICE,
336
+ .instance_size = sizeof(Exynos4210RngState),
337
+ .instance_init = exynos4210_rng_init,
338
+ .class_init = exynos4210_rng_class_init,
339
+};
340
+
341
+static void exynos4210_rng_register(void)
342
+{
343
+ type_register_static(&exynos4210_rng_info);
344
+}
345
+
346
+type_init(exynos4210_rng_register)
347
--
348
2.7.4
349
350
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/4] aspeed: Register all watchdogs
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
The ast2400 contains two and the ast2500 contains three watchdogs.
4
Add this information to the AspeedSoCInfo and realise the correct number
5
of watchdogs for that each SoC type.
6
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Reviewed-by: Cédric Le Goater <clg@kaod.org>
9
Tested-by: Cédric Le Goater <clg@kaod.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/aspeed_soc.h | 4 +++-
13
hw/arm/aspeed_soc.c | 25 +++++++++++++++++--------
14
2 files changed, 20 insertions(+), 9 deletions(-)
15
16
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/aspeed_soc.h
19
+++ b/include/hw/arm/aspeed_soc.h
20
@@ -XXX,XX +XXX,XX @@
21
#include "hw/net/ftgmac100.h"
22
23
#define ASPEED_SPIS_NUM 2
24
+#define ASPEED_WDTS_NUM 3
25
26
typedef struct AspeedSoCState {
27
/*< private >*/
28
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
29
AspeedSMCState fmc;
30
AspeedSMCState spi[ASPEED_SPIS_NUM];
31
AspeedSDMCState sdmc;
32
- AspeedWDTState wdt;
33
+ AspeedWDTState wdt[ASPEED_WDTS_NUM];
34
FTGMAC100State ftgmac100;
35
} AspeedSoCState;
36
37
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
38
const hwaddr *spi_bases;
39
const char *fmc_typename;
40
const char **spi_typename;
41
+ int wdts_num;
42
} AspeedSoCInfo;
43
44
typedef struct AspeedSoCClass {
45
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/aspeed_soc.c
48
+++ b/hw/arm/aspeed_soc.c
49
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
50
.spi_bases = aspeed_soc_ast2400_spi_bases,
51
.fmc_typename = "aspeed.smc.fmc",
52
.spi_typename = aspeed_soc_ast2400_typenames,
53
+ .wdts_num = 2,
54
}, {
55
.name = "ast2400-a1",
56
.cpu_model = "arm926",
57
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
58
.spi_bases = aspeed_soc_ast2400_spi_bases,
59
.fmc_typename = "aspeed.smc.fmc",
60
.spi_typename = aspeed_soc_ast2400_typenames,
61
+ .wdts_num = 2,
62
}, {
63
.name = "ast2400",
64
.cpu_model = "arm926",
65
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
66
.spi_bases = aspeed_soc_ast2400_spi_bases,
67
.fmc_typename = "aspeed.smc.fmc",
68
.spi_typename = aspeed_soc_ast2400_typenames,
69
+ .wdts_num = 2,
70
}, {
71
.name = "ast2500-a1",
72
.cpu_model = "arm1176",
73
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
74
.spi_bases = aspeed_soc_ast2500_spi_bases,
75
.fmc_typename = "aspeed.smc.ast2500-fmc",
76
.spi_typename = aspeed_soc_ast2500_typenames,
77
+ .wdts_num = 3,
78
},
79
};
80
81
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
82
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
83
"ram-size", &error_abort);
84
85
- object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
86
- object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
87
- qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
88
+ for (i = 0; i < sc->info->wdts_num; i++) {
89
+ object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
90
+ object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);
91
+ qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());
92
+ }
93
94
object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
95
object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
96
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
97
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
98
99
/* Watch dog */
100
- object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
101
- if (err) {
102
- error_propagate(errp, err);
103
- return;
104
+ for (i = 0; i < sc->info->wdts_num; i++) {
105
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
106
+ if (err) {
107
+ error_propagate(errp, err);
108
+ return;
109
+ }
110
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
111
+ ASPEED_SOC_WDT_BASE + i * 0x20);
112
}
113
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
114
115
/* Net */
116
qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
117
--
118
2.7.4
119
120
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/4] ARM: KVM: Enable in-kernel timers with user space gic
Deleted patch
1
From: Alexander Graf <agraf@suse.de>
2
1
3
When running with KVM enabled, you can choose between emulating the
4
gic in kernel or user space. If the kernel supports in-kernel virtualization
5
of the interrupt controller, it will default to that. If not, if will
6
default to user space emulation.
7
8
Unfortunately when running in user mode gic emulation, we miss out on
9
interrupt events which are only available from kernel space, such as the timer.
10
This patch leverages the new kernel/user space pending line synchronization for
11
timer events. It does not handle PMU events yet.
12
13
Signed-off-by: Alexander Graf <agraf@suse.de>
14
Reviewed-by: Andrew Jones <drjones@redhat.com>
15
Message-id: 1498577737-130264-1-git-send-email-agraf@suse.de
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
include/sysemu/kvm.h | 11 +++++++++++
19
target/arm/cpu.h | 3 +++
20
accel/kvm/kvm-all.c | 5 +++++
21
accel/stubs/kvm-stub.c | 5 +++++
22
hw/intc/arm_gic.c | 7 +++++++
23
target/arm/kvm.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++
24
6 files changed, 82 insertions(+)
25
26
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/sysemu/kvm.h
29
+++ b/include/sysemu/kvm.h
30
@@ -XXX,XX +XXX,XX @@ int kvm_init_vcpu(CPUState *cpu);
31
int kvm_cpu_exec(CPUState *cpu);
32
int kvm_destroy_vcpu(CPUState *cpu);
33
34
+/**
35
+ * kvm_arm_supports_user_irq
36
+ *
37
+ * Not all KVM implementations support notifications for kernel generated
38
+ * interrupt events to user space. This function indicates whether the current
39
+ * KVM implementation does support them.
40
+ *
41
+ * Returns: true if KVM supports using kernel generated IRQs from user space
42
+ */
43
+bool kvm_arm_supports_user_irq(void);
44
+
45
#ifdef NEED_CPU_H
46
#include "cpu.h"
47
48
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/cpu.h
51
+++ b/target/arm/cpu.h
52
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
53
void *el_change_hook_opaque;
54
55
int32_t node_id; /* NUMA node this CPU belongs to */
56
+
57
+ /* Used to synchronize KVM and QEMU in-kernel device levels */
58
+ uint8_t device_irq_level;
59
};
60
61
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
62
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/accel/kvm/kvm-all.c
65
+++ b/accel/kvm/kvm-all.c
66
@@ -XXX,XX +XXX,XX @@ int kvm_has_intx_set_mask(void)
67
return kvm_state->intx_set_mask;
68
}
69
70
+bool kvm_arm_supports_user_irq(void)
71
+{
72
+ return kvm_check_extension(kvm_state, KVM_CAP_ARM_USER_IRQ);
73
+}
74
+
75
#ifdef KVM_CAP_SET_GUEST_DEBUG
76
struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *cpu,
77
target_ulong pc)
78
diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/accel/stubs/kvm-stub.c
81
+++ b/accel/stubs/kvm-stub.c
82
@@ -XXX,XX +XXX,XX @@ void kvm_init_cpu_signals(CPUState *cpu)
83
{
84
abort();
85
}
86
+
87
+bool kvm_arm_supports_user_irq(void)
88
+{
89
+ return false;
90
+}
91
#endif
92
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/intc/arm_gic.c
95
+++ b/hw/intc/arm_gic.c
96
@@ -XXX,XX +XXX,XX @@
97
#include "qom/cpu.h"
98
#include "qemu/log.h"
99
#include "trace.h"
100
+#include "sysemu/kvm.h"
101
102
/* #define DEBUG_GIC */
103
104
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
105
return;
106
}
107
108
+ if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
109
+ error_setg(errp, "KVM with user space irqchip only works when the "
110
+ "host kernel supports KVM_CAP_ARM_USER_IRQ");
111
+ return;
112
+ }
113
+
114
/* This creates distributor and main CPU interface (s->cpuiomem[0]) */
115
gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
116
117
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/arm/kvm.c
120
+++ b/target/arm/kvm.c
121
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
122
*/
123
kvm_async_interrupts_allowed = true;
124
125
+ /*
126
+ * PSCI wakes up secondary cores, so we always need to
127
+ * have vCPUs waiting in kernel space
128
+ */
129
+ kvm_halt_in_kernel_allowed = true;
130
+
131
cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
132
133
type_register_static(&host_arm_cpu_type_info);
134
@@ -XXX,XX +XXX,XX @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
135
136
MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
137
{
138
+ ARMCPU *cpu;
139
+ uint32_t switched_level;
140
+
141
+ if (kvm_irqchip_in_kernel()) {
142
+ /*
143
+ * We only need to sync timer states with user-space interrupt
144
+ * controllers, so return early and save cycles if we don't.
145
+ */
146
+ return MEMTXATTRS_UNSPECIFIED;
147
+ }
148
+
149
+ cpu = ARM_CPU(cs);
150
+
151
+ /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */
152
+ if (run->s.regs.device_irq_level != cpu->device_irq_level) {
153
+ switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level;
154
+
155
+ qemu_mutex_lock_iothread();
156
+
157
+ if (switched_level & KVM_ARM_DEV_EL1_VTIMER) {
158
+ qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT],
159
+ !!(run->s.regs.device_irq_level &
160
+ KVM_ARM_DEV_EL1_VTIMER));
161
+ switched_level &= ~KVM_ARM_DEV_EL1_VTIMER;
162
+ }
163
+
164
+ if (switched_level & KVM_ARM_DEV_EL1_PTIMER) {
165
+ qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS],
166
+ !!(run->s.regs.device_irq_level &
167
+ KVM_ARM_DEV_EL1_PTIMER));
168
+ switched_level &= ~KVM_ARM_DEV_EL1_PTIMER;
169
+ }
170
+
171
+ /* XXX PMU IRQ is missing */
172
+
173
+ if (switched_level) {
174
+ qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n",
175
+ __func__, switched_level);
176
+ }
177
+
178
+ /* We also mark unknown levels as processed to not waste cycles */
179
+ cpu->device_irq_level = run->s.regs.device_irq_level;
180
+ qemu_mutex_unlock_iothread();
181
+ }
182
+
183
return MEMTXATTRS_UNSPECIFIED;
184
}
185
186
--
187
2.7.4
188
189
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/4] target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
Deleted patch
1
For v7M, writes to the CONTROL register are only permitted for
2
privileged code. However even if the code is privileged, the
3
write must not affect the SPSEL bit in the CONTROL register
4
if the CPU is in Thread mode (as documented in the pseudocode
5
for the MSR instruction). Implement this, instead of permitting
6
SPSEL to be written in all cases.
7
1
8
This was causing mbed applications not to run, because the
9
RTX RTOS they use relies on this behaviour.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 1498820791-8130-1-git-send-email-peter.maydell@linaro.org
14
---
15
target/arm/helper.c | 13 ++++++++++---
16
1 file changed, 10 insertions(+), 3 deletions(-)
17
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
21
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
23
}
24
break;
25
case 20: /* CONTROL */
26
- switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
27
- env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK |
28
- R_V7M_CONTROL_NPRIV_MASK);
29
+ /* Writing to the SPSEL bit only has an effect if we are in
30
+ * thread mode; other bits can be updated by any privileged code.
31
+ * switch_v7m_sp() deals with updating the SPSEL bit in
32
+ * env->v7m.control, so we only need update the others.
33
+ */
34
+ if (env->v7m.exception == 0) {
35
+ switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
36
+ }
37
+ env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;
38
+ env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK;
39
break;
40
default:
41
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
42
--
43
2.7.4
44
45
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.