Series comparison

-[Qemu-devel] [PULL 0/4] target-arm queue
+[Qemu-devel] [PULL 00/13] target-arm queue
-A surprisingly short target-arm queue, but no point in holding
+Arm patch queue -- these are all bug fix patches but we might
-onto these waiting for more code to arrive :-)
+as well put them in to rc0...
 thanks
 -- PMM
-The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:
+The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
-  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)
+  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)
-are available in the git repository at:
+are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711
+  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319
-for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:
+for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
-  target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)
+  hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * v7M: ignore writes to CONTROL.SPSEL from Thread mode
+ * fsl-imx6: Fix incorrect Ethernet interrupt defines
- * KVM: Enable in-kernel timers with user space gic
+ * dump: Update correct kdump phys_base field for AArch64
- * aspeed: Register all watchdogs
+ * char: i.MX: Add support for "TX complete" interrupt
- * hw/misc: Add Exynos4210 Pseudo Random Number Generator
+ * bcm2836/raspi: Fix various bugs resulting in panics trying
    to boot a Debian Linux kernel on raspi3
 ----------------------------------------------------------------
-Alexander Graf (1):
+Andrey Smirnov (2):
-      ARM: KVM: Enable in-kernel timers with user space gic
+      char: i.MX: Simplify imx_update()
       char: i.MX: Add support for "TX complete" interrupt
-Joel Stanley (1):
+Guenter Roeck (1):
-      aspeed: Register all watchdogs
+      fsl-imx6: Swap Ethernet interrupt defines
-Krzysztof Kozlowski (1):
+Peter Maydell (9):
-      hw/misc: Add Exynos4210 Pseudo Random Number Generator
+      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
       hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
       hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
       hw/arm/bcm2386: Fix parent type of bcm2386
       hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
       hw/arm/bcm2836: Create proper bcm2837 device
       hw/arm/bcm2836: Use correct affinity values for BCM2837
       hw/arm/bcm2836: Hardcode correct CPU type
       hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
-Peter Maydell (1):
+Wei Huang (1):
-      target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
+      dump: Update correct kdump phys_base field for AArch64
- hw/misc/Makefile.objs       |   2 +-
+ include/hw/arm/bcm2836.h     | 31 +++++++++++++---
- include/hw/arm/aspeed_soc.h |   4 +-
+ include/hw/arm/fsl-imx6.h    |  4 +-
- include/sysemu/kvm.h        |  11 ++
+ include/hw/char/imx_serial.h |  3 ++
- target/arm/cpu.h            |   3 +
+ dump.c                       | 14 +++++--
- accel/kvm/kvm-all.c         |   5 +
+ hw/arm/bcm2836.c             | 87 +++++++++++++++++++++++++++++++-------------
- accel/stubs/kvm-stub.c      |   5 +
+ hw/arm/boot.c                | 12 ++++++
- hw/arm/aspeed_soc.c         |  25 ++--
+ hw/arm/raspi.c               | 77 +++++++++++++++++++++++++++++++--------
- hw/arm/exynos4210.c         |   4 +
+ hw/char/imx_serial.c         | 44 ++++++++++++++++------
- hw/intc/arm_gic.c           |   7 ++
+ hw/net/imx_fec.c             | 28 +++++++++++++-
- hw/misc/exynos4210_rng.c    | 277 ++++++++++++++++++++++++++++++++++++++++++++
+files changed, 237 insertions(+), 63 deletions(-)
  target/arm/helper.c         |  13 ++-
  target/arm/kvm.c            |  51 ++++++++
 files changed, 394 insertions(+), 13 deletions(-)
  create mode 100644 hw/misc/exynos4210_rng.c

-New patch
+[Qemu-devel] [PULL 01/13] fsl-imx6: Swap Ethernet interrupt defines
+From: Guenter Roeck <linux@roeck-us.net>
+The sabrelite machine model used by qemu-system-arm is based on the
+Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
+controller which is supported in QEMU using the imx_fec.c module
+(actually called imx.enet for this model.)
+The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
+imx.enet device like this:
+ #define FSL_IMX6_ENET_MAC_1588_IRQ 118
+ #define FSL_IMX6_ENET_MAC_IRQ 119
+According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
+page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
+interrupts are as follows.
+ENET MAC 0 IRQ
+ENET MAC 0 1588 Timer interrupt
+where
+- 32 == 118
+- 32 == 119
+In other words, the vector definitions in the fsl-imx6.h file are reversed.
+Fixing the interrupts alone causes problems with older Linux kernels:
+The Ethernet interface will fail to probe with Linux v4.9 and earlier.
+Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
+error handling. This is a Linux kernel problem, not a qemu problem:
+the Linux kernel only worked by accident since it requested both interrupts.
+For backward compatibility, generate the Ethernet interrupt on both interrupt
+lines. This was shown to work from all Linux kernel releases starting with
+v3.16.
+Link: https://bugs.launchpad.net/qemu/+bug/1753309
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6.h |  4 ++--
+ hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
+files changed, 29 insertions(+), 3 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6.h
++++ b/include/hw/arm/fsl-imx6.h
+@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
+ #define FSL_IMX6_HDMI_MASTER_IRQ 115
+ #define FSL_IMX6_HDMI_CEC_IRQ 116
+ #define FSL_IMX6_MLB150_LOW_IRQ 117
+-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
+-#define FSL_IMX6_ENET_MAC_IRQ 119
++#define FSL_IMX6_ENET_MAC_IRQ 118
++#define FSL_IMX6_ENET_MAC_1588_IRQ 119
+ #define FSL_IMX6_PCIE1_IRQ 120
+ #define FSL_IMX6_PCIE2_IRQ 121
+ #define FSL_IMX6_PCIE3_IRQ 122
+diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/net/imx_fec.c
++++ b/hw/net/imx_fec.c
+@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
+ static void imx_eth_update(IMXFECState *s)
+ {
+-    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
++    /*
++     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
++     * interrupts swapped. This worked with older versions of Linux (4.14
++     * and older) since Linux associated both interrupt lines with Ethernet
++     * MAC interrupts. Specifically,
++     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
++     *   timer interrupts. Those versions of Linux fail with versions of QEMU
++     *   with swapped interrupt assignments.
++     * - In linux 4.14, both interrupt lines were registered with the Ethernet
++     *   MAC interrupt handler. As a result, all versions of qemu happen to
++     *   work, though that is accidental.
++     * - In Linux 4.9 and older, the timer interrupt was registered directly
++     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
++     *   redirected to a GPIO interrupt to work around erratum ERR006687.
++     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
++     *   interrupt never fired since IOMUX is currently not supported in qemu.
++     *   Linux instead received MAC interrupts on the timer interrupt.
++     *   As a result, qemu versions with the swapped interrupt assignment work,
++     *   albeit accidentally, but qemu versions with the correct interrupt
++     *   assignment fail.
++     *
++     * To ensure that all versions of Linux work, generate ENET_INT_MAC
++     * interrrupts on both interrupt lines. This should be changed if and when
++     * qemu supports IOMUX.
++     */
++    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
++        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
+         qemu_set_irq(s->irq[1], 1);
+     } else {
+         qemu_set_irq(s->irq[1], 0);
+--
+.16.2

-New patch
+[Qemu-devel] [PULL 02/13] dump: Update correct kdump phys_base field for AArch64
+From: Wei Huang <wei@redhat.com>
+For guest kernel that supports KASLR, the load address can change every
+time when guest VM runs. To find the physical base address correctly,
+current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
+However this string pattern is only available on x86_64. AArch64 uses a
+different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
+QEMU dump uses the correct string on AArch64.
+Signed-off-by: Wei Huang <wei@redhat.com>
+Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
+Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ dump.c | 14 +++++++++++---
+file changed, 11 insertions(+), 3 deletions(-)
+diff --git a/dump.c b/dump.c
+index XXXXXXX..XXXXXXX 100644
+--- a/dump.c
++++ b/dump.c
+@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
+     lines = g_strsplit((char *)vmci, "\n", -1);
+     for (i = 0; lines[i]; i++) {
+-        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
+-            if (qemu_strtou64(lines[i] + 18, NULL, 16,
++        const char *prefix = NULL;
++
++        if (s->dump_info.d_machine == EM_X86_64) {
++            prefix = "NUMBER(phys_base)=";
++        } else if (s->dump_info.d_machine == EM_AARCH64) {
++            prefix = "NUMBER(PHYS_OFFSET)=";
++        }
++
++        if (prefix && g_str_has_prefix(lines[i], prefix)) {
++            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
+                               &phys_base) < 0) {
+-                warn_report("Failed to read NUMBER(phys_base)=");
++                warn_report("Failed to read %s", prefix);
+             } else {
+                 s->dump_info.phys_base = phys_base;
+             }
+--
+.16.2

-New patch
+[Qemu-devel] [PULL 03/13] char: i.MX: Simplify imx_update()
+From: Andrey Smirnov <andrew.smirnov@gmail.com>
+Code of imx_update() is slightly confusing since the "flags" variable
+doesn't really corespond to anything in real hardware and server as a
+kitchensink accumulating events normally reported via USR1 and USR2
+registers.
+Change the code to explicitly evaluate state of interrupts reported
+via USR1 and USR2 against corresponding masking bits and use the to
+detemine if IRQ line should be asserted or not.
+NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
+reasons:
+. Emulation code implements a single character FIFO, so this flag
+       will always be set since characters are trasmitted as a part of
+       the code emulating "push" into the FIFO
+. imx_update() is really just a function doing ORing and maksing
+       of reported events, so checking for UTS1_TXEMPTY should happen,
+       if it's ever really needed should probably happen outside of
+       it.
+Cc: qemu-devel@nongnu.org
+Cc: qemu-arm@nongnu.org
+Cc: Bill Paul <wpaul@windriver.com>
+Cc: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
+Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/char/imx_serial.c | 24 ++++++++++++++++--------
+file changed, 16 insertions(+), 8 deletions(-)
+diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/char/imx_serial.c
++++ b/hw/char/imx_serial.c
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+ static void imx_update(IMXSerialState *s)
+ {
+-    uint32_t flags;
++    uint32_t usr1;
++    uint32_t usr2;
++    uint32_t mask;
+-    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
+-    if (s->ucr1 & UCR1_TXMPTYEN) {
+-        flags |= (s->uts1 & UTS1_TXEMPTY);
+-    } else {
+-        flags &= ~USR1_TRDY;
+-    }
++    /*
++     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
++     * UCR1, so we can get away with something as simple as the
++     * following:
++     */
++    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
++    /*
++     * Bits that we want in USR2 are not as conveniently laid out,
++     * unfortunately.
++     */
++    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
++    usr2 = s->usr2 & mask;
+-    qemu_set_irq(s->irq, !!flags);
++    qemu_set_irq(s->irq, usr1 || usr2);
+ }
+ static void imx_serial_reset(IMXSerialState *s)
+--
+.16.2

-New patch
+[Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete" interrupt
+From: Andrey Smirnov <andrew.smirnov@gmail.com>
+Add support for "TX complete"/TXDC interrupt generate by real HW since
+it is needed to support guests other than Linux.
+Based on the patch by Bill Paul as found here:
+https://bugs.launchpad.net/qemu/+bug/1753314
+Cc: qemu-devel@nongnu.org
+Cc: qemu-arm@nongnu.org
+Cc: Bill Paul <wpaul@windriver.com>
+Cc: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Bill Paul <wpaul@windriver.com>
+Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
+Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/char/imx_serial.h |  3 +++
+ hw/char/imx_serial.c         | 20 +++++++++++++++++---
+files changed, 20 insertions(+), 3 deletions(-)
+diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/char/imx_serial.h
++++ b/include/hw/char/imx_serial.h
+@@ -XXX,XX +XXX,XX @@
+ #define UCR2_RXEN       (1<<1)    /* Receiver enable */
+ #define UCR2_SRST       (1<<0)    /* Reset complete */
++#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
++
+ #define UTS1_TXEMPTY    (1<<6)
+ #define UTS1_RXEMPTY    (1<<5)
+ #define UTS1_TXFULL     (1<<4)
+@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
+     uint32_t ubmr;
+     uint32_t ubrc;
+     uint32_t ucr3;
++    uint32_t ucr4;
+     qemu_irq irq;
+     CharBackend chr;
+diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/char/imx_serial.c
++++ b/hw/char/imx_serial.c
+@@ -XXX,XX +XXX,XX @@
+ static const VMStateDescription vmstate_imx_serial = {
+     .name = TYPE_IMX_SERIAL,
+-    .version_id = 1,
+-    .minimum_version_id = 1,
++    .version_id = 2,
++    .minimum_version_id = 2,
+     .fields = (VMStateField[]) {
+         VMSTATE_INT32(readbuff, IMXSerialState),
+         VMSTATE_UINT32(usr1, IMXSerialState),
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
+         VMSTATE_UINT32(ubmr, IMXSerialState),
+         VMSTATE_UINT32(ubrc, IMXSerialState),
+         VMSTATE_UINT32(ucr3, IMXSerialState),
++        VMSTATE_UINT32(ucr4, IMXSerialState),
+         VMSTATE_END_OF_LIST()
+     },
+ };
+@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
+      * unfortunately.
+      */
+     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
++    /*
++     * TCEN and TXDC are both bit 3
++     */
++    mask |= s->ucr4 & UCR4_TCEN;
++
+     usr2 = s->usr2 & mask;
+     qemu_set_irq(s->irq, usr1 || usr2);
+@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
+         return s->ucr3;
+     case 0x23: /* UCR4 */
++        return s->ucr4;
++
+     case 0x29: /* BRM Incremental */
+         return 0x0; /* TODO */
+@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
+              * qemu_chr_fe_write and background I/O callbacks */
+             qemu_chr_fe_write_all(&s->chr, &ch, 1);
+             s->usr1 &= ~USR1_TRDY;
++            s->usr2 &= ~USR2_TXDC;
+             imx_update(s);
+             s->usr1 |= USR1_TRDY;
++            s->usr2 |= USR2_TXDC;
+             imx_update(s);
+         }
+         break;
+@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
+         s->ucr3 = value & 0xffff;
+         break;
+-    case 0x2d: /* UTS1 */
+     case 0x23: /* UCR4 */
++        s->ucr4 = value & 0xffff;
++        imx_update(s);
++        break;
++
++    case 0x2d: /* UTS1 */
+         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
+                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
+         /* TODO */
+--
+.16.2

-New patch
+[Qemu-devel] [PULL 05/13] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
+For the rpi1 and 2 we want to boot the Linux kernel via some
+custom setup code that makes sure that the SMC instruction
+acts as a no-op, because it's used for cache maintenance.
+The rpi3 boots AArch64 kernels, which don't need SMC for
+cache maintenance and always expect to be booted non-secure.
+Don't fill in the aarch32-specific parts of the binfo struct.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
+---
+ hw/arm/raspi.c | 17 +++++++++++++----
+file changed, 13 insertions(+), 4 deletions(-)
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/raspi.c
++++ b/hw/arm/raspi.c
+@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+     binfo.board_id = raspi_boardid[version];
+     binfo.ram_size = ram_size;
+     binfo.nb_cpus = smp_cpus;
+-    binfo.board_setup_addr = BOARDSETUP_ADDR;
+-    binfo.write_board_setup = write_board_setup;
+-    binfo.secure_board_setup = true;
+-    binfo.secure_boot = true;
++
++    if (version <= 2) {
++        /* The rpi1 and 2 require some custom setup code to run in Secure
++         * mode before booting a kernel (to set up the SMC vectors so
++         * that we get a no-op SMC; this is used by Linux to call the
++         * firmware for some cache maintenance operations.
++         * The rpi3 doesn't need this.
++         */
++        binfo.board_setup_addr = BOARDSETUP_ADDR;
++        binfo.write_board_setup = write_board_setup;
++        binfo.secure_board_setup = true;
++        binfo.secure_boot = true;
++    }
+     /* Pi2 and Pi3 requires SMP setup */
+     if (version >= 2) {
+--
+.16.2

-[Qemu-devel] [PULL 4/4] target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
+[Qemu-devel] [PULL 06/13] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
-For v7M, writes to the CONTROL register are only permitted for
+Add some assertions that if we're about to boot an AArch64 kernel,
-privileged code. However even if the code is privileged, the
+the board code has not mistakenly set either secure_boot or
-write must not affect the SPSEL bit in the CONTROL register
+secure_board_setup. It doesn't make sense to set secure_boot,
-if the CPU is in Thread mode (as documented in the pseudocode
+because all AArch64 kernels must be booted in non-secure mode.
 for the MSR instruction). Implement this, instead of permitting
 SPSEL to be written in all cases.
-This was causing mbed applications not to run, because the
+It might in theory make sense to set secure_board_setup, but
-RTX RTOS they use relies on this behaviour.
+we don't currently support that, because only the AArch32
 bootloader[] code calls this hook; bootloader_aarch64[] does not.
 Since we don't have a current need for this functionality, just
 assert that we don't try to use it. If it's needed we'll add
 it later.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1498820791-8130-1-git-send-email-peter.maydell@linaro.org
+Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 13 ++++++++++---
+ hw/arm/boot.c | 7 +++++++
-file changed, 10 insertions(+), 3 deletions(-)
+file changed, 7 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/arm/boot.c
-+++ b/target/arm/helper.c
++++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
+@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
-         }
+                     } else {
-         break;
+                         env->pstate = PSTATE_MODE_EL1h;
-     case 20: /* CONTROL */
+                     }
--        switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
++                    /* AArch64 kernels never boot in secure mode */
--        env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK |
++                    assert(!info->secure_boot);
--                                  R_V7M_CONTROL_NPRIV_MASK);
++                    /* This hook is only supported for AArch32 currently:
-+        /* Writing to the SPSEL bit only has an effect if we are in
++                     * bootloader_aarch64[] will not call the hook, and
-+         * thread mode; other bits can be updated by any privileged code.
++                     * the code above has already dropped us into EL2 or EL1.
-+         * switch_v7m_sp() deals with updating the SPSEL bit in
++                     */
-+         * env->v7m.control, so we only need update the others.
++                    assert(!info->secure_board_setup);
-+         */
+                 }
-+        if (env->v7m.exception == 0) {
-+            switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
+                 /* Set to non-secure if not a secure boot */
 +        }
 +        env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;
 +        env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK;
          break;
      default:
          qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
 --
-.7.4
+.16.2

-New patch
+[Qemu-devel] [PULL 07/13] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
+If we're directly booting a Linux kernel and the CPU supports both
+EL3 and EL2, we start the kernel in EL2, as it expects. We must also
+set the SCR_EL3.HCE bit in this situation, so that the HVC
+instruction is enabled rather than UNDEFing. Otherwise at least some
+kernels will panic when trying to initialize KVM in the guest.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
+---
+ hw/arm/boot.c | 5 +++++
+file changed, 5 insertions(+)
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/boot.c
++++ b/hw/arm/boot.c
+@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+                     assert(!info->secure_board_setup);
+                 }
++                if (arm_feature(env, ARM_FEATURE_EL2)) {
++                    /* If we have EL2 then Linux expects the HVC insn to work */
++                    env->cp15.scr_el3 |= SCR_HCE;
++                }
++
+                 /* Set to non-secure if not a secure boot */
+                 if (!info->secure_boot &&
+                     (cs != first_cpu || !info->secure_board_setup)) {
+--
+.16.2

-New patch
+[Qemu-devel] [PULL 08/13] hw/arm/bcm2386: Fix parent type of bcm2386
+The TypeInfo and state struct for bcm2386 disagree about what the
+parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
+but the BCM2386State struct only defines the parent_obj field
+as DeviceState. This would have caused problems if anything
+actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
+Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
+need any of the additional functionality TYPE_SYS_BUS_DEVICE
+provides.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
+---
+ hw/arm/bcm2836.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/bcm2836.c
++++ b/hw/arm/bcm2836.c
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+ static const TypeInfo bcm2836_type_info = {
+     .name = TYPE_BCM2836,
+-    .parent = TYPE_SYS_BUS_DEVICE,
++    .parent = TYPE_DEVICE,
+     .instance_size = sizeof(BCM2836State),
+     .instance_init = bcm2836_init,
+     .class_init = bcm2836_class_init,
+--
+.16.2

-New patch
+[Qemu-devel] [PULL 09/13] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
+Our BCM2836 type is really a generic one that can be any of
+the bcm283x family. Rename it accordingly. We change only
+the names which are visible via the header file to the
+rest of the QEMU code, leaving private function names
+in bcm2836.c as they are.
+This is a preliminary to making bcm283x be an abstract
+parent class to specific types for the bcm2836 and bcm2837.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
+---
+ include/hw/arm/bcm2836.h | 12 ++++++------
+ hw/arm/bcm2836.c         | 17 +++++++++--------
+ hw/arm/raspi.c           | 16 ++++++++--------
+files changed, 23 insertions(+), 22 deletions(-)
+diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/bcm2836.h
++++ b/include/hw/arm/bcm2836.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/arm/bcm2835_peripherals.h"
+ #include "hw/intc/bcm2836_control.h"
+-#define TYPE_BCM2836 "bcm2836"
+-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
++#define TYPE_BCM283X "bcm283x"
++#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
+-#define BCM2836_NCPUS 4
++#define BCM283X_NCPUS 4
+-typedef struct BCM2836State {
++typedef struct BCM283XState {
+     /*< private >*/
+     DeviceState parent_obj;
+     /*< public >*/
+@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
+     char *cpu_type;
+     uint32_t enabled_cpus;
+-    ARMCPU cpus[BCM2836_NCPUS];
++    ARMCPU cpus[BCM283X_NCPUS];
+     BCM2836ControlState control;
+     BCM2835PeripheralState peripherals;
+-} BCM2836State;
++} BCM283XState;
+ #endif /* BCM2836_H */
+diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/bcm2836.c
++++ b/hw/arm/bcm2836.c
+@@ -XXX,XX +XXX,XX @@
+ static void bcm2836_init(Object *obj)
+ {
+-    BCM2836State *s = BCM2836(obj);
++    BCM283XState *s = BCM283X(obj);
+     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
+     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
+ static void bcm2836_realize(DeviceState *dev, Error **errp)
+ {
+-    BCM2836State *s = BCM2836(dev);
++    BCM283XState *s = BCM283X(dev);
+     Object *obj;
+     Error *err = NULL;
+     int n;
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+     /* common peripherals from bcm2835 */
+     obj = OBJECT(dev);
+-    for (n = 0; n < BCM2836_NCPUS; n++) {
++    for (n = 0; n < BCM283X_NCPUS; n++) {
+         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+                           s->cpu_type);
+         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
+         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
+-    for (n = 0; n < BCM2836_NCPUS; n++) {
++    for (n = 0; n < BCM283X_NCPUS; n++) {
+         /* Mirror bcm2836, which has clusterid set to 0xf
+          * TODO: this should be converted to a property of ARM_CPU
+          */
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+ }
+ static Property bcm2836_props[] = {
+-    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
+-    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
++    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
++    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
++                       BCM283X_NCPUS),
+     DEFINE_PROP_END_OF_LIST()
+ };
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
+ }
+ static const TypeInfo bcm2836_type_info = {
+-    .name = TYPE_BCM2836,
++    .name = TYPE_BCM283X,
+     .parent = TYPE_DEVICE,
+-    .instance_size = sizeof(BCM2836State),
++    .instance_size = sizeof(BCM283XState),
+     .instance_init = bcm2836_init,
+     .class_init = bcm2836_class_init,
+ };
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/raspi.c
++++ b/hw/arm/raspi.c
+@@ -XXX,XX +XXX,XX @@
+ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
+ typedef struct RasPiState {
+-    BCM2836State soc;
++    BCM283XState soc;
+     MemoryRegion ram;
+ } RasPiState;
+@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
+     BusState *bus;
+     DeviceState *carddev;
+-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
++    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
+     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
+                               &error_abort);
+@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
+     mc->no_floppy = 1;
+     mc->no_cdrom = 1;
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
+-    mc->max_cpus = BCM2836_NCPUS;
+-    mc->min_cpus = BCM2836_NCPUS;
+-    mc->default_cpus = BCM2836_NCPUS;
++    mc->max_cpus = BCM283X_NCPUS;
++    mc->min_cpus = BCM283X_NCPUS;
++    mc->default_cpus = BCM283X_NCPUS;
+     mc->default_ram_size = 1024 * 1024 * 1024;
+     mc->ignore_memory_transaction_failures = true;
+ };
+@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
+     mc->no_floppy = 1;
+     mc->no_cdrom = 1;
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
+-    mc->max_cpus = BCM2836_NCPUS;
+-    mc->min_cpus = BCM2836_NCPUS;
+-    mc->default_cpus = BCM2836_NCPUS;
++    mc->max_cpus = BCM283X_NCPUS;
++    mc->min_cpus = BCM283X_NCPUS;
++    mc->default_cpus = BCM283X_NCPUS;
+     mc->default_ram_size = 1024 * 1024 * 1024;
+ }
+ DEFINE_MACHINE("raspi3", raspi3_machine_init)
+--
+.16.2

-[Qemu-devel] [PULL 1/4] hw/misc: Add Exynos4210 Pseudo Random Number Generator
+[Qemu-devel] [PULL 10/13] hw/arm/bcm2836: Create proper bcm2837 device
-From: Krzysztof Kozlowski <krzk@kernel.org>
+The bcm2837 is pretty similar to the bcm2836, but it does have
 some differences. Notably, the MPIDR affinity aff1 values it
 sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
 uses, and if this is wrong Linux will not boot.
-Add emulation for Exynos4210 Pseudo Random Number Generator which could
+Rather than trying to have one device with properties that
-work on fixed seeds or with seeds provided by True Random Number
+configure it differently for the two cases, create two
-Generator block inside the SoC.
+separate QOM devices for the two SoCs. We use the same approach
 as hw/arm/aspeed_soc.c and share code and have a data table
 that might differ per-SoC. For the moment the two types don't
 actually have different behaviour.
-Implement only the fixed seeds part of it in polling mode (no
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-interrupts).
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
 ---
  include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
  hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
  hw/arm/raspi.c           |  3 ++-
 files changed, 53 insertions(+), 6 deletions(-)
-Emulation tested with two independent Linux kernel exynos-rng drivers:
+diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
 . New kcapi-rng interface (targeting Linux v4.12),
 . Old hwrng inteface
    # echo "exynos" > /sys/class/misc/hw_random/rng_current
    # dd if=/dev/hwrng of=/dev/null bs=1 count=16
 Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
 Message-id: 20170425180609.11004-1-krzk@kernel.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 [PMM: wrapped a few overlong lines; more efficient implementation
  of exynos4210_rng_seed_ready()]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/misc/Makefile.objs    |   2 +-
  hw/arm/exynos4210.c      |   4 +
  hw/misc/exynos4210_rng.c | 277 +++++++++++++++++++++++++++++++++++++++++++++++
 files changed, 282 insertions(+), 1 deletion(-)
  create mode 100644 hw/misc/exynos4210_rng.c
 diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Makefile.objs
+--- a/include/hw/arm/bcm2836.h
-+++ b/hw/misc/Makefile.objs
++++ b/include/hw/arm/bcm2836.h
-@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IVSHMEM) += ivshmem.o
+@@ -XXX,XX +XXX,XX @@
- obj-$(CONFIG_REALVIEW) += arm_sysctl.o
- obj-$(CONFIG_NSERIES) += cbus.o
+ #define BCM283X_NCPUS 4
- obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
--obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o
++/* These type names are for specific SoCs; other than instantiating
-+obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o exynos4210_rng.o
++ * them, code using these devices should always handle them via the
- obj-$(CONFIG_IMX) += imx_ccm.o
++ * BCM283x base class, so they have no BCM2836(obj) etc macros.
- obj-$(CONFIG_IMX) += imx31_ccm.o
++ */
- obj-$(CONFIG_IMX) += imx25_ccm.o
++#define TYPE_BCM2836 "bcm2836"
-diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
++#define TYPE_BCM2837 "bcm2837"
 +
  typedef struct BCM283XState {
      /*< private >*/
      DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
      BCM2835PeripheralState peripherals;
  } BCM283XState;
 +typedef struct BCM283XInfo BCM283XInfo;
 +
 +typedef struct BCM283XClass {
 +    DeviceClass parent_class;
 +    const BCM283XInfo *info;
 +} BCM283XClass;
 +
 +#define BCM283X_CLASS(klass) \
 +    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
 +#define BCM283X_GET_CLASS(obj) \
 +    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
 +
  #endif /* BCM2836_H */
 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/exynos4210.c
+--- a/hw/arm/bcm2836.c
-+++ b/hw/arm/exynos4210.c
++++ b/hw/arm/bcm2836.c
 @@ -XXX,XX +XXX,XX @@
- /* Clock controller SFR base address */
+ /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
- #define EXYNOS4210_CLK_BASE_ADDR            0x10030000
+ #define BCM2836_CONTROL_BASE    0x40000000
-+/* PRNG/HASH SFR base address */
++struct BCM283XInfo {
-+#define EXYNOS4210_RNG_BASE_ADDR            0x10830400
++    const char *name;
 +
  /* Display controllers (FIMD) */
  #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
      sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
      sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
 +    sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
      /* PWM */
      sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210_rng.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/exynos4210_rng.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + *  Exynos4210 Pseudo Random Nubmer Generator Emulation
 + *
 + *  Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
 + *
 + *  This program is free software; you can redistribute it and/or modify it
 + *  under the terms of the GNU General Public License as published by the
 + *  Free Software Foundation; either version 2 of the License, or
 + *  (at your option) any later version.
 + *
 + *  This program is distributed in the hope that it will be useful, but WITHOUT
 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + *  for more details.
 + *
 + *  You should have received a copy of the GNU General Public License along
 + *  with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "crypto/random.h"
 +#include "hw/sysbus.h"
 +#include "qemu/log.h"
 +
 +#define DEBUG_EXYNOS_RNG 0
 +
 +#define DPRINTF(fmt, ...) \
 +    do { \
 +        if (DEBUG_EXYNOS_RNG) { \
 +            printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \
 +        } \
 +    } while (0)
 +
 +#define TYPE_EXYNOS4210_RNG             "exynos4210.rng"
 +#define EXYNOS4210_RNG(obj) \
 +    OBJECT_CHECK(Exynos4210RngState, (obj), TYPE_EXYNOS4210_RNG)
 +
 +/*
 + * Exynos4220, PRNG, only polling mode is supported.
 + */
 +
 +/* RNG_CONTROL_1 register bitfields, reset value: 0x0 */
 +#define EXYNOS4210_RNG_CONTROL_1_PRNG           0x8
 +#define EXYNOS4210_RNG_CONTROL_1_START_INIT     BIT(4)
 +/* RNG_STATUS register bitfields, reset value: 0x1 */
 +#define EXYNOS4210_RNG_STATUS_PRNG_ERROR        BIT(7)
 +#define EXYNOS4210_RNG_STATUS_PRNG_DONE         BIT(5)
 +#define EXYNOS4210_RNG_STATUS_MSG_DONE          BIT(4)
 +#define EXYNOS4210_RNG_STATUS_PARTIAL_DONE      BIT(3)
 +#define EXYNOS4210_RNG_STATUS_PRNG_BUSY         BIT(2)
 +#define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1)
 +#define EXYNOS4210_RNG_STATUS_BUFFER_READY      BIT(0)
 +#define EXYNOS4210_RNG_STATUS_WRITE_MASK   (EXYNOS4210_RNG_STATUS_PRNG_DONE \
 +                                           | EXYNOS4210_RNG_STATUS_MSG_DONE \
 +                                           | EXYNOS4210_RNG_STATUS_PARTIAL_DONE)
 +
 +#define EXYNOS4210_RNG_CONTROL_1                  0x0
 +#define EXYNOS4210_RNG_STATUS                    0x10
 +#define EXYNOS4210_RNG_SEED_IN                  0x140
 +#define EXYNOS4210_RNG_SEED_IN_OFFSET(n)   (EXYNOS4210_RNG_SEED_IN + (n * 0x4))
 +#define EXYNOS4210_RNG_PRNG                     0x160
 +#define EXYNOS4210_RNG_PRNG_OFFSET(n)      (EXYNOS4210_RNG_PRNG + (n * 0x4))
 +
 +#define EXYNOS4210_RNG_PRNG_NUM                 5
 +
 +#define EXYNOS4210_RNG_REGS_MEM_SIZE            0x200
 +
 +typedef struct Exynos4210RngState {
 +    SysBusDevice parent_obj;
 +    MemoryRegion iomem;
 +
 +    int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM];
 +    /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */
 +    uint32_t seed_set;
 +
 +    /* Register values */
 +    uint32_t reg_control;
 +    uint32_t reg_status;
 +} Exynos4210RngState;
 +
 +static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s)
 +{
 +    uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM);
 +
 +    /* Return true if all the seed-set bits are set. */
 +    return (s->seed_set & mask) == mask;
 +}
 +
 +static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i,
 +                                    uint64_t val)
 +{
 +    /*
 +     * We actually ignore the seed and always generate true random numbers.
 +     * Theoretically this should not match the device as Exynos has
 +     * a Pseudo Random Number Generator but testing shown that it always
 +     * generates random numbers regardless of the seed value.
 +     */
 +    s->seed_set |= BIT(i);
 +
 +    /* If all seeds were written, update the status to reflect it */
 +    if (exynos4210_rng_seed_ready(s)) {
 +        s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
 +    } else {
 +        s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
 +    }
 +}
 +
 +static void exynos4210_rng_run_engine(Exynos4210RngState *s)
 +{
 +    Error *err = NULL;
 +    int ret;
 +
 +    /* Seed set? */
 +    if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) {
 +        goto out;
 +    }
 +
 +    /* PRNG engine chosen? */
 +    if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) {
 +        goto out;
 +    }
 +
 +    /* PRNG engine started? */
 +    if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) {
 +        goto out;
 +    }
 +
 +    /* Get randoms */
 +    ret = qcrypto_random_bytes((uint8_t *)s->randr_value,
 +                               sizeof(s->randr_value), &err);
 +    if (!ret) {
 +        /* Notify that PRNG is ready */
 +        s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE;
 +    } else {
 +        error_report_err(err);
 +    }
 +
 +out:
 +    /* Always clear start engine bit */
 +    s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT;
 +}
 +
 +static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset,
 +                                    unsigned size)
 +{
 +    Exynos4210RngState *s = (Exynos4210RngState *)opaque;
 +    uint32_t val = 0;
 +
 +    assert(size == 4);
 +
 +    switch (offset) {
 +    case EXYNOS4210_RNG_CONTROL_1:
 +        val = s->reg_control;
 +        break;
 +
 +    case EXYNOS4210_RNG_STATUS:
 +        val = s->reg_status;
 +        break;
 +
 +    case EXYNOS4210_RNG_PRNG_OFFSET(0):
 +    case EXYNOS4210_RNG_PRNG_OFFSET(1):
 +    case EXYNOS4210_RNG_PRNG_OFFSET(2):
 +    case EXYNOS4210_RNG_PRNG_OFFSET(3):
 +    case EXYNOS4210_RNG_PRNG_OFFSET(4):
 +        val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4];
 +        DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n",
 +                offset, val);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: bad read offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +    }
 +
 +    return val;
 +}
 +
 +static void exynos4210_rng_write(void *opaque, hwaddr offset,
 +                                 uint64_t val, unsigned size)
 +{
 +    Exynos4210RngState *s = (Exynos4210RngState *)opaque;
 +
 +    assert(size == 4);
 +
 +    switch (offset) {
 +    case EXYNOS4210_RNG_CONTROL_1:
 +        DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val);
 +        s->reg_control = val;
 +        exynos4210_rng_run_engine(s);
 +        break;
 +
 +    case EXYNOS4210_RNG_STATUS:
 +        /* For clearing status fields */
 +        s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK;
 +        s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK;
 +        break;
 +
 +    case EXYNOS4210_RNG_SEED_IN_OFFSET(0):
 +    case EXYNOS4210_RNG_SEED_IN_OFFSET(1):
 +    case EXYNOS4210_RNG_SEED_IN_OFFSET(2):
 +    case EXYNOS4210_RNG_SEED_IN_OFFSET(3):
 +    case EXYNOS4210_RNG_SEED_IN_OFFSET(4):
 +        exynos4210_rng_set_seed(s,
 +                                (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4,
 +                                val);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: bad write offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +    }
 +}
 +
 +static const MemoryRegionOps exynos4210_rng_ops = {
 +    .read = exynos4210_rng_read,
 +    .write = exynos4210_rng_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +};
 +
-+static void exynos4210_rng_reset(DeviceState *dev)
++static const BCM283XInfo bcm283x_socs[] = {
-+{
++    {
-+    Exynos4210RngState *s = EXYNOS4210_RNG(dev);
++        .name = TYPE_BCM2836,
-+
++    },
-+    s->reg_control = 0;
++    {
-+    s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY;
++        .name = TYPE_BCM2837,
-+    memset(s->randr_value, 0, sizeof(s->randr_value));
++    },
 +    s->seed_set = 0;
 +}
 +
 +static void exynos4210_rng_init(Object *obj)
 +{
 +    Exynos4210RngState *s = EXYNOS4210_RNG(obj);
 +    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s,
 +                          TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE);
 +    sysbus_init_mmio(dev, &s->iomem);
 +}
 +
 +static const VMStateDescription exynos4210_rng_vmstate = {
 +    .name = TYPE_EXYNOS4210_RNG,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState,
 +                            EXYNOS4210_RNG_PRNG_NUM),
 +        VMSTATE_UINT32(seed_set, Exynos4210RngState),
 +        VMSTATE_UINT32(reg_status, Exynos4210RngState),
 +        VMSTATE_UINT32(reg_control, Exynos4210RngState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
-+static void exynos4210_rng_class_init(ObjectClass *klass, void *data)
+ static void bcm2836_init(Object *obj)
-+{
+ {
-+    DeviceClass *dc = DEVICE_CLASS(klass);
+     BCM283XState *s = BCM283X(obj);
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
      DEFINE_PROP_END_OF_LIST()
  };
 -static void bcm2836_class_init(ObjectClass *oc, void *data)
 +static void bcm283x_class_init(ObjectClass *oc, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(oc);
 +    BCM283XClass *bc = BCM283X_CLASS(oc);
 -    dc->props = bcm2836_props;
 +    bc->info = data;
      dc->realize = bcm2836_realize;
 +    dc->props = bcm2836_props;
  }
 -static const TypeInfo bcm2836_type_info = {
 +static const TypeInfo bcm283x_type_info = {
      .name = TYPE_BCM283X,
      .parent = TYPE_DEVICE,
      .instance_size = sizeof(BCM283XState),
      .instance_init = bcm2836_init,
 -    .class_init = bcm2836_class_init,
 +    .class_size = sizeof(BCM283XClass),
 +    .abstract = true,
  };
  static void bcm2836_register_types(void)
  {
 -    type_register_static(&bcm2836_type_info);
 +    int i;
 +
-+    dc->reset = exynos4210_rng_reset;
++    type_register_static(&bcm283x_type_info);
-+    dc->vmsd = &exynos4210_rng_vmstate;
++    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
-+}
++        TypeInfo ti = {
-+
++            .name = bcm283x_socs[i].name,
-+static const TypeInfo exynos4210_rng_info = {
++            .parent = TYPE_BCM283X,
-+    .name          = TYPE_EXYNOS4210_RNG,
++            .class_init = bcm283x_class_init,
-+    .parent        = TYPE_SYS_BUS_DEVICE,
++            .class_data = (void *) &bcm283x_socs[i],
-+    .instance_size = sizeof(Exynos4210RngState),
++        };
-+    .instance_init = exynos4210_rng_init,
++        type_register(&ti);
-+    .class_init    = exynos4210_rng_class_init,
++    }
-+};
+ }
-+
-+static void exynos4210_rng_register(void)
+ type_init(bcm2836_register_types)
-+{
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
-+    type_register_static(&exynos4210_rng_info);
+index XXXXXXX..XXXXXXX 100644
-+}
+--- a/hw/arm/raspi.c
-+
++++ b/hw/arm/raspi.c
-+type_init(exynos4210_rng_register)
+@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
      BusState *bus;
      DeviceState *carddev;
 -    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
 +    object_initialize(&s->soc, sizeof(s->soc),
 +                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
      object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                                &error_abort);
 --
-.7.4
+.16.2

-[Qemu-devel] [PULL 2/4] aspeed: Register all watchdogs
+[Qemu-devel] [PULL 11/13] hw/arm/bcm2836: Use correct affinity values for BCM2837
-From: Joel Stanley <joel@jms.id.au>
+The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
 CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
 is required for Linux to boot.
-The ast2400 contains two and the ast2500 contains three watchdogs.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Add this information to the AspeedSoCInfo and realise the correct number
+Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
-of watchdogs for that each SoC type.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
 ---
  hw/arm/bcm2836.c | 11 +++++++----
 file changed, 7 insertions(+), 4 deletions(-)
-Signed-off-by: Joel Stanley <joel@jms.id.au>
+diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Tested-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/aspeed_soc.h |  4 +++-
  hw/arm/aspeed_soc.c         | 25 +++++++++++++++++--------
 files changed, 20 insertions(+), 9 deletions(-)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/aspeed_soc.h
+--- a/hw/arm/bcm2836.c
-+++ b/include/hw/arm/aspeed_soc.h
++++ b/hw/arm/bcm2836.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/net/ftgmac100.h"
+ struct BCM283XInfo {
- #define ASPEED_SPIS_NUM  2
+     const char *name;
-+#define ASPEED_WDTS_NUM  3
++    int clusterid;
+ };
- typedef struct AspeedSoCState {
-     /*< private >*/
+ static const BCM283XInfo bcm283x_socs[] = {
-@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
+     {
-     AspeedSMCState fmc;
+         .name = TYPE_BCM2836,
-     AspeedSMCState spi[ASPEED_SPIS_NUM];
++        .clusterid = 0xf,
-     AspeedSDMCState sdmc;
+     },
--    AspeedWDTState wdt;
+     {
-+    AspeedWDTState wdt[ASPEED_WDTS_NUM];
+         .name = TYPE_BCM2837,
-     FTGMAC100State ftgmac100;
++        .clusterid = 0x0,
  } AspeedSoCState;
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
      const hwaddr *spi_bases;
      const char *fmc_typename;
      const char **spi_typename;
 +    int wdts_num;
  } AspeedSoCInfo;
  typedef struct AspeedSoCClass {
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc.c
 +++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
          .spi_bases    = aspeed_soc_ast2400_spi_bases,
          .fmc_typename = "aspeed.smc.fmc",
          .spi_typename = aspeed_soc_ast2400_typenames,
 +        .wdts_num     = 2,
      }, {
          .name         = "ast2400-a1",
          .cpu_model    = "arm926",
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
          .spi_bases    = aspeed_soc_ast2400_spi_bases,
          .fmc_typename = "aspeed.smc.fmc",
          .spi_typename = aspeed_soc_ast2400_typenames,
 +        .wdts_num     = 2,
      }, {
          .name         = "ast2400",
          .cpu_model    = "arm926",
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
          .spi_bases    = aspeed_soc_ast2400_spi_bases,
          .fmc_typename = "aspeed.smc.fmc",
          .spi_typename = aspeed_soc_ast2400_typenames,
 +        .wdts_num     = 2,
      }, {
          .name         = "ast2500-a1",
          .cpu_model    = "arm1176",
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
          .spi_bases    = aspeed_soc_ast2500_spi_bases,
          .fmc_typename = "aspeed.smc.ast2500-fmc",
          .spi_typename = aspeed_soc_ast2500_typenames,
 +        .wdts_num     = 3,
      },
  };
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
-     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
+ static void bcm2836_realize(DeviceState *dev, Error **errp)
-                               "ram-size", &error_abort);
+ {
+     BCM283XState *s = BCM283X(dev);
--    object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
++    BCM283XClass *bc = BCM283X_GET_CLASS(dev);
--    object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
++    const BCM283XInfo *info = bc->info;
--    qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
+     Object *obj;
-+    for (i = 0; i < sc->info->wdts_num; i++) {
+     Error *err = NULL;
-+        object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
+     int n;
-+        object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
-+        qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());
+         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
-+    }
+     for (n = 0; n < BCM283X_NCPUS; n++) {
-     object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
+-        /* Mirror bcm2836, which has clusterid set to 0xf
-     object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
+-         * TODO: this should be converted to a property of ARM_CPU
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+-         */
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
+-        s->cpus[n].mp_affinity = 0xF00 | n;
++        /* TODO: this should be converted to a property of ARM_CPU */
-     /* Watch dog */
++        s->cpus[n].mp_affinity = (info->clusterid << 8) | n;
--    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
--    if (err) {
+         /* set periphbase/CBAR value for CPU-local registers */
--        error_propagate(errp, err);
+         object_property_set_int(OBJECT(&s->cpus[n]),
 -        return;
 +    for (i = 0; i < sc->info->wdts_num; i++) {
 +        object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
 +        if (err) {
 +            error_propagate(errp, err);
 +            return;
 +        }
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 +                        ASPEED_SOC_WDT_BASE + i * 0x20);
      }
 -    sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
      /* Net */
      qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
 --
-.7.4
+.16.2

-New patch
+[Qemu-devel] [PULL 12/13] hw/arm/bcm2836: Hardcode correct CPU type
+Now we have separate types for BCM2386 and BCM2387, we might as well
+just hard-code the CPU type they use rather than having it passed
+through as an object property. This then lets us put the initialization
+of the CPU object in init rather than realize.
+Note that this change means that it's no longer possible on
+the command line to use -cpu to ask for a different kind of
+CPU than the SoC supports. This was never a supported thing to
+do anyway; we were just not sanity-checking the command line.
+This does require us to only build the bcm2837 object on
+TARGET_AARCH64 configs, since otherwise it won't instantiate
+due to the missing cortex-a53 device and "make check" will fail.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
+---
+ hw/arm/bcm2836.c | 24 +++++++++++++++---------
+ hw/arm/raspi.c   |  2 --
+files changed, 15 insertions(+), 11 deletions(-)
+diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/bcm2836.c
++++ b/hw/arm/bcm2836.c
+@@ -XXX,XX +XXX,XX @@
+ struct BCM283XInfo {
+     const char *name;
++    const char *cpu_type;
+     int clusterid;
+ };
+ static const BCM283XInfo bcm283x_socs[] = {
+     {
+         .name = TYPE_BCM2836,
++        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
+         .clusterid = 0xf,
+     },
++#ifdef TARGET_AARCH64
+     {
+         .name = TYPE_BCM2837,
++        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
+         .clusterid = 0x0,
+     },
++#endif
+ };
+ static void bcm2836_init(Object *obj)
+ {
+     BCM283XState *s = BCM283X(obj);
++    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
++    const BCM283XInfo *info = bc->info;
++    int n;
++
++    for (n = 0; n < BCM283X_NCPUS; n++) {
++        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
++                          info->cpu_type);
++        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
++                                  &error_abort);
++    }
+     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
+     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+     /* common peripherals from bcm2835 */
+-    obj = OBJECT(dev);
+-    for (n = 0; n < BCM283X_NCPUS; n++) {
+-        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+-                          s->cpu_type);
+-        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+-                                  &error_abort);
+-    }
+-
+     obj = object_property_get_link(OBJECT(dev), "ram", &err);
+     if (obj == NULL) {
+         error_setg(errp, "%s: required ram link not found: %s",
+@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
+ }
+ static Property bcm2836_props[] = {
+-    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
+     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+                        BCM283X_NCPUS),
+     DEFINE_PROP_END_OF_LIST()
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/raspi.c
++++ b/hw/arm/raspi.c
+@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
+     /* Setup the SOC */
+     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
+                                    &error_abort);
+-    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
+-                            &error_abort);
+     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
+                             &error_abort);
+     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
+--
+.16.2

-[Qemu-devel] [PULL 3/4] ARM: KVM: Enable in-kernel timers with user space gic
+[Qemu-devel] [PULL 13/13] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs
-From: Alexander Graf <agraf@suse.de>
+The raspi3 has AArch64 CPUs, which means that our smpboot
 code for keeping the secondary CPUs in a pen needs to have
 a version for A64 as well as A32. Without this, the
 secondary CPUs go into an infinite loop of taking undefined
 instruction exceptions.
-When running with KVM enabled, you can choose between emulating the
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-gic in kernel or user space. If the kernel supports in-kernel virtualization
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-of the interrupt controller, it will default to that. If not, if will
+Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
-default to user space emulation.
+---
  hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
 file changed, 40 insertions(+), 1 deletion(-)
-Unfortunately when running in user mode gic emulation, we miss out on
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 interrupt events which are only available from kernel space, such as the timer.
 This patch leverages the new kernel/user space pending line synchronization for
 timer events. It does not handle PMU events yet.
 Signed-off-by: Alexander Graf <agraf@suse.de>
 Reviewed-by: Andrew Jones <drjones@redhat.com>
 Message-id: 1498577737-130264-1-git-send-email-agraf@suse.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/sysemu/kvm.h   | 11 +++++++++++
  target/arm/cpu.h       |  3 +++
  accel/kvm/kvm-all.c    |  5 +++++
  accel/stubs/kvm-stub.c |  5 +++++
  hw/intc/arm_gic.c      |  7 +++++++
  target/arm/kvm.c       | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++
 files changed, 82 insertions(+)
 diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/sysemu/kvm.h
+--- a/hw/arm/raspi.c
-+++ b/include/sysemu/kvm.h
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ int kvm_init_vcpu(CPUState *cpu);
+@@ -XXX,XX +XXX,XX @@
- int kvm_cpu_exec(CPUState *cpu);
+ #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
- int kvm_destroy_vcpu(CPUState *cpu);
+ #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
+ #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
-+/**
++#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
-+ * kvm_arm_supports_user_irq
-+ *
+ /* Table of Linux board IDs for different Pi versions */
-+ * Not all KVM implementations support notifications for kernel generated
+ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
-+ * interrupt events to user space. This function indicates whether the current
+@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
-+ * KVM implementation does support them.
+                        info->smp_loader_start);
-+ *
+ }
-+ * Returns: true if KVM supports using kernel generated IRQs from user space
-+ */
++static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
-+bool kvm_arm_supports_user_irq(void);
++{
 +    /* Unlike the AArch32 version we don't need to call the board setup hook.
 +     * The mechanism for doing the spin-table is also entirely different.
 +     * We must have four 64-bit fields at absolute addresses
 +     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
 +     * our CPUs, and which we must ensure are zero initialized before
 +     * the primary CPU goes into the kernel. We put these variables inside
 +     * a rom blob, so that the reset for ROM contents zeroes them for us.
 +     */
 +    static const uint32_t smpboot[] = {
 +        0xd2801b05, /*        mov     x5, 0xd8 */
 +        0xd53800a6, /*        mrs     x6, mpidr_el1 */
 +        0x924004c6, /*        and     x6, x6, #0x3 */
 +        0xd503205f, /* spin:  wfe */
 +        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
 +        0xb4ffffc4, /*        cbz     x4, spin */
 +        0xd2800000, /*        mov     x0, #0x0 */
 +        0xd2800001, /*        mov     x1, #0x0 */
 +        0xd2800002, /*        mov     x2, #0x0 */
 +        0xd2800003, /*        mov     x3, #0x0 */
 +        0xd61f0080, /*        br      x4 */
 +    };
 +
- #ifdef NEED_CPU_H
++    static const uint64_t spintables[] = {
- #include "cpu.h"
++        0, 0, 0, 0
++    };
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
      void *el_change_hook_opaque;
      int32_t node_id; /* NUMA node this CPU belongs to */
 +
-+    /* Used to synchronize KVM and QEMU in-kernel device levels */
++    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
-+    uint8_t device_irq_level;
++                       info->smp_loader_start);
- };
++    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
++                       SPINTABLE_ADDR);
  static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
 diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/kvm/kvm-all.c
 +++ b/accel/kvm/kvm-all.c
@@ -XXX,XX +XXX,XX @@ int kvm_has_intx_set_mask(void)
      return kvm_state->intx_set_mask;
  }
 +bool kvm_arm_supports_user_irq(void)
 +{
 +    return kvm_check_extension(kvm_state, KVM_CAP_ARM_USER_IRQ);
 +}
 +
- #ifdef KVM_CAP_SET_GUEST_DEBUG
+ static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
  struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *cpu,
                                                   target_ulong pc)
 diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/stubs/kvm-stub.c
 +++ b/accel/stubs/kvm-stub.c
@@ -XXX,XX +XXX,XX @@ void kvm_init_cpu_signals(CPUState *cpu)
  {
-     abort();
+     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
- }
+@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
-+
+     /* Pi2 and Pi3 requires SMP setup */
-+bool kvm_arm_supports_user_irq(void)
+     if (version >= 2) {
-+{
+         binfo.smp_loader_start = SMPBOOT_ADDR;
-+    return false;
+-        binfo.write_secondary_boot = write_smpboot;
-+}
++        if (version == 2) {
- #endif
++            binfo.write_secondary_boot = write_smpboot;
-diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
++        } else {
-index XXXXXXX..XXXXXXX 100644
++            binfo.write_secondary_boot = write_smpboot64;
---- a/hw/intc/arm_gic.c
++        }
-+++ b/hw/intc/arm_gic.c
+         binfo.secondary_cpu_reset_hook = reset_secondary;
@@ -XXX,XX +XXX,XX @@
  #include "qom/cpu.h"
  #include "qemu/log.h"
  #include "trace.h"
 +#include "sysemu/kvm.h"
  /* #define DEBUG_GIC */
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
          return;
      }
-+    if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
-+        error_setg(errp, "KVM with user space irqchip only works when the "
-+                         "host kernel supports KVM_CAP_ARM_USER_IRQ");
-+        return;
-+    }
-+
-     /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
-     gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
-diff --git a/target/arm/kvm.c b/target/arm/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm.c
-+++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
-      */
-     kvm_async_interrupts_allowed = true;
-+    /*
-+     * PSCI wakes up secondary cores, so we always need to
-+     * have vCPUs waiting in kernel space
-+     */
-+    kvm_halt_in_kernel_allowed = true;
-+
-     cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
-     type_register_static(&host_arm_cpu_type_info);
-@@ -XXX,XX +XXX,XX @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
- MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
- {
-+    ARMCPU *cpu;
-+    uint32_t switched_level;
-+
-+    if (kvm_irqchip_in_kernel()) {
-+        /*
-+         * We only need to sync timer states with user-space interrupt
-+         * controllers, so return early and save cycles if we don't.
-+         */
-+        return MEMTXATTRS_UNSPECIFIED;
-+    }
-+
-+    cpu = ARM_CPU(cs);
-+
-+    /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */
-+    if (run->s.regs.device_irq_level != cpu->device_irq_level) {
-+        switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level;
-+
-+        qemu_mutex_lock_iothread();
-+
-+        if (switched_level & KVM_ARM_DEV_EL1_VTIMER) {
-+            qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT],
-+                         !!(run->s.regs.device_irq_level &
-+                            KVM_ARM_DEV_EL1_VTIMER));
-+            switched_level &= ~KVM_ARM_DEV_EL1_VTIMER;
-+        }
-+
-+        if (switched_level & KVM_ARM_DEV_EL1_PTIMER) {
-+            qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS],
-+                         !!(run->s.regs.device_irq_level &
-+                            KVM_ARM_DEV_EL1_PTIMER));
-+            switched_level &= ~KVM_ARM_DEV_EL1_PTIMER;
-+        }
-+
-+        /* XXX PMU IRQ is missing */
-+
-+        if (switched_level) {
-+            qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n",
-+                          __func__, switched_level);
-+        }
-+
-+        /* We also mark unknown levels as processed to not waste cycles */
-+        cpu->device_irq_level = run->s.regs.device_irq_level;
-+        qemu_mutex_unlock_iothread();
-+    }
-+
-     return MEMTXATTRS_UNSPECIFIED;
- }
 --
-.7.4
+.16.2

A surprisingly short target-arm queue, but no point in holding
onto these waiting for more code to arrive :-)

thanks
-- PMM

The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:

Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711

for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:

target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)

----------------------------------------------------------------
target-arm queue:
 * v7M: ignore writes to CONTROL.SPSEL from Thread mode
 * KVM: Enable in-kernel timers with user space gic
 * aspeed: Register all watchdogs
 * hw/misc: Add Exynos4210 Pseudo Random Number Generator

----------------------------------------------------------------
Alexander Graf (1):
      ARM: KVM: Enable in-kernel timers with user space gic

Joel Stanley (1):
      aspeed: Register all watchdogs

Krzysztof Kozlowski (1):
      hw/misc: Add Exynos4210 Pseudo Random Number Generator

Peter Maydell (1):
      target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode

From: Krzysztof Kozlowski <krzk@kernel.org>

Add emulation for Exynos4210 Pseudo Random Number Generator which could
work on fixed seeds or with seeds provided by True Random Number
Generator block inside the SoC.

Implement only the fixed seeds part of it in polling mode (no
interrupts).

Emulation tested with two independent Linux kernel exynos-rng drivers:
1. New kcapi-rng interface (targeting Linux v4.12),
2. Old hwrng inteface
   # echo "exynos" > /sys/class/misc/hw_random/rng_current
   # dd if=/dev/hwrng of=/dev/null bs=1 count=16

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Message-id: 20170425180609.11004-1-krzk@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: wrapped a few overlong lines; more efficient implementation
 of exynos4210_rng_seed_ready()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/Makefile.objs    |   2 +-
 hw/arm/exynos4210.c      |   4 +
 hw/misc/exynos4210_rng.c | 277 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 282 insertions(+), 1 deletion(-)
 create mode 100644 hw/misc/exynos4210_rng.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IVSHMEM) += ivshmem.o
 obj-$(CONFIG_REALVIEW) += arm_sysctl.o
 obj-$(CONFIG_NSERIES) += cbus.o
 obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
-obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o
+obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o exynos4210_rng.o
 obj-$(CONFIG_IMX) += imx_ccm.o
 obj-$(CONFIG_IMX) += imx31_ccm.o
 obj-$(CONFIG_IMX) += imx25_ccm.o
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 /* Clock controller SFR base address */
 #define EXYNOS4210_CLK_BASE_ADDR            0x10030000
 
+/* PRNG/HASH SFR base address */
+#define EXYNOS4210_RNG_BASE_ADDR            0x10830400
+
 /* Display controllers (FIMD) */
 #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
 
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
     sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 
     sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
+    sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
 
     /* PWM */
     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210_rng.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/exynos4210_rng.c
@@ -XXX,XX +XXX,XX @@
+/*
+ *  Exynos4210 Pseudo Random Nubmer Generator Emulation
+ *
+ *  Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "crypto/random.h"
+#include "hw/sysbus.h"
+#include "qemu/log.h"
+
+#define DEBUG_EXYNOS_RNG 0
+
+#define DPRINTF(fmt, ...) \
+    do { \
+        if (DEBUG_EXYNOS_RNG) { \
+            printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \
+        } \
+    } while (0)
+
+#define TYPE_EXYNOS4210_RNG             "exynos4210.rng"
+#define EXYNOS4210_RNG(obj) \
+    OBJECT_CHECK(Exynos4210RngState, (obj), TYPE_EXYNOS4210_RNG)
+
+/*
+ * Exynos4220, PRNG, only polling mode is supported.
+ */
+
+/* RNG_CONTROL_1 register bitfields, reset value: 0x0 */
+#define EXYNOS4210_RNG_CONTROL_1_PRNG           0x8
+#define EXYNOS4210_RNG_CONTROL_1_START_INIT     BIT(4)
+/* RNG_STATUS register bitfields, reset value: 0x1 */
+#define EXYNOS4210_RNG_STATUS_PRNG_ERROR        BIT(7)
+#define EXYNOS4210_RNG_STATUS_PRNG_DONE         BIT(5)
+#define EXYNOS4210_RNG_STATUS_MSG_DONE          BIT(4)
+#define EXYNOS4210_RNG_STATUS_PARTIAL_DONE      BIT(3)
+#define EXYNOS4210_RNG_STATUS_PRNG_BUSY         BIT(2)
+#define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1)
+#define EXYNOS4210_RNG_STATUS_BUFFER_READY      BIT(0)
+#define EXYNOS4210_RNG_STATUS_WRITE_MASK   (EXYNOS4210_RNG_STATUS_PRNG_DONE \
+                                           | EXYNOS4210_RNG_STATUS_MSG_DONE \
+                                           | EXYNOS4210_RNG_STATUS_PARTIAL_DONE)
+
+#define EXYNOS4210_RNG_CONTROL_1                  0x0
+#define EXYNOS4210_RNG_STATUS                    0x10
+#define EXYNOS4210_RNG_SEED_IN                  0x140
+#define EXYNOS4210_RNG_SEED_IN_OFFSET(n)   (EXYNOS4210_RNG_SEED_IN + (n * 0x4))
+#define EXYNOS4210_RNG_PRNG                     0x160
+#define EXYNOS4210_RNG_PRNG_OFFSET(n)      (EXYNOS4210_RNG_PRNG + (n * 0x4))
+
+#define EXYNOS4210_RNG_PRNG_NUM                 5
+
+#define EXYNOS4210_RNG_REGS_MEM_SIZE            0x200
+
+typedef struct Exynos4210RngState {
+    SysBusDevice parent_obj;
+    MemoryRegion iomem;
+
+    int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM];
+    /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */
+    uint32_t seed_set;
+
+    /* Register values */
+    uint32_t reg_control;
+    uint32_t reg_status;
+} Exynos4210RngState;
+
+static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s)
+{
+    uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM);
+
+    /* Return true if all the seed-set bits are set. */
+    return (s->seed_set & mask) == mask;
+}
+
+static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i,
+                                    uint64_t val)
+{
+    /*
+     * We actually ignore the seed and always generate true random numbers.
+     * Theoretically this should not match the device as Exynos has
+     * a Pseudo Random Number Generator but testing shown that it always
+     * generates random numbers regardless of the seed value.
+     */
+    s->seed_set |= BIT(i);
+
+    /* If all seeds were written, update the status to reflect it */
+    if (exynos4210_rng_seed_ready(s)) {
+        s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
+    } else {
+        s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
+    }
+}
+
+static void exynos4210_rng_run_engine(Exynos4210RngState *s)
+{
+    Error *err = NULL;
+    int ret;
+
+    /* Seed set? */
+    if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) {
+        goto out;
+    }
+
+    /* PRNG engine chosen? */
+    if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) {
+        goto out;
+    }
+
+    /* PRNG engine started? */
+    if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) {
+        goto out;
+    }
+
+    /* Get randoms */
+    ret = qcrypto_random_bytes((uint8_t *)s->randr_value,
+                               sizeof(s->randr_value), &err);
+    if (!ret) {
+        /* Notify that PRNG is ready */
+        s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE;
+    } else {
+        error_report_err(err);
+    }
+
+out:
+    /* Always clear start engine bit */
+    s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT;
+}
+
+static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset,
+                                    unsigned size)
+{
+    Exynos4210RngState *s = (Exynos4210RngState *)opaque;
+    uint32_t val = 0;
+
+    assert(size == 4);
+
+    switch (offset) {
+    case EXYNOS4210_RNG_CONTROL_1:
+        val = s->reg_control;
+        break;
+
+    case EXYNOS4210_RNG_STATUS:
+        val = s->reg_status;
+        break;
+
+    case EXYNOS4210_RNG_PRNG_OFFSET(0):
+    case EXYNOS4210_RNG_PRNG_OFFSET(1):
+    case EXYNOS4210_RNG_PRNG_OFFSET(2):
+    case EXYNOS4210_RNG_PRNG_OFFSET(3):
+    case EXYNOS4210_RNG_PRNG_OFFSET(4):
+        val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4];
+        DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n",
+                offset, val);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: bad read offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+    }
+
+    return val;
+}
+
+static void exynos4210_rng_write(void *opaque, hwaddr offset,
+                                 uint64_t val, unsigned size)
+{
+    Exynos4210RngState *s = (Exynos4210RngState *)opaque;
+
+    assert(size == 4);
+
+    switch (offset) {
+    case EXYNOS4210_RNG_CONTROL_1:
+        DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val);
+        s->reg_control = val;
+        exynos4210_rng_run_engine(s);
+        break;
+
+    case EXYNOS4210_RNG_STATUS:
+        /* For clearing status fields */
+        s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK;
+        s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK;
+        break;
+
+    case EXYNOS4210_RNG_SEED_IN_OFFSET(0):
+    case EXYNOS4210_RNG_SEED_IN_OFFSET(1):
+    case EXYNOS4210_RNG_SEED_IN_OFFSET(2):
+    case EXYNOS4210_RNG_SEED_IN_OFFSET(3):
+    case EXYNOS4210_RNG_SEED_IN_OFFSET(4):
+        exynos4210_rng_set_seed(s,
+                                (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4,
+                                val);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: bad write offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+    }
+}
+
+static const MemoryRegionOps exynos4210_rng_ops = {
+    .read = exynos4210_rng_read,
+    .write = exynos4210_rng_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void exynos4210_rng_reset(DeviceState *dev)
+{
+    Exynos4210RngState *s = EXYNOS4210_RNG(dev);
+
+    s->reg_control = 0;
+    s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY;
+    memset(s->randr_value, 0, sizeof(s->randr_value));
+    s->seed_set = 0;
+}
+
+static void exynos4210_rng_init(Object *obj)
+{
+    Exynos4210RngState *s = EXYNOS4210_RNG(obj);
+    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+
+    memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s,
+                          TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE);
+    sysbus_init_mmio(dev, &s->iomem);
+}
+
+static const VMStateDescription exynos4210_rng_vmstate = {
+    .name = TYPE_EXYNOS4210_RNG,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState,
+                            EXYNOS4210_RNG_PRNG_NUM),
+        VMSTATE_UINT32(seed_set, Exynos4210RngState),
+        VMSTATE_UINT32(reg_status, Exynos4210RngState),
+        VMSTATE_UINT32(reg_control, Exynos4210RngState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void exynos4210_rng_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = exynos4210_rng_reset;
+    dc->vmsd = &exynos4210_rng_vmstate;
+}
+
+static const TypeInfo exynos4210_rng_info = {
+    .name          = TYPE_EXYNOS4210_RNG,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Exynos4210RngState),
+    .instance_init = exynos4210_rng_init,
+    .class_init    = exynos4210_rng_class_init,
+};
+
+static void exynos4210_rng_register(void)
+{
+    type_register_static(&exynos4210_rng_info);
+}
+
+type_init(exynos4210_rng_register)
-- 
2.7.4

From: Joel Stanley <joel@jms.id.au>

The ast2400 contains two and the ast2500 contains three watchdogs.
Add this information to the AspeedSoCInfo and realise the correct number
of watchdogs for that each SoC type.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/aspeed_soc.h |  4 +++-
 hw/arm/aspeed_soc.c         | 25 +++++++++++++++++--------
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/net/ftgmac100.h"
 
 #define ASPEED_SPIS_NUM  2
+#define ASPEED_WDTS_NUM  3
 
 typedef struct AspeedSoCState {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
     AspeedSMCState fmc;
     AspeedSMCState spi[ASPEED_SPIS_NUM];
     AspeedSDMCState sdmc;
-    AspeedWDTState wdt;
+    AspeedWDTState wdt[ASPEED_WDTS_NUM];
     FTGMAC100State ftgmac100;
 } AspeedSoCState;
 
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCInfo {
     const hwaddr *spi_bases;
     const char *fmc_typename;
     const char **spi_typename;
+    int wdts_num;
 } AspeedSoCInfo;
 
 typedef struct AspeedSoCClass {
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
         .spi_bases    = aspeed_soc_ast2400_spi_bases,
         .fmc_typename = "aspeed.smc.fmc",
         .spi_typename = aspeed_soc_ast2400_typenames,
+        .wdts_num     = 2,
     }, {
         .name         = "ast2400-a1",
         .cpu_model    = "arm926",
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
         .spi_bases    = aspeed_soc_ast2400_spi_bases,
         .fmc_typename = "aspeed.smc.fmc",
         .spi_typename = aspeed_soc_ast2400_typenames,
+        .wdts_num     = 2,
     }, {
         .name         = "ast2400",
         .cpu_model    = "arm926",
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
         .spi_bases    = aspeed_soc_ast2400_spi_bases,
         .fmc_typename = "aspeed.smc.fmc",
         .spi_typename = aspeed_soc_ast2400_typenames,
+        .wdts_num     = 2,
     }, {
         .name         = "ast2500-a1",
         .cpu_model    = "arm1176",
@@ -XXX,XX +XXX,XX @@ static const AspeedSoCInfo aspeed_socs[] = {
         .spi_bases    = aspeed_soc_ast2500_spi_bases,
         .fmc_typename = "aspeed.smc.ast2500-fmc",
         .spi_typename = aspeed_soc_ast2500_typenames,
+        .wdts_num     = 3,
     },
 };
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                               "ram-size", &error_abort);
 
-    object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
-    object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
-    qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
+    for (i = 0; i < sc->info->wdts_num; i++) {
+        object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
+        object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);
+        qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());
+    }
 
     object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
     object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
 
     /* Watch dog */
-    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
-    if (err) {
-        error_propagate(errp, err);
-        return;
+    for (i = 0; i < sc->info->wdts_num; i++) {
+        object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
+                        ASPEED_SOC_WDT_BASE + i * 0x20);
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
 
     /* Net */
     qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
-- 
2.7.4

From: Alexander Graf <agraf@suse.de>

When running with KVM enabled, you can choose between emulating the
gic in kernel or user space. If the kernel supports in-kernel virtualization
of the interrupt controller, it will default to that. If not, if will
default to user space emulation.

Unfortunately when running in user mode gic emulation, we miss out on
interrupt events which are only available from kernel space, such as the timer.
This patch leverages the new kernel/user space pending line synchronization for
timer events. It does not handle PMU events yet.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 1498577737-130264-1-git-send-email-agraf@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/sysemu/kvm.h   | 11 +++++++++++
 target/arm/cpu.h       |  3 +++
 accel/kvm/kvm-all.c    |  5 +++++
 accel/stubs/kvm-stub.c |  5 +++++
 hw/intc/arm_gic.c      |  7 +++++++
 target/arm/kvm.c       | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 82 insertions(+)

diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -XXX,XX +XXX,XX @@ int kvm_init_vcpu(CPUState *cpu);
 int kvm_cpu_exec(CPUState *cpu);
 int kvm_destroy_vcpu(CPUState *cpu);
 
+/**
+ * kvm_arm_supports_user_irq
+ *
+ * Not all KVM implementations support notifications for kernel generated
+ * interrupt events to user space. This function indicates whether the current
+ * KVM implementation does support them.
+ *
+ * Returns: true if KVM supports using kernel generated IRQs from user space
+ */
+bool kvm_arm_supports_user_irq(void);
+
 #ifdef NEED_CPU_H
 #include "cpu.h"
 
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     void *el_change_hook_opaque;
 
     int32_t node_id; /* NUMA node this CPU belongs to */
+
+    /* Used to synchronize KVM and QEMU in-kernel device levels */
+    uint8_t device_irq_level;
 };
 
 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -XXX,XX +XXX,XX @@ int kvm_has_intx_set_mask(void)
     return kvm_state->intx_set_mask;
 }
 
+bool kvm_arm_supports_user_irq(void)
+{
+    return kvm_check_extension(kvm_state, KVM_CAP_ARM_USER_IRQ);
+}
+
 #ifdef KVM_CAP_SET_GUEST_DEBUG
 struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *cpu,
                                                  target_ulong pc)
diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/stubs/kvm-stub.c
+++ b/accel/stubs/kvm-stub.c
@@ -XXX,XX +XXX,XX @@ void kvm_init_cpu_signals(CPUState *cpu)
 {
     abort();
 }
+
+bool kvm_arm_supports_user_irq(void)
+{
+    return false;
+}
 #endif
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -XXX,XX +XXX,XX @@
 #include "qom/cpu.h"
 #include "qemu/log.h"
 #include "trace.h"
+#include "sysemu/kvm.h"
 
 /* #define DEBUG_GIC */
 
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
+        error_setg(errp, "KVM with user space irqchip only works when the "
+                         "host kernel supports KVM_CAP_ARM_USER_IRQ");
+        return;
+    }
+
     /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
     gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
 
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
      */
     kvm_async_interrupts_allowed = true;
 
+    /*
+     * PSCI wakes up secondary cores, so we always need to
+     * have vCPUs waiting in kernel space
+     */
+    kvm_halt_in_kernel_allowed = true;
+
     cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
 
     type_register_static(&host_arm_cpu_type_info);
@@ -XXX,XX +XXX,XX @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
 
 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 {
+    ARMCPU *cpu;
+    uint32_t switched_level;
+
+    if (kvm_irqchip_in_kernel()) {
+        /*
+         * We only need to sync timer states with user-space interrupt
+         * controllers, so return early and save cycles if we don't.
+         */
+        return MEMTXATTRS_UNSPECIFIED;
+    }
+
+    cpu = ARM_CPU(cs);
+
+    /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */
+    if (run->s.regs.device_irq_level != cpu->device_irq_level) {
+        switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level;
+
+        qemu_mutex_lock_iothread();
+
+        if (switched_level & KVM_ARM_DEV_EL1_VTIMER) {
+            qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT],
+                         !!(run->s.regs.device_irq_level &
+                            KVM_ARM_DEV_EL1_VTIMER));
+            switched_level &= ~KVM_ARM_DEV_EL1_VTIMER;
+        }
+
+        if (switched_level & KVM_ARM_DEV_EL1_PTIMER) {
+            qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS],
+                         !!(run->s.regs.device_irq_level &
+                            KVM_ARM_DEV_EL1_PTIMER));
+            switched_level &= ~KVM_ARM_DEV_EL1_PTIMER;
+        }
+
+        /* XXX PMU IRQ is missing */
+
+        if (switched_level) {
+            qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n",
+                          __func__, switched_level);
+        }
+
+        /* We also mark unknown levels as processed to not waste cycles */
+        cpu->device_irq_level = run->s.regs.device_irq_level;
+        qemu_mutex_unlock_iothread();
+    }
+
     return MEMTXATTRS_UNSPECIFIED;
 }
 
-- 
2.7.4

For v7M, writes to the CONTROL register are only permitted for
privileged code. However even if the code is privileged, the
write must not affect the SPSEL bit in the CONTROL register
if the CPU is in Thread mode (as documented in the pseudocode
for the MSR instruction). Implement this, instead of permitting
SPSEL to be written in all cases.

This was causing mbed applications not to run, because the
RTX RTOS they use relies on this behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1498820791-8130-1-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
         }
         break;
     case 20: /* CONTROL */
-        switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
-        env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK |
-                                  R_V7M_CONTROL_NPRIV_MASK);
+        /* Writing to the SPSEL bit only has an effect if we are in
+         * thread mode; other bits can be updated by any privileged code.
+         * switch_v7m_sp() deals with updating the SPSEL bit in
+         * env->v7m.control, so we only need update the others.
+         */
+        if (env->v7m.exception == 0) {
+            switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
+        }
+        env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;
+        env->v7m.control |= val & R_V7M_CONTROL_NPRIV_MASK;
         break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
-- 
2.7.4

Arm patch queue -- these are all bug fix patches but we might
as well put them in to rc0...

thanks
-- PMM

The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-03-19 11:44:26 +0000)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180319

for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:

hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * fsl-imx6: Fix incorrect Ethernet interrupt defines
 * dump: Update correct kdump phys_base field for AArch64
 * char: i.MX: Add support for "TX complete" interrupt
 * bcm2836/raspi: Fix various bugs resulting in panics trying
   to boot a Debian Linux kernel on raspi3

----------------------------------------------------------------
Andrey Smirnov (2):
      char: i.MX: Simplify imx_update()
      char: i.MX: Add support for "TX complete" interrupt

Guenter Roeck (1):
      fsl-imx6: Swap Ethernet interrupt defines

Peter Maydell (9):
      hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
      hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64
      hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
      hw/arm/bcm2386: Fix parent type of bcm2386
      hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
      hw/arm/bcm2836: Create proper bcm2837 device
      hw/arm/bcm2836: Use correct affinity values for BCM2837
      hw/arm/bcm2836: Hardcode correct CPU type
      hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

Wei Huang (1):
      dump: Update correct kdump phys_base field for AArch64

From: Guenter Roeck <linux@roeck-us.net>

The sabrelite machine model used by qemu-system-arm is based on the
Freescale/NXP i.MX6Q processor. This SoC has an on-board ethernet
controller which is supported in QEMU using the imx_fec.c module
(actually called imx.enet for this model.)

The include/hw/arm/fsm-imx6.h file defines the interrupt vectors for the
imx.enet device like this:

#define FSL_IMX6_ENET_MAC_1588_IRQ 118
 #define FSL_IMX6_ENET_MAC_IRQ 119

According to https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf,
page 225, in Table 3-1. ARM Cortex A9 domain interrupt summary,
interrupts are as follows.

150 ENET MAC 0 IRQ
151 ENET MAC 0 1588 Timer interrupt

where

150 - 32 == 118
151 - 32 == 119

In other words, the vector definitions in the fsl-imx6.h file are reversed.

Fixing the interrupts alone causes problems with older Linux kernels:
The Ethernet interface will fail to probe with Linux v4.9 and earlier.
Linux v4.1 and earlier will crash due to a bug in Ethernet driver probe
error handling. This is a Linux kernel problem, not a qemu problem:
the Linux kernel only worked by accident since it requested both interrupts.

For backward compatibility, generate the Ethernet interrupt on both interrupt
lines. This was shown to work from all Linux kernel releases starting with
v3.16.

Link: https://bugs.launchpad.net/qemu/+bug/1753309
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1520723090-22130-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6.h |  4 ++--
 hw/net/imx_fec.c          | 28 +++++++++++++++++++++++++++-
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
 #define FSL_IMX6_HDMI_MASTER_IRQ 115
 #define FSL_IMX6_HDMI_CEC_IRQ 116
 #define FSL_IMX6_MLB150_LOW_IRQ 117
-#define FSL_IMX6_ENET_MAC_1588_IRQ 118
-#define FSL_IMX6_ENET_MAC_IRQ 119
+#define FSL_IMX6_ENET_MAC_IRQ 118
+#define FSL_IMX6_ENET_MAC_1588_IRQ 119
 #define FSL_IMX6_PCIE1_IRQ 120
 #define FSL_IMX6_PCIE2_IRQ 121
 #define FSL_IMX6_PCIE3_IRQ 122
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
 
 static void imx_eth_update(IMXFECState *s)
 {
-    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) {
+    /*
+     * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
+     * interrupts swapped. This worked with older versions of Linux (4.14
+     * and older) since Linux associated both interrupt lines with Ethernet
+     * MAC interrupts. Specifically,
+     * - Linux 4.15 and later have separate interrupt handlers for the MAC and
+     *   timer interrupts. Those versions of Linux fail with versions of QEMU
+     *   with swapped interrupt assignments.
+     * - In linux 4.14, both interrupt lines were registered with the Ethernet
+     *   MAC interrupt handler. As a result, all versions of qemu happen to
+     *   work, though that is accidental.
+     * - In Linux 4.9 and older, the timer interrupt was registered directly
+     *   with the Ethernet MAC interrupt handler. The MAC interrupt was
+     *   redirected to a GPIO interrupt to work around erratum ERR006687.
+     *   This was implemented using the SOC's IOMUX block. In qemu, this GPIO
+     *   interrupt never fired since IOMUX is currently not supported in qemu.
+     *   Linux instead received MAC interrupts on the timer interrupt.
+     *   As a result, qemu versions with the swapped interrupt assignment work,
+     *   albeit accidentally, but qemu versions with the correct interrupt
+     *   assignment fail.
+     *
+     * To ensure that all versions of Linux work, generate ENET_INT_MAC
+     * interrrupts on both interrupt lines. This should be changed if and when
+     * qemu supports IOMUX.
+     */
+    if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] &
+        (ENET_INT_MAC | ENET_INT_TS_TIMER)) {
         qemu_set_irq(s->irq[1], 1);
     } else {
         qemu_set_irq(s->irq[1], 0);
-- 
2.16.2

From: Wei Huang <wei@redhat.com>

For guest kernel that supports KASLR, the load address can change every
time when guest VM runs. To find the physical base address correctly,
current QEMU dump searches VMCOREINFO for the string "NUMBER(phys_base)=".
However this string pattern is only available on x86_64. AArch64 uses a
different field, called "NUMBER(PHYS_OFFSET)=". This patch makes sure
QEMU dump uses the correct string on AArch64.

Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 1520615003-20869-1-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 dump.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/dump.c b/dump.c
index XXXXXXX..XXXXXXX 100644
--- a/dump.c
+++ b/dump.c
@@ -XXX,XX +XXX,XX @@ static void vmcoreinfo_update_phys_base(DumpState *s)
 
     lines = g_strsplit((char *)vmci, "\n", -1);
     for (i = 0; lines[i]; i++) {
-        if (g_str_has_prefix(lines[i], "NUMBER(phys_base)=")) {
-            if (qemu_strtou64(lines[i] + 18, NULL, 16,
+        const char *prefix = NULL;
+
+        if (s->dump_info.d_machine == EM_X86_64) {
+            prefix = "NUMBER(phys_base)=";
+        } else if (s->dump_info.d_machine == EM_AARCH64) {
+            prefix = "NUMBER(PHYS_OFFSET)=";
+        }
+
+        if (prefix && g_str_has_prefix(lines[i], prefix)) {
+            if (qemu_strtou64(lines[i] + strlen(prefix), NULL, 16,
                               &phys_base) < 0) {
-                warn_report("Failed to read NUMBER(phys_base)=");
+                warn_report("Failed to read %s", prefix);
             } else {
                 s->dump_info.phys_base = phys_base;
             }
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Code of imx_update() is slightly confusing since the "flags" variable
doesn't really corespond to anything in real hardware and server as a
kitchensink accumulating events normally reported via USR1 and USR2
registers.

Change the code to explicitly evaluate state of interrupts reported
via USR1 and USR2 against corresponding masking bits and use the to
detemine if IRQ line should be asserted or not.

NOTE: Check for UTS1_TXEMPTY being set has been dropped for two
reasons:

1. Emulation code implements a single character FIFO, so this flag
       will always be set since characters are trasmitted as a part of
       the code emulating "push" into the FIFO

2. imx_update() is really just a function doing ORing and maksing
       of reported events, so checking for UTS1_TXEMPTY should happen,
       if it's ever really needed should probably happen outside of
       it.

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-1-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/imx_serial.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
 
 static void imx_update(IMXSerialState *s)
 {
-    uint32_t flags;
+    uint32_t usr1;
+    uint32_t usr2;
+    uint32_t mask;
 
-    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
-    if (s->ucr1 & UCR1_TXMPTYEN) {
-        flags |= (s->uts1 & UTS1_TXEMPTY);
-    } else {
-        flags &= ~USR1_TRDY;
-    }
+    /*
+     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
+     * UCR1, so we can get away with something as simple as the
+     * following:
+     */
+    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
+    /*
+     * Bits that we want in USR2 are not as conveniently laid out,
+     * unfortunately.
+     */
+    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    usr2 = s->usr2 & mask;
 
-    qemu_set_irq(s->irq, !!flags);
+    qemu_set_irq(s->irq, usr1 || usr2);
 }
 
 static void imx_serial_reset(IMXSerialState *s)
-- 
2.16.2

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add support for "TX complete"/TXDC interrupt generate by real HW since
it is needed to support guests other than Linux.

Based on the patch by Bill Paul as found here:
https://bugs.launchpad.net/qemu/+bug/1753314

Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bill Paul <wpaul@windriver.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/char/imx_serial.h |  3 +++
 hw/char/imx_serial.c         | 20 +++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -XXX,XX +XXX,XX @@
 #define UCR2_RXEN       (1<<1)    /* Receiver enable */
 #define UCR2_SRST       (1<<0)    /* Reset complete */
 
+#define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
+
 #define UTS1_TXEMPTY    (1<<6)
 #define UTS1_RXEMPTY    (1<<5)
 #define UTS1_TXFULL     (1<<4)
@@ -XXX,XX +XXX,XX @@ typedef struct IMXSerialState {
     uint32_t ubmr;
     uint32_t ubrc;
     uint32_t ucr3;
+    uint32_t ucr4;
 
     qemu_irq irq;
     CharBackend chr;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -XXX,XX +XXX,XX @@
 
 static const VMStateDescription vmstate_imx_serial = {
     .name = TYPE_IMX_SERIAL,
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_INT32(readbuff, IMXSerialState),
         VMSTATE_UINT32(usr1, IMXSerialState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_serial = {
         VMSTATE_UINT32(ubmr, IMXSerialState),
         VMSTATE_UINT32(ubrc, IMXSerialState),
         VMSTATE_UINT32(ucr3, IMXSerialState),
+        VMSTATE_UINT32(ucr4, IMXSerialState),
         VMSTATE_END_OF_LIST()
     },
 };
@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)
      * unfortunately.
      */
     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+    /*
+     * TCEN and TXDC are both bit 3
+     */
+    mask |= s->ucr4 & UCR4_TCEN;
+
     usr2 = s->usr2 & mask;
 
     qemu_set_irq(s->irq, usr1 || usr2);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
         return s->ucr3;
 
     case 0x23: /* UCR4 */
+        return s->ucr4;
+
     case 0x29: /* BRM Incremental */
         return 0x0; /* TODO */
 
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
              * qemu_chr_fe_write and background I/O callbacks */
             qemu_chr_fe_write_all(&s->chr, &ch, 1);
             s->usr1 &= ~USR1_TRDY;
+            s->usr2 &= ~USR2_TXDC;
             imx_update(s);
             s->usr1 |= USR1_TRDY;
+            s->usr2 |= USR2_TXDC;
             imx_update(s);
         }
         break;
@@ -XXX,XX +XXX,XX @@ static void imx_serial_write(void *opaque, hwaddr offset,
         s->ucr3 = value & 0xffff;
         break;
 
-    case 0x2d: /* UTS1 */
     case 0x23: /* UCR4 */
+        s->ucr4 = value & 0xffff;
+        imx_update(s);
+        break;
+
+    case 0x2d: /* UTS1 */
         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
         /* TODO */
-- 
2.16.2

For the rpi1 and 2 we want to boot the Linux kernel via some
custom setup code that makes sure that the SMC instruction
acts as a no-op, because it's used for cache maintenance.
The rpi3 boots AArch64 kernels, which don't need SMC for
cache maintenance and always expect to be booted non-secure.
Don't fill in the aarch32-specific parts of the binfo struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-2-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     binfo.board_id = raspi_boardid[version];
     binfo.ram_size = ram_size;
     binfo.nb_cpus = smp_cpus;
-    binfo.board_setup_addr = BOARDSETUP_ADDR;
-    binfo.write_board_setup = write_board_setup;
-    binfo.secure_board_setup = true;
-    binfo.secure_boot = true;
+
+    if (version <= 2) {
+        /* The rpi1 and 2 require some custom setup code to run in Secure
+         * mode before booting a kernel (to set up the SMC vectors so
+         * that we get a no-op SMC; this is used by Linux to call the
+         * firmware for some cache maintenance operations.
+         * The rpi3 doesn't need this.
+         */
+        binfo.board_setup_addr = BOARDSETUP_ADDR;
+        binfo.write_board_setup = write_board_setup;
+        binfo.secure_board_setup = true;
+        binfo.secure_boot = true;
+    }
 
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
-- 
2.16.2

Add some assertions that if we're about to boot an AArch64 kernel,
the board code has not mistakenly set either secure_boot or
secure_board_setup. It doesn't make sense to set secure_boot,
because all AArch64 kernels must be booted in non-secure mode.

It might in theory make sense to set secure_board_setup, but
we don't currently support that, because only the AArch32
bootloader[] code calls this hook; bootloader_aarch64[] does not.
Since we don't have a current need for this functionality, just
assert that we don't try to use it. If it's needed we'll add
it later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-3-peter.maydell@linaro.org
---
 hw/arm/boot.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     } else {
                         env->pstate = PSTATE_MODE_EL1h;
                     }
+                    /* AArch64 kernels never boot in secure mode */
+                    assert(!info->secure_boot);
+                    /* This hook is only supported for AArch32 currently:
+                     * bootloader_aarch64[] will not call the hook, and
+                     * the code above has already dropped us into EL2 or EL1.
+                     */
+                    assert(!info->secure_board_setup);
                 }
 
                 /* Set to non-secure if not a secure boot */
-- 
2.16.2

If we're directly booting a Linux kernel and the CPU supports both
EL3 and EL2, we start the kernel in EL2, as it expects. We must also
set the SCR_EL3.HCE bit in this situation, so that the HVC
instruction is enabled rather than UNDEFing. Otherwise at least some
kernels will panic when trying to initialize KVM in the guest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180313153458.26822-4-peter.maydell@linaro.org
---
 hw/arm/boot.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     assert(!info->secure_board_setup);
                 }
 
+                if (arm_feature(env, ARM_FEATURE_EL2)) {
+                    /* If we have EL2 then Linux expects the HVC insn to work */
+                    env->cp15.scr_el3 |= SCR_HCE;
+                }
+
                 /* Set to non-secure if not a secure boot */
                 if (!info->secure_boot &&
                     (cs != first_cpu || !info->secure_board_setup)) {
-- 
2.16.2

The TypeInfo and state struct for bcm2386 disagree about what the
parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE,
but the BCM2386State struct only defines the parent_obj field
as DeviceState. This would have caused problems if anything
actually tried to treat the object as a TYPE_SYS_BUS_DEVICE.
Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't
need any of the additional functionality TYPE_SYS_BUS_DEVICE
provides.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-5-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo bcm2836_type_info = {
     .name = TYPE_BCM2836,
-    .parent = TYPE_SYS_BUS_DEVICE,
+    .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM2836State),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
-- 
2.16.2

Our BCM2836 type is really a generic one that can be any of
the bcm283x family. Rename it accordingly. We change only
the names which are visible via the header file to the
rest of the QEMU code, leaving private function names
in bcm2836.c as they are.

This is a preliminary to making bcm283x be an abstract
parent class to specific types for the bcm2836 and bcm2837.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-6-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 12 ++++++------
 hw/arm/bcm2836.c         | 17 +++++++++--------
 hw/arm/raspi.c           | 16 ++++++++--------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
-#define TYPE_BCM2836 "bcm2836"
-#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+#define TYPE_BCM283X "bcm283x"
+#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
 
-#define BCM2836_NCPUS 4
+#define BCM283X_NCPUS 4
 
-typedef struct BCM2836State {
+typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
     /*< public >*/
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836State {
     char *cpu_type;
     uint32_t enabled_cpus;
 
-    ARMCPU cpus[BCM2836_NCPUS];
+    ARMCPU cpus[BCM283X_NCPUS];
     BCM2836ControlState control;
     BCM2835PeripheralState peripherals;
-} BCM2836State;
+} BCM283XState;
 
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 static void bcm2836_init(Object *obj)
 {
-    BCM2836State *s = BCM2836(obj);
+    BCM283XState *s = BCM283X(obj);
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_init(Object *obj)
 
 static void bcm2836_realize(DeviceState *dev, Error **errp)
 {
-    BCM2836State *s = BCM2836(dev);
+    BCM283XState *s = BCM283X(dev);
     Object *obj;
     Error *err = NULL;
     int n;
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     /* common peripherals from bcm2835 */
 
     obj = OBJECT(dev);
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
                           s->cpu_type);
         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
         qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
 
-    for (n = 0; n < BCM2836_NCPUS; n++) {
+    for (n = 0; n < BCM283X_NCPUS; n++) {
         /* Mirror bcm2836, which has clusterid set to 0xf
          * TODO: this should be converted to a property of ARM_CPU
          */
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
-    DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
+    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
+    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
+                       BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
 }
 
 static const TypeInfo bcm2836_type_info = {
-    .name = TYPE_BCM2836,
+    .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
-    .instance_size = sizeof(BCM2836State),
+    .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
     .class_init = bcm2836_class_init,
 };
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
 
 typedef struct RasPiState {
-    BCM2836State soc;
+    BCM283XState soc;
     MemoryRegion ram;
 } RasPiState;
 
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836);
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
@@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
     mc->ignore_memory_transaction_failures = true;
 };
@@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc)
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
-    mc->max_cpus = BCM2836_NCPUS;
-    mc->min_cpus = BCM2836_NCPUS;
-    mc->default_cpus = BCM2836_NCPUS;
+    mc->max_cpus = BCM283X_NCPUS;
+    mc->min_cpus = BCM283X_NCPUS;
+    mc->default_cpus = BCM283X_NCPUS;
     mc->default_ram_size = 1024 * 1024 * 1024;
 }
 DEFINE_MACHINE("raspi3", raspi3_machine_init)
-- 
2.16.2

The bcm2837 is pretty similar to the bcm2836, but it does have
some differences. Notably, the MPIDR affinity aff1 values it
sets for the CPUs are 0x0, rather than the 0xf that the bcm2836
uses, and if this is wrong Linux will not boot.

Rather than trying to have one device with properties that
configure it differently for the two cases, create two
separate QOM devices for the two SoCs. We use the same approach
as hw/arm/aspeed_soc.c and share code and have a data table
that might differ per-SoC. For the moment the two types don't
actually have different behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-7-peter.maydell@linaro.org
---
 include/hw/arm/bcm2836.h | 19 +++++++++++++++++++
 hw/arm/bcm2836.c         | 37 ++++++++++++++++++++++++++++++++-----
 hw/arm/raspi.c           |  3 ++-
 3 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 
 #define BCM283X_NCPUS 4
 
+/* These type names are for specific SoCs; other than instantiating
+ * them, code using these devices should always handle them via the
+ * BCM283x base class, so they have no BCM2836(obj) etc macros.
+ */
+#define TYPE_BCM2836 "bcm2836"
+#define TYPE_BCM2837 "bcm2837"
+
 typedef struct BCM283XState {
     /*< private >*/
     DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XState {
     BCM2835PeripheralState peripherals;
 } BCM283XState;
 
+typedef struct BCM283XInfo BCM283XInfo;
+
+typedef struct BCM283XClass {
+    DeviceClass parent_class;
+    const BCM283XInfo *info;
+} BCM283XClass;
+
+#define BCM283X_CLASS(klass) \
+    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+#define BCM283X_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+
 #endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
 #define BCM2836_CONTROL_BASE    0x40000000
 
+struct BCM283XInfo {
+    const char *name;
+};
+
+static const BCM283XInfo bcm283x_socs[] = {
+    {
+        .name = TYPE_BCM2836,
+    },
+    {
+        .name = TYPE_BCM2837,
+    },
+};
+
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
@@ -XXX,XX +XXX,XX @@ static Property bcm2836_props[] = {
     DEFINE_PROP_END_OF_LIST()
 };
 
-static void bcm2836_class_init(ObjectClass *oc, void *data)
+static void bcm283x_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
+    BCM283XClass *bc = BCM283X_CLASS(oc);
 
-    dc->props = bcm2836_props;
+    bc->info = data;
     dc->realize = bcm2836_realize;
+    dc->props = bcm2836_props;
 }
 
-static const TypeInfo bcm2836_type_info = {
+static const TypeInfo bcm283x_type_info = {
     .name = TYPE_BCM283X,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(BCM283XState),
     .instance_init = bcm2836_init,
-    .class_init = bcm2836_class_init,
+    .class_size = sizeof(BCM283XClass),
+    .abstract = true,
 };
 
 static void bcm2836_register_types(void)
 {
-    type_register_static(&bcm2836_type_info);
+    int i;
+
+    type_register_static(&bcm283x_type_info);
+    for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
+        TypeInfo ti = {
+            .name = bcm283x_socs[i].name,
+            .parent = TYPE_BCM283X,
+            .class_init = bcm283x_class_init,
+            .class_data = (void *) &bcm283x_socs[i],
+        };
+        type_register(&ti);
+    }
 }
 
 type_init(bcm2836_register_types)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     BusState *bus;
     DeviceState *carddev;
 
-    object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X);
+    object_initialize(&s->soc, sizeof(s->soc),
+                      version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                               &error_abort);
 
-- 
2.16.2

The BCM2837 sets the Aff1 field of the MPIDR affinity values for the
CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it
is required for Linux to boot.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-8-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Now we have separate types for BCM2386 and BCM2387, we might as well
just hard-code the CPU type they use rather than having it passed
through as an object property. This then lets us put the initialization
of the CPU object in init rather than realize.

Note that this change means that it's no longer possible on
the command line to use -cpu to ask for a different kind of
CPU than the SoC supports. This was never a supported thing to
do anyway; we were just not sanity-checking the command line.

This does require us to only build the bcm2837 object on
TARGET_AARCH64 configs, since otherwise it won't instantiate
due to the missing cortex-a53 device and "make check" will fail.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-9-peter.maydell@linaro.org
---
 hw/arm/bcm2836.c | 24 +++++++++++++++---------
 hw/arm/raspi.c   |  2 --
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 
 struct BCM283XInfo {
     const char *name;
+    const char *cpu_type;
     int clusterid;
 };
 
 static const BCM283XInfo bcm283x_socs[] = {
     {
         .name = TYPE_BCM2836,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"),
         .clusterid = 0xf,
     },
+#ifdef TARGET_AARCH64
     {
         .name = TYPE_BCM2837,
+        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
         .clusterid = 0x0,
     },
+#endif
 };
 
 static void bcm2836_init(Object *obj)
 {
     BCM283XState *s = BCM283X(obj);
+    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
+    const BCM283XInfo *info = bc->info;
+    int n;
+
+    for (n = 0; n < BCM283X_NCPUS; n++) {
+        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+                          info->cpu_type);
+        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+                                  &error_abort);
+    }
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 
     /* common peripherals from bcm2835 */
 
-    obj = OBJECT(dev);
-    for (n = 0; n < BCM283X_NCPUS; n++) {
-        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
-                          s->cpu_type);
-        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
-                                  &error_abort);
-    }
-
     obj = object_property_get_link(OBJECT(dev), "ram", &err);
     if (obj == NULL) {
         error_setg(errp, "%s: required ram link not found: %s",
@@ -XXX,XX +XXX,XX @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
-    DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type),
     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
                        BCM283X_NCPUS),
     DEFINE_PROP_END_OF_LIST()
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
     /* Setup the SOC */
     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                    &error_abort);
-    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
-                            &error_abort);
     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                             &error_abort);
     int board_rev = version == 3 ? 0xa02082 : 0xa21041;
-- 
2.16.2

The raspi3 has AArch64 CPUs, which means that our smpboot
code for keeping the secondary CPUs in a pen needs to have
a version for A64 as well as A32. Without this, the
secondary CPUs go into an infinite loop of taking undefined
instruction exceptions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180313153458.26822-10-peter.maydell@linaro.org
---
 hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
+#define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
 
 /* Table of Linux board IDs for different Pi versions */
 static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};
@@ -XXX,XX +XXX,XX @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
                        info->smp_loader_start);
 }
 
+static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
+{
+    /* Unlike the AArch32 version we don't need to call the board setup hook.
+     * The mechanism for doing the spin-table is also entirely different.
+     * We must have four 64-bit fields at absolute addresses
+     * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
+     * our CPUs, and which we must ensure are zero initialized before
+     * the primary CPU goes into the kernel. We put these variables inside
+     * a rom blob, so that the reset for ROM contents zeroes them for us.
+     */
+    static const uint32_t smpboot[] = {
+        0xd2801b05, /*        mov     x5, 0xd8 */
+        0xd53800a6, /*        mrs     x6, mpidr_el1 */
+        0x924004c6, /*        and     x6, x6, #0x3 */
+        0xd503205f, /* spin:  wfe */
+        0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
+        0xb4ffffc4, /*        cbz     x4, spin */
+        0xd2800000, /*        mov     x0, #0x0 */
+        0xd2800001, /*        mov     x1, #0x0 */
+        0xd2800002, /*        mov     x2, #0x0 */
+        0xd2800003, /*        mov     x3, #0x0 */
+        0xd61f0080, /*        br      x4 */
+    };
+
+    static const uint64_t spintables[] = {
+        0, 0, 0, 0
+    };
+
+    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),
+                       info->smp_loader_start);
+    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),
+                       SPINTABLE_ADDR);
+}
+
 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
 {
     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
         binfo.smp_loader_start = SMPBOOT_ADDR;
-        binfo.write_secondary_boot = write_smpboot;
+        if (version == 2) {
+            binfo.write_secondary_boot = write_smpboot;
+        } else {
+            binfo.write_secondary_boot = write_smpboot64;
+        }
         binfo.secondary_cpu_reset_hook = reset_secondary;
     }
 
-- 
2.16.2