1 | Target-arm queue... | 1 | Nothing too exciting, but does include the last bits of v8.1M support work. |
---|---|---|---|
2 | 2 | ||
3 | thanks | ||
4 | -- PMM | 3 | -- PMM |
5 | 4 | ||
6 | The following changes since commit 735286a4f88255e1463d42ce28d8d14181fd32d4: | 5 | The following changes since commit e79de63ab1bd1f6550e7b915e433bec1ad1a870a: |
7 | 6 | ||
8 | Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170613' into staging (2017-06-13 13:51:29 +0100) | 7 | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210107' into staging (2021-01-07 20:34:05 +0000) |
9 | 8 | ||
10 | are available in the git repository at: | 9 | are available in the Git repository at: |
11 | 10 | ||
12 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170613 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210108 |
13 | 12 | ||
14 | for you to fetch changes up to 252a7a6a968c279a4636a86b0559ba3a930a90b5: | 13 | for you to fetch changes up to c9f8511ea8d2b80723af0fea1f716d752c1b5208: |
15 | 14 | ||
16 | hw/intc/arm_gicv3_its: Allow save/restore (2017-06-13 14:57:01 +0100) | 15 | docs/system: arm: Add sabrelite board description (2021-01-08 15:13:39 +0000) |
17 | 16 | ||
18 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
19 | target-arm queue: | 18 | target-arm queue: |
20 | * vITS: Support save/restore | 19 | * intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs |
21 | * timer/aspeed: Fix timer enablement when reload is not set | 20 | * target/arm: Fix MTE0_ACTIVE |
22 | * aspped: add temperature sensor device | 21 | * target/arm: Implement v8.1M and Cortex-M55 model |
23 | * timer.h: Provide better monotonic time on ARM hosts | 22 | * hw/arm/highbank: Drop dead KVM support code |
24 | * exynos4210: various cleanups | 23 | * util/qemu-timer: Make timer_free() imply timer_del() |
25 | * exynos4210: support system poweroff | 24 | * various devices: Use ptimer_free() in finalize function |
25 | * docs/system: arm: Add sabrelite board description | ||
26 | * sabrelite: Minor fixes to allow booting U-Boot | ||
26 | 27 | ||
27 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
28 | Cédric Le Goater (3): | 29 | Andrew Jones (1): |
29 | hw/misc: add a TMP42{1, 2, 3} device model | 30 | hw/arm/virt: Remove virt machine state 'smp_cpus' |
30 | aspeed: add a temp sensor device on I2C bus 3 | ||
31 | timer/aspeed: fix timer enablement when a reload is not set | ||
32 | 31 | ||
33 | Eric Auger (4): | 32 | Bin Meng (4): |
34 | kvm-all: Pass an error object to kvm_device_access | 33 | hw/misc: imx6_ccm: Update PMU_MISC0 reset value |
35 | hw/intc/arm_gicv3_its: Implement state save/restore | 34 | hw/msic: imx6_ccm: Correct register value for silicon type |
36 | hw/intc/arm_gicv3_kvm: Implement pending table save | 35 | hw/arm: sabrelite: Connect the Ethernet PHY at address 6 |
37 | hw/intc/arm_gicv3_its: Allow save/restore | 36 | docs/system: arm: Add sabrelite board description |
38 | 37 | ||
39 | Krzysztof Kozlowski (9): | 38 | Edgar E. Iglesias (1): |
40 | hw/intc/exynos4210_gic: Use more meaningful name for local variable | 39 | intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs |
41 | hw/timer/exynos4210_mct: Fix checkpatch style errors | ||
42 | hw/timer/exynos4210_mct: Cleanup indentation and empty new lines | ||
43 | hw/timer/exynos4210_mct: Remove unused defines | ||
44 | hw/arm/exynos: Move DRAM initialization next boards | ||
45 | hw/arm/exynos: Declare local variables in some order | ||
46 | hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string | ||
47 | hw/intc/exynos4210_gic: Constify array of combiner interrupts | ||
48 | hw/misc/exynos4210_pmu: Add support for system poweroff | ||
49 | 40 | ||
50 | Pranith Kumar (1): | 41 | Gan Qixin (7): |
51 | timer.h: Provide better monotonic time | 42 | digic-timer: Use ptimer_free() in the finalize function to avoid memleaks |
43 | allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks | ||
44 | exynos4210_rtc: Use ptimer_free() in the finalize function to avoid memleaks | ||
45 | exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks | ||
46 | mss-timer: Use ptimer_free() in the finalize function to avoid memleaks | ||
47 | musicpal: Use ptimer_free() in the finalize function to avoid memleaks | ||
48 | exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks | ||
52 | 49 | ||
53 | hw/misc/Makefile.objs | 1 + | 50 | Peter Maydell (9): |
54 | include/hw/arm/exynos4210.h | 5 +- | 51 | hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN |
55 | include/hw/intc/arm_gicv3_its_common.h | 8 + | 52 | target/arm: Correct store of FPSCR value via FPCXT_S |
56 | include/migration/vmstate.h | 2 + | 53 | target/arm: Implement FPCXT_NS fp system register |
57 | include/qemu/timer.h | 5 +- | 54 | target/arm: Implement Cortex-M55 model |
58 | include/sysemu/kvm.h | 11 +- | 55 | hw/arm/highbank: Drop dead KVM support code |
59 | hw/arm/aspeed.c | 9 + | 56 | util/qemu-timer: Make timer_free() imply timer_del() |
60 | hw/arm/exynos4210.c | 27 +-- | 57 | scripts/coccinelle: New script to remove unnecessary timer_del() calls |
61 | hw/arm/exynos4_boards.c | 50 +++- | 58 | Remove superfluous timer_del() calls |
62 | hw/intc/arm_gic_kvm.c | 9 +- | 59 | target/arm: Remove timer_del()/timer_deinit() before timer_free() |
63 | hw/intc/arm_gicv3_common.c | 1 + | ||
64 | hw/intc/arm_gicv3_its_common.c | 12 +- | ||
65 | hw/intc/arm_gicv3_its_kvm.c | 131 +++++++++-- | ||
66 | hw/intc/arm_gicv3_kvm.c | 48 +++- | ||
67 | hw/intc/exynos4210_gic.c | 14 +- | ||
68 | hw/misc/exynos4210_pmu.c | 20 +- | ||
69 | hw/misc/tmp421.c | 402 +++++++++++++++++++++++++++++++++ | ||
70 | hw/timer/aspeed_timer.c | 37 ++- | ||
71 | hw/timer/exynos4210_mct.c | 50 ++-- | ||
72 | kvm-all.c | 14 +- | ||
73 | default-configs/arm-softmmu.mak | 1 + | ||
74 | 21 files changed, 741 insertions(+), 116 deletions(-) | ||
75 | create mode 100644 hw/misc/tmp421.c | ||
76 | 60 | ||
61 | Richard Henderson (1): | ||
62 | target/arm: Fix MTE0_ACTIVE | ||
63 | |||
64 | docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++ | ||
65 | docs/system/target-arm.rst | 1 + | ||
66 | scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++ | ||
67 | include/hw/arm/virt.h | 3 +- | ||
68 | include/qemu/timer.h | 24 +++--- | ||
69 | block/iscsi.c | 2 - | ||
70 | block/nbd.c | 1 - | ||
71 | block/qcow2.c | 1 - | ||
72 | hw/arm/highbank.c | 14 +-- | ||
73 | hw/arm/musicpal.c | 12 +++ | ||
74 | hw/arm/sabrelite.c | 4 + | ||
75 | hw/arm/virt-acpi-build.c | 9 +- | ||
76 | hw/arm/virt.c | 21 +++-- | ||
77 | hw/block/nvme.c | 2 - | ||
78 | hw/char/serial.c | 2 - | ||
79 | hw/char/virtio-serial-bus.c | 2 - | ||
80 | hw/ide/core.c | 1 - | ||
81 | hw/input/hid.c | 1 - | ||
82 | hw/intc/apic.c | 1 - | ||
83 | hw/intc/arm_gic.c | 4 +- | ||
84 | hw/intc/armv7m_nvic.c | 15 ++++ | ||
85 | hw/intc/ioapic.c | 1 - | ||
86 | hw/ipmi/ipmi_bmc_extern.c | 1 - | ||
87 | hw/misc/imx6_ccm.c | 4 +- | ||
88 | hw/net/e1000.c | 3 - | ||
89 | hw/net/e1000e_core.c | 8 -- | ||
90 | hw/net/pcnet-pci.c | 1 - | ||
91 | hw/net/rtl8139.c | 1 - | ||
92 | hw/net/spapr_llan.c | 1 - | ||
93 | hw/net/virtio-net.c | 2 - | ||
94 | hw/rtc/exynos4210_rtc.c | 9 ++ | ||
95 | hw/s390x/s390-pci-inst.c | 1 - | ||
96 | hw/sd/sd.c | 1 - | ||
97 | hw/sd/sdhci.c | 2 - | ||
98 | hw/timer/allwinner-a10-pit.c | 11 +++ | ||
99 | hw/timer/digic-timer.c | 8 ++ | ||
100 | hw/timer/exynos4210_mct.c | 14 +++ | ||
101 | hw/timer/exynos4210_pwm.c | 11 +++ | ||
102 | hw/timer/mss-timer.c | 13 +++ | ||
103 | hw/usb/dev-hub.c | 1 - | ||
104 | hw/usb/hcd-ehci.c | 1 - | ||
105 | hw/usb/hcd-ohci-pci.c | 1 - | ||
106 | hw/usb/hcd-uhci.c | 1 - | ||
107 | hw/usb/hcd-xhci.c | 1 - | ||
108 | hw/usb/redirect.c | 1 - | ||
109 | hw/vfio/display.c | 1 - | ||
110 | hw/virtio/vhost-vsock-common.c | 1 - | ||
111 | hw/virtio/virtio-balloon.c | 1 - | ||
112 | hw/virtio/virtio-rng.c | 1 - | ||
113 | hw/watchdog/wdt_diag288.c | 1 - | ||
114 | hw/watchdog/wdt_i6300esb.c | 1 - | ||
115 | migration/colo.c | 1 - | ||
116 | monitor/hmp-cmds.c | 1 - | ||
117 | net/announce.c | 1 - | ||
118 | net/colo-compare.c | 1 - | ||
119 | net/slirp.c | 1 - | ||
120 | replay/replay-debugging.c | 1 - | ||
121 | target/arm/cpu.c | 2 - | ||
122 | target/arm/cpu_tcg.c | 42 +++++++++ | ||
123 | target/arm/helper.c | 2 +- | ||
124 | target/s390x/cpu.c | 2 - | ||
125 | ui/console.c | 1 - | ||
126 | ui/spice-core.c | 1 - | ||
127 | util/throttle.c | 1 - | ||
128 | target/arm/translate-vfp.c.inc | 114 ++++++++++++++++++++++-- | ||
129 | 65 files changed, 421 insertions(+), 111 deletions(-) | ||
130 | create mode 100644 docs/system/arm/sabrelite.rst | ||
131 | create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci | ||
132 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
1 | 2 | ||
3 | Correct the indexing into s->cpu_ctlr for vCPUs. | ||
4 | |||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
8 | Message-id: 20201214222154.3480243-2-edgar.iglesias@gmail.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/intc/arm_gic.c | 4 +++- | ||
12 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/intc/arm_gic.c | ||
17 | +++ b/hw/intc/arm_gic.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static inline void gic_get_best_virq(GICState *s, int cpu, | ||
19 | static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt, | ||
20 | int group_mask) | ||
21 | { | ||
22 | + int cpu_iface = virt ? (cpu + GIC_NCPU) : cpu; | ||
23 | + | ||
24 | if (!virt && !(s->ctlr & group_mask)) { | ||
25 | return false; | ||
26 | } | ||
27 | @@ -XXX,XX +XXX,XX @@ static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt, | ||
28 | return false; | ||
29 | } | ||
30 | |||
31 | - if (!(s->cpu_ctlr[cpu] & group_mask)) { | ||
32 | + if (!(s->cpu_ctlr[cpu_iface] & group_mask)) { | ||
33 | return false; | ||
34 | } | ||
35 | |||
36 | -- | ||
37 | 2.20.1 | ||
38 | |||
39 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Use a define for a9mpcore_priv device type name instead of hard-coded | 3 | virt machine's 'smp_cpus' and machine->smp.cpus must always have the |
4 | string. | 4 | same value. And, anywhere we have virt machine state we have machine |
5 | state. So let's remove the redundancy. Also, to make it easier to see | ||
6 | that machine->smp is the true source for "smp_cpus" and "max_cpus", | ||
7 | avoid passing them in function parameters, preferring instead to get | ||
8 | them from the state. | ||
5 | 9 | ||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 10 | No functional change intended. |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | |
12 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
13 | Reviewed-by: David Edmondson <david.edmondson@oracle.com> | ||
14 | Reviewed-by: Ying Fang <fangying1@huawei.com> | ||
15 | Message-id: 20201215174815.51520-1-drjones@redhat.com | ||
16 | [PMM: minor formatting tweak to smp_cpus variable declaration] | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 18 | --- |
10 | hw/arm/exynos4210.c | 3 ++- | 19 | include/hw/arm/virt.h | 3 +-- |
11 | 1 file changed, 2 insertions(+), 1 deletion(-) | 20 | hw/arm/virt-acpi-build.c | 9 +++++---- |
21 | hw/arm/virt.c | 21 ++++++++++----------- | ||
22 | 3 files changed, 16 insertions(+), 17 deletions(-) | ||
12 | 23 | ||
13 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 24 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h |
14 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/exynos4210.c | 26 | --- a/include/hw/arm/virt.h |
16 | +++ b/hw/arm/exynos4210.c | 27 | +++ b/include/hw/arm/virt.h |
28 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineState { | ||
29 | MemMapEntry *memmap; | ||
30 | char *pciehb_nodename; | ||
31 | const int *irqmap; | ||
32 | - int smp_cpus; | ||
33 | void *fdt; | ||
34 | int fdt_size; | ||
35 | uint32_t clock_phandle; | ||
36 | @@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) | ||
37 | |||
38 | assert(vms->gic_version == VIRT_GIC_VERSION_3); | ||
39 | |||
40 | - return vms->smp_cpus > redist0_capacity ? 2 : 1; | ||
41 | + return MACHINE(vms)->smp.cpus > redist0_capacity ? 2 : 1; | ||
42 | } | ||
43 | |||
44 | #endif /* QEMU_ARM_VIRT_H */ | ||
45 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/hw/arm/virt-acpi-build.c | ||
48 | +++ b/hw/arm/virt-acpi-build.c | ||
17 | @@ -XXX,XX +XXX,XX @@ | 49 | @@ -XXX,XX +XXX,XX @@ |
18 | #include "qemu-common.h" | 50 | |
19 | #include "qemu/log.h" | 51 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
20 | #include "cpu.h" | 52 | |
21 | +#include "hw/cpu/a9mpcore.h" | 53 | -static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) |
22 | #include "hw/boards.h" | 54 | +static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) |
23 | #include "sysemu/sysemu.h" | 55 | { |
24 | #include "hw/sysbus.h" | 56 | + MachineState *ms = MACHINE(vms); |
25 | @@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | 57 | uint16_t i; |
58 | |||
59 | - for (i = 0; i < smp_cpus; i++) { | ||
60 | + for (i = 0; i < ms->smp.cpus; i++) { | ||
61 | Aml *dev = aml_device("C%.03X", i); | ||
62 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); | ||
63 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | ||
64 | @@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
65 | gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); | ||
66 | gicd->version = vms->gic_version; | ||
67 | |||
68 | - for (i = 0; i < vms->smp_cpus; i++) { | ||
69 | + for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { | ||
70 | AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, | ||
71 | sizeof(*gicc)); | ||
72 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); | ||
73 | @@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
74 | * the RTC ACPI device at all when using UEFI. | ||
75 | */ | ||
76 | scope = aml_scope("\\_SB"); | ||
77 | - acpi_dsdt_add_cpus(scope, vms->smp_cpus); | ||
78 | + acpi_dsdt_add_cpus(scope, vms); | ||
79 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], | ||
80 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | ||
81 | if (vmc->acpi_expose_flash) { | ||
82 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | --- a/hw/arm/virt.c | ||
85 | +++ b/hw/arm/virt.c | ||
86 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) | ||
87 | if (vms->gic_version == VIRT_GIC_VERSION_2) { | ||
88 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | ||
89 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | ||
90 | - (1 << vms->smp_cpus) - 1); | ||
91 | + (1 << MACHINE(vms)->smp.cpus) - 1); | ||
26 | } | 92 | } |
27 | 93 | ||
28 | /* Private memory region and Internal GIC */ | 94 | qemu_fdt_add_subnode(vms->fdt, "/timer"); |
29 | - dev = qdev_create(NULL, "a9mpcore_priv"); | 95 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) |
30 | + dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); | 96 | int cpu; |
31 | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | 97 | int addr_cells = 1; |
32 | qdev_init_nofail(dev); | 98 | const MachineState *ms = MACHINE(vms); |
33 | busdev = SYS_BUS_DEVICE(dev); | 99 | + int smp_cpus = ms->smp.cpus; |
100 | |||
101 | /* | ||
102 | * From Documentation/devicetree/bindings/arm/cpus.txt | ||
103 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
104 | * The simplest way to go is to examine affinity IDs of all our CPUs. If | ||
105 | * at least one of them has Aff3 populated, we set #address-cells to 2. | ||
106 | */ | ||
107 | - for (cpu = 0; cpu < vms->smp_cpus; cpu++) { | ||
108 | + for (cpu = 0; cpu < smp_cpus; cpu++) { | ||
109 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | ||
110 | |||
111 | if (armcpu->mp_affinity & ARM_AFF3_MASK) { | ||
112 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
113 | qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); | ||
114 | qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); | ||
115 | |||
116 | - for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { | ||
117 | + for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { | ||
118 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | ||
119 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | ||
120 | CPUState *cs = CPU(armcpu); | ||
121 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
122 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", | ||
123 | armcpu->dtb_compatible); | ||
124 | |||
125 | - if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED | ||
126 | - && vms->smp_cpus > 1) { | ||
127 | + if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { | ||
128 | qemu_fdt_setprop_string(vms->fdt, nodename, | ||
129 | "enable-method", "psci"); | ||
130 | } | ||
131 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) | ||
132 | if (vms->gic_version == VIRT_GIC_VERSION_2) { | ||
133 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | ||
134 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | ||
135 | - (1 << vms->smp_cpus) - 1); | ||
136 | + (1 << MACHINE(vms)->smp.cpus) - 1); | ||
137 | } | ||
138 | |||
139 | qemu_fdt_add_subnode(vms->fdt, "/pmu"); | ||
140 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) | ||
141 | * virt_cpu_post_init() must be called after the CPUs have | ||
142 | * been realized and the GIC has been created. | ||
143 | */ | ||
144 | -static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus, | ||
145 | - MemoryRegion *sysmem) | ||
146 | +static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) | ||
147 | { | ||
148 | + int max_cpus = MACHINE(vms)->smp.max_cpus; | ||
149 | bool aarch64, pmu, steal_time; | ||
150 | CPUState *cpu; | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
153 | exit(1); | ||
154 | } | ||
155 | |||
156 | - vms->smp_cpus = smp_cpus; | ||
157 | - | ||
158 | if (vms->virt && kvm_enabled()) { | ||
159 | error_report("mach-virt: KVM does not support providing " | ||
160 | "Virtualization extensions to the guest CPU"); | ||
161 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
162 | create_fdt(vms); | ||
163 | |||
164 | possible_cpus = mc->possible_cpu_arch_ids(machine); | ||
165 | + assert(possible_cpus->len == max_cpus); | ||
166 | for (n = 0; n < possible_cpus->len; n++) { | ||
167 | Object *cpuobj; | ||
168 | CPUState *cs; | ||
169 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
170 | |||
171 | create_gic(vms); | ||
172 | |||
173 | - virt_cpu_post_init(vms, possible_cpus->len, sysmem); | ||
174 | + virt_cpu_post_init(vms, sysmem); | ||
175 | |||
176 | fdt_add_pmu_nodes(vms); | ||
177 | |||
34 | -- | 178 | -- |
35 | 2.7.4 | 179 | 2.20.1 |
36 | 180 | ||
37 | 181 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We change the restoration priority of both the GICv3 and ITS. The | 3 | In 50244cc76abc we updated mte_check_fail to match the ARM |
4 | GICv3 must be restored before the ITS and the ITS needs to be restored | 4 | pseudocode, using the correct EL to select the TCF field. |
5 | before PCIe devices since it translates their MSI transactions. | 5 | But we failed to update MTE0_ACTIVE the same way, which led |
6 | to g_assert_not_reached(). | ||
6 | 7 | ||
7 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 8 | Cc: qemu-stable@nongnu.org |
8 | Reviewed-by: Juan Quintela <quintela@redhat.com> | 9 | Buglink: https://bugs.launchpad.net/bugs/1907137 |
9 | Message-id: 1497023553-18411-5-git-send-email-eric.auger@redhat.com | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20201221204426.88514-1-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 14 | --- |
12 | include/migration/vmstate.h | 2 ++ | 15 | target/arm/helper.c | 2 +- |
13 | hw/intc/arm_gicv3_common.c | 1 + | 16 | 1 file changed, 1 insertion(+), 1 deletion(-) |
14 | hw/intc/arm_gicv3_its_common.c | 2 +- | ||
15 | hw/intc/arm_gicv3_its_kvm.c | 24 ++++++++++++------------ | ||
16 | 4 files changed, 16 insertions(+), 13 deletions(-) | ||
17 | 17 | ||
18 | diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h | 18 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
19 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/migration/vmstate.h | 20 | --- a/target/arm/helper.c |
21 | +++ b/include/migration/vmstate.h | 21 | +++ b/target/arm/helper.c |
22 | @@ -XXX,XX +XXX,XX @@ enum VMStateFlags { | 22 | @@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
23 | typedef enum { | 23 | if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) |
24 | MIG_PRI_DEFAULT = 0, | 24 | && tbid |
25 | MIG_PRI_IOMMU, /* Must happen before PCI devices */ | 25 | && !(env->pstate & PSTATE_TCO) |
26 | + MIG_PRI_GICV3_ITS, /* Must happen before PCI devices */ | 26 | - && (sctlr & SCTLR_TCF0) |
27 | + MIG_PRI_GICV3, /* Must happen before the ITS */ | 27 | + && (sctlr & SCTLR_TCF) |
28 | MIG_PRI_MAX, | 28 | && allocation_tag_access_enabled(env, 0, sctlr)) { |
29 | } MigrationPriority; | 29 | flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); |
30 | 30 | } | |
31 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/intc/arm_gicv3_common.c | ||
34 | +++ b/hw/intc/arm_gicv3_common.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = { | ||
36 | .minimum_version_id = 1, | ||
37 | .pre_save = gicv3_pre_save, | ||
38 | .post_load = gicv3_post_load, | ||
39 | + .priority = MIG_PRI_GICV3, | ||
40 | .fields = (VMStateField[]) { | ||
41 | VMSTATE_UINT32(gicd_ctlr, GICv3State), | ||
42 | VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), | ||
43 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/intc/arm_gicv3_its_common.c | ||
46 | +++ b/hw/intc/arm_gicv3_its_common.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = { | ||
48 | .name = "arm_gicv3_its", | ||
49 | .pre_save = gicv3_its_pre_save, | ||
50 | .post_load = gicv3_its_post_load, | ||
51 | - .unmigratable = true, | ||
52 | + .priority = MIG_PRI_GICV3_ITS, | ||
53 | .fields = (VMStateField[]) { | ||
54 | VMSTATE_UINT32(ctlr, GICv3ITSState), | ||
55 | VMSTATE_UINT32(iidr, GICv3ITSState), | ||
56 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
59 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
61 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | ||
62 | Error *local_err = NULL; | ||
63 | |||
64 | - /* | ||
65 | - * Block migration of a KVM GICv3 ITS device: the API for saving and | ||
66 | - * restoring the state in the kernel is not yet available | ||
67 | - */ | ||
68 | - error_setg(&s->migration_blocker, "vITS migration is not implemented"); | ||
69 | - migrate_add_blocker(s->migration_blocker, &local_err); | ||
70 | - if (local_err) { | ||
71 | - error_propagate(errp, local_err); | ||
72 | - error_free(s->migration_blocker); | ||
73 | - return; | ||
74 | - } | ||
75 | - | ||
76 | s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false); | ||
77 | if (s->dev_fd < 0) { | ||
78 | error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS"); | ||
79 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
80 | |||
81 | gicv3_its_init_mmio(s, NULL); | ||
82 | |||
83 | + if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
84 | + GITS_CTLR)) { | ||
85 | + error_setg(&s->migration_blocker, "This operating system kernel " | ||
86 | + "does not support vITS migration"); | ||
87 | + migrate_add_blocker(s->migration_blocker, &local_err); | ||
88 | + if (local_err) { | ||
89 | + error_propagate(errp, local_err); | ||
90 | + error_free(s->migration_blocker); | ||
91 | + return; | ||
92 | + } | ||
93 | + } | ||
94 | + | ||
95 | kvm_msi_use_devid = true; | ||
96 | kvm_gsi_direct_mapping = false; | ||
97 | kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); | ||
98 | -- | 31 | -- |
99 | 2.7.4 | 32 | 2.20.1 |
100 | 33 | ||
101 | 34 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The CCR is a register most of whose bits are banked between security | ||
2 | states but where BFHFNMIGN is not, and we keep it in the non-secure | ||
3 | entry of the v7m.ccr[] array. The logic which tries to handle this | ||
4 | bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS | ||
5 | is zero" requirement; correct the omission. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20201210201433.26262-2-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/intc/armv7m_nvic.c | 15 +++++++++++++++ | ||
12 | 1 file changed, 15 insertions(+) | ||
13 | |||
14 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/intc/armv7m_nvic.c | ||
17 | +++ b/hw/intc/armv7m_nvic.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
19 | */ | ||
20 | val = cpu->env.v7m.ccr[attrs.secure]; | ||
21 | val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; | ||
22 | + /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */ | ||
23 | + if (!attrs.secure) { | ||
24 | + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | ||
25 | + val &= ~R_V7M_CCR_BFHFNMIGN_MASK; | ||
26 | + } | ||
27 | + } | ||
28 | return val; | ||
29 | case 0xd24: /* System Handler Control and State (SHCSR) */ | ||
30 | if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { | ||
31 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
32 | (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) | ||
33 | | (value & R_V7M_CCR_BFHFNMIGN_MASK); | ||
34 | value &= ~R_V7M_CCR_BFHFNMIGN_MASK; | ||
35 | + } else { | ||
36 | + /* | ||
37 | + * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so | ||
38 | + * preserve the state currently in the NS element of the array | ||
39 | + */ | ||
40 | + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | ||
41 | + value &= ~R_V7M_CCR_BFHFNMIGN_MASK; | ||
42 | + value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; | ||
43 | + } | ||
44 | } | ||
45 | |||
46 | cpu->env.v7m.ccr[attrs.secure] = value; | ||
47 | -- | ||
48 | 2.20.1 | ||
49 | |||
50 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register, |
---|---|---|---|
2 | but we got the write behaviour wrong. On read, this register reads | ||
3 | bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't | ||
4 | just write back those bits -- it writes a value to the whole FPSCR, | ||
5 | whose upper 4 bits are zeroes. | ||
2 | 6 | ||
3 | There are to SysBusDevice variables in exynos4210_gic_realize() | 7 | We also incorrectly implemented the write-to-FPSCR as a simple store |
4 | function: one for the device itself and second for arm_gic device. Add | 8 | to vfp.xregs; this skips the "update the softfloat flags" part of |
5 | a prefix "gic" to the second one so it will be easier to understand the | 9 | the vfp_set_fpscr helper so the value would read back correctly but |
6 | code. | 10 | not actually take effect. |
7 | 11 | ||
8 | While at it, put local uninitialized 'i' variable at the end, next to | 12 | Fix both of these things by doing a complete write to the FPSCR |
9 | other uninitialized ones. | 13 | using the helper function. |
10 | 14 | ||
11 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20201210201433.26262-3-peter.maydell@linaro.org | ||
15 | --- | 18 | --- |
16 | hw/intc/exynos4210_gic.c | 12 ++++++------ | 19 | target/arm/translate-vfp.c.inc | 12 ++++++------ |
17 | 1 file changed, 6 insertions(+), 6 deletions(-) | 20 | 1 file changed, 6 insertions(+), 6 deletions(-) |
18 | 21 | ||
19 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 22 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc |
20 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/intc/exynos4210_gic.c | 24 | --- a/target/arm/translate-vfp.c.inc |
22 | +++ b/hw/intc/exynos4210_gic.c | 25 | +++ b/target/arm/translate-vfp.c.inc |
23 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | 26 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, |
24 | DeviceState *dev = DEVICE(obj); | 27 | } |
25 | Exynos4210GicState *s = EXYNOS4210_GIC(obj); | 28 | case ARM_VFP_FPCXT_S: |
26 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 29 | { |
27 | - uint32_t i; | 30 | - TCGv_i32 sfpa, control, fpscr; |
28 | const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; | 31 | - /* Set FPSCR[27:0] and CONTROL.SFPA from value */ |
29 | const char dist_prefix[] = "exynos4210-gic-alias_dist"; | 32 | + TCGv_i32 sfpa, control; |
30 | char cpu_alias_name[sizeof(cpu_prefix) + 3]; | 33 | + /* |
31 | char dist_alias_name[sizeof(cpu_prefix) + 3]; | 34 | + * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes |
32 | - SysBusDevice *busdev; | 35 | + * bits [27:0] from value and zeroes bits [31:28]. |
33 | + SysBusDevice *gicbusdev; | 36 | + */ |
34 | + uint32_t i; | 37 | tmp = loadfn(s, opaque); |
35 | 38 | sfpa = tcg_temp_new_i32(); | |
36 | s->gic = qdev_create(NULL, "arm_gic"); | 39 | tcg_gen_shri_i32(sfpa, tmp, 31); |
37 | qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); | 40 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, |
38 | qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); | 41 | tcg_gen_deposit_i32(control, control, sfpa, |
39 | qdev_init_nofail(s->gic); | 42 | R_V7M_CONTROL_SFPA_SHIFT, 1); |
40 | - busdev = SYS_BUS_DEVICE(s->gic); | 43 | store_cpu_field(control, v7m.control[M_REG_S]); |
41 | + gicbusdev = SYS_BUS_DEVICE(s->gic); | 44 | - fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); |
42 | 45 | - tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK); | |
43 | /* Pass through outbound IRQ lines from the GIC */ | 46 | tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); |
44 | - sysbus_pass_irq(sbd, busdev); | 47 | - tcg_gen_or_i32(fpscr, fpscr, tmp); |
45 | + sysbus_pass_irq(sbd, gicbusdev); | 48 | - store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); |
46 | 49 | + gen_helper_vfp_set_fpscr(cpu_env, tmp); | |
47 | /* Pass through inbound GPIO lines to the GIC */ | 50 | tcg_temp_free_i32(tmp); |
48 | qdev_init_gpio_in(dev, exynos4210_gic_set_irq, | 51 | tcg_temp_free_i32(sfpa); |
49 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | 52 | break; |
50 | sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); | ||
51 | memory_region_init_alias(&s->cpu_alias[i], obj, | ||
52 | cpu_alias_name, | ||
53 | - sysbus_mmio_get_region(busdev, 1), | ||
54 | + sysbus_mmio_get_region(gicbusdev, 1), | ||
55 | 0, | ||
56 | EXYNOS4210_GIC_CPU_REGION_SIZE); | ||
57 | memory_region_add_subregion(&s->cpu_container, | ||
58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | ||
59 | sprintf(dist_alias_name, "%s%x", dist_prefix, i); | ||
60 | memory_region_init_alias(&s->dist_alias[i], obj, | ||
61 | dist_alias_name, | ||
62 | - sysbus_mmio_get_region(busdev, 0), | ||
63 | + sysbus_mmio_get_region(gicbusdev, 0), | ||
64 | 0, | ||
65 | EXYNOS4210_GIC_DIST_REGION_SIZE); | ||
66 | memory_region_add_subregion(&s->dist_container, | ||
67 | -- | 53 | -- |
68 | 2.7.4 | 54 | 2.20.1 |
69 | 55 | ||
70 | 56 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Implement the v8.1M FPCXT_NS floating-point system register. This is |
---|---|---|---|
2 | a little more complicated than FPCXT_S, because it has specific | ||
3 | handling for "current FP state is inactive", and it only wants to do | ||
4 | PreserveFPState(), not the full set of actions done by | ||
5 | ExecuteFPCheck() which vfp_access_check() implements. | ||
2 | 6 | ||
3 | In some circumstances, we don't want to abort if the | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | kvm_device_access fails. This will be the case during ITS | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | migration, in case the ITS table save/restore fails because | 9 | Message-id: 20201210201433.26262-4-peter.maydell@linaro.org |
6 | the guest did not program the vITS correctly. So let's pass an | 10 | --- |
7 | error object to the function and return the ioctl value. New | 11 | target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++- |
8 | callers will be able to make a decision upon this returned | 12 | 1 file changed, 99 insertions(+), 3 deletions(-) |
9 | value. | ||
10 | 13 | ||
11 | Existing callers pass &error_abort which will cause the | 14 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc |
12 | function to abort on failure. | ||
13 | |||
14 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
15 | Reviewed-by: Juan Quintela <quintela@redhat.com> | ||
16 | Reviewed-by: Peter Xu <peterx@redhat.com> | ||
17 | Message-id: 1497023553-18411-2-git-send-email-eric.auger@redhat.com | ||
18 | [PMM: wrapped long line] | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | --- | ||
21 | include/sysemu/kvm.h | 11 +++++++---- | ||
22 | hw/intc/arm_gic_kvm.c | 9 +++++---- | ||
23 | hw/intc/arm_gicv3_its_kvm.c | 2 +- | ||
24 | hw/intc/arm_gicv3_kvm.c | 14 +++++++------- | ||
25 | kvm-all.c | 14 ++++++++------ | ||
26 | 5 files changed, 28 insertions(+), 22 deletions(-) | ||
27 | |||
28 | diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/include/sysemu/kvm.h | 16 | --- a/target/arm/translate-vfp.c.inc |
31 | +++ b/include/sysemu/kvm.h | 17 | +++ b/target/arm/translate-vfp.c.inc |
32 | @@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int fd, uint32_t group, uint64_t attr); | 18 | @@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) |
33 | * @attr: the attribute of that group to set or get | 19 | } |
34 | * @val: pointer to a storage area for the value | 20 | break; |
35 | * @write: true for set and false for get operation | 21 | case ARM_VFP_FPCXT_S: |
36 | + * @errp: error object handle | 22 | + case ARM_VFP_FPCXT_NS: |
37 | * | 23 | if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
38 | - * This function is not allowed to fail. Use kvm_device_check_attr() | 24 | return false; |
39 | - * in order to check for the availability of optional attributes. | 25 | } |
40 | + * Returns: 0 on success | 26 | @@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) |
41 | + * < 0 on error | 27 | return FPSysRegCheckFailed; |
42 | + * Use kvm_device_check_attr() in order to check for the availability | 28 | } |
43 | + * of optional attributes. | 29 | |
44 | */ | 30 | - if (!vfp_access_check(s)) { |
45 | -void kvm_device_access(int fd, int group, uint64_t attr, | 31 | + /* |
46 | - void *val, bool write); | 32 | + * FPCXT_NS is a special case: it has specific handling for |
47 | +int kvm_device_access(int fd, int group, uint64_t attr, | 33 | + * "current FP state is inactive", and must do the PreserveFPState() |
48 | + void *val, bool write, Error **errp); | 34 | + * but not the usual full set of actions done by ExecuteFPCheck(). |
49 | 35 | + * So we don't call vfp_access_check() and the callers must handle this. | |
50 | /** | 36 | + */ |
51 | * kvm_create_device - create a KVM device for the device control API | 37 | + if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) { |
52 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c | 38 | return FPSysRegCheckDone; |
53 | index XXXXXXX..XXXXXXX 100644 | 39 | } |
54 | --- a/hw/intc/arm_gic_kvm.c | 40 | - |
55 | +++ b/hw/intc/arm_gic_kvm.c | 41 | return FPSysRegCheckContinue; |
56 | @@ -XXX,XX +XXX,XX @@ static void kvm_gicd_access(GICState *s, int offset, int cpu, | 42 | } |
57 | uint32_t *val, bool write) | 43 | |
44 | +static void gen_branch_fpInactive(DisasContext *s, TCGCond cond, | ||
45 | + TCGLabel *label) | ||
46 | +{ | ||
47 | + /* | ||
48 | + * FPCXT_NS is a special case: it has specific handling for | ||
49 | + * "current FP state is inactive", and must do the PreserveFPState() | ||
50 | + * but not the usual full set of actions done by ExecuteFPCheck(). | ||
51 | + * We don't have a TB flag that matches the fpInactive check, so we | ||
52 | + * do it at runtime as we don't expect FPCXT_NS accesses to be frequent. | ||
53 | + * | ||
54 | + * Emit code that checks fpInactive and does a conditional | ||
55 | + * branch to label based on it: | ||
56 | + * if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive) | ||
57 | + * if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active) | ||
58 | + */ | ||
59 | + assert(cond == TCG_COND_EQ || cond == TCG_COND_NE); | ||
60 | + | ||
61 | + /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */ | ||
62 | + TCGv_i32 aspen, fpca; | ||
63 | + aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); | ||
64 | + fpca = load_cpu_field(v7m.control[M_REG_S]); | ||
65 | + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
66 | + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
67 | + tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); | ||
68 | + tcg_gen_or_i32(fpca, fpca, aspen); | ||
69 | + tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label); | ||
70 | + tcg_temp_free_i32(aspen); | ||
71 | + tcg_temp_free_i32(fpca); | ||
72 | +} | ||
73 | + | ||
74 | static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
75 | |||
76 | fp_sysreg_loadfn *loadfn, | ||
77 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
58 | { | 78 | { |
59 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, | 79 | /* Do a write to an M-profile floating point system register */ |
60 | - KVM_VGIC_ATTR(offset, cpu), val, write); | 80 | TCGv_i32 tmp; |
61 | + KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); | 81 | + TCGLabel *lab_end = NULL; |
82 | |||
83 | switch (fp_sysreg_checks(s, regno)) { | ||
84 | case FPSysRegCheckFailed: | ||
85 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
86 | tcg_temp_free_i32(tmp); | ||
87 | break; | ||
88 | } | ||
89 | + case ARM_VFP_FPCXT_NS: | ||
90 | + lab_end = gen_new_label(); | ||
91 | + /* fpInactive case: write is a NOP, so branch to end */ | ||
92 | + gen_branch_fpInactive(s, TCG_COND_NE, lab_end); | ||
93 | + /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */ | ||
94 | + gen_preserve_fp_state(s); | ||
95 | + /* fall through */ | ||
96 | case ARM_VFP_FPCXT_S: | ||
97 | { | ||
98 | TCGv_i32 sfpa, control; | ||
99 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
100 | default: | ||
101 | g_assert_not_reached(); | ||
102 | } | ||
103 | + if (lab_end) { | ||
104 | + gen_set_label(lab_end); | ||
105 | + } | ||
106 | return true; | ||
62 | } | 107 | } |
63 | 108 | ||
64 | static void kvm_gicc_access(GICState *s, int offset, int cpu, | 109 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, |
65 | uint32_t *val, bool write) | ||
66 | { | 110 | { |
67 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS, | 111 | /* Do a read from an M-profile floating point system register */ |
68 | - KVM_VGIC_ATTR(offset, cpu), val, write); | 112 | TCGv_i32 tmp; |
69 | + KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); | 113 | + TCGLabel *lab_end = NULL; |
114 | + bool lookup_tb = false; | ||
115 | |||
116 | switch (fp_sysreg_checks(s, regno)) { | ||
117 | case FPSysRegCheckFailed: | ||
118 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
119 | fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
120 | gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
121 | tcg_temp_free_i32(fpscr); | ||
122 | - gen_lookup_tb(s); | ||
123 | + lookup_tb = true; | ||
124 | + break; | ||
125 | + } | ||
126 | + case ARM_VFP_FPCXT_NS: | ||
127 | + { | ||
128 | + TCGv_i32 control, sfpa, fpscr, fpdscr, zero; | ||
129 | + TCGLabel *lab_active = gen_new_label(); | ||
130 | + | ||
131 | + lookup_tb = true; | ||
132 | + | ||
133 | + gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); | ||
134 | + /* fpInactive case: reads as FPDSCR_NS */ | ||
135 | + TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
136 | + storefn(s, opaque, tmp); | ||
137 | + lab_end = gen_new_label(); | ||
138 | + tcg_gen_br(lab_end); | ||
139 | + | ||
140 | + gen_set_label(lab_active); | ||
141 | + /* !fpInactive: Reads the same as FPCXT_S, but side effects differ */ | ||
142 | + gen_preserve_fp_state(s); | ||
143 | + tmp = tcg_temp_new_i32(); | ||
144 | + sfpa = tcg_temp_new_i32(); | ||
145 | + fpscr = tcg_temp_new_i32(); | ||
146 | + gen_helper_vfp_get_fpscr(fpscr, cpu_env); | ||
147 | + tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); | ||
148 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
149 | + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); | ||
150 | + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); | ||
151 | + tcg_gen_or_i32(tmp, tmp, sfpa); | ||
152 | + tcg_temp_free_i32(control); | ||
153 | + /* Store result before updating FPSCR, in case it faults */ | ||
154 | + storefn(s, opaque, tmp); | ||
155 | + /* If SFPA is zero then set FPSCR from FPDSCR_NS */ | ||
156 | + fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
157 | + zero = tcg_const_i32(0); | ||
158 | + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); | ||
159 | + gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
160 | + tcg_temp_free_i32(zero); | ||
161 | + tcg_temp_free_i32(sfpa); | ||
162 | + tcg_temp_free_i32(fpdscr); | ||
163 | + tcg_temp_free_i32(fpscr); | ||
164 | break; | ||
165 | } | ||
166 | default: | ||
167 | g_assert_not_reached(); | ||
168 | } | ||
169 | + | ||
170 | + if (lab_end) { | ||
171 | + gen_set_label(lab_end); | ||
172 | + } | ||
173 | + if (lookup_tb) { | ||
174 | + gen_lookup_tb(s); | ||
175 | + } | ||
176 | return true; | ||
70 | } | 177 | } |
71 | 178 | ||
72 | #define for_each_irq_reg(_ctr, _max_irq, _field_width) \ | ||
73 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) | ||
74 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) { | ||
75 | uint32_t numirqs = s->num_irq; | ||
76 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, | ||
77 | - &numirqs, true); | ||
78 | + &numirqs, true, &error_abort); | ||
79 | } | ||
80 | /* Tell the kernel to complete VGIC initialization now */ | ||
81 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
82 | KVM_DEV_ARM_VGIC_CTRL_INIT)) { | ||
83 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
84 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | ||
85 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, | ||
86 | + &error_abort); | ||
87 | } | ||
88 | } else if (ret != -ENODEV && ret != -ENOTSUP) { | ||
89 | error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); | ||
90 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
93 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
95 | |||
96 | /* explicit init of the ITS */ | ||
97 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
98 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | ||
99 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); | ||
100 | |||
101 | /* register the base address */ | ||
102 | kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, | ||
103 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/hw/intc/arm_gicv3_kvm.c | ||
106 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicd_access(GICv3State *s, int offset, | ||
108 | { | ||
109 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, | ||
110 | KVM_VGIC_ATTR(offset, 0), | ||
111 | - val, write); | ||
112 | + val, write, &error_abort); | ||
113 | } | ||
114 | |||
115 | static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, | ||
116 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, | ||
117 | { | ||
118 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, | ||
119 | KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), | ||
120 | - val, write); | ||
121 | + val, write, &error_abort); | ||
122 | } | ||
123 | |||
124 | static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, | ||
125 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, | ||
126 | { | ||
127 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, | ||
128 | KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), | ||
129 | - val, write); | ||
130 | + val, write, &error_abort); | ||
131 | } | ||
132 | |||
133 | static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, | ||
134 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, | ||
135 | KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | | ||
136 | (VGIC_LEVEL_INFO_LINE_LEVEL << | ||
137 | KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), | ||
138 | - val, write); | ||
139 | + val, write, &error_abort); | ||
140 | } | ||
141 | |||
142 | /* Loop through each distributor IRQ related register; since bits | ||
143 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) | ||
144 | /* Initialize to actual HW supported configuration */ | ||
145 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, | ||
146 | KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), | ||
147 | - &c->icc_ctlr_el1[GICV3_NS], false); | ||
148 | + &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); | ||
149 | |||
150 | c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; | ||
151 | } | ||
152 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | ||
153 | } | ||
154 | |||
155 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, | ||
156 | - 0, &s->num_irq, true); | ||
157 | + 0, &s->num_irq, true, &error_abort); | ||
158 | |||
159 | /* Tell the kernel to complete VGIC initialization now */ | ||
160 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
161 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | ||
162 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); | ||
163 | |||
164 | kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, | ||
165 | KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd); | ||
166 | diff --git a/kvm-all.c b/kvm-all.c | ||
167 | index XXXXXXX..XXXXXXX 100644 | ||
168 | --- a/kvm-all.c | ||
169 | +++ b/kvm-all.c | ||
170 | @@ -XXX,XX +XXX,XX @@ | ||
171 | #include "qemu/option.h" | ||
172 | #include "qemu/config-file.h" | ||
173 | #include "qemu/error-report.h" | ||
174 | +#include "qapi/error.h" | ||
175 | #include "hw/hw.h" | ||
176 | #include "hw/pci/msi.h" | ||
177 | #include "hw/pci/msix.h" | ||
178 | @@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int dev_fd, uint32_t group, uint64_t attr) | ||
179 | return kvm_device_ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute) ? 0 : 1; | ||
180 | } | ||
181 | |||
182 | -void kvm_device_access(int fd, int group, uint64_t attr, | ||
183 | - void *val, bool write) | ||
184 | +int kvm_device_access(int fd, int group, uint64_t attr, | ||
185 | + void *val, bool write, Error **errp) | ||
186 | { | ||
187 | struct kvm_device_attr kvmattr; | ||
188 | int err; | ||
189 | @@ -XXX,XX +XXX,XX @@ void kvm_device_access(int fd, int group, uint64_t attr, | ||
190 | write ? KVM_SET_DEVICE_ATTR : KVM_GET_DEVICE_ATTR, | ||
191 | &kvmattr); | ||
192 | if (err < 0) { | ||
193 | - error_report("KVM_%s_DEVICE_ATTR failed: %s", | ||
194 | - write ? "SET" : "GET", strerror(-err)); | ||
195 | - error_printf("Group %d attr 0x%016" PRIx64 "\n", group, attr); | ||
196 | - abort(); | ||
197 | + error_setg_errno(errp, -err, | ||
198 | + "KVM_%s_DEVICE_ATTR failed: Group %d " | ||
199 | + "attr 0x%016" PRIx64, | ||
200 | + write ? "SET" : "GET", group, attr); | ||
201 | } | ||
202 | + return err; | ||
203 | } | ||
204 | |||
205 | /* Return 1 on success, 0 on failure */ | ||
206 | -- | 179 | -- |
207 | 2.7.4 | 180 | 2.20.1 |
208 | 181 | ||
209 | 182 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Now that we have implemented all the features needed by the v8.1M | ||
2 | architecture, we can add the model of the Cortex-M55. This is the | ||
3 | configuration without MVE support; we'll add MVE later. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201210201433.26262-5-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++ | ||
10 | 1 file changed, 42 insertions(+) | ||
11 | |||
12 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/cpu_tcg.c | ||
15 | +++ b/target/arm/cpu_tcg.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj) | ||
17 | cpu->ctr = 0x8000c000; | ||
18 | } | ||
19 | |||
20 | +static void cortex_m55_initfn(Object *obj) | ||
21 | +{ | ||
22 | + ARMCPU *cpu = ARM_CPU(obj); | ||
23 | + | ||
24 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
25 | + set_feature(&cpu->env, ARM_FEATURE_V8_1M); | ||
26 | + set_feature(&cpu->env, ARM_FEATURE_M); | ||
27 | + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
28 | + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | ||
29 | + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
30 | + cpu->midr = 0x410fd221; /* r0p1 */ | ||
31 | + cpu->revidr = 0; | ||
32 | + cpu->pmsav7_dregion = 16; | ||
33 | + cpu->sau_sregion = 8; | ||
34 | + /* | ||
35 | + * These are the MVFR* values for the FPU, no MVE configuration; | ||
36 | + * we will update them later when we implement MVE | ||
37 | + */ | ||
38 | + cpu->isar.mvfr0 = 0x10110221; | ||
39 | + cpu->isar.mvfr1 = 0x12100011; | ||
40 | + cpu->isar.mvfr2 = 0x00000040; | ||
41 | + cpu->isar.id_pfr0 = 0x20000030; | ||
42 | + cpu->isar.id_pfr1 = 0x00000230; | ||
43 | + cpu->isar.id_dfr0 = 0x10200000; | ||
44 | + cpu->id_afr0 = 0x00000000; | ||
45 | + cpu->isar.id_mmfr0 = 0x00111040; | ||
46 | + cpu->isar.id_mmfr1 = 0x00000000; | ||
47 | + cpu->isar.id_mmfr2 = 0x01000000; | ||
48 | + cpu->isar.id_mmfr3 = 0x00000011; | ||
49 | + cpu->isar.id_isar0 = 0x01103110; | ||
50 | + cpu->isar.id_isar1 = 0x02212000; | ||
51 | + cpu->isar.id_isar2 = 0x20232232; | ||
52 | + cpu->isar.id_isar3 = 0x01111131; | ||
53 | + cpu->isar.id_isar4 = 0x01310132; | ||
54 | + cpu->isar.id_isar5 = 0x00000000; | ||
55 | + cpu->isar.id_isar6 = 0x00000000; | ||
56 | + cpu->clidr = 0x00000000; /* caches not implemented */ | ||
57 | + cpu->ctr = 0x8303c003; | ||
58 | +} | ||
59 | + | ||
60 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { | ||
61 | /* Dummy the TCM region regs for the moment */ | ||
62 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | ||
63 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = { | ||
64 | .class_init = arm_v7m_class_init }, | ||
65 | { .name = "cortex-m33", .initfn = cortex_m33_initfn, | ||
66 | .class_init = arm_v7m_class_init }, | ||
67 | + { .name = "cortex-m55", .initfn = cortex_m55_initfn, | ||
68 | + .class_init = arm_v7m_class_init }, | ||
69 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, | ||
70 | { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, | ||
71 | { .name = "ti925t", .initfn = ti925t_initfn }, | ||
72 | -- | ||
73 | 2.20.1 | ||
74 | |||
75 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Support for running KVM on 32-bit Arm hosts was removed in commit | ||
2 | 82bf7ae84ce739e. You can still run a 32-bit guest on a 64-bit Arm | ||
3 | host CPU, but because Arm KVM requires the host and guest CPU types | ||
4 | to match, it is not possible to run a guest that requires a Cortex-A9 | ||
5 | or Cortex-A15 CPU there. That means that the code in the | ||
6 | highbank/midway board models to support KVM is no longer used, and we | ||
7 | can delete it. | ||
1 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Message-id: 20201215144215.28482-1-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/arm/highbank.c | 14 ++++---------- | ||
15 | 1 file changed, 4 insertions(+), 10 deletions(-) | ||
16 | |||
17 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/highbank.c | ||
20 | +++ b/hw/arm/highbank.c | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | #include "hw/arm/boot.h" | ||
23 | #include "hw/loader.h" | ||
24 | #include "net/net.h" | ||
25 | -#include "sysemu/kvm.h" | ||
26 | #include "sysemu/runstate.h" | ||
27 | #include "sysemu/sysemu.h" | ||
28 | #include "hw/boards.h" | ||
29 | @@ -XXX,XX +XXX,XX @@ | ||
30 | #include "hw/cpu/a15mpcore.h" | ||
31 | #include "qemu/log.h" | ||
32 | #include "qom/object.h" | ||
33 | +#include "cpu.h" | ||
34 | |||
35 | #define SMP_BOOT_ADDR 0x100 | ||
36 | #define SMP_BOOT_REG 0x40 | ||
37 | @@ -XXX,XX +XXX,XX @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) | ||
38 | highbank_binfo.loader_start = 0; | ||
39 | highbank_binfo.write_secondary_boot = hb_write_secondary; | ||
40 | highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; | ||
41 | - if (!kvm_enabled()) { | ||
42 | - highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; | ||
43 | - highbank_binfo.write_board_setup = hb_write_board_setup; | ||
44 | - highbank_binfo.secure_board_setup = true; | ||
45 | - } else { | ||
46 | - warn_report("cannot load built-in Monitor support " | ||
47 | - "if KVM is enabled. Some guests (such as Linux) " | ||
48 | - "may not boot."); | ||
49 | - } | ||
50 | + highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; | ||
51 | + highbank_binfo.write_board_setup = hb_write_board_setup; | ||
52 | + highbank_binfo.secure_board_setup = true; | ||
53 | |||
54 | arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo); | ||
55 | } | ||
56 | -- | ||
57 | 2.20.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
1 | From: Pranith Kumar <bobby.prani@gmail.com> | 1 | Currently timer_free() is a simple wrapper for g_free(). This means |
---|---|---|---|
2 | that the timer being freed must not be currently active, as otherwise | ||
3 | QEMU might crash later when the active list is processed and still | ||
4 | has a pointer to freed memory on it. As a result almost all calls to | ||
5 | timer_free() are preceded by a timer_del() call, as can be seen in | ||
6 | the output of | ||
7 | git grep -B1 '\<timer_free\>' | ||
2 | 8 | ||
3 | Tested and confirmed that the stretch i386 debian qcow2 image on a | 9 | This is unfortunate API design as it makes it easy to accidentally |
4 | raspberry pi 2 works. | 10 | misuse (by forgetting the timer_del()), and the correct use is |
11 | annoyingly verbose. | ||
5 | 12 | ||
6 | Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/> | 13 | Make timer_free() imply a timer_del(). |
7 | Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> | 14 | |
8 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
9 | Message-id: 20170418191817.10430-1-bobby.prani@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Message-id: 20201215154107.3255-2-peter.maydell@linaro.org | ||
11 | --- | 19 | --- |
12 | include/qemu/timer.h | 5 ++--- | 20 | include/qemu/timer.h | 24 +++++++++++++----------- |
13 | 1 file changed, 2 insertions(+), 3 deletions(-) | 21 | 1 file changed, 13 insertions(+), 11 deletions(-) |
14 | 22 | ||
15 | diff --git a/include/qemu/timer.h b/include/qemu/timer.h | 23 | diff --git a/include/qemu/timer.h b/include/qemu/timer.h |
16 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/qemu/timer.h | 25 | --- a/include/qemu/timer.h |
18 | +++ b/include/qemu/timer.h | 26 | +++ b/include/qemu/timer.h |
19 | @@ -XXX,XX +XXX,XX @@ static inline int64_t cpu_get_host_ticks(void) | 27 | @@ -XXX,XX +XXX,XX @@ static inline QEMUTimer *timer_new_ms(QEMUClockType type, QEMUTimerCB *cb, |
20 | /* The host CPU doesn't have an easily accessible cycle counter. | 28 | */ |
21 | Just return a monotonically increasing value. This will be | 29 | void timer_deinit(QEMUTimer *ts); |
22 | totally wrong, but hopefully better than nothing. */ | 30 | |
23 | -static inline int64_t cpu_get_host_ticks (void) | 31 | -/** |
24 | +static inline int64_t cpu_get_host_ticks(void) | 32 | - * timer_free: |
25 | { | 33 | - * @ts: the timer |
26 | - static int64_t ticks = 0; | 34 | - * |
27 | - return ticks++; | 35 | - * Free a timer (it must not be on the active list) |
28 | + return get_clock(); | 36 | - */ |
29 | } | 37 | -static inline void timer_free(QEMUTimer *ts) |
30 | #endif | 38 | -{ |
31 | 39 | - g_free(ts); | |
40 | -} | ||
41 | - | ||
42 | /** | ||
43 | * timer_del: | ||
44 | * @ts: the timer | ||
45 | @@ -XXX,XX +XXX,XX @@ static inline void timer_free(QEMUTimer *ts) | ||
46 | */ | ||
47 | void timer_del(QEMUTimer *ts); | ||
48 | |||
49 | +/** | ||
50 | + * timer_free: | ||
51 | + * @ts: the timer | ||
52 | + * | ||
53 | + * Free a timer. This will call timer_del() for you to remove | ||
54 | + * the timer from the active list if it was still active. | ||
55 | + */ | ||
56 | +static inline void timer_free(QEMUTimer *ts) | ||
57 | +{ | ||
58 | + timer_del(ts); | ||
59 | + g_free(ts); | ||
60 | +} | ||
61 | + | ||
62 | /** | ||
63 | * timer_mod_ns: | ||
64 | * @ts: the timer | ||
32 | -- | 65 | -- |
33 | 2.7.4 | 66 | 2.20.1 |
34 | 67 | ||
35 | 68 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | Now that timer_free() implicitly calls timer_del(), sequences |
---|---|---|---|
2 | timer_del(mytimer); | ||
3 | timer_free(mytimer); | ||
2 | 4 | ||
3 | Largely inspired by the TMP105 temperature sensor, here is a model for | 5 | can be simplified to just |
4 | the TMP42{1,2,3} temperature sensors. | 6 | timer_free(mytimer); |
5 | 7 | ||
6 | Specs can be found here : | 8 | Add a Coccinelle script to do this transformation. |
7 | 9 | ||
8 | http://www.ti.com/lit/gpn/tmp421 | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Acked-by: Paolo Bonzini <pbonzini@redhat.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20201215154107.3255-3-peter.maydell@linaro.org | ||
15 | --- | ||
16 | scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++++++++++++++++ | ||
17 | 1 file changed, 18 insertions(+) | ||
18 | create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci | ||
9 | 19 | ||
10 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 20 | diff --git a/scripts/coccinelle/timer-del-timer-free.cocci b/scripts/coccinelle/timer-del-timer-free.cocci |
11 | Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/misc/Makefile.objs | 1 + | ||
16 | hw/misc/tmp421.c | 402 ++++++++++++++++++++++++++++++++++++++++ | ||
17 | default-configs/arm-softmmu.mak | 1 + | ||
18 | 3 files changed, 404 insertions(+) | ||
19 | create mode 100644 hw/misc/tmp421.c | ||
20 | |||
21 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/misc/Makefile.objs | ||
24 | +++ b/hw/misc/Makefile.objs | ||
25 | @@ -XXX,XX +XXX,XX @@ | ||
26 | common-obj-$(CONFIG_APPLESMC) += applesmc.o | ||
27 | common-obj-$(CONFIG_MAX111X) += max111x.o | ||
28 | common-obj-$(CONFIG_TMP105) += tmp105.o | ||
29 | +common-obj-$(CONFIG_TMP421) += tmp421.o | ||
30 | common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o | ||
31 | common-obj-$(CONFIG_SGA) += sga.o | ||
32 | common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o | ||
33 | diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c | ||
34 | new file mode 100644 | 21 | new file mode 100644 |
35 | index XXXXXXX..XXXXXXX | 22 | index XXXXXXX..XXXXXXX |
36 | --- /dev/null | 23 | --- /dev/null |
37 | +++ b/hw/misc/tmp421.c | 24 | +++ b/scripts/coccinelle/timer-del-timer-free.cocci |
38 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ |
39 | +/* | 26 | +// Remove superfluous timer_del() calls |
40 | + * Texas Instruments TMP421 temperature sensor. | 27 | +// |
41 | + * | 28 | +// Copyright Linaro Limited 2020 |
42 | + * Copyright (c) 2016 IBM Corporation. | 29 | +// This work is licensed under the terms of the GNU GPLv2 or later. |
43 | + * | 30 | +// |
44 | + * Largely inspired by : | 31 | +// spatch --macro-file scripts/cocci-macro-file.h \ |
45 | + * | 32 | +// --sp-file scripts/coccinelle/timer-del-timer-free.cocci \ |
46 | + * Texas Instruments TMP105 temperature sensor. | 33 | +// --in-place --dir . |
47 | + * | 34 | +// |
48 | + * Copyright (C) 2008 Nokia Corporation | 35 | +// The timer_free() function now implicitly calls timer_del() |
49 | + * Written by Andrzej Zaborowski <andrew@openedhand.com> | 36 | +// for you, so calls to timer_del() immediately before the |
50 | + * | 37 | +// timer_free() of the same timer can be deleted. |
51 | + * This program is free software; you can redistribute it and/or | ||
52 | + * modify it under the terms of the GNU General Public License as | ||
53 | + * published by the Free Software Foundation; either version 2 or | ||
54 | + * (at your option) version 3 of the License. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
59 | + * GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | ||
64 | + | 38 | + |
65 | +#include "qemu/osdep.h" | 39 | +@@ |
66 | +#include "hw/hw.h" | 40 | +expression T; |
67 | +#include "hw/i2c/i2c.h" | 41 | +@@ |
68 | +#include "qapi/error.h" | 42 | +-timer_del(T); |
69 | +#include "qapi/visitor.h" | 43 | + timer_free(T); |
70 | + | ||
71 | +/* Manufacturer / Device ID's */ | ||
72 | +#define TMP421_MANUFACTURER_ID 0x55 | ||
73 | +#define TMP421_DEVICE_ID 0x21 | ||
74 | +#define TMP422_DEVICE_ID 0x22 | ||
75 | +#define TMP423_DEVICE_ID 0x23 | ||
76 | + | ||
77 | +typedef struct DeviceInfo { | ||
78 | + int model; | ||
79 | + const char *name; | ||
80 | +} DeviceInfo; | ||
81 | + | ||
82 | +static const DeviceInfo devices[] = { | ||
83 | + { TMP421_DEVICE_ID, "tmp421" }, | ||
84 | + { TMP422_DEVICE_ID, "tmp422" }, | ||
85 | + { TMP423_DEVICE_ID, "tmp423" }, | ||
86 | +}; | ||
87 | + | ||
88 | +typedef struct TMP421State { | ||
89 | + /*< private >*/ | ||
90 | + I2CSlave i2c; | ||
91 | + /*< public >*/ | ||
92 | + | ||
93 | + int16_t temperature[4]; | ||
94 | + | ||
95 | + uint8_t status; | ||
96 | + uint8_t config[2]; | ||
97 | + uint8_t rate; | ||
98 | + | ||
99 | + uint8_t len; | ||
100 | + uint8_t buf[2]; | ||
101 | + uint8_t pointer; | ||
102 | + | ||
103 | +} TMP421State; | ||
104 | + | ||
105 | +typedef struct TMP421Class { | ||
106 | + I2CSlaveClass parent_class; | ||
107 | + DeviceInfo *dev; | ||
108 | +} TMP421Class; | ||
109 | + | ||
110 | +#define TYPE_TMP421 "tmp421-generic" | ||
111 | +#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421) | ||
112 | + | ||
113 | +#define TMP421_CLASS(klass) \ | ||
114 | + OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421) | ||
115 | +#define TMP421_GET_CLASS(obj) \ | ||
116 | + OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421) | ||
117 | + | ||
118 | +/* the TMP421 registers */ | ||
119 | +#define TMP421_STATUS_REG 0x08 | ||
120 | +#define TMP421_STATUS_BUSY (1 << 7) | ||
121 | +#define TMP421_CONFIG_REG_1 0x09 | ||
122 | +#define TMP421_CONFIG_RANGE (1 << 2) | ||
123 | +#define TMP421_CONFIG_SHUTDOWN (1 << 6) | ||
124 | +#define TMP421_CONFIG_REG_2 0x0A | ||
125 | +#define TMP421_CONFIG_RC (1 << 2) | ||
126 | +#define TMP421_CONFIG_LEN (1 << 3) | ||
127 | +#define TMP421_CONFIG_REN (1 << 4) | ||
128 | +#define TMP421_CONFIG_REN2 (1 << 5) | ||
129 | +#define TMP421_CONFIG_REN3 (1 << 6) | ||
130 | + | ||
131 | +#define TMP421_CONVERSION_RATE_REG 0x0B | ||
132 | +#define TMP421_ONE_SHOT 0x0F | ||
133 | + | ||
134 | +#define TMP421_RESET 0xFC | ||
135 | +#define TMP421_MANUFACTURER_ID_REG 0xFE | ||
136 | +#define TMP421_DEVICE_ID_REG 0xFF | ||
137 | + | ||
138 | +#define TMP421_TEMP_MSB0 0x00 | ||
139 | +#define TMP421_TEMP_MSB1 0x01 | ||
140 | +#define TMP421_TEMP_MSB2 0x02 | ||
141 | +#define TMP421_TEMP_MSB3 0x03 | ||
142 | +#define TMP421_TEMP_LSB0 0x10 | ||
143 | +#define TMP421_TEMP_LSB1 0x11 | ||
144 | +#define TMP421_TEMP_LSB2 0x12 | ||
145 | +#define TMP421_TEMP_LSB3 0x13 | ||
146 | + | ||
147 | +static const int32_t mins[2] = { -40000, -55000 }; | ||
148 | +static const int32_t maxs[2] = { 127000, 150000 }; | ||
149 | + | ||
150 | +static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name, | ||
151 | + void *opaque, Error **errp) | ||
152 | +{ | ||
153 | + TMP421State *s = TMP421(obj); | ||
154 | + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); | ||
155 | + int offset = ext_range * 64 * 256; | ||
156 | + int64_t value; | ||
157 | + int tempid; | ||
158 | + | ||
159 | + if (sscanf(name, "temperature%d", &tempid) != 1) { | ||
160 | + error_setg(errp, "error reading %s: %m", name); | ||
161 | + return; | ||
162 | + } | ||
163 | + | ||
164 | + if (tempid >= 4 || tempid < 0) { | ||
165 | + error_setg(errp, "error reading %s", name); | ||
166 | + return; | ||
167 | + } | ||
168 | + | ||
169 | + value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256; | ||
170 | + | ||
171 | + visit_type_int(v, name, &value, errp); | ||
172 | +} | ||
173 | + | ||
174 | +/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8 | ||
175 | + * fixed point, so units are 1/256 centigrades. A simple ratio will do. | ||
176 | + */ | ||
177 | +static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name, | ||
178 | + void *opaque, Error **errp) | ||
179 | +{ | ||
180 | + TMP421State *s = TMP421(obj); | ||
181 | + Error *local_err = NULL; | ||
182 | + int64_t temp; | ||
183 | + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); | ||
184 | + int offset = ext_range * 64 * 256; | ||
185 | + int tempid; | ||
186 | + | ||
187 | + visit_type_int(v, name, &temp, &local_err); | ||
188 | + if (local_err) { | ||
189 | + error_propagate(errp, local_err); | ||
190 | + return; | ||
191 | + } | ||
192 | + | ||
193 | + if (temp >= maxs[ext_range] || temp < mins[ext_range]) { | ||
194 | + error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range", | ||
195 | + temp / 1000, temp % 1000); | ||
196 | + return; | ||
197 | + } | ||
198 | + | ||
199 | + if (sscanf(name, "temperature%d", &tempid) != 1) { | ||
200 | + error_setg(errp, "error reading %s: %m", name); | ||
201 | + return; | ||
202 | + } | ||
203 | + | ||
204 | + if (tempid >= 4 || tempid < 0) { | ||
205 | + error_setg(errp, "error reading %s", name); | ||
206 | + return; | ||
207 | + } | ||
208 | + | ||
209 | + s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset; | ||
210 | +} | ||
211 | + | ||
212 | +static void tmp421_read(TMP421State *s) | ||
213 | +{ | ||
214 | + TMP421Class *sc = TMP421_GET_CLASS(s); | ||
215 | + | ||
216 | + s->len = 0; | ||
217 | + | ||
218 | + switch (s->pointer) { | ||
219 | + case TMP421_MANUFACTURER_ID_REG: | ||
220 | + s->buf[s->len++] = TMP421_MANUFACTURER_ID; | ||
221 | + break; | ||
222 | + case TMP421_DEVICE_ID_REG: | ||
223 | + s->buf[s->len++] = sc->dev->model; | ||
224 | + break; | ||
225 | + case TMP421_CONFIG_REG_1: | ||
226 | + s->buf[s->len++] = s->config[0]; | ||
227 | + break; | ||
228 | + case TMP421_CONFIG_REG_2: | ||
229 | + s->buf[s->len++] = s->config[1]; | ||
230 | + break; | ||
231 | + case TMP421_CONVERSION_RATE_REG: | ||
232 | + s->buf[s->len++] = s->rate; | ||
233 | + break; | ||
234 | + case TMP421_STATUS_REG: | ||
235 | + s->buf[s->len++] = s->status; | ||
236 | + break; | ||
237 | + | ||
238 | + /* FIXME: check for channel enablement in config registers */ | ||
239 | + case TMP421_TEMP_MSB0: | ||
240 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8); | ||
241 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; | ||
242 | + break; | ||
243 | + case TMP421_TEMP_MSB1: | ||
244 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8); | ||
245 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; | ||
246 | + break; | ||
247 | + case TMP421_TEMP_MSB2: | ||
248 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8); | ||
249 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; | ||
250 | + break; | ||
251 | + case TMP421_TEMP_MSB3: | ||
252 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8); | ||
253 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; | ||
254 | + break; | ||
255 | + case TMP421_TEMP_LSB0: | ||
256 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; | ||
257 | + break; | ||
258 | + case TMP421_TEMP_LSB1: | ||
259 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; | ||
260 | + break; | ||
261 | + case TMP421_TEMP_LSB2: | ||
262 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; | ||
263 | + break; | ||
264 | + case TMP421_TEMP_LSB3: | ||
265 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; | ||
266 | + break; | ||
267 | + } | ||
268 | +} | ||
269 | + | ||
270 | +static void tmp421_reset(I2CSlave *i2c); | ||
271 | + | ||
272 | +static void tmp421_write(TMP421State *s) | ||
273 | +{ | ||
274 | + switch (s->pointer) { | ||
275 | + case TMP421_CONVERSION_RATE_REG: | ||
276 | + s->rate = s->buf[0]; | ||
277 | + break; | ||
278 | + case TMP421_CONFIG_REG_1: | ||
279 | + s->config[0] = s->buf[0]; | ||
280 | + break; | ||
281 | + case TMP421_CONFIG_REG_2: | ||
282 | + s->config[1] = s->buf[0]; | ||
283 | + break; | ||
284 | + case TMP421_RESET: | ||
285 | + tmp421_reset(I2C_SLAVE(s)); | ||
286 | + break; | ||
287 | + } | ||
288 | +} | ||
289 | + | ||
290 | +static int tmp421_rx(I2CSlave *i2c) | ||
291 | +{ | ||
292 | + TMP421State *s = TMP421(i2c); | ||
293 | + | ||
294 | + if (s->len < 2) { | ||
295 | + return s->buf[s->len++]; | ||
296 | + } else { | ||
297 | + return 0xff; | ||
298 | + } | ||
299 | +} | ||
300 | + | ||
301 | +static int tmp421_tx(I2CSlave *i2c, uint8_t data) | ||
302 | +{ | ||
303 | + TMP421State *s = TMP421(i2c); | ||
304 | + | ||
305 | + if (s->len == 0) { | ||
306 | + /* first byte is the register pointer for a read or write | ||
307 | + * operation */ | ||
308 | + s->pointer = data; | ||
309 | + s->len++; | ||
310 | + } else if (s->len == 1) { | ||
311 | + /* second byte is the data to write. The device only supports | ||
312 | + * one byte writes */ | ||
313 | + s->buf[0] = data; | ||
314 | + tmp421_write(s); | ||
315 | + } | ||
316 | + | ||
317 | + return 0; | ||
318 | +} | ||
319 | + | ||
320 | +static int tmp421_event(I2CSlave *i2c, enum i2c_event event) | ||
321 | +{ | ||
322 | + TMP421State *s = TMP421(i2c); | ||
323 | + | ||
324 | + if (event == I2C_START_RECV) { | ||
325 | + tmp421_read(s); | ||
326 | + } | ||
327 | + | ||
328 | + s->len = 0; | ||
329 | + return 0; | ||
330 | +} | ||
331 | + | ||
332 | +static const VMStateDescription vmstate_tmp421 = { | ||
333 | + .name = "TMP421", | ||
334 | + .version_id = 0, | ||
335 | + .minimum_version_id = 0, | ||
336 | + .fields = (VMStateField[]) { | ||
337 | + VMSTATE_UINT8(len, TMP421State), | ||
338 | + VMSTATE_UINT8_ARRAY(buf, TMP421State, 2), | ||
339 | + VMSTATE_UINT8(pointer, TMP421State), | ||
340 | + VMSTATE_UINT8_ARRAY(config, TMP421State, 2), | ||
341 | + VMSTATE_UINT8(status, TMP421State), | ||
342 | + VMSTATE_UINT8(rate, TMP421State), | ||
343 | + VMSTATE_INT16_ARRAY(temperature, TMP421State, 4), | ||
344 | + VMSTATE_I2C_SLAVE(i2c, TMP421State), | ||
345 | + VMSTATE_END_OF_LIST() | ||
346 | + } | ||
347 | +}; | ||
348 | + | ||
349 | +static void tmp421_reset(I2CSlave *i2c) | ||
350 | +{ | ||
351 | + TMP421State *s = TMP421(i2c); | ||
352 | + TMP421Class *sc = TMP421_GET_CLASS(s); | ||
353 | + | ||
354 | + memset(s->temperature, 0, sizeof(s->temperature)); | ||
355 | + s->pointer = 0; | ||
356 | + | ||
357 | + s->config[0] = 0; /* TMP421_CONFIG_RANGE */ | ||
358 | + | ||
359 | + /* resistance correction and channel enablement */ | ||
360 | + switch (sc->dev->model) { | ||
361 | + case TMP421_DEVICE_ID: | ||
362 | + s->config[1] = 0x1c; | ||
363 | + break; | ||
364 | + case TMP422_DEVICE_ID: | ||
365 | + s->config[1] = 0x3c; | ||
366 | + break; | ||
367 | + case TMP423_DEVICE_ID: | ||
368 | + s->config[1] = 0x7c; | ||
369 | + break; | ||
370 | + } | ||
371 | + | ||
372 | + s->rate = 0x7; /* 8Hz */ | ||
373 | + s->status = 0; | ||
374 | +} | ||
375 | + | ||
376 | +static int tmp421_init(I2CSlave *i2c) | ||
377 | +{ | ||
378 | + TMP421State *s = TMP421(i2c); | ||
379 | + | ||
380 | + tmp421_reset(&s->i2c); | ||
381 | + | ||
382 | + return 0; | ||
383 | +} | ||
384 | + | ||
385 | +static void tmp421_initfn(Object *obj) | ||
386 | +{ | ||
387 | + object_property_add(obj, "temperature0", "int", | ||
388 | + tmp421_get_temperature, | ||
389 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
390 | + object_property_add(obj, "temperature1", "int", | ||
391 | + tmp421_get_temperature, | ||
392 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
393 | + object_property_add(obj, "temperature2", "int", | ||
394 | + tmp421_get_temperature, | ||
395 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
396 | + object_property_add(obj, "temperature3", "int", | ||
397 | + tmp421_get_temperature, | ||
398 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
399 | +} | ||
400 | + | ||
401 | +static void tmp421_class_init(ObjectClass *klass, void *data) | ||
402 | +{ | ||
403 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
404 | + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
405 | + TMP421Class *sc = TMP421_CLASS(klass); | ||
406 | + | ||
407 | + k->init = tmp421_init; | ||
408 | + k->event = tmp421_event; | ||
409 | + k->recv = tmp421_rx; | ||
410 | + k->send = tmp421_tx; | ||
411 | + dc->vmsd = &vmstate_tmp421; | ||
412 | + sc->dev = (DeviceInfo *) data; | ||
413 | +} | ||
414 | + | ||
415 | +static const TypeInfo tmp421_info = { | ||
416 | + .name = TYPE_TMP421, | ||
417 | + .parent = TYPE_I2C_SLAVE, | ||
418 | + .instance_size = sizeof(TMP421State), | ||
419 | + .class_size = sizeof(TMP421Class), | ||
420 | + .instance_init = tmp421_initfn, | ||
421 | + .abstract = true, | ||
422 | +}; | ||
423 | + | ||
424 | +static void tmp421_register_types(void) | ||
425 | +{ | ||
426 | + int i; | ||
427 | + | ||
428 | + type_register_static(&tmp421_info); | ||
429 | + for (i = 0; i < ARRAY_SIZE(devices); ++i) { | ||
430 | + TypeInfo ti = { | ||
431 | + .name = devices[i].name, | ||
432 | + .parent = TYPE_TMP421, | ||
433 | + .class_init = tmp421_class_init, | ||
434 | + .class_data = (void *) &devices[i], | ||
435 | + }; | ||
436 | + type_register(&ti); | ||
437 | + } | ||
438 | +} | ||
439 | + | ||
440 | +type_init(tmp421_register_types) | ||
441 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
442 | index XXXXXXX..XXXXXXX 100644 | ||
443 | --- a/default-configs/arm-softmmu.mak | ||
444 | +++ b/default-configs/arm-softmmu.mak | ||
445 | @@ -XXX,XX +XXX,XX @@ CONFIG_TWL92230=y | ||
446 | CONFIG_TSC2005=y | ||
447 | CONFIG_LM832X=y | ||
448 | CONFIG_TMP105=y | ||
449 | +CONFIG_TMP421=y | ||
450 | CONFIG_STELLARIS=y | ||
451 | CONFIG_STELLARIS_INPUT=y | ||
452 | CONFIG_STELLARIS_ENET=y | ||
453 | -- | 44 | -- |
454 | 2.7.4 | 45 | 2.20.1 |
455 | 46 | ||
456 | 47 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | This commit is the result of running the timer-del-timer-free.cocci | ||
2 | script on the whole source tree. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Acked-by: Corey Minyard <cminyard@mvista.com> | ||
6 | Acked-by: Paolo Bonzini <pbonzini@redhat.com> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20201215154107.3255-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | block/iscsi.c | 2 -- | ||
12 | block/nbd.c | 1 - | ||
13 | block/qcow2.c | 1 - | ||
14 | hw/block/nvme.c | 2 -- | ||
15 | hw/char/serial.c | 2 -- | ||
16 | hw/char/virtio-serial-bus.c | 2 -- | ||
17 | hw/ide/core.c | 1 - | ||
18 | hw/input/hid.c | 1 - | ||
19 | hw/intc/apic.c | 1 - | ||
20 | hw/intc/ioapic.c | 1 - | ||
21 | hw/ipmi/ipmi_bmc_extern.c | 1 - | ||
22 | hw/net/e1000.c | 3 --- | ||
23 | hw/net/e1000e_core.c | 8 -------- | ||
24 | hw/net/pcnet-pci.c | 1 - | ||
25 | hw/net/rtl8139.c | 1 - | ||
26 | hw/net/spapr_llan.c | 1 - | ||
27 | hw/net/virtio-net.c | 2 -- | ||
28 | hw/s390x/s390-pci-inst.c | 1 - | ||
29 | hw/sd/sd.c | 1 - | ||
30 | hw/sd/sdhci.c | 2 -- | ||
31 | hw/usb/dev-hub.c | 1 - | ||
32 | hw/usb/hcd-ehci.c | 1 - | ||
33 | hw/usb/hcd-ohci-pci.c | 1 - | ||
34 | hw/usb/hcd-uhci.c | 1 - | ||
35 | hw/usb/hcd-xhci.c | 1 - | ||
36 | hw/usb/redirect.c | 1 - | ||
37 | hw/vfio/display.c | 1 - | ||
38 | hw/virtio/vhost-vsock-common.c | 1 - | ||
39 | hw/virtio/virtio-balloon.c | 1 - | ||
40 | hw/virtio/virtio-rng.c | 1 - | ||
41 | hw/watchdog/wdt_diag288.c | 1 - | ||
42 | hw/watchdog/wdt_i6300esb.c | 1 - | ||
43 | migration/colo.c | 1 - | ||
44 | monitor/hmp-cmds.c | 1 - | ||
45 | net/announce.c | 1 - | ||
46 | net/colo-compare.c | 1 - | ||
47 | net/slirp.c | 1 - | ||
48 | replay/replay-debugging.c | 1 - | ||
49 | target/s390x/cpu.c | 2 -- | ||
50 | ui/console.c | 1 - | ||
51 | ui/spice-core.c | 1 - | ||
52 | util/throttle.c | 1 - | ||
53 | 42 files changed, 58 deletions(-) | ||
54 | |||
55 | diff --git a/block/iscsi.c b/block/iscsi.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/block/iscsi.c | ||
58 | +++ b/block/iscsi.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static void iscsi_detach_aio_context(BlockDriverState *bs) | ||
60 | iscsilun->events = 0; | ||
61 | |||
62 | if (iscsilun->nop_timer) { | ||
63 | - timer_del(iscsilun->nop_timer); | ||
64 | timer_free(iscsilun->nop_timer); | ||
65 | iscsilun->nop_timer = NULL; | ||
66 | } | ||
67 | if (iscsilun->event_timer) { | ||
68 | - timer_del(iscsilun->event_timer); | ||
69 | timer_free(iscsilun->event_timer); | ||
70 | iscsilun->event_timer = NULL; | ||
71 | } | ||
72 | diff --git a/block/nbd.c b/block/nbd.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/block/nbd.c | ||
75 | +++ b/block/nbd.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static void nbd_recv_coroutines_wake_all(BDRVNBDState *s) | ||
77 | static void reconnect_delay_timer_del(BDRVNBDState *s) | ||
78 | { | ||
79 | if (s->reconnect_delay_timer) { | ||
80 | - timer_del(s->reconnect_delay_timer); | ||
81 | timer_free(s->reconnect_delay_timer); | ||
82 | s->reconnect_delay_timer = NULL; | ||
83 | } | ||
84 | diff --git a/block/qcow2.c b/block/qcow2.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/block/qcow2.c | ||
87 | +++ b/block/qcow2.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static void cache_clean_timer_del(BlockDriverState *bs) | ||
89 | { | ||
90 | BDRVQcow2State *s = bs->opaque; | ||
91 | if (s->cache_clean_timer) { | ||
92 | - timer_del(s->cache_clean_timer); | ||
93 | timer_free(s->cache_clean_timer); | ||
94 | s->cache_clean_timer = NULL; | ||
95 | } | ||
96 | diff --git a/hw/block/nvme.c b/hw/block/nvme.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/hw/block/nvme.c | ||
99 | +++ b/hw/block/nvme.c | ||
100 | @@ -XXX,XX +XXX,XX @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req) | ||
101 | static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n) | ||
102 | { | ||
103 | n->sq[sq->sqid] = NULL; | ||
104 | - timer_del(sq->timer); | ||
105 | timer_free(sq->timer); | ||
106 | g_free(sq->io_req); | ||
107 | if (sq->sqid) { | ||
108 | @@ -XXX,XX +XXX,XX @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req) | ||
109 | static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n) | ||
110 | { | ||
111 | n->cq[cq->cqid] = NULL; | ||
112 | - timer_del(cq->timer); | ||
113 | timer_free(cq->timer); | ||
114 | msix_vector_unuse(&n->parent_obj, cq->vector); | ||
115 | if (cq->cqid) { | ||
116 | diff --git a/hw/char/serial.c b/hw/char/serial.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/hw/char/serial.c | ||
119 | +++ b/hw/char/serial.c | ||
120 | @@ -XXX,XX +XXX,XX @@ static void serial_unrealize(DeviceState *dev) | ||
121 | |||
122 | qemu_chr_fe_deinit(&s->chr, false); | ||
123 | |||
124 | - timer_del(s->modem_status_poll); | ||
125 | timer_free(s->modem_status_poll); | ||
126 | |||
127 | - timer_del(s->fifo_timeout_timer); | ||
128 | timer_free(s->fifo_timeout_timer); | ||
129 | |||
130 | fifo8_destroy(&s->recv_fifo); | ||
131 | diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c | ||
132 | index XXXXXXX..XXXXXXX 100644 | ||
133 | --- a/hw/char/virtio-serial-bus.c | ||
134 | +++ b/hw/char/virtio-serial-bus.c | ||
135 | @@ -XXX,XX +XXX,XX @@ static void virtio_serial_post_load_timer_cb(void *opaque) | ||
136 | } | ||
137 | } | ||
138 | g_free(s->post_load->connected); | ||
139 | - timer_del(s->post_load->timer); | ||
140 | timer_free(s->post_load->timer); | ||
141 | g_free(s->post_load); | ||
142 | s->post_load = NULL; | ||
143 | @@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_unrealize(DeviceState *dev) | ||
144 | g_free(vser->ports_map); | ||
145 | if (vser->post_load) { | ||
146 | g_free(vser->post_load->connected); | ||
147 | - timer_del(vser->post_load->timer); | ||
148 | timer_free(vser->post_load->timer); | ||
149 | g_free(vser->post_load); | ||
150 | } | ||
151 | diff --git a/hw/ide/core.c b/hw/ide/core.c | ||
152 | index XXXXXXX..XXXXXXX 100644 | ||
153 | --- a/hw/ide/core.c | ||
154 | +++ b/hw/ide/core.c | ||
155 | @@ -XXX,XX +XXX,XX @@ void ide_init2(IDEBus *bus, qemu_irq irq) | ||
156 | |||
157 | void ide_exit(IDEState *s) | ||
158 | { | ||
159 | - timer_del(s->sector_write_timer); | ||
160 | timer_free(s->sector_write_timer); | ||
161 | qemu_vfree(s->smart_selftest_data); | ||
162 | qemu_vfree(s->io_buffer); | ||
163 | diff --git a/hw/input/hid.c b/hw/input/hid.c | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/hw/input/hid.c | ||
166 | +++ b/hw/input/hid.c | ||
167 | @@ -XXX,XX +XXX,XX @@ static void hid_idle_timer(void *opaque) | ||
168 | static void hid_del_idle_timer(HIDState *hs) | ||
169 | { | ||
170 | if (hs->idle_timer) { | ||
171 | - timer_del(hs->idle_timer); | ||
172 | timer_free(hs->idle_timer); | ||
173 | hs->idle_timer = NULL; | ||
174 | } | ||
175 | diff --git a/hw/intc/apic.c b/hw/intc/apic.c | ||
176 | index XXXXXXX..XXXXXXX 100644 | ||
177 | --- a/hw/intc/apic.c | ||
178 | +++ b/hw/intc/apic.c | ||
179 | @@ -XXX,XX +XXX,XX @@ static void apic_unrealize(DeviceState *dev) | ||
180 | { | ||
181 | APICCommonState *s = APIC(dev); | ||
182 | |||
183 | - timer_del(s->timer); | ||
184 | timer_free(s->timer); | ||
185 | local_apics[s->id] = NULL; | ||
186 | } | ||
187 | diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c | ||
188 | index XXXXXXX..XXXXXXX 100644 | ||
189 | --- a/hw/intc/ioapic.c | ||
190 | +++ b/hw/intc/ioapic.c | ||
191 | @@ -XXX,XX +XXX,XX @@ static void ioapic_unrealize(DeviceState *dev) | ||
192 | { | ||
193 | IOAPICCommonState *s = IOAPIC_COMMON(dev); | ||
194 | |||
195 | - timer_del(s->delayed_ioapic_service_timer); | ||
196 | timer_free(s->delayed_ioapic_service_timer); | ||
197 | } | ||
198 | |||
199 | diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/hw/ipmi/ipmi_bmc_extern.c | ||
202 | +++ b/hw/ipmi/ipmi_bmc_extern.c | ||
203 | @@ -XXX,XX +XXX,XX @@ static void ipmi_bmc_extern_finalize(Object *obj) | ||
204 | { | ||
205 | IPMIBmcExtern *ibe = IPMI_BMC_EXTERN(obj); | ||
206 | |||
207 | - timer_del(ibe->extern_timer); | ||
208 | timer_free(ibe->extern_timer); | ||
209 | } | ||
210 | |||
211 | diff --git a/hw/net/e1000.c b/hw/net/e1000.c | ||
212 | index XXXXXXX..XXXXXXX 100644 | ||
213 | --- a/hw/net/e1000.c | ||
214 | +++ b/hw/net/e1000.c | ||
215 | @@ -XXX,XX +XXX,XX @@ pci_e1000_uninit(PCIDevice *dev) | ||
216 | { | ||
217 | E1000State *d = E1000(dev); | ||
218 | |||
219 | - timer_del(d->autoneg_timer); | ||
220 | timer_free(d->autoneg_timer); | ||
221 | - timer_del(d->mit_timer); | ||
222 | timer_free(d->mit_timer); | ||
223 | - timer_del(d->flush_queue_timer); | ||
224 | timer_free(d->flush_queue_timer); | ||
225 | qemu_del_nic(d->nic); | ||
226 | } | ||
227 | diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c | ||
228 | index XXXXXXX..XXXXXXX 100644 | ||
229 | --- a/hw/net/e1000e_core.c | ||
230 | +++ b/hw/net/e1000e_core.c | ||
231 | @@ -XXX,XX +XXX,XX @@ e1000e_intrmgr_pci_unint(E1000ECore *core) | ||
232 | { | ||
233 | int i; | ||
234 | |||
235 | - timer_del(core->radv.timer); | ||
236 | timer_free(core->radv.timer); | ||
237 | - timer_del(core->rdtr.timer); | ||
238 | timer_free(core->rdtr.timer); | ||
239 | - timer_del(core->raid.timer); | ||
240 | timer_free(core->raid.timer); | ||
241 | |||
242 | - timer_del(core->tadv.timer); | ||
243 | timer_free(core->tadv.timer); | ||
244 | - timer_del(core->tidv.timer); | ||
245 | timer_free(core->tidv.timer); | ||
246 | |||
247 | - timer_del(core->itr.timer); | ||
248 | timer_free(core->itr.timer); | ||
249 | |||
250 | for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { | ||
251 | - timer_del(core->eitr[i].timer); | ||
252 | timer_free(core->eitr[i].timer); | ||
253 | } | ||
254 | } | ||
255 | @@ -XXX,XX +XXX,XX @@ e1000e_core_pci_uninit(E1000ECore *core) | ||
256 | { | ||
257 | int i; | ||
258 | |||
259 | - timer_del(core->autoneg_timer); | ||
260 | timer_free(core->autoneg_timer); | ||
261 | |||
262 | e1000e_intrmgr_pci_unint(core); | ||
263 | diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c | ||
264 | index XXXXXXX..XXXXXXX 100644 | ||
265 | --- a/hw/net/pcnet-pci.c | ||
266 | +++ b/hw/net/pcnet-pci.c | ||
267 | @@ -XXX,XX +XXX,XX @@ static void pci_pcnet_uninit(PCIDevice *dev) | ||
268 | PCIPCNetState *d = PCI_PCNET(dev); | ||
269 | |||
270 | qemu_free_irq(d->state.irq); | ||
271 | - timer_del(d->state.poll_timer); | ||
272 | timer_free(d->state.poll_timer); | ||
273 | qemu_del_nic(d->state.nic); | ||
274 | } | ||
275 | diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c | ||
276 | index XXXXXXX..XXXXXXX 100644 | ||
277 | --- a/hw/net/rtl8139.c | ||
278 | +++ b/hw/net/rtl8139.c | ||
279 | @@ -XXX,XX +XXX,XX @@ static void pci_rtl8139_uninit(PCIDevice *dev) | ||
280 | |||
281 | g_free(s->cplus_txbuffer); | ||
282 | s->cplus_txbuffer = NULL; | ||
283 | - timer_del(s->timer); | ||
284 | timer_free(s->timer); | ||
285 | qemu_del_nic(s->nic); | ||
286 | } | ||
287 | diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c | ||
288 | index XXXXXXX..XXXXXXX 100644 | ||
289 | --- a/hw/net/spapr_llan.c | ||
290 | +++ b/hw/net/spapr_llan.c | ||
291 | @@ -XXX,XX +XXX,XX @@ static void spapr_vlan_instance_finalize(Object *obj) | ||
292 | } | ||
293 | |||
294 | if (dev->rxp_timer) { | ||
295 | - timer_del(dev->rxp_timer); | ||
296 | timer_free(dev->rxp_timer); | ||
297 | } | ||
298 | } | ||
299 | diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c | ||
300 | index XXXXXXX..XXXXXXX 100644 | ||
301 | --- a/hw/net/virtio-net.c | ||
302 | +++ b/hw/net/virtio-net.c | ||
303 | @@ -XXX,XX +XXX,XX @@ static void virtio_net_rsc_cleanup(VirtIONet *n) | ||
304 | g_free(seg); | ||
305 | } | ||
306 | |||
307 | - timer_del(chain->drain_timer); | ||
308 | timer_free(chain->drain_timer); | ||
309 | QTAILQ_REMOVE(&n->rsc_chains, chain, next); | ||
310 | g_free(chain); | ||
311 | @@ -XXX,XX +XXX,XX @@ static void virtio_net_del_queue(VirtIONet *n, int index) | ||
312 | |||
313 | virtio_del_queue(vdev, index * 2); | ||
314 | if (q->tx_timer) { | ||
315 | - timer_del(q->tx_timer); | ||
316 | timer_free(q->tx_timer); | ||
317 | q->tx_timer = NULL; | ||
318 | } else { | ||
319 | diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c | ||
320 | index XXXXXXX..XXXXXXX 100644 | ||
321 | --- a/hw/s390x/s390-pci-inst.c | ||
322 | +++ b/hw/s390x/s390-pci-inst.c | ||
323 | @@ -XXX,XX +XXX,XX @@ void pci_dereg_ioat(S390PCIIOMMU *iommu) | ||
324 | void fmb_timer_free(S390PCIBusDevice *pbdev) | ||
325 | { | ||
326 | if (pbdev->fmb_timer) { | ||
327 | - timer_del(pbdev->fmb_timer); | ||
328 | timer_free(pbdev->fmb_timer); | ||
329 | pbdev->fmb_timer = NULL; | ||
330 | } | ||
331 | diff --git a/hw/sd/sd.c b/hw/sd/sd.c | ||
332 | index XXXXXXX..XXXXXXX 100644 | ||
333 | --- a/hw/sd/sd.c | ||
334 | +++ b/hw/sd/sd.c | ||
335 | @@ -XXX,XX +XXX,XX @@ static void sd_instance_finalize(Object *obj) | ||
336 | { | ||
337 | SDState *sd = SD_CARD(obj); | ||
338 | |||
339 | - timer_del(sd->ocr_power_timer); | ||
340 | timer_free(sd->ocr_power_timer); | ||
341 | } | ||
342 | |||
343 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | ||
344 | index XXXXXXX..XXXXXXX 100644 | ||
345 | --- a/hw/sd/sdhci.c | ||
346 | +++ b/hw/sd/sdhci.c | ||
347 | @@ -XXX,XX +XXX,XX @@ void sdhci_initfn(SDHCIState *s) | ||
348 | |||
349 | void sdhci_uninitfn(SDHCIState *s) | ||
350 | { | ||
351 | - timer_del(s->insert_timer); | ||
352 | timer_free(s->insert_timer); | ||
353 | - timer_del(s->transfer_timer); | ||
354 | timer_free(s->transfer_timer); | ||
355 | |||
356 | g_free(s->fifo_buffer); | ||
357 | diff --git a/hw/usb/dev-hub.c b/hw/usb/dev-hub.c | ||
358 | index XXXXXXX..XXXXXXX 100644 | ||
359 | --- a/hw/usb/dev-hub.c | ||
360 | +++ b/hw/usb/dev-hub.c | ||
361 | @@ -XXX,XX +XXX,XX @@ static void usb_hub_unrealize(USBDevice *dev) | ||
362 | &s->ports[i].port); | ||
363 | } | ||
364 | |||
365 | - timer_del(s->port_timer); | ||
366 | timer_free(s->port_timer); | ||
367 | } | ||
368 | |||
369 | diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c | ||
370 | index XXXXXXX..XXXXXXX 100644 | ||
371 | --- a/hw/usb/hcd-ehci.c | ||
372 | +++ b/hw/usb/hcd-ehci.c | ||
373 | @@ -XXX,XX +XXX,XX @@ void usb_ehci_unrealize(EHCIState *s, DeviceState *dev) | ||
374 | trace_usb_ehci_unrealize(); | ||
375 | |||
376 | if (s->frame_timer) { | ||
377 | - timer_del(s->frame_timer); | ||
378 | timer_free(s->frame_timer); | ||
379 | s->frame_timer = NULL; | ||
380 | } | ||
381 | diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c | ||
382 | index XXXXXXX..XXXXXXX 100644 | ||
383 | --- a/hw/usb/hcd-ohci-pci.c | ||
384 | +++ b/hw/usb/hcd-ohci-pci.c | ||
385 | @@ -XXX,XX +XXX,XX @@ static void usb_ohci_exit(PCIDevice *dev) | ||
386 | usb_bus_release(&s->bus); | ||
387 | } | ||
388 | |||
389 | - timer_del(s->eof_timer); | ||
390 | timer_free(s->eof_timer); | ||
391 | } | ||
392 | |||
393 | diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c | ||
394 | index XXXXXXX..XXXXXXX 100644 | ||
395 | --- a/hw/usb/hcd-uhci.c | ||
396 | +++ b/hw/usb/hcd-uhci.c | ||
397 | @@ -XXX,XX +XXX,XX @@ static void usb_uhci_exit(PCIDevice *dev) | ||
398 | trace_usb_uhci_exit(); | ||
399 | |||
400 | if (s->frame_timer) { | ||
401 | - timer_del(s->frame_timer); | ||
402 | timer_free(s->frame_timer); | ||
403 | s->frame_timer = NULL; | ||
404 | } | ||
405 | diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c | ||
406 | index XXXXXXX..XXXXXXX 100644 | ||
407 | --- a/hw/usb/hcd-xhci.c | ||
408 | +++ b/hw/usb/hcd-xhci.c | ||
409 | @@ -XXX,XX +XXX,XX @@ static void usb_xhci_unrealize(DeviceState *dev) | ||
410 | } | ||
411 | |||
412 | if (xhci->mfwrap_timer) { | ||
413 | - timer_del(xhci->mfwrap_timer); | ||
414 | timer_free(xhci->mfwrap_timer); | ||
415 | xhci->mfwrap_timer = NULL; | ||
416 | } | ||
417 | diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c | ||
418 | index XXXXXXX..XXXXXXX 100644 | ||
419 | --- a/hw/usb/redirect.c | ||
420 | +++ b/hw/usb/redirect.c | ||
421 | @@ -XXX,XX +XXX,XX @@ static void usbredir_unrealize(USBDevice *udev) | ||
422 | qemu_bh_delete(dev->chardev_close_bh); | ||
423 | qemu_bh_delete(dev->device_reject_bh); | ||
424 | |||
425 | - timer_del(dev->attach_timer); | ||
426 | timer_free(dev->attach_timer); | ||
427 | |||
428 | usbredir_cleanup_device_queues(dev); | ||
429 | diff --git a/hw/vfio/display.c b/hw/vfio/display.c | ||
430 | index XXXXXXX..XXXXXXX 100644 | ||
431 | --- a/hw/vfio/display.c | ||
432 | +++ b/hw/vfio/display.c | ||
433 | @@ -XXX,XX +XXX,XX @@ static void vfio_display_edid_exit(VFIODisplay *dpy) | ||
434 | |||
435 | g_free(dpy->edid_regs); | ||
436 | g_free(dpy->edid_blob); | ||
437 | - timer_del(dpy->edid_link_timer); | ||
438 | timer_free(dpy->edid_link_timer); | ||
439 | } | ||
440 | |||
441 | diff --git a/hw/virtio/vhost-vsock-common.c b/hw/virtio/vhost-vsock-common.c | ||
442 | index XXXXXXX..XXXXXXX 100644 | ||
443 | --- a/hw/virtio/vhost-vsock-common.c | ||
444 | +++ b/hw/virtio/vhost-vsock-common.c | ||
445 | @@ -XXX,XX +XXX,XX @@ static void vhost_vsock_common_post_load_timer_cleanup(VHostVSockCommon *vvc) | ||
446 | return; | ||
447 | } | ||
448 | |||
449 | - timer_del(vvc->post_load_timer); | ||
450 | timer_free(vvc->post_load_timer); | ||
451 | vvc->post_load_timer = NULL; | ||
452 | } | ||
453 | diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c | ||
454 | index XXXXXXX..XXXXXXX 100644 | ||
455 | --- a/hw/virtio/virtio-balloon.c | ||
456 | +++ b/hw/virtio/virtio-balloon.c | ||
457 | @@ -XXX,XX +XXX,XX @@ static bool balloon_stats_enabled(const VirtIOBalloon *s) | ||
458 | static void balloon_stats_destroy_timer(VirtIOBalloon *s) | ||
459 | { | ||
460 | if (balloon_stats_enabled(s)) { | ||
461 | - timer_del(s->stats_timer); | ||
462 | timer_free(s->stats_timer); | ||
463 | s->stats_timer = NULL; | ||
464 | s->stats_poll_interval = 0; | ||
465 | diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c | ||
466 | index XXXXXXX..XXXXXXX 100644 | ||
467 | --- a/hw/virtio/virtio-rng.c | ||
468 | +++ b/hw/virtio/virtio-rng.c | ||
469 | @@ -XXX,XX +XXX,XX @@ static void virtio_rng_device_unrealize(DeviceState *dev) | ||
470 | VirtIORNG *vrng = VIRTIO_RNG(dev); | ||
471 | |||
472 | qemu_del_vm_change_state_handler(vrng->vmstate); | ||
473 | - timer_del(vrng->rate_limit_timer); | ||
474 | timer_free(vrng->rate_limit_timer); | ||
475 | virtio_del_queue(vdev, 0); | ||
476 | virtio_cleanup(vdev); | ||
477 | diff --git a/hw/watchdog/wdt_diag288.c b/hw/watchdog/wdt_diag288.c | ||
478 | index XXXXXXX..XXXXXXX 100644 | ||
479 | --- a/hw/watchdog/wdt_diag288.c | ||
480 | +++ b/hw/watchdog/wdt_diag288.c | ||
481 | @@ -XXX,XX +XXX,XX @@ static void wdt_diag288_unrealize(DeviceState *dev) | ||
482 | { | ||
483 | DIAG288State *diag288 = DIAG288(dev); | ||
484 | |||
485 | - timer_del(diag288->timer); | ||
486 | timer_free(diag288->timer); | ||
487 | } | ||
488 | |||
489 | diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c | ||
490 | index XXXXXXX..XXXXXXX 100644 | ||
491 | --- a/hw/watchdog/wdt_i6300esb.c | ||
492 | +++ b/hw/watchdog/wdt_i6300esb.c | ||
493 | @@ -XXX,XX +XXX,XX @@ static void i6300esb_exit(PCIDevice *dev) | ||
494 | { | ||
495 | I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev); | ||
496 | |||
497 | - timer_del(d->timer); | ||
498 | timer_free(d->timer); | ||
499 | } | ||
500 | |||
501 | diff --git a/migration/colo.c b/migration/colo.c | ||
502 | index XXXXXXX..XXXXXXX 100644 | ||
503 | --- a/migration/colo.c | ||
504 | +++ b/migration/colo.c | ||
505 | @@ -XXX,XX +XXX,XX @@ out: | ||
506 | * error. | ||
507 | */ | ||
508 | colo_compare_unregister_notifier(&packets_compare_notifier); | ||
509 | - timer_del(s->colo_delay_timer); | ||
510 | timer_free(s->colo_delay_timer); | ||
511 | qemu_event_destroy(&s->colo_checkpoint_event); | ||
512 | |||
513 | diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c | ||
514 | index XXXXXXX..XXXXXXX 100644 | ||
515 | --- a/monitor/hmp-cmds.c | ||
516 | +++ b/monitor/hmp-cmds.c | ||
517 | @@ -XXX,XX +XXX,XX @@ static void hmp_migrate_status_cb(void *opaque) | ||
518 | error_report("%s", info->error_desc); | ||
519 | } | ||
520 | monitor_resume(status->mon); | ||
521 | - timer_del(status->timer); | ||
522 | timer_free(status->timer); | ||
523 | g_free(status); | ||
524 | } | ||
525 | diff --git a/net/announce.c b/net/announce.c | ||
526 | index XXXXXXX..XXXXXXX 100644 | ||
527 | --- a/net/announce.c | ||
528 | +++ b/net/announce.c | ||
529 | @@ -XXX,XX +XXX,XX @@ void qemu_announce_timer_del(AnnounceTimer *timer, bool free_named) | ||
530 | { | ||
531 | bool free_timer = false; | ||
532 | if (timer->tm) { | ||
533 | - timer_del(timer->tm); | ||
534 | timer_free(timer->tm); | ||
535 | timer->tm = NULL; | ||
536 | } | ||
537 | diff --git a/net/colo-compare.c b/net/colo-compare.c | ||
538 | index XXXXXXX..XXXXXXX 100644 | ||
539 | --- a/net/colo-compare.c | ||
540 | +++ b/net/colo-compare.c | ||
541 | @@ -XXX,XX +XXX,XX @@ static void colo_compare_timer_init(CompareState *s) | ||
542 | static void colo_compare_timer_del(CompareState *s) | ||
543 | { | ||
544 | if (s->packet_check_timer) { | ||
545 | - timer_del(s->packet_check_timer); | ||
546 | timer_free(s->packet_check_timer); | ||
547 | s->packet_check_timer = NULL; | ||
548 | } | ||
549 | diff --git a/net/slirp.c b/net/slirp.c | ||
550 | index XXXXXXX..XXXXXXX 100644 | ||
551 | --- a/net/slirp.c | ||
552 | +++ b/net/slirp.c | ||
553 | @@ -XXX,XX +XXX,XX @@ static void *net_slirp_timer_new(SlirpTimerCb cb, | ||
554 | |||
555 | static void net_slirp_timer_free(void *timer, void *opaque) | ||
556 | { | ||
557 | - timer_del(timer); | ||
558 | timer_free(timer); | ||
559 | } | ||
560 | |||
561 | diff --git a/replay/replay-debugging.c b/replay/replay-debugging.c | ||
562 | index XXXXXXX..XXXXXXX 100644 | ||
563 | --- a/replay/replay-debugging.c | ||
564 | +++ b/replay/replay-debugging.c | ||
565 | @@ -XXX,XX +XXX,XX @@ static void replay_delete_break(void) | ||
566 | assert(replay_mutex_locked()); | ||
567 | |||
568 | if (replay_break_timer) { | ||
569 | - timer_del(replay_break_timer); | ||
570 | timer_free(replay_break_timer); | ||
571 | replay_break_timer = NULL; | ||
572 | } | ||
573 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
574 | index XXXXXXX..XXXXXXX 100644 | ||
575 | --- a/target/s390x/cpu.c | ||
576 | +++ b/target/s390x/cpu.c | ||
577 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_finalize(Object *obj) | ||
578 | #if !defined(CONFIG_USER_ONLY) | ||
579 | S390CPU *cpu = S390_CPU(obj); | ||
580 | |||
581 | - timer_del(cpu->env.tod_timer); | ||
582 | timer_free(cpu->env.tod_timer); | ||
583 | - timer_del(cpu->env.cpu_timer); | ||
584 | timer_free(cpu->env.cpu_timer); | ||
585 | |||
586 | qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu); | ||
587 | diff --git a/ui/console.c b/ui/console.c | ||
588 | index XXXXXXX..XXXXXXX 100644 | ||
589 | --- a/ui/console.c | ||
590 | +++ b/ui/console.c | ||
591 | @@ -XXX,XX +XXX,XX @@ static void gui_setup_refresh(DisplayState *ds) | ||
592 | timer_mod(ds->gui_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME)); | ||
593 | } | ||
594 | if (!need_timer && ds->gui_timer != NULL) { | ||
595 | - timer_del(ds->gui_timer); | ||
596 | timer_free(ds->gui_timer); | ||
597 | ds->gui_timer = NULL; | ||
598 | } | ||
599 | diff --git a/ui/spice-core.c b/ui/spice-core.c | ||
600 | index XXXXXXX..XXXXXXX 100644 | ||
601 | --- a/ui/spice-core.c | ||
602 | +++ b/ui/spice-core.c | ||
603 | @@ -XXX,XX +XXX,XX @@ static void timer_cancel(SpiceTimer *timer) | ||
604 | |||
605 | static void timer_remove(SpiceTimer *timer) | ||
606 | { | ||
607 | - timer_del(timer->timer); | ||
608 | timer_free(timer->timer); | ||
609 | g_free(timer); | ||
610 | } | ||
611 | diff --git a/util/throttle.c b/util/throttle.c | ||
612 | index XXXXXXX..XXXXXXX 100644 | ||
613 | --- a/util/throttle.c | ||
614 | +++ b/util/throttle.c | ||
615 | @@ -XXX,XX +XXX,XX @@ static void throttle_timer_destroy(QEMUTimer **timer) | ||
616 | { | ||
617 | assert(*timer != NULL); | ||
618 | |||
619 | - timer_del(*timer); | ||
620 | timer_free(*timer); | ||
621 | *timer = NULL; | ||
622 | } | ||
623 | -- | ||
624 | 2.20.1 | ||
625 | |||
626 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The Arm CPU finalize function uses a sequence of timer_del(), timer_deinit(), | ||
2 | timer_free() to free the timer. The timer_deinit() step in this was always | ||
3 | unnecessary, and now the timer_del() is implied by timer_free(), so we can | ||
4 | collapse this down to simply calling timer_free(). | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20201215154107.3255-5-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/cpu.c | 2 -- | ||
12 | 1 file changed, 2 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.c | ||
17 | +++ b/target/arm/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj) | ||
19 | } | ||
20 | #ifndef CONFIG_USER_ONLY | ||
21 | if (cpu->pmu_timer) { | ||
22 | - timer_del(cpu->pmu_timer); | ||
23 | - timer_deinit(cpu->pmu_timer); | ||
24 | timer_free(cpu->pmu_timer); | ||
25 | } | ||
26 | #endif | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Gan Qixin <ganqixin@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | On all Exynos-based boards, the system powers down itself by driving | 3 | When running device-introspect-test, a memory leak occurred in the |
4 | PS_HOLD signal low - eight bit in PS_HOLD_CONTROL register of PMU. | 4 | digic_timer_init function, so use ptimer_free() in the finalize function to |
5 | Handle writing to respective PMU register to fix power off failure: | 5 | avoid it. |
6 | 6 | ||
7 | reboot: Power down | 7 | ASAN shows memory leak stack: |
8 | Unable to poweroff system | ||
9 | shutdown: 31 output lines suppressed due to ratelimiting | ||
10 | Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000000 | ||
11 | 8 | ||
12 | CPU: 0 PID: 1 Comm: shutdown Not tainted 4.11.0-rc8 #846 | 9 | Indirect leak of 288 byte(s) in 3 object(s) allocated from: |
13 | Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) | 10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) |
14 | [<c031050c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14) | 11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) |
15 | [<c030ba6c>] (show_stack) from [<c05b2800>] (dump_stack+0x88/0x9c) | 12 | #2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432 |
16 | [<c05b2800>] (dump_stack) from [<c03d3140>] (panic+0xdc/0x268) | 13 | #3 0xaaabf5b04084 in digic_timer_init /qemu/hw/timer/digic-timer.c:142 |
17 | [<c03d3140>] (panic) from [<c0343614>] (do_exit+0xa90/0xab4) | 14 | #4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 |
18 | [<c0343614>] (do_exit) from [<c035f2dc>] (SyS_reboot+0x164/0x1d0) | 15 | #5 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564 |
19 | [<c035f2dc>] (SyS_reboot) from [<c0307c80>] (ret_fast_syscall+0x0/0x3c) | 16 | #6 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547 |
17 | #7 0xaaabf5b40e84 in digic_init /qemu/hw/arm/digic.c:46 | ||
18 | #8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
19 | #9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
20 | #10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
21 | #11 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
22 | #12 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
20 | 23 | ||
21 | Additionally the initial value of PS_HOLD has to be changed because | 24 | Reported-by: Euler Robot <euler.robot@huawei.com> |
22 | recent Linux kernel (v4.12-rc1) uses regmap cache for this access. | 25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> |
23 | When the register is kept at reset value, the kernel will not issue a | ||
24 | write to it. Usually the bootloader sets the eight bit of PS_HOLD high | ||
25 | so mimic its existence here. | ||
26 | |||
27 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | ||
28 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
29 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | --- | 28 | --- |
32 | hw/misc/exynos4210_pmu.c | 20 +++++++++++++++++++- | 29 | hw/timer/digic-timer.c | 8 ++++++++ |
33 | 1 file changed, 19 insertions(+), 1 deletion(-) | 30 | 1 file changed, 8 insertions(+) |
34 | 31 | ||
35 | diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c | 32 | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c |
36 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/hw/misc/exynos4210_pmu.c | 34 | --- a/hw/timer/digic-timer.c |
38 | +++ b/hw/misc/exynos4210_pmu.c | 35 | +++ b/hw/timer/digic-timer.c |
39 | @@ -XXX,XX +XXX,XX @@ | 36 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_init(Object *obj) |
40 | 37 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); | |
41 | #include "qemu/osdep.h" | 38 | } |
42 | #include "hw/sysbus.h" | 39 | |
43 | +#include "sysemu/sysemu.h" | 40 | +static void digic_timer_finalize(Object *obj) |
44 | |||
45 | #ifndef DEBUG_PMU | ||
46 | #define DEBUG_PMU 0 | ||
47 | @@ -XXX,XX +XXX,XX @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = { | ||
48 | {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000}, | ||
49 | {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000}, | ||
50 | {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000}, | ||
51 | - {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200}, | ||
52 | + /* | ||
53 | + * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit. | ||
54 | + * DATA bit high, set usually by bootloader, keeps system on. | ||
55 | + */ | ||
56 | + {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)}, | ||
57 | {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001}, | ||
58 | {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001}, | ||
59 | {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000}, | ||
60 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210PmuState { | ||
61 | uint32_t reg[PMU_NUM_OF_REGISTERS]; | ||
62 | } Exynos4210PmuState; | ||
63 | |||
64 | +static void exynos4210_pmu_poweroff(void) | ||
65 | +{ | 41 | +{ |
66 | + PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n"); | 42 | + DigicTimerState *s = DIGIC_TIMER(obj); |
67 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | 43 | + |
44 | + ptimer_free(s->ptimer); | ||
68 | +} | 45 | +} |
69 | + | 46 | + |
70 | static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset, | 47 | static void digic_timer_class_init(ObjectClass *klass, void *class_data) |
71 | unsigned size) | ||
72 | { | 48 | { |
73 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset, | 49 | DeviceClass *dc = DEVICE_CLASS(klass); |
74 | PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name, | 50 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo digic_timer_info = { |
75 | (uint32_t)offset, (uint32_t)val); | 51 | .parent = TYPE_SYS_BUS_DEVICE, |
76 | s->reg[i] = val; | 52 | .instance_size = sizeof(DigicTimerState), |
77 | + if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) { | 53 | .instance_init = digic_timer_init, |
78 | + /* | 54 | + .instance_finalize = digic_timer_finalize, |
79 | + * We are interested only in setting data bit | 55 | .class_init = digic_timer_class_init, |
80 | + * of PS_HOLD_CONTROL register to indicate power off request. | 56 | }; |
81 | + */ | 57 | |
82 | + exynos4210_pmu_poweroff(); | ||
83 | + } | ||
84 | return; | ||
85 | } | ||
86 | reg_p++; | ||
87 | -- | 58 | -- |
88 | 2.7.4 | 59 | 2.20.1 |
89 | 60 | ||
90 | 61 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Gan Qixin <ganqixin@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Before QOM-ifying the Exynos4 SoC model, move the DRAM initialization | 3 | When running device-introspect-test, a memory leak occurred in the a10_pit_init |
4 | from exynos4210.c to exynos4_boards.c because DRAM is board specific, | 4 | function, so use ptimer_free() in the finalize function to avoid it. |
5 | not SoC. | ||
6 | 5 | ||
7 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 6 | ASAN shows memory leak stack: |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | |
8 | Indirect leak of 288 byte(s) in 6 object(s) allocated from: | ||
9 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
10 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
11 | #2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523 | ||
12 | #3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544 | ||
13 | #4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562 | ||
14 | #5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433 | ||
15 | #6 0xaaabf57415e8 in a10_pit_init /qemu/hw/timer/allwinner-a10-pit.c:278 | ||
16 | #7 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
17 | #8 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564 | ||
18 | #9 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547 | ||
19 | #10 0xaaabf5b94680 in aw_a10_init /qemu/hw/arm/allwinner-a10.c:49 | ||
20 | #11 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
21 | #12 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
22 | |||
23 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
24 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 27 | --- |
11 | include/hw/arm/exynos4210.h | 5 +---- | 28 | hw/timer/allwinner-a10-pit.c | 11 +++++++++++ |
12 | hw/arm/exynos4210.c | 20 +----------------- | 29 | 1 file changed, 11 insertions(+) |
13 | hw/arm/exynos4_boards.c | 50 ++++++++++++++++++++++++++++++++++++++------- | ||
14 | 3 files changed, 45 insertions(+), 30 deletions(-) | ||
15 | 30 | ||
16 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 31 | diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c |
17 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/exynos4210.h | 33 | --- a/hw/timer/allwinner-a10-pit.c |
19 | +++ b/include/hw/arm/exynos4210.h | 34 | +++ b/hw/timer/allwinner-a10-pit.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State { | 35 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj) |
21 | MemoryRegion iram_mem; | ||
22 | MemoryRegion irom_mem; | ||
23 | MemoryRegion irom_alias_mem; | ||
24 | - MemoryRegion dram0_mem; | ||
25 | - MemoryRegion dram1_mem; | ||
26 | MemoryRegion boot_secondary; | ||
27 | MemoryRegion bootreg_mem; | ||
28 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | ||
29 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State { | ||
30 | void exynos4210_write_secondary(ARMCPU *cpu, | ||
31 | const struct arm_boot_info *info); | ||
32 | |||
33 | -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | ||
34 | - unsigned long ram_size); | ||
35 | +Exynos4210State *exynos4210_init(MemoryRegion *system_mem); | ||
36 | |||
37 | /* Initialize exynos4210 IRQ subsystem stub */ | ||
38 | qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); | ||
39 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/hw/arm/exynos4210.c | ||
42 | +++ b/hw/arm/exynos4210.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu) | ||
44 | return mp_affinity; | ||
45 | } | ||
46 | |||
47 | -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | ||
48 | - unsigned long ram_size) | ||
49 | +Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | ||
50 | { | ||
51 | int i, n; | ||
52 | Exynos4210State *s = g_new(Exynos4210State, 1); | ||
53 | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | ||
54 | - unsigned long mem_size; | ||
55 | DeviceState *dev; | ||
56 | SysBusDevice *busdev; | ||
57 | ObjectClass *cpu_oc; | ||
58 | @@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | ||
59 | memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, | ||
60 | &s->iram_mem); | ||
61 | |||
62 | - /* DRAM */ | ||
63 | - mem_size = ram_size; | ||
64 | - if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { | ||
65 | - memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", | ||
66 | - mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); | ||
67 | - vmstate_register_ram_global(&s->dram1_mem); | ||
68 | - memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, | ||
69 | - &s->dram1_mem); | ||
70 | - mem_size = EXYNOS4210_DRAM_MAX_SIZE; | ||
71 | - } | ||
72 | - memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, | ||
73 | - &error_fatal); | ||
74 | - vmstate_register_ram_global(&s->dram0_mem); | ||
75 | - memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, | ||
76 | - &s->dram0_mem); | ||
77 | - | ||
78 | /* PMU. | ||
79 | * The only reason of existence at the moment is that secondary CPU boot | ||
80 | * loader uses PMU INFORM5 register as a holding pen. | ||
81 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/hw/arm/exynos4_boards.c | ||
84 | +++ b/hw/arm/exynos4_boards.c | ||
85 | @@ -XXX,XX +XXX,XX @@ | ||
86 | */ | ||
87 | |||
88 | #include "qemu/osdep.h" | ||
89 | +#include "qapi/error.h" | ||
90 | #include "qemu/error-report.h" | ||
91 | #include "qemu-common.h" | ||
92 | #include "cpu.h" | ||
93 | @@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType { | ||
94 | EXYNOS4_NUM_OF_BOARDS | ||
95 | } Exynos4BoardType; | ||
96 | |||
97 | +typedef struct Exynos4BoardState { | ||
98 | + Exynos4210State *soc; | ||
99 | + MemoryRegion dram0_mem; | ||
100 | + MemoryRegion dram1_mem; | ||
101 | +} Exynos4BoardState; | ||
102 | + | ||
103 | static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = { | ||
104 | [EXYNOS4_BOARD_NURI] = 0xD33, | ||
105 | [EXYNOS4_BOARD_SMDKC210] = 0xB16, | ||
106 | @@ -XXX,XX +XXX,XX @@ static void lan9215_init(uint32_t base, qemu_irq irq) | ||
107 | } | 36 | } |
108 | } | 37 | } |
109 | 38 | ||
110 | -static Exynos4210State *exynos4_boards_init_common(MachineState *machine, | 39 | +static void a10_pit_finalize(Object *obj) |
111 | - Exynos4BoardType board_type) | ||
112 | +static void exynos4_boards_init_ram(Exynos4BoardState *s, | ||
113 | + MemoryRegion *system_mem, | ||
114 | + unsigned long ram_size) | ||
115 | +{ | 40 | +{ |
116 | + unsigned long mem_size = ram_size; | 41 | + AwA10PITState *s = AW_A10_PIT(obj); |
42 | + int i; | ||
117 | + | 43 | + |
118 | + if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { | 44 | + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { |
119 | + memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", | 45 | + ptimer_free(s->timer[i]); |
120 | + mem_size - EXYNOS4210_DRAM_MAX_SIZE, | ||
121 | + &error_fatal); | ||
122 | + vmstate_register_ram_global(&s->dram1_mem); | ||
123 | + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, | ||
124 | + &s->dram1_mem); | ||
125 | + mem_size = EXYNOS4210_DRAM_MAX_SIZE; | ||
126 | + } | 46 | + } |
127 | + | ||
128 | + memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, | ||
129 | + &error_fatal); | ||
130 | + vmstate_register_ram_global(&s->dram0_mem); | ||
131 | + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, | ||
132 | + &s->dram0_mem); | ||
133 | +} | 47 | +} |
134 | + | 48 | + |
135 | +static Exynos4BoardState * | 49 | static void a10_pit_class_init(ObjectClass *klass, void *data) |
136 | +exynos4_boards_init_common(MachineState *machine, | ||
137 | + Exynos4BoardType board_type) | ||
138 | { | 50 | { |
139 | + Exynos4BoardState *s = g_new(Exynos4BoardState, 1); | 51 | DeviceClass *dc = DEVICE_CLASS(klass); |
140 | MachineClass *mc = MACHINE_GET_CLASS(machine); | 52 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo a10_pit_info = { |
141 | 53 | .parent = TYPE_SYS_BUS_DEVICE, | |
142 | if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) { | 54 | .instance_size = sizeof(AwA10PITState), |
143 | @@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine, | 55 | .instance_init = a10_pit_init, |
144 | machine->kernel_cmdline, | 56 | + .instance_finalize = a10_pit_finalize, |
145 | machine->initrd_filename); | 57 | .class_init = a10_pit_class_init, |
146 | 58 | }; | |
147 | - return exynos4210_init(get_system_memory(), | ||
148 | - exynos4_board_ram_size[board_type]); | ||
149 | + exynos4_boards_init_ram(s, get_system_memory(), | ||
150 | + exynos4_board_ram_size[board_type]); | ||
151 | + | ||
152 | + s->soc = exynos4210_init(get_system_memory()); | ||
153 | + | ||
154 | + return s; | ||
155 | } | ||
156 | |||
157 | static void nuri_init(MachineState *machine) | ||
158 | @@ -XXX,XX +XXX,XX @@ static void nuri_init(MachineState *machine) | ||
159 | |||
160 | static void smdkc210_init(MachineState *machine) | ||
161 | { | ||
162 | - Exynos4210State *s = exynos4_boards_init_common(machine, | ||
163 | - EXYNOS4_BOARD_SMDKC210); | ||
164 | + Exynos4BoardState *s = exynos4_boards_init_common(machine, | ||
165 | + EXYNOS4_BOARD_SMDKC210); | ||
166 | |||
167 | lan9215_init(SMDK_LAN9118_BASE_ADDR, | ||
168 | - qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)])); | ||
169 | + qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)])); | ||
170 | arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo); | ||
171 | } | ||
172 | 59 | ||
173 | -- | 60 | -- |
174 | 2.7.4 | 61 | 2.20.1 |
175 | 62 | ||
176 | 63 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Gan Qixin <ganqixin@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Temperatures can be changed from the monitor with : | 3 | When running device-introspect-test, a memory leak occurred in the |
4 | exynos4210_rtc_init function, so use ptimer_free() in the finalize function to | ||
5 | avoid it. | ||
4 | 6 | ||
5 | (qemu) qom-set /machine/unattached/device[2] temperature0 12000 | 7 | ASAN shows memory leak stack: |
6 | 8 | ||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 9 | Indirect leak of 96 byte(s) in 1 object(s) allocated from: |
8 | Message-id: 1496739230-32109-3-git-send-email-clg@kaod.org | 10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) |
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432 | ||
13 | #3 0xaaabf57b3934 in exynos4210_rtc_init /qemu/hw/rtc/exynos4210_rtc.c:567 | ||
14 | #4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
15 | #5 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
16 | #6 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
17 | #7 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
18 | #8 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
19 | #9 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136 | ||
20 | #10 0xaaabf6552708 in aio_bh_poll /qemu/util/async.c:164 | ||
21 | #11 0xaaabf655f19c in aio_dispatch /qemu/util/aio-posix.c:381 | ||
22 | #12 0xaaabf65523f4 in aio_ctx_dispatch /qemu/util/async.c:306 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | 28 | --- |
12 | hw/arm/aspeed.c | 9 +++++++++ | 29 | hw/rtc/exynos4210_rtc.c | 9 +++++++++ |
13 | 1 file changed, 9 insertions(+) | 30 | 1 file changed, 9 insertions(+) |
14 | 31 | ||
15 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 32 | diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c |
16 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/aspeed.c | 34 | --- a/hw/rtc/exynos4210_rtc.c |
18 | +++ b/hw/arm/aspeed.c | 35 | +++ b/hw/rtc/exynos4210_rtc.c |
19 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 36 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj) |
20 | static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) | 37 | sysbus_init_mmio(dev, &s->iomem); |
38 | } | ||
39 | |||
40 | +static void exynos4210_rtc_finalize(Object *obj) | ||
41 | +{ | ||
42 | + Exynos4210RTCState *s = EXYNOS4210_RTC(obj); | ||
43 | + | ||
44 | + ptimer_free(s->ptimer); | ||
45 | + ptimer_free(s->ptimer_1Hz); | ||
46 | +} | ||
47 | + | ||
48 | static void exynos4210_rtc_class_init(ObjectClass *klass, void *data) | ||
21 | { | 49 | { |
22 | AspeedSoCState *soc = &bmc->soc; | 50 | DeviceClass *dc = DEVICE_CLASS(klass); |
23 | + DeviceState *dev; | 51 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_rtc_info = { |
24 | 52 | .parent = TYPE_SYS_BUS_DEVICE, | |
25 | /* The palmetto platform expects a ds3231 RTC but a ds1338 is | 53 | .instance_size = sizeof(Exynos4210RTCState), |
26 | * enough to provide basic RTC features. Alarms will be missing */ | 54 | .instance_init = exynos4210_rtc_init, |
27 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); | 55 | + .instance_finalize = exynos4210_rtc_finalize, |
28 | + | 56 | .class_init = exynos4210_rtc_class_init, |
29 | + /* add a TMP423 temperature sensor */ | 57 | }; |
30 | + dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), | 58 | |
31 | + "tmp423", 0x4c); | ||
32 | + object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); | ||
33 | + object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); | ||
34 | + object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); | ||
35 | + object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); | ||
36 | } | ||
37 | |||
38 | static void palmetto_bmc_init(MachineState *machine) | ||
39 | -- | 59 | -- |
40 | 2.7.4 | 60 | 2.20.1 |
41 | 61 | ||
42 | 62 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Gan Qixin <ganqixin@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | We need to handle both registers and ITS tables. While | 3 | When running device-introspect-test, a memory leak occurred in the |
4 | register handling is standard, ITS table handling is more | 4 | exynos4210_pwm_init function, so use ptimer_free() in the finalize function to |
5 | challenging since the kernel API is devised so that the | 5 | avoid it. |
6 | tables are flushed into guest RAM and not in vmstate buffers. | ||
7 | 6 | ||
8 | Flushing the ITS tables on device pre_save() is too late | 7 | ASAN shows memory leak stack: |
9 | since the guest RAM is already saved at this point. | ||
10 | 8 | ||
11 | Table flushing needs to happen when we are sure the vcpus | 9 | Indirect leak of 240 byte(s) in 5 object(s) allocated from: |
12 | are stopped and before the last dirty page saving. The | 10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) |
13 | right point is RUN_STATE_FINISH_MIGRATE but sometimes the | 11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) |
14 | VM gets stopped before migration launch so let's simply | 12 | #2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523 |
15 | flush the tables each time the VM gets stopped. | 13 | #3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544 |
14 | #4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562 | ||
15 | #5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433 | ||
16 | #6 0xaaabf56a36cc in exynos4210_pwm_init /qemu/hw/timer/exynos4210_pwm.c:401 | ||
17 | #7 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
18 | #8 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
19 | #9 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
20 | #10 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
21 | #11 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
22 | #12 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136 | ||
16 | 23 | ||
17 | For regular ITS registers we just can use vmstate pre_save() | 24 | Reported-by: Euler Robot <euler.robot@huawei.com> |
18 | and post_load() callbacks. | 25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> |
19 | |||
20 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
21 | Message-id: 1497023553-18411-3-git-send-email-eric.auger@redhat.com | ||
22 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
24 | --- | 28 | --- |
25 | include/hw/intc/arm_gicv3_its_common.h | 8 +++ | 29 | hw/timer/exynos4210_pwm.c | 11 +++++++++++ |
26 | hw/intc/arm_gicv3_its_common.c | 10 ++++ | 30 | 1 file changed, 11 insertions(+) |
27 | hw/intc/arm_gicv3_its_kvm.c | 105 +++++++++++++++++++++++++++++++++ | ||
28 | 3 files changed, 123 insertions(+) | ||
29 | 31 | ||
30 | diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h | 32 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c |
31 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/include/hw/intc/arm_gicv3_its_common.h | 34 | --- a/hw/timer/exynos4210_pwm.c |
33 | +++ b/include/hw/intc/arm_gicv3_its_common.h | 35 | +++ b/hw/timer/exynos4210_pwm.c |
34 | @@ -XXX,XX +XXX,XX @@ | 36 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj) |
35 | #define ITS_TRANS_SIZE 0x10000 | 37 | sysbus_init_mmio(dev, &s->iomem); |
36 | #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE) | 38 | } |
37 | 39 | ||
38 | +#define GITS_CTLR 0x0 | 40 | +static void exynos4210_pwm_finalize(Object *obj) |
39 | +#define GITS_IIDR 0x4 | 41 | +{ |
40 | +#define GITS_CBASER 0x80 | 42 | + Exynos4210PWMState *s = EXYNOS4210_PWM(obj); |
41 | +#define GITS_CWRITER 0x88 | 43 | + int i; |
42 | +#define GITS_CREADR 0x90 | ||
43 | +#define GITS_BASER 0x100 | ||
44 | + | 44 | + |
45 | struct GICv3ITSState { | 45 | + for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { |
46 | SysBusDevice parent_obj; | 46 | + ptimer_free(s->timer[i].ptimer); |
47 | |||
48 | @@ -XXX,XX +XXX,XX @@ struct GICv3ITSState { | ||
49 | |||
50 | /* Registers */ | ||
51 | uint32_t ctlr; | ||
52 | + uint32_t iidr; | ||
53 | uint64_t cbaser; | ||
54 | uint64_t cwriter; | ||
55 | uint64_t creadr; | ||
56 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/intc/arm_gicv3_its_common.c | ||
59 | +++ b/hw/intc/arm_gicv3_its_common.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = { | ||
61 | .pre_save = gicv3_its_pre_save, | ||
62 | .post_load = gicv3_its_post_load, | ||
63 | .unmigratable = true, | ||
64 | + .fields = (VMStateField[]) { | ||
65 | + VMSTATE_UINT32(ctlr, GICv3ITSState), | ||
66 | + VMSTATE_UINT32(iidr, GICv3ITSState), | ||
67 | + VMSTATE_UINT64(cbaser, GICv3ITSState), | ||
68 | + VMSTATE_UINT64(cwriter, GICv3ITSState), | ||
69 | + VMSTATE_UINT64(creadr, GICv3ITSState), | ||
70 | + VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8), | ||
71 | + VMSTATE_END_OF_LIST() | ||
72 | + }, | ||
73 | }; | ||
74 | |||
75 | static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, | ||
76 | @@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev) | ||
77 | s->cbaser = 0; | ||
78 | s->cwriter = 0; | ||
79 | s->creadr = 0; | ||
80 | + s->iidr = 0; | ||
81 | memset(&s->baser, 0, sizeof(s->baser)); | ||
82 | |||
83 | gicv3_its_post_load(s, 0); | ||
84 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
87 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid) | ||
89 | return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); | ||
90 | } | ||
91 | |||
92 | +/** | ||
93 | + * vm_change_state_handler - VM change state callback aiming at flushing | ||
94 | + * ITS tables into guest RAM | ||
95 | + * | ||
96 | + * The tables get flushed to guest RAM whenever the VM gets stopped. | ||
97 | + */ | ||
98 | +static void vm_change_state_handler(void *opaque, int running, | ||
99 | + RunState state) | ||
100 | +{ | ||
101 | + GICv3ITSState *s = (GICv3ITSState *)opaque; | ||
102 | + Error *err = NULL; | ||
103 | + int ret; | ||
104 | + | ||
105 | + if (running) { | ||
106 | + return; | ||
107 | + } | ||
108 | + | ||
109 | + ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
110 | + KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err); | ||
111 | + if (err) { | ||
112 | + error_report_err(err); | ||
113 | + } | ||
114 | + if (ret < 0 && ret != -EFAULT) { | ||
115 | + abort(); | ||
116 | + } | 47 | + } |
117 | +} | 48 | +} |
118 | + | 49 | + |
119 | static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | 50 | static void exynos4210_pwm_class_init(ObjectClass *klass, void *data) |
120 | { | ||
121 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | ||
122 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
123 | kvm_msi_use_devid = true; | ||
124 | kvm_gsi_direct_mapping = false; | ||
125 | kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); | ||
126 | + | ||
127 | + qemu_add_vm_change_state_handler(vm_change_state_handler, s); | ||
128 | } | ||
129 | |||
130 | static void kvm_arm_its_init(Object *obj) | ||
131 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_init(Object *obj) | ||
132 | &error_abort); | ||
133 | } | ||
134 | |||
135 | +/** | ||
136 | + * kvm_arm_its_pre_save - handles the saving of ITS registers. | ||
137 | + * ITS tables are flushed into guest RAM separately and earlier, | ||
138 | + * through the VM change state handler, since at the moment pre_save() | ||
139 | + * is called, the guest RAM has already been saved. | ||
140 | + */ | ||
141 | +static void kvm_arm_its_pre_save(GICv3ITSState *s) | ||
142 | +{ | ||
143 | + int i; | ||
144 | + | ||
145 | + for (i = 0; i < 8; i++) { | ||
146 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
147 | + GITS_BASER + i * 8, &s->baser[i], false, | ||
148 | + &error_abort); | ||
149 | + } | ||
150 | + | ||
151 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
152 | + GITS_CTLR, &s->ctlr, false, &error_abort); | ||
153 | + | ||
154 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
155 | + GITS_CBASER, &s->cbaser, false, &error_abort); | ||
156 | + | ||
157 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
158 | + GITS_CREADR, &s->creadr, false, &error_abort); | ||
159 | + | ||
160 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
161 | + GITS_CWRITER, &s->cwriter, false, &error_abort); | ||
162 | + | ||
163 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
164 | + GITS_IIDR, &s->iidr, false, &error_abort); | ||
165 | +} | ||
166 | + | ||
167 | +/** | ||
168 | + * kvm_arm_its_post_load - Restore both the ITS registers and tables | ||
169 | + */ | ||
170 | +static void kvm_arm_its_post_load(GICv3ITSState *s) | ||
171 | +{ | ||
172 | + int i; | ||
173 | + | ||
174 | + if (!s->iidr) { | ||
175 | + return; | ||
176 | + } | ||
177 | + | ||
178 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
179 | + GITS_IIDR, &s->iidr, true, &error_abort); | ||
180 | + | ||
181 | + /* | ||
182 | + * must be written before GITS_CREADR since GITS_CBASER write | ||
183 | + * access resets GITS_CREADR. | ||
184 | + */ | ||
185 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
186 | + GITS_CBASER, &s->cbaser, true, &error_abort); | ||
187 | + | ||
188 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
189 | + GITS_CREADR, &s->creadr, true, &error_abort); | ||
190 | + | ||
191 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
192 | + GITS_CWRITER, &s->cwriter, true, &error_abort); | ||
193 | + | ||
194 | + | ||
195 | + for (i = 0; i < 8; i++) { | ||
196 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
197 | + GITS_BASER + i * 8, &s->baser[i], true, | ||
198 | + &error_abort); | ||
199 | + } | ||
200 | + | ||
201 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
202 | + KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true, | ||
203 | + &error_abort); | ||
204 | + | ||
205 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
206 | + GITS_CTLR, &s->ctlr, true, &error_abort); | ||
207 | +} | ||
208 | + | ||
209 | static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | ||
210 | { | 51 | { |
211 | DeviceClass *dc = DEVICE_CLASS(klass); | 52 | DeviceClass *dc = DEVICE_CLASS(klass); |
212 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | 53 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_pwm_info = { |
213 | 54 | .parent = TYPE_SYS_BUS_DEVICE, | |
214 | dc->realize = kvm_arm_its_realize; | 55 | .instance_size = sizeof(Exynos4210PWMState), |
215 | icc->send_msi = kvm_its_send_msi; | 56 | .instance_init = exynos4210_pwm_init, |
216 | + icc->pre_save = kvm_arm_its_pre_save; | 57 | + .instance_finalize = exynos4210_pwm_finalize, |
217 | + icc->post_load = kvm_arm_its_post_load; | 58 | .class_init = exynos4210_pwm_class_init, |
218 | } | 59 | }; |
219 | 60 | ||
220 | static const TypeInfo kvm_arm_its_info = { | ||
221 | -- | 61 | -- |
222 | 2.7.4 | 62 | 2.20.1 |
223 | 63 | ||
224 | 64 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Gan Qixin <ganqixin@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | This patch adds the flush of the LPI pending bits into the | 3 | When running device-introspect-test, a memory leak occurred in the |
4 | redistributor pending tables. This happens on VM stop. | 4 | mss_timer_init function, so use ptimer_free() in the finalize function to avoid |
5 | it. | ||
5 | 6 | ||
6 | There is no explicit restore as the tables are implicitly sync'ed | 7 | ASAN shows memory leak stack: |
7 | on ITS table restore and on LPI enable at redistributor level. | ||
8 | 8 | ||
9 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 9 | Indirect leak of 192 byte(s) in 2 object(s) allocated from: |
10 | Message-id: 1497023553-18411-4-git-send-email-eric.auger@redhat.com | 10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) |
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432 | ||
13 | #3 0xaaabf58a0010 in mss_timer_init /qemu/hw/timer/mss-timer.c:235 | ||
14 | #4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
15 | #5 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564 | ||
16 | #6 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547 | ||
17 | #7 0xaaabf5b8316c in m2sxxx_soc_initfn /qemu/hw/arm/msf2-soc.c:70 | ||
18 | #8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
19 | #9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
20 | #10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
21 | #11 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
22 | #12 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 28 | --- |
14 | hw/intc/arm_gicv3_kvm.c | 34 ++++++++++++++++++++++++++++++++++ | 29 | hw/timer/mss-timer.c | 13 +++++++++++++ |
15 | 1 file changed, 34 insertions(+) | 30 | 1 file changed, 13 insertions(+) |
16 | 31 | ||
17 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | 32 | diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c |
18 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/intc/arm_gicv3_kvm.c | 34 | --- a/hw/timer/mss-timer.c |
20 | +++ b/hw/intc/arm_gicv3_kvm.c | 35 | +++ b/hw/timer/mss-timer.c |
21 | @@ -XXX,XX +XXX,XX @@ | 36 | @@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj) |
22 | #include "hw/sysbus.h" | 37 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); |
23 | #include "qemu/error-report.h" | 38 | } |
24 | #include "sysemu/kvm.h" | 39 | |
25 | +#include "sysemu/sysemu.h" | 40 | +static void mss_timer_finalize(Object *obj) |
26 | #include "kvm_arm.h" | ||
27 | #include "gicv3_internal.h" | ||
28 | #include "vgic_common.h" | ||
29 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | ||
30 | REGINFO_SENTINEL | ||
31 | }; | ||
32 | |||
33 | +/** | ||
34 | + * vm_change_state_handler - VM change state callback aiming at flushing | ||
35 | + * RDIST pending tables into guest RAM | ||
36 | + * | ||
37 | + * The tables get flushed to guest RAM whenever the VM gets stopped. | ||
38 | + */ | ||
39 | +static void vm_change_state_handler(void *opaque, int running, | ||
40 | + RunState state) | ||
41 | +{ | 41 | +{ |
42 | + GICv3State *s = (GICv3State *)opaque; | 42 | + MSSTimerState *t = MSS_TIMER(obj); |
43 | + Error *err = NULL; | 43 | + int i; |
44 | + int ret; | ||
45 | + | 44 | + |
46 | + if (running) { | 45 | + for (i = 0; i < NUM_TIMERS; i++) { |
47 | + return; | 46 | + struct Msf2Timer *st = &t->timers[i]; |
48 | + } | ||
49 | + | 47 | + |
50 | + ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 48 | + ptimer_free(st->ptimer); |
51 | + KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, | ||
52 | + NULL, true, &err); | ||
53 | + if (err) { | ||
54 | + error_report_err(err); | ||
55 | + } | ||
56 | + if (ret < 0 && ret != -EFAULT) { | ||
57 | + abort(); | ||
58 | + } | 49 | + } |
59 | +} | 50 | +} |
60 | + | 51 | + |
61 | + | 52 | static const VMStateDescription vmstate_timers = { |
62 | static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | 53 | .name = "mss-timer-block", |
63 | { | 54 | .version_id = 1, |
64 | GICv3State *s = KVM_ARM_GICV3(dev); | 55 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo mss_timer_info = { |
65 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | 56 | .parent = TYPE_SYS_BUS_DEVICE, |
66 | return; | 57 | .instance_size = sizeof(MSSTimerState), |
67 | } | 58 | .instance_init = mss_timer_init, |
68 | } | 59 | + .instance_finalize = mss_timer_finalize, |
69 | + if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 60 | .class_init = mss_timer_class_init, |
70 | + KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { | 61 | }; |
71 | + qemu_add_vm_change_state_handler(vm_change_state_handler, s); | 62 | |
72 | + } | ||
73 | } | ||
74 | |||
75 | static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) | ||
76 | -- | 63 | -- |
77 | 2.7.4 | 64 | 2.20.1 |
78 | 65 | ||
79 | 66 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Gan Qixin <ganqixin@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | When a timer is enabled before a reload value is set, the controller | 3 | When running device-introspect-test, a memory leak occurred in the |
4 | waits for a reload value to be set before starting decrementing. This | 4 | mv88w8618_pit_init function, so use ptimer_free() in the finalize function to |
5 | fix tries to cover that case by changing the timer expiry only when | 5 | avoid it. |
6 | a reload value is valid. | ||
7 | 6 | ||
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 7 | ASAN shows memory leak stack: |
9 | Reviewed-by: Andrew Jeffery <andrew@aj.id.au> | 8 | |
10 | Message-id: 1496739312-32304-1-git-send-email-clg@kaod.org | 9 | Indirect leak of 192 byte(s) in 4 object(s) allocated from: |
10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523 | ||
13 | #3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544 | ||
14 | #4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562 | ||
15 | #5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433 | ||
16 | #6 0xaaabf5bb2290 in mv88w8618_timer_init /qemu/hw/arm/musicpal.c:862 | ||
17 | #7 0xaaabf5bb2290 in mv88w8618_pit_init /qemu/hw/arm/musicpal.c:954 | ||
18 | #8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
19 | #9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
20 | #10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
21 | #11 0xaaabf5a95540 in qdev_device_help /qemu/softmmu/qdev-monitor.c:283 | ||
22 | #12 0xaaabf5a96940 in qmp_device_add /qemu/softmmu/qdev-monitor.c:801 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 28 | --- |
13 | hw/timer/aspeed_timer.c | 37 +++++++++++++++++++++++++++++-------- | 29 | hw/arm/musicpal.c | 12 ++++++++++++ |
14 | 1 file changed, 29 insertions(+), 8 deletions(-) | 30 | 1 file changed, 12 insertions(+) |
15 | 31 | ||
16 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | 32 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c |
17 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/timer/aspeed_timer.c | 34 | --- a/hw/arm/musicpal.c |
19 | +++ b/hw/timer/aspeed_timer.c | 35 | +++ b/hw/arm/musicpal.c |
20 | @@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t) | 36 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_init(Object *obj) |
21 | next = seq[1]; | 37 | sysbus_init_mmio(dev, &s->iomem); |
22 | } else if (now < seq[2]) { | ||
23 | next = seq[2]; | ||
24 | - } else { | ||
25 | + } else if (t->reload) { | ||
26 | reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate); | ||
27 | t->start = now - ((now - t->start) % reload_ns); | ||
28 | + } else { | ||
29 | + /* no reload value, return 0 */ | ||
30 | + break; | ||
31 | } | ||
32 | } | ||
33 | |||
34 | return next; | ||
35 | } | 38 | } |
36 | 39 | ||
37 | +static void aspeed_timer_mod(AspeedTimer *t) | 40 | +static void mv88w8618_pit_finalize(Object *obj) |
38 | +{ | 41 | +{ |
39 | + uint64_t next = calculate_next(t); | 42 | + SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
40 | + if (next) { | 43 | + mv88w8618_pit_state *s = MV88W8618_PIT(dev); |
41 | + timer_mod(&t->timer, next); | 44 | + int i; |
45 | + | ||
46 | + for (i = 0; i < 4; i++) { | ||
47 | + ptimer_free(s->timer[i].ptimer); | ||
42 | + } | 48 | + } |
43 | +} | 49 | +} |
44 | + | 50 | + |
45 | static void aspeed_timer_expire(void *opaque) | 51 | static const VMStateDescription mv88w8618_timer_vmsd = { |
46 | { | 52 | .name = "timer", |
47 | AspeedTimer *t = opaque; | 53 | .version_id = 1, |
48 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_expire(void *opaque) | 54 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo mv88w8618_pit_info = { |
49 | qemu_set_irq(t->irq, t->level); | 55 | .parent = TYPE_SYS_BUS_DEVICE, |
50 | } | 56 | .instance_size = sizeof(mv88w8618_pit_state), |
51 | 57 | .instance_init = mv88w8618_pit_init, | |
52 | - timer_mod(&t->timer, calculate_next(t)); | 58 | + .instance_finalize = mv88w8618_pit_finalize, |
53 | + aspeed_timer_mod(t); | 59 | .class_init = mv88w8618_pit_class_init, |
54 | } | 60 | }; |
55 | 61 | ||
56 | static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg) | ||
57 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, | ||
58 | uint32_t value) | ||
59 | { | ||
60 | AspeedTimer *t; | ||
61 | + uint32_t old_reload; | ||
62 | |||
63 | trace_aspeed_timer_set_value(timer, reg, value); | ||
64 | t = &s->timers[timer]; | ||
65 | switch (reg) { | ||
66 | + case TIMER_REG_RELOAD: | ||
67 | + old_reload = t->reload; | ||
68 | + t->reload = value; | ||
69 | + | ||
70 | + /* If the reload value was not previously set, or zero, and | ||
71 | + * the current value is valid, try to start the timer if it is | ||
72 | + * enabled. | ||
73 | + */ | ||
74 | + if (old_reload || !t->reload) { | ||
75 | + break; | ||
76 | + } | ||
77 | + | ||
78 | case TIMER_REG_STATUS: | ||
79 | if (timer_enabled(t)) { | ||
80 | uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
81 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, | ||
82 | uint32_t rate = calculate_rate(t); | ||
83 | |||
84 | t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate); | ||
85 | - timer_mod(&t->timer, calculate_next(t)); | ||
86 | + aspeed_timer_mod(t); | ||
87 | } | ||
88 | break; | ||
89 | - case TIMER_REG_RELOAD: | ||
90 | - t->reload = value; | ||
91 | - break; | ||
92 | case TIMER_REG_MATCH_FIRST: | ||
93 | case TIMER_REG_MATCH_SECOND: | ||
94 | t->match[reg - 2] = value; | ||
95 | if (timer_enabled(t)) { | ||
96 | - timer_mod(&t->timer, calculate_next(t)); | ||
97 | + aspeed_timer_mod(t); | ||
98 | } | ||
99 | break; | ||
100 | default: | ||
101 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable) | ||
102 | trace_aspeed_timer_ctrl_enable(t->id, enable); | ||
103 | if (enable) { | ||
104 | t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
105 | - timer_mod(&t->timer, calculate_next(t)); | ||
106 | + aspeed_timer_mod(t); | ||
107 | } else { | ||
108 | timer_del(&t->timer); | ||
109 | } | ||
110 | -- | 62 | -- |
111 | 2.7.4 | 63 | 2.20.1 |
112 | 64 | ||
113 | 65 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Gan Qixin <ganqixin@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Remove defines not used anywhere. | 3 | When running device-introspect-test, a memory leak occurred in the |
4 | exynos4210_mct_init function, so use ptimer_free() in the finalize function to | ||
5 | avoid it. | ||
4 | 6 | ||
5 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 7 | ASAN shows memory leak stack: |
8 | |||
9 | Indirect leak of 96 byte(s) in 1 object(s) allocated from: | ||
10 | #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) | ||
11 | #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) | ||
12 | #2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432 | ||
13 | #3 0xaaabf56b01a0 in exynos4210_mct_init /qemu/hw/timer/exynos4210_mct.c:1505 | ||
14 | #4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515 | ||
15 | #5 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729 | ||
16 | #6 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153 | ||
17 | #7 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59 | ||
18 | #8 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110 | ||
19 | #9 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136 | ||
20 | #10 0xaaabf6552708 in aio_bh_poll /qemu/util/async.c:164 | ||
21 | #11 0xaaabf655f19c in aio_dispatch /qemu/util/aio-posix.c:381 | ||
22 | #12 0xaaabf65523f4 in aio_ctx_dispatch /qemu/util/async.c:306 | ||
23 | |||
24 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
25 | Signed-off-by: Gan Qixin <ganqixin@huawei.com> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 28 | --- |
9 | hw/timer/exynos4210_mct.c | 3 --- | 29 | hw/timer/exynos4210_mct.c | 14 ++++++++++++++ |
10 | 1 file changed, 3 deletions(-) | 30 | 1 file changed, 14 insertions(+) |
11 | 31 | ||
12 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 32 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c |
13 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/timer/exynos4210_mct.c | 34 | --- a/hw/timer/exynos4210_mct.c |
15 | +++ b/hw/timer/exynos4210_mct.c | 35 | +++ b/hw/timer/exynos4210_mct.c |
16 | @@ -XXX,XX +XXX,XX @@ enum LocalTimerRegCntIndexes { | 36 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj) |
17 | L_REG_CNT_AMOUNT | 37 | sysbus_init_mmio(dev, &s->iomem); |
38 | } | ||
39 | |||
40 | +static void exynos4210_mct_finalize(Object *obj) | ||
41 | +{ | ||
42 | + int i; | ||
43 | + Exynos4210MCTState *s = EXYNOS4210_MCT(obj); | ||
44 | + | ||
45 | + ptimer_free(s->g_timer.ptimer_frc); | ||
46 | + | ||
47 | + for (i = 0; i < 2; i++) { | ||
48 | + ptimer_free(s->l_timer[i].tick_timer.ptimer_tick); | ||
49 | + ptimer_free(s->l_timer[i].ptimer_frc); | ||
50 | + } | ||
51 | +} | ||
52 | + | ||
53 | static void exynos4210_mct_class_init(ObjectClass *klass, void *data) | ||
54 | { | ||
55 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
56 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_mct_info = { | ||
57 | .parent = TYPE_SYS_BUS_DEVICE, | ||
58 | .instance_size = sizeof(Exynos4210MCTState), | ||
59 | .instance_init = exynos4210_mct_init, | ||
60 | + .instance_finalize = exynos4210_mct_finalize, | ||
61 | .class_init = exynos4210_mct_class_init, | ||
18 | }; | 62 | }; |
19 | 63 | ||
20 | -#define MCT_NIRQ 6 | ||
21 | #define MCT_SFR_SIZE 0x444 | ||
22 | |||
23 | #define MCT_GT_CMP_NUM 4 | ||
24 | |||
25 | -#define MCT_GT_MAX_VAL UINT64_MAX | ||
26 | - | ||
27 | #define MCT_GT_COUNTER_STEP 0x100000000ULL | ||
28 | #define MCT_LT_COUNTER_STEP 0x100000000ULL | ||
29 | #define MCT_LT_CNT_LOW_LIMIT 0x100 | ||
30 | -- | 64 | -- |
31 | 2.7.4 | 65 | 2.20.1 |
32 | 66 | ||
33 | 67 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Bin Meng <bin.meng@windriver.com> |
---|---|---|---|
2 | 2 | ||
3 | Statements under 'case' were in some places wrongly indented bringing | 3 | U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap() |
4 | confusion and making the code less readable. Remove also few unneeded | 4 | in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the |
5 | blank lines. No functional changes. | 5 | bandgap has stabilized. |
6 | 6 | ||
7 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 7 | With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6 |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | sabrelite board (mx6qsabrelite_defconfig), with a slight change made |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot |
10 | shell on QEMU with the following command: | ||
11 | |||
12 | $ qemu-system-arm -M sabrelite -smp 4 -m 1G -kernel u-boot \ | ||
13 | -display none -serial null -serial stdio | ||
14 | |||
15 | Boot log below: | ||
16 | |||
17 | U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800) | ||
18 | |||
19 | CPU: Freescale i.MX?? rev1.0 at 792 MHz | ||
20 | Reset cause: POR | ||
21 | Model: Freescale i.MX6 Quad SABRE Lite Board | ||
22 | Board: SABRE Lite | ||
23 | I2C: ready | ||
24 | DRAM: 1 GiB | ||
25 | force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55 | ||
26 | force_idle_bus: failed to clear bus, sda=0 scl=0 | ||
27 | force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c | ||
28 | force_idle_bus: failed to clear bus, sda=0 scl=0 | ||
29 | force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5 | ||
30 | force_idle_bus: failed to clear bus, sda=0 scl=0 | ||
31 | MMC: FSL_SDHC: 0, FSL_SDHC: 1 | ||
32 | Loading Environment from MMC... *** Warning - No block device, using default environment | ||
33 | |||
34 | In: serial | ||
35 | Out: serial | ||
36 | Err: serial | ||
37 | Net: Board Net Initialization Failed | ||
38 | No ethernet found. | ||
39 | starting USB... | ||
40 | Bus usb@2184000: usb dr_mode not found | ||
41 | USB EHCI 1.00 | ||
42 | Bus usb@2184200: USB EHCI 1.00 | ||
43 | scanning bus usb@2184000 for devices... 1 USB Device(s) found | ||
44 | scanning bus usb@2184200 for devices... 1 USB Device(s) found | ||
45 | scanning usb for storage devices... 0 Storage Device(s) found | ||
46 | scanning usb for ethernet devices... 0 Ethernet Device(s) found | ||
47 | Hit any key to stop autoboot: 0 | ||
48 | => | ||
49 | |||
50 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
51 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
52 | Message-id: 20210106063504.10841-2-bmeng.cn@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 53 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 54 | --- |
12 | hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++------------------------- | 55 | hw/misc/imx6_ccm.c | 2 +- |
13 | 1 file changed, 20 insertions(+), 25 deletions(-) | 56 | 1 file changed, 1 insertion(+), 1 deletion(-) |
14 | 57 | ||
15 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 58 | diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c |
16 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/timer/exynos4210_mct.c | 60 | --- a/hw/misc/imx6_ccm.c |
18 | +++ b/hw/timer/exynos4210_mct.c | 61 | +++ b/hw/misc/imx6_ccm.c |
19 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, | 62 | @@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev) |
20 | 63 | s->analog[PMU_REG_3P0] = 0x00000F74; | |
21 | case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): | 64 | s->analog[PMU_REG_2P5] = 0x00005071; |
22 | case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): | 65 | s->analog[PMU_REG_CORE] = 0x00402010; |
23 | - index = GET_G_COMP_IDX(offset); | 66 | - s->analog[PMU_MISC0] = 0x04000000; |
24 | - shift = 8 * (offset & 0x4); | 67 | + s->analog[PMU_MISC0] = 0x04000080; |
25 | - value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); | 68 | s->analog[PMU_MISC1] = 0x00000000; |
26 | + index = GET_G_COMP_IDX(offset); | 69 | s->analog[PMU_MISC2] = 0x00272727; |
27 | + shift = 8 * (offset & 0x4); | ||
28 | + value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); | ||
29 | break; | ||
30 | |||
31 | case G_TCON: | ||
32 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, | ||
33 | lt_i = GET_L_TIMER_IDX(offset); | ||
34 | |||
35 | value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]); | ||
36 | - | ||
37 | break; | ||
38 | |||
39 | case L0_TCON: case L1_TCON: | ||
40 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
41 | |||
42 | case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): | ||
43 | case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): | ||
44 | - index = GET_G_COMP_IDX(offset); | ||
45 | - shift = 8 * (offset & 0x4); | ||
46 | - s->g_timer.reg.comp[index] = | ||
47 | - (s->g_timer.reg.comp[index] & | ||
48 | - (((uint64_t)UINT32_MAX << 32) >> shift)) + | ||
49 | - (value << shift); | ||
50 | + index = GET_G_COMP_IDX(offset); | ||
51 | + shift = 8 * (offset & 0x4); | ||
52 | + s->g_timer.reg.comp[index] = | ||
53 | + (s->g_timer.reg.comp[index] & | ||
54 | + (((uint64_t)UINT32_MAX << 32) >> shift)) + | ||
55 | + (value << shift); | ||
56 | |||
57 | - DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | ||
58 | + DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | ||
59 | |||
60 | - if (offset & 0x4) { | ||
61 | - s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | ||
62 | - } else { | ||
63 | - s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
64 | - } | ||
65 | + if (offset & 0x4) { | ||
66 | + s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | ||
67 | + } else { | ||
68 | + s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
69 | + } | ||
70 | |||
71 | - exynos4210_gfrc_restart(s); | ||
72 | - break; | ||
73 | + exynos4210_gfrc_restart(s); | ||
74 | + break; | ||
75 | |||
76 | case G_TCON: | ||
77 | old_val = s->g_timer.reg.tcon; | ||
78 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
79 | break; | ||
80 | |||
81 | case G_INT_ENB: | ||
82 | - | ||
83 | /* Raise IRQ if transition from disabled to enabled and CSTAT pending */ | ||
84 | for (i = 0; i < MCT_GT_CMP_NUM; i++) { | ||
85 | if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon & | ||
86 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
87 | break; | ||
88 | |||
89 | case L0_TCNTB: case L1_TCNTB: | ||
90 | - | ||
91 | lt_i = GET_L_TIMER_IDX(offset); | ||
92 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
93 | |||
94 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
95 | break; | ||
96 | |||
97 | case L0_ICNTB: case L1_ICNTB: | ||
98 | - | ||
99 | lt_i = GET_L_TIMER_IDX(offset); | ||
100 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
101 | |||
102 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
103 | if (icntb_max[lt_i] < value) { | ||
104 | icntb_max[lt_i] = value; | ||
105 | } | ||
106 | -DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", | ||
107 | - lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); | ||
108 | + DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", | ||
109 | + lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); | ||
110 | #endif | ||
111 | -break; | ||
112 | + break; | ||
113 | |||
114 | case L0_FRCNTB: case L1_FRCNTB: | ||
115 | - | ||
116 | lt_i = GET_L_TIMER_IDX(offset); | ||
117 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
118 | 70 | ||
119 | -- | 71 | -- |
120 | 2.7.4 | 72 | 2.20.1 |
121 | 73 | ||
122 | 74 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Bin Meng <bin.meng@windriver.com> |
---|---|---|---|
2 | 2 | ||
3 | The static array of interrupt combiner mappings is not modified so it | 3 | Currently when U-Boot boots, it prints "??" for i.MX processor: |
4 | can be made const for code safeness. | ||
5 | 4 | ||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 5 | CPU: Freescale i.MX?? rev1.0 at 792 MHz |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | |
7 | The register that was used to determine the silicon type is | ||
8 | undocumented in the latest IMX6DQRM (Rev. 6, 05/2020), but we | ||
9 | can refer to get_cpu_rev() in arch/arm/mach-imx/mx6/soc.c in | ||
10 | the U-Boot source codes that USB_ANALOG_DIGPROG is used. | ||
11 | |||
12 | Update its reset value to indicate i.MX6Q. | ||
13 | |||
14 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
15 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
16 | Message-id: 20210106063504.10841-3-bmeng.cn@gmail.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 18 | --- |
10 | hw/intc/exynos4210_gic.c | 2 +- | 19 | hw/misc/imx6_ccm.c | 2 +- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 20 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 21 | ||
13 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 22 | diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c |
14 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/intc/exynos4210_gic.c | 24 | --- a/hw/misc/imx6_ccm.c |
16 | +++ b/hw/intc/exynos4210_gic.c | 25 | +++ b/hw/misc/imx6_ccm.c |
17 | @@ -XXX,XX +XXX,XX @@ enum ExtInt { | 26 | @@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev) |
18 | * which is INTG16 in Internal Interrupt Combiner. | 27 | s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x00000004; |
19 | */ | 28 | s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000; |
20 | 29 | s->analog[USB_ANALOG_USB2_MISC] = 0x00000002; | |
21 | -static uint32_t | 30 | - s->analog[USB_ANALOG_DIGPROG] = 0x00000000; |
22 | +static const uint32_t | 31 | + s->analog[USB_ANALOG_DIGPROG] = 0x00630000; |
23 | combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 32 | |
24 | /* int combiner groups 16-19 */ | 33 | /* all PLLs need to be locked */ |
25 | { }, { }, { }, { }, | 34 | s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK; |
26 | -- | 35 | -- |
27 | 2.7.4 | 36 | 2.20.1 |
28 | 37 | ||
29 | 38 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Bin Meng <bin.meng@windriver.com> |
---|---|---|---|
2 | 2 | ||
3 | Bring some more readability by declaring local function variables: first | 3 | At present, when booting U-Boot on QEMU sabrelite, we see: |
4 | initialized ones and then the rest (with reversed-christmas-tree order). | ||
5 | 4 | ||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 5 | Net: Board Net Initialization Failed |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | No ethernet found. |
7 | |||
8 | U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the | ||
9 | U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real | ||
10 | board, the Ethernet PHY is at address 6. Adjust this by updating the | ||
11 | "fec-phy-num" property of the fsl_imx6 SoC object. | ||
12 | |||
13 | With this change, U-Boot sees the PHY but complains MAC address: | ||
14 | |||
15 | Net: using phy at 6 | ||
16 | FEC [PRIME] | ||
17 | Error: FEC address not set. | ||
18 | |||
19 | This is due to U-Boot tries to read the MAC address from the fuse, | ||
20 | which QEMU does not have any valid content filled in. However this | ||
21 | does not prevent the Ethernet from working in QEMU. We just need to | ||
22 | set up the MAC address later in the U-Boot command shell, by: | ||
23 | |||
24 | => setenv ethaddr 00:11:22:33:44:55 | ||
25 | |||
26 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
27 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
28 | Message-id: 20210106063504.10841-4-bmeng.cn@gmail.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 30 | --- |
10 | hw/arm/exynos4210.c | 4 ++-- | 31 | hw/arm/sabrelite.c | 4 ++++ |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 32 | 1 file changed, 4 insertions(+) |
12 | 33 | ||
13 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 34 | diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c |
14 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/exynos4210.c | 36 | --- a/hw/arm/sabrelite.c |
16 | +++ b/hw/arm/exynos4210.c | 37 | +++ b/hw/arm/sabrelite.c |
17 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu) | 38 | @@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine) |
18 | 39 | ||
19 | Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | 40 | s = FSL_IMX6(object_new(TYPE_FSL_IMX6)); |
20 | { | 41 | object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); |
21 | - int i, n; | 42 | + |
22 | Exynos4210State *s = g_new(Exynos4210State, 1); | 43 | + /* Ethernet PHY address is 6 */ |
23 | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | 44 | + object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal); |
24 | - DeviceState *dev; | 45 | + |
25 | SysBusDevice *busdev; | 46 | qdev_realize(DEVICE(s), NULL, &error_fatal); |
26 | ObjectClass *cpu_oc; | 47 | |
27 | + DeviceState *dev; | 48 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, |
28 | + int i, n; | ||
29 | |||
30 | cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); | ||
31 | assert(cpu_oc); | ||
32 | -- | 49 | -- |
33 | 2.7.4 | 50 | 2.20.1 |
34 | 51 | ||
35 | 52 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Bin Meng <bin.meng@windriver.com> |
---|---|---|---|
2 | 2 | ||
3 | Fix checkpatch errors: | 3 | This adds the target guide for SABRE Lite board, and documents how |
4 | 1. ERROR: spaces required around that '+' (ctx:VxV) | 4 | to boot a Linux kernel and U-Boot bootloader. |
5 | 2. ERROR: spaces required around that '&' (ctx:VxV) | ||
6 | 5 | ||
7 | No functional changes. | 6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> |
8 | 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | |
9 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 8 | Message-id: 20210106063504.10841-5-bmeng.cn@gmail.com |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | hw/timer/exynos4210_mct.c | 4 ++-- | 11 | docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++++++++++ |
15 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | docs/system/target-arm.rst | 1 + |
13 | 2 files changed, 120 insertions(+) | ||
14 | create mode 100644 docs/system/arm/sabrelite.rst | ||
16 | 15 | ||
17 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 16 | diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst |
17 | new file mode 100644 | ||
18 | index XXXXXXX..XXXXXXX | ||
19 | --- /dev/null | ||
20 | +++ b/docs/system/arm/sabrelite.rst | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | +Boundary Devices SABRE Lite (``sabrelite``) | ||
23 | +=========================================== | ||
24 | + | ||
25 | +Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development | ||
26 | +platform featuring the powerful Freescale / NXP Semiconductor's i.MX 6 Quad | ||
27 | +Applications Processor. | ||
28 | + | ||
29 | +Supported devices | ||
30 | +----------------- | ||
31 | + | ||
32 | +The SABRE Lite machine supports the following devices: | ||
33 | + | ||
34 | + * Up to 4 Cortex A9 cores | ||
35 | + * Generic Interrupt Controller | ||
36 | + * 1 Clock Controller Module | ||
37 | + * 1 System Reset Controller | ||
38 | + * 5 UARTs | ||
39 | + * 2 EPIC timers | ||
40 | + * 1 GPT timer | ||
41 | + * 2 Watchdog timers | ||
42 | + * 1 FEC Ethernet controller | ||
43 | + * 3 I2C controllers | ||
44 | + * 7 GPIO controllers | ||
45 | + * 4 SDHC storage controllers | ||
46 | + * 4 USB 2.0 host controllers | ||
47 | + * 5 ECSPI controllers | ||
48 | + * 1 SST 25VF016B flash | ||
49 | + | ||
50 | +Please note above list is a complete superset the QEMU SABRE Lite machine can | ||
51 | +support. For a normal use case, a device tree blob that represents a real world | ||
52 | +SABRE Lite board, only exposes a subset of devices to the guest software. | ||
53 | + | ||
54 | +Boot options | ||
55 | +------------ | ||
56 | + | ||
57 | +The SABRE Lite machine can start using the standard -kernel functionality | ||
58 | +for loading a Linux kernel, U-Boot bootloader or ELF executable. | ||
59 | + | ||
60 | +Running Linux kernel | ||
61 | +-------------------- | ||
62 | + | ||
63 | +Linux mainline v5.10 release is tested at the time of writing. To build a Linux | ||
64 | +mainline kernel that can be booted by the SABRE Lite machine, simply configure | ||
65 | +the kernel using the imx_v6_v7_defconfig configuration: | ||
66 | + | ||
67 | +.. code-block:: bash | ||
68 | + | ||
69 | + $ export ARCH=arm | ||
70 | + $ export CROSS_COMPILE=arm-linux-gnueabihf- | ||
71 | + $ make imx_v6_v7_defconfig | ||
72 | + $ make | ||
73 | + | ||
74 | +To boot the newly built Linux kernel in QEMU with the SABRE Lite machine, use: | ||
75 | + | ||
76 | +.. code-block:: bash | ||
77 | + | ||
78 | + $ qemu-system-arm -M sabrelite -smp 4 -m 1G \ | ||
79 | + -display none -serial null -serial stdio \ | ||
80 | + -kernel arch/arm/boot/zImage \ | ||
81 | + -dtb arch/arm/boot/dts/imx6q-sabrelite.dtb \ | ||
82 | + -initrd /path/to/rootfs.ext4 \ | ||
83 | + -append "root=/dev/ram" | ||
84 | + | ||
85 | +Running U-Boot | ||
86 | +-------------- | ||
87 | + | ||
88 | +U-Boot mainline v2020.10 release is tested at the time of writing. To build a | ||
89 | +U-Boot mainline bootloader that can be booted by the SABRE Lite machine, use | ||
90 | +the mx6qsabrelite_defconfig with similar commands as described above for Linux: | ||
91 | + | ||
92 | +.. code-block:: bash | ||
93 | + | ||
94 | + $ export CROSS_COMPILE=arm-linux-gnueabihf- | ||
95 | + $ make mx6qsabrelite_defconfig | ||
96 | + | ||
97 | +Note we need to adjust settings by: | ||
98 | + | ||
99 | +.. code-block:: bash | ||
100 | + | ||
101 | + $ make menuconfig | ||
102 | + | ||
103 | +then manually select the following configuration in U-Boot: | ||
104 | + | ||
105 | + Device Tree Control > Provider of DTB for DT Control > Embedded DTB | ||
106 | + | ||
107 | +To start U-Boot using the SABRE Lite machine, provide the u-boot binary to | ||
108 | +the -kernel argument, along with an SD card image with rootfs: | ||
109 | + | ||
110 | +.. code-block:: bash | ||
111 | + | ||
112 | + $ qemu-system-arm -M sabrelite -smp 4 -m 1G \ | ||
113 | + -display none -serial null -serial stdio \ | ||
114 | + -kernel u-boot | ||
115 | + | ||
116 | +The following example shows booting Linux kernel from dhcp, and uses the | ||
117 | +rootfs on an SD card. This requires some additional command line parameters | ||
118 | +for QEMU: | ||
119 | + | ||
120 | +.. code-block:: none | ||
121 | + | ||
122 | + -nic user,tftp=/path/to/kernel/zImage \ | ||
123 | + -drive file=sdcard.img,id=rootfs -device sd-card,drive=rootfs | ||
124 | + | ||
125 | +The directory for the built-in TFTP server should also contain the device tree | ||
126 | +blob of the SABRE Lite board. The sample SD card image was populated with the | ||
127 | +root file system with one single partition. You may adjust the kernel "root=" | ||
128 | +boot parameter accordingly. | ||
129 | + | ||
130 | +After U-Boot boots, type the following commands in the U-Boot command shell to | ||
131 | +boot the Linux kernel: | ||
132 | + | ||
133 | +.. code-block:: none | ||
134 | + | ||
135 | + => setenv ethaddr 00:11:22:33:44:55 | ||
136 | + => setenv bootfile zImage | ||
137 | + => dhcp | ||
138 | + => tftpboot 14000000 imx6q-sabrelite.dtb | ||
139 | + => setenv bootargs root=/dev/mmcblk3p1 | ||
140 | + => bootz 12000000 - 14000000 | ||
141 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
18 | index XXXXXXX..XXXXXXX 100644 | 142 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/timer/exynos4210_mct.c | 143 | --- a/docs/system/target-arm.rst |
20 | +++ b/hw/timer/exynos4210_mct.c | 144 | +++ b/docs/system/target-arm.rst |
21 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | 145 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
22 | { | 146 | arm/versatile |
23 | uint32_t freq = s->freq; | 147 | arm/vexpress |
24 | s->freq = 24000000 / | 148 | arm/aspeed |
25 | - ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) * | 149 | + arm/sabrelite |
26 | + ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg) + 1) * | 150 | arm/digic |
27 | MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); | 151 | arm/musicpal |
28 | 152 | arm/gumstix | |
29 | if (freq != s->freq) { | ||
30 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
31 | |||
32 | DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | ||
33 | |||
34 | - if (offset&0x4) { | ||
35 | + if (offset & 0x4) { | ||
36 | s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | ||
37 | } else { | ||
38 | s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
39 | -- | 153 | -- |
40 | 2.7.4 | 154 | 2.20.1 |
41 | 155 | ||
42 | 156 | diff view generated by jsdifflib |