1 | Target-arm queue... | 1 | Small pile of bug fixes for rc1. I've included my patches to get |
---|---|---|---|
2 | our docs building with Sphinx 3, just for convenience... | ||
2 | 3 | ||
3 | thanks | ||
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit 735286a4f88255e1463d42ce28d8d14181fd32d4: | 6 | The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170613' into staging (2017-06-13 13:51:29 +0100) | 8 | Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000) |
9 | 9 | ||
10 | are available in the git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170613 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102 |
13 | 13 | ||
14 | for you to fetch changes up to 252a7a6a968c279a4636a86b0559ba3a930a90b5: | 14 | for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a: |
15 | 15 | ||
16 | hw/intc/arm_gicv3_its: Allow save/restore (2017-06-13 14:57:01 +0100) | 16 | tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * vITS: Support save/restore | 20 | * target/arm: Fix Neon emulation bugs on big-endian hosts |
21 | * timer/aspeed: Fix timer enablement when reload is not set | 21 | * target/arm: fix handling of HCR.FB |
22 | * aspped: add temperature sensor device | 22 | * target/arm: fix LORID_EL1 access check |
23 | * timer.h: Provide better monotonic time on ARM hosts | 23 | * disas/capstone: Fix monitor disassembly of >32 bytes |
24 | * exynos4210: various cleanups | 24 | * hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) |
25 | * exynos4210: support system poweroff | 25 | * hw/arm/boot: fix SVE for EL3 direct kernel boot |
26 | * hw/display/omap_lcdc: Fix potential NULL pointer dereference | ||
27 | * hw/display/exynos4210_fimd: Fix potential NULL pointer dereference | ||
28 | * target/arm: Get correct MMU index for other-security-state | ||
29 | * configure: Test that gio libs from pkg-config work | ||
30 | * hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work | ||
31 | * docs: Fix building with Sphinx 3 | ||
32 | * tests/qtest/npcm7xx_rng-test: Disable randomness tests | ||
26 | 33 | ||
27 | ---------------------------------------------------------------- | 34 | ---------------------------------------------------------------- |
28 | Cédric Le Goater (3): | 35 | AlexChen (2): |
29 | hw/misc: add a TMP42{1, 2, 3} device model | 36 | hw/display/omap_lcdc: Fix potential NULL pointer dereference |
30 | aspeed: add a temp sensor device on I2C bus 3 | 37 | hw/display/exynos4210_fimd: Fix potential NULL pointer dereference |
31 | timer/aspeed: fix timer enablement when a reload is not set | ||
32 | 38 | ||
33 | Eric Auger (4): | 39 | Peter Maydell (9): |
34 | kvm-all: Pass an error object to kvm_device_access | 40 | target/arm: Fix float16 pairwise Neon ops on big-endian hosts |
35 | hw/intc/arm_gicv3_its: Implement state save/restore | 41 | target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts |
36 | hw/intc/arm_gicv3_kvm: Implement pending table save | 42 | disas/capstone: Fix monitor disassembly of >32 bytes |
37 | hw/intc/arm_gicv3_its: Allow save/restore | 43 | target/arm: Get correct MMU index for other-security-state |
44 | configure: Test that gio libs from pkg-config work | ||
45 | hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work | ||
46 | scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments | ||
47 | qemu-option-trace.rst.inc: Don't use option:: markup | ||
48 | tests/qtest/npcm7xx_rng-test: Disable randomness tests | ||
38 | 49 | ||
39 | Krzysztof Kozlowski (9): | 50 | Philippe Mathieu-Daudé (1): |
40 | hw/intc/exynos4210_gic: Use more meaningful name for local variable | 51 | hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) |
41 | hw/timer/exynos4210_mct: Fix checkpatch style errors | ||
42 | hw/timer/exynos4210_mct: Cleanup indentation and empty new lines | ||
43 | hw/timer/exynos4210_mct: Remove unused defines | ||
44 | hw/arm/exynos: Move DRAM initialization next boards | ||
45 | hw/arm/exynos: Declare local variables in some order | ||
46 | hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string | ||
47 | hw/intc/exynos4210_gic: Constify array of combiner interrupts | ||
48 | hw/misc/exynos4210_pmu: Add support for system poweroff | ||
49 | 52 | ||
50 | Pranith Kumar (1): | 53 | Richard Henderson (11): |
51 | timer.h: Provide better monotonic time | 54 | target/arm: Introduce neon_full_reg_offset |
55 | target/arm: Move neon_element_offset to translate.c | ||
56 | target/arm: Use neon_element_offset in neon_load/store_reg | ||
57 | target/arm: Use neon_element_offset in vfp_reg_offset | ||
58 | target/arm: Add read/write_neon_element32 | ||
59 | target/arm: Expand read/write_neon_element32 to all MemOp | ||
60 | target/arm: Rename neon_load_reg32 to vfp_load_reg32 | ||
61 | target/arm: Add read/write_neon_element64 | ||
62 | target/arm: Rename neon_load_reg64 to vfp_load_reg64 | ||
63 | target/arm: Simplify do_long_3d and do_2scalar_long | ||
64 | target/arm: Improve do_prewiden_3d | ||
52 | 65 | ||
53 | hw/misc/Makefile.objs | 1 + | 66 | Rémi Denis-Courmont (3): |
54 | include/hw/arm/exynos4210.h | 5 +- | 67 | target/arm: fix handling of HCR.FB |
55 | include/hw/intc/arm_gicv3_its_common.h | 8 + | 68 | target/arm: fix LORID_EL1 access check |
56 | include/migration/vmstate.h | 2 + | 69 | hw/arm/boot: fix SVE for EL3 direct kernel boot |
57 | include/qemu/timer.h | 5 +- | ||
58 | include/sysemu/kvm.h | 11 +- | ||
59 | hw/arm/aspeed.c | 9 + | ||
60 | hw/arm/exynos4210.c | 27 +-- | ||
61 | hw/arm/exynos4_boards.c | 50 +++- | ||
62 | hw/intc/arm_gic_kvm.c | 9 +- | ||
63 | hw/intc/arm_gicv3_common.c | 1 + | ||
64 | hw/intc/arm_gicv3_its_common.c | 12 +- | ||
65 | hw/intc/arm_gicv3_its_kvm.c | 131 +++++++++-- | ||
66 | hw/intc/arm_gicv3_kvm.c | 48 +++- | ||
67 | hw/intc/exynos4210_gic.c | 14 +- | ||
68 | hw/misc/exynos4210_pmu.c | 20 +- | ||
69 | hw/misc/tmp421.c | 402 +++++++++++++++++++++++++++++++++ | ||
70 | hw/timer/aspeed_timer.c | 37 ++- | ||
71 | hw/timer/exynos4210_mct.c | 50 ++-- | ||
72 | kvm-all.c | 14 +- | ||
73 | default-configs/arm-softmmu.mak | 1 + | ||
74 | 21 files changed, 741 insertions(+), 116 deletions(-) | ||
75 | create mode 100644 hw/misc/tmp421.c | ||
76 | 70 | ||
71 | docs/qemu-option-trace.rst.inc | 6 +- | ||
72 | configure | 10 +- | ||
73 | include/hw/intc/arm_gicv3_common.h | 1 - | ||
74 | disas/capstone.c | 2 +- | ||
75 | hw/arm/boot.c | 3 + | ||
76 | hw/arm/smmuv3.c | 3 +- | ||
77 | hw/display/exynos4210_fimd.c | 4 +- | ||
78 | hw/display/omap_lcdc.c | 10 +- | ||
79 | hw/intc/arm_gicv3_cpuif.c | 5 +- | ||
80 | target/arm/helper.c | 24 +- | ||
81 | target/arm/m_helper.c | 3 +- | ||
82 | target/arm/translate.c | 153 +++++++++--- | ||
83 | target/arm/vec_helper.c | 12 +- | ||
84 | tests/qtest/npcm7xx_rng-test.c | 14 +- | ||
85 | scripts/kernel-doc | 18 +- | ||
86 | target/arm/translate-neon.c.inc | 472 ++++++++++++++++++++----------------- | ||
87 | target/arm/translate-vfp.c.inc | 341 +++++++++++---------------- | ||
88 | 17 files changed, 588 insertions(+), 493 deletions(-) | ||
89 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We need to handle both registers and ITS tables. While | 3 | This function makes it clear that we're talking about the whole |
4 | register handling is standard, ITS table handling is more | 4 | register, and not the 32-bit piece at index 0. This fixes a bug |
5 | challenging since the kernel API is devised so that the | 5 | when running on a big-endian host. |
6 | tables are flushed into guest RAM and not in vmstate buffers. | ||
7 | 6 | ||
8 | Flushing the ITS tables on device pre_save() is too late | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | since the guest RAM is already saved at this point. | 8 | Message-id: 20201030022618.785675-2-richard.henderson@linaro.org |
10 | |||
11 | Table flushing needs to happen when we are sure the vcpus | ||
12 | are stopped and before the last dirty page saving. The | ||
13 | right point is RUN_STATE_FINISH_MIGRATE but sometimes the | ||
14 | VM gets stopped before migration launch so let's simply | ||
15 | flush the tables each time the VM gets stopped. | ||
16 | |||
17 | For regular ITS registers we just can use vmstate pre_save() | ||
18 | and post_load() callbacks. | ||
19 | |||
20 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
21 | Message-id: 1497023553-18411-3-git-send-email-eric.auger@redhat.com | ||
22 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
24 | --- | 11 | --- |
25 | include/hw/intc/arm_gicv3_its_common.h | 8 +++ | 12 | target/arm/translate.c | 8 ++++++ |
26 | hw/intc/arm_gicv3_its_common.c | 10 ++++ | 13 | target/arm/translate-neon.c.inc | 44 ++++++++++++++++----------------- |
27 | hw/intc/arm_gicv3_its_kvm.c | 105 +++++++++++++++++++++++++++++++++ | 14 | target/arm/translate-vfp.c.inc | 2 +- |
28 | 3 files changed, 123 insertions(+) | 15 | 3 files changed, 31 insertions(+), 23 deletions(-) |
29 | 16 | ||
30 | diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h | 17 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
31 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/include/hw/intc/arm_gicv3_its_common.h | 19 | --- a/target/arm/translate.c |
33 | +++ b/include/hw/intc/arm_gicv3_its_common.h | 20 | +++ b/target/arm/translate.c |
34 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm) |
35 | #define ITS_TRANS_SIZE 0x10000 | 22 | unallocated_encoding(s); |
36 | #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE) | ||
37 | |||
38 | +#define GITS_CTLR 0x0 | ||
39 | +#define GITS_IIDR 0x4 | ||
40 | +#define GITS_CBASER 0x80 | ||
41 | +#define GITS_CWRITER 0x88 | ||
42 | +#define GITS_CREADR 0x90 | ||
43 | +#define GITS_BASER 0x100 | ||
44 | + | ||
45 | struct GICv3ITSState { | ||
46 | SysBusDevice parent_obj; | ||
47 | |||
48 | @@ -XXX,XX +XXX,XX @@ struct GICv3ITSState { | ||
49 | |||
50 | /* Registers */ | ||
51 | uint32_t ctlr; | ||
52 | + uint32_t iidr; | ||
53 | uint64_t cbaser; | ||
54 | uint64_t cwriter; | ||
55 | uint64_t creadr; | ||
56 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/intc/arm_gicv3_its_common.c | ||
59 | +++ b/hw/intc/arm_gicv3_its_common.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = { | ||
61 | .pre_save = gicv3_its_pre_save, | ||
62 | .post_load = gicv3_its_post_load, | ||
63 | .unmigratable = true, | ||
64 | + .fields = (VMStateField[]) { | ||
65 | + VMSTATE_UINT32(ctlr, GICv3ITSState), | ||
66 | + VMSTATE_UINT32(iidr, GICv3ITSState), | ||
67 | + VMSTATE_UINT64(cbaser, GICv3ITSState), | ||
68 | + VMSTATE_UINT64(cwriter, GICv3ITSState), | ||
69 | + VMSTATE_UINT64(creadr, GICv3ITSState), | ||
70 | + VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8), | ||
71 | + VMSTATE_END_OF_LIST() | ||
72 | + }, | ||
73 | }; | ||
74 | |||
75 | static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, | ||
76 | @@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev) | ||
77 | s->cbaser = 0; | ||
78 | s->cwriter = 0; | ||
79 | s->creadr = 0; | ||
80 | + s->iidr = 0; | ||
81 | memset(&s->baser, 0, sizeof(s->baser)); | ||
82 | |||
83 | gicv3_its_post_load(s, 0); | ||
84 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
87 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid) | ||
89 | return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); | ||
90 | } | 23 | } |
91 | 24 | ||
92 | +/** | 25 | +/* |
93 | + * vm_change_state_handler - VM change state callback aiming at flushing | 26 | + * Return the offset of a "full" NEON Dreg. |
94 | + * ITS tables into guest RAM | ||
95 | + * | ||
96 | + * The tables get flushed to guest RAM whenever the VM gets stopped. | ||
97 | + */ | 27 | + */ |
98 | +static void vm_change_state_handler(void *opaque, int running, | 28 | +static long neon_full_reg_offset(unsigned reg) |
99 | + RunState state) | ||
100 | +{ | 29 | +{ |
101 | + GICv3ITSState *s = (GICv3ITSState *)opaque; | 30 | + return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); |
102 | + Error *err = NULL; | ||
103 | + int ret; | ||
104 | + | ||
105 | + if (running) { | ||
106 | + return; | ||
107 | + } | ||
108 | + | ||
109 | + ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
110 | + KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err); | ||
111 | + if (err) { | ||
112 | + error_report_err(err); | ||
113 | + } | ||
114 | + if (ret < 0 && ret != -EFAULT) { | ||
115 | + abort(); | ||
116 | + } | ||
117 | +} | 31 | +} |
118 | + | 32 | + |
119 | static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | 33 | static inline long vfp_reg_offset(bool dp, unsigned reg) |
120 | { | 34 | { |
121 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | 35 | if (dp) { |
122 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | 36 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
123 | kvm_msi_use_devid = true; | 37 | index XXXXXXX..XXXXXXX 100644 |
124 | kvm_gsi_direct_mapping = false; | 38 | --- a/target/arm/translate-neon.c.inc |
125 | kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); | 39 | +++ b/target/arm/translate-neon.c.inc |
126 | + | 40 | @@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size) |
127 | + qemu_add_vm_change_state_handler(vm_change_state_handler, s); | 41 | ofs ^= 8 - element_size; |
42 | } | ||
43 | #endif | ||
44 | - return neon_reg_offset(reg, 0) + ofs; | ||
45 | + return neon_full_reg_offset(reg) + ofs; | ||
128 | } | 46 | } |
129 | 47 | ||
130 | static void kvm_arm_its_init(Object *obj) | 48 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) |
131 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_init(Object *obj) | 49 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) |
132 | &error_abort); | 50 | * We cannot write 16 bytes at once because the |
51 | * destination is unaligned. | ||
52 | */ | ||
53 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | ||
54 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), | ||
55 | 8, 8, tmp); | ||
56 | - tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), | ||
57 | - neon_reg_offset(vd, 0), 8, 8); | ||
58 | + tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1), | ||
59 | + neon_full_reg_offset(vd), 8, 8); | ||
60 | } else { | ||
61 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | ||
62 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), | ||
63 | vec_size, vec_size, tmp); | ||
64 | } | ||
65 | tcg_gen_addi_i32(addr, addr, 1 << size); | ||
66 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) | ||
67 | static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) | ||
68 | { | ||
69 | int vec_size = a->q ? 16 : 8; | ||
70 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
71 | - int rn_ofs = neon_reg_offset(a->vn, 0); | ||
72 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
73 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
74 | + int rn_ofs = neon_full_reg_offset(a->vn); | ||
75 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
76 | |||
77 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
78 | return false; | ||
79 | @@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) | ||
80 | { | ||
81 | /* Handle a 2-reg-shift insn which can be vectorized. */ | ||
82 | int vec_size = a->q ? 16 : 8; | ||
83 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
84 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
85 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
86 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
87 | |||
88 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
89 | return false; | ||
90 | @@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, | ||
91 | { | ||
92 | /* FP operations in 2-reg-and-shift group */ | ||
93 | int vec_size = a->q ? 16 : 8; | ||
94 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
95 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
96 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
97 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
98 | TCGv_ptr fpst; | ||
99 | |||
100 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
102 | return true; | ||
103 | } | ||
104 | |||
105 | - reg_ofs = neon_reg_offset(a->vd, 0); | ||
106 | + reg_ofs = neon_full_reg_offset(a->vd); | ||
107 | vec_size = a->q ? 16 : 8; | ||
108 | imm = asimd_imm_const(a->imm, a->cmode, a->op); | ||
109 | |||
110 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) | ||
111 | return true; | ||
112 | } | ||
113 | |||
114 | - tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), | ||
115 | - neon_reg_offset(a->vn, 0), | ||
116 | - neon_reg_offset(a->vm, 0), | ||
117 | + tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd), | ||
118 | + neon_full_reg_offset(a->vn), | ||
119 | + neon_full_reg_offset(a->vm), | ||
120 | 16, 16, 0, fn_gvec); | ||
121 | return true; | ||
133 | } | 122 | } |
134 | 123 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, | |
135 | +/** | ||
136 | + * kvm_arm_its_pre_save - handles the saving of ITS registers. | ||
137 | + * ITS tables are flushed into guest RAM separately and earlier, | ||
138 | + * through the VM change state handler, since at the moment pre_save() | ||
139 | + * is called, the guest RAM has already been saved. | ||
140 | + */ | ||
141 | +static void kvm_arm_its_pre_save(GICv3ITSState *s) | ||
142 | +{ | ||
143 | + int i; | ||
144 | + | ||
145 | + for (i = 0; i < 8; i++) { | ||
146 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
147 | + GITS_BASER + i * 8, &s->baser[i], false, | ||
148 | + &error_abort); | ||
149 | + } | ||
150 | + | ||
151 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
152 | + GITS_CTLR, &s->ctlr, false, &error_abort); | ||
153 | + | ||
154 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
155 | + GITS_CBASER, &s->cbaser, false, &error_abort); | ||
156 | + | ||
157 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
158 | + GITS_CREADR, &s->creadr, false, &error_abort); | ||
159 | + | ||
160 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
161 | + GITS_CWRITER, &s->cwriter, false, &error_abort); | ||
162 | + | ||
163 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
164 | + GITS_IIDR, &s->iidr, false, &error_abort); | ||
165 | +} | ||
166 | + | ||
167 | +/** | ||
168 | + * kvm_arm_its_post_load - Restore both the ITS registers and tables | ||
169 | + */ | ||
170 | +static void kvm_arm_its_post_load(GICv3ITSState *s) | ||
171 | +{ | ||
172 | + int i; | ||
173 | + | ||
174 | + if (!s->iidr) { | ||
175 | + return; | ||
176 | + } | ||
177 | + | ||
178 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
179 | + GITS_IIDR, &s->iidr, true, &error_abort); | ||
180 | + | ||
181 | + /* | ||
182 | + * must be written before GITS_CREADR since GITS_CBASER write | ||
183 | + * access resets GITS_CREADR. | ||
184 | + */ | ||
185 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
186 | + GITS_CBASER, &s->cbaser, true, &error_abort); | ||
187 | + | ||
188 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
189 | + GITS_CREADR, &s->creadr, true, &error_abort); | ||
190 | + | ||
191 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
192 | + GITS_CWRITER, &s->cwriter, true, &error_abort); | ||
193 | + | ||
194 | + | ||
195 | + for (i = 0; i < 8; i++) { | ||
196 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
197 | + GITS_BASER + i * 8, &s->baser[i], true, | ||
198 | + &error_abort); | ||
199 | + } | ||
200 | + | ||
201 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
202 | + KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true, | ||
203 | + &error_abort); | ||
204 | + | ||
205 | + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
206 | + GITS_CTLR, &s->ctlr, true, &error_abort); | ||
207 | +} | ||
208 | + | ||
209 | static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | ||
210 | { | 124 | { |
211 | DeviceClass *dc = DEVICE_CLASS(klass); | 125 | /* Two registers and a scalar, using gvec */ |
212 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | 126 | int vec_size = a->q ? 16 : 8; |
213 | 127 | - int rd_ofs = neon_reg_offset(a->vd, 0); | |
214 | dc->realize = kvm_arm_its_realize; | 128 | - int rn_ofs = neon_reg_offset(a->vn, 0); |
215 | icc->send_msi = kvm_its_send_msi; | 129 | + int rd_ofs = neon_full_reg_offset(a->vd); |
216 | + icc->pre_save = kvm_arm_its_pre_save; | 130 | + int rn_ofs = neon_full_reg_offset(a->vn); |
217 | + icc->post_load = kvm_arm_its_post_load; | 131 | int rm_ofs; |
218 | } | 132 | int idx; |
219 | 133 | TCGv_ptr fpstatus; | |
220 | static const TypeInfo kvm_arm_its_info = { | 134 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, |
135 | /* a->vm is M:Vm, which encodes both register and index */ | ||
136 | idx = extract32(a->vm, a->size + 2, 2); | ||
137 | a->vm = extract32(a->vm, 0, a->size + 2); | ||
138 | - rm_ofs = neon_reg_offset(a->vm, 0); | ||
139 | + rm_ofs = neon_full_reg_offset(a->vm); | ||
140 | |||
141 | fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD); | ||
142 | tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus, | ||
143 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
144 | return true; | ||
145 | } | ||
146 | |||
147 | - tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), | ||
148 | + tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd), | ||
149 | neon_element_offset(a->vm, a->index, a->size), | ||
150 | a->q ? 16 : 8, a->q ? 16 : 8); | ||
151 | return true; | ||
152 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
153 | static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) | ||
154 | { | ||
155 | int vec_size = a->q ? 16 : 8; | ||
156 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
157 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
158 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
159 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
160 | |||
161 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
162 | return false; | ||
163 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/target/arm/translate-vfp.c.inc | ||
166 | +++ b/target/arm/translate-vfp.c.inc | ||
167 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
168 | } | ||
169 | |||
170 | tmp = load_reg(s, a->rt); | ||
171 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), | ||
172 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn), | ||
173 | vec_size, vec_size, tmp); | ||
174 | tcg_temp_free_i32(tmp); | ||
175 | |||
221 | -- | 176 | -- |
222 | 2.7.4 | 177 | 2.20.1 |
223 | 178 | ||
224 | 179 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | On all Exynos-based boards, the system powers down itself by driving | 3 | This will shortly have users outside of translate-neon.c.inc. |
4 | PS_HOLD signal low - eight bit in PS_HOLD_CONTROL register of PMU. | ||
5 | Handle writing to respective PMU register to fix power off failure: | ||
6 | 4 | ||
7 | reboot: Power down | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Unable to poweroff system | 6 | Message-id: 20201030022618.785675-3-richard.henderson@linaro.org |
9 | shutdown: 31 output lines suppressed due to ratelimiting | ||
10 | Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000000 | ||
11 | |||
12 | CPU: 0 PID: 1 Comm: shutdown Not tainted 4.11.0-rc8 #846 | ||
13 | Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) | ||
14 | [<c031050c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14) | ||
15 | [<c030ba6c>] (show_stack) from [<c05b2800>] (dump_stack+0x88/0x9c) | ||
16 | [<c05b2800>] (dump_stack) from [<c03d3140>] (panic+0xdc/0x268) | ||
17 | [<c03d3140>] (panic) from [<c0343614>] (do_exit+0xa90/0xab4) | ||
18 | [<c0343614>] (do_exit) from [<c035f2dc>] (SyS_reboot+0x164/0x1d0) | ||
19 | [<c035f2dc>] (SyS_reboot) from [<c0307c80>] (ret_fast_syscall+0x0/0x3c) | ||
20 | |||
21 | Additionally the initial value of PS_HOLD has to be changed because | ||
22 | recent Linux kernel (v4.12-rc1) uses regmap cache for this access. | ||
23 | When the register is kept at reset value, the kernel will not issue a | ||
24 | write to it. Usually the bootloader sets the eight bit of PS_HOLD high | ||
25 | so mimic its existence here. | ||
26 | |||
27 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | ||
28 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
29 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | --- | 9 | --- |
32 | hw/misc/exynos4210_pmu.c | 20 +++++++++++++++++++- | 10 | target/arm/translate.c | 20 ++++++++++++++++++++ |
33 | 1 file changed, 19 insertions(+), 1 deletion(-) | 11 | target/arm/translate-neon.c.inc | 19 ------------------- |
12 | 2 files changed, 20 insertions(+), 19 deletions(-) | ||
34 | 13 | ||
35 | diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
36 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/hw/misc/exynos4210_pmu.c | 16 | --- a/target/arm/translate.c |
38 | +++ b/hw/misc/exynos4210_pmu.c | 17 | +++ b/target/arm/translate.c |
39 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg) |
40 | 19 | return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | |
41 | #include "qemu/osdep.h" | 20 | } |
42 | #include "hw/sysbus.h" | 21 | |
43 | +#include "sysemu/sysemu.h" | 22 | +/* |
44 | 23 | + * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | |
45 | #ifndef DEBUG_PMU | 24 | + * where 0 is the least significant end of the register. |
46 | #define DEBUG_PMU 0 | 25 | + */ |
47 | @@ -XXX,XX +XXX,XX @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = { | 26 | +static long neon_element_offset(int reg, int element, MemOp size) |
48 | {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000}, | 27 | +{ |
49 | {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000}, | 28 | + int element_size = 1 << size; |
50 | {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000}, | 29 | + int ofs = element * element_size; |
51 | - {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200}, | 30 | +#ifdef HOST_WORDS_BIGENDIAN |
52 | + /* | 31 | + /* |
53 | + * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit. | 32 | + * Calculate the offset assuming fully little-endian, |
54 | + * DATA bit high, set usually by bootloader, keeps system on. | 33 | + * then XOR to account for the order of the 8-byte units. |
55 | + */ | 34 | + */ |
56 | + {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)}, | 35 | + if (element_size < 8) { |
57 | {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001}, | 36 | + ofs ^= 8 - element_size; |
58 | {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001}, | 37 | + } |
59 | {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000}, | 38 | +#endif |
60 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210PmuState { | 39 | + return neon_full_reg_offset(reg) + ofs; |
61 | uint32_t reg[PMU_NUM_OF_REGISTERS]; | ||
62 | } Exynos4210PmuState; | ||
63 | |||
64 | +static void exynos4210_pmu_poweroff(void) | ||
65 | +{ | ||
66 | + PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n"); | ||
67 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | ||
68 | +} | 40 | +} |
69 | + | 41 | + |
70 | static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset, | 42 | static inline long vfp_reg_offset(bool dp, unsigned reg) |
71 | unsigned size) | ||
72 | { | 43 | { |
73 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset, | 44 | if (dp) { |
74 | PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name, | 45 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
75 | (uint32_t)offset, (uint32_t)val); | 46 | index XXXXXXX..XXXXXXX 100644 |
76 | s->reg[i] = val; | 47 | --- a/target/arm/translate-neon.c.inc |
77 | + if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) { | 48 | +++ b/target/arm/translate-neon.c.inc |
78 | + /* | 49 | @@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x) |
79 | + * We are interested only in setting data bit | 50 | #include "decode-neon-ls.c.inc" |
80 | + * of PS_HOLD_CONTROL register to indicate power off request. | 51 | #include "decode-neon-shared.c.inc" |
81 | + */ | 52 | |
82 | + exynos4210_pmu_poweroff(); | 53 | -/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, |
83 | + } | 54 | - * where 0 is the least significant end of the register. |
84 | return; | 55 | - */ |
85 | } | 56 | -static inline long |
86 | reg_p++; | 57 | -neon_element_offset(int reg, int element, MemOp size) |
58 | -{ | ||
59 | - int element_size = 1 << size; | ||
60 | - int ofs = element * element_size; | ||
61 | -#ifdef HOST_WORDS_BIGENDIAN | ||
62 | - /* Calculate the offset assuming fully little-endian, | ||
63 | - * then XOR to account for the order of the 8-byte units. | ||
64 | - */ | ||
65 | - if (element_size < 8) { | ||
66 | - ofs ^= 8 - element_size; | ||
67 | - } | ||
68 | -#endif | ||
69 | - return neon_full_reg_offset(reg) + ofs; | ||
70 | -} | ||
71 | - | ||
72 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | ||
73 | { | ||
74 | long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | ||
87 | -- | 75 | -- |
88 | 2.7.4 | 76 | 2.20.1 |
89 | 77 | ||
90 | 78 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Before QOM-ifying the Exynos4 SoC model, move the DRAM initialization | 3 | These are the only users of neon_reg_offset, so remove that. |
4 | from exynos4210.c to exynos4_boards.c because DRAM is board specific, | ||
5 | not SoC. | ||
6 | 4 | ||
7 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Message-id: 20201030022618.785675-4-richard.henderson@linaro.org |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | include/hw/arm/exynos4210.h | 5 +---- | 10 | target/arm/translate.c | 14 ++------------ |
12 | hw/arm/exynos4210.c | 20 +----------------- | 11 | 1 file changed, 2 insertions(+), 12 deletions(-) |
13 | hw/arm/exynos4_boards.c | 50 ++++++++++++++++++++++++++++++++++++++------- | ||
14 | 3 files changed, 45 insertions(+), 30 deletions(-) | ||
15 | 12 | ||
16 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 13 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
17 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/exynos4210.h | 15 | --- a/target/arm/translate.c |
19 | +++ b/include/hw/arm/exynos4210.h | 16 | +++ b/target/arm/translate.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State { | 17 | @@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg) |
21 | MemoryRegion iram_mem; | ||
22 | MemoryRegion irom_mem; | ||
23 | MemoryRegion irom_alias_mem; | ||
24 | - MemoryRegion dram0_mem; | ||
25 | - MemoryRegion dram1_mem; | ||
26 | MemoryRegion boot_secondary; | ||
27 | MemoryRegion bootreg_mem; | ||
28 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | ||
29 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State { | ||
30 | void exynos4210_write_secondary(ARMCPU *cpu, | ||
31 | const struct arm_boot_info *info); | ||
32 | |||
33 | -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | ||
34 | - unsigned long ram_size); | ||
35 | +Exynos4210State *exynos4210_init(MemoryRegion *system_mem); | ||
36 | |||
37 | /* Initialize exynos4210 IRQ subsystem stub */ | ||
38 | qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); | ||
39 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/hw/arm/exynos4210.c | ||
42 | +++ b/hw/arm/exynos4210.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu) | ||
44 | return mp_affinity; | ||
45 | } | ||
46 | |||
47 | -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | ||
48 | - unsigned long ram_size) | ||
49 | +Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | ||
50 | { | ||
51 | int i, n; | ||
52 | Exynos4210State *s = g_new(Exynos4210State, 1); | ||
53 | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | ||
54 | - unsigned long mem_size; | ||
55 | DeviceState *dev; | ||
56 | SysBusDevice *busdev; | ||
57 | ObjectClass *cpu_oc; | ||
58 | @@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, | ||
59 | memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, | ||
60 | &s->iram_mem); | ||
61 | |||
62 | - /* DRAM */ | ||
63 | - mem_size = ram_size; | ||
64 | - if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { | ||
65 | - memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", | ||
66 | - mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); | ||
67 | - vmstate_register_ram_global(&s->dram1_mem); | ||
68 | - memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, | ||
69 | - &s->dram1_mem); | ||
70 | - mem_size = EXYNOS4210_DRAM_MAX_SIZE; | ||
71 | - } | ||
72 | - memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, | ||
73 | - &error_fatal); | ||
74 | - vmstate_register_ram_global(&s->dram0_mem); | ||
75 | - memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, | ||
76 | - &s->dram0_mem); | ||
77 | - | ||
78 | /* PMU. | ||
79 | * The only reason of existence at the moment is that secondary CPU boot | ||
80 | * loader uses PMU INFORM5 register as a holding pen. | ||
81 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/hw/arm/exynos4_boards.c | ||
84 | +++ b/hw/arm/exynos4_boards.c | ||
85 | @@ -XXX,XX +XXX,XX @@ | ||
86 | */ | ||
87 | |||
88 | #include "qemu/osdep.h" | ||
89 | +#include "qapi/error.h" | ||
90 | #include "qemu/error-report.h" | ||
91 | #include "qemu-common.h" | ||
92 | #include "cpu.h" | ||
93 | @@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType { | ||
94 | EXYNOS4_NUM_OF_BOARDS | ||
95 | } Exynos4BoardType; | ||
96 | |||
97 | +typedef struct Exynos4BoardState { | ||
98 | + Exynos4210State *soc; | ||
99 | + MemoryRegion dram0_mem; | ||
100 | + MemoryRegion dram1_mem; | ||
101 | +} Exynos4BoardState; | ||
102 | + | ||
103 | static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = { | ||
104 | [EXYNOS4_BOARD_NURI] = 0xD33, | ||
105 | [EXYNOS4_BOARD_SMDKC210] = 0xB16, | ||
106 | @@ -XXX,XX +XXX,XX @@ static void lan9215_init(uint32_t base, qemu_irq irq) | ||
107 | } | 18 | } |
108 | } | 19 | } |
109 | 20 | ||
110 | -static Exynos4210State *exynos4_boards_init_common(MachineState *machine, | 21 | -/* Return the offset of a 32-bit piece of a NEON register. |
111 | - Exynos4BoardType board_type) | 22 | - zero is the least significant end of the register. */ |
112 | +static void exynos4_boards_init_ram(Exynos4BoardState *s, | 23 | -static inline long |
113 | + MemoryRegion *system_mem, | 24 | -neon_reg_offset (int reg, int n) |
114 | + unsigned long ram_size) | 25 | -{ |
115 | +{ | 26 | - int sreg; |
116 | + unsigned long mem_size = ram_size; | 27 | - sreg = reg * 2 + n; |
117 | + | 28 | - return vfp_reg_offset(0, sreg); |
118 | + if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { | 29 | -} |
119 | + memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", | 30 | - |
120 | + mem_size - EXYNOS4210_DRAM_MAX_SIZE, | 31 | static TCGv_i32 neon_load_reg(int reg, int pass) |
121 | + &error_fatal); | ||
122 | + vmstate_register_ram_global(&s->dram1_mem); | ||
123 | + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, | ||
124 | + &s->dram1_mem); | ||
125 | + mem_size = EXYNOS4210_DRAM_MAX_SIZE; | ||
126 | + } | ||
127 | + | ||
128 | + memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, | ||
129 | + &error_fatal); | ||
130 | + vmstate_register_ram_global(&s->dram0_mem); | ||
131 | + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, | ||
132 | + &s->dram0_mem); | ||
133 | +} | ||
134 | + | ||
135 | +static Exynos4BoardState * | ||
136 | +exynos4_boards_init_common(MachineState *machine, | ||
137 | + Exynos4BoardType board_type) | ||
138 | { | 32 | { |
139 | + Exynos4BoardState *s = g_new(Exynos4BoardState, 1); | 33 | TCGv_i32 tmp = tcg_temp_new_i32(); |
140 | MachineClass *mc = MACHINE_GET_CLASS(machine); | 34 | - tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); |
141 | 35 | + tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); | |
142 | if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) { | 36 | return tmp; |
143 | @@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine, | ||
144 | machine->kernel_cmdline, | ||
145 | machine->initrd_filename); | ||
146 | |||
147 | - return exynos4210_init(get_system_memory(), | ||
148 | - exynos4_board_ram_size[board_type]); | ||
149 | + exynos4_boards_init_ram(s, get_system_memory(), | ||
150 | + exynos4_board_ram_size[board_type]); | ||
151 | + | ||
152 | + s->soc = exynos4210_init(get_system_memory()); | ||
153 | + | ||
154 | + return s; | ||
155 | } | 37 | } |
156 | 38 | ||
157 | static void nuri_init(MachineState *machine) | 39 | static void neon_store_reg(int reg, int pass, TCGv_i32 var) |
158 | @@ -XXX,XX +XXX,XX @@ static void nuri_init(MachineState *machine) | ||
159 | |||
160 | static void smdkc210_init(MachineState *machine) | ||
161 | { | 40 | { |
162 | - Exynos4210State *s = exynos4_boards_init_common(machine, | 41 | - tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); |
163 | - EXYNOS4_BOARD_SMDKC210); | 42 | + tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); |
164 | + Exynos4BoardState *s = exynos4_boards_init_common(machine, | 43 | tcg_temp_free_i32(var); |
165 | + EXYNOS4_BOARD_SMDKC210); | ||
166 | |||
167 | lan9215_init(SMDK_LAN9118_BASE_ADDR, | ||
168 | - qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)])); | ||
169 | + qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)])); | ||
170 | arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo); | ||
171 | } | 44 | } |
172 | 45 | ||
173 | -- | 46 | -- |
174 | 2.7.4 | 47 | 2.20.1 |
175 | 48 | ||
176 | 49 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We change the restoration priority of both the GICv3 and ITS. The | 3 | This seems a bit more readable than using offsetof CPU_DoubleU. |
4 | GICv3 must be restored before the ITS and the ITS needs to be restored | ||
5 | before PCIe devices since it translates their MSI transactions. | ||
6 | 4 | ||
7 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Juan Quintela <quintela@redhat.com> | 6 | Message-id: 20201030022618.785675-5-richard.henderson@linaro.org |
9 | Message-id: 1497023553-18411-5-git-send-email-eric.auger@redhat.com | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 9 | --- |
12 | include/migration/vmstate.h | 2 ++ | 10 | target/arm/translate.c | 13 ++++--------- |
13 | hw/intc/arm_gicv3_common.c | 1 + | 11 | 1 file changed, 4 insertions(+), 9 deletions(-) |
14 | hw/intc/arm_gicv3_its_common.c | 2 +- | ||
15 | hw/intc/arm_gicv3_its_kvm.c | 24 ++++++++++++------------ | ||
16 | 4 files changed, 16 insertions(+), 13 deletions(-) | ||
17 | 12 | ||
18 | diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h | 13 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
19 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/migration/vmstate.h | 15 | --- a/target/arm/translate.c |
21 | +++ b/include/migration/vmstate.h | 16 | +++ b/target/arm/translate.c |
22 | @@ -XXX,XX +XXX,XX @@ enum VMStateFlags { | 17 | @@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size) |
23 | typedef enum { | 18 | return neon_full_reg_offset(reg) + ofs; |
24 | MIG_PRI_DEFAULT = 0, | 19 | } |
25 | MIG_PRI_IOMMU, /* Must happen before PCI devices */ | 20 | |
26 | + MIG_PRI_GICV3_ITS, /* Must happen before PCI devices */ | 21 | -static inline long vfp_reg_offset(bool dp, unsigned reg) |
27 | + MIG_PRI_GICV3, /* Must happen before the ITS */ | 22 | +/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */ |
28 | MIG_PRI_MAX, | 23 | +static long vfp_reg_offset(bool dp, unsigned reg) |
29 | } MigrationPriority; | 24 | { |
30 | 25 | if (dp) { | |
31 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | 26 | - return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); |
32 | index XXXXXXX..XXXXXXX 100644 | 27 | + return neon_element_offset(reg, 0, MO_64); |
33 | --- a/hw/intc/arm_gicv3_common.c | 28 | } else { |
34 | +++ b/hw/intc/arm_gicv3_common.c | 29 | - long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]); |
35 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = { | 30 | - if (reg & 1) { |
36 | .minimum_version_id = 1, | 31 | - ofs += offsetof(CPU_DoubleU, l.upper); |
37 | .pre_save = gicv3_pre_save, | 32 | - } else { |
38 | .post_load = gicv3_post_load, | 33 | - ofs += offsetof(CPU_DoubleU, l.lower); |
39 | + .priority = MIG_PRI_GICV3, | 34 | - } |
40 | .fields = (VMStateField[]) { | 35 | - return ofs; |
41 | VMSTATE_UINT32(gicd_ctlr, GICv3State), | 36 | + return neon_element_offset(reg >> 1, reg & 1, MO_32); |
42 | VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), | 37 | } |
43 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | 38 | } |
44 | index XXXXXXX..XXXXXXX 100644 | 39 | |
45 | --- a/hw/intc/arm_gicv3_its_common.c | ||
46 | +++ b/hw/intc/arm_gicv3_its_common.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = { | ||
48 | .name = "arm_gicv3_its", | ||
49 | .pre_save = gicv3_its_pre_save, | ||
50 | .post_load = gicv3_its_post_load, | ||
51 | - .unmigratable = true, | ||
52 | + .priority = MIG_PRI_GICV3_ITS, | ||
53 | .fields = (VMStateField[]) { | ||
54 | VMSTATE_UINT32(ctlr, GICv3ITSState), | ||
55 | VMSTATE_UINT32(iidr, GICv3ITSState), | ||
56 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
59 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
61 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | ||
62 | Error *local_err = NULL; | ||
63 | |||
64 | - /* | ||
65 | - * Block migration of a KVM GICv3 ITS device: the API for saving and | ||
66 | - * restoring the state in the kernel is not yet available | ||
67 | - */ | ||
68 | - error_setg(&s->migration_blocker, "vITS migration is not implemented"); | ||
69 | - migrate_add_blocker(s->migration_blocker, &local_err); | ||
70 | - if (local_err) { | ||
71 | - error_propagate(errp, local_err); | ||
72 | - error_free(s->migration_blocker); | ||
73 | - return; | ||
74 | - } | ||
75 | - | ||
76 | s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false); | ||
77 | if (s->dev_fd < 0) { | ||
78 | error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS"); | ||
79 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
80 | |||
81 | gicv3_its_init_mmio(s, NULL); | ||
82 | |||
83 | + if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | ||
84 | + GITS_CTLR)) { | ||
85 | + error_setg(&s->migration_blocker, "This operating system kernel " | ||
86 | + "does not support vITS migration"); | ||
87 | + migrate_add_blocker(s->migration_blocker, &local_err); | ||
88 | + if (local_err) { | ||
89 | + error_propagate(errp, local_err); | ||
90 | + error_free(s->migration_blocker); | ||
91 | + return; | ||
92 | + } | ||
93 | + } | ||
94 | + | ||
95 | kvm_msi_use_devid = true; | ||
96 | kvm_gsi_direct_mapping = false; | ||
97 | kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); | ||
98 | -- | 40 | -- |
99 | 2.7.4 | 41 | 2.20.1 |
100 | 42 | ||
101 | 43 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Largely inspired by the TMP105 temperature sensor, here is a model for | 3 | Model these off the aa64 read/write_vec_element functions. |
4 | the TMP42{1,2,3} temperature sensors. | 4 | Use it within translate-neon.c.inc. The new functions do |
5 | not allocate or free temps, so this rearranges the calling | ||
6 | code a bit. | ||
5 | 7 | ||
6 | Specs can be found here : | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20201030022618.785675-6-richard.henderson@linaro.org | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/translate.c | 26 ++++ | ||
14 | target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------ | ||
15 | 2 files changed, 183 insertions(+), 99 deletions(-) | ||
7 | 16 | ||
8 | http://www.ti.com/lit/gpn/tmp421 | 17 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
9 | |||
10 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
11 | Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/misc/Makefile.objs | 1 + | ||
16 | hw/misc/tmp421.c | 402 ++++++++++++++++++++++++++++++++++++++++ | ||
17 | default-configs/arm-softmmu.mak | 1 + | ||
18 | 3 files changed, 404 insertions(+) | ||
19 | create mode 100644 hw/misc/tmp421.c | ||
20 | |||
21 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
22 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/misc/Makefile.objs | 19 | --- a/target/arm/translate.c |
24 | +++ b/hw/misc/Makefile.objs | 20 | +++ b/target/arm/translate.c |
25 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg) |
26 | common-obj-$(CONFIG_APPLESMC) += applesmc.o | 22 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); |
27 | common-obj-$(CONFIG_MAX111X) += max111x.o | 23 | } |
28 | common-obj-$(CONFIG_TMP105) += tmp105.o | 24 | |
29 | +common-obj-$(CONFIG_TMP421) += tmp421.o | 25 | +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) |
30 | common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o | ||
31 | common-obj-$(CONFIG_SGA) += sga.o | ||
32 | common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o | ||
33 | diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c | ||
34 | new file mode 100644 | ||
35 | index XXXXXXX..XXXXXXX | ||
36 | --- /dev/null | ||
37 | +++ b/hw/misc/tmp421.c | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | +/* | ||
40 | + * Texas Instruments TMP421 temperature sensor. | ||
41 | + * | ||
42 | + * Copyright (c) 2016 IBM Corporation. | ||
43 | + * | ||
44 | + * Largely inspired by : | ||
45 | + * | ||
46 | + * Texas Instruments TMP105 temperature sensor. | ||
47 | + * | ||
48 | + * Copyright (C) 2008 Nokia Corporation | ||
49 | + * Written by Andrzej Zaborowski <andrew@openedhand.com> | ||
50 | + * | ||
51 | + * This program is free software; you can redistribute it and/or | ||
52 | + * modify it under the terms of the GNU General Public License as | ||
53 | + * published by the Free Software Foundation; either version 2 or | ||
54 | + * (at your option) version 3 of the License. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
59 | + * GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | ||
64 | + | ||
65 | +#include "qemu/osdep.h" | ||
66 | +#include "hw/hw.h" | ||
67 | +#include "hw/i2c/i2c.h" | ||
68 | +#include "qapi/error.h" | ||
69 | +#include "qapi/visitor.h" | ||
70 | + | ||
71 | +/* Manufacturer / Device ID's */ | ||
72 | +#define TMP421_MANUFACTURER_ID 0x55 | ||
73 | +#define TMP421_DEVICE_ID 0x21 | ||
74 | +#define TMP422_DEVICE_ID 0x22 | ||
75 | +#define TMP423_DEVICE_ID 0x23 | ||
76 | + | ||
77 | +typedef struct DeviceInfo { | ||
78 | + int model; | ||
79 | + const char *name; | ||
80 | +} DeviceInfo; | ||
81 | + | ||
82 | +static const DeviceInfo devices[] = { | ||
83 | + { TMP421_DEVICE_ID, "tmp421" }, | ||
84 | + { TMP422_DEVICE_ID, "tmp422" }, | ||
85 | + { TMP423_DEVICE_ID, "tmp423" }, | ||
86 | +}; | ||
87 | + | ||
88 | +typedef struct TMP421State { | ||
89 | + /*< private >*/ | ||
90 | + I2CSlave i2c; | ||
91 | + /*< public >*/ | ||
92 | + | ||
93 | + int16_t temperature[4]; | ||
94 | + | ||
95 | + uint8_t status; | ||
96 | + uint8_t config[2]; | ||
97 | + uint8_t rate; | ||
98 | + | ||
99 | + uint8_t len; | ||
100 | + uint8_t buf[2]; | ||
101 | + uint8_t pointer; | ||
102 | + | ||
103 | +} TMP421State; | ||
104 | + | ||
105 | +typedef struct TMP421Class { | ||
106 | + I2CSlaveClass parent_class; | ||
107 | + DeviceInfo *dev; | ||
108 | +} TMP421Class; | ||
109 | + | ||
110 | +#define TYPE_TMP421 "tmp421-generic" | ||
111 | +#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421) | ||
112 | + | ||
113 | +#define TMP421_CLASS(klass) \ | ||
114 | + OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421) | ||
115 | +#define TMP421_GET_CLASS(obj) \ | ||
116 | + OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421) | ||
117 | + | ||
118 | +/* the TMP421 registers */ | ||
119 | +#define TMP421_STATUS_REG 0x08 | ||
120 | +#define TMP421_STATUS_BUSY (1 << 7) | ||
121 | +#define TMP421_CONFIG_REG_1 0x09 | ||
122 | +#define TMP421_CONFIG_RANGE (1 << 2) | ||
123 | +#define TMP421_CONFIG_SHUTDOWN (1 << 6) | ||
124 | +#define TMP421_CONFIG_REG_2 0x0A | ||
125 | +#define TMP421_CONFIG_RC (1 << 2) | ||
126 | +#define TMP421_CONFIG_LEN (1 << 3) | ||
127 | +#define TMP421_CONFIG_REN (1 << 4) | ||
128 | +#define TMP421_CONFIG_REN2 (1 << 5) | ||
129 | +#define TMP421_CONFIG_REN3 (1 << 6) | ||
130 | + | ||
131 | +#define TMP421_CONVERSION_RATE_REG 0x0B | ||
132 | +#define TMP421_ONE_SHOT 0x0F | ||
133 | + | ||
134 | +#define TMP421_RESET 0xFC | ||
135 | +#define TMP421_MANUFACTURER_ID_REG 0xFE | ||
136 | +#define TMP421_DEVICE_ID_REG 0xFF | ||
137 | + | ||
138 | +#define TMP421_TEMP_MSB0 0x00 | ||
139 | +#define TMP421_TEMP_MSB1 0x01 | ||
140 | +#define TMP421_TEMP_MSB2 0x02 | ||
141 | +#define TMP421_TEMP_MSB3 0x03 | ||
142 | +#define TMP421_TEMP_LSB0 0x10 | ||
143 | +#define TMP421_TEMP_LSB1 0x11 | ||
144 | +#define TMP421_TEMP_LSB2 0x12 | ||
145 | +#define TMP421_TEMP_LSB3 0x13 | ||
146 | + | ||
147 | +static const int32_t mins[2] = { -40000, -55000 }; | ||
148 | +static const int32_t maxs[2] = { 127000, 150000 }; | ||
149 | + | ||
150 | +static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name, | ||
151 | + void *opaque, Error **errp) | ||
152 | +{ | 26 | +{ |
153 | + TMP421State *s = TMP421(obj); | 27 | + long off = neon_element_offset(reg, ele, size); |
154 | + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); | 28 | + |
155 | + int offset = ext_range * 64 * 256; | 29 | + switch (size) { |
156 | + int64_t value; | 30 | + case MO_32: |
157 | + int tempid; | 31 | + tcg_gen_ld_i32(dest, cpu_env, off); |
158 | + | ||
159 | + if (sscanf(name, "temperature%d", &tempid) != 1) { | ||
160 | + error_setg(errp, "error reading %s: %m", name); | ||
161 | + return; | ||
162 | + } | ||
163 | + | ||
164 | + if (tempid >= 4 || tempid < 0) { | ||
165 | + error_setg(errp, "error reading %s", name); | ||
166 | + return; | ||
167 | + } | ||
168 | + | ||
169 | + value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256; | ||
170 | + | ||
171 | + visit_type_int(v, name, &value, errp); | ||
172 | +} | ||
173 | + | ||
174 | +/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8 | ||
175 | + * fixed point, so units are 1/256 centigrades. A simple ratio will do. | ||
176 | + */ | ||
177 | +static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name, | ||
178 | + void *opaque, Error **errp) | ||
179 | +{ | ||
180 | + TMP421State *s = TMP421(obj); | ||
181 | + Error *local_err = NULL; | ||
182 | + int64_t temp; | ||
183 | + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); | ||
184 | + int offset = ext_range * 64 * 256; | ||
185 | + int tempid; | ||
186 | + | ||
187 | + visit_type_int(v, name, &temp, &local_err); | ||
188 | + if (local_err) { | ||
189 | + error_propagate(errp, local_err); | ||
190 | + return; | ||
191 | + } | ||
192 | + | ||
193 | + if (temp >= maxs[ext_range] || temp < mins[ext_range]) { | ||
194 | + error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range", | ||
195 | + temp / 1000, temp % 1000); | ||
196 | + return; | ||
197 | + } | ||
198 | + | ||
199 | + if (sscanf(name, "temperature%d", &tempid) != 1) { | ||
200 | + error_setg(errp, "error reading %s: %m", name); | ||
201 | + return; | ||
202 | + } | ||
203 | + | ||
204 | + if (tempid >= 4 || tempid < 0) { | ||
205 | + error_setg(errp, "error reading %s", name); | ||
206 | + return; | ||
207 | + } | ||
208 | + | ||
209 | + s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset; | ||
210 | +} | ||
211 | + | ||
212 | +static void tmp421_read(TMP421State *s) | ||
213 | +{ | ||
214 | + TMP421Class *sc = TMP421_GET_CLASS(s); | ||
215 | + | ||
216 | + s->len = 0; | ||
217 | + | ||
218 | + switch (s->pointer) { | ||
219 | + case TMP421_MANUFACTURER_ID_REG: | ||
220 | + s->buf[s->len++] = TMP421_MANUFACTURER_ID; | ||
221 | + break; | 32 | + break; |
222 | + case TMP421_DEVICE_ID_REG: | 33 | + default: |
223 | + s->buf[s->len++] = sc->dev->model; | 34 | + g_assert_not_reached(); |
224 | + break; | ||
225 | + case TMP421_CONFIG_REG_1: | ||
226 | + s->buf[s->len++] = s->config[0]; | ||
227 | + break; | ||
228 | + case TMP421_CONFIG_REG_2: | ||
229 | + s->buf[s->len++] = s->config[1]; | ||
230 | + break; | ||
231 | + case TMP421_CONVERSION_RATE_REG: | ||
232 | + s->buf[s->len++] = s->rate; | ||
233 | + break; | ||
234 | + case TMP421_STATUS_REG: | ||
235 | + s->buf[s->len++] = s->status; | ||
236 | + break; | ||
237 | + | ||
238 | + /* FIXME: check for channel enablement in config registers */ | ||
239 | + case TMP421_TEMP_MSB0: | ||
240 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8); | ||
241 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; | ||
242 | + break; | ||
243 | + case TMP421_TEMP_MSB1: | ||
244 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8); | ||
245 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; | ||
246 | + break; | ||
247 | + case TMP421_TEMP_MSB2: | ||
248 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8); | ||
249 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; | ||
250 | + break; | ||
251 | + case TMP421_TEMP_MSB3: | ||
252 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8); | ||
253 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; | ||
254 | + break; | ||
255 | + case TMP421_TEMP_LSB0: | ||
256 | + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; | ||
257 | + break; | ||
258 | + case TMP421_TEMP_LSB1: | ||
259 | + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; | ||
260 | + break; | ||
261 | + case TMP421_TEMP_LSB2: | ||
262 | + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; | ||
263 | + break; | ||
264 | + case TMP421_TEMP_LSB3: | ||
265 | + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; | ||
266 | + break; | ||
267 | + } | 35 | + } |
268 | +} | 36 | +} |
269 | + | 37 | + |
270 | +static void tmp421_reset(I2CSlave *i2c); | 38 | +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size) |
271 | + | ||
272 | +static void tmp421_write(TMP421State *s) | ||
273 | +{ | 39 | +{ |
274 | + switch (s->pointer) { | 40 | + long off = neon_element_offset(reg, ele, size); |
275 | + case TMP421_CONVERSION_RATE_REG: | 41 | + |
276 | + s->rate = s->buf[0]; | 42 | + switch (size) { |
43 | + case MO_32: | ||
44 | + tcg_gen_st_i32(src, cpu_env, off); | ||
277 | + break; | 45 | + break; |
278 | + case TMP421_CONFIG_REG_1: | 46 | + default: |
279 | + s->config[0] = s->buf[0]; | 47 | + g_assert_not_reached(); |
280 | + break; | ||
281 | + case TMP421_CONFIG_REG_2: | ||
282 | + s->config[1] = s->buf[0]; | ||
283 | + break; | ||
284 | + case TMP421_RESET: | ||
285 | + tmp421_reset(I2C_SLAVE(s)); | ||
286 | + break; | ||
287 | + } | 48 | + } |
288 | +} | 49 | +} |
289 | + | 50 | + |
290 | +static int tmp421_rx(I2CSlave *i2c) | 51 | static TCGv_ptr vfp_reg_ptr(bool dp, int reg) |
291 | +{ | 52 | { |
292 | + TMP421State *s = TMP421(i2c); | 53 | TCGv_ptr ret = tcg_temp_new_ptr(); |
293 | + | 54 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
294 | + if (s->len < 2) { | ||
295 | + return s->buf[s->len++]; | ||
296 | + } else { | ||
297 | + return 0xff; | ||
298 | + } | ||
299 | +} | ||
300 | + | ||
301 | +static int tmp421_tx(I2CSlave *i2c, uint8_t data) | ||
302 | +{ | ||
303 | + TMP421State *s = TMP421(i2c); | ||
304 | + | ||
305 | + if (s->len == 0) { | ||
306 | + /* first byte is the register pointer for a read or write | ||
307 | + * operation */ | ||
308 | + s->pointer = data; | ||
309 | + s->len++; | ||
310 | + } else if (s->len == 1) { | ||
311 | + /* second byte is the data to write. The device only supports | ||
312 | + * one byte writes */ | ||
313 | + s->buf[0] = data; | ||
314 | + tmp421_write(s); | ||
315 | + } | ||
316 | + | ||
317 | + return 0; | ||
318 | +} | ||
319 | + | ||
320 | +static int tmp421_event(I2CSlave *i2c, enum i2c_event event) | ||
321 | +{ | ||
322 | + TMP421State *s = TMP421(i2c); | ||
323 | + | ||
324 | + if (event == I2C_START_RECV) { | ||
325 | + tmp421_read(s); | ||
326 | + } | ||
327 | + | ||
328 | + s->len = 0; | ||
329 | + return 0; | ||
330 | +} | ||
331 | + | ||
332 | +static const VMStateDescription vmstate_tmp421 = { | ||
333 | + .name = "TMP421", | ||
334 | + .version_id = 0, | ||
335 | + .minimum_version_id = 0, | ||
336 | + .fields = (VMStateField[]) { | ||
337 | + VMSTATE_UINT8(len, TMP421State), | ||
338 | + VMSTATE_UINT8_ARRAY(buf, TMP421State, 2), | ||
339 | + VMSTATE_UINT8(pointer, TMP421State), | ||
340 | + VMSTATE_UINT8_ARRAY(config, TMP421State, 2), | ||
341 | + VMSTATE_UINT8(status, TMP421State), | ||
342 | + VMSTATE_UINT8(rate, TMP421State), | ||
343 | + VMSTATE_INT16_ARRAY(temperature, TMP421State, 4), | ||
344 | + VMSTATE_I2C_SLAVE(i2c, TMP421State), | ||
345 | + VMSTATE_END_OF_LIST() | ||
346 | + } | ||
347 | +}; | ||
348 | + | ||
349 | +static void tmp421_reset(I2CSlave *i2c) | ||
350 | +{ | ||
351 | + TMP421State *s = TMP421(i2c); | ||
352 | + TMP421Class *sc = TMP421_GET_CLASS(s); | ||
353 | + | ||
354 | + memset(s->temperature, 0, sizeof(s->temperature)); | ||
355 | + s->pointer = 0; | ||
356 | + | ||
357 | + s->config[0] = 0; /* TMP421_CONFIG_RANGE */ | ||
358 | + | ||
359 | + /* resistance correction and channel enablement */ | ||
360 | + switch (sc->dev->model) { | ||
361 | + case TMP421_DEVICE_ID: | ||
362 | + s->config[1] = 0x1c; | ||
363 | + break; | ||
364 | + case TMP422_DEVICE_ID: | ||
365 | + s->config[1] = 0x3c; | ||
366 | + break; | ||
367 | + case TMP423_DEVICE_ID: | ||
368 | + s->config[1] = 0x7c; | ||
369 | + break; | ||
370 | + } | ||
371 | + | ||
372 | + s->rate = 0x7; /* 8Hz */ | ||
373 | + s->status = 0; | ||
374 | +} | ||
375 | + | ||
376 | +static int tmp421_init(I2CSlave *i2c) | ||
377 | +{ | ||
378 | + TMP421State *s = TMP421(i2c); | ||
379 | + | ||
380 | + tmp421_reset(&s->i2c); | ||
381 | + | ||
382 | + return 0; | ||
383 | +} | ||
384 | + | ||
385 | +static void tmp421_initfn(Object *obj) | ||
386 | +{ | ||
387 | + object_property_add(obj, "temperature0", "int", | ||
388 | + tmp421_get_temperature, | ||
389 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
390 | + object_property_add(obj, "temperature1", "int", | ||
391 | + tmp421_get_temperature, | ||
392 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
393 | + object_property_add(obj, "temperature2", "int", | ||
394 | + tmp421_get_temperature, | ||
395 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
396 | + object_property_add(obj, "temperature3", "int", | ||
397 | + tmp421_get_temperature, | ||
398 | + tmp421_set_temperature, NULL, NULL, NULL); | ||
399 | +} | ||
400 | + | ||
401 | +static void tmp421_class_init(ObjectClass *klass, void *data) | ||
402 | +{ | ||
403 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
404 | + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
405 | + TMP421Class *sc = TMP421_CLASS(klass); | ||
406 | + | ||
407 | + k->init = tmp421_init; | ||
408 | + k->event = tmp421_event; | ||
409 | + k->recv = tmp421_rx; | ||
410 | + k->send = tmp421_tx; | ||
411 | + dc->vmsd = &vmstate_tmp421; | ||
412 | + sc->dev = (DeviceInfo *) data; | ||
413 | +} | ||
414 | + | ||
415 | +static const TypeInfo tmp421_info = { | ||
416 | + .name = TYPE_TMP421, | ||
417 | + .parent = TYPE_I2C_SLAVE, | ||
418 | + .instance_size = sizeof(TMP421State), | ||
419 | + .class_size = sizeof(TMP421Class), | ||
420 | + .instance_init = tmp421_initfn, | ||
421 | + .abstract = true, | ||
422 | +}; | ||
423 | + | ||
424 | +static void tmp421_register_types(void) | ||
425 | +{ | ||
426 | + int i; | ||
427 | + | ||
428 | + type_register_static(&tmp421_info); | ||
429 | + for (i = 0; i < ARRAY_SIZE(devices); ++i) { | ||
430 | + TypeInfo ti = { | ||
431 | + .name = devices[i].name, | ||
432 | + .parent = TYPE_TMP421, | ||
433 | + .class_init = tmp421_class_init, | ||
434 | + .class_data = (void *) &devices[i], | ||
435 | + }; | ||
436 | + type_register(&ti); | ||
437 | + } | ||
438 | +} | ||
439 | + | ||
440 | +type_init(tmp421_register_types) | ||
441 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
442 | index XXXXXXX..XXXXXXX 100644 | 55 | index XXXXXXX..XXXXXXX 100644 |
443 | --- a/default-configs/arm-softmmu.mak | 56 | --- a/target/arm/translate-neon.c.inc |
444 | +++ b/default-configs/arm-softmmu.mak | 57 | +++ b/target/arm/translate-neon.c.inc |
445 | @@ -XXX,XX +XXX,XX @@ CONFIG_TWL92230=y | 58 | @@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn) |
446 | CONFIG_TSC2005=y | 59 | * early. Since Q is 0 there are always just two passes, so instead |
447 | CONFIG_LM832X=y | 60 | * of a complicated loop over each pass we just unroll. |
448 | CONFIG_TMP105=y | 61 | */ |
449 | +CONFIG_TMP421=y | 62 | - tmp = neon_load_reg(a->vn, 0); |
450 | CONFIG_STELLARIS=y | 63 | - tmp2 = neon_load_reg(a->vn, 1); |
451 | CONFIG_STELLARIS_INPUT=y | 64 | + tmp = tcg_temp_new_i32(); |
452 | CONFIG_STELLARIS_ENET=y | 65 | + tmp2 = tcg_temp_new_i32(); |
66 | + tmp3 = tcg_temp_new_i32(); | ||
67 | + | ||
68 | + read_neon_element32(tmp, a->vn, 0, MO_32); | ||
69 | + read_neon_element32(tmp2, a->vn, 1, MO_32); | ||
70 | fn(tmp, tmp, tmp2); | ||
71 | - tcg_temp_free_i32(tmp2); | ||
72 | |||
73 | - tmp3 = neon_load_reg(a->vm, 0); | ||
74 | - tmp2 = neon_load_reg(a->vm, 1); | ||
75 | + read_neon_element32(tmp3, a->vm, 0, MO_32); | ||
76 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
77 | fn(tmp3, tmp3, tmp2); | ||
78 | - tcg_temp_free_i32(tmp2); | ||
79 | |||
80 | - neon_store_reg(a->vd, 0, tmp); | ||
81 | - neon_store_reg(a->vd, 1, tmp3); | ||
82 | + write_neon_element32(tmp, a->vd, 0, MO_32); | ||
83 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
84 | + | ||
85 | + tcg_temp_free_i32(tmp); | ||
86 | + tcg_temp_free_i32(tmp2); | ||
87 | + tcg_temp_free_i32(tmp3); | ||
88 | return true; | ||
89 | } | ||
90 | |||
91 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, | ||
92 | * 2-reg-and-shift operations, size < 3 case, where the | ||
93 | * helper needs to be passed cpu_env. | ||
94 | */ | ||
95 | - TCGv_i32 constimm; | ||
96 | + TCGv_i32 constimm, tmp; | ||
97 | int pass; | ||
98 | |||
99 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
100 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, | ||
101 | * by immediate using the variable shift operations. | ||
102 | */ | ||
103 | constimm = tcg_const_i32(dup_const(a->size, a->shift)); | ||
104 | + tmp = tcg_temp_new_i32(); | ||
105 | |||
106 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
107 | - TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
108 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
109 | fn(tmp, cpu_env, tmp, constimm); | ||
110 | - neon_store_reg(a->vd, pass, tmp); | ||
111 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
112 | } | ||
113 | + tcg_temp_free_i32(tmp); | ||
114 | tcg_temp_free_i32(constimm); | ||
115 | return true; | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, | ||
118 | constimm = tcg_const_i64(-a->shift); | ||
119 | rm1 = tcg_temp_new_i64(); | ||
120 | rm2 = tcg_temp_new_i64(); | ||
121 | + rd = tcg_temp_new_i32(); | ||
122 | |||
123 | /* Load both inputs first to avoid potential overwrite if rm == rd */ | ||
124 | neon_load_reg64(rm1, a->vm); | ||
125 | neon_load_reg64(rm2, a->vm + 1); | ||
126 | |||
127 | shiftfn(rm1, rm1, constimm); | ||
128 | - rd = tcg_temp_new_i32(); | ||
129 | narrowfn(rd, cpu_env, rm1); | ||
130 | - neon_store_reg(a->vd, 0, rd); | ||
131 | + write_neon_element32(rd, a->vd, 0, MO_32); | ||
132 | |||
133 | shiftfn(rm2, rm2, constimm); | ||
134 | - rd = tcg_temp_new_i32(); | ||
135 | narrowfn(rd, cpu_env, rm2); | ||
136 | - neon_store_reg(a->vd, 1, rd); | ||
137 | + write_neon_element32(rd, a->vd, 1, MO_32); | ||
138 | |||
139 | + tcg_temp_free_i32(rd); | ||
140 | tcg_temp_free_i64(rm1); | ||
141 | tcg_temp_free_i64(rm2); | ||
142 | tcg_temp_free_i64(constimm); | ||
143 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
144 | constimm = tcg_const_i32(imm); | ||
145 | |||
146 | /* Load all inputs first to avoid potential overwrite */ | ||
147 | - rm1 = neon_load_reg(a->vm, 0); | ||
148 | - rm2 = neon_load_reg(a->vm, 1); | ||
149 | - rm3 = neon_load_reg(a->vm + 1, 0); | ||
150 | - rm4 = neon_load_reg(a->vm + 1, 1); | ||
151 | + rm1 = tcg_temp_new_i32(); | ||
152 | + rm2 = tcg_temp_new_i32(); | ||
153 | + rm3 = tcg_temp_new_i32(); | ||
154 | + rm4 = tcg_temp_new_i32(); | ||
155 | + read_neon_element32(rm1, a->vm, 0, MO_32); | ||
156 | + read_neon_element32(rm2, a->vm, 1, MO_32); | ||
157 | + read_neon_element32(rm3, a->vm, 2, MO_32); | ||
158 | + read_neon_element32(rm4, a->vm, 3, MO_32); | ||
159 | rtmp = tcg_temp_new_i64(); | ||
160 | |||
161 | shiftfn(rm1, rm1, constimm); | ||
162 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
163 | tcg_temp_free_i32(rm2); | ||
164 | |||
165 | narrowfn(rm1, cpu_env, rtmp); | ||
166 | - neon_store_reg(a->vd, 0, rm1); | ||
167 | + write_neon_element32(rm1, a->vd, 0, MO_32); | ||
168 | + tcg_temp_free_i32(rm1); | ||
169 | |||
170 | shiftfn(rm3, rm3, constimm); | ||
171 | shiftfn(rm4, rm4, constimm); | ||
172 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
173 | |||
174 | narrowfn(rm3, cpu_env, rtmp); | ||
175 | tcg_temp_free_i64(rtmp); | ||
176 | - neon_store_reg(a->vd, 1, rm3); | ||
177 | + write_neon_element32(rm3, a->vd, 1, MO_32); | ||
178 | + tcg_temp_free_i32(rm3); | ||
179 | return true; | ||
180 | } | ||
181 | |||
182 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
183 | widen_mask = dup_const(a->size + 1, widen_mask); | ||
184 | } | ||
185 | |||
186 | - rm0 = neon_load_reg(a->vm, 0); | ||
187 | - rm1 = neon_load_reg(a->vm, 1); | ||
188 | + rm0 = tcg_temp_new_i32(); | ||
189 | + rm1 = tcg_temp_new_i32(); | ||
190 | + read_neon_element32(rm0, a->vm, 0, MO_32); | ||
191 | + read_neon_element32(rm1, a->vm, 1, MO_32); | ||
192 | tmp = tcg_temp_new_i64(); | ||
193 | |||
194 | widenfn(tmp, rm0); | ||
195 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
196 | if (src1_wide) { | ||
197 | neon_load_reg64(rn0_64, a->vn); | ||
198 | } else { | ||
199 | - TCGv_i32 tmp = neon_load_reg(a->vn, 0); | ||
200 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
201 | + read_neon_element32(tmp, a->vn, 0, MO_32); | ||
202 | widenfn(rn0_64, tmp); | ||
203 | tcg_temp_free_i32(tmp); | ||
204 | } | ||
205 | - rm = neon_load_reg(a->vm, 0); | ||
206 | + rm = tcg_temp_new_i32(); | ||
207 | + read_neon_element32(rm, a->vm, 0, MO_32); | ||
208 | |||
209 | widenfn(rm_64, rm); | ||
210 | tcg_temp_free_i32(rm); | ||
211 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
212 | if (src1_wide) { | ||
213 | neon_load_reg64(rn1_64, a->vn + 1); | ||
214 | } else { | ||
215 | - TCGv_i32 tmp = neon_load_reg(a->vn, 1); | ||
216 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
217 | + read_neon_element32(tmp, a->vn, 1, MO_32); | ||
218 | widenfn(rn1_64, tmp); | ||
219 | tcg_temp_free_i32(tmp); | ||
220 | } | ||
221 | - rm = neon_load_reg(a->vm, 1); | ||
222 | + rm = tcg_temp_new_i32(); | ||
223 | + read_neon_element32(rm, a->vm, 1, MO_32); | ||
224 | |||
225 | neon_store_reg64(rn0_64, a->vd); | ||
226 | |||
227 | @@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | ||
228 | |||
229 | narrowfn(rd1, rn_64); | ||
230 | |||
231 | - neon_store_reg(a->vd, 0, rd0); | ||
232 | - neon_store_reg(a->vd, 1, rd1); | ||
233 | + write_neon_element32(rd0, a->vd, 0, MO_32); | ||
234 | + write_neon_element32(rd1, a->vd, 1, MO_32); | ||
235 | |||
236 | + tcg_temp_free_i32(rd0); | ||
237 | + tcg_temp_free_i32(rd1); | ||
238 | tcg_temp_free_i64(rn_64); | ||
239 | tcg_temp_free_i64(rm_64); | ||
240 | |||
241 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
242 | rd0 = tcg_temp_new_i64(); | ||
243 | rd1 = tcg_temp_new_i64(); | ||
244 | |||
245 | - rn = neon_load_reg(a->vn, 0); | ||
246 | - rm = neon_load_reg(a->vm, 0); | ||
247 | + rn = tcg_temp_new_i32(); | ||
248 | + rm = tcg_temp_new_i32(); | ||
249 | + read_neon_element32(rn, a->vn, 0, MO_32); | ||
250 | + read_neon_element32(rm, a->vm, 0, MO_32); | ||
251 | opfn(rd0, rn, rm); | ||
252 | - tcg_temp_free_i32(rn); | ||
253 | - tcg_temp_free_i32(rm); | ||
254 | |||
255 | - rn = neon_load_reg(a->vn, 1); | ||
256 | - rm = neon_load_reg(a->vm, 1); | ||
257 | + read_neon_element32(rn, a->vn, 1, MO_32); | ||
258 | + read_neon_element32(rm, a->vm, 1, MO_32); | ||
259 | opfn(rd1, rn, rm); | ||
260 | tcg_temp_free_i32(rn); | ||
261 | tcg_temp_free_i32(rm); | ||
262 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var) | ||
263 | |||
264 | static inline TCGv_i32 neon_get_scalar(int size, int reg) | ||
265 | { | ||
266 | - TCGv_i32 tmp; | ||
267 | - if (size == 1) { | ||
268 | - tmp = neon_load_reg(reg & 7, reg >> 4); | ||
269 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
270 | + if (size == MO_16) { | ||
271 | + read_neon_element32(tmp, reg & 7, reg >> 4, MO_32); | ||
272 | if (reg & 8) { | ||
273 | gen_neon_dup_high16(tmp); | ||
274 | } else { | ||
275 | gen_neon_dup_low16(tmp); | ||
276 | } | ||
277 | } else { | ||
278 | - tmp = neon_load_reg(reg & 15, reg >> 4); | ||
279 | + read_neon_element32(tmp, reg & 15, reg >> 4, MO_32); | ||
280 | } | ||
281 | return tmp; | ||
282 | } | ||
283 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
284 | * perform an accumulation operation of that result into the | ||
285 | * destination. | ||
286 | */ | ||
287 | - TCGv_i32 scalar; | ||
288 | + TCGv_i32 scalar, tmp; | ||
289 | int pass; | ||
290 | |||
291 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
292 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
293 | } | ||
294 | |||
295 | scalar = neon_get_scalar(a->size, a->vm); | ||
296 | + tmp = tcg_temp_new_i32(); | ||
297 | |||
298 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
299 | - TCGv_i32 tmp = neon_load_reg(a->vn, pass); | ||
300 | + read_neon_element32(tmp, a->vn, pass, MO_32); | ||
301 | opfn(tmp, tmp, scalar); | ||
302 | if (accfn) { | ||
303 | - TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
304 | + TCGv_i32 rd = tcg_temp_new_i32(); | ||
305 | + read_neon_element32(rd, a->vd, pass, MO_32); | ||
306 | accfn(tmp, rd, tmp); | ||
307 | tcg_temp_free_i32(rd); | ||
308 | } | ||
309 | - neon_store_reg(a->vd, pass, tmp); | ||
310 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
311 | } | ||
312 | + tcg_temp_free_i32(tmp); | ||
313 | tcg_temp_free_i32(scalar); | ||
314 | return true; | ||
315 | } | ||
316 | @@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | ||
317 | * performs a kind of fused op-then-accumulate using a helper | ||
318 | * function that takes all of rd, rn and the scalar at once. | ||
319 | */ | ||
320 | - TCGv_i32 scalar; | ||
321 | + TCGv_i32 scalar, rn, rd; | ||
322 | int pass; | ||
323 | |||
324 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
325 | @@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | ||
326 | } | ||
327 | |||
328 | scalar = neon_get_scalar(a->size, a->vm); | ||
329 | + rn = tcg_temp_new_i32(); | ||
330 | + rd = tcg_temp_new_i32(); | ||
331 | |||
332 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
333 | - TCGv_i32 rn = neon_load_reg(a->vn, pass); | ||
334 | - TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
335 | + read_neon_element32(rn, a->vn, pass, MO_32); | ||
336 | + read_neon_element32(rd, a->vd, pass, MO_32); | ||
337 | opfn(rd, cpu_env, rn, scalar, rd); | ||
338 | - tcg_temp_free_i32(rn); | ||
339 | - neon_store_reg(a->vd, pass, rd); | ||
340 | + write_neon_element32(rd, a->vd, pass, MO_32); | ||
341 | } | ||
342 | + tcg_temp_free_i32(rn); | ||
343 | + tcg_temp_free_i32(rd); | ||
344 | tcg_temp_free_i32(scalar); | ||
345 | |||
346 | return true; | ||
347 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
348 | scalar = neon_get_scalar(a->size, a->vm); | ||
349 | |||
350 | /* Load all inputs before writing any outputs, in case of overlap */ | ||
351 | - rn = neon_load_reg(a->vn, 0); | ||
352 | + rn = tcg_temp_new_i32(); | ||
353 | + read_neon_element32(rn, a->vn, 0, MO_32); | ||
354 | rn0_64 = tcg_temp_new_i64(); | ||
355 | opfn(rn0_64, rn, scalar); | ||
356 | - tcg_temp_free_i32(rn); | ||
357 | |||
358 | - rn = neon_load_reg(a->vn, 1); | ||
359 | + read_neon_element32(rn, a->vn, 1, MO_32); | ||
360 | rn1_64 = tcg_temp_new_i64(); | ||
361 | opfn(rn1_64, rn, scalar); | ||
362 | tcg_temp_free_i32(rn); | ||
363 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
364 | return false; | ||
365 | } | ||
366 | n <<= 3; | ||
367 | + tmp = tcg_temp_new_i32(); | ||
368 | if (a->op) { | ||
369 | - tmp = neon_load_reg(a->vd, 0); | ||
370 | + read_neon_element32(tmp, a->vd, 0, MO_32); | ||
371 | } else { | ||
372 | - tmp = tcg_temp_new_i32(); | ||
373 | tcg_gen_movi_i32(tmp, 0); | ||
374 | } | ||
375 | - tmp2 = neon_load_reg(a->vm, 0); | ||
376 | + tmp2 = tcg_temp_new_i32(); | ||
377 | + read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
378 | ptr1 = vfp_reg_ptr(true, a->vn); | ||
379 | tmp4 = tcg_const_i32(n); | ||
380 | gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
381 | - tcg_temp_free_i32(tmp); | ||
382 | + | ||
383 | if (a->op) { | ||
384 | - tmp = neon_load_reg(a->vd, 1); | ||
385 | + read_neon_element32(tmp, a->vd, 1, MO_32); | ||
386 | } else { | ||
387 | - tmp = tcg_temp_new_i32(); | ||
388 | tcg_gen_movi_i32(tmp, 0); | ||
389 | } | ||
390 | - tmp3 = neon_load_reg(a->vm, 1); | ||
391 | + tmp3 = tcg_temp_new_i32(); | ||
392 | + read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
393 | gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
394 | + tcg_temp_free_i32(tmp); | ||
395 | tcg_temp_free_i32(tmp4); | ||
396 | tcg_temp_free_ptr(ptr1); | ||
397 | - neon_store_reg(a->vd, 0, tmp2); | ||
398 | - neon_store_reg(a->vd, 1, tmp3); | ||
399 | - tcg_temp_free_i32(tmp); | ||
400 | + | ||
401 | + write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
402 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
403 | + tcg_temp_free_i32(tmp2); | ||
404 | + tcg_temp_free_i32(tmp3); | ||
405 | return true; | ||
406 | } | ||
407 | |||
408 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
409 | static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
410 | { | ||
411 | int pass, half; | ||
412 | + TCGv_i32 tmp[2]; | ||
413 | |||
414 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
415 | return false; | ||
416 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
417 | return true; | ||
418 | } | ||
419 | |||
420 | - for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
421 | - TCGv_i32 tmp[2]; | ||
422 | + tmp[0] = tcg_temp_new_i32(); | ||
423 | + tmp[1] = tcg_temp_new_i32(); | ||
424 | |||
425 | + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
426 | for (half = 0; half < 2; half++) { | ||
427 | - tmp[half] = neon_load_reg(a->vm, pass * 2 + half); | ||
428 | + read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32); | ||
429 | switch (a->size) { | ||
430 | case 0: | ||
431 | tcg_gen_bswap32_i32(tmp[half], tmp[half]); | ||
432 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
433 | g_assert_not_reached(); | ||
434 | } | ||
435 | } | ||
436 | - neon_store_reg(a->vd, pass * 2, tmp[1]); | ||
437 | - neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); | ||
438 | + write_neon_element32(tmp[1], a->vd, pass * 2, MO_32); | ||
439 | + write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32); | ||
440 | } | ||
441 | + | ||
442 | + tcg_temp_free_i32(tmp[0]); | ||
443 | + tcg_temp_free_i32(tmp[1]); | ||
444 | return true; | ||
445 | } | ||
446 | |||
447 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
448 | rm0_64 = tcg_temp_new_i64(); | ||
449 | rm1_64 = tcg_temp_new_i64(); | ||
450 | rd_64 = tcg_temp_new_i64(); | ||
451 | - tmp = neon_load_reg(a->vm, pass * 2); | ||
452 | + | ||
453 | + tmp = tcg_temp_new_i32(); | ||
454 | + read_neon_element32(tmp, a->vm, pass * 2, MO_32); | ||
455 | widenfn(rm0_64, tmp); | ||
456 | - tcg_temp_free_i32(tmp); | ||
457 | - tmp = neon_load_reg(a->vm, pass * 2 + 1); | ||
458 | + read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32); | ||
459 | widenfn(rm1_64, tmp); | ||
460 | tcg_temp_free_i32(tmp); | ||
461 | + | ||
462 | opfn(rd_64, rm0_64, rm1_64); | ||
463 | tcg_temp_free_i64(rm0_64); | ||
464 | tcg_temp_free_i64(rm1_64); | ||
465 | @@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
466 | narrowfn(rd0, cpu_env, rm); | ||
467 | neon_load_reg64(rm, a->vm + 1); | ||
468 | narrowfn(rd1, cpu_env, rm); | ||
469 | - neon_store_reg(a->vd, 0, rd0); | ||
470 | - neon_store_reg(a->vd, 1, rd1); | ||
471 | + write_neon_element32(rd0, a->vd, 0, MO_32); | ||
472 | + write_neon_element32(rd1, a->vd, 1, MO_32); | ||
473 | + tcg_temp_free_i32(rd0); | ||
474 | + tcg_temp_free_i32(rd1); | ||
475 | tcg_temp_free_i64(rm); | ||
476 | return true; | ||
477 | } | ||
478 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
479 | } | ||
480 | |||
481 | rd = tcg_temp_new_i64(); | ||
482 | + rm0 = tcg_temp_new_i32(); | ||
483 | + rm1 = tcg_temp_new_i32(); | ||
484 | |||
485 | - rm0 = neon_load_reg(a->vm, 0); | ||
486 | - rm1 = neon_load_reg(a->vm, 1); | ||
487 | + read_neon_element32(rm0, a->vm, 0, MO_32); | ||
488 | + read_neon_element32(rm1, a->vm, 1, MO_32); | ||
489 | |||
490 | widenfn(rd, rm0); | ||
491 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
492 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) | ||
493 | |||
494 | fpst = fpstatus_ptr(FPST_STD); | ||
495 | ahp = get_ahp_flag(); | ||
496 | - tmp = neon_load_reg(a->vm, 0); | ||
497 | + tmp = tcg_temp_new_i32(); | ||
498 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
499 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
500 | - tmp2 = neon_load_reg(a->vm, 1); | ||
501 | + tmp2 = tcg_temp_new_i32(); | ||
502 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
503 | gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); | ||
504 | tcg_gen_shli_i32(tmp2, tmp2, 16); | ||
505 | tcg_gen_or_i32(tmp2, tmp2, tmp); | ||
506 | - tcg_temp_free_i32(tmp); | ||
507 | - tmp = neon_load_reg(a->vm, 2); | ||
508 | + read_neon_element32(tmp, a->vm, 2, MO_32); | ||
509 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
510 | - tmp3 = neon_load_reg(a->vm, 3); | ||
511 | - neon_store_reg(a->vd, 0, tmp2); | ||
512 | + tmp3 = tcg_temp_new_i32(); | ||
513 | + read_neon_element32(tmp3, a->vm, 3, MO_32); | ||
514 | + write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
515 | + tcg_temp_free_i32(tmp2); | ||
516 | gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); | ||
517 | tcg_gen_shli_i32(tmp3, tmp3, 16); | ||
518 | tcg_gen_or_i32(tmp3, tmp3, tmp); | ||
519 | - neon_store_reg(a->vd, 1, tmp3); | ||
520 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
521 | + tcg_temp_free_i32(tmp3); | ||
522 | tcg_temp_free_i32(tmp); | ||
523 | tcg_temp_free_i32(ahp); | ||
524 | tcg_temp_free_ptr(fpst); | ||
525 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
526 | fpst = fpstatus_ptr(FPST_STD); | ||
527 | ahp = get_ahp_flag(); | ||
528 | tmp3 = tcg_temp_new_i32(); | ||
529 | - tmp = neon_load_reg(a->vm, 0); | ||
530 | - tmp2 = neon_load_reg(a->vm, 1); | ||
531 | + tmp2 = tcg_temp_new_i32(); | ||
532 | + tmp = tcg_temp_new_i32(); | ||
533 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
534 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
535 | tcg_gen_ext16u_i32(tmp3, tmp); | ||
536 | gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
537 | - neon_store_reg(a->vd, 0, tmp3); | ||
538 | + write_neon_element32(tmp3, a->vd, 0, MO_32); | ||
539 | tcg_gen_shri_i32(tmp, tmp, 16); | ||
540 | gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); | ||
541 | - neon_store_reg(a->vd, 1, tmp); | ||
542 | - tmp3 = tcg_temp_new_i32(); | ||
543 | + write_neon_element32(tmp, a->vd, 1, MO_32); | ||
544 | + tcg_temp_free_i32(tmp); | ||
545 | tcg_gen_ext16u_i32(tmp3, tmp2); | ||
546 | gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
547 | - neon_store_reg(a->vd, 2, tmp3); | ||
548 | + write_neon_element32(tmp3, a->vd, 2, MO_32); | ||
549 | + tcg_temp_free_i32(tmp3); | ||
550 | tcg_gen_shri_i32(tmp2, tmp2, 16); | ||
551 | gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); | ||
552 | - neon_store_reg(a->vd, 3, tmp2); | ||
553 | + write_neon_element32(tmp2, a->vd, 3, MO_32); | ||
554 | + tcg_temp_free_i32(tmp2); | ||
555 | tcg_temp_free_i32(ahp); | ||
556 | tcg_temp_free_ptr(fpst); | ||
557 | |||
558 | @@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) | ||
559 | |||
560 | static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
561 | { | ||
562 | + TCGv_i32 tmp; | ||
563 | int pass; | ||
564 | |||
565 | /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ | ||
566 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
567 | return true; | ||
568 | } | ||
569 | |||
570 | + tmp = tcg_temp_new_i32(); | ||
571 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
572 | - TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
573 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
574 | fn(tmp, tmp); | ||
575 | - neon_store_reg(a->vd, pass, tmp); | ||
576 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
577 | } | ||
578 | + tcg_temp_free_i32(tmp); | ||
579 | |||
580 | return true; | ||
581 | } | ||
582 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a) | ||
583 | return true; | ||
584 | } | ||
585 | |||
586 | - if (a->size == 2) { | ||
587 | + tmp = tcg_temp_new_i32(); | ||
588 | + tmp2 = tcg_temp_new_i32(); | ||
589 | + if (a->size == MO_32) { | ||
590 | for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) { | ||
591 | - tmp = neon_load_reg(a->vm, pass); | ||
592 | - tmp2 = neon_load_reg(a->vd, pass + 1); | ||
593 | - neon_store_reg(a->vm, pass, tmp2); | ||
594 | - neon_store_reg(a->vd, pass + 1, tmp); | ||
595 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
596 | + read_neon_element32(tmp2, a->vd, pass + 1, MO_32); | ||
597 | + write_neon_element32(tmp2, a->vm, pass, MO_32); | ||
598 | + write_neon_element32(tmp, a->vd, pass + 1, MO_32); | ||
599 | } | ||
600 | } else { | ||
601 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
602 | - tmp = neon_load_reg(a->vm, pass); | ||
603 | - tmp2 = neon_load_reg(a->vd, pass); | ||
604 | - if (a->size == 0) { | ||
605 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
606 | + read_neon_element32(tmp2, a->vd, pass, MO_32); | ||
607 | + if (a->size == MO_8) { | ||
608 | gen_neon_trn_u8(tmp, tmp2); | ||
609 | } else { | ||
610 | gen_neon_trn_u16(tmp, tmp2); | ||
611 | } | ||
612 | - neon_store_reg(a->vm, pass, tmp2); | ||
613 | - neon_store_reg(a->vd, pass, tmp); | ||
614 | + write_neon_element32(tmp2, a->vm, pass, MO_32); | ||
615 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
616 | } | ||
617 | } | ||
618 | + tcg_temp_free_i32(tmp); | ||
619 | + tcg_temp_free_i32(tmp2); | ||
620 | return true; | ||
621 | } | ||
453 | -- | 622 | -- |
454 | 2.7.4 | 623 | 2.20.1 |
455 | 624 | ||
456 | 625 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | We can then use this to improve VMOV (scalar to gp) and | ||
4 | VMOV (gp to scalar) so that we simply perform the memory | ||
5 | operation that we wanted, rather than inserting or | ||
6 | extracting from a 32-bit quantity. | ||
7 | |||
8 | These were the last uses of neon_load/store_reg, so remove them. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20201030022618.785675-7-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/translate.c | 50 +++++++++++++----------- | ||
16 | target/arm/translate-vfp.c.inc | 71 +++++----------------------------- | ||
17 | 2 files changed, 37 insertions(+), 84 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/translate.c | ||
22 | +++ b/target/arm/translate.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg) | ||
24 | * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
25 | * where 0 is the least significant end of the register. | ||
26 | */ | ||
27 | -static long neon_element_offset(int reg, int element, MemOp size) | ||
28 | +static long neon_element_offset(int reg, int element, MemOp memop) | ||
29 | { | ||
30 | - int element_size = 1 << size; | ||
31 | + int element_size = 1 << (memop & MO_SIZE); | ||
32 | int ofs = element * element_size; | ||
33 | #ifdef HOST_WORDS_BIGENDIAN | ||
34 | /* | ||
35 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) | ||
36 | } | ||
37 | } | ||
38 | |||
39 | -static TCGv_i32 neon_load_reg(int reg, int pass) | ||
40 | -{ | ||
41 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
42 | - tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); | ||
43 | - return tmp; | ||
44 | -} | ||
45 | - | ||
46 | -static void neon_store_reg(int reg, int pass, TCGv_i32 var) | ||
47 | -{ | ||
48 | - tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); | ||
49 | - tcg_temp_free_i32(var); | ||
50 | -} | ||
51 | - | ||
52 | static inline void neon_load_reg64(TCGv_i64 var, int reg) | ||
53 | { | ||
54 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | ||
55 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg) | ||
56 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
57 | } | ||
58 | |||
59 | -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) | ||
60 | +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
61 | { | ||
62 | - long off = neon_element_offset(reg, ele, size); | ||
63 | + long off = neon_element_offset(reg, ele, memop); | ||
64 | |||
65 | - switch (size) { | ||
66 | - case MO_32: | ||
67 | + switch (memop) { | ||
68 | + case MO_SB: | ||
69 | + tcg_gen_ld8s_i32(dest, cpu_env, off); | ||
70 | + break; | ||
71 | + case MO_UB: | ||
72 | + tcg_gen_ld8u_i32(dest, cpu_env, off); | ||
73 | + break; | ||
74 | + case MO_SW: | ||
75 | + tcg_gen_ld16s_i32(dest, cpu_env, off); | ||
76 | + break; | ||
77 | + case MO_UW: | ||
78 | + tcg_gen_ld16u_i32(dest, cpu_env, off); | ||
79 | + break; | ||
80 | + case MO_UL: | ||
81 | + case MO_SL: | ||
82 | tcg_gen_ld_i32(dest, cpu_env, off); | ||
83 | break; | ||
84 | default: | ||
85 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) | ||
86 | } | ||
87 | } | ||
88 | |||
89 | -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size) | ||
90 | +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
91 | { | ||
92 | - long off = neon_element_offset(reg, ele, size); | ||
93 | + long off = neon_element_offset(reg, ele, memop); | ||
94 | |||
95 | - switch (size) { | ||
96 | + switch (memop) { | ||
97 | + case MO_8: | ||
98 | + tcg_gen_st8_i32(src, cpu_env, off); | ||
99 | + break; | ||
100 | + case MO_16: | ||
101 | + tcg_gen_st16_i32(src, cpu_env, off); | ||
102 | + break; | ||
103 | case MO_32: | ||
104 | tcg_gen_st_i32(src, cpu_env, off); | ||
105 | break; | ||
106 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/arm/translate-vfp.c.inc | ||
109 | +++ b/target/arm/translate-vfp.c.inc | ||
110 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
111 | { | ||
112 | /* VMOV scalar to general purpose register */ | ||
113 | TCGv_i32 tmp; | ||
114 | - int pass; | ||
115 | - uint32_t offset; | ||
116 | |||
117 | - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | ||
118 | - if (a->size == 2 | ||
119 | + /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */ | ||
120 | + if (a->size == MO_32 | ||
121 | ? !dc_isar_feature(aa32_fpsp_v2, s) | ||
122 | : !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
123 | return false; | ||
124 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
125 | return false; | ||
126 | } | ||
127 | |||
128 | - offset = a->index << a->size; | ||
129 | - pass = extract32(offset, 2, 1); | ||
130 | - offset = extract32(offset, 0, 2) * 8; | ||
131 | - | ||
132 | if (!vfp_access_check(s)) { | ||
133 | return true; | ||
134 | } | ||
135 | |||
136 | - tmp = neon_load_reg(a->vn, pass); | ||
137 | - switch (a->size) { | ||
138 | - case 0: | ||
139 | - if (offset) { | ||
140 | - tcg_gen_shri_i32(tmp, tmp, offset); | ||
141 | - } | ||
142 | - if (a->u) { | ||
143 | - gen_uxtb(tmp); | ||
144 | - } else { | ||
145 | - gen_sxtb(tmp); | ||
146 | - } | ||
147 | - break; | ||
148 | - case 1: | ||
149 | - if (a->u) { | ||
150 | - if (offset) { | ||
151 | - tcg_gen_shri_i32(tmp, tmp, 16); | ||
152 | - } else { | ||
153 | - gen_uxth(tmp); | ||
154 | - } | ||
155 | - } else { | ||
156 | - if (offset) { | ||
157 | - tcg_gen_sari_i32(tmp, tmp, 16); | ||
158 | - } else { | ||
159 | - gen_sxth(tmp); | ||
160 | - } | ||
161 | - } | ||
162 | - break; | ||
163 | - case 2: | ||
164 | - break; | ||
165 | - } | ||
166 | + tmp = tcg_temp_new_i32(); | ||
167 | + read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN)); | ||
168 | store_reg(s, a->rt, tmp); | ||
169 | |||
170 | return true; | ||
171 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
172 | static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
173 | { | ||
174 | /* VMOV general purpose register to scalar */ | ||
175 | - TCGv_i32 tmp, tmp2; | ||
176 | - int pass; | ||
177 | - uint32_t offset; | ||
178 | + TCGv_i32 tmp; | ||
179 | |||
180 | - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | ||
181 | - if (a->size == 2 | ||
182 | + /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */ | ||
183 | + if (a->size == MO_32 | ||
184 | ? !dc_isar_feature(aa32_fpsp_v2, s) | ||
185 | : !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
186 | return false; | ||
187 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
188 | return false; | ||
189 | } | ||
190 | |||
191 | - offset = a->index << a->size; | ||
192 | - pass = extract32(offset, 2, 1); | ||
193 | - offset = extract32(offset, 0, 2) * 8; | ||
194 | - | ||
195 | if (!vfp_access_check(s)) { | ||
196 | return true; | ||
197 | } | ||
198 | |||
199 | tmp = load_reg(s, a->rt); | ||
200 | - switch (a->size) { | ||
201 | - case 0: | ||
202 | - tmp2 = neon_load_reg(a->vn, pass); | ||
203 | - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); | ||
204 | - tcg_temp_free_i32(tmp2); | ||
205 | - break; | ||
206 | - case 1: | ||
207 | - tmp2 = neon_load_reg(a->vn, pass); | ||
208 | - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); | ||
209 | - tcg_temp_free_i32(tmp2); | ||
210 | - break; | ||
211 | - case 2: | ||
212 | - break; | ||
213 | - } | ||
214 | - neon_store_reg(a->vn, pass, tmp); | ||
215 | + write_neon_element32(tmp, a->vn, a->index, a->size); | ||
216 | + tcg_temp_free_i32(tmp); | ||
217 | |||
218 | return true; | ||
219 | } | ||
220 | -- | ||
221 | 2.20.1 | ||
222 | |||
223 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Bring some more readability by declaring local function variables: first | 3 | The only uses of this function are for loading VFP |
4 | initialized ones and then the rest (with reversed-christmas-tree order). | 4 | single-precision values, and nothing to do with NEON. |
5 | 5 | ||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Message-id: 20201030022618.785675-8-richard.henderson@linaro.org |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | hw/arm/exynos4210.c | 4 ++-- | 11 | target/arm/translate.c | 4 +- |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | target/arm/translate-vfp.c.inc | 184 ++++++++++++++++----------------- |
13 | 2 files changed, 94 insertions(+), 94 deletions(-) | ||
12 | 14 | ||
13 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 15 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/exynos4210.c | 17 | --- a/target/arm/translate.c |
16 | +++ b/hw/arm/exynos4210.c | 18 | +++ b/target/arm/translate.c |
17 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu) | 19 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg) |
18 | 20 | tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); | |
19 | Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | 21 | } |
22 | |||
23 | -static inline void neon_load_reg32(TCGv_i32 var, int reg) | ||
24 | +static inline void vfp_load_reg32(TCGv_i32 var, int reg) | ||
20 | { | 25 | { |
21 | - int i, n; | 26 | tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); |
22 | Exynos4210State *s = g_new(Exynos4210State, 1); | 27 | } |
23 | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | 28 | |
24 | - DeviceState *dev; | 29 | -static inline void neon_store_reg32(TCGv_i32 var, int reg) |
25 | SysBusDevice *busdev; | 30 | +static inline void vfp_store_reg32(TCGv_i32 var, int reg) |
26 | ObjectClass *cpu_oc; | 31 | { |
27 | + DeviceState *dev; | 32 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); |
28 | + int i, n; | 33 | } |
29 | 34 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | |
30 | cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); | 35 | index XXXXXXX..XXXXXXX 100644 |
31 | assert(cpu_oc); | 36 | --- a/target/arm/translate-vfp.c.inc |
37 | +++ b/target/arm/translate-vfp.c.inc | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
39 | frn = tcg_temp_new_i32(); | ||
40 | frm = tcg_temp_new_i32(); | ||
41 | dest = tcg_temp_new_i32(); | ||
42 | - neon_load_reg32(frn, rn); | ||
43 | - neon_load_reg32(frm, rm); | ||
44 | + vfp_load_reg32(frn, rn); | ||
45 | + vfp_load_reg32(frm, rm); | ||
46 | switch (a->cc) { | ||
47 | case 0: /* eq: Z */ | ||
48 | tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, | ||
49 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
50 | if (sz == 1) { | ||
51 | tcg_gen_andi_i32(dest, dest, 0xffff); | ||
52 | } | ||
53 | - neon_store_reg32(dest, rd); | ||
54 | + vfp_store_reg32(dest, rd); | ||
55 | tcg_temp_free_i32(frn); | ||
56 | tcg_temp_free_i32(frm); | ||
57 | tcg_temp_free_i32(dest); | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
59 | TCGv_i32 tcg_res; | ||
60 | tcg_op = tcg_temp_new_i32(); | ||
61 | tcg_res = tcg_temp_new_i32(); | ||
62 | - neon_load_reg32(tcg_op, rm); | ||
63 | + vfp_load_reg32(tcg_op, rm); | ||
64 | if (sz == 1) { | ||
65 | gen_helper_rinth(tcg_res, tcg_op, fpst); | ||
66 | } else { | ||
67 | gen_helper_rints(tcg_res, tcg_op, fpst); | ||
68 | } | ||
69 | - neon_store_reg32(tcg_res, rd); | ||
70 | + vfp_store_reg32(tcg_res, rd); | ||
71 | tcg_temp_free_i32(tcg_op); | ||
72 | tcg_temp_free_i32(tcg_res); | ||
73 | } | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
75 | gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); | ||
76 | } | ||
77 | tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); | ||
78 | - neon_store_reg32(tcg_tmp, rd); | ||
79 | + vfp_store_reg32(tcg_tmp, rd); | ||
80 | tcg_temp_free_i32(tcg_tmp); | ||
81 | tcg_temp_free_i64(tcg_res); | ||
82 | tcg_temp_free_i64(tcg_double); | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
84 | TCGv_i32 tcg_single, tcg_res; | ||
85 | tcg_single = tcg_temp_new_i32(); | ||
86 | tcg_res = tcg_temp_new_i32(); | ||
87 | - neon_load_reg32(tcg_single, rm); | ||
88 | + vfp_load_reg32(tcg_single, rm); | ||
89 | if (sz == 1) { | ||
90 | if (is_signed) { | ||
91 | gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst); | ||
92 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
93 | gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); | ||
94 | } | ||
95 | } | ||
96 | - neon_store_reg32(tcg_res, rd); | ||
97 | + vfp_store_reg32(tcg_res, rd); | ||
98 | tcg_temp_free_i32(tcg_res); | ||
99 | tcg_temp_free_i32(tcg_single); | ||
100 | } | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) | ||
102 | if (a->l) { | ||
103 | /* VFP to general purpose register */ | ||
104 | tmp = tcg_temp_new_i32(); | ||
105 | - neon_load_reg32(tmp, a->vn); | ||
106 | + vfp_load_reg32(tmp, a->vn); | ||
107 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | ||
108 | store_reg(s, a->rt, tmp); | ||
109 | } else { | ||
110 | /* general purpose register to VFP */ | ||
111 | tmp = load_reg(s, a->rt); | ||
112 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | ||
113 | - neon_store_reg32(tmp, a->vn); | ||
114 | + vfp_store_reg32(tmp, a->vn); | ||
115 | tcg_temp_free_i32(tmp); | ||
116 | } | ||
117 | |||
118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) | ||
119 | if (a->l) { | ||
120 | /* VFP to general purpose register */ | ||
121 | tmp = tcg_temp_new_i32(); | ||
122 | - neon_load_reg32(tmp, a->vn); | ||
123 | + vfp_load_reg32(tmp, a->vn); | ||
124 | if (a->rt == 15) { | ||
125 | /* Set the 4 flag bits in the CPSR. */ | ||
126 | gen_set_nzcv(tmp); | ||
127 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) | ||
128 | } else { | ||
129 | /* general purpose register to VFP */ | ||
130 | tmp = load_reg(s, a->rt); | ||
131 | - neon_store_reg32(tmp, a->vn); | ||
132 | + vfp_store_reg32(tmp, a->vn); | ||
133 | tcg_temp_free_i32(tmp); | ||
134 | } | ||
135 | |||
136 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) | ||
137 | if (a->op) { | ||
138 | /* fpreg to gpreg */ | ||
139 | tmp = tcg_temp_new_i32(); | ||
140 | - neon_load_reg32(tmp, a->vm); | ||
141 | + vfp_load_reg32(tmp, a->vm); | ||
142 | store_reg(s, a->rt, tmp); | ||
143 | tmp = tcg_temp_new_i32(); | ||
144 | - neon_load_reg32(tmp, a->vm + 1); | ||
145 | + vfp_load_reg32(tmp, a->vm + 1); | ||
146 | store_reg(s, a->rt2, tmp); | ||
147 | } else { | ||
148 | /* gpreg to fpreg */ | ||
149 | tmp = load_reg(s, a->rt); | ||
150 | - neon_store_reg32(tmp, a->vm); | ||
151 | + vfp_store_reg32(tmp, a->vm); | ||
152 | tcg_temp_free_i32(tmp); | ||
153 | tmp = load_reg(s, a->rt2); | ||
154 | - neon_store_reg32(tmp, a->vm + 1); | ||
155 | + vfp_store_reg32(tmp, a->vm + 1); | ||
156 | tcg_temp_free_i32(tmp); | ||
157 | } | ||
158 | |||
159 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) | ||
160 | if (a->op) { | ||
161 | /* fpreg to gpreg */ | ||
162 | tmp = tcg_temp_new_i32(); | ||
163 | - neon_load_reg32(tmp, a->vm * 2); | ||
164 | + vfp_load_reg32(tmp, a->vm * 2); | ||
165 | store_reg(s, a->rt, tmp); | ||
166 | tmp = tcg_temp_new_i32(); | ||
167 | - neon_load_reg32(tmp, a->vm * 2 + 1); | ||
168 | + vfp_load_reg32(tmp, a->vm * 2 + 1); | ||
169 | store_reg(s, a->rt2, tmp); | ||
170 | } else { | ||
171 | /* gpreg to fpreg */ | ||
172 | tmp = load_reg(s, a->rt); | ||
173 | - neon_store_reg32(tmp, a->vm * 2); | ||
174 | + vfp_store_reg32(tmp, a->vm * 2); | ||
175 | tcg_temp_free_i32(tmp); | ||
176 | tmp = load_reg(s, a->rt2); | ||
177 | - neon_store_reg32(tmp, a->vm * 2 + 1); | ||
178 | + vfp_store_reg32(tmp, a->vm * 2 + 1); | ||
179 | tcg_temp_free_i32(tmp); | ||
180 | } | ||
181 | |||
182 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
183 | tmp = tcg_temp_new_i32(); | ||
184 | if (a->l) { | ||
185 | gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); | ||
186 | - neon_store_reg32(tmp, a->vd); | ||
187 | + vfp_store_reg32(tmp, a->vd); | ||
188 | } else { | ||
189 | - neon_load_reg32(tmp, a->vd); | ||
190 | + vfp_load_reg32(tmp, a->vd); | ||
191 | gen_aa32_st16(s, tmp, addr, get_mem_index(s)); | ||
192 | } | ||
193 | tcg_temp_free_i32(tmp); | ||
194 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
195 | tmp = tcg_temp_new_i32(); | ||
196 | if (a->l) { | ||
197 | gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
198 | - neon_store_reg32(tmp, a->vd); | ||
199 | + vfp_store_reg32(tmp, a->vd); | ||
200 | } else { | ||
201 | - neon_load_reg32(tmp, a->vd); | ||
202 | + vfp_load_reg32(tmp, a->vd); | ||
203 | gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
204 | } | ||
205 | tcg_temp_free_i32(tmp); | ||
206 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) | ||
207 | if (a->l) { | ||
208 | /* load */ | ||
209 | gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
210 | - neon_store_reg32(tmp, a->vd + i); | ||
211 | + vfp_store_reg32(tmp, a->vd + i); | ||
212 | } else { | ||
213 | /* store */ | ||
214 | - neon_load_reg32(tmp, a->vd + i); | ||
215 | + vfp_load_reg32(tmp, a->vd + i); | ||
216 | gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
217 | } | ||
218 | tcg_gen_addi_i32(addr, addr, offset); | ||
219 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
220 | fd = tcg_temp_new_i32(); | ||
221 | fpst = fpstatus_ptr(FPST_FPCR); | ||
222 | |||
223 | - neon_load_reg32(f0, vn); | ||
224 | - neon_load_reg32(f1, vm); | ||
225 | + vfp_load_reg32(f0, vn); | ||
226 | + vfp_load_reg32(f1, vm); | ||
227 | |||
228 | for (;;) { | ||
229 | if (reads_vd) { | ||
230 | - neon_load_reg32(fd, vd); | ||
231 | + vfp_load_reg32(fd, vd); | ||
232 | } | ||
233 | fn(fd, f0, f1, fpst); | ||
234 | - neon_store_reg32(fd, vd); | ||
235 | + vfp_store_reg32(fd, vd); | ||
236 | |||
237 | if (veclen == 0) { | ||
238 | break; | ||
239 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
240 | veclen--; | ||
241 | vd = vfp_advance_sreg(vd, delta_d); | ||
242 | vn = vfp_advance_sreg(vn, delta_d); | ||
243 | - neon_load_reg32(f0, vn); | ||
244 | + vfp_load_reg32(f0, vn); | ||
245 | if (delta_m) { | ||
246 | vm = vfp_advance_sreg(vm, delta_m); | ||
247 | - neon_load_reg32(f1, vm); | ||
248 | + vfp_load_reg32(f1, vm); | ||
249 | } | ||
250 | } | ||
251 | |||
252 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
253 | fd = tcg_temp_new_i32(); | ||
254 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
255 | |||
256 | - neon_load_reg32(f0, vn); | ||
257 | - neon_load_reg32(f1, vm); | ||
258 | + vfp_load_reg32(f0, vn); | ||
259 | + vfp_load_reg32(f1, vm); | ||
260 | |||
261 | if (reads_vd) { | ||
262 | - neon_load_reg32(fd, vd); | ||
263 | + vfp_load_reg32(fd, vd); | ||
264 | } | ||
265 | fn(fd, f0, f1, fpst); | ||
266 | - neon_store_reg32(fd, vd); | ||
267 | + vfp_store_reg32(fd, vd); | ||
268 | |||
269 | tcg_temp_free_i32(f0); | ||
270 | tcg_temp_free_i32(f1); | ||
271 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
272 | f0 = tcg_temp_new_i32(); | ||
273 | fd = tcg_temp_new_i32(); | ||
274 | |||
275 | - neon_load_reg32(f0, vm); | ||
276 | + vfp_load_reg32(f0, vm); | ||
277 | |||
278 | for (;;) { | ||
279 | fn(fd, f0); | ||
280 | - neon_store_reg32(fd, vd); | ||
281 | + vfp_store_reg32(fd, vd); | ||
282 | |||
283 | if (veclen == 0) { | ||
284 | break; | ||
285 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
286 | /* single source one-many */ | ||
287 | while (veclen--) { | ||
288 | vd = vfp_advance_sreg(vd, delta_d); | ||
289 | - neon_store_reg32(fd, vd); | ||
290 | + vfp_store_reg32(fd, vd); | ||
291 | } | ||
292 | break; | ||
293 | } | ||
294 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
295 | veclen--; | ||
296 | vd = vfp_advance_sreg(vd, delta_d); | ||
297 | vm = vfp_advance_sreg(vm, delta_m); | ||
298 | - neon_load_reg32(f0, vm); | ||
299 | + vfp_load_reg32(f0, vm); | ||
300 | } | ||
301 | |||
302 | tcg_temp_free_i32(f0); | ||
303 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
304 | } | ||
305 | |||
306 | f0 = tcg_temp_new_i32(); | ||
307 | - neon_load_reg32(f0, vm); | ||
308 | + vfp_load_reg32(f0, vm); | ||
309 | fn(f0, f0); | ||
310 | - neon_store_reg32(f0, vd); | ||
311 | + vfp_store_reg32(f0, vd); | ||
312 | tcg_temp_free_i32(f0); | ||
313 | |||
314 | return true; | ||
315 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | ||
316 | vm = tcg_temp_new_i32(); | ||
317 | vd = tcg_temp_new_i32(); | ||
318 | |||
319 | - neon_load_reg32(vn, a->vn); | ||
320 | - neon_load_reg32(vm, a->vm); | ||
321 | + vfp_load_reg32(vn, a->vn); | ||
322 | + vfp_load_reg32(vm, a->vm); | ||
323 | if (neg_n) { | ||
324 | /* VFNMS, VFMS */ | ||
325 | gen_helper_vfp_negh(vn, vn); | ||
326 | } | ||
327 | - neon_load_reg32(vd, a->vd); | ||
328 | + vfp_load_reg32(vd, a->vd); | ||
329 | if (neg_d) { | ||
330 | /* VFNMA, VFNMS */ | ||
331 | gen_helper_vfp_negh(vd, vd); | ||
332 | } | ||
333 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
334 | gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst); | ||
335 | - neon_store_reg32(vd, a->vd); | ||
336 | + vfp_store_reg32(vd, a->vd); | ||
337 | |||
338 | tcg_temp_free_ptr(fpst); | ||
339 | tcg_temp_free_i32(vn); | ||
340 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | ||
341 | vm = tcg_temp_new_i32(); | ||
342 | vd = tcg_temp_new_i32(); | ||
343 | |||
344 | - neon_load_reg32(vn, a->vn); | ||
345 | - neon_load_reg32(vm, a->vm); | ||
346 | + vfp_load_reg32(vn, a->vn); | ||
347 | + vfp_load_reg32(vm, a->vm); | ||
348 | if (neg_n) { | ||
349 | /* VFNMS, VFMS */ | ||
350 | gen_helper_vfp_negs(vn, vn); | ||
351 | } | ||
352 | - neon_load_reg32(vd, a->vd); | ||
353 | + vfp_load_reg32(vd, a->vd); | ||
354 | if (neg_d) { | ||
355 | /* VFNMA, VFNMS */ | ||
356 | gen_helper_vfp_negs(vd, vd); | ||
357 | } | ||
358 | fpst = fpstatus_ptr(FPST_FPCR); | ||
359 | gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); | ||
360 | - neon_store_reg32(vd, a->vd); | ||
361 | + vfp_store_reg32(vd, a->vd); | ||
362 | |||
363 | tcg_temp_free_ptr(fpst); | ||
364 | tcg_temp_free_i32(vn); | ||
365 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
366 | } | ||
367 | |||
368 | fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm)); | ||
369 | - neon_store_reg32(fd, a->vd); | ||
370 | + vfp_store_reg32(fd, a->vd); | ||
371 | tcg_temp_free_i32(fd); | ||
372 | return true; | ||
373 | } | ||
374 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
375 | fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); | ||
376 | |||
377 | for (;;) { | ||
378 | - neon_store_reg32(fd, vd); | ||
379 | + vfp_store_reg32(fd, vd); | ||
380 | |||
381 | if (veclen == 0) { | ||
382 | break; | ||
383 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a) | ||
384 | vd = tcg_temp_new_i32(); | ||
385 | vm = tcg_temp_new_i32(); | ||
386 | |||
387 | - neon_load_reg32(vd, a->vd); | ||
388 | + vfp_load_reg32(vd, a->vd); | ||
389 | if (a->z) { | ||
390 | tcg_gen_movi_i32(vm, 0); | ||
391 | } else { | ||
392 | - neon_load_reg32(vm, a->vm); | ||
393 | + vfp_load_reg32(vm, a->vm); | ||
394 | } | ||
395 | |||
396 | if (a->e) { | ||
397 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a) | ||
398 | vd = tcg_temp_new_i32(); | ||
399 | vm = tcg_temp_new_i32(); | ||
400 | |||
401 | - neon_load_reg32(vd, a->vd); | ||
402 | + vfp_load_reg32(vd, a->vd); | ||
403 | if (a->z) { | ||
404 | tcg_gen_movi_i32(vm, 0); | ||
405 | } else { | ||
406 | - neon_load_reg32(vm, a->vm); | ||
407 | + vfp_load_reg32(vm, a->vm); | ||
408 | } | ||
409 | |||
410 | if (a->e) { | ||
411 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a) | ||
412 | /* The T bit tells us if we want the low or high 16 bits of Vm */ | ||
413 | tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); | ||
414 | gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); | ||
415 | - neon_store_reg32(tmp, a->vd); | ||
416 | + vfp_store_reg32(tmp, a->vd); | ||
417 | tcg_temp_free_i32(ahp_mode); | ||
418 | tcg_temp_free_ptr(fpst); | ||
419 | tcg_temp_free_i32(tmp); | ||
420 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) | ||
421 | ahp_mode = get_ahp_flag(); | ||
422 | tmp = tcg_temp_new_i32(); | ||
423 | |||
424 | - neon_load_reg32(tmp, a->vm); | ||
425 | + vfp_load_reg32(tmp, a->vm); | ||
426 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); | ||
427 | tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); | ||
428 | tcg_temp_free_i32(ahp_mode); | ||
429 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a) | ||
430 | } | ||
431 | |||
432 | tmp = tcg_temp_new_i32(); | ||
433 | - neon_load_reg32(tmp, a->vm); | ||
434 | + vfp_load_reg32(tmp, a->vm); | ||
435 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
436 | gen_helper_rinth(tmp, tmp, fpst); | ||
437 | - neon_store_reg32(tmp, a->vd); | ||
438 | + vfp_store_reg32(tmp, a->vd); | ||
439 | tcg_temp_free_ptr(fpst); | ||
440 | tcg_temp_free_i32(tmp); | ||
441 | return true; | ||
442 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) | ||
443 | } | ||
444 | |||
445 | tmp = tcg_temp_new_i32(); | ||
446 | - neon_load_reg32(tmp, a->vm); | ||
447 | + vfp_load_reg32(tmp, a->vm); | ||
448 | fpst = fpstatus_ptr(FPST_FPCR); | ||
449 | gen_helper_rints(tmp, tmp, fpst); | ||
450 | - neon_store_reg32(tmp, a->vd); | ||
451 | + vfp_store_reg32(tmp, a->vd); | ||
452 | tcg_temp_free_ptr(fpst); | ||
453 | tcg_temp_free_i32(tmp); | ||
454 | return true; | ||
455 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a) | ||
456 | } | ||
457 | |||
458 | tmp = tcg_temp_new_i32(); | ||
459 | - neon_load_reg32(tmp, a->vm); | ||
460 | + vfp_load_reg32(tmp, a->vm); | ||
461 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
462 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
463 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
464 | gen_helper_rinth(tmp, tmp, fpst); | ||
465 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
466 | - neon_store_reg32(tmp, a->vd); | ||
467 | + vfp_store_reg32(tmp, a->vd); | ||
468 | tcg_temp_free_ptr(fpst); | ||
469 | tcg_temp_free_i32(tcg_rmode); | ||
470 | tcg_temp_free_i32(tmp); | ||
471 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) | ||
472 | } | ||
473 | |||
474 | tmp = tcg_temp_new_i32(); | ||
475 | - neon_load_reg32(tmp, a->vm); | ||
476 | + vfp_load_reg32(tmp, a->vm); | ||
477 | fpst = fpstatus_ptr(FPST_FPCR); | ||
478 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
479 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
480 | gen_helper_rints(tmp, tmp, fpst); | ||
481 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
482 | - neon_store_reg32(tmp, a->vd); | ||
483 | + vfp_store_reg32(tmp, a->vd); | ||
484 | tcg_temp_free_ptr(fpst); | ||
485 | tcg_temp_free_i32(tcg_rmode); | ||
486 | tcg_temp_free_i32(tmp); | ||
487 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a) | ||
488 | } | ||
489 | |||
490 | tmp = tcg_temp_new_i32(); | ||
491 | - neon_load_reg32(tmp, a->vm); | ||
492 | + vfp_load_reg32(tmp, a->vm); | ||
493 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
494 | gen_helper_rinth_exact(tmp, tmp, fpst); | ||
495 | - neon_store_reg32(tmp, a->vd); | ||
496 | + vfp_store_reg32(tmp, a->vd); | ||
497 | tcg_temp_free_ptr(fpst); | ||
498 | tcg_temp_free_i32(tmp); | ||
499 | return true; | ||
500 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) | ||
501 | } | ||
502 | |||
503 | tmp = tcg_temp_new_i32(); | ||
504 | - neon_load_reg32(tmp, a->vm); | ||
505 | + vfp_load_reg32(tmp, a->vm); | ||
506 | fpst = fpstatus_ptr(FPST_FPCR); | ||
507 | gen_helper_rints_exact(tmp, tmp, fpst); | ||
508 | - neon_store_reg32(tmp, a->vd); | ||
509 | + vfp_store_reg32(tmp, a->vd); | ||
510 | tcg_temp_free_ptr(fpst); | ||
511 | tcg_temp_free_i32(tmp); | ||
512 | return true; | ||
513 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
514 | |||
515 | vm = tcg_temp_new_i32(); | ||
516 | vd = tcg_temp_new_i64(); | ||
517 | - neon_load_reg32(vm, a->vm); | ||
518 | + vfp_load_reg32(vm, a->vm); | ||
519 | gen_helper_vfp_fcvtds(vd, vm, cpu_env); | ||
520 | neon_store_reg64(vd, a->vd); | ||
521 | tcg_temp_free_i32(vm); | ||
522 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
523 | vm = tcg_temp_new_i64(); | ||
524 | neon_load_reg64(vm, a->vm); | ||
525 | gen_helper_vfp_fcvtsd(vd, vm, cpu_env); | ||
526 | - neon_store_reg32(vd, a->vd); | ||
527 | + vfp_store_reg32(vd, a->vd); | ||
528 | tcg_temp_free_i32(vd); | ||
529 | tcg_temp_free_i64(vm); | ||
530 | return true; | ||
531 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) | ||
532 | } | ||
533 | |||
534 | vm = tcg_temp_new_i32(); | ||
535 | - neon_load_reg32(vm, a->vm); | ||
536 | + vfp_load_reg32(vm, a->vm); | ||
537 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
538 | if (a->s) { | ||
539 | /* i32 -> f16 */ | ||
540 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) | ||
541 | /* u32 -> f16 */ | ||
542 | gen_helper_vfp_uitoh(vm, vm, fpst); | ||
543 | } | ||
544 | - neon_store_reg32(vm, a->vd); | ||
545 | + vfp_store_reg32(vm, a->vd); | ||
546 | tcg_temp_free_i32(vm); | ||
547 | tcg_temp_free_ptr(fpst); | ||
548 | return true; | ||
549 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
550 | } | ||
551 | |||
552 | vm = tcg_temp_new_i32(); | ||
553 | - neon_load_reg32(vm, a->vm); | ||
554 | + vfp_load_reg32(vm, a->vm); | ||
555 | fpst = fpstatus_ptr(FPST_FPCR); | ||
556 | if (a->s) { | ||
557 | /* i32 -> f32 */ | ||
558 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
559 | /* u32 -> f32 */ | ||
560 | gen_helper_vfp_uitos(vm, vm, fpst); | ||
561 | } | ||
562 | - neon_store_reg32(vm, a->vd); | ||
563 | + vfp_store_reg32(vm, a->vd); | ||
564 | tcg_temp_free_i32(vm); | ||
565 | tcg_temp_free_ptr(fpst); | ||
566 | return true; | ||
567 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
568 | |||
569 | vm = tcg_temp_new_i32(); | ||
570 | vd = tcg_temp_new_i64(); | ||
571 | - neon_load_reg32(vm, a->vm); | ||
572 | + vfp_load_reg32(vm, a->vm); | ||
573 | fpst = fpstatus_ptr(FPST_FPCR); | ||
574 | if (a->s) { | ||
575 | /* i32 -> f64 */ | ||
576 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
577 | vd = tcg_temp_new_i32(); | ||
578 | neon_load_reg64(vm, a->vm); | ||
579 | gen_helper_vjcvt(vd, vm, cpu_env); | ||
580 | - neon_store_reg32(vd, a->vd); | ||
581 | + vfp_store_reg32(vd, a->vd); | ||
582 | tcg_temp_free_i64(vm); | ||
583 | tcg_temp_free_i32(vd); | ||
584 | return true; | ||
585 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
586 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
587 | |||
588 | vd = tcg_temp_new_i32(); | ||
589 | - neon_load_reg32(vd, a->vd); | ||
590 | + vfp_load_reg32(vd, a->vd); | ||
591 | |||
592 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
593 | shift = tcg_const_i32(frac_bits); | ||
594 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
595 | g_assert_not_reached(); | ||
596 | } | ||
597 | |||
598 | - neon_store_reg32(vd, a->vd); | ||
599 | + vfp_store_reg32(vd, a->vd); | ||
600 | tcg_temp_free_i32(vd); | ||
601 | tcg_temp_free_i32(shift); | ||
602 | tcg_temp_free_ptr(fpst); | ||
603 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
604 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
605 | |||
606 | vd = tcg_temp_new_i32(); | ||
607 | - neon_load_reg32(vd, a->vd); | ||
608 | + vfp_load_reg32(vd, a->vd); | ||
609 | |||
610 | fpst = fpstatus_ptr(FPST_FPCR); | ||
611 | shift = tcg_const_i32(frac_bits); | ||
612 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
613 | g_assert_not_reached(); | ||
614 | } | ||
615 | |||
616 | - neon_store_reg32(vd, a->vd); | ||
617 | + vfp_store_reg32(vd, a->vd); | ||
618 | tcg_temp_free_i32(vd); | ||
619 | tcg_temp_free_i32(shift); | ||
620 | tcg_temp_free_ptr(fpst); | ||
621 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
622 | |||
623 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
624 | vm = tcg_temp_new_i32(); | ||
625 | - neon_load_reg32(vm, a->vm); | ||
626 | + vfp_load_reg32(vm, a->vm); | ||
627 | |||
628 | if (a->s) { | ||
629 | if (a->rz) { | ||
630 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
631 | gen_helper_vfp_touih(vm, vm, fpst); | ||
632 | } | ||
633 | } | ||
634 | - neon_store_reg32(vm, a->vd); | ||
635 | + vfp_store_reg32(vm, a->vd); | ||
636 | tcg_temp_free_i32(vm); | ||
637 | tcg_temp_free_ptr(fpst); | ||
638 | return true; | ||
639 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
640 | |||
641 | fpst = fpstatus_ptr(FPST_FPCR); | ||
642 | vm = tcg_temp_new_i32(); | ||
643 | - neon_load_reg32(vm, a->vm); | ||
644 | + vfp_load_reg32(vm, a->vm); | ||
645 | |||
646 | if (a->s) { | ||
647 | if (a->rz) { | ||
648 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
649 | gen_helper_vfp_touis(vm, vm, fpst); | ||
650 | } | ||
651 | } | ||
652 | - neon_store_reg32(vm, a->vd); | ||
653 | + vfp_store_reg32(vm, a->vd); | ||
654 | tcg_temp_free_i32(vm); | ||
655 | tcg_temp_free_ptr(fpst); | ||
656 | return true; | ||
657 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
658 | gen_helper_vfp_touid(vd, vm, fpst); | ||
659 | } | ||
660 | } | ||
661 | - neon_store_reg32(vd, a->vd); | ||
662 | + vfp_store_reg32(vd, a->vd); | ||
663 | tcg_temp_free_i32(vd); | ||
664 | tcg_temp_free_i64(vm); | ||
665 | tcg_temp_free_ptr(fpst); | ||
666 | @@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a) | ||
667 | /* Insert low half of Vm into high half of Vd */ | ||
668 | rm = tcg_temp_new_i32(); | ||
669 | rd = tcg_temp_new_i32(); | ||
670 | - neon_load_reg32(rm, a->vm); | ||
671 | - neon_load_reg32(rd, a->vd); | ||
672 | + vfp_load_reg32(rm, a->vm); | ||
673 | + vfp_load_reg32(rd, a->vd); | ||
674 | tcg_gen_deposit_i32(rd, rd, rm, 16, 16); | ||
675 | - neon_store_reg32(rd, a->vd); | ||
676 | + vfp_store_reg32(rd, a->vd); | ||
677 | tcg_temp_free_i32(rm); | ||
678 | tcg_temp_free_i32(rd); | ||
679 | return true; | ||
680 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a) | ||
681 | |||
682 | /* Set Vd to high half of Vm */ | ||
683 | rm = tcg_temp_new_i32(); | ||
684 | - neon_load_reg32(rm, a->vm); | ||
685 | + vfp_load_reg32(rm, a->vm); | ||
686 | tcg_gen_shri_i32(rm, rm, 16); | ||
687 | - neon_store_reg32(rm, a->vd); | ||
688 | + vfp_store_reg32(rm, a->vd); | ||
689 | tcg_temp_free_i32(rm); | ||
690 | return true; | ||
691 | } | ||
32 | -- | 692 | -- |
33 | 2.7.4 | 693 | 2.20.1 |
34 | 694 | ||
35 | 695 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | Replace all uses of neon_load/store_reg64 within translate-neon.c.inc. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20201030022618.785675-9-richard.henderson@linaro.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/translate.c | 26 +++++++++ | ||
11 | target/arm/translate-neon.c.inc | 94 ++++++++++++++++----------------- | ||
12 | 2 files changed, 73 insertions(+), 47 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate.c | ||
17 | +++ b/target/arm/translate.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
19 | } | ||
20 | } | ||
21 | |||
22 | +static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
23 | +{ | ||
24 | + long off = neon_element_offset(reg, ele, memop); | ||
25 | + | ||
26 | + switch (memop) { | ||
27 | + case MO_Q: | ||
28 | + tcg_gen_ld_i64(dest, cpu_env, off); | ||
29 | + break; | ||
30 | + default: | ||
31 | + g_assert_not_reached(); | ||
32 | + } | ||
33 | +} | ||
34 | + | ||
35 | static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
36 | { | ||
37 | long off = neon_element_offset(reg, ele, memop); | ||
38 | @@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
39 | } | ||
40 | } | ||
41 | |||
42 | +static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
43 | +{ | ||
44 | + long off = neon_element_offset(reg, ele, memop); | ||
45 | + | ||
46 | + switch (memop) { | ||
47 | + case MO_64: | ||
48 | + tcg_gen_st_i64(src, cpu_env, off); | ||
49 | + break; | ||
50 | + default: | ||
51 | + g_assert_not_reached(); | ||
52 | + } | ||
53 | +} | ||
54 | + | ||
55 | static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
56 | { | ||
57 | TCGv_ptr ret = tcg_temp_new_ptr(); | ||
58 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/translate-neon.c.inc | ||
61 | +++ b/target/arm/translate-neon.c.inc | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, | ||
63 | for (pass = 0; pass < a->q + 1; pass++) { | ||
64 | TCGv_i64 tmp = tcg_temp_new_i64(); | ||
65 | |||
66 | - neon_load_reg64(tmp, a->vm + pass); | ||
67 | + read_neon_element64(tmp, a->vm, pass, MO_64); | ||
68 | fn(tmp, cpu_env, tmp, constimm); | ||
69 | - neon_store_reg64(tmp, a->vd + pass); | ||
70 | + write_neon_element64(tmp, a->vd, pass, MO_64); | ||
71 | tcg_temp_free_i64(tmp); | ||
72 | } | ||
73 | tcg_temp_free_i64(constimm); | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, | ||
75 | rd = tcg_temp_new_i32(); | ||
76 | |||
77 | /* Load both inputs first to avoid potential overwrite if rm == rd */ | ||
78 | - neon_load_reg64(rm1, a->vm); | ||
79 | - neon_load_reg64(rm2, a->vm + 1); | ||
80 | + read_neon_element64(rm1, a->vm, 0, MO_64); | ||
81 | + read_neon_element64(rm2, a->vm, 1, MO_64); | ||
82 | |||
83 | shiftfn(rm1, rm1, constimm); | ||
84 | narrowfn(rd, cpu_env, rm1); | ||
85 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
86 | tcg_gen_shli_i64(tmp, tmp, a->shift); | ||
87 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | ||
88 | } | ||
89 | - neon_store_reg64(tmp, a->vd); | ||
90 | + write_neon_element64(tmp, a->vd, 0, MO_64); | ||
91 | |||
92 | widenfn(tmp, rm1); | ||
93 | tcg_temp_free_i32(rm1); | ||
94 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
95 | tcg_gen_shli_i64(tmp, tmp, a->shift); | ||
96 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | ||
97 | } | ||
98 | - neon_store_reg64(tmp, a->vd + 1); | ||
99 | + write_neon_element64(tmp, a->vd, 1, MO_64); | ||
100 | tcg_temp_free_i64(tmp); | ||
101 | return true; | ||
102 | } | ||
103 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
104 | rm_64 = tcg_temp_new_i64(); | ||
105 | |||
106 | if (src1_wide) { | ||
107 | - neon_load_reg64(rn0_64, a->vn); | ||
108 | + read_neon_element64(rn0_64, a->vn, 0, MO_64); | ||
109 | } else { | ||
110 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
111 | read_neon_element32(tmp, a->vn, 0, MO_32); | ||
112 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
113 | * avoid incorrect results if a narrow input overlaps with the result. | ||
114 | */ | ||
115 | if (src1_wide) { | ||
116 | - neon_load_reg64(rn1_64, a->vn + 1); | ||
117 | + read_neon_element64(rn1_64, a->vn, 1, MO_64); | ||
118 | } else { | ||
119 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
120 | read_neon_element32(tmp, a->vn, 1, MO_32); | ||
121 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
122 | rm = tcg_temp_new_i32(); | ||
123 | read_neon_element32(rm, a->vm, 1, MO_32); | ||
124 | |||
125 | - neon_store_reg64(rn0_64, a->vd); | ||
126 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
127 | |||
128 | widenfn(rm_64, rm); | ||
129 | tcg_temp_free_i32(rm); | ||
130 | opfn(rn1_64, rn1_64, rm_64); | ||
131 | - neon_store_reg64(rn1_64, a->vd + 1); | ||
132 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
133 | |||
134 | tcg_temp_free_i64(rn0_64); | ||
135 | tcg_temp_free_i64(rn1_64); | ||
136 | @@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | ||
137 | rd0 = tcg_temp_new_i32(); | ||
138 | rd1 = tcg_temp_new_i32(); | ||
139 | |||
140 | - neon_load_reg64(rn_64, a->vn); | ||
141 | - neon_load_reg64(rm_64, a->vm); | ||
142 | + read_neon_element64(rn_64, a->vn, 0, MO_64); | ||
143 | + read_neon_element64(rm_64, a->vm, 0, MO_64); | ||
144 | |||
145 | opfn(rn_64, rn_64, rm_64); | ||
146 | |||
147 | narrowfn(rd0, rn_64); | ||
148 | |||
149 | - neon_load_reg64(rn_64, a->vn + 1); | ||
150 | - neon_load_reg64(rm_64, a->vm + 1); | ||
151 | + read_neon_element64(rn_64, a->vn, 1, MO_64); | ||
152 | + read_neon_element64(rm_64, a->vm, 1, MO_64); | ||
153 | |||
154 | opfn(rn_64, rn_64, rm_64); | ||
155 | |||
156 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
157 | /* Don't store results until after all loads: they might overlap */ | ||
158 | if (accfn) { | ||
159 | tmp = tcg_temp_new_i64(); | ||
160 | - neon_load_reg64(tmp, a->vd); | ||
161 | + read_neon_element64(tmp, a->vd, 0, MO_64); | ||
162 | accfn(tmp, tmp, rd0); | ||
163 | - neon_store_reg64(tmp, a->vd); | ||
164 | - neon_load_reg64(tmp, a->vd + 1); | ||
165 | + write_neon_element64(tmp, a->vd, 0, MO_64); | ||
166 | + read_neon_element64(tmp, a->vd, 1, MO_64); | ||
167 | accfn(tmp, tmp, rd1); | ||
168 | - neon_store_reg64(tmp, a->vd + 1); | ||
169 | + write_neon_element64(tmp, a->vd, 1, MO_64); | ||
170 | tcg_temp_free_i64(tmp); | ||
171 | } else { | ||
172 | - neon_store_reg64(rd0, a->vd); | ||
173 | - neon_store_reg64(rd1, a->vd + 1); | ||
174 | + write_neon_element64(rd0, a->vd, 0, MO_64); | ||
175 | + write_neon_element64(rd1, a->vd, 1, MO_64); | ||
176 | } | ||
177 | |||
178 | tcg_temp_free_i64(rd0); | ||
179 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
180 | |||
181 | if (accfn) { | ||
182 | TCGv_i64 t64 = tcg_temp_new_i64(); | ||
183 | - neon_load_reg64(t64, a->vd); | ||
184 | + read_neon_element64(t64, a->vd, 0, MO_64); | ||
185 | accfn(t64, t64, rn0_64); | ||
186 | - neon_store_reg64(t64, a->vd); | ||
187 | - neon_load_reg64(t64, a->vd + 1); | ||
188 | + write_neon_element64(t64, a->vd, 0, MO_64); | ||
189 | + read_neon_element64(t64, a->vd, 1, MO_64); | ||
190 | accfn(t64, t64, rn1_64); | ||
191 | - neon_store_reg64(t64, a->vd + 1); | ||
192 | + write_neon_element64(t64, a->vd, 1, MO_64); | ||
193 | tcg_temp_free_i64(t64); | ||
194 | } else { | ||
195 | - neon_store_reg64(rn0_64, a->vd); | ||
196 | - neon_store_reg64(rn1_64, a->vd + 1); | ||
197 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
198 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
199 | } | ||
200 | tcg_temp_free_i64(rn0_64); | ||
201 | tcg_temp_free_i64(rn1_64); | ||
202 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
203 | right = tcg_temp_new_i64(); | ||
204 | dest = tcg_temp_new_i64(); | ||
205 | |||
206 | - neon_load_reg64(right, a->vn); | ||
207 | - neon_load_reg64(left, a->vm); | ||
208 | + read_neon_element64(right, a->vn, 0, MO_64); | ||
209 | + read_neon_element64(left, a->vm, 0, MO_64); | ||
210 | tcg_gen_extract2_i64(dest, right, left, a->imm * 8); | ||
211 | - neon_store_reg64(dest, a->vd); | ||
212 | + write_neon_element64(dest, a->vd, 0, MO_64); | ||
213 | |||
214 | tcg_temp_free_i64(left); | ||
215 | tcg_temp_free_i64(right); | ||
216 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
217 | destright = tcg_temp_new_i64(); | ||
218 | |||
219 | if (a->imm < 8) { | ||
220 | - neon_load_reg64(right, a->vn); | ||
221 | - neon_load_reg64(middle, a->vn + 1); | ||
222 | + read_neon_element64(right, a->vn, 0, MO_64); | ||
223 | + read_neon_element64(middle, a->vn, 1, MO_64); | ||
224 | tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); | ||
225 | - neon_load_reg64(left, a->vm); | ||
226 | + read_neon_element64(left, a->vm, 0, MO_64); | ||
227 | tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); | ||
228 | } else { | ||
229 | - neon_load_reg64(right, a->vn + 1); | ||
230 | - neon_load_reg64(middle, a->vm); | ||
231 | + read_neon_element64(right, a->vn, 1, MO_64); | ||
232 | + read_neon_element64(middle, a->vm, 0, MO_64); | ||
233 | tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8); | ||
234 | - neon_load_reg64(left, a->vm + 1); | ||
235 | + read_neon_element64(left, a->vm, 1, MO_64); | ||
236 | tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); | ||
237 | } | ||
238 | |||
239 | - neon_store_reg64(destright, a->vd); | ||
240 | - neon_store_reg64(destleft, a->vd + 1); | ||
241 | + write_neon_element64(destright, a->vd, 0, MO_64); | ||
242 | + write_neon_element64(destleft, a->vd, 1, MO_64); | ||
243 | |||
244 | tcg_temp_free_i64(destright); | ||
245 | tcg_temp_free_i64(destleft); | ||
246 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
247 | |||
248 | if (accfn) { | ||
249 | TCGv_i64 tmp64 = tcg_temp_new_i64(); | ||
250 | - neon_load_reg64(tmp64, a->vd + pass); | ||
251 | + read_neon_element64(tmp64, a->vd, pass, MO_64); | ||
252 | accfn(rd_64, tmp64, rd_64); | ||
253 | tcg_temp_free_i64(tmp64); | ||
254 | } | ||
255 | - neon_store_reg64(rd_64, a->vd + pass); | ||
256 | + write_neon_element64(rd_64, a->vd, pass, MO_64); | ||
257 | tcg_temp_free_i64(rd_64); | ||
258 | } | ||
259 | return true; | ||
260 | @@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
261 | rd0 = tcg_temp_new_i32(); | ||
262 | rd1 = tcg_temp_new_i32(); | ||
263 | |||
264 | - neon_load_reg64(rm, a->vm); | ||
265 | + read_neon_element64(rm, a->vm, 0, MO_64); | ||
266 | narrowfn(rd0, cpu_env, rm); | ||
267 | - neon_load_reg64(rm, a->vm + 1); | ||
268 | + read_neon_element64(rm, a->vm, 1, MO_64); | ||
269 | narrowfn(rd1, cpu_env, rm); | ||
270 | write_neon_element32(rd0, a->vd, 0, MO_32); | ||
271 | write_neon_element32(rd1, a->vd, 1, MO_32); | ||
272 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
273 | |||
274 | widenfn(rd, rm0); | ||
275 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
276 | - neon_store_reg64(rd, a->vd); | ||
277 | + write_neon_element64(rd, a->vd, 0, MO_64); | ||
278 | widenfn(rd, rm1); | ||
279 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
280 | - neon_store_reg64(rd, a->vd + 1); | ||
281 | + write_neon_element64(rd, a->vd, 1, MO_64); | ||
282 | |||
283 | tcg_temp_free_i64(rd); | ||
284 | tcg_temp_free_i32(rm0); | ||
285 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a) | ||
286 | rm = tcg_temp_new_i64(); | ||
287 | rd = tcg_temp_new_i64(); | ||
288 | for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
289 | - neon_load_reg64(rm, a->vm + pass); | ||
290 | - neon_load_reg64(rd, a->vd + pass); | ||
291 | - neon_store_reg64(rm, a->vd + pass); | ||
292 | - neon_store_reg64(rd, a->vm + pass); | ||
293 | + read_neon_element64(rm, a->vm, pass, MO_64); | ||
294 | + read_neon_element64(rd, a->vd, pass, MO_64); | ||
295 | + write_neon_element64(rm, a->vd, pass, MO_64); | ||
296 | + write_neon_element64(rd, a->vm, pass, MO_64); | ||
297 | } | ||
298 | tcg_temp_free_i64(rm); | ||
299 | tcg_temp_free_i64(rd); | ||
300 | -- | ||
301 | 2.20.1 | ||
302 | |||
303 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | The only uses of this function are for loading VFP | ||
4 | double-precision values, and nothing to do with NEON. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201030022618.785675-10-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate.c | 8 ++-- | ||
12 | target/arm/translate-vfp.c.inc | 84 +++++++++++++++++----------------- | ||
13 | 2 files changed, 46 insertions(+), 46 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate.c | ||
18 | +++ b/target/arm/translate.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) | ||
20 | } | ||
21 | } | ||
22 | |||
23 | -static inline void neon_load_reg64(TCGv_i64 var, int reg) | ||
24 | +static inline void vfp_load_reg64(TCGv_i64 var, int reg) | ||
25 | { | ||
26 | - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | ||
27 | + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
28 | } | ||
29 | |||
30 | -static inline void neon_store_reg64(TCGv_i64 var, int reg) | ||
31 | +static inline void vfp_store_reg64(TCGv_i64 var, int reg) | ||
32 | { | ||
33 | - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); | ||
34 | + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
35 | } | ||
36 | |||
37 | static inline void vfp_load_reg32(TCGv_i32 var, int reg) | ||
38 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/translate-vfp.c.inc | ||
41 | +++ b/target/arm/translate-vfp.c.inc | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
43 | tcg_gen_ext_i32_i64(nf, cpu_NF); | ||
44 | tcg_gen_ext_i32_i64(vf, cpu_VF); | ||
45 | |||
46 | - neon_load_reg64(frn, rn); | ||
47 | - neon_load_reg64(frm, rm); | ||
48 | + vfp_load_reg64(frn, rn); | ||
49 | + vfp_load_reg64(frm, rm); | ||
50 | switch (a->cc) { | ||
51 | case 0: /* eq: Z */ | ||
52 | tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, | ||
53 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
54 | tcg_temp_free_i64(tmp); | ||
55 | break; | ||
56 | } | ||
57 | - neon_store_reg64(dest, rd); | ||
58 | + vfp_store_reg64(dest, rd); | ||
59 | tcg_temp_free_i64(frn); | ||
60 | tcg_temp_free_i64(frm); | ||
61 | tcg_temp_free_i64(dest); | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
63 | TCGv_i64 tcg_res; | ||
64 | tcg_op = tcg_temp_new_i64(); | ||
65 | tcg_res = tcg_temp_new_i64(); | ||
66 | - neon_load_reg64(tcg_op, rm); | ||
67 | + vfp_load_reg64(tcg_op, rm); | ||
68 | gen_helper_rintd(tcg_res, tcg_op, fpst); | ||
69 | - neon_store_reg64(tcg_res, rd); | ||
70 | + vfp_store_reg64(tcg_res, rd); | ||
71 | tcg_temp_free_i64(tcg_op); | ||
72 | tcg_temp_free_i64(tcg_res); | ||
73 | } else { | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
75 | tcg_double = tcg_temp_new_i64(); | ||
76 | tcg_res = tcg_temp_new_i64(); | ||
77 | tcg_tmp = tcg_temp_new_i32(); | ||
78 | - neon_load_reg64(tcg_double, rm); | ||
79 | + vfp_load_reg64(tcg_double, rm); | ||
80 | if (is_signed) { | ||
81 | gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); | ||
82 | } else { | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) | ||
84 | tmp = tcg_temp_new_i64(); | ||
85 | if (a->l) { | ||
86 | gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); | ||
87 | - neon_store_reg64(tmp, a->vd); | ||
88 | + vfp_store_reg64(tmp, a->vd); | ||
89 | } else { | ||
90 | - neon_load_reg64(tmp, a->vd); | ||
91 | + vfp_load_reg64(tmp, a->vd); | ||
92 | gen_aa32_st64(s, tmp, addr, get_mem_index(s)); | ||
93 | } | ||
94 | tcg_temp_free_i64(tmp); | ||
95 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) | ||
96 | if (a->l) { | ||
97 | /* load */ | ||
98 | gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); | ||
99 | - neon_store_reg64(tmp, a->vd + i); | ||
100 | + vfp_store_reg64(tmp, a->vd + i); | ||
101 | } else { | ||
102 | /* store */ | ||
103 | - neon_load_reg64(tmp, a->vd + i); | ||
104 | + vfp_load_reg64(tmp, a->vd + i); | ||
105 | gen_aa32_st64(s, tmp, addr, get_mem_index(s)); | ||
106 | } | ||
107 | tcg_gen_addi_i32(addr, addr, offset); | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
109 | fd = tcg_temp_new_i64(); | ||
110 | fpst = fpstatus_ptr(FPST_FPCR); | ||
111 | |||
112 | - neon_load_reg64(f0, vn); | ||
113 | - neon_load_reg64(f1, vm); | ||
114 | + vfp_load_reg64(f0, vn); | ||
115 | + vfp_load_reg64(f1, vm); | ||
116 | |||
117 | for (;;) { | ||
118 | if (reads_vd) { | ||
119 | - neon_load_reg64(fd, vd); | ||
120 | + vfp_load_reg64(fd, vd); | ||
121 | } | ||
122 | fn(fd, f0, f1, fpst); | ||
123 | - neon_store_reg64(fd, vd); | ||
124 | + vfp_store_reg64(fd, vd); | ||
125 | |||
126 | if (veclen == 0) { | ||
127 | break; | ||
128 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
129 | veclen--; | ||
130 | vd = vfp_advance_dreg(vd, delta_d); | ||
131 | vn = vfp_advance_dreg(vn, delta_d); | ||
132 | - neon_load_reg64(f0, vn); | ||
133 | + vfp_load_reg64(f0, vn); | ||
134 | if (delta_m) { | ||
135 | vm = vfp_advance_dreg(vm, delta_m); | ||
136 | - neon_load_reg64(f1, vm); | ||
137 | + vfp_load_reg64(f1, vm); | ||
138 | } | ||
139 | } | ||
140 | |||
141 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
142 | f0 = tcg_temp_new_i64(); | ||
143 | fd = tcg_temp_new_i64(); | ||
144 | |||
145 | - neon_load_reg64(f0, vm); | ||
146 | + vfp_load_reg64(f0, vm); | ||
147 | |||
148 | for (;;) { | ||
149 | fn(fd, f0); | ||
150 | - neon_store_reg64(fd, vd); | ||
151 | + vfp_store_reg64(fd, vd); | ||
152 | |||
153 | if (veclen == 0) { | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
156 | /* single source one-many */ | ||
157 | while (veclen--) { | ||
158 | vd = vfp_advance_dreg(vd, delta_d); | ||
159 | - neon_store_reg64(fd, vd); | ||
160 | + vfp_store_reg64(fd, vd); | ||
161 | } | ||
162 | break; | ||
163 | } | ||
164 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
165 | veclen--; | ||
166 | vd = vfp_advance_dreg(vd, delta_d); | ||
167 | vd = vfp_advance_dreg(vm, delta_m); | ||
168 | - neon_load_reg64(f0, vm); | ||
169 | + vfp_load_reg64(f0, vm); | ||
170 | } | ||
171 | |||
172 | tcg_temp_free_i64(f0); | ||
173 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) | ||
174 | vm = tcg_temp_new_i64(); | ||
175 | vd = tcg_temp_new_i64(); | ||
176 | |||
177 | - neon_load_reg64(vn, a->vn); | ||
178 | - neon_load_reg64(vm, a->vm); | ||
179 | + vfp_load_reg64(vn, a->vn); | ||
180 | + vfp_load_reg64(vm, a->vm); | ||
181 | if (neg_n) { | ||
182 | /* VFNMS, VFMS */ | ||
183 | gen_helper_vfp_negd(vn, vn); | ||
184 | } | ||
185 | - neon_load_reg64(vd, a->vd); | ||
186 | + vfp_load_reg64(vd, a->vd); | ||
187 | if (neg_d) { | ||
188 | /* VFNMA, VFNMS */ | ||
189 | gen_helper_vfp_negd(vd, vd); | ||
190 | } | ||
191 | fpst = fpstatus_ptr(FPST_FPCR); | ||
192 | gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); | ||
193 | - neon_store_reg64(vd, a->vd); | ||
194 | + vfp_store_reg64(vd, a->vd); | ||
195 | |||
196 | tcg_temp_free_ptr(fpst); | ||
197 | tcg_temp_free_i64(vn); | ||
198 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
199 | fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); | ||
200 | |||
201 | for (;;) { | ||
202 | - neon_store_reg64(fd, vd); | ||
203 | + vfp_store_reg64(fd, vd); | ||
204 | |||
205 | if (veclen == 0) { | ||
206 | break; | ||
207 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) | ||
208 | vd = tcg_temp_new_i64(); | ||
209 | vm = tcg_temp_new_i64(); | ||
210 | |||
211 | - neon_load_reg64(vd, a->vd); | ||
212 | + vfp_load_reg64(vd, a->vd); | ||
213 | if (a->z) { | ||
214 | tcg_gen_movi_i64(vm, 0); | ||
215 | } else { | ||
216 | - neon_load_reg64(vm, a->vm); | ||
217 | + vfp_load_reg64(vm, a->vm); | ||
218 | } | ||
219 | |||
220 | if (a->e) { | ||
221 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) | ||
222 | tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); | ||
223 | vd = tcg_temp_new_i64(); | ||
224 | gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); | ||
225 | - neon_store_reg64(vd, a->vd); | ||
226 | + vfp_store_reg64(vd, a->vd); | ||
227 | tcg_temp_free_i32(ahp_mode); | ||
228 | tcg_temp_free_ptr(fpst); | ||
229 | tcg_temp_free_i32(tmp); | ||
230 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) | ||
231 | tmp = tcg_temp_new_i32(); | ||
232 | vm = tcg_temp_new_i64(); | ||
233 | |||
234 | - neon_load_reg64(vm, a->vm); | ||
235 | + vfp_load_reg64(vm, a->vm); | ||
236 | gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); | ||
237 | tcg_temp_free_i64(vm); | ||
238 | tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); | ||
239 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) | ||
240 | } | ||
241 | |||
242 | tmp = tcg_temp_new_i64(); | ||
243 | - neon_load_reg64(tmp, a->vm); | ||
244 | + vfp_load_reg64(tmp, a->vm); | ||
245 | fpst = fpstatus_ptr(FPST_FPCR); | ||
246 | gen_helper_rintd(tmp, tmp, fpst); | ||
247 | - neon_store_reg64(tmp, a->vd); | ||
248 | + vfp_store_reg64(tmp, a->vd); | ||
249 | tcg_temp_free_ptr(fpst); | ||
250 | tcg_temp_free_i64(tmp); | ||
251 | return true; | ||
252 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) | ||
253 | } | ||
254 | |||
255 | tmp = tcg_temp_new_i64(); | ||
256 | - neon_load_reg64(tmp, a->vm); | ||
257 | + vfp_load_reg64(tmp, a->vm); | ||
258 | fpst = fpstatus_ptr(FPST_FPCR); | ||
259 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
260 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
261 | gen_helper_rintd(tmp, tmp, fpst); | ||
262 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
263 | - neon_store_reg64(tmp, a->vd); | ||
264 | + vfp_store_reg64(tmp, a->vd); | ||
265 | tcg_temp_free_ptr(fpst); | ||
266 | tcg_temp_free_i64(tmp); | ||
267 | tcg_temp_free_i32(tcg_rmode); | ||
268 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) | ||
269 | } | ||
270 | |||
271 | tmp = tcg_temp_new_i64(); | ||
272 | - neon_load_reg64(tmp, a->vm); | ||
273 | + vfp_load_reg64(tmp, a->vm); | ||
274 | fpst = fpstatus_ptr(FPST_FPCR); | ||
275 | gen_helper_rintd_exact(tmp, tmp, fpst); | ||
276 | - neon_store_reg64(tmp, a->vd); | ||
277 | + vfp_store_reg64(tmp, a->vd); | ||
278 | tcg_temp_free_ptr(fpst); | ||
279 | tcg_temp_free_i64(tmp); | ||
280 | return true; | ||
281 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
282 | vd = tcg_temp_new_i64(); | ||
283 | vfp_load_reg32(vm, a->vm); | ||
284 | gen_helper_vfp_fcvtds(vd, vm, cpu_env); | ||
285 | - neon_store_reg64(vd, a->vd); | ||
286 | + vfp_store_reg64(vd, a->vd); | ||
287 | tcg_temp_free_i32(vm); | ||
288 | tcg_temp_free_i64(vd); | ||
289 | return true; | ||
290 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
291 | |||
292 | vd = tcg_temp_new_i32(); | ||
293 | vm = tcg_temp_new_i64(); | ||
294 | - neon_load_reg64(vm, a->vm); | ||
295 | + vfp_load_reg64(vm, a->vm); | ||
296 | gen_helper_vfp_fcvtsd(vd, vm, cpu_env); | ||
297 | vfp_store_reg32(vd, a->vd); | ||
298 | tcg_temp_free_i32(vd); | ||
299 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
300 | /* u32 -> f64 */ | ||
301 | gen_helper_vfp_uitod(vd, vm, fpst); | ||
302 | } | ||
303 | - neon_store_reg64(vd, a->vd); | ||
304 | + vfp_store_reg64(vd, a->vd); | ||
305 | tcg_temp_free_i32(vm); | ||
306 | tcg_temp_free_i64(vd); | ||
307 | tcg_temp_free_ptr(fpst); | ||
308 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
309 | |||
310 | vm = tcg_temp_new_i64(); | ||
311 | vd = tcg_temp_new_i32(); | ||
312 | - neon_load_reg64(vm, a->vm); | ||
313 | + vfp_load_reg64(vm, a->vm); | ||
314 | gen_helper_vjcvt(vd, vm, cpu_env); | ||
315 | vfp_store_reg32(vd, a->vd); | ||
316 | tcg_temp_free_i64(vm); | ||
317 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
318 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
319 | |||
320 | vd = tcg_temp_new_i64(); | ||
321 | - neon_load_reg64(vd, a->vd); | ||
322 | + vfp_load_reg64(vd, a->vd); | ||
323 | |||
324 | fpst = fpstatus_ptr(FPST_FPCR); | ||
325 | shift = tcg_const_i32(frac_bits); | ||
326 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
327 | g_assert_not_reached(); | ||
328 | } | ||
329 | |||
330 | - neon_store_reg64(vd, a->vd); | ||
331 | + vfp_store_reg64(vd, a->vd); | ||
332 | tcg_temp_free_i64(vd); | ||
333 | tcg_temp_free_i32(shift); | ||
334 | tcg_temp_free_ptr(fpst); | ||
335 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
336 | fpst = fpstatus_ptr(FPST_FPCR); | ||
337 | vm = tcg_temp_new_i64(); | ||
338 | vd = tcg_temp_new_i32(); | ||
339 | - neon_load_reg64(vm, a->vm); | ||
340 | + vfp_load_reg64(vm, a->vm); | ||
341 | |||
342 | if (a->s) { | ||
343 | if (a->rz) { | ||
344 | -- | ||
345 | 2.20.1 | ||
346 | |||
347 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Remove defines not used anywhere. | 3 | In both cases, we can sink the write-back and perform |
4 | the accumulate into the normal destination temps. | ||
4 | 5 | ||
5 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20201030022618.785675-11-richard.henderson@linaro.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 10 | --- |
9 | hw/timer/exynos4210_mct.c | 3 --- | 11 | target/arm/translate-neon.c.inc | 23 +++++++++-------------- |
10 | 1 file changed, 3 deletions(-) | 12 | 1 file changed, 9 insertions(+), 14 deletions(-) |
11 | 13 | ||
12 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 14 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/timer/exynos4210_mct.c | 16 | --- a/target/arm/translate-neon.c.inc |
15 | +++ b/hw/timer/exynos4210_mct.c | 17 | +++ b/target/arm/translate-neon.c.inc |
16 | @@ -XXX,XX +XXX,XX @@ enum LocalTimerRegCntIndexes { | 18 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, |
17 | L_REG_CNT_AMOUNT | 19 | if (accfn) { |
18 | }; | 20 | tmp = tcg_temp_new_i64(); |
19 | 21 | read_neon_element64(tmp, a->vd, 0, MO_64); | |
20 | -#define MCT_NIRQ 6 | 22 | - accfn(tmp, tmp, rd0); |
21 | #define MCT_SFR_SIZE 0x444 | 23 | - write_neon_element64(tmp, a->vd, 0, MO_64); |
22 | 24 | + accfn(rd0, tmp, rd0); | |
23 | #define MCT_GT_CMP_NUM 4 | 25 | read_neon_element64(tmp, a->vd, 1, MO_64); |
24 | 26 | - accfn(tmp, tmp, rd1); | |
25 | -#define MCT_GT_MAX_VAL UINT64_MAX | 27 | - write_neon_element64(tmp, a->vd, 1, MO_64); |
26 | - | 28 | + accfn(rd1, tmp, rd1); |
27 | #define MCT_GT_COUNTER_STEP 0x100000000ULL | 29 | tcg_temp_free_i64(tmp); |
28 | #define MCT_LT_COUNTER_STEP 0x100000000ULL | 30 | - } else { |
29 | #define MCT_LT_CNT_LOW_LIMIT 0x100 | 31 | - write_neon_element64(rd0, a->vd, 0, MO_64); |
32 | - write_neon_element64(rd1, a->vd, 1, MO_64); | ||
33 | } | ||
34 | |||
35 | + write_neon_element64(rd0, a->vd, 0, MO_64); | ||
36 | + write_neon_element64(rd1, a->vd, 1, MO_64); | ||
37 | tcg_temp_free_i64(rd0); | ||
38 | tcg_temp_free_i64(rd1); | ||
39 | |||
40 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
41 | if (accfn) { | ||
42 | TCGv_i64 t64 = tcg_temp_new_i64(); | ||
43 | read_neon_element64(t64, a->vd, 0, MO_64); | ||
44 | - accfn(t64, t64, rn0_64); | ||
45 | - write_neon_element64(t64, a->vd, 0, MO_64); | ||
46 | + accfn(rn0_64, t64, rn0_64); | ||
47 | read_neon_element64(t64, a->vd, 1, MO_64); | ||
48 | - accfn(t64, t64, rn1_64); | ||
49 | - write_neon_element64(t64, a->vd, 1, MO_64); | ||
50 | + accfn(rn1_64, t64, rn1_64); | ||
51 | tcg_temp_free_i64(t64); | ||
52 | - } else { | ||
53 | - write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
54 | - write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
55 | } | ||
56 | + | ||
57 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
58 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
59 | tcg_temp_free_i64(rn0_64); | ||
60 | tcg_temp_free_i64(rn1_64); | ||
61 | return true; | ||
30 | -- | 62 | -- |
31 | 2.7.4 | 63 | 2.20.1 |
32 | 64 | ||
33 | 65 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When a timer is enabled before a reload value is set, the controller | 3 | We can use proper widening loads to extend 32-bit inputs, |
4 | waits for a reload value to be set before starting decrementing. This | 4 | and skip the "widenfn" step. |
5 | fix tries to cover that case by changing the timer expiry only when | ||
6 | a reload value is valid. | ||
7 | 5 | ||
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Andrew Jeffery <andrew@aj.id.au> | 7 | Message-id: 20201030022618.785675-12-richard.henderson@linaro.org |
10 | Message-id: 1496739312-32304-1-git-send-email-clg@kaod.org | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 10 | --- |
13 | hw/timer/aspeed_timer.c | 37 +++++++++++++++++++++++++++++-------- | 11 | target/arm/translate.c | 6 +++ |
14 | 1 file changed, 29 insertions(+), 8 deletions(-) | 12 | target/arm/translate-neon.c.inc | 66 ++++++++++++++++++--------------- |
13 | 2 files changed, 43 insertions(+), 29 deletions(-) | ||
15 | 14 | ||
16 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | 15 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/timer/aspeed_timer.c | 17 | --- a/target/arm/translate.c |
19 | +++ b/hw/timer/aspeed_timer.c | 18 | +++ b/target/arm/translate.c |
20 | @@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t) | 19 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) |
21 | next = seq[1]; | 20 | long off = neon_element_offset(reg, ele, memop); |
22 | } else if (now < seq[2]) { | 21 | |
23 | next = seq[2]; | 22 | switch (memop) { |
24 | - } else { | 23 | + case MO_SL: |
25 | + } else if (t->reload) { | 24 | + tcg_gen_ld32s_i64(dest, cpu_env, off); |
26 | reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate); | 25 | + break; |
27 | t->start = now - ((now - t->start) % reload_ns); | 26 | + case MO_UL: |
28 | + } else { | 27 | + tcg_gen_ld32u_i64(dest, cpu_env, off); |
29 | + /* no reload value, return 0 */ | 28 | + break; |
30 | + break; | 29 | case MO_Q: |
31 | } | 30 | tcg_gen_ld_i64(dest, cpu_env, off); |
31 | break; | ||
32 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/translate-neon.c.inc | ||
35 | +++ b/target/arm/translate-neon.c.inc | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) | ||
37 | static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
38 | NeonGenWidenFn *widenfn, | ||
39 | NeonGenTwo64OpFn *opfn, | ||
40 | - bool src1_wide) | ||
41 | + int src1_mop, int src2_mop) | ||
42 | { | ||
43 | /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */ | ||
44 | TCGv_i64 rn0_64, rn1_64, rm_64; | ||
45 | - TCGv_i32 rm; | ||
46 | |||
47 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
48 | return false; | ||
49 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
50 | return false; | ||
32 | } | 51 | } |
33 | 52 | ||
34 | return next; | 53 | - if (!widenfn || !opfn) { |
54 | + if (!opfn) { | ||
55 | /* size == 3 case, which is an entirely different insn group */ | ||
56 | return false; | ||
57 | } | ||
58 | |||
59 | - if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { | ||
60 | + if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) { | ||
61 | return false; | ||
62 | } | ||
63 | |||
64 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
65 | rn1_64 = tcg_temp_new_i64(); | ||
66 | rm_64 = tcg_temp_new_i64(); | ||
67 | |||
68 | - if (src1_wide) { | ||
69 | - read_neon_element64(rn0_64, a->vn, 0, MO_64); | ||
70 | + if (src1_mop >= 0) { | ||
71 | + read_neon_element64(rn0_64, a->vn, 0, src1_mop); | ||
72 | } else { | ||
73 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
74 | read_neon_element32(tmp, a->vn, 0, MO_32); | ||
75 | widenfn(rn0_64, tmp); | ||
76 | tcg_temp_free_i32(tmp); | ||
77 | } | ||
78 | - rm = tcg_temp_new_i32(); | ||
79 | - read_neon_element32(rm, a->vm, 0, MO_32); | ||
80 | + if (src2_mop >= 0) { | ||
81 | + read_neon_element64(rm_64, a->vm, 0, src2_mop); | ||
82 | + } else { | ||
83 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
84 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
85 | + widenfn(rm_64, tmp); | ||
86 | + tcg_temp_free_i32(tmp); | ||
87 | + } | ||
88 | |||
89 | - widenfn(rm_64, rm); | ||
90 | - tcg_temp_free_i32(rm); | ||
91 | opfn(rn0_64, rn0_64, rm_64); | ||
92 | |||
93 | /* | ||
94 | * Load second pass inputs before storing the first pass result, to | ||
95 | * avoid incorrect results if a narrow input overlaps with the result. | ||
96 | */ | ||
97 | - if (src1_wide) { | ||
98 | - read_neon_element64(rn1_64, a->vn, 1, MO_64); | ||
99 | + if (src1_mop >= 0) { | ||
100 | + read_neon_element64(rn1_64, a->vn, 1, src1_mop); | ||
101 | } else { | ||
102 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
103 | read_neon_element32(tmp, a->vn, 1, MO_32); | ||
104 | widenfn(rn1_64, tmp); | ||
105 | tcg_temp_free_i32(tmp); | ||
106 | } | ||
107 | - rm = tcg_temp_new_i32(); | ||
108 | - read_neon_element32(rm, a->vm, 1, MO_32); | ||
109 | + if (src2_mop >= 0) { | ||
110 | + read_neon_element64(rm_64, a->vm, 1, src2_mop); | ||
111 | + } else { | ||
112 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
113 | + read_neon_element32(tmp, a->vm, 1, MO_32); | ||
114 | + widenfn(rm_64, tmp); | ||
115 | + tcg_temp_free_i32(tmp); | ||
116 | + } | ||
117 | |||
118 | write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
119 | |||
120 | - widenfn(rm_64, rm); | ||
121 | - tcg_temp_free_i32(rm); | ||
122 | opfn(rn1_64, rn1_64, rm_64); | ||
123 | write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
124 | |||
125 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
126 | return true; | ||
35 | } | 127 | } |
36 | 128 | ||
37 | +static void aspeed_timer_mod(AspeedTimer *t) | 129 | -#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ |
38 | +{ | 130 | +#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \ |
39 | + uint64_t next = calculate_next(t); | 131 | static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ |
40 | + if (next) { | 132 | { \ |
41 | + timer_mod(&t->timer, next); | 133 | static NeonGenWidenFn * const widenfn[] = { \ |
42 | + } | 134 | gen_helper_neon_widen_##S##8, \ |
43 | +} | 135 | gen_helper_neon_widen_##S##16, \ |
44 | + | 136 | - tcg_gen_##EXT##_i32_i64, \ |
45 | static void aspeed_timer_expire(void *opaque) | 137 | - NULL, \ |
46 | { | 138 | + NULL, NULL, \ |
47 | AspeedTimer *t = opaque; | 139 | }; \ |
48 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_expire(void *opaque) | 140 | static NeonGenTwo64OpFn * const addfn[] = { \ |
49 | qemu_set_irq(t->irq, t->level); | 141 | gen_helper_neon_##OP##l_u16, \ |
142 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
143 | tcg_gen_##OP##_i64, \ | ||
144 | NULL, \ | ||
145 | }; \ | ||
146 | - return do_prewiden_3d(s, a, widenfn[a->size], \ | ||
147 | - addfn[a->size], SRC1WIDE); \ | ||
148 | + int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1; \ | ||
149 | + return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \ | ||
150 | + SRC1WIDE ? MO_Q : narrow_mop, \ | ||
151 | + narrow_mop); \ | ||
50 | } | 152 | } |
51 | 153 | ||
52 | - timer_mod(&t->timer, calculate_next(t)); | 154 | -DO_PREWIDEN(VADDL_S, s, ext, add, false) |
53 | + aspeed_timer_mod(t); | 155 | -DO_PREWIDEN(VADDL_U, u, extu, add, false) |
54 | } | 156 | -DO_PREWIDEN(VSUBL_S, s, ext, sub, false) |
55 | 157 | -DO_PREWIDEN(VSUBL_U, u, extu, sub, false) | |
56 | static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg) | 158 | -DO_PREWIDEN(VADDW_S, s, ext, add, true) |
57 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, | 159 | -DO_PREWIDEN(VADDW_U, u, extu, add, true) |
58 | uint32_t value) | 160 | -DO_PREWIDEN(VSUBW_S, s, ext, sub, true) |
59 | { | 161 | -DO_PREWIDEN(VSUBW_U, u, extu, sub, true) |
60 | AspeedTimer *t; | 162 | +DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN) |
61 | + uint32_t old_reload; | 163 | +DO_PREWIDEN(VADDL_U, u, add, false, 0) |
62 | 164 | +DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN) | |
63 | trace_aspeed_timer_set_value(timer, reg, value); | 165 | +DO_PREWIDEN(VSUBL_U, u, sub, false, 0) |
64 | t = &s->timers[timer]; | 166 | +DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN) |
65 | switch (reg) { | 167 | +DO_PREWIDEN(VADDW_U, u, add, true, 0) |
66 | + case TIMER_REG_RELOAD: | 168 | +DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN) |
67 | + old_reload = t->reload; | 169 | +DO_PREWIDEN(VSUBW_U, u, sub, true, 0) |
68 | + t->reload = value; | 170 | |
69 | + | 171 | static bool do_narrow_3d(DisasContext *s, arg_3diff *a, |
70 | + /* If the reload value was not previously set, or zero, and | 172 | NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) |
71 | + * the current value is valid, try to start the timer if it is | ||
72 | + * enabled. | ||
73 | + */ | ||
74 | + if (old_reload || !t->reload) { | ||
75 | + break; | ||
76 | + } | ||
77 | + | ||
78 | case TIMER_REG_STATUS: | ||
79 | if (timer_enabled(t)) { | ||
80 | uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
81 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, | ||
82 | uint32_t rate = calculate_rate(t); | ||
83 | |||
84 | t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate); | ||
85 | - timer_mod(&t->timer, calculate_next(t)); | ||
86 | + aspeed_timer_mod(t); | ||
87 | } | ||
88 | break; | ||
89 | - case TIMER_REG_RELOAD: | ||
90 | - t->reload = value; | ||
91 | - break; | ||
92 | case TIMER_REG_MATCH_FIRST: | ||
93 | case TIMER_REG_MATCH_SECOND: | ||
94 | t->match[reg - 2] = value; | ||
95 | if (timer_enabled(t)) { | ||
96 | - timer_mod(&t->timer, calculate_next(t)); | ||
97 | + aspeed_timer_mod(t); | ||
98 | } | ||
99 | break; | ||
100 | default: | ||
101 | @@ -XXX,XX +XXX,XX @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable) | ||
102 | trace_aspeed_timer_ctrl_enable(t->id, enable); | ||
103 | if (enable) { | ||
104 | t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
105 | - timer_mod(&t->timer, calculate_next(t)); | ||
106 | + aspeed_timer_mod(t); | ||
107 | } else { | ||
108 | timer_del(&t->timer); | ||
109 | } | ||
110 | -- | 173 | -- |
111 | 2.7.4 | 174 | 2.20.1 |
112 | 175 | ||
113 | 176 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error | ||
2 | meant we were using the H4() address swizzler macro rather than the | ||
3 | H2() which is required for 2-byte data. This had no effect on | ||
4 | little-endian hosts but meant we put the result data into the | ||
5 | destination Dreg in the wrong order on big-endian hosts. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 20201028191712.4910-2-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/vec_helper.c | 8 ++++---- | ||
13 | 1 file changed, 4 insertions(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/vec_helper.c | ||
18 | +++ b/target/arm/vec_helper.c | ||
19 | @@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t) | ||
20 | r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \ | ||
21 | r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \ | ||
22 | \ | ||
23 | - d[H4(0)] = r0; \ | ||
24 | - d[H4(1)] = r1; \ | ||
25 | - d[H4(2)] = r2; \ | ||
26 | - d[H4(3)] = r3; \ | ||
27 | + d[H2(0)] = r0; \ | ||
28 | + d[H2(1)] = r1; \ | ||
29 | + d[H2(2)] = r2; \ | ||
30 | + d[H2(3)] = r3; \ | ||
31 | } | ||
32 | |||
33 | DO_NEON_PAIRWISE(neon_padd, add) | ||
34 | -- | ||
35 | 2.20.1 | ||
36 | |||
37 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | The helper functions for performing the udot/sdot operations against |
---|---|---|---|
2 | a scalar were not using an address-swizzling macro when converting | ||
3 | the index of the scalar element into a pointer into the vm array. | ||
4 | This had no effect on little-endian hosts but meant we generated | ||
5 | incorrect results on big-endian hosts. | ||
2 | 6 | ||
3 | Fix checkpatch errors: | 7 | For these insns, the index is indexing over group of 4 8-bit values, |
4 | 1. ERROR: spaces required around that '+' (ctx:VxV) | 8 | so 32 bits per indexed entity, and H4() is therefore what we want. |
5 | 2. ERROR: spaces required around that '&' (ctx:VxV) | 9 | (For Neon the only possible input indexes are 0 and 1.) |
6 | 10 | ||
7 | No functional changes. | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |
9 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Message-id: 20201028191712.4910-3-peter.maydell@linaro.org |
13 | --- | 15 | --- |
14 | hw/timer/exynos4210_mct.c | 4 ++-- | 16 | target/arm/vec_helper.c | 4 ++-- |
15 | 1 file changed, 2 insertions(+), 2 deletions(-) | 17 | 1 file changed, 2 insertions(+), 2 deletions(-) |
16 | 18 | ||
17 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 19 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c |
18 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/timer/exynos4210_mct.c | 21 | --- a/target/arm/vec_helper.c |
20 | +++ b/hw/timer/exynos4210_mct.c | 22 | +++ b/target/arm/vec_helper.c |
21 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | 23 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) |
22 | { | 24 | intptr_t index = simd_data(desc); |
23 | uint32_t freq = s->freq; | 25 | uint32_t *d = vd; |
24 | s->freq = 24000000 / | 26 | int8_t *n = vn; |
25 | - ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) * | 27 | - int8_t *m_indexed = (int8_t *)vm + index * 4; |
26 | + ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg) + 1) * | 28 | + int8_t *m_indexed = (int8_t *)vm + H4(index) * 4; |
27 | MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); | 29 | |
28 | 30 | /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. | |
29 | if (freq != s->freq) { | 31 | * Otherwise opr_sz is a multiple of 16. |
30 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | 32 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) |
31 | 33 | intptr_t index = simd_data(desc); | |
32 | DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | 34 | uint32_t *d = vd; |
33 | 35 | uint8_t *n = vn; | |
34 | - if (offset&0x4) { | 36 | - uint8_t *m_indexed = (uint8_t *)vm + index * 4; |
35 | + if (offset & 0x4) { | 37 | + uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4; |
36 | s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | 38 | |
37 | } else { | 39 | /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. |
38 | s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | 40 | * Otherwise opr_sz is a multiple of 16. |
39 | -- | 41 | -- |
40 | 2.7.4 | 42 | 2.20.1 |
41 | 43 | ||
42 | 44 | diff view generated by jsdifflib |
1 | From: Pranith Kumar <bobby.prani@gmail.com> | 1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Tested and confirmed that the stretch i386 debian qcow2 image on a | 3 | HCR should be applied when NS is set, not when it is cleared. |
4 | raspberry pi 2 works. | ||
5 | 4 | ||
6 | Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/> | 5 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
7 | Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
9 | Message-id: 20170418191817.10430-1-bobby.prani@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 8 | --- |
12 | include/qemu/timer.h | 5 ++--- | 9 | target/arm/helper.c | 5 ++--- |
13 | 1 file changed, 2 insertions(+), 3 deletions(-) | 10 | 1 file changed, 2 insertions(+), 3 deletions(-) |
14 | 11 | ||
15 | diff --git a/include/qemu/timer.h b/include/qemu/timer.h | 12 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/qemu/timer.h | 14 | --- a/target/arm/helper.c |
18 | +++ b/include/qemu/timer.h | 15 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ static inline int64_t cpu_get_host_ticks(void) | 16 | @@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
20 | /* The host CPU doesn't have an easily accessible cycle counter. | 17 | |
21 | Just return a monotonically increasing value. This will be | 18 | /* |
22 | totally wrong, but hopefully better than nothing. */ | 19 | * Non-IS variants of TLB operations are upgraded to |
23 | -static inline int64_t cpu_get_host_ticks (void) | 20 | - * IS versions if we are at NS EL1 and HCR_EL2.FB is set to |
24 | +static inline int64_t cpu_get_host_ticks(void) | 21 | + * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to |
22 | * force broadcast of these operations. | ||
23 | */ | ||
24 | static bool tlb_force_broadcast(CPUARMState *env) | ||
25 | { | 25 | { |
26 | - static int64_t ticks = 0; | 26 | - return (env->cp15.hcr_el2 & HCR_FB) && |
27 | - return ticks++; | 27 | - arm_current_el(env) == 1 && arm_is_secure_below_el3(env); |
28 | + return get_clock(); | 28 | + return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); |
29 | } | 29 | } |
30 | #endif | 30 | |
31 | 31 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
32 | -- | 32 | -- |
33 | 2.7.4 | 33 | 2.20.1 |
34 | 34 | ||
35 | 35 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | In some circumstances, we don't want to abort if the | 3 | Secure mode is not exempted from checking SCR_EL3.TLOR, and in the |
4 | kvm_device_access fails. This will be the case during ITS | 4 | future HCR_EL2.TLOR when S-EL2 is enabled. |
5 | migration, in case the ITS table save/restore fails because | ||
6 | the guest did not program the vITS correctly. So let's pass an | ||
7 | error object to the function and return the ioctl value. New | ||
8 | callers will be able to make a decision upon this returned | ||
9 | value. | ||
10 | 5 | ||
11 | Existing callers pass &error_abort which will cause the | 6 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
12 | function to abort on failure. | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | |||
14 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
15 | Reviewed-by: Juan Quintela <quintela@redhat.com> | ||
16 | Reviewed-by: Peter Xu <peterx@redhat.com> | ||
17 | Message-id: 1497023553-18411-2-git-send-email-eric.auger@redhat.com | ||
18 | [PMM: wrapped long line] | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | --- | 9 | --- |
21 | include/sysemu/kvm.h | 11 +++++++---- | 10 | target/arm/helper.c | 19 +++++-------------- |
22 | hw/intc/arm_gic_kvm.c | 9 +++++---- | 11 | 1 file changed, 5 insertions(+), 14 deletions(-) |
23 | hw/intc/arm_gicv3_its_kvm.c | 2 +- | ||
24 | hw/intc/arm_gicv3_kvm.c | 14 +++++++------- | ||
25 | kvm-all.c | 14 ++++++++------ | ||
26 | 5 files changed, 28 insertions(+), 22 deletions(-) | ||
27 | 12 | ||
28 | diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h | 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
29 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/include/sysemu/kvm.h | 15 | --- a/target/arm/helper.c |
31 | +++ b/include/sysemu/kvm.h | 16 | +++ b/target/arm/helper.c |
32 | @@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int fd, uint32_t group, uint64_t attr); | 17 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) |
33 | * @attr: the attribute of that group to set or get | 18 | #endif |
34 | * @val: pointer to a storage area for the value | 19 | |
35 | * @write: true for set and false for get operation | 20 | /* Shared logic between LORID and the rest of the LOR* registers. |
36 | + * @errp: error object handle | 21 | - * Secure state has already been delt with. |
37 | * | 22 | + * Secure state exclusion has already been dealt with. |
38 | - * This function is not allowed to fail. Use kvm_device_check_attr() | ||
39 | - * in order to check for the availability of optional attributes. | ||
40 | + * Returns: 0 on success | ||
41 | + * < 0 on error | ||
42 | + * Use kvm_device_check_attr() in order to check for the availability | ||
43 | + * of optional attributes. | ||
44 | */ | 23 | */ |
45 | -void kvm_device_access(int fd, int group, uint64_t attr, | 24 | -static CPAccessResult access_lor_ns(CPUARMState *env) |
46 | - void *val, bool write); | 25 | +static CPAccessResult access_lor_ns(CPUARMState *env, |
47 | +int kvm_device_access(int fd, int group, uint64_t attr, | 26 | + const ARMCPRegInfo *ri, bool isread) |
48 | + void *val, bool write, Error **errp); | ||
49 | |||
50 | /** | ||
51 | * kvm_create_device - create a KVM device for the device control API | ||
52 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/hw/intc/arm_gic_kvm.c | ||
55 | +++ b/hw/intc/arm_gic_kvm.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void kvm_gicd_access(GICState *s, int offset, int cpu, | ||
57 | uint32_t *val, bool write) | ||
58 | { | 27 | { |
59 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, | 28 | int el = arm_current_el(env); |
60 | - KVM_VGIC_ATTR(offset, cpu), val, write); | 29 | |
61 | + KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); | 30 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env) |
31 | return CP_ACCESS_OK; | ||
62 | } | 32 | } |
63 | 33 | ||
64 | static void kvm_gicc_access(GICState *s, int offset, int cpu, | 34 | -static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, |
65 | uint32_t *val, bool write) | 35 | - bool isread) |
36 | -{ | ||
37 | - if (arm_is_secure_below_el3(env)) { | ||
38 | - /* Access ok in secure mode. */ | ||
39 | - return CP_ACCESS_OK; | ||
40 | - } | ||
41 | - return access_lor_ns(env); | ||
42 | -} | ||
43 | - | ||
44 | static CPAccessResult access_lor_other(CPUARMState *env, | ||
45 | const ARMCPRegInfo *ri, bool isread) | ||
66 | { | 46 | { |
67 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS, | 47 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env, |
68 | - KVM_VGIC_ATTR(offset, cpu), val, write); | 48 | /* Access denied in secure mode. */ |
69 | + KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); | 49 | return CP_ACCESS_TRAP; |
50 | } | ||
51 | - return access_lor_ns(env); | ||
52 | + return access_lor_ns(env, ri, isread); | ||
70 | } | 53 | } |
71 | 54 | ||
72 | #define for_each_irq_reg(_ctr, _max_irq, _field_width) \ | 55 | /* |
73 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) | 56 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = { |
74 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) { | 57 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
75 | uint32_t numirqs = s->num_irq; | 58 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, |
76 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, | 59 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, |
77 | - &numirqs, true); | 60 | - .access = PL1_R, .accessfn = access_lorid, |
78 | + &numirqs, true, &error_abort); | 61 | + .access = PL1_R, .accessfn = access_lor_ns, |
79 | } | 62 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
80 | /* Tell the kernel to complete VGIC initialization now */ | 63 | REGINFO_SENTINEL |
81 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 64 | }; |
82 | KVM_DEV_ARM_VGIC_CTRL_INIT)) { | ||
83 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
84 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | ||
85 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, | ||
86 | + &error_abort); | ||
87 | } | ||
88 | } else if (ret != -ENODEV && ret != -ENOTSUP) { | ||
89 | error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); | ||
90 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
93 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) | ||
95 | |||
96 | /* explicit init of the ITS */ | ||
97 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
98 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | ||
99 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); | ||
100 | |||
101 | /* register the base address */ | ||
102 | kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, | ||
103 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/hw/intc/arm_gicv3_kvm.c | ||
106 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicd_access(GICv3State *s, int offset, | ||
108 | { | ||
109 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, | ||
110 | KVM_VGIC_ATTR(offset, 0), | ||
111 | - val, write); | ||
112 | + val, write, &error_abort); | ||
113 | } | ||
114 | |||
115 | static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, | ||
116 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, | ||
117 | { | ||
118 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, | ||
119 | KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), | ||
120 | - val, write); | ||
121 | + val, write, &error_abort); | ||
122 | } | ||
123 | |||
124 | static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, | ||
125 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, | ||
126 | { | ||
127 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, | ||
128 | KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), | ||
129 | - val, write); | ||
130 | + val, write, &error_abort); | ||
131 | } | ||
132 | |||
133 | static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, | ||
134 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, | ||
135 | KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | | ||
136 | (VGIC_LEVEL_INFO_LINE_LEVEL << | ||
137 | KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), | ||
138 | - val, write); | ||
139 | + val, write, &error_abort); | ||
140 | } | ||
141 | |||
142 | /* Loop through each distributor IRQ related register; since bits | ||
143 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) | ||
144 | /* Initialize to actual HW supported configuration */ | ||
145 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, | ||
146 | KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), | ||
147 | - &c->icc_ctlr_el1[GICV3_NS], false); | ||
148 | + &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); | ||
149 | |||
150 | c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; | ||
151 | } | ||
152 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | ||
153 | } | ||
154 | |||
155 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, | ||
156 | - 0, &s->num_irq, true); | ||
157 | + 0, &s->num_irq, true, &error_abort); | ||
158 | |||
159 | /* Tell the kernel to complete VGIC initialization now */ | ||
160 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
161 | - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); | ||
162 | + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); | ||
163 | |||
164 | kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, | ||
165 | KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd); | ||
166 | diff --git a/kvm-all.c b/kvm-all.c | ||
167 | index XXXXXXX..XXXXXXX 100644 | ||
168 | --- a/kvm-all.c | ||
169 | +++ b/kvm-all.c | ||
170 | @@ -XXX,XX +XXX,XX @@ | ||
171 | #include "qemu/option.h" | ||
172 | #include "qemu/config-file.h" | ||
173 | #include "qemu/error-report.h" | ||
174 | +#include "qapi/error.h" | ||
175 | #include "hw/hw.h" | ||
176 | #include "hw/pci/msi.h" | ||
177 | #include "hw/pci/msix.h" | ||
178 | @@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int dev_fd, uint32_t group, uint64_t attr) | ||
179 | return kvm_device_ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute) ? 0 : 1; | ||
180 | } | ||
181 | |||
182 | -void kvm_device_access(int fd, int group, uint64_t attr, | ||
183 | - void *val, bool write) | ||
184 | +int kvm_device_access(int fd, int group, uint64_t attr, | ||
185 | + void *val, bool write, Error **errp) | ||
186 | { | ||
187 | struct kvm_device_attr kvmattr; | ||
188 | int err; | ||
189 | @@ -XXX,XX +XXX,XX @@ void kvm_device_access(int fd, int group, uint64_t attr, | ||
190 | write ? KVM_SET_DEVICE_ATTR : KVM_GET_DEVICE_ATTR, | ||
191 | &kvmattr); | ||
192 | if (err < 0) { | ||
193 | - error_report("KVM_%s_DEVICE_ATTR failed: %s", | ||
194 | - write ? "SET" : "GET", strerror(-err)); | ||
195 | - error_printf("Group %d attr 0x%016" PRIx64 "\n", group, attr); | ||
196 | - abort(); | ||
197 | + error_setg_errno(errp, -err, | ||
198 | + "KVM_%s_DEVICE_ATTR failed: Group %d " | ||
199 | + "attr 0x%016" PRIx64, | ||
200 | + write ? "SET" : "GET", group, attr); | ||
201 | } | ||
202 | + return err; | ||
203 | } | ||
204 | |||
205 | /* Return 1 on success, 0 on failure */ | ||
206 | -- | 65 | -- |
207 | 2.7.4 | 66 | 2.20.1 |
208 | 67 | ||
209 | 68 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | If we're using the capstone disassembler, disassembly of a run of |
---|---|---|---|
2 | instructions more than 32 bytes long disassembles the wrong data for | ||
3 | instructions beyond the 32 byte mark: | ||
2 | 4 | ||
3 | The static array of interrupt combiner mappings is not modified so it | 5 | (qemu) xp /16x 0x100 |
4 | can be made const for code safeness. | 6 | 0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000 |
7 | 0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000 | ||
8 | 0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574 | ||
9 | 0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000 | ||
10 | (qemu) xp /16i 0x100 | ||
11 | 0x00000100: 00000005 andeq r0, r0, r5 | ||
12 | 0x00000104: 54410001 strbpl r0, [r1], #-1 | ||
13 | 0x00000108: 00000001 andeq r0, r0, r1 | ||
14 | 0x0000010c: 00001000 andeq r1, r0, r0 | ||
15 | 0x00000110: 00000000 andeq r0, r0, r0 | ||
16 | 0x00000114: 00000004 andeq r0, r0, r4 | ||
17 | 0x00000118: 54410002 strbpl r0, [r1], #-2 | ||
18 | 0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c | ||
19 | 0x00000120: 54410001 strbpl r0, [r1], #-1 | ||
20 | 0x00000124: 00000001 andeq r0, r0, r1 | ||
21 | 0x00000128: 00001000 andeq r1, r0, r0 | ||
22 | 0x0000012c: 00000000 andeq r0, r0, r0 | ||
23 | 0x00000130: 00000004 andeq r0, r0, r4 | ||
24 | 0x00000134: 54410002 strbpl r0, [r1], #-2 | ||
25 | 0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c | ||
26 | 0x0000013c: 00000000 andeq r0, r0, r0 | ||
5 | 27 | ||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 28 | Here the disassembly of 0x120..0x13f is using the data that is in |
29 | 0x104..0x123. | ||
30 | |||
31 | This is caused by passing the wrong value to the read_memory_func(). | ||
32 | The intention is that at this point in the loop the 'cap_buf' buffer | ||
33 | already contains 'csize' bytes of data for the instruction at guest | ||
34 | addr 'pc', and we want to read in an extra 'tsize' bytes. Those | ||
35 | extra bytes are therefore at 'pc + csize', not 'pc'. On the first | ||
36 | time through the loop 'csize' happens to be zero, so the initial read | ||
37 | of 32 bytes into cap_buf is correct and as long as the disassembly | ||
38 | never needs to read more data we return the correct information. | ||
39 | |||
40 | Use the correct guest address in the call to read_memory_func(). | ||
41 | |||
42 | Cc: qemu-stable@nongnu.org | ||
43 | Fixes: https://bugs.launchpad.net/qemu/+bug/1900779 | ||
44 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 45 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 46 | Message-id: 20201022132445.25039-1-peter.maydell@linaro.org |
9 | --- | 47 | --- |
10 | hw/intc/exynos4210_gic.c | 2 +- | 48 | disas/capstone.c | 2 +- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 49 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 50 | ||
13 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 51 | diff --git a/disas/capstone.c b/disas/capstone.c |
14 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/intc/exynos4210_gic.c | 53 | --- a/disas/capstone.c |
16 | +++ b/hw/intc/exynos4210_gic.c | 54 | +++ b/disas/capstone.c |
17 | @@ -XXX,XX +XXX,XX @@ enum ExtInt { | 55 | @@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count) |
18 | * which is INTG16 in Internal Interrupt Combiner. | 56 | |
19 | */ | 57 | /* Make certain that we can make progress. */ |
20 | 58 | assert(tsize != 0); | |
21 | -static uint32_t | 59 | - info->read_memory_func(pc, cap_buf + csize, tsize, info); |
22 | +static const uint32_t | 60 | + info->read_memory_func(pc + csize, cap_buf + csize, tsize, info); |
23 | combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 61 | csize += tsize; |
24 | /* int combiner groups 16-19 */ | 62 | |
25 | { }, { }, { }, { }, | 63 | if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) { |
26 | -- | 64 | -- |
27 | 2.7.4 | 65 | 2.20.1 |
28 | 66 | ||
29 | 67 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Use a define for a9mpcore_priv device type name instead of hard-coded | 3 | Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. |
4 | string. | 4 | This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): |
5 | 5 | ||
6 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 6 | CID 1432363 (#1 of 1): Unintentional integer overflow: |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | |
8 | overflow_before_widen: | ||
9 | Potentially overflowing expression 1 << scale with type int | ||
10 | (32 bits, signed) is evaluated using 32-bit arithmetic, and | ||
11 | then used in a context that expects an expression of type | ||
12 | hwaddr (64 bits, unsigned). | ||
13 | |||
14 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
15 | Acked-by: Eric Auger <eric.auger@redhat.com> | ||
16 | Message-id: 20201030144617.1535064-1-philmd@redhat.com | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 19 | --- |
10 | hw/arm/exynos4210.c | 3 ++- | 20 | hw/arm/smmuv3.c | 3 ++- |
11 | 1 file changed, 2 insertions(+), 1 deletion(-) | 21 | 1 file changed, 2 insertions(+), 1 deletion(-) |
12 | 22 | ||
13 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 23 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c |
14 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/exynos4210.c | 25 | --- a/hw/arm/smmuv3.c |
16 | +++ b/hw/arm/exynos4210.c | 26 | +++ b/hw/arm/smmuv3.c |
17 | @@ -XXX,XX +XXX,XX @@ | 27 | @@ -XXX,XX +XXX,XX @@ |
18 | #include "qemu-common.h" | 28 | */ |
19 | #include "qemu/log.h" | 29 | |
20 | #include "cpu.h" | 30 | #include "qemu/osdep.h" |
21 | +#include "hw/cpu/a9mpcore.h" | 31 | +#include "qemu/bitops.h" |
22 | #include "hw/boards.h" | 32 | #include "hw/irq.h" |
23 | #include "sysemu/sysemu.h" | ||
24 | #include "hw/sysbus.h" | 33 | #include "hw/sysbus.h" |
25 | @@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | 34 | #include "migration/vmstate.h" |
35 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) | ||
36 | scale = CMD_SCALE(cmd); | ||
37 | num = CMD_NUM(cmd); | ||
38 | ttl = CMD_TTL(cmd); | ||
39 | - num_pages = (num + 1) * (1 << (scale)); | ||
40 | + num_pages = (num + 1) * BIT_ULL(scale); | ||
26 | } | 41 | } |
27 | 42 | ||
28 | /* Private memory region and Internal GIC */ | 43 | if (type == SMMU_CMD_TLBI_NH_VA) { |
29 | - dev = qdev_create(NULL, "a9mpcore_priv"); | ||
30 | + dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); | ||
31 | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
32 | qdev_init_nofail(dev); | ||
33 | busdev = SYS_BUS_DEVICE(dev); | ||
34 | -- | 44 | -- |
35 | 2.7.4 | 45 | 2.20.1 |
36 | 46 | ||
37 | 47 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | There are to SysBusDevice variables in exynos4210_gic_realize() | 3 | When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so |
4 | function: one for the device itself and second for arm_gic device. Add | 4 | that SVE will not trap to EL3. |
5 | a prefix "gic" to the second one so it will be easier to understand the | ||
6 | code. | ||
7 | 5 | ||
8 | While at it, put local uninitialized 'i' variable at the end, next to | 6 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> |
9 | other uninitialized ones. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | 8 | Message-id: 20201030151541.11976-1-remi@remlab.net | |
11 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 10 | --- |
16 | hw/intc/exynos4210_gic.c | 12 ++++++------ | 11 | hw/arm/boot.c | 3 +++ |
17 | 1 file changed, 6 insertions(+), 6 deletions(-) | 12 | 1 file changed, 3 insertions(+) |
18 | 13 | ||
19 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
20 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/intc/exynos4210_gic.c | 16 | --- a/hw/arm/boot.c |
22 | +++ b/hw/intc/exynos4210_gic.c | 17 | +++ b/hw/arm/boot.c |
23 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | 18 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) |
24 | DeviceState *dev = DEVICE(obj); | 19 | if (cpu_isar_feature(aa64_mte, cpu)) { |
25 | Exynos4210GicState *s = EXYNOS4210_GIC(obj); | 20 | env->cp15.scr_el3 |= SCR_ATA; |
26 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 21 | } |
27 | - uint32_t i; | 22 | + if (cpu_isar_feature(aa64_sve, cpu)) { |
28 | const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; | 23 | + env->cp15.cptr_el[3] |= CPTR_EZ; |
29 | const char dist_prefix[] = "exynos4210-gic-alias_dist"; | 24 | + } |
30 | char cpu_alias_name[sizeof(cpu_prefix) + 3]; | 25 | /* AArch64 kernels never boot in secure mode */ |
31 | char dist_alias_name[sizeof(cpu_prefix) + 3]; | 26 | assert(!info->secure_boot); |
32 | - SysBusDevice *busdev; | 27 | /* This hook is only supported for AArch32 currently: |
33 | + SysBusDevice *gicbusdev; | ||
34 | + uint32_t i; | ||
35 | |||
36 | s->gic = qdev_create(NULL, "arm_gic"); | ||
37 | qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); | ||
38 | qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); | ||
39 | qdev_init_nofail(s->gic); | ||
40 | - busdev = SYS_BUS_DEVICE(s->gic); | ||
41 | + gicbusdev = SYS_BUS_DEVICE(s->gic); | ||
42 | |||
43 | /* Pass through outbound IRQ lines from the GIC */ | ||
44 | - sysbus_pass_irq(sbd, busdev); | ||
45 | + sysbus_pass_irq(sbd, gicbusdev); | ||
46 | |||
47 | /* Pass through inbound GPIO lines to the GIC */ | ||
48 | qdev_init_gpio_in(dev, exynos4210_gic_set_irq, | ||
49 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | ||
50 | sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); | ||
51 | memory_region_init_alias(&s->cpu_alias[i], obj, | ||
52 | cpu_alias_name, | ||
53 | - sysbus_mmio_get_region(busdev, 1), | ||
54 | + sysbus_mmio_get_region(gicbusdev, 1), | ||
55 | 0, | ||
56 | EXYNOS4210_GIC_CPU_REGION_SIZE); | ||
57 | memory_region_add_subregion(&s->cpu_container, | ||
58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj) | ||
59 | sprintf(dist_alias_name, "%s%x", dist_prefix, i); | ||
60 | memory_region_init_alias(&s->dist_alias[i], obj, | ||
61 | dist_alias_name, | ||
62 | - sysbus_mmio_get_region(busdev, 0), | ||
63 | + sysbus_mmio_get_region(gicbusdev, 0), | ||
64 | 0, | ||
65 | EXYNOS4210_GIC_DIST_REGION_SIZE); | ||
66 | memory_region_add_subregion(&s->dist_container, | ||
67 | -- | 28 | -- |
68 | 2.7.4 | 29 | 2.20.1 |
69 | 30 | ||
70 | 31 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: AlexChen <alex.chen@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | This patch adds the flush of the LPI pending bits into the | 3 | In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before |
4 | redistributor pending tables. This happens on VM stop. | 4 | being check if it is valid, which may lead to NULL pointer dereference. |
5 | So move the assignment to surface after checking that the omap_lcd is valid | ||
6 | and move surface_bits_per_pixel(surface) to after the surface assignment. | ||
5 | 7 | ||
6 | There is no explicit restore as the tables are implicitly sync'ed | 8 | Reported-by: Euler Robot <euler.robot@huawei.com> |
7 | on ITS table restore and on LPI enable at redistributor level. | 9 | Signed-off-by: AlexChen <alex.chen@huawei.com> |
8 | 10 | Message-id: 5F9CDB8A.9000001@huawei.com | |
9 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
10 | Message-id: 1497023553-18411-4-git-send-email-eric.auger@redhat.com | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 13 | --- |
14 | hw/intc/arm_gicv3_kvm.c | 34 ++++++++++++++++++++++++++++++++++ | 14 | hw/display/omap_lcdc.c | 10 +++++++--- |
15 | 1 file changed, 34 insertions(+) | 15 | 1 file changed, 7 insertions(+), 3 deletions(-) |
16 | 16 | ||
17 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | 17 | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/intc/arm_gicv3_kvm.c | 19 | --- a/hw/display/omap_lcdc.c |
20 | +++ b/hw/intc/arm_gicv3_kvm.c | 20 | +++ b/hw/display/omap_lcdc.c |
21 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) |
22 | #include "hw/sysbus.h" | 22 | static void omap_update_display(void *opaque) |
23 | #include "qemu/error-report.h" | 23 | { |
24 | #include "sysemu/kvm.h" | 24 | struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; |
25 | +#include "sysemu/sysemu.h" | 25 | - DisplaySurface *surface = qemu_console_surface(omap_lcd->con); |
26 | #include "kvm_arm.h" | 26 | + DisplaySurface *surface; |
27 | #include "gicv3_internal.h" | 27 | draw_line_func draw_line; |
28 | #include "vgic_common.h" | 28 | int size, height, first, last; |
29 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | 29 | int width, linesize, step, bpp, frame_offset; |
30 | REGINFO_SENTINEL | 30 | hwaddr frame_base; |
31 | }; | 31 | |
32 | 32 | - if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable || | |
33 | +/** | 33 | - !surface_bits_per_pixel(surface)) { |
34 | + * vm_change_state_handler - VM change state callback aiming at flushing | 34 | + if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) { |
35 | + * RDIST pending tables into guest RAM | ||
36 | + * | ||
37 | + * The tables get flushed to guest RAM whenever the VM gets stopped. | ||
38 | + */ | ||
39 | +static void vm_change_state_handler(void *opaque, int running, | ||
40 | + RunState state) | ||
41 | +{ | ||
42 | + GICv3State *s = (GICv3State *)opaque; | ||
43 | + Error *err = NULL; | ||
44 | + int ret; | ||
45 | + | ||
46 | + if (running) { | ||
47 | + return; | 35 | + return; |
48 | + } | 36 | + } |
49 | + | 37 | + |
50 | + ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 38 | + surface = qemu_console_surface(omap_lcd->con); |
51 | + KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, | 39 | + if (!surface_bits_per_pixel(surface)) { |
52 | + NULL, true, &err); | 40 | return; |
53 | + if (err) { | ||
54 | + error_report_err(err); | ||
55 | + } | ||
56 | + if (ret < 0 && ret != -EFAULT) { | ||
57 | + abort(); | ||
58 | + } | ||
59 | +} | ||
60 | + | ||
61 | + | ||
62 | static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | ||
63 | { | ||
64 | GICv3State *s = KVM_ARM_GICV3(dev); | ||
65 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | ||
66 | return; | ||
67 | } | ||
68 | } | 41 | } |
69 | + if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 42 | |
70 | + KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { | ||
71 | + qemu_add_vm_change_state_handler(vm_change_state_handler, s); | ||
72 | + } | ||
73 | } | ||
74 | |||
75 | static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) | ||
76 | -- | 43 | -- |
77 | 2.7.4 | 44 | 2.20.1 |
78 | 45 | ||
79 | 46 | diff view generated by jsdifflib |
1 | From: Krzysztof Kozlowski <krzk@kernel.org> | 1 | From: AlexChen <alex.chen@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Statements under 'case' were in some places wrongly indented bringing | 3 | In exynos4210_fimd_update(), the pointer s is dereferinced before |
4 | confusion and making the code less readable. Remove also few unneeded | 4 | being check if it is valid, which may lead to NULL pointer dereference. |
5 | blank lines. No functional changes. | 5 | So move the assignment to global_width after checking that the s is valid. |
6 | 6 | ||
7 | Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> | 7 | Reported-by: Euler Robot <euler.robot@huawei.com> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Alex Chen <alex.chen@huawei.com> |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
10 | Message-id: 5F9F8D88.9030102@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++------------------------- | 13 | hw/display/exynos4210_fimd.c | 4 +++- |
13 | 1 file changed, 20 insertions(+), 25 deletions(-) | 14 | 1 file changed, 3 insertions(+), 1 deletion(-) |
14 | 15 | ||
15 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 16 | diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/timer/exynos4210_mct.c | 18 | --- a/hw/display/exynos4210_fimd.c |
18 | +++ b/hw/timer/exynos4210_mct.c | 19 | +++ b/hw/display/exynos4210_fimd.c |
19 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, | 20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque) |
20 | 21 | bool blend = false; | |
21 | case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): | 22 | uint8_t *host_fb_addr; |
22 | case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): | 23 | bool is_dirty = false; |
23 | - index = GET_G_COMP_IDX(offset); | 24 | - const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; |
24 | - shift = 8 * (offset & 0x4); | 25 | + int global_width; |
25 | - value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); | 26 | |
26 | + index = GET_G_COMP_IDX(offset); | 27 | if (!s || !s->console || !s->enabled || |
27 | + shift = 8 * (offset & 0x4); | 28 | surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { |
28 | + value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); | 29 | return; |
29 | break; | 30 | } |
30 | 31 | + | |
31 | case G_TCON: | 32 | + global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; |
32 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, | 33 | exynos4210_update_resolution(s); |
33 | lt_i = GET_L_TIMER_IDX(offset); | 34 | surface = qemu_console_surface(s->console); |
34 | |||
35 | value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]); | ||
36 | - | ||
37 | break; | ||
38 | |||
39 | case L0_TCON: case L1_TCON: | ||
40 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
41 | |||
42 | case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): | ||
43 | case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): | ||
44 | - index = GET_G_COMP_IDX(offset); | ||
45 | - shift = 8 * (offset & 0x4); | ||
46 | - s->g_timer.reg.comp[index] = | ||
47 | - (s->g_timer.reg.comp[index] & | ||
48 | - (((uint64_t)UINT32_MAX << 32) >> shift)) + | ||
49 | - (value << shift); | ||
50 | + index = GET_G_COMP_IDX(offset); | ||
51 | + shift = 8 * (offset & 0x4); | ||
52 | + s->g_timer.reg.comp[index] = | ||
53 | + (s->g_timer.reg.comp[index] & | ||
54 | + (((uint64_t)UINT32_MAX << 32) >> shift)) + | ||
55 | + (value << shift); | ||
56 | |||
57 | - DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | ||
58 | + DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); | ||
59 | |||
60 | - if (offset & 0x4) { | ||
61 | - s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | ||
62 | - } else { | ||
63 | - s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
64 | - } | ||
65 | + if (offset & 0x4) { | ||
66 | + s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); | ||
67 | + } else { | ||
68 | + s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); | ||
69 | + } | ||
70 | |||
71 | - exynos4210_gfrc_restart(s); | ||
72 | - break; | ||
73 | + exynos4210_gfrc_restart(s); | ||
74 | + break; | ||
75 | |||
76 | case G_TCON: | ||
77 | old_val = s->g_timer.reg.tcon; | ||
78 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
79 | break; | ||
80 | |||
81 | case G_INT_ENB: | ||
82 | - | ||
83 | /* Raise IRQ if transition from disabled to enabled and CSTAT pending */ | ||
84 | for (i = 0; i < MCT_GT_CMP_NUM; i++) { | ||
85 | if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon & | ||
86 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
87 | break; | ||
88 | |||
89 | case L0_TCNTB: case L1_TCNTB: | ||
90 | - | ||
91 | lt_i = GET_L_TIMER_IDX(offset); | ||
92 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
93 | |||
94 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
95 | break; | ||
96 | |||
97 | case L0_ICNTB: case L1_ICNTB: | ||
98 | - | ||
99 | lt_i = GET_L_TIMER_IDX(offset); | ||
100 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
101 | |||
102 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, | ||
103 | if (icntb_max[lt_i] < value) { | ||
104 | icntb_max[lt_i] = value; | ||
105 | } | ||
106 | -DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", | ||
107 | - lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); | ||
108 | + DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", | ||
109 | + lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); | ||
110 | #endif | ||
111 | -break; | ||
112 | + break; | ||
113 | |||
114 | case L0_FRCNTB: case L1_FRCNTB: | ||
115 | - | ||
116 | lt_i = GET_L_TIMER_IDX(offset); | ||
117 | index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); | ||
118 | 35 | ||
119 | -- | 36 | -- |
120 | 2.7.4 | 37 | 2.20.1 |
121 | 38 | ||
122 | 39 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to | ||
2 | armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el(). | ||
3 | This is incorrect when the security state being queried is not the | ||
4 | current one, because arm_current_el() uses the current security state | ||
5 | to determine which of the banked CONTROL.nPRIV bits to look at. | ||
6 | The effect was that if (for instance) Secure state was in privileged | ||
7 | mode but Non-Secure was not then we would return the wrong MMU index. | ||
1 | 8 | ||
9 | The only places where we are using this function in a way that could | ||
10 | trigger this bug are for the stack loads during a v8M function-return | ||
11 | and for the instruction fetch of a v8M SG insn. | ||
12 | |||
13 | Fix the bug by expanding out the M-profile version of the | ||
14 | arm_current_el() logic inline so it can use the passed in secstate | ||
15 | rather than env->v7m.secure. | ||
16 | |||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
19 | Message-id: 20201022164408.13214-1-peter.maydell@linaro.org | ||
20 | --- | ||
21 | target/arm/m_helper.c | 3 ++- | ||
22 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
23 | |||
24 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/arm/m_helper.c | ||
27 | +++ b/target/arm/m_helper.c | ||
28 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
29 | /* Return the MMU index for a v7M CPU in the specified security state */ | ||
30 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
31 | { | ||
32 | - bool priv = arm_current_el(env) != 0; | ||
33 | + bool priv = arm_v7m_is_handler_mode(env) || | ||
34 | + !(env->v7m.control[secstate] & 1); | ||
35 | |||
36 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
37 | } | ||
38 | -- | ||
39 | 2.20.1 | ||
40 | |||
41 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | On some hosts (eg Ubuntu Bionic) pkg-config returns a set of | ||
2 | libraries for gio-2.0 which don't actually work when compiling | ||
3 | statically. (Specifically, the returned library string includes | ||
4 | -lmount, but not -lblkid which -lmount depends upon, so linking | ||
5 | fails due to missing symbols.) | ||
1 | 6 | ||
7 | Check that the libraries work, and don't enable gio if they don't, | ||
8 | in the same way we do for gnutls. | ||
9 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
13 | Message-id: 20200928160402.7961-1-peter.maydell@linaro.org | ||
14 | --- | ||
15 | configure | 10 +++++++++- | ||
16 | 1 file changed, 9 insertions(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/configure b/configure | ||
19 | index XXXXXXX..XXXXXXX 100755 | ||
20 | --- a/configure | ||
21 | +++ b/configure | ||
22 | @@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then | ||
23 | fi | ||
24 | |||
25 | if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then | ||
26 | - gio=yes | ||
27 | gio_cflags=$($pkg_config --cflags gio-2.0) | ||
28 | gio_libs=$($pkg_config --libs gio-2.0) | ||
29 | gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0) | ||
30 | if [ ! -x "$gdbus_codegen" ]; then | ||
31 | gdbus_codegen= | ||
32 | fi | ||
33 | + # Check that the libraries actually work -- Ubuntu 18.04 ships | ||
34 | + # with pkg-config --static --libs data for gio-2.0 that is missing | ||
35 | + # -lblkid and will give a link error. | ||
36 | + write_c_skeleton | ||
37 | + if compile_prog "" "gio_libs" ; then | ||
38 | + gio=yes | ||
39 | + else | ||
40 | + gio=no | ||
41 | + fi | ||
42 | else | ||
43 | gio=no | ||
44 | fi | ||
45 | -- | ||
46 | 2.20.1 | ||
47 | |||
48 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt |
---|---|---|---|
2 | into the GICv3CPUState struct's maintenance_irq field. This will | ||
3 | only work if the board happens to have already wired up the CPU | ||
4 | maintenance IRQ before the GIC was realized. Unfortunately this is | ||
5 | not the case for the 'virt' board, and so the value that gets copied | ||
6 | is NULL (since a qemu_irq is really a pointer to an IRQState struct | ||
7 | under the hood). The effect is that the CPU interface code never | ||
8 | actually raises the maintenance interrupt line. | ||
2 | 9 | ||
3 | Temperatures can be changed from the monitor with : | 10 | Instead, since the GICv3CPUState has a pointer to the CPUState, make |
11 | the dereference at the point where we want to raise the interrupt, to | ||
12 | avoid an implicit requirement on board code to wire things up in a | ||
13 | particular order. | ||
4 | 14 | ||
5 | (qemu) qom-set /machine/unattached/device[2] temperature0 12000 | 15 | Reported-by: Jose Martins <josemartins90@gmail.com> |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Message-id: 20201009153904.28529-1-peter.maydell@linaro.org | ||
18 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
19 | --- | ||
20 | include/hw/intc/arm_gicv3_common.h | 1 - | ||
21 | hw/intc/arm_gicv3_cpuif.c | 5 ++--- | ||
22 | 2 files changed, 2 insertions(+), 4 deletions(-) | ||
6 | 23 | ||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 24 | diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h |
8 | Message-id: 1496739230-32109-3-git-send-email-clg@kaod.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/aspeed.c | 9 +++++++++ | ||
13 | 1 file changed, 9 insertions(+) | ||
14 | |||
15 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/aspeed.c | 26 | --- a/include/hw/intc/arm_gicv3_common.h |
18 | +++ b/hw/arm/aspeed.c | 27 | +++ b/include/hw/intc/arm_gicv3_common.h |
19 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | 28 | @@ -XXX,XX +XXX,XX @@ struct GICv3CPUState { |
20 | static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) | 29 | qemu_irq parent_fiq; |
21 | { | 30 | qemu_irq parent_virq; |
22 | AspeedSoCState *soc = &bmc->soc; | 31 | qemu_irq parent_vfiq; |
23 | + DeviceState *dev; | 32 | - qemu_irq maintenance_irq; |
24 | 33 | ||
25 | /* The palmetto platform expects a ds3231 RTC but a ds1338 is | 34 | /* Redistributor */ |
26 | * enough to provide basic RTC features. Alarms will be missing */ | 35 | uint32_t level; /* Current IRQ level */ |
27 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); | 36 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c |
28 | + | 37 | index XXXXXXX..XXXXXXX 100644 |
29 | + /* add a TMP423 temperature sensor */ | 38 | --- a/hw/intc/arm_gicv3_cpuif.c |
30 | + dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), | 39 | +++ b/hw/intc/arm_gicv3_cpuif.c |
31 | + "tmp423", 0x4c); | 40 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) |
32 | + object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); | 41 | int irqlevel = 0; |
33 | + object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); | 42 | int fiqlevel = 0; |
34 | + object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); | 43 | int maintlevel = 0; |
35 | + object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); | 44 | + ARMCPU *cpu = ARM_CPU(cs->cpu); |
45 | |||
46 | idx = hppvi_index(cs); | ||
47 | trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); | ||
48 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) | ||
49 | |||
50 | qemu_set_irq(cs->parent_vfiq, fiqlevel); | ||
51 | qemu_set_irq(cs->parent_virq, irqlevel); | ||
52 | - qemu_set_irq(cs->maintenance_irq, maintlevel); | ||
53 | + qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); | ||
36 | } | 54 | } |
37 | 55 | ||
38 | static void palmetto_bmc_init(MachineState *machine) | 56 | static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
57 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) | ||
58 | && cpu->gic_num_lrs) { | ||
59 | int j; | ||
60 | |||
61 | - cs->maintenance_irq = cpu->gicv3_maintenance_interrupt; | ||
62 | - | ||
63 | cs->num_list_regs = cpu->gic_num_lrs; | ||
64 | cs->vpribits = cpu->gic_vpribits; | ||
65 | cs->vprebits = cpu->gic_vprebits; | ||
39 | -- | 66 | -- |
40 | 2.7.4 | 67 | 2.20.1 |
41 | 68 | ||
42 | 69 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The kerneldoc script currently emits Sphinx markup for a macro with | ||
2 | arguments that uses the c:function directive. This is correct for | ||
3 | Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow | ||
4 | documentation of macros with arguments and c:function is not picky | ||
5 | about the syntax of what it is passed. However, in Sphinx 3 the | ||
6 | c:macro directive was enhanced to support macros with arguments, | ||
7 | and c:function was made more picky about what syntax it accepted. | ||
1 | 8 | ||
9 | When kerneldoc is told that it needs to produce output for Sphinx | ||
10 | 3 or later, make it emit c:function only for functions and c:macro | ||
11 | for macros with arguments. We assume that anything with a return | ||
12 | type is a function and anything without is a macro. | ||
13 | |||
14 | This fixes the Sphinx error: | ||
15 | |||
16 | /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator | ||
17 | If declarator-id with parameters (e.g., 'void f(int arg)'): | ||
18 | Invalid C declaration: Expected identifier in nested name. [error at 25] | ||
19 | DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) | ||
20 | -------------------------^ | ||
21 | If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'): | ||
22 | Error in declarator or parameters | ||
23 | Invalid C declaration: Expecting "(" in parameters. [error at 39] | ||
24 | DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) | ||
25 | ---------------------------------------^ | ||
26 | |||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | ||
29 | Tested-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
30 | Message-id: 20201030174700.7204-2-peter.maydell@linaro.org | ||
31 | --- | ||
32 | scripts/kernel-doc | 18 +++++++++++++++++- | ||
33 | 1 file changed, 17 insertions(+), 1 deletion(-) | ||
34 | |||
35 | diff --git a/scripts/kernel-doc b/scripts/kernel-doc | ||
36 | index XXXXXXX..XXXXXXX 100755 | ||
37 | --- a/scripts/kernel-doc | ||
38 | +++ b/scripts/kernel-doc | ||
39 | @@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) { | ||
40 | output_highlight_rst($args{'purpose'}); | ||
41 | $start = "\n\n**Syntax**\n\n ``"; | ||
42 | } else { | ||
43 | - print ".. c:function:: "; | ||
44 | + if ((split(/\./, $sphinx_version))[0] >= 3) { | ||
45 | + # Sphinx 3 and later distinguish macros and functions and | ||
46 | + # complain if you use c:function with something that's not | ||
47 | + # syntactically valid as a function declaration. | ||
48 | + # We assume that anything with a return type is a function | ||
49 | + # and anything without is a macro. | ||
50 | + if ($args{'functiontype'} ne "") { | ||
51 | + print ".. c:function:: "; | ||
52 | + } else { | ||
53 | + print ".. c:macro:: "; | ||
54 | + } | ||
55 | + } else { | ||
56 | + # Older Sphinx don't support documenting macros that take | ||
57 | + # arguments with c:macro, and don't complain about the use | ||
58 | + # of c:function for this. | ||
59 | + print ".. c:function:: "; | ||
60 | + } | ||
61 | } | ||
62 | if ($args{'functiontype'} ne "") { | ||
63 | $start .= $args{'functiontype'} . " " . $args{'function'} . " ("; | ||
64 | -- | ||
65 | 2.20.1 | ||
66 | |||
67 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Sphinx 3.2 is pickier than earlier versions about the option:: markup, | ||
2 | and complains about our usage in qemu-option-trace.rst: | ||
1 | 3 | ||
4 | ../../docs/qemu-option-trace.rst.inc:4:Malformed option description | ||
5 | '[enable=]PATTERN', should look like "opt", "-opt args", "--opt args", | ||
6 | "/opt args" or "+opt args" | ||
7 | |||
8 | In this file, we're really trying to document the different parts of | ||
9 | the top-level --trace option, which qemu-nbd.rst and qemu-img.rst | ||
10 | have already introduced with an option:: markup. So it's not right | ||
11 | to use option:: here anyway. Switch to a different markup | ||
12 | (definition lists) which gives about the same formatted output. | ||
13 | |||
14 | (Unlike option::, this markup doesn't produce index entries; but | ||
15 | at the moment we don't do anything much with indexes anyway, and | ||
16 | in any case I think it doesn't make much sense to have individual | ||
17 | index entries for the sub-parts of the --trace option.) | ||
18 | |||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | ||
21 | Tested-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
22 | Message-id: 20201030174700.7204-3-peter.maydell@linaro.org | ||
23 | --- | ||
24 | docs/qemu-option-trace.rst.inc | 6 +++--- | ||
25 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
26 | |||
27 | diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/docs/qemu-option-trace.rst.inc | ||
30 | +++ b/docs/qemu-option-trace.rst.inc | ||
31 | @@ -XXX,XX +XXX,XX @@ | ||
32 | |||
33 | Specify tracing options. | ||
34 | |||
35 | -.. option:: [enable=]PATTERN | ||
36 | +``[enable=]PATTERN`` | ||
37 | |||
38 | Immediately enable events matching *PATTERN* | ||
39 | (either event name or a globbing pattern). This option is only | ||
40 | @@ -XXX,XX +XXX,XX @@ Specify tracing options. | ||
41 | |||
42 | Use :option:`-trace help` to print a list of names of trace points. | ||
43 | |||
44 | -.. option:: events=FILE | ||
45 | +``events=FILE`` | ||
46 | |||
47 | Immediately enable events listed in *FILE*. | ||
48 | The file must contain one event name (as listed in the ``trace-events-all`` | ||
49 | @@ -XXX,XX +XXX,XX @@ Specify tracing options. | ||
50 | available if QEMU has been compiled with the ``simple``, ``log`` or | ||
51 | ``ftrace`` tracing backend. | ||
52 | |||
53 | -.. option:: file=FILE | ||
54 | +``file=FILE`` | ||
55 | |||
56 | Log output traces to *FILE*. | ||
57 | This option is only available if QEMU has been compiled with | ||
58 | -- | ||
59 | 2.20.1 | ||
60 | |||
61 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The randomness tests in the NPCM7xx RNG test fail intermittently | ||
2 | but fairly frequently. On my machine running the test in a loop: | ||
3 | while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done | ||
1 | 4 | ||
5 | will fail in less than a minute with an error like: | ||
6 | ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs: | ||
7 | assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01) | ||
8 | |||
9 | (Failures have been observed on all 4 of the randomness tests, | ||
10 | not just first_byte_runs.) | ||
11 | |||
12 | It's not clear why these tests are failing like this, but intermittent | ||
13 | failures make CI and merge testing awkward, so disable running them | ||
14 | unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when | ||
15 | running the test suite, until we work out the cause. | ||
16 | |||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
19 | Message-id: 20201102152454.8287-1-peter.maydell@linaro.org | ||
20 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
21 | --- | ||
22 | tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++---- | ||
23 | 1 file changed, 10 insertions(+), 4 deletions(-) | ||
24 | |||
25 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/tests/qtest/npcm7xx_rng-test.c | ||
28 | +++ b/tests/qtest/npcm7xx_rng-test.c | ||
29 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | ||
30 | |||
31 | qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable); | ||
32 | qtest_add_func("npcm7xx_rng/rosel", test_rosel); | ||
33 | - qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit); | ||
34 | - qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); | ||
35 | - qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit); | ||
36 | - qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); | ||
37 | + /* | ||
38 | + * These tests fail intermittently; only run them on explicit | ||
39 | + * request until we figure out why. | ||
40 | + */ | ||
41 | + if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) { | ||
42 | + qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit); | ||
43 | + qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); | ||
44 | + qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit); | ||
45 | + qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); | ||
46 | + } | ||
47 | |||
48 | qtest_start("-machine npcm750-evb"); | ||
49 | ret = g_test_run(); | ||
50 | -- | ||
51 | 2.20.1 | ||
52 | |||
53 | diff view generated by jsdifflib |