[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/8] target-arm queue
1
Target-arm queue...
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Handful of bugfixes for rc2. None of these are particularly critical
2
or exciting.
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3
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 735286a4f88255e1463d42ce28d8d14181fd32d4:
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The following changes since commit 45a150aa2b3492acf6691c7bdbeb25a8545d8345:
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7
8
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170613' into staging (2017-06-13 13:51:29 +0100)
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Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' into staging (2020-08-03 15:13:49 +0100)
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9
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are available in the git repository at:
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are available in the Git repository at:
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11
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170613
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200803
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13
14
for you to fetch changes up to 252a7a6a968c279a4636a86b0559ba3a930a90b5:
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for you to fetch changes up to 13557fd392890cbd985bceba7f717e01efd674b8:
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15
16
hw/intc/arm_gicv3_its: Allow save/restore (2017-06-13 14:57:01 +0100)
16
hw/timer/imx_epit: Avoid assertion when CR.SWR is written (2020-08-03 17:56:11 +0100)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* vITS: Support save/restore
20
* hw/timer/imx_epit: Avoid assertion when CR.SWR is written
21
* timer/aspeed: Fix timer enablement when reload is not set
21
* netduino2, netduinoplus2, microbit: set system_clock_scale so that
22
* aspped: add temperature sensor device
22
SysTick running on the CPU clock works
23
* timer.h: Provide better monotonic time on ARM hosts
23
* target/arm: Avoid maybe-uninitialized warning with gcc 4.9
24
* exynos4210: various cleanups
24
* target/arm: Fix AddPAC error indication
25
* exynos4210: support system poweroff
25
* Make AIRCR.SYSRESETREQ actually reset the system for the
26
microbit, mps2-*, musca-*, netduino* boards
26
27
27
----------------------------------------------------------------
28
----------------------------------------------------------------
28
Cédric Le Goater (3):
29
Kaige Li (1):
29
hw/misc: add a TMP42{1, 2, 3} device model
30
target/arm: Avoid maybe-uninitialized warning with gcc 4.9
30
aspeed: add a temp sensor device on I2C bus 3
31
timer/aspeed: fix timer enablement when a reload is not set
32
31
33
Eric Auger (4):
32
Peter Maydell (6):
34
kvm-all: Pass an error object to kvm_device_access
33
hw/arm/netduino2, netduinoplus2: Set system_clock_scale
35
hw/intc/arm_gicv3_its: Implement state save/restore
34
include/hw/irq.h: New function qemu_irq_is_connected()
36
hw/intc/arm_gicv3_kvm: Implement pending table save
35
hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
37
hw/intc/arm_gicv3_its: Allow save/restore
36
msf2-soc, stellaris: Don't wire up SYSRESETREQ
37
hw/arm/nrf51_soc: Set system_clock_scale
38
hw/timer/imx_epit: Avoid assertion when CR.SWR is written
38
39
39
Krzysztof Kozlowski (9):
40
Richard Henderson (1):
40
hw/intc/exynos4210_gic: Use more meaningful name for local variable
41
target/arm: Fix AddPAC error indication
41
hw/timer/exynos4210_mct: Fix checkpatch style errors
42
hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
43
hw/timer/exynos4210_mct: Remove unused defines
44
hw/arm/exynos: Move DRAM initialization next boards
45
hw/arm/exynos: Declare local variables in some order
46
hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string
47
hw/intc/exynos4210_gic: Constify array of combiner interrupts
48
hw/misc/exynos4210_pmu: Add support for system poweroff
49
42
50
Pranith Kumar (1):
43
include/hw/arm/armv7m.h | 4 +++-
51
timer.h: Provide better monotonic time
44
include/hw/irq.h | 18 ++++++++++++++++++
45
hw/arm/msf2-soc.c | 11 -----------
46
hw/arm/netduino2.c | 10 ++++++++++
47
hw/arm/netduinoplus2.c | 10 ++++++++++
48
hw/arm/nrf51_soc.c | 5 +++++
49
hw/arm/stellaris.c | 12 ------------
50
hw/intc/armv7m_nvic.c | 17 ++++++++++++++++-
51
hw/timer/imx_epit.c | 13 ++++++++++---
52
target/arm/pauth_helper.c | 6 +++++-
53
target/arm/translate-a64.c | 2 +-
54
tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++++
55
tests/tcg/aarch64/Makefile.target | 2 +-
56
13 files changed, 112 insertions(+), 31 deletions(-)
57
create mode 100644 tests/tcg/aarch64/pauth-5.c
52
58
53
hw/misc/Makefile.objs | 1 +
54
include/hw/arm/exynos4210.h | 5 +-
55
include/hw/intc/arm_gicv3_its_common.h | 8 +
56
include/migration/vmstate.h | 2 +
57
include/qemu/timer.h | 5 +-
58
include/sysemu/kvm.h | 11 +-
59
hw/arm/aspeed.c | 9 +
60
hw/arm/exynos4210.c | 27 +--
61
hw/arm/exynos4_boards.c | 50 +++-
62
hw/intc/arm_gic_kvm.c | 9 +-
63
hw/intc/arm_gicv3_common.c | 1 +
64
hw/intc/arm_gicv3_its_common.c | 12 +-
65
hw/intc/arm_gicv3_its_kvm.c | 131 +++++++++--
66
hw/intc/arm_gicv3_kvm.c | 48 +++-
67
hw/intc/exynos4210_gic.c | 14 +-
68
hw/misc/exynos4210_pmu.c | 20 +-
69
hw/misc/tmp421.c | 402 +++++++++++++++++++++++++++++++++
70
hw/timer/aspeed_timer.c | 37 ++-
71
hw/timer/exynos4210_mct.c | 50 ++--
72
kvm-all.c | 14 +-
73
default-configs/arm-softmmu.mak | 1 +
74
21 files changed, 741 insertions(+), 116 deletions(-)
75
create mode 100644 hw/misc/tmp421.c
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
There are to SysBusDevice variables in exynos4210_gic_realize()
4
function: one for the device itself and second for arm_gic device. Add
5
a prefix "gic" to the second one so it will be easier to understand the
6
code.
7
8
While at it, put local uninitialized 'i' variable at the end, next to
9
other uninitialized ones.
10
11
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/intc/exynos4210_gic.c | 12 ++++++------
17
1 file changed, 6 insertions(+), 6 deletions(-)
18
19
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/intc/exynos4210_gic.c
22
+++ b/hw/intc/exynos4210_gic.c
23
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj)
24
DeviceState *dev = DEVICE(obj);
25
Exynos4210GicState *s = EXYNOS4210_GIC(obj);
26
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
27
- uint32_t i;
28
const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
29
const char dist_prefix[] = "exynos4210-gic-alias_dist";
30
char cpu_alias_name[sizeof(cpu_prefix) + 3];
31
char dist_alias_name[sizeof(cpu_prefix) + 3];
32
- SysBusDevice *busdev;
33
+ SysBusDevice *gicbusdev;
34
+ uint32_t i;
35
36
s->gic = qdev_create(NULL, "arm_gic");
37
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
38
qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ);
39
qdev_init_nofail(s->gic);
40
- busdev = SYS_BUS_DEVICE(s->gic);
41
+ gicbusdev = SYS_BUS_DEVICE(s->gic);
42
43
/* Pass through outbound IRQ lines from the GIC */
44
- sysbus_pass_irq(sbd, busdev);
45
+ sysbus_pass_irq(sbd, gicbusdev);
46
47
/* Pass through inbound GPIO lines to the GIC */
48
qdev_init_gpio_in(dev, exynos4210_gic_set_irq,
49
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj)
50
sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
51
memory_region_init_alias(&s->cpu_alias[i], obj,
52
cpu_alias_name,
53
- sysbus_mmio_get_region(busdev, 1),
54
+ sysbus_mmio_get_region(gicbusdev, 1),
55
0,
56
EXYNOS4210_GIC_CPU_REGION_SIZE);
57
memory_region_add_subregion(&s->cpu_container,
58
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj)
59
sprintf(dist_alias_name, "%s%x", dist_prefix, i);
60
memory_region_init_alias(&s->dist_alias[i], obj,
61
dist_alias_name,
62
- sysbus_mmio_get_region(busdev, 0),
63
+ sysbus_mmio_get_region(gicbusdev, 0),
64
0,
65
EXYNOS4210_GIC_DIST_REGION_SIZE);
66
memory_region_add_subregion(&s->dist_container,
67
--
68
2.7.4
69
70
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/17] hw/timer/exynos4210_mct: Fix checkpatch style errors
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
Fix checkpatch errors:
4
1. ERROR: spaces required around that '+' (ctx:VxV)
5
2. ERROR: spaces required around that '&' (ctx:VxV)
6
7
No functional changes.
8
9
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/timer/exynos4210_mct.c | 4 ++--
15
1 file changed, 2 insertions(+), 2 deletions(-)
16
17
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/timer/exynos4210_mct.c
20
+++ b/hw/timer/exynos4210_mct.c
21
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
22
{
23
uint32_t freq = s->freq;
24
s->freq = 24000000 /
25
- ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) *
26
+ ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg) + 1) *
27
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
28
29
if (freq != s->freq) {
30
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
31
32
DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
33
34
- if (offset&0x4) {
35
+ if (offset & 0x4) {
36
s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
37
} else {
38
s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
39
--
40
2.7.4
41
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/17] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
Statements under 'case' were in some places wrongly indented bringing
4
confusion and making the code less readable. Remove also few unneeded
5
blank lines. No functional changes.
6
7
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++-------------------------
13
1 file changed, 20 insertions(+), 25 deletions(-)
14
15
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/timer/exynos4210_mct.c
18
+++ b/hw/timer/exynos4210_mct.c
19
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
20
21
case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
22
case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
23
- index = GET_G_COMP_IDX(offset);
24
- shift = 8 * (offset & 0x4);
25
- value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
26
+ index = GET_G_COMP_IDX(offset);
27
+ shift = 8 * (offset & 0x4);
28
+ value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
29
break;
30
31
case G_TCON:
32
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
33
lt_i = GET_L_TIMER_IDX(offset);
34
35
value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]);
36
-
37
break;
38
39
case L0_TCON: case L1_TCON:
40
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
41
42
case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
43
case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
44
- index = GET_G_COMP_IDX(offset);
45
- shift = 8 * (offset & 0x4);
46
- s->g_timer.reg.comp[index] =
47
- (s->g_timer.reg.comp[index] &
48
- (((uint64_t)UINT32_MAX << 32) >> shift)) +
49
- (value << shift);
50
+ index = GET_G_COMP_IDX(offset);
51
+ shift = 8 * (offset & 0x4);
52
+ s->g_timer.reg.comp[index] =
53
+ (s->g_timer.reg.comp[index] &
54
+ (((uint64_t)UINT32_MAX << 32) >> shift)) +
55
+ (value << shift);
56
57
- DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
58
+ DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
59
60
- if (offset & 0x4) {
61
- s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
62
- } else {
63
- s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
64
- }
65
+ if (offset & 0x4) {
66
+ s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
67
+ } else {
68
+ s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
69
+ }
70
71
- exynos4210_gfrc_restart(s);
72
- break;
73
+ exynos4210_gfrc_restart(s);
74
+ break;
75
76
case G_TCON:
77
old_val = s->g_timer.reg.tcon;
78
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
79
break;
80
81
case G_INT_ENB:
82
-
83
/* Raise IRQ if transition from disabled to enabled and CSTAT pending */
84
for (i = 0; i < MCT_GT_CMP_NUM; i++) {
85
if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon &
86
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
87
break;
88
89
case L0_TCNTB: case L1_TCNTB:
90
-
91
lt_i = GET_L_TIMER_IDX(offset);
92
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
93
94
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
95
break;
96
97
case L0_ICNTB: case L1_ICNTB:
98
-
99
lt_i = GET_L_TIMER_IDX(offset);
100
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
101
102
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
103
if (icntb_max[lt_i] < value) {
104
icntb_max[lt_i] = value;
105
}
106
-DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
107
- lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
108
+ DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
109
+ lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
110
#endif
111
-break;
112
+ break;
113
114
case L0_FRCNTB: case L1_FRCNTB:
115
-
116
lt_i = GET_L_TIMER_IDX(offset);
117
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
118
119
--
120
2.7.4
121
122
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/17] hw/timer/exynos4210_mct: Remove unused defines
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
Remove defines not used anywhere.
4
5
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/timer/exynos4210_mct.c | 3 ---
10
1 file changed, 3 deletions(-)
11
12
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/timer/exynos4210_mct.c
15
+++ b/hw/timer/exynos4210_mct.c
16
@@ -XXX,XX +XXX,XX @@ enum LocalTimerRegCntIndexes {
17
L_REG_CNT_AMOUNT
18
};
19
20
-#define MCT_NIRQ 6
21
#define MCT_SFR_SIZE 0x444
22
23
#define MCT_GT_CMP_NUM 4
24
25
-#define MCT_GT_MAX_VAL UINT64_MAX
26
-
27
#define MCT_GT_COUNTER_STEP 0x100000000ULL
28
#define MCT_LT_COUNTER_STEP 0x100000000ULL
29
#define MCT_LT_CNT_LOW_LIMIT 0x100
30
--
31
2.7.4
32
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/17] hw/arm/exynos: Move DRAM initialization next boards
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
Before QOM-ifying the Exynos4 SoC model, move the DRAM initialization
4
from exynos4210.c to exynos4_boards.c because DRAM is board specific,
5
not SoC.
6
7
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/exynos4210.h | 5 +----
12
hw/arm/exynos4210.c | 20 +-----------------
13
hw/arm/exynos4_boards.c | 50 ++++++++++++++++++++++++++++++++++++++-------
14
3 files changed, 45 insertions(+), 30 deletions(-)
15
16
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/exynos4210.h
19
+++ b/include/hw/arm/exynos4210.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
21
MemoryRegion iram_mem;
22
MemoryRegion irom_mem;
23
MemoryRegion irom_alias_mem;
24
- MemoryRegion dram0_mem;
25
- MemoryRegion dram1_mem;
26
MemoryRegion boot_secondary;
27
MemoryRegion bootreg_mem;
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
29
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
30
void exynos4210_write_secondary(ARMCPU *cpu,
31
const struct arm_boot_info *info);
32
33
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
34
- unsigned long ram_size);
35
+Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
36
37
/* Initialize exynos4210 IRQ subsystem stub */
38
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
39
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/exynos4210.c
42
+++ b/hw/arm/exynos4210.c
43
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
44
return mp_affinity;
45
}
46
47
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
48
- unsigned long ram_size)
49
+Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
50
{
51
int i, n;
52
Exynos4210State *s = g_new(Exynos4210State, 1);
53
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
54
- unsigned long mem_size;
55
DeviceState *dev;
56
SysBusDevice *busdev;
57
ObjectClass *cpu_oc;
58
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
59
memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
60
&s->iram_mem);
61
62
- /* DRAM */
63
- mem_size = ram_size;
64
- if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
65
- memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
66
- mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
67
- vmstate_register_ram_global(&s->dram1_mem);
68
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
69
- &s->dram1_mem);
70
- mem_size = EXYNOS4210_DRAM_MAX_SIZE;
71
- }
72
- memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
73
- &error_fatal);
74
- vmstate_register_ram_global(&s->dram0_mem);
75
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
76
- &s->dram0_mem);
77
-
78
/* PMU.
79
* The only reason of existence at the moment is that secondary CPU boot
80
* loader uses PMU INFORM5 register as a holding pen.
81
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/hw/arm/exynos4_boards.c
84
+++ b/hw/arm/exynos4_boards.c
85
@@ -XXX,XX +XXX,XX @@
86
*/
87
88
#include "qemu/osdep.h"
89
+#include "qapi/error.h"
90
#include "qemu/error-report.h"
91
#include "qemu-common.h"
92
#include "cpu.h"
93
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
94
EXYNOS4_NUM_OF_BOARDS
95
} Exynos4BoardType;
96
97
+typedef struct Exynos4BoardState {
98
+ Exynos4210State *soc;
99
+ MemoryRegion dram0_mem;
100
+ MemoryRegion dram1_mem;
101
+} Exynos4BoardState;
102
+
103
static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
104
[EXYNOS4_BOARD_NURI] = 0xD33,
105
[EXYNOS4_BOARD_SMDKC210] = 0xB16,
106
@@ -XXX,XX +XXX,XX @@ static void lan9215_init(uint32_t base, qemu_irq irq)
107
}
108
}
109
110
-static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
111
- Exynos4BoardType board_type)
112
+static void exynos4_boards_init_ram(Exynos4BoardState *s,
113
+ MemoryRegion *system_mem,
114
+ unsigned long ram_size)
115
+{
116
+ unsigned long mem_size = ram_size;
117
+
118
+ if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
119
+ memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
120
+ mem_size - EXYNOS4210_DRAM_MAX_SIZE,
121
+ &error_fatal);
122
+ vmstate_register_ram_global(&s->dram1_mem);
123
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
124
+ &s->dram1_mem);
125
+ mem_size = EXYNOS4210_DRAM_MAX_SIZE;
126
+ }
127
+
128
+ memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
129
+ &error_fatal);
130
+ vmstate_register_ram_global(&s->dram0_mem);
131
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
132
+ &s->dram0_mem);
133
+}
134
+
135
+static Exynos4BoardState *
136
+exynos4_boards_init_common(MachineState *machine,
137
+ Exynos4BoardType board_type)
138
{
139
+ Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
140
MachineClass *mc = MACHINE_GET_CLASS(machine);
141
142
if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
143
@@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
144
machine->kernel_cmdline,
145
machine->initrd_filename);
146
147
- return exynos4210_init(get_system_memory(),
148
- exynos4_board_ram_size[board_type]);
149
+ exynos4_boards_init_ram(s, get_system_memory(),
150
+ exynos4_board_ram_size[board_type]);
151
+
152
+ s->soc = exynos4210_init(get_system_memory());
153
+
154
+ return s;
155
}
156
157
static void nuri_init(MachineState *machine)
158
@@ -XXX,XX +XXX,XX @@ static void nuri_init(MachineState *machine)
159
160
static void smdkc210_init(MachineState *machine)
161
{
162
- Exynos4210State *s = exynos4_boards_init_common(machine,
163
- EXYNOS4_BOARD_SMDKC210);
164
+ Exynos4BoardState *s = exynos4_boards_init_common(machine,
165
+ EXYNOS4_BOARD_SMDKC210);
166
167
lan9215_init(SMDK_LAN9118_BASE_ADDR,
168
- qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)]));
169
+ qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
170
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
171
}
172
173
--
174
2.7.4
175
176
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/17] hw/arm/exynos: Declare local variables in some order
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
Bring some more readability by declaring local function variables: first
4
initialized ones and then the rest (with reversed-christmas-tree order).
5
6
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/exynos4210.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4210.c
16
+++ b/hw/arm/exynos4210.c
17
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
18
19
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
20
{
21
- int i, n;
22
Exynos4210State *s = g_new(Exynos4210State, 1);
23
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
24
- DeviceState *dev;
25
SysBusDevice *busdev;
26
ObjectClass *cpu_oc;
27
+ DeviceState *dev;
28
+ int i, n;
29
30
cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
31
assert(cpu_oc);
32
--
33
2.7.4
34
35
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/17] hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
Use a define for a9mpcore_priv device type name instead of hard-coded
4
string.
5
6
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/exynos4210.c | 3 ++-
11
1 file changed, 2 insertions(+), 1 deletion(-)
12
13
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4210.c
16
+++ b/hw/arm/exynos4210.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "qemu-common.h"
19
#include "qemu/log.h"
20
#include "cpu.h"
21
+#include "hw/cpu/a9mpcore.h"
22
#include "hw/boards.h"
23
#include "sysemu/sysemu.h"
24
#include "hw/sysbus.h"
25
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
26
}
27
28
/* Private memory region and Internal GIC */
29
- dev = qdev_create(NULL, "a9mpcore_priv");
30
+ dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
31
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
32
qdev_init_nofail(dev);
33
busdev = SYS_BUS_DEVICE(dev);
34
--
35
2.7.4
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/17] hw/intc/arm_gicv3_its: Allow save/restore
[PULL 1/8] hw/arm/netduino2, netduinoplus2: Set system_clock_scale
1
From: Eric Auger <eric.auger@redhat.com>
1
The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
2
global, which meant that if guest code used the systick timer in "use
3
the processor clock" mode it would hang because time never advances.
2
4
3
We change the restoration priority of both the GICv3 and ITS. The
5
Set the global to match the documented CPU clock speed of these boards.
4
GICv3 must be restored before the ITS and the ITS needs to be restored
6
Judging by the data sheet this is slightly simplistic because the
5
before PCIe devices since it translates their MSI transactions.
7
SoC allows configuration of the SYSCLK source and frequency via the
8
RCC (reset and clock control) module, but we don't model that.
6
9
7
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Fixes: https://bugs.launchpad.net/qemu/+bug/1876187
8
Reviewed-by: Juan Quintela <quintela@redhat.com>
9
Message-id: 1497023553-18411-5-git-send-email-eric.auger@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20200727162617.26227-1-peter.maydell@linaro.org
11
---
14
---
12
include/migration/vmstate.h | 2 ++
15
hw/arm/netduino2.c | 10 ++++++++++
13
hw/intc/arm_gicv3_common.c | 1 +
16
hw/arm/netduinoplus2.c | 10 ++++++++++
14
hw/intc/arm_gicv3_its_common.c | 2 +-
17
2 files changed, 20 insertions(+)
15
hw/intc/arm_gicv3_its_kvm.c | 24 ++++++++++++------------
16
4 files changed, 16 insertions(+), 13 deletions(-)
17
18
18
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
19
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
19
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
20
--- a/include/migration/vmstate.h
21
--- a/hw/arm/netduino2.c
21
+++ b/include/migration/vmstate.h
22
+++ b/hw/arm/netduino2.c
22
@@ -XXX,XX +XXX,XX @@ enum VMStateFlags {
23
@@ -XXX,XX +XXX,XX @@
23
typedef enum {
24
#include "hw/arm/stm32f205_soc.h"
24
MIG_PRI_DEFAULT = 0,
25
#include "hw/arm/boot.h"
25
MIG_PRI_IOMMU, /* Must happen before PCI devices */
26
26
+ MIG_PRI_GICV3_ITS, /* Must happen before PCI devices */
27
+/* Main SYSCLK frequency in Hz (120MHz) */
27
+ MIG_PRI_GICV3, /* Must happen before the ITS */
28
+#define SYSCLK_FRQ 120000000ULL
28
MIG_PRI_MAX,
29
+
29
} MigrationPriority;
30
static void netduino2_init(MachineState *machine)
30
31
{
31
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
32
DeviceState *dev;
33
34
+ /*
35
+ * TODO: ideally we would model the SoC RCC and let it handle
36
+ * system_clock_scale, including its ability to define different
37
+ * possible SYSCLK sources.
38
+ */
39
+ system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
40
+
41
dev = qdev_new(TYPE_STM32F205_SOC);
42
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
43
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
44
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
32
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/intc/arm_gicv3_common.c
46
--- a/hw/arm/netduinoplus2.c
34
+++ b/hw/intc/arm_gicv3_common.c
47
+++ b/hw/arm/netduinoplus2.c
35
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
48
@@ -XXX,XX +XXX,XX @@
36
.minimum_version_id = 1,
49
#include "hw/arm/stm32f405_soc.h"
37
.pre_save = gicv3_pre_save,
50
#include "hw/arm/boot.h"
38
.post_load = gicv3_post_load,
51
39
+ .priority = MIG_PRI_GICV3,
52
+/* Main SYSCLK frequency in Hz (168MHz) */
40
.fields = (VMStateField[]) {
53
+#define SYSCLK_FRQ 168000000ULL
41
VMSTATE_UINT32(gicd_ctlr, GICv3State),
42
VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
43
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/arm_gicv3_its_common.c
46
+++ b/hw/intc/arm_gicv3_its_common.c
47
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = {
48
.name = "arm_gicv3_its",
49
.pre_save = gicv3_its_pre_save,
50
.post_load = gicv3_its_post_load,
51
- .unmigratable = true,
52
+ .priority = MIG_PRI_GICV3_ITS,
53
.fields = (VMStateField[]) {
54
VMSTATE_UINT32(ctlr, GICv3ITSState),
55
VMSTATE_UINT32(iidr, GICv3ITSState),
56
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/arm_gicv3_its_kvm.c
59
+++ b/hw/intc/arm_gicv3_its_kvm.c
60
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
61
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
62
Error *local_err = NULL;
63
64
- /*
65
- * Block migration of a KVM GICv3 ITS device: the API for saving and
66
- * restoring the state in the kernel is not yet available
67
- */
68
- error_setg(&s->migration_blocker, "vITS migration is not implemented");
69
- migrate_add_blocker(s->migration_blocker, &local_err);
70
- if (local_err) {
71
- error_propagate(errp, local_err);
72
- error_free(s->migration_blocker);
73
- return;
74
- }
75
-
76
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
77
if (s->dev_fd < 0) {
78
error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
79
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
80
81
gicv3_its_init_mmio(s, NULL);
82
83
+ if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
84
+ GITS_CTLR)) {
85
+ error_setg(&s->migration_blocker, "This operating system kernel "
86
+ "does not support vITS migration");
87
+ migrate_add_blocker(s->migration_blocker, &local_err);
88
+ if (local_err) {
89
+ error_propagate(errp, local_err);
90
+ error_free(s->migration_blocker);
91
+ return;
92
+ }
93
+ }
94
+
54
+
95
kvm_msi_use_devid = true;
55
static void netduinoplus2_init(MachineState *machine)
96
kvm_gsi_direct_mapping = false;
56
{
97
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
57
DeviceState *dev;
58
59
+ /*
60
+ * TODO: ideally we would model the SoC RCC and let it handle
61
+ * system_clock_scale, including its ability to define different
62
+ * possible SYSCLK sources.
63
+ */
64
+ system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
65
+
66
dev = qdev_new(TYPE_STM32F405_SOC);
67
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
68
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
98
--
69
--
99
2.7.4
70
2.20.1
100
71
101
72
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/17] hw/intc/arm_gicv3_kvm: Implement pending table save
[PULL 2/8] include/hw/irq.h: New function qemu_irq_is_connected()
1
From: Eric Auger <eric.auger@redhat.com>
1
Mostly devices don't need to care whether one of their output
2
qemu_irq lines is connected, because functions like qemu_set_irq()
3
silently do nothing if there is nothing on the other end. However
4
sometimes a device might want to implement default behaviour for the
5
case where the machine hasn't wired the line up to anywhere.
2
6
3
This patch adds the flush of the LPI pending bits into the
7
Provide a function qemu_irq_is_connected() that devices can use for
4
redistributor pending tables. This happens on VM stop.
8
this purpose. (The test is trivial but encapsulating it in a
9
function makes it easier to see where we're doing it in case we need
10
to change the implementation later.)
5
11
6
There is no explicit restore as the tables are implicitly sync'ed
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
on ITS table restore and on LPI enable at redistributor level.
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20200728103744.6909-2-peter.maydell@linaro.org
16
---
17
include/hw/irq.h | 18 ++++++++++++++++++
18
1 file changed, 18 insertions(+)
8
19
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
20
diff --git a/include/hw/irq.h b/include/hw/irq.h
10
Message-id: 1497023553-18411-4-git-send-email-eric.auger@redhat.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/intc/arm_gicv3_kvm.c | 34 ++++++++++++++++++++++++++++++++++
15
1 file changed, 34 insertions(+)
16
17
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/arm_gicv3_kvm.c
22
--- a/include/hw/irq.h
20
+++ b/hw/intc/arm_gicv3_kvm.c
23
+++ b/include/hw/irq.h
21
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
22
#include "hw/sysbus.h"
25
on an existing vector of qemu_irq. */
23
#include "qemu/error-report.h"
26
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
24
#include "sysemu/kvm.h"
25
+#include "sysemu/sysemu.h"
26
#include "kvm_arm.h"
27
#include "gicv3_internal.h"
28
#include "vgic_common.h"
29
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
30
REGINFO_SENTINEL
31
};
32
27
33
+/**
28
+/**
34
+ * vm_change_state_handler - VM change state callback aiming at flushing
29
+ * qemu_irq_is_connected: Return true if IRQ line is wired up
35
+ * RDIST pending tables into guest RAM
36
+ *
30
+ *
37
+ * The tables get flushed to guest RAM whenever the VM gets stopped.
31
+ * If a qemu_irq has a device on the other (receiving) end of it,
32
+ * return true; otherwise return false.
33
+ *
34
+ * Usually device models don't need to care whether the machine model
35
+ * has wired up their outbound qemu_irq lines, because functions like
36
+ * qemu_set_irq() silently do nothing if there is nothing on the other
37
+ * end of the line. However occasionally a device model will want to
38
+ * provide default behaviour if its output is left floating, and
39
+ * it can use this function to identify when that is the case.
38
+ */
40
+ */
39
+static void vm_change_state_handler(void *opaque, int running,
41
+static inline bool qemu_irq_is_connected(qemu_irq irq)
40
+ RunState state)
41
+{
42
+{
42
+ GICv3State *s = (GICv3State *)opaque;
43
+ return irq != NULL;
43
+ Error *err = NULL;
44
+ int ret;
45
+
46
+ if (running) {
47
+ return;
48
+ }
49
+
50
+ ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
51
+ KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES,
52
+ NULL, true, &err);
53
+ if (err) {
54
+ error_report_err(err);
55
+ }
56
+ if (ret < 0 && ret != -EFAULT) {
57
+ abort();
58
+ }
59
+}
44
+}
60
+
45
+
61
+
46
#endif
62
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
63
{
64
GICv3State *s = KVM_ARM_GICV3(dev);
65
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
66
return;
67
}
68
}
69
+ if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
70
+ KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) {
71
+ qemu_add_vm_change_state_handler(vm_change_state_handler, s);
72
+ }
73
}
74
75
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
76
--
47
--
77
2.7.4
48
2.20.1
78
49
79
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/17] hw/intc/arm_gicv3_its: Implement state save/restore
[PULL 3/8] hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
1
From: Eric Auger <eric.auger@redhat.com>
1
The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals
2
when the guest sets the SYSRESETREQ bit in the AIRCR register. This
3
matches the hardware design (where the CPU has a signal of this name
4
and it is up to the SoC to connect that up to an actual reset
5
mechanism), but in QEMU it mostly results in duplicated code in SoC
6
objects and bugs where SoC model implementors forget to wire up the
7
SYSRESETREQ line.
2
8
3
We need to handle both registers and ITS tables. While
9
Provide a default behaviour for the case where SYSRESETREQ is not
4
register handling is standard, ITS table handling is more
10
actually connected to anything: use qemu_system_reset_request() to
5
challenging since the kernel API is devised so that the
11
perform a system reset. This will allow us to remove the
6
tables are flushed into guest RAM and not in vmstate buffers.
12
implementations of SYSRESETREQ handling from the boards where that's
13
exactly what it does, and also fixes the bugs in the board models
14
which forgot to wire up the signal:
7
15
8
Flushing the ITS tables on device pre_save() is too late
16
* microbit
9
since the guest RAM is already saved at this point.
17
* mps2-an385
18
* mps2-an505
19
* mps2-an511
20
* mps2-an521
21
* musca-a
22
* musca-b1
23
* netduino
24
* netduinoplus2
10
25
11
Table flushing needs to happen when we are sure the vcpus
26
We still allow the board to wire up the signal if it needs to, in case
12
are stopped and before the last dirty page saving. The
27
we need to model more complicated reset controller logic or to model
13
right point is RUN_STATE_FINISH_MIGRATE but sometimes the
28
buggy SoC hardware which forgot to wire up the line itself. But
14
VM gets stopped before migration launch so let's simply
29
defaulting to "reset the system" is more often going to be correct
15
flush the tables each time the VM gets stopped.
30
than defaulting to "do nothing".
16
31
17
For regular ITS registers we just can use vmstate pre_save()
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
and post_load() callbacks.
33
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
34
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
35
Message-id: 20200728103744.6909-3-peter.maydell@linaro.org
36
---
37
include/hw/arm/armv7m.h | 4 +++-
38
hw/intc/armv7m_nvic.c | 17 ++++++++++++++++-
39
2 files changed, 19 insertions(+), 2 deletions(-)
19
40
20
Signed-off-by: Eric Auger <eric.auger@redhat.com>
41
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
21
Message-id: 1497023553-18411-3-git-send-email-eric.auger@redhat.com
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
include/hw/intc/arm_gicv3_its_common.h | 8 +++
26
hw/intc/arm_gicv3_its_common.c | 10 ++++
27
hw/intc/arm_gicv3_its_kvm.c | 105 +++++++++++++++++++++++++++++++++
28
3 files changed, 123 insertions(+)
29
30
diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
31
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/intc/arm_gicv3_its_common.h
43
--- a/include/hw/arm/armv7m.h
33
+++ b/include/hw/intc/arm_gicv3_its_common.h
44
+++ b/include/hw/arm/armv7m.h
45
@@ -XXX,XX +XXX,XX @@ typedef struct {
46
47
/* ARMv7M container object.
48
* + Unnamed GPIO input lines: external IRQ lines for the NVIC
49
- * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
50
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
51
+ * If this GPIO is not wired up then the NVIC will default to performing
52
+ * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
53
* + Property "cpu-type": CPU type to instantiate
54
* + Property "num-irq": number of external IRQ lines
55
* + Property "memory": MemoryRegion defining the physical address space
56
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/armv7m_nvic.c
59
+++ b/hw/intc/armv7m_nvic.c
34
@@ -XXX,XX +XXX,XX @@
60
@@ -XXX,XX +XXX,XX @@
35
#define ITS_TRANS_SIZE 0x10000
61
#include "hw/intc/armv7m_nvic.h"
36
#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
62
#include "hw/irq.h"
37
63
#include "hw/qdev-properties.h"
38
+#define GITS_CTLR 0x0
64
+#include "sysemu/runstate.h"
39
+#define GITS_IIDR 0x4
65
#include "target/arm/cpu.h"
40
+#define GITS_CBASER 0x80
66
#include "exec/exec-all.h"
41
+#define GITS_CWRITER 0x88
67
#include "exec/memop.h"
42
+#define GITS_CREADR 0x90
68
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
43
+#define GITS_BASER 0x100
69
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
44
+
45
struct GICv3ITSState {
46
SysBusDevice parent_obj;
47
48
@@ -XXX,XX +XXX,XX @@ struct GICv3ITSState {
49
50
/* Registers */
51
uint32_t ctlr;
52
+ uint32_t iidr;
53
uint64_t cbaser;
54
uint64_t cwriter;
55
uint64_t creadr;
56
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/arm_gicv3_its_common.c
59
+++ b/hw/intc/arm_gicv3_its_common.c
60
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = {
61
.pre_save = gicv3_its_pre_save,
62
.post_load = gicv3_its_post_load,
63
.unmigratable = true,
64
+ .fields = (VMStateField[]) {
65
+ VMSTATE_UINT32(ctlr, GICv3ITSState),
66
+ VMSTATE_UINT32(iidr, GICv3ITSState),
67
+ VMSTATE_UINT64(cbaser, GICv3ITSState),
68
+ VMSTATE_UINT64(cwriter, GICv3ITSState),
69
+ VMSTATE_UINT64(creadr, GICv3ITSState),
70
+ VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
71
+ VMSTATE_END_OF_LIST()
72
+ },
73
};
70
};
74
71
75
static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
72
+static void signal_sysresetreq(NVICState *s)
76
@@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev)
77
s->cbaser = 0;
78
s->cwriter = 0;
79
s->creadr = 0;
80
+ s->iidr = 0;
81
memset(&s->baser, 0, sizeof(s->baser));
82
83
gicv3_its_post_load(s, 0);
84
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/intc/arm_gicv3_its_kvm.c
87
+++ b/hw/intc/arm_gicv3_its_kvm.c
88
@@ -XXX,XX +XXX,XX @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
89
return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
90
}
91
92
+/**
93
+ * vm_change_state_handler - VM change state callback aiming at flushing
94
+ * ITS tables into guest RAM
95
+ *
96
+ * The tables get flushed to guest RAM whenever the VM gets stopped.
97
+ */
98
+static void vm_change_state_handler(void *opaque, int running,
99
+ RunState state)
100
+{
73
+{
101
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
74
+ if (qemu_irq_is_connected(s->sysresetreq)) {
102
+ Error *err = NULL;
75
+ qemu_irq_pulse(s->sysresetreq);
103
+ int ret;
76
+ } else {
104
+
77
+ /*
105
+ if (running) {
78
+ * Default behaviour if the SoC doesn't need to wire up
106
+ return;
79
+ * SYSRESETREQ (eg to a system reset controller of some kind):
107
+ }
80
+ * perform a system reset via the usual QEMU API.
108
+
81
+ */
109
+ ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
82
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
110
+ KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err);
111
+ if (err) {
112
+ error_report_err(err);
113
+ }
114
+ if (ret < 0 && ret != -EFAULT) {
115
+ abort();
116
+ }
83
+ }
117
+}
84
+}
118
+
85
+
119
static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
86
static int nvic_pending_prio(NVICState *s)
120
{
87
{
121
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
88
/* return the group priority of the current pending interrupt,
122
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
89
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
123
kvm_msi_use_devid = true;
90
if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
124
kvm_gsi_direct_mapping = false;
91
if (attrs.secure ||
125
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
92
!(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
126
+
93
- qemu_irq_pulse(s->sysresetreq);
127
+ qemu_add_vm_change_state_handler(vm_change_state_handler, s);
94
+ signal_sysresetreq(s);
128
}
95
}
129
96
}
130
static void kvm_arm_its_init(Object *obj)
97
if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
131
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_init(Object *obj)
132
&error_abort);
133
}
134
135
+/**
136
+ * kvm_arm_its_pre_save - handles the saving of ITS registers.
137
+ * ITS tables are flushed into guest RAM separately and earlier,
138
+ * through the VM change state handler, since at the moment pre_save()
139
+ * is called, the guest RAM has already been saved.
140
+ */
141
+static void kvm_arm_its_pre_save(GICv3ITSState *s)
142
+{
143
+ int i;
144
+
145
+ for (i = 0; i < 8; i++) {
146
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
147
+ GITS_BASER + i * 8, &s->baser[i], false,
148
+ &error_abort);
149
+ }
150
+
151
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
152
+ GITS_CTLR, &s->ctlr, false, &error_abort);
153
+
154
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
155
+ GITS_CBASER, &s->cbaser, false, &error_abort);
156
+
157
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
158
+ GITS_CREADR, &s->creadr, false, &error_abort);
159
+
160
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
161
+ GITS_CWRITER, &s->cwriter, false, &error_abort);
162
+
163
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
164
+ GITS_IIDR, &s->iidr, false, &error_abort);
165
+}
166
+
167
+/**
168
+ * kvm_arm_its_post_load - Restore both the ITS registers and tables
169
+ */
170
+static void kvm_arm_its_post_load(GICv3ITSState *s)
171
+{
172
+ int i;
173
+
174
+ if (!s->iidr) {
175
+ return;
176
+ }
177
+
178
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
179
+ GITS_IIDR, &s->iidr, true, &error_abort);
180
+
181
+ /*
182
+ * must be written before GITS_CREADR since GITS_CBASER write
183
+ * access resets GITS_CREADR.
184
+ */
185
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
186
+ GITS_CBASER, &s->cbaser, true, &error_abort);
187
+
188
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
189
+ GITS_CREADR, &s->creadr, true, &error_abort);
190
+
191
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
192
+ GITS_CWRITER, &s->cwriter, true, &error_abort);
193
+
194
+
195
+ for (i = 0; i < 8; i++) {
196
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
197
+ GITS_BASER + i * 8, &s->baser[i], true,
198
+ &error_abort);
199
+ }
200
+
201
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
202
+ KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true,
203
+ &error_abort);
204
+
205
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
206
+ GITS_CTLR, &s->ctlr, true, &error_abort);
207
+}
208
+
209
static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
210
{
211
DeviceClass *dc = DEVICE_CLASS(klass);
212
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
213
214
dc->realize = kvm_arm_its_realize;
215
icc->send_msi = kvm_its_send_msi;
216
+ icc->pre_save = kvm_arm_its_pre_save;
217
+ icc->post_load = kvm_arm_its_post_load;
218
}
219
220
static const TypeInfo kvm_arm_its_info = {
221
--
98
--
222
2.7.4
99
2.20.1
223
100
224
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/17] timer/aspeed: fix timer enablement when a reload is not set
[PULL 4/8] msf2-soc, stellaris: Don't wire up SYSRESETREQ
1
From: Cédric Le Goater <clg@kaod.org>
1
The MSF2 SoC model and the Stellaris board code both wire
2
SYSRESETREQ up to a function that just invokes
3
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4
This is now the default action that the NVIC does if the line is
5
not connected, so we can delete the handling code.
2
6
3
When a timer is enabled before a reload value is set, the controller
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
waits for a reload value to be set before starting decrementing. This
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
fix tries to cover that case by changing the timer expiry only when
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
a reload value is valid.
10
Message-id: 20200728103744.6909-4-peter.maydell@linaro.org
11
---
12
hw/arm/msf2-soc.c | 11 -----------
13
hw/arm/stellaris.c | 12 ------------
14
2 files changed, 23 deletions(-)
7
15
8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
16
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
9
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
10
Message-id: 1496739312-32304-1-git-send-email-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/timer/aspeed_timer.c | 37 +++++++++++++++++++++++++++++--------
14
1 file changed, 29 insertions(+), 8 deletions(-)
15
16
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/aspeed_timer.c
18
--- a/hw/arm/msf2-soc.c
19
+++ b/hw/timer/aspeed_timer.c
19
+++ b/hw/arm/msf2-soc.c
20
@@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t)
20
@@ -XXX,XX +XXX,XX @@
21
next = seq[1];
21
#include "hw/irq.h"
22
} else if (now < seq[2]) {
22
#include "hw/arm/msf2-soc.h"
23
next = seq[2];
23
#include "hw/misc/unimp.h"
24
- } else {
24
-#include "sysemu/runstate.h"
25
+ } else if (t->reload) {
25
#include "sysemu/sysemu.h"
26
reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate);
26
27
t->start = now - ((now - t->start) % reload_ns);
27
#define MSF2_TIMER_BASE 0x40004000
28
+ } else {
28
@@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
29
+ /* no reload value, return 0 */
29
static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
30
+ break;
30
static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
31
}
31
32
-static void do_sys_reset(void *opaque, int n, int level)
33
-{
34
- if (level) {
35
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
36
- }
37
-}
38
-
39
static void m2sxxx_soc_initfn(Object *obj)
40
{
41
MSF2State *s = MSF2_SOC(obj);
42
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
43
return;
32
}
44
}
33
45
34
return next;
46
- qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
47
- qemu_allocate_irq(&do_sys_reset, NULL, 0));
48
-
49
system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
50
51
for (i = 0; i < MSF2_NUM_UARTS; i++) {
52
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/stellaris.c
55
+++ b/hw/arm/stellaris.c
56
@@ -XXX,XX +XXX,XX @@
57
#include "hw/boards.h"
58
#include "qemu/log.h"
59
#include "exec/address-spaces.h"
60
-#include "sysemu/runstate.h"
61
#include "sysemu/sysemu.h"
62
#include "hw/arm/armv7m.h"
63
#include "hw/char/pl011.h"
64
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
65
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
35
}
66
}
36
67
37
+static void aspeed_timer_mod(AspeedTimer *t)
68
-static
38
+{
69
-void do_sys_reset(void *opaque, int n, int level)
39
+ uint64_t next = calculate_next(t);
70
-{
40
+ if (next) {
71
- if (level) {
41
+ timer_mod(&t->timer, next);
72
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
42
+ }
73
- }
43
+}
74
-}
44
+
75
-
45
static void aspeed_timer_expire(void *opaque)
76
/* Board init. */
46
{
77
static stellaris_board_info stellaris_boards[] = {
47
AspeedTimer *t = opaque;
78
{ "LM3S811EVB",
48
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_expire(void *opaque)
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
49
qemu_set_irq(t->irq, t->level);
80
/* This will exit with an error if the user passed us a bad cpu_type */
50
}
81
sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
51
82
52
- timer_mod(&t->timer, calculate_next(t));
83
- qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
53
+ aspeed_timer_mod(t);
84
- qemu_allocate_irq(&do_sys_reset, NULL, 0));
54
}
85
-
55
86
if (board->dc1 & (1 << 16)) {
56
static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
87
dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
57
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
88
qdev_get_gpio_in(nvic, 14),
58
uint32_t value)
59
{
60
AspeedTimer *t;
61
+ uint32_t old_reload;
62
63
trace_aspeed_timer_set_value(timer, reg, value);
64
t = &s->timers[timer];
65
switch (reg) {
66
+ case TIMER_REG_RELOAD:
67
+ old_reload = t->reload;
68
+ t->reload = value;
69
+
70
+ /* If the reload value was not previously set, or zero, and
71
+ * the current value is valid, try to start the timer if it is
72
+ * enabled.
73
+ */
74
+ if (old_reload || !t->reload) {
75
+ break;
76
+ }
77
+
78
case TIMER_REG_STATUS:
79
if (timer_enabled(t)) {
80
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
81
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
82
uint32_t rate = calculate_rate(t);
83
84
t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
85
- timer_mod(&t->timer, calculate_next(t));
86
+ aspeed_timer_mod(t);
87
}
88
break;
89
- case TIMER_REG_RELOAD:
90
- t->reload = value;
91
- break;
92
case TIMER_REG_MATCH_FIRST:
93
case TIMER_REG_MATCH_SECOND:
94
t->match[reg - 2] = value;
95
if (timer_enabled(t)) {
96
- timer_mod(&t->timer, calculate_next(t));
97
+ aspeed_timer_mod(t);
98
}
99
break;
100
default:
101
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable)
102
trace_aspeed_timer_ctrl_enable(t->id, enable);
103
if (enable) {
104
t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
105
- timer_mod(&t->timer, calculate_next(t));
106
+ aspeed_timer_mod(t);
107
} else {
108
timer_del(&t->timer);
109
}
110
--
89
--
111
2.7.4
90
2.20.1
112
91
113
92
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/17] hw/misc: add a TMP42{1, 2, 3} device model
[PULL 5/8] target/arm: Fix AddPAC error indication
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Largely inspired by the TMP105 temperature sensor, here is a model for
3
The definition of top_bit used in this function is one higher
4
the TMP42{1,2,3} temperature sensors.
4
than that used in the Arm ARM psuedo-code, which put the error
5
indication at top_bit - 1 at the wrong place, which meant that
6
it wasn't visible to Auth.
5
7
6
Specs can be found here :
8
Fixing the definition of top_bit requires more changes, because
9
its most common use is for the count of bits in top_bit:bot_bit,
10
which would then need to be computed as top_bit - bot_bit + 1.
7
11
8
    http://www.ti.com/lit/gpn/tmp421
12
For now, prefer the minimal fix to the error indication alone.
9
13
10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
Fixes: 63ff0ca94cb
11
Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org
15
Reported-by: Derrick McKee <derrick.mckee@gmail.com>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200728195706.11087-1-richard.henderson@linaro.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
[PMM: added comment about the divergence from the pseudocode]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
---
21
---
15
hw/misc/Makefile.objs | 1 +
22
target/arm/pauth_helper.c | 6 +++++-
16
hw/misc/tmp421.c | 402 ++++++++++++++++++++++++++++++++++++++++
23
tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++
17
default-configs/arm-softmmu.mak | 1 +
24
tests/tcg/aarch64/Makefile.target | 2 +-
18
3 files changed, 404 insertions(+)
25
3 files changed, 39 insertions(+), 2 deletions(-)
19
create mode 100644 hw/misc/tmp421.c
26
create mode 100644 tests/tcg/aarch64/pauth-5.c
20
27
21
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
28
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
22
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/misc/Makefile.objs
30
--- a/target/arm/pauth_helper.c
24
+++ b/hw/misc/Makefile.objs
31
+++ b/target/arm/pauth_helper.c
25
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
26
common-obj-$(CONFIG_APPLESMC) += applesmc.o
33
*/
27
common-obj-$(CONFIG_MAX111X) += max111x.o
34
test = sextract64(ptr, bot_bit, top_bit - bot_bit);
28
common-obj-$(CONFIG_TMP105) += tmp105.o
35
if (test != 0 && test != -1) {
29
+common-obj-$(CONFIG_TMP421) += tmp421.o
36
- pac ^= MAKE_64BIT_MASK(top_bit - 1, 1);
30
common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o
37
+ /*
31
common-obj-$(CONFIG_SGA) += sga.o
38
+ * Note that our top_bit is one greater than the pseudocode's
32
common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
39
+ * version, hence "- 2" here.
33
diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c
40
+ */
41
+ pac ^= MAKE_64BIT_MASK(top_bit - 2, 1);
42
}
43
44
/*
45
diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c
34
new file mode 100644
46
new file mode 100644
35
index XXXXXXX..XXXXXXX
47
index XXXXXXX..XXXXXXX
36
--- /dev/null
48
--- /dev/null
37
+++ b/hw/misc/tmp421.c
49
+++ b/tests/tcg/aarch64/pauth-5.c
38
@@ -XXX,XX +XXX,XX @@
50
@@ -XXX,XX +XXX,XX @@
39
+/*
51
+#include <assert.h>
40
+ * Texas Instruments TMP421 temperature sensor.
41
+ *
42
+ * Copyright (c) 2016 IBM Corporation.
43
+ *
44
+ * Largely inspired by :
45
+ *
46
+ * Texas Instruments TMP105 temperature sensor.
47
+ *
48
+ * Copyright (C) 2008 Nokia Corporation
49
+ * Written by Andrzej Zaborowski <andrew@openedhand.com>
50
+ *
51
+ * This program is free software; you can redistribute it and/or
52
+ * modify it under the terms of the GNU General Public License as
53
+ * published by the Free Software Foundation; either version 2 or
54
+ * (at your option) version 3 of the License.
55
+ *
56
+ * This program is distributed in the hope that it will be useful,
57
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
58
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
59
+ * GNU General Public License for more details.
60
+ *
61
+ * You should have received a copy of the GNU General Public License along
62
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
63
+ */
64
+
52
+
65
+#include "qemu/osdep.h"
53
+static int x;
66
+#include "hw/hw.h"
67
+#include "hw/i2c/i2c.h"
68
+#include "qapi/error.h"
69
+#include "qapi/visitor.h"
70
+
54
+
71
+/* Manufacturer / Device ID's */
55
+int main()
72
+#define TMP421_MANUFACTURER_ID 0x55
56
+{
73
+#define TMP421_DEVICE_ID 0x21
57
+ int *p0 = &x, *p1, *p2, *p3;
74
+#define TMP422_DEVICE_ID 0x22
58
+ unsigned long salt = 0;
75
+#define TMP423_DEVICE_ID 0x23
76
+
59
+
77
+typedef struct DeviceInfo {
60
+ /*
78
+ int model;
61
+ * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so
79
+ const char *name;
62
+ * a 1/128 chance of auth = pac(ptr,key,salt) producing zero.
80
+} DeviceInfo;
63
+ * Find a salt that creates auth != 0.
64
+ */
65
+ do {
66
+ salt++;
67
+ asm("pacda %0, %1" : "=r"(p1) : "r"(salt), "0"(p0));
68
+ } while (p0 == p1);
81
+
69
+
82
+static const DeviceInfo devices[] = {
70
+ /*
83
+ { TMP421_DEVICE_ID, "tmp421" },
71
+ * This pac must fail, because the input pointer bears an encryption,
84
+ { TMP422_DEVICE_ID, "tmp422" },
72
+ * and so is not properly extended within bits [55:47]. This will
85
+ { TMP423_DEVICE_ID, "tmp423" },
73
+ * toggle bit 54 in the output...
86
+};
74
+ */
75
+ asm("pacda %0, %1" : "=r"(p2) : "r"(salt), "0"(p1));
87
+
76
+
88
+typedef struct TMP421State {
77
+ /* ... so that the aut must fail, setting bit 53 in the output ... */
89
+ /*< private >*/
78
+ asm("autda %0, %1" : "=r"(p3) : "r"(salt), "0"(p2));
90
+ I2CSlave i2c;
91
+ /*< public >*/
92
+
79
+
93
+ int16_t temperature[4];
80
+ /* ... which means this equality must not hold. */
94
+
81
+ assert(p3 != p0);
95
+ uint8_t status;
96
+ uint8_t config[2];
97
+ uint8_t rate;
98
+
99
+ uint8_t len;
100
+ uint8_t buf[2];
101
+ uint8_t pointer;
102
+
103
+} TMP421State;
104
+
105
+typedef struct TMP421Class {
106
+ I2CSlaveClass parent_class;
107
+ DeviceInfo *dev;
108
+} TMP421Class;
109
+
110
+#define TYPE_TMP421 "tmp421-generic"
111
+#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421)
112
+
113
+#define TMP421_CLASS(klass) \
114
+ OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421)
115
+#define TMP421_GET_CLASS(obj) \
116
+ OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421)
117
+
118
+/* the TMP421 registers */
119
+#define TMP421_STATUS_REG 0x08
120
+#define TMP421_STATUS_BUSY (1 << 7)
121
+#define TMP421_CONFIG_REG_1 0x09
122
+#define TMP421_CONFIG_RANGE (1 << 2)
123
+#define TMP421_CONFIG_SHUTDOWN (1 << 6)
124
+#define TMP421_CONFIG_REG_2 0x0A
125
+#define TMP421_CONFIG_RC (1 << 2)
126
+#define TMP421_CONFIG_LEN (1 << 3)
127
+#define TMP421_CONFIG_REN (1 << 4)
128
+#define TMP421_CONFIG_REN2 (1 << 5)
129
+#define TMP421_CONFIG_REN3 (1 << 6)
130
+
131
+#define TMP421_CONVERSION_RATE_REG 0x0B
132
+#define TMP421_ONE_SHOT 0x0F
133
+
134
+#define TMP421_RESET 0xFC
135
+#define TMP421_MANUFACTURER_ID_REG 0xFE
136
+#define TMP421_DEVICE_ID_REG 0xFF
137
+
138
+#define TMP421_TEMP_MSB0 0x00
139
+#define TMP421_TEMP_MSB1 0x01
140
+#define TMP421_TEMP_MSB2 0x02
141
+#define TMP421_TEMP_MSB3 0x03
142
+#define TMP421_TEMP_LSB0 0x10
143
+#define TMP421_TEMP_LSB1 0x11
144
+#define TMP421_TEMP_LSB2 0x12
145
+#define TMP421_TEMP_LSB3 0x13
146
+
147
+static const int32_t mins[2] = { -40000, -55000 };
148
+static const int32_t maxs[2] = { 127000, 150000 };
149
+
150
+static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name,
151
+ void *opaque, Error **errp)
152
+{
153
+ TMP421State *s = TMP421(obj);
154
+ bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
155
+ int offset = ext_range * 64 * 256;
156
+ int64_t value;
157
+ int tempid;
158
+
159
+ if (sscanf(name, "temperature%d", &tempid) != 1) {
160
+ error_setg(errp, "error reading %s: %m", name);
161
+ return;
162
+ }
163
+
164
+ if (tempid >= 4 || tempid < 0) {
165
+ error_setg(errp, "error reading %s", name);
166
+ return;
167
+ }
168
+
169
+ value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256;
170
+
171
+ visit_type_int(v, name, &value, errp);
172
+}
173
+
174
+/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8
175
+ * fixed point, so units are 1/256 centigrades. A simple ratio will do.
176
+ */
177
+static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name,
178
+ void *opaque, Error **errp)
179
+{
180
+ TMP421State *s = TMP421(obj);
181
+ Error *local_err = NULL;
182
+ int64_t temp;
183
+ bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
184
+ int offset = ext_range * 64 * 256;
185
+ int tempid;
186
+
187
+ visit_type_int(v, name, &temp, &local_err);
188
+ if (local_err) {
189
+ error_propagate(errp, local_err);
190
+ return;
191
+ }
192
+
193
+ if (temp >= maxs[ext_range] || temp < mins[ext_range]) {
194
+ error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range",
195
+ temp / 1000, temp % 1000);
196
+ return;
197
+ }
198
+
199
+ if (sscanf(name, "temperature%d", &tempid) != 1) {
200
+ error_setg(errp, "error reading %s: %m", name);
201
+ return;
202
+ }
203
+
204
+ if (tempid >= 4 || tempid < 0) {
205
+ error_setg(errp, "error reading %s", name);
206
+ return;
207
+ }
208
+
209
+ s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset;
210
+}
211
+
212
+static void tmp421_read(TMP421State *s)
213
+{
214
+ TMP421Class *sc = TMP421_GET_CLASS(s);
215
+
216
+ s->len = 0;
217
+
218
+ switch (s->pointer) {
219
+ case TMP421_MANUFACTURER_ID_REG:
220
+ s->buf[s->len++] = TMP421_MANUFACTURER_ID;
221
+ break;
222
+ case TMP421_DEVICE_ID_REG:
223
+ s->buf[s->len++] = sc->dev->model;
224
+ break;
225
+ case TMP421_CONFIG_REG_1:
226
+ s->buf[s->len++] = s->config[0];
227
+ break;
228
+ case TMP421_CONFIG_REG_2:
229
+ s->buf[s->len++] = s->config[1];
230
+ break;
231
+ case TMP421_CONVERSION_RATE_REG:
232
+ s->buf[s->len++] = s->rate;
233
+ break;
234
+ case TMP421_STATUS_REG:
235
+ s->buf[s->len++] = s->status;
236
+ break;
237
+
238
+ /* FIXME: check for channel enablement in config registers */
239
+ case TMP421_TEMP_MSB0:
240
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8);
241
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
242
+ break;
243
+ case TMP421_TEMP_MSB1:
244
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8);
245
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
246
+ break;
247
+ case TMP421_TEMP_MSB2:
248
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8);
249
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
250
+ break;
251
+ case TMP421_TEMP_MSB3:
252
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8);
253
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
254
+ break;
255
+ case TMP421_TEMP_LSB0:
256
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
257
+ break;
258
+ case TMP421_TEMP_LSB1:
259
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
260
+ break;
261
+ case TMP421_TEMP_LSB2:
262
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
263
+ break;
264
+ case TMP421_TEMP_LSB3:
265
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
266
+ break;
267
+ }
268
+}
269
+
270
+static void tmp421_reset(I2CSlave *i2c);
271
+
272
+static void tmp421_write(TMP421State *s)
273
+{
274
+ switch (s->pointer) {
275
+ case TMP421_CONVERSION_RATE_REG:
276
+ s->rate = s->buf[0];
277
+ break;
278
+ case TMP421_CONFIG_REG_1:
279
+ s->config[0] = s->buf[0];
280
+ break;
281
+ case TMP421_CONFIG_REG_2:
282
+ s->config[1] = s->buf[0];
283
+ break;
284
+ case TMP421_RESET:
285
+ tmp421_reset(I2C_SLAVE(s));
286
+ break;
287
+ }
288
+}
289
+
290
+static int tmp421_rx(I2CSlave *i2c)
291
+{
292
+ TMP421State *s = TMP421(i2c);
293
+
294
+ if (s->len < 2) {
295
+ return s->buf[s->len++];
296
+ } else {
297
+ return 0xff;
298
+ }
299
+}
300
+
301
+static int tmp421_tx(I2CSlave *i2c, uint8_t data)
302
+{
303
+ TMP421State *s = TMP421(i2c);
304
+
305
+ if (s->len == 0) {
306
+ /* first byte is the register pointer for a read or write
307
+ * operation */
308
+ s->pointer = data;
309
+ s->len++;
310
+ } else if (s->len == 1) {
311
+ /* second byte is the data to write. The device only supports
312
+ * one byte writes */
313
+ s->buf[0] = data;
314
+ tmp421_write(s);
315
+ }
316
+
317
+ return 0;
82
+ return 0;
318
+}
83
+}
319
+
84
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
320
+static int tmp421_event(I2CSlave *i2c, enum i2c_event event)
321
+{
322
+ TMP421State *s = TMP421(i2c);
323
+
324
+ if (event == I2C_START_RECV) {
325
+ tmp421_read(s);
326
+ }
327
+
328
+ s->len = 0;
329
+ return 0;
330
+}
331
+
332
+static const VMStateDescription vmstate_tmp421 = {
333
+ .name = "TMP421",
334
+ .version_id = 0,
335
+ .minimum_version_id = 0,
336
+ .fields = (VMStateField[]) {
337
+ VMSTATE_UINT8(len, TMP421State),
338
+ VMSTATE_UINT8_ARRAY(buf, TMP421State, 2),
339
+ VMSTATE_UINT8(pointer, TMP421State),
340
+ VMSTATE_UINT8_ARRAY(config, TMP421State, 2),
341
+ VMSTATE_UINT8(status, TMP421State),
342
+ VMSTATE_UINT8(rate, TMP421State),
343
+ VMSTATE_INT16_ARRAY(temperature, TMP421State, 4),
344
+ VMSTATE_I2C_SLAVE(i2c, TMP421State),
345
+ VMSTATE_END_OF_LIST()
346
+ }
347
+};
348
+
349
+static void tmp421_reset(I2CSlave *i2c)
350
+{
351
+ TMP421State *s = TMP421(i2c);
352
+ TMP421Class *sc = TMP421_GET_CLASS(s);
353
+
354
+ memset(s->temperature, 0, sizeof(s->temperature));
355
+ s->pointer = 0;
356
+
357
+ s->config[0] = 0; /* TMP421_CONFIG_RANGE */
358
+
359
+ /* resistance correction and channel enablement */
360
+ switch (sc->dev->model) {
361
+ case TMP421_DEVICE_ID:
362
+ s->config[1] = 0x1c;
363
+ break;
364
+ case TMP422_DEVICE_ID:
365
+ s->config[1] = 0x3c;
366
+ break;
367
+ case TMP423_DEVICE_ID:
368
+ s->config[1] = 0x7c;
369
+ break;
370
+ }
371
+
372
+ s->rate = 0x7; /* 8Hz */
373
+ s->status = 0;
374
+}
375
+
376
+static int tmp421_init(I2CSlave *i2c)
377
+{
378
+ TMP421State *s = TMP421(i2c);
379
+
380
+ tmp421_reset(&s->i2c);
381
+
382
+ return 0;
383
+}
384
+
385
+static void tmp421_initfn(Object *obj)
386
+{
387
+ object_property_add(obj, "temperature0", "int",
388
+ tmp421_get_temperature,
389
+ tmp421_set_temperature, NULL, NULL, NULL);
390
+ object_property_add(obj, "temperature1", "int",
391
+ tmp421_get_temperature,
392
+ tmp421_set_temperature, NULL, NULL, NULL);
393
+ object_property_add(obj, "temperature2", "int",
394
+ tmp421_get_temperature,
395
+ tmp421_set_temperature, NULL, NULL, NULL);
396
+ object_property_add(obj, "temperature3", "int",
397
+ tmp421_get_temperature,
398
+ tmp421_set_temperature, NULL, NULL, NULL);
399
+}
400
+
401
+static void tmp421_class_init(ObjectClass *klass, void *data)
402
+{
403
+ DeviceClass *dc = DEVICE_CLASS(klass);
404
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
405
+ TMP421Class *sc = TMP421_CLASS(klass);
406
+
407
+ k->init = tmp421_init;
408
+ k->event = tmp421_event;
409
+ k->recv = tmp421_rx;
410
+ k->send = tmp421_tx;
411
+ dc->vmsd = &vmstate_tmp421;
412
+ sc->dev = (DeviceInfo *) data;
413
+}
414
+
415
+static const TypeInfo tmp421_info = {
416
+ .name = TYPE_TMP421,
417
+ .parent = TYPE_I2C_SLAVE,
418
+ .instance_size = sizeof(TMP421State),
419
+ .class_size = sizeof(TMP421Class),
420
+ .instance_init = tmp421_initfn,
421
+ .abstract = true,
422
+};
423
+
424
+static void tmp421_register_types(void)
425
+{
426
+ int i;
427
+
428
+ type_register_static(&tmp421_info);
429
+ for (i = 0; i < ARRAY_SIZE(devices); ++i) {
430
+ TypeInfo ti = {
431
+ .name = devices[i].name,
432
+ .parent = TYPE_TMP421,
433
+ .class_init = tmp421_class_init,
434
+ .class_data = (void *) &devices[i],
435
+ };
436
+ type_register(&ti);
437
+ }
438
+}
439
+
440
+type_init(tmp421_register_types)
441
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
442
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
443
--- a/default-configs/arm-softmmu.mak
86
--- a/tests/tcg/aarch64/Makefile.target
444
+++ b/default-configs/arm-softmmu.mak
87
+++ b/tests/tcg/aarch64/Makefile.target
445
@@ -XXX,XX +XXX,XX @@ CONFIG_TWL92230=y
88
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
446
CONFIG_TSC2005=y
89
447
CONFIG_LM832X=y
90
# Pauth Tests
448
CONFIG_TMP105=y
91
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_3),)
449
+CONFIG_TMP421=y
92
-AARCH64_TESTS += pauth-1 pauth-2 pauth-4
450
CONFIG_STELLARIS=y
93
+AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5
451
CONFIG_STELLARIS_INPUT=y
94
pauth-%: CFLAGS += -march=armv8.3-a
452
CONFIG_STELLARIS_ENET=y
95
run-pauth-%: QEMU_OPTS += -cpu max
96
run-plugin-pauth-%: QEMU_OPTS += -cpu max
453
--
97
--
454
2.7.4
98
2.20.1
455
99
456
100
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/17] hw/intc/exynos4210_gic: Constify array of combiner interrupts
[PULL 6/8] target/arm: Avoid maybe-uninitialized warning with gcc 4.9
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Kaige Li <likaige@loongson.cn>
2
2
3
The static array of interrupt combiner mappings is not modified so it
3
GCC version 4.9.4 isn't clever enough to figure out that all
4
can be made const for code safeness.
4
execution paths in disas_ldst() that use 'fn' will have initialized
5
it first, and so it warns:
5
6
6
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
7
/home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’:
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
/home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
9
fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
10
^
11
/home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here
12
AtomicThreeOpFn *fn;
13
^
14
15
Make it happy by initializing the variable to NULL.
16
17
Signed-off-by: Kaige Li <likaige@loongson.cn>
18
Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
[PMM: Clean up commit message and note which gcc version this was]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
22
---
10
hw/intc/exynos4210_gic.c | 2 +-
23
target/arm/translate-a64.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
24
1 file changed, 1 insertion(+), 1 deletion(-)
12
25
13
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
26
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/exynos4210_gic.c
28
--- a/target/arm/translate-a64.c
16
+++ b/hw/intc/exynos4210_gic.c
29
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ enum ExtInt {
30
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
18
* which is INTG16 in Internal Interrupt Combiner.
31
bool r = extract32(insn, 22, 1);
19
*/
32
bool a = extract32(insn, 23, 1);
20
33
TCGv_i64 tcg_rs, clean_addr;
21
-static uint32_t
34
- AtomicThreeOpFn *fn;
22
+static const uint32_t
35
+ AtomicThreeOpFn *fn = NULL;
23
combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
36
24
/* int combiner groups 16-19 */
37
if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
25
{ }, { }, { }, { },
38
unallocated_encoding(s);
26
--
39
--
27
2.7.4
40
2.20.1
28
41
29
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/17] hw/misc/exynos4210_pmu: Add support for system poweroff
Deleted patch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
2
1
3
On all Exynos-based boards, the system powers down itself by driving
4
PS_HOLD signal low - eight bit in PS_HOLD_CONTROL register of PMU.
5
Handle writing to respective PMU register to fix power off failure:
6
7
reboot: Power down
8
Unable to poweroff system
9
shutdown: 31 output lines suppressed due to ratelimiting
10
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000000
11
12
CPU: 0 PID: 1 Comm: shutdown Not tainted 4.11.0-rc8 #846
13
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
14
[<c031050c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14)
15
[<c030ba6c>] (show_stack) from [<c05b2800>] (dump_stack+0x88/0x9c)
16
[<c05b2800>] (dump_stack) from [<c03d3140>] (panic+0xdc/0x268)
17
[<c03d3140>] (panic) from [<c0343614>] (do_exit+0xa90/0xab4)
18
[<c0343614>] (do_exit) from [<c035f2dc>] (SyS_reboot+0x164/0x1d0)
19
[<c035f2dc>] (SyS_reboot) from [<c0307c80>] (ret_fast_syscall+0x0/0x3c)
20
21
Additionally the initial value of PS_HOLD has to be changed because
22
recent Linux kernel (v4.12-rc1) uses regmap cache for this access.
23
When the register is kept at reset value, the kernel will not issue a
24
write to it. Usually the bootloader sets the eight bit of PS_HOLD high
25
so mimic its existence here.
26
27
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
32
hw/misc/exynos4210_pmu.c | 20 +++++++++++++++++++-
33
1 file changed, 19 insertions(+), 1 deletion(-)
34
35
diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/misc/exynos4210_pmu.c
38
+++ b/hw/misc/exynos4210_pmu.c
39
@@ -XXX,XX +XXX,XX @@
40
41
#include "qemu/osdep.h"
42
#include "hw/sysbus.h"
43
+#include "sysemu/sysemu.h"
44
45
#ifndef DEBUG_PMU
46
#define DEBUG_PMU 0
47
@@ -XXX,XX +XXX,XX @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
48
{"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000},
49
{"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000},
50
{"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000},
51
- {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200},
52
+ /*
53
+ * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit.
54
+ * DATA bit high, set usually by bootloader, keeps system on.
55
+ */
56
+ {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)},
57
{"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001},
58
{"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001},
59
{"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000},
60
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210PmuState {
61
uint32_t reg[PMU_NUM_OF_REGISTERS];
62
} Exynos4210PmuState;
63
64
+static void exynos4210_pmu_poweroff(void)
65
+{
66
+ PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n");
67
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
68
+}
69
+
70
static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
71
unsigned size)
72
{
73
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
74
PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
75
(uint32_t)offset, (uint32_t)val);
76
s->reg[i] = val;
77
+ if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) {
78
+ /*
79
+ * We are interested only in setting data bit
80
+ * of PS_HOLD_CONTROL register to indicate power off request.
81
+ */
82
+ exynos4210_pmu_poweroff();
83
+ }
84
return;
85
}
86
reg_p++;
87
--
88
2.7.4
89
90
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/17] kvm-all: Pass an error object to kvm_device_access
[PULL 7/8] hw/arm/nrf51_soc: Set system_clock_scale
1
From: Eric Auger <eric.auger@redhat.com>
1
The nrf51 SoC model wasn't setting the system_clock_scale
2
global.which meant that if guest code used the systick timer in "use
3
the processor clock" mode it would hang because time never advances.
2
4
3
In some circumstances, we don't want to abort if the
5
Set the global to match the documented CPU clock speed for this SoC.
4
kvm_device_access fails. This will be the case during ITS
5
migration, in case the ITS table save/restore fails because
6
the guest did not program the vITS correctly. So let's pass an
7
error object to the function and return the ioctl value. New
8
callers will be able to make a decision upon this returned
9
value.
10
6
11
Existing callers pass &error_abort which will cause the
7
This SoC in fact doesn't have a SysTick timer (which is the only thing
12
function to abort on failure.
8
currently that cares about the system_clock_scale), because it's
9
a configurable option in the Cortex-M0. However our Cortex-M0 and
10
thus our nrf51 and our micro:bit board do provide a SysTick, so
11
we ought to provide a functional one rather than a broken one.
13
12
14
Signed-off-by: Eric Auger <eric.auger@redhat.com>
15
Reviewed-by: Juan Quintela <quintela@redhat.com>
16
Reviewed-by: Peter Xu <peterx@redhat.com>
17
Message-id: 1497023553-18411-2-git-send-email-eric.auger@redhat.com
18
[PMM: wrapped long line]
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
20
---
16
---
21
include/sysemu/kvm.h | 11 +++++++----
17
hw/arm/nrf51_soc.c | 5 +++++
22
hw/intc/arm_gic_kvm.c | 9 +++++----
18
1 file changed, 5 insertions(+)
23
hw/intc/arm_gicv3_its_kvm.c | 2 +-
24
hw/intc/arm_gicv3_kvm.c | 14 +++++++-------
25
kvm-all.c | 14 ++++++++------
26
5 files changed, 28 insertions(+), 22 deletions(-)
27
19
28
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
20
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
29
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
30
--- a/include/sysemu/kvm.h
22
--- a/hw/arm/nrf51_soc.c
31
+++ b/include/sysemu/kvm.h
23
+++ b/hw/arm/nrf51_soc.c
32
@@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int fd, uint32_t group, uint64_t attr);
24
@@ -XXX,XX +XXX,XX @@
33
* @attr: the attribute of that group to set or get
25
34
* @val: pointer to a storage area for the value
26
#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
35
* @write: true for set and false for get operation
27
36
+ * @errp: error object handle
28
+/* HCLK (the main CPU clock) on this SoC is always 16MHz */
37
*
29
+#define HCLK_FRQ 16000000
38
- * This function is not allowed to fail. Use kvm_device_check_attr()
30
+
39
- * in order to check for the availability of optional attributes.
31
static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
40
+ * Returns: 0 on success
41
+ * < 0 on error
42
+ * Use kvm_device_check_attr() in order to check for the availability
43
+ * of optional attributes.
44
*/
45
-void kvm_device_access(int fd, int group, uint64_t attr,
46
- void *val, bool write);
47
+int kvm_device_access(int fd, int group, uint64_t attr,
48
+ void *val, bool write, Error **errp);
49
50
/**
51
* kvm_create_device - create a KVM device for the device control API
52
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/intc/arm_gic_kvm.c
55
+++ b/hw/intc/arm_gic_kvm.c
56
@@ -XXX,XX +XXX,XX @@ static void kvm_gicd_access(GICState *s, int offset, int cpu,
57
uint32_t *val, bool write)
58
{
32
{
59
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
33
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
60
- KVM_VGIC_ATTR(offset, cpu), val, write);
34
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
61
+ KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
35
return;
62
}
63
64
static void kvm_gicc_access(GICState *s, int offset, int cpu,
65
uint32_t *val, bool write)
66
{
67
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
68
- KVM_VGIC_ATTR(offset, cpu), val, write);
69
+ KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
70
}
71
72
#define for_each_irq_reg(_ctr, _max_irq, _field_width) \
73
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
74
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
75
uint32_t numirqs = s->num_irq;
76
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0,
77
- &numirqs, true);
78
+ &numirqs, true, &error_abort);
79
}
80
/* Tell the kernel to complete VGIC initialization now */
81
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
82
KVM_DEV_ARM_VGIC_CTRL_INIT)) {
83
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
84
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
85
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
86
+ &error_abort);
87
}
88
} else if (ret != -ENODEV && ret != -ENOTSUP) {
89
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
90
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/intc/arm_gicv3_its_kvm.c
93
+++ b/hw/intc/arm_gicv3_its_kvm.c
94
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
95
96
/* explicit init of the ITS */
97
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
98
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
99
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
100
101
/* register the base address */
102
kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
103
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/hw/intc/arm_gicv3_kvm.c
106
+++ b/hw/intc/arm_gicv3_kvm.c
107
@@ -XXX,XX +XXX,XX @@ static inline void kvm_gicd_access(GICv3State *s, int offset,
108
{
109
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
110
KVM_VGIC_ATTR(offset, 0),
111
- val, write);
112
+ val, write, &error_abort);
113
}
114
115
static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
116
@@ -XXX,XX +XXX,XX @@ static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
117
{
118
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
119
KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
120
- val, write);
121
+ val, write, &error_abort);
122
}
123
124
static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
125
@@ -XXX,XX +XXX,XX @@ static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
126
{
127
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
128
KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
129
- val, write);
130
+ val, write, &error_abort);
131
}
132
133
static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
134
@@ -XXX,XX +XXX,XX @@ static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
135
KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
136
(VGIC_LEVEL_INFO_LINE_LEVEL <<
137
KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
138
- val, write);
139
+ val, write, &error_abort);
140
}
141
142
/* Loop through each distributor IRQ related register; since bits
143
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
144
/* Initialize to actual HW supported configuration */
145
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
146
KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
147
- &c->icc_ctlr_el1[GICV3_NS], false);
148
+ &c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
149
150
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
151
}
152
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
153
}
36
}
154
37
155
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
38
+ system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
156
- 0, &s->num_irq, true);
39
+
157
+ 0, &s->num_irq, true, &error_abort);
40
object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
158
41
&error_abort);
159
/* Tell the kernel to complete VGIC initialization now */
42
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
160
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
161
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
162
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
163
164
kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
165
KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd);
166
diff --git a/kvm-all.c b/kvm-all.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/kvm-all.c
169
+++ b/kvm-all.c
170
@@ -XXX,XX +XXX,XX @@
171
#include "qemu/option.h"
172
#include "qemu/config-file.h"
173
#include "qemu/error-report.h"
174
+#include "qapi/error.h"
175
#include "hw/hw.h"
176
#include "hw/pci/msi.h"
177
#include "hw/pci/msix.h"
178
@@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int dev_fd, uint32_t group, uint64_t attr)
179
return kvm_device_ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute) ? 0 : 1;
180
}
181
182
-void kvm_device_access(int fd, int group, uint64_t attr,
183
- void *val, bool write)
184
+int kvm_device_access(int fd, int group, uint64_t attr,
185
+ void *val, bool write, Error **errp)
186
{
187
struct kvm_device_attr kvmattr;
188
int err;
189
@@ -XXX,XX +XXX,XX @@ void kvm_device_access(int fd, int group, uint64_t attr,
190
write ? KVM_SET_DEVICE_ATTR : KVM_GET_DEVICE_ATTR,
191
&kvmattr);
192
if (err < 0) {
193
- error_report("KVM_%s_DEVICE_ATTR failed: %s",
194
- write ? "SET" : "GET", strerror(-err));
195
- error_printf("Group %d attr 0x%016" PRIx64 "\n", group, attr);
196
- abort();
197
+ error_setg_errno(errp, -err,
198
+ "KVM_%s_DEVICE_ATTR failed: Group %d "
199
+ "attr 0x%016" PRIx64,
200
+ write ? "SET" : "GET", group, attr);
201
}
202
+ return err;
203
}
204
205
/* Return 1 on success, 0 on failure */
206
--
43
--
207
2.7.4
44
2.20.1
208
45
209
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/17] timer.h: Provide better monotonic time
[PULL 8/8] hw/timer/imx_epit: Avoid assertion when CR.SWR is written
1
From: Pranith Kumar <bobby.prani@gmail.com>
1
The imx_epit device has a software-controllable reset triggered by
2
setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
3
means that we will end up assert()ing if the guest does this, because
4
the code in imx_epit_write() starts ptimer transactions, and then
5
imx_epit_reset() also starts ptimer transactions, triggering
6
"ptimer_transaction_begin: Assertion `!s->in_transaction' failed".
2
7
3
Tested and confirmed that the stretch i386 debian qcow2 image on a
8
The cleanest way to avoid this double-transaction is to move the
4
raspberry pi 2 works.
9
start-transaction for the CR write handling down below the check of
10
the SWR bit.
5
11
6
Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/>
12
Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
7
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
13
Fixes: cc2722ec83ad944505fe
8
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
9
Message-id: 20170418191817.10430-1-bobby.prani@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
11
---
17
---
12
include/qemu/timer.h | 5 ++---
18
hw/timer/imx_epit.c | 13 ++++++++++---
13
1 file changed, 2 insertions(+), 3 deletions(-)
19
1 file changed, 10 insertions(+), 3 deletions(-)
14
20
15
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
21
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
16
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
17
--- a/include/qemu/timer.h
23
--- a/hw/timer/imx_epit.c
18
+++ b/include/qemu/timer.h
24
+++ b/hw/timer/imx_epit.c
19
@@ -XXX,XX +XXX,XX @@ static inline int64_t cpu_get_host_ticks(void)
25
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
20
/* The host CPU doesn't have an easily accessible cycle counter.
26
21
Just return a monotonically increasing value. This will be
27
switch (offset >> 2) {
22
totally wrong, but hopefully better than nothing. */
28
case 0: /* CR */
23
-static inline int64_t cpu_get_host_ticks (void)
29
- ptimer_transaction_begin(s->timer_cmp);
24
+static inline int64_t cpu_get_host_ticks(void)
30
- ptimer_transaction_begin(s->timer_reload);
25
{
31
26
- static int64_t ticks = 0;
32
oldcr = s->cr;
27
- return ticks++;
33
s->cr = value & 0x03ffffff;
28
+ return get_clock();
34
if (s->cr & CR_SWR) {
29
}
35
/* handle the reset */
30
#endif
36
imx_epit_reset(DEVICE(s));
37
- } else {
38
+ /*
39
+ * TODO: could we 'break' here? following operations appear
40
+ * to duplicate the work imx_epit_reset() already did.
41
+ */
42
+ }
43
+
44
+ ptimer_transaction_begin(s->timer_cmp);
45
+ ptimer_transaction_begin(s->timer_reload);
46
+
47
+ if (!(s->cr & CR_SWR)) {
48
imx_epit_set_freq(s);
49
}
31
50
32
--
51
--
33
2.7.4
52
2.20.1
34
53
35
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/17] aspeed: add a temp sensor device on I2C bus 3
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
Temperatures can be changed from the monitor with :
4
5
    (qemu) qom-set /machine/unattached/device[2] temperature0 12000
6
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 1496739230-32109-3-git-send-email-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/aspeed.c | 9 +++++++++
13
1 file changed, 9 insertions(+)
14
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed.c
18
+++ b/hw/arm/aspeed.c
19
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
20
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
21
{
22
AspeedSoCState *soc = &bmc->soc;
23
+ DeviceState *dev;
24
25
/* The palmetto platform expects a ds3231 RTC but a ds1338 is
26
* enough to provide basic RTC features. Alarms will be missing */
27
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
28
+
29
+ /* add a TMP423 temperature sensor */
30
+ dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
31
+ "tmp423", 0x4c);
32
+ object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
33
+ object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
34
+ object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
35
+ object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
36
}
37
38
static void palmetto_bmc_init(MachineState *machine)
39
--
40
2.7.4
41
42
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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