[Qemu-devel] [PULL 00/17] target-arm queue
[Qemu-devel] [PULL 00/25] target-arm queue
1
Target-arm queue...
1
target-arm queue. This has the "plumb txattrs through various
2
bits of exec.c" patches, and a collection of bug fixes from
3
various people.
2
4
3
thanks
5
thanks
4
-- PMM
6
-- PMM
5
7
6
The following changes since commit 735286a4f88255e1463d42ce28d8d14181fd32d4:
7
8
8
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170613' into staging (2017-06-13 13:51:29 +0100)
9
9
10
are available in the git repository at:
10
The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
11
11
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170613
12
Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
13
13
14
for you to fetch changes up to 252a7a6a968c279a4636a86b0559ba3a930a90b5:
14
are available in the Git repository at:
15
15
16
hw/intc/arm_gicv3_its: Allow save/restore (2017-06-13 14:57:01 +0100)
16
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
17
18
for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
19
20
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
17
21
18
----------------------------------------------------------------
22
----------------------------------------------------------------
19
target-arm queue:
23
target-arm queue:
20
* vITS: Support save/restore
24
* target/arm: Honour FPCR.FZ in FRECPX
21
* timer/aspeed: Fix timer enablement when reload is not set
25
* MAINTAINERS: Add entries for newer MPS2 boards and devices
22
* aspped: add temperature sensor device
26
* hw/intc/arm_gicv3: Fix APxR<n> register dispatching
23
* timer.h: Provide better monotonic time on ARM hosts
27
* arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
24
* exynos4210: various cleanups
28
GIC state
25
* exynos4210: support system poweroff
29
* tcg: Fix helper function vs host abi for float16
30
* arm: fix qemu crash on startup with -bios option
31
* arm: fix malloc type mismatch
32
* xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
33
* Correct CPACR reset value for v7 cores
34
* memory.h: Improve IOMMU related documentation
35
* exec: Plumb transaction attributes through various functions in
36
preparation for allowing IOMMUs to see them
37
* vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
38
* ARM: ACPI: Fix use-after-free due to memory realloc
39
* KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
26
40
27
----------------------------------------------------------------
41
----------------------------------------------------------------
28
Cédric Le Goater (3):
42
Francisco Iglesias (1):
29
hw/misc: add a TMP42{1, 2, 3} device model
43
xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
30
aspeed: add a temp sensor device on I2C bus 3
31
timer/aspeed: fix timer enablement when a reload is not set
32
44
33
Eric Auger (4):
45
Igor Mammedov (1):
34
kvm-all: Pass an error object to kvm_device_access
46
arm: fix qemu crash on startup with -bios option
35
hw/intc/arm_gicv3_its: Implement state save/restore
36
hw/intc/arm_gicv3_kvm: Implement pending table save
37
hw/intc/arm_gicv3_its: Allow save/restore
38
47
39
Krzysztof Kozlowski (9):
48
Jan Kiszka (1):
40
hw/intc/exynos4210_gic: Use more meaningful name for local variable
49
hw/intc/arm_gicv3: Fix APxR<n> register dispatching
41
hw/timer/exynos4210_mct: Fix checkpatch style errors
42
hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
43
hw/timer/exynos4210_mct: Remove unused defines
44
hw/arm/exynos: Move DRAM initialization next boards
45
hw/arm/exynos: Declare local variables in some order
46
hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string
47
hw/intc/exynos4210_gic: Constify array of combiner interrupts
48
hw/misc/exynos4210_pmu: Add support for system poweroff
49
50
50
Pranith Kumar (1):
51
Paolo Bonzini (1):
51
timer.h: Provide better monotonic time
52
arm: fix malloc type mismatch
52
53
53
hw/misc/Makefile.objs | 1 +
54
Peter Maydell (17):
54
include/hw/arm/exynos4210.h | 5 +-
55
target/arm: Honour FPCR.FZ in FRECPX
55
include/hw/intc/arm_gicv3_its_common.h | 8 +
56
MAINTAINERS: Add entries for newer MPS2 boards and devices
56
include/migration/vmstate.h | 2 +
57
Correct CPACR reset value for v7 cores
57
include/qemu/timer.h | 5 +-
58
memory.h: Improve IOMMU related documentation
58
include/sysemu/kvm.h | 11 +-
59
Make tb_invalidate_phys_addr() take a MemTxAttrs argument
59
hw/arm/aspeed.c | 9 +
60
Make address_space_translate{, _cached}() take a MemTxAttrs argument
60
hw/arm/exynos4210.c | 27 +--
61
Make address_space_map() take a MemTxAttrs argument
61
hw/arm/exynos4_boards.c | 50 +++-
62
Make address_space_access_valid() take a MemTxAttrs argument
62
hw/intc/arm_gic_kvm.c | 9 +-
63
Make flatview_extend_translation() take a MemTxAttrs argument
63
hw/intc/arm_gicv3_common.c | 1 +
64
Make memory_region_access_valid() take a MemTxAttrs argument
64
hw/intc/arm_gicv3_its_common.c | 12 +-
65
Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
65
hw/intc/arm_gicv3_its_kvm.c | 131 +++++++++--
66
Make flatview_access_valid() take a MemTxAttrs argument
66
hw/intc/arm_gicv3_kvm.c | 48 +++-
67
Make flatview_translate() take a MemTxAttrs argument
67
hw/intc/exynos4210_gic.c | 14 +-
68
Make address_space_get_iotlb_entry() take a MemTxAttrs argument
68
hw/misc/exynos4210_pmu.c | 20 +-
69
Make flatview_do_translate() take a MemTxAttrs argument
69
hw/misc/tmp421.c | 402 +++++++++++++++++++++++++++++++++
70
Make address_space_translate_iommu take a MemTxAttrs argument
70
hw/timer/aspeed_timer.c | 37 ++-
71
vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
71
hw/timer/exynos4210_mct.c | 50 ++--
72
kvm-all.c | 14 +-
73
default-configs/arm-softmmu.mak | 1 +
74
21 files changed, 741 insertions(+), 116 deletions(-)
75
create mode 100644 hw/misc/tmp421.c
76
72
73
Richard Henderson (1):
74
tcg: Fix helper function vs host abi for float16
75
76
Shannon Zhao (3):
77
arm_gicv3_kvm: increase clroffset accordingly
78
ARM: ACPI: Fix use-after-free due to memory realloc
79
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
80
81
include/exec/exec-all.h | 5 +-
82
include/exec/helper-head.h | 2 +-
83
include/exec/memory-internal.h | 3 +-
84
include/exec/memory.h | 128 +++++++++++++++++++++++++++++++++++------
85
include/migration/vmstate.h | 3 +
86
include/sysemu/dma.h | 6 +-
87
accel/tcg/translate-all.c | 4 +-
88
exec.c | 95 ++++++++++++++++++------------
89
hw/arm/boot.c | 18 +++---
90
hw/arm/virt-acpi-build.c | 20 +++++--
91
hw/dma/xlnx-zdma.c | 10 +++-
92
hw/hppa/dino.c | 3 +-
93
hw/intc/arm_gic_kvm.c | 1 -
94
hw/intc/arm_gicv3_cpuif.c | 12 ++--
95
hw/intc/arm_gicv3_kvm.c | 2 +-
96
hw/nvram/fw_cfg.c | 12 ++--
97
hw/s390x/s390-pci-inst.c | 3 +-
98
hw/scsi/esp.c | 3 +-
99
hw/vfio/common.c | 3 +-
100
hw/virtio/vhost.c | 3 +-
101
hw/xen/xen_pt_msi.c | 3 +-
102
memory.c | 12 ++--
103
memory_ldst.inc.c | 18 +++---
104
target/arm/gdbstub.c | 3 +-
105
target/arm/helper-a64.c | 41 +++++++------
106
target/arm/helper.c | 90 ++++++++++++++++-------------
107
target/ppc/mmu-hash64.c | 3 +-
108
target/riscv/helper.c | 2 +-
109
target/s390x/diag.c | 6 +-
110
target/s390x/excp_helper.c | 3 +-
111
target/s390x/mmu_helper.c | 3 +-
112
target/s390x/sigp.c | 3 +-
113
target/xtensa/op_helper.c | 3 +-
114
MAINTAINERS | 9 ++-
115
34 files changed, 353 insertions(+), 182 deletions(-)
116
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX
1
The FRECPX instructions should (like most other floating point operations)
2
honour the FPCR.FZ bit which specifies whether input denormals should
3
be flushed to zero (or FZ16 for the half-precision version).
4
We forgot to implement this, which doesn't affect the results (since
5
the calculation doesn't actually care about the mantissa bits) but did
6
mean we were failing to set the FPSR.IDC bit.
1
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
11
---
12
target/arm/helper-a64.c | 6 ++++++
13
1 file changed, 6 insertions(+)
14
15
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-a64.c
18
+++ b/target/arm/helper-a64.c
19
@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
20
return nan;
21
}
22
23
+ a = float16_squash_input_denormal(a, fpst);
24
+
25
val16 = float16_val(a);
26
sbit = 0x8000 & val16;
27
exp = extract32(val16, 10, 5);
28
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
29
return nan;
30
}
31
32
+ a = float32_squash_input_denormal(a, fpst);
33
+
34
val32 = float32_val(a);
35
sbit = 0x80000000ULL & val32;
36
exp = extract32(val32, 23, 8);
37
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
38
return nan;
39
}
40
41
+ a = float64_squash_input_denormal(a, fpst);
42
+
43
val64 = float64_val(a);
44
sbit = 0x8000000000000000ULL & val64;
45
exp = extract64(float64_val(a), 52, 11);
46
--
47
2.17.1
48
49
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices
1
Add entries to MAINTAINERS to cover the newer MPS2 boards and
2
the new devices they use.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
6
---
7
MAINTAINERS | 9 +++++++--
8
1 file changed, 7 insertions(+), 2 deletions(-)
9
10
diff --git a/MAINTAINERS b/MAINTAINERS
11
index XXXXXXX..XXXXXXX 100644
12
--- a/MAINTAINERS
13
+++ b/MAINTAINERS
14
@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
15
F: include/hw/timer/cmsdk-apb-timer.h
16
F: hw/char/cmsdk-apb-uart.c
17
F: include/hw/char/cmsdk-apb-uart.h
18
+F: hw/misc/tz-ppc.c
19
+F: include/hw/misc/tz-ppc.h
20
21
ARM cores
22
M: Peter Maydell <peter.maydell@linaro.org>
23
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
24
L: qemu-arm@nongnu.org
25
S: Maintained
26
F: hw/arm/mps2.c
27
-F: hw/misc/mps2-scc.c
28
-F: include/hw/misc/mps2-scc.h
29
+F: hw/arm/mps2-tz.c
30
+F: hw/misc/mps2-*.c
31
+F: include/hw/misc/mps2-*.h
32
+F: hw/arm/iotkit.c
33
+F: include/hw/arm/iotkit.h
34
35
Musicpal
36
M: Jan Kiszka <jan.kiszka@web.de>
37
--
38
2.17.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable
[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Jan Kiszka <jan.kiszka@siemens.com>
2
2
3
There are to SysBusDevice variables in exynos4210_gic_realize()
3
There was a nasty flip in identifying which register group an access is
4
function: one for the device itself and second for arm_gic device. Add
4
targeting. The issue caused spuriously raised priorities of the guest
5
a prefix "gic" to the second one so it will be easier to understand the
5
when handing CPUs over in the Jailhouse hypervisor.
6
code.
7
6
8
While at it, put local uninitialized 'i' variable at the end, next to
7
Cc: qemu-stable@nongnu.org
9
other uninitialized ones.
8
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
10
9
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
11
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
hw/intc/exynos4210_gic.c | 12 ++++++------
13
hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
17
1 file changed, 6 insertions(+), 6 deletions(-)
14
1 file changed, 6 insertions(+), 6 deletions(-)
18
15
19
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
16
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/intc/exynos4210_gic.c
18
--- a/hw/intc/arm_gicv3_cpuif.c
22
+++ b/hw/intc/exynos4210_gic.c
19
+++ b/hw/intc/arm_gicv3_cpuif.c
23
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj)
20
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
24
DeviceState *dev = DEVICE(obj);
21
{
25
Exynos4210GicState *s = EXYNOS4210_GIC(obj);
22
GICv3CPUState *cs = icc_cs_from_env(env);
26
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
23
int regno = ri->opc2 & 3;
27
- uint32_t i;
24
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
28
const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
25
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
29
const char dist_prefix[] = "exynos4210-gic-alias_dist";
26
uint64_t value = cs->ich_apr[grp][regno];
30
char cpu_alias_name[sizeof(cpu_prefix) + 3];
27
31
char dist_alias_name[sizeof(cpu_prefix) + 3];
28
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
32
- SysBusDevice *busdev;
29
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
33
+ SysBusDevice *gicbusdev;
30
{
34
+ uint32_t i;
31
GICv3CPUState *cs = icc_cs_from_env(env);
35
32
int regno = ri->opc2 & 3;
36
s->gic = qdev_create(NULL, "arm_gic");
33
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
37
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
34
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
38
qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ);
35
39
qdev_init_nofail(s->gic);
36
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
40
- busdev = SYS_BUS_DEVICE(s->gic);
37
41
+ gicbusdev = SYS_BUS_DEVICE(s->gic);
38
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
42
39
uint64_t value;
43
/* Pass through outbound IRQ lines from the GIC */
40
44
- sysbus_pass_irq(sbd, busdev);
41
int regno = ri->opc2 & 3;
45
+ sysbus_pass_irq(sbd, gicbusdev);
42
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
46
43
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
47
/* Pass through inbound GPIO lines to the GIC */
44
48
qdev_init_gpio_in(dev, exynos4210_gic_set_irq,
45
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
49
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj)
46
return icv_ap_read(env, ri);
50
sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
47
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
51
memory_region_init_alias(&s->cpu_alias[i], obj,
48
GICv3CPUState *cs = icc_cs_from_env(env);
52
cpu_alias_name,
49
53
- sysbus_mmio_get_region(busdev, 1),
50
int regno = ri->opc2 & 3;
54
+ sysbus_mmio_get_region(gicbusdev, 1),
51
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
55
0,
52
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
56
EXYNOS4210_GIC_CPU_REGION_SIZE);
53
57
memory_region_add_subregion(&s->cpu_container,
54
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
58
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_init(Object *obj)
55
icv_ap_write(env, ri, value);
59
sprintf(dist_alias_name, "%s%x", dist_prefix, i);
56
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
60
memory_region_init_alias(&s->dist_alias[i], obj,
57
{
61
dist_alias_name,
58
GICv3CPUState *cs = icc_cs_from_env(env);
62
- sysbus_mmio_get_region(busdev, 0),
59
int regno = ri->opc2 & 3;
63
+ sysbus_mmio_get_region(gicbusdev, 0),
60
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
64
0,
61
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
65
EXYNOS4210_GIC_DIST_REGION_SIZE);
62
uint64_t value;
66
memory_region_add_subregion(&s->dist_container,
63
64
value = cs->ich_apr[grp][regno];
65
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
66
{
67
GICv3CPUState *cs = icc_cs_from_env(env);
68
int regno = ri->opc2 & 3;
69
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
70
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
71
72
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
73
67
--
74
--
68
2.7.4
75
2.17.1
69
76
70
77
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/17] hw/intc/arm_gicv3_kvm: Implement pending table save
[Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
2
2
3
This patch adds the flush of the LPI pending bits into the
3
It forgot to increase clroffset during the loop. So it only clear the
4
redistributor pending tables. This happens on VM stop.
4
first 4 bytes.
5
5
6
There is no explicit restore as the tables are implicitly sync'ed
6
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
7
on ITS table restore and on LPI enable at redistributor level.
7
Cc: qemu-stable@nongnu.org
8
8
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 1497023553-18411-4-git-send-email-eric.auger@redhat.com
10
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
13
---
14
hw/intc/arm_gicv3_kvm.c | 34 ++++++++++++++++++++++++++++++++++
14
hw/intc/arm_gicv3_kvm.c | 1 +
15
1 file changed, 34 insertions(+)
15
1 file changed, 1 insertion(+)
16
16
17
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
17
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/arm_gicv3_kvm.c
19
--- a/hw/intc/arm_gicv3_kvm.c
20
+++ b/hw/intc/arm_gicv3_kvm.c
20
+++ b/hw/intc/arm_gicv3_kvm.c
21
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
22
#include "hw/sysbus.h"
22
if (clroffset != 0) {
23
#include "qemu/error-report.h"
23
reg = 0;
24
#include "sysemu/kvm.h"
24
kvm_gicd_access(s, clroffset, &reg, true);
25
+#include "sysemu/sysemu.h"
25
+ clroffset += 4;
26
#include "kvm_arm.h"
27
#include "gicv3_internal.h"
28
#include "vgic_common.h"
29
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
30
REGINFO_SENTINEL
31
};
32
33
+/**
34
+ * vm_change_state_handler - VM change state callback aiming at flushing
35
+ * RDIST pending tables into guest RAM
36
+ *
37
+ * The tables get flushed to guest RAM whenever the VM gets stopped.
38
+ */
39
+static void vm_change_state_handler(void *opaque, int running,
40
+ RunState state)
41
+{
42
+ GICv3State *s = (GICv3State *)opaque;
43
+ Error *err = NULL;
44
+ int ret;
45
+
46
+ if (running) {
47
+ return;
48
+ }
49
+
50
+ ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
51
+ KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES,
52
+ NULL, true, &err);
53
+ if (err) {
54
+ error_report_err(err);
55
+ }
56
+ if (ret < 0 && ret != -EFAULT) {
57
+ abort();
58
+ }
59
+}
60
+
61
+
62
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
63
{
64
GICv3State *s = KVM_ARM_GICV3(dev);
65
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
66
return;
67
}
26
}
68
}
27
reg = *gic_bmp_ptr32(bmp, irq);
69
+ if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
28
kvm_gicd_access(s, offset, &reg, true);
70
+ KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) {
71
+ qemu_add_vm_change_state_handler(vm_change_state_handler, s);
72
+ }
73
}
74
75
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
76
--
29
--
77
2.7.4
30
2.17.1
78
31
79
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/17] hw/intc/exynos4210_gic: Constify array of combiner interrupts
[Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The static array of interrupt combiner mappings is not modified so it
3
Depending on the host abi, float16, aka uint16_t, values are
4
can be made const for code safeness.
4
passed and returned either zero-extended in the host register
5
5
or with garbage at the top of the host register.
6
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
6
7
The tcg code generator has so far been assuming garbage, as that
8
matches the x86 abi, but this is incorrect for other host abis.
9
Further, target/arm has so far been assuming zero-extended results,
10
so that it may store the 16-bit value into a 32-bit slot with the
11
high 16-bits already clear.
12
13
Rectify both problems by mapping "f16" in the helper definition
14
to uint32_t instead of (a typedef for) uint16_t. This forces
15
the host compiler to assume garbage in the upper 16 bits on input
16
and to zero-extend the result on output.
17
18
Cc: qemu-stable@nongnu.org
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
22
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
25
---
10
hw/intc/exynos4210_gic.c | 2 +-
26
include/exec/helper-head.h | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
27
target/arm/helper-a64.c | 35 +++++++++--------
12
28
target/arm/helper.c | 80 +++++++++++++++++++-------------------
13
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
29
3 files changed, 59 insertions(+), 58 deletions(-)
30
31
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
14
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/exynos4210_gic.c
33
--- a/include/exec/helper-head.h
16
+++ b/hw/intc/exynos4210_gic.c
34
+++ b/include/exec/helper-head.h
17
@@ -XXX,XX +XXX,XX @@ enum ExtInt {
35
@@ -XXX,XX +XXX,XX @@
18
* which is INTG16 in Internal Interrupt Combiner.
36
#define dh_ctype_int int
37
#define dh_ctype_i64 uint64_t
38
#define dh_ctype_s64 int64_t
39
-#define dh_ctype_f16 float16
40
+#define dh_ctype_f16 uint32_t
41
#define dh_ctype_f32 float32
42
#define dh_ctype_f64 float64
43
#define dh_ctype_ptr void *
44
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/helper-a64.c
47
+++ b/target/arm/helper-a64.c
48
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
49
return flags;
50
}
51
52
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
53
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
54
{
55
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
56
}
57
58
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
59
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
60
{
61
return float_rel_to_flags(float16_compare(x, y, fp_status));
62
}
63
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
64
#define float64_three make_float64(0x4008000000000000ULL)
65
#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
66
67
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
68
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
69
{
70
float_status *fpst = fpstp;
71
72
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
73
return float64_muladd(a, b, float64_two, 0, fpst);
74
}
75
76
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
77
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
78
{
79
float_status *fpst = fpstp;
80
81
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
82
}
83
84
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
85
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
86
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
87
{
88
float_status *fpst = fpstp;
89
uint16_t val16, sbit;
90
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
91
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
92
93
#define ADVSIMD_HALFOP(name) \
94
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
95
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
96
{ \
97
float_status *fpst = fpstp; \
98
return float16_ ## name(a, b, fpst); \
99
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
100
ADVSIMD_TWOHALFOP(mulx)
101
102
/* fused multiply-accumulate */
103
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
104
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
105
+ void *fpstp)
106
{
107
float_status *fpst = fpstp;
108
return float16_muladd(a, b, c, 0, fpst);
109
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
110
111
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
112
113
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
114
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
115
{
116
float_status *fpst = fpstp;
117
int compare = float16_compare_quiet(a, b, fpst);
118
return ADVSIMD_CMPRES(compare == float_relation_equal);
119
}
120
121
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
122
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
123
{
124
float_status *fpst = fpstp;
125
int compare = float16_compare(a, b, fpst);
126
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
127
compare == float_relation_equal);
128
}
129
130
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
131
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
132
{
133
float_status *fpst = fpstp;
134
int compare = float16_compare(a, b, fpst);
135
return ADVSIMD_CMPRES(compare == float_relation_greater);
136
}
137
138
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
139
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
140
{
141
float_status *fpst = fpstp;
142
float16 f0 = float16_abs(a);
143
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
144
compare == float_relation_equal);
145
}
146
147
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
148
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
149
{
150
float_status *fpst = fpstp;
151
float16 f0 = float16_abs(a);
152
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
153
}
154
155
/* round to integral */
156
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
157
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
158
{
159
return float16_round_to_int(x, fp_status);
160
}
161
162
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
163
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
164
{
165
int old_flags = get_float_exception_flags(fp_status), new_flags;
166
float16 ret;
167
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
168
* setting the mode appropriately before calling the helper.
19
*/
169
*/
20
170
21
-static uint32_t
171
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
22
+static const uint32_t
172
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
23
combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
173
{
24
/* int combiner groups 16-19 */
174
float_status *fpst = fpstp;
25
{ }, { }, { }, { },
175
176
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
177
return float16_to_int16(a, fpst);
178
}
179
180
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
181
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
182
{
183
float_status *fpst = fpstp;
184
185
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
186
* Square Root and Reciprocal square root
187
*/
188
189
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
190
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
191
{
192
float_status *s = fpstp;
193
194
diff --git a/target/arm/helper.c b/target/arm/helper.c
195
index XXXXXXX..XXXXXXX 100644
196
--- a/target/arm/helper.c
197
+++ b/target/arm/helper.c
198
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
199
200
/* Integer to float and float to integer conversions */
201
202
-#define CONV_ITOF(name, fsz, sign) \
203
- float##fsz HELPER(name)(uint32_t x, void *fpstp) \
204
-{ \
205
- float_status *fpst = fpstp; \
206
- return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
207
+#define CONV_ITOF(name, ftype, fsz, sign) \
208
+ftype HELPER(name)(uint32_t x, void *fpstp) \
209
+{ \
210
+ float_status *fpst = fpstp; \
211
+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
212
}
213
214
-#define CONV_FTOI(name, fsz, sign, round) \
215
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
216
-{ \
217
- float_status *fpst = fpstp; \
218
- if (float##fsz##_is_any_nan(x)) { \
219
- float_raise(float_flag_invalid, fpst); \
220
- return 0; \
221
- } \
222
- return float##fsz##_to_##sign##int32##round(x, fpst); \
223
+#define CONV_FTOI(name, ftype, fsz, sign, round) \
224
+uint32_t HELPER(name)(ftype x, void *fpstp) \
225
+{ \
226
+ float_status *fpst = fpstp; \
227
+ if (float##fsz##_is_any_nan(x)) { \
228
+ float_raise(float_flag_invalid, fpst); \
229
+ return 0; \
230
+ } \
231
+ return float##fsz##_to_##sign##int32##round(x, fpst); \
232
}
233
234
-#define FLOAT_CONVS(name, p, fsz, sign) \
235
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
236
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
237
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
238
+#define FLOAT_CONVS(name, p, ftype, fsz, sign) \
239
+ CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
240
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
241
+ CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
242
243
-FLOAT_CONVS(si, h, 16, )
244
-FLOAT_CONVS(si, s, 32, )
245
-FLOAT_CONVS(si, d, 64, )
246
-FLOAT_CONVS(ui, h, 16, u)
247
-FLOAT_CONVS(ui, s, 32, u)
248
-FLOAT_CONVS(ui, d, 64, u)
249
+FLOAT_CONVS(si, h, uint32_t, 16, )
250
+FLOAT_CONVS(si, s, float32, 32, )
251
+FLOAT_CONVS(si, d, float64, 64, )
252
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
253
+FLOAT_CONVS(ui, s, float32, 32, u)
254
+FLOAT_CONVS(ui, d, float64, 64, u)
255
256
#undef CONV_ITOF
257
#undef CONV_FTOI
258
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
259
return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
260
}
261
262
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
263
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
264
{
265
return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
266
}
267
268
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
269
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
270
{
271
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
272
}
273
274
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
275
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
276
{
277
return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
278
}
279
280
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
281
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
282
{
283
return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
284
}
285
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
286
}
287
}
288
289
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
290
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
291
{
292
return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
293
}
294
295
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
296
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
297
{
298
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
299
}
300
301
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
302
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
303
{
304
return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
305
}
306
307
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
308
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
309
{
310
return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
311
}
312
313
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
314
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
315
{
316
return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
317
}
318
319
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
320
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
321
{
322
return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
323
}
324
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
325
}
326
327
/* Half precision conversions. */
328
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
329
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
330
{
331
/* Squash FZ16 to 0 for the duration of conversion. In this case,
332
* it would affect flushing input denormals.
333
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
334
return r;
335
}
336
337
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
338
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
339
{
340
/* Squash FZ16 to 0 for the duration of conversion. In this case,
341
* it would affect flushing output denormals.
342
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
343
return r;
344
}
345
346
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
347
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
348
{
349
/* Squash FZ16 to 0 for the duration of conversion. In this case,
350
* it would affect flushing input denormals.
351
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
352
return r;
353
}
354
355
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
356
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
357
{
358
/* Squash FZ16 to 0 for the duration of conversion. In this case,
359
* it would affect flushing output denormals.
360
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
361
g_assert_not_reached();
362
}
363
364
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
365
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
366
{
367
float_status *fpst = fpstp;
368
float16 f16 = float16_squash_input_denormal(input, fpst);
369
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
370
return extract64(estimate, 0, 8) << 44;
371
}
372
373
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
374
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
375
{
376
float_status *s = fpstp;
377
float16 f16 = float16_squash_input_denormal(input, s);
26
--
378
--
27
2.7.4
379
2.17.1
28
380
29
381
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/17] hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string
[Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Igor Mammedov <imammedo@redhat.com>
2
2
3
Use a define for a9mpcore_priv device type name instead of hard-coded
3
When QEMU is started with following CLI
4
string.
4
-machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
5
it crashes with abort at
6
accel/kvm/kvm-all.c:2164:
7
KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
5
8
6
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
9
Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
arm_gicv3_icc_reset() where the later is called by CPU reset
11
reset callback.
12
13
However commit:
14
3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
15
broke CPU reset callback registration in case
16
17
arm_load_kernel()
18
...
19
if (!info->kernel_filename || info->firmware_loaded)
20
21
branch is taken, i.e. it's sufficient to provide a firmware
22
or do not provide kernel on CLI to skip cpu reset callback
23
registration, where before offending commit the callback
24
has been registered unconditionally.
25
26
Fix it by registering the callback right at the beginning of
27
arm_load_kernel() unconditionally instead of doing it at the end.
28
29
NOTE:
30
we probably should eliminate that dependency anyways as well as
31
separate arch CPU reset parts from arm_load_kernel() into CPU
32
itself, but that refactoring that I probably would have to do
33
anyways later for CPU hotplug to work.
34
35
Reported-by: Auger Eric <eric.auger@redhat.com>
36
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
37
Reviewed-by: Eric Auger <eric.auger@redhat.com>
38
Tested-by: Eric Auger <eric.auger@redhat.com>
39
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
42
---
10
hw/arm/exynos4210.c | 3 ++-
43
hw/arm/boot.c | 18 +++++++++---------
11
1 file changed, 2 insertions(+), 1 deletion(-)
44
1 file changed, 9 insertions(+), 9 deletions(-)
12
45
13
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
46
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
14
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4210.c
48
--- a/hw/arm/boot.c
16
+++ b/hw/arm/exynos4210.c
49
+++ b/hw/arm/boot.c
17
@@ -XXX,XX +XXX,XX @@
50
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
18
#include "qemu-common.h"
51
static const ARMInsnFixup *primary_loader;
19
#include "qemu/log.h"
52
AddressSpace *as = arm_boot_address_space(cpu, info);
20
#include "cpu.h"
53
21
+#include "hw/cpu/a9mpcore.h"
54
+ /* CPU objects (unlike devices) are not automatically reset on system
22
#include "hw/boards.h"
55
+ * reset, so we must always register a handler to do so. If we're
23
#include "sysemu/sysemu.h"
56
+ * actually loading a kernel, the handler is also responsible for
24
#include "hw/sysbus.h"
57
+ * arranging that we start it correctly.
25
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
58
+ */
59
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
60
+ qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
61
+ }
62
+
63
/* The board code is not supposed to set secure_board_setup unless
64
* running its code in secure mode is actually possible, and KVM
65
* doesn't support secure.
66
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
67
ARM_CPU(cs)->env.boot_info = info;
26
}
68
}
27
69
28
/* Private memory region and Internal GIC */
70
- /* CPU objects (unlike devices) are not automatically reset on system
29
- dev = qdev_create(NULL, "a9mpcore_priv");
71
- * reset, so we must always register a handler to do so. If we're
30
+ dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
72
- * actually loading a kernel, the handler is also responsible for
31
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
73
- * arranging that we start it correctly.
32
qdev_init_nofail(dev);
74
- */
33
busdev = SYS_BUS_DEVICE(dev);
75
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
76
- qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
77
- }
78
-
79
if (!info->skip_dtb_autoload && have_dtb(info)) {
80
if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
81
exit(1);
34
--
82
--
35
2.7.4
83
2.17.1
36
84
37
85
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/17] hw/timer/exynos4210_mct: Fix checkpatch style errors
[Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Paolo Bonzini <pbonzini@redhat.com>
2
2
3
Fix checkpatch errors:
3
cpregs_keys is an uint32_t* so the allocation should use uint32_t.
4
1. ERROR: spaces required around that '+' (ctx:VxV)
4
g_new is even better because it is type-safe.
5
2. ERROR: spaces required around that '&' (ctx:VxV)
6
5
7
No functional changes.
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
8
9
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/timer/exynos4210_mct.c | 4 ++--
11
target/arm/gdbstub.c | 3 +--
15
1 file changed, 2 insertions(+), 2 deletions(-)
12
1 file changed, 1 insertion(+), 2 deletions(-)
16
13
17
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
14
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/timer/exynos4210_mct.c
16
--- a/target/arm/gdbstub.c
20
+++ b/hw/timer/exynos4210_mct.c
17
+++ b/target/arm/gdbstub.c
21
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
18
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
22
{
19
RegisterSysregXmlParam param = {cs, s};
23
uint32_t freq = s->freq;
20
24
s->freq = 24000000 /
21
cpu->dyn_xml.num_cpregs = 0;
25
- ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) *
22
- cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
26
+ ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg) + 1) *
23
- g_hash_table_size(cpu->cp_regs));
27
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
24
+ cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
28
25
g_string_printf(s, "<?xml version=\"1.0\"?>");
29
if (freq != s->freq) {
26
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
30
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
27
g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
31
32
DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
33
34
- if (offset&0x4) {
35
+ if (offset & 0x4) {
36
s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
37
} else {
38
s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
39
--
28
--
40
2.7.4
29
2.17.1
41
30
42
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/17] hw/timer/exynos4210_mct: Remove unused defines
[Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Francisco Iglesias <frasse.iglesias@gmail.com>
2
2
3
Remove defines not used anywhere.
3
Coverity found that the string return by 'object_get_canonical_path' was not
4
being freed at two locations in the model (CID 1391294 and CID 1391293) and
5
also that a memset was being called with a value greater than the max of a byte
6
on the second argument (CID 1391286). This patch corrects this by adding the
7
freeing of the strings and also changing to memset to zero instead on
8
descriptor unaligned errors.
4
9
5
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
10
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
16
---
9
hw/timer/exynos4210_mct.c | 3 ---
17
hw/dma/xlnx-zdma.c | 10 +++++++---
10
1 file changed, 3 deletions(-)
18
1 file changed, 7 insertions(+), 3 deletions(-)
11
19
12
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
20
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
13
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/timer/exynos4210_mct.c
22
--- a/hw/dma/xlnx-zdma.c
15
+++ b/hw/timer/exynos4210_mct.c
23
+++ b/hw/dma/xlnx-zdma.c
16
@@ -XXX,XX +XXX,XX @@ enum LocalTimerRegCntIndexes {
24
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
17
L_REG_CNT_AMOUNT
25
qemu_log_mask(LOG_GUEST_ERROR,
18
};
26
"zdma: unaligned descriptor at %" PRIx64,
19
27
addr);
20
-#define MCT_NIRQ 6
28
- memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
21
#define MCT_SFR_SIZE 0x444
29
+ memset(buf, 0x0, sizeof(XlnxZDMADescr));
22
30
s->error = true;
23
#define MCT_GT_CMP_NUM 4
31
return false;
24
32
}
25
-#define MCT_GT_MAX_VAL UINT64_MAX
33
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
26
-
34
RegisterInfo *r = &s->regs_info[addr / 4];
27
#define MCT_GT_COUNTER_STEP 0x100000000ULL
35
28
#define MCT_LT_COUNTER_STEP 0x100000000ULL
36
if (!r->data) {
29
#define MCT_LT_CNT_LOW_LIMIT 0x100
37
+ gchar *path = object_get_canonical_path(OBJECT(s));
38
qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
39
- object_get_canonical_path(OBJECT(s)),
40
+ path,
41
addr);
42
+ g_free(path);
43
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
44
zdma_ch_imr_update_irq(s);
45
return 0;
46
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
47
RegisterInfo *r = &s->regs_info[addr / 4];
48
49
if (!r->data) {
50
+ gchar *path = object_get_canonical_path(OBJECT(s));
51
qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
52
- object_get_canonical_path(OBJECT(s)),
53
+ path,
54
addr, value);
55
+ g_free(path);
56
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
57
zdma_ch_imr_update_irq(s);
58
return;
30
--
59
--
31
2.7.4
60
2.17.1
32
61
33
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/17] hw/arm/exynos: Move DRAM initialization next boards
[Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
In commit f0aff255700 we made cpacr_write() enforce that some CPACR
2
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
3
we forgot to also update the register's reset value. The effect
4
was that (a) a guest that read CPACR on reset would not see ones in
5
the RAO bits, and (b) if you did a migration before the guest did
6
a write to the CPACR then the migration would fail because the
7
destination would enforce the RAO bits and then complain that they
8
didn't match the zero value from the source.
2
9
3
Before QOM-ifying the Exynos4 SoC model, move the DRAM initialization
10
Implement reset for the CPACR using a custom reset function
4
from exynos4210.c to exynos4_boards.c because DRAM is board specific,
11
that just calls cpacr_write(), to avoid having to duplicate
5
not SoC.
12
the logic for which bits are RAO.
6
13
7
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
14
This bug would affect migration for TCG CPUs which are ARMv7
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
with VFP but without one of Neon or VFPv3.
16
17
Reported-by: Cédric Le Goater <clg@kaod.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Tested-by: Cédric Le Goater <clg@kaod.org>
20
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
10
---
21
---
11
include/hw/arm/exynos4210.h | 5 +----
22
target/arm/helper.c | 10 +++++++++-
12
hw/arm/exynos4210.c | 20 +-----------------
23
1 file changed, 9 insertions(+), 1 deletion(-)
13
hw/arm/exynos4_boards.c | 50 ++++++++++++++++++++++++++++++++++++++-------
14
3 files changed, 45 insertions(+), 30 deletions(-)
15
24
16
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
25
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/exynos4210.h
27
--- a/target/arm/helper.c
19
+++ b/include/hw/arm/exynos4210.h
28
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
29
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
21
MemoryRegion iram_mem;
30
env->cp15.cpacr_el1 = value;
22
MemoryRegion irom_mem;
23
MemoryRegion irom_alias_mem;
24
- MemoryRegion dram0_mem;
25
- MemoryRegion dram1_mem;
26
MemoryRegion boot_secondary;
27
MemoryRegion bootreg_mem;
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
29
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
30
void exynos4210_write_secondary(ARMCPU *cpu,
31
const struct arm_boot_info *info);
32
33
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
34
- unsigned long ram_size);
35
+Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
36
37
/* Initialize exynos4210 IRQ subsystem stub */
38
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
39
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/exynos4210.c
42
+++ b/hw/arm/exynos4210.c
43
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
44
return mp_affinity;
45
}
31
}
46
32
47
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
33
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
48
- unsigned long ram_size)
49
+Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
50
{
51
int i, n;
52
Exynos4210State *s = g_new(Exynos4210State, 1);
53
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
54
- unsigned long mem_size;
55
DeviceState *dev;
56
SysBusDevice *busdev;
57
ObjectClass *cpu_oc;
58
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
59
memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
60
&s->iram_mem);
61
62
- /* DRAM */
63
- mem_size = ram_size;
64
- if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
65
- memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
66
- mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
67
- vmstate_register_ram_global(&s->dram1_mem);
68
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
69
- &s->dram1_mem);
70
- mem_size = EXYNOS4210_DRAM_MAX_SIZE;
71
- }
72
- memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
73
- &error_fatal);
74
- vmstate_register_ram_global(&s->dram0_mem);
75
- memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
76
- &s->dram0_mem);
77
-
78
/* PMU.
79
* The only reason of existence at the moment is that secondary CPU boot
80
* loader uses PMU INFORM5 register as a holding pen.
81
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/hw/arm/exynos4_boards.c
84
+++ b/hw/arm/exynos4_boards.c
85
@@ -XXX,XX +XXX,XX @@
86
*/
87
88
#include "qemu/osdep.h"
89
+#include "qapi/error.h"
90
#include "qemu/error-report.h"
91
#include "qemu-common.h"
92
#include "cpu.h"
93
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
94
EXYNOS4_NUM_OF_BOARDS
95
} Exynos4BoardType;
96
97
+typedef struct Exynos4BoardState {
98
+ Exynos4210State *soc;
99
+ MemoryRegion dram0_mem;
100
+ MemoryRegion dram1_mem;
101
+} Exynos4BoardState;
102
+
103
static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
104
[EXYNOS4_BOARD_NURI] = 0xD33,
105
[EXYNOS4_BOARD_SMDKC210] = 0xB16,
106
@@ -XXX,XX +XXX,XX @@ static void lan9215_init(uint32_t base, qemu_irq irq)
107
}
108
}
109
110
-static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
111
- Exynos4BoardType board_type)
112
+static void exynos4_boards_init_ram(Exynos4BoardState *s,
113
+ MemoryRegion *system_mem,
114
+ unsigned long ram_size)
115
+{
34
+{
116
+ unsigned long mem_size = ram_size;
35
+ /* Call cpacr_write() so that we reset with the correct RAO bits set
117
+
36
+ * for our CPU features.
118
+ if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
37
+ */
119
+ memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
38
+ cpacr_write(env, ri, 0);
120
+ mem_size - EXYNOS4210_DRAM_MAX_SIZE,
121
+ &error_fatal);
122
+ vmstate_register_ram_global(&s->dram1_mem);
123
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
124
+ &s->dram1_mem);
125
+ mem_size = EXYNOS4210_DRAM_MAX_SIZE;
126
+ }
127
+
128
+ memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
129
+ &error_fatal);
130
+ vmstate_register_ram_global(&s->dram0_mem);
131
+ memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
132
+ &s->dram0_mem);
133
+}
39
+}
134
+
40
+
135
+static Exynos4BoardState *
41
static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
136
+exynos4_boards_init_common(MachineState *machine,
42
bool isread)
137
+ Exynos4BoardType board_type)
138
{
43
{
139
+ Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
140
MachineClass *mc = MACHINE_GET_CLASS(machine);
45
{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
141
46
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
142
if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
47
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
143
@@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
48
- .resetvalue = 0, .writefn = cpacr_write },
144
machine->kernel_cmdline,
49
+ .resetfn = cpacr_reset, .writefn = cpacr_write },
145
machine->initrd_filename);
50
REGINFO_SENTINEL
146
51
};
147
- return exynos4210_init(get_system_memory(),
148
- exynos4_board_ram_size[board_type]);
149
+ exynos4_boards_init_ram(s, get_system_memory(),
150
+ exynos4_board_ram_size[board_type]);
151
+
152
+ s->soc = exynos4210_init(get_system_memory());
153
+
154
+ return s;
155
}
156
157
static void nuri_init(MachineState *machine)
158
@@ -XXX,XX +XXX,XX @@ static void nuri_init(MachineState *machine)
159
160
static void smdkc210_init(MachineState *machine)
161
{
162
- Exynos4210State *s = exynos4_boards_init_common(machine,
163
- EXYNOS4_BOARD_SMDKC210);
164
+ Exynos4BoardState *s = exynos4_boards_init_common(machine,
165
+ EXYNOS4_BOARD_SMDKC210);
166
167
lan9215_init(SMDK_LAN9118_BASE_ADDR,
168
- qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)]));
169
+ qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
170
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
171
}
172
52
173
--
53
--
174
2.7.4
54
2.17.1
175
55
176
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/17] hw/misc: add a TMP42{1, 2, 3} device model
[Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation
1
From: Cédric Le Goater <clg@kaod.org>
1
Add more detail to the documentation for memory_region_init_iommu()
2
and other IOMMU-related functions and data structures.
2
3
3
Largely inspired by the TMP105 temperature sensor, here is a model for
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
the TMP42{1,2,3} temperature sensors.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
9
---
10
include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
11
1 file changed, 95 insertions(+), 10 deletions(-)
5
12
6
Specs can be found here :
13
diff --git a/include/exec/memory.h b/include/exec/memory.h
7
8
    http://www.ti.com/lit/gpn/tmp421
9
10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
11
Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/misc/Makefile.objs | 1 +
16
hw/misc/tmp421.c | 402 ++++++++++++++++++++++++++++++++++++++++
17
default-configs/arm-softmmu.mak | 1 +
18
3 files changed, 404 insertions(+)
19
create mode 100644 hw/misc/tmp421.c
20
21
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
22
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/misc/Makefile.objs
15
--- a/include/exec/memory.h
24
+++ b/hw/misc/Makefile.objs
16
+++ b/include/exec/memory.h
25
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
26
common-obj-$(CONFIG_APPLESMC) += applesmc.o
18
IOMMU_ATTR_SPAPR_TCE_FD
27
common-obj-$(CONFIG_MAX111X) += max111x.o
19
};
28
common-obj-$(CONFIG_TMP105) += tmp105.o
20
29
+common-obj-$(CONFIG_TMP421) += tmp421.o
21
+/**
30
common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o
22
+ * IOMMUMemoryRegionClass:
31
common-obj-$(CONFIG_SGA) += sga.o
32
common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
33
diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c
34
new file mode 100644
35
index XXXXXXX..XXXXXXX
36
--- /dev/null
37
+++ b/hw/misc/tmp421.c
38
@@ -XXX,XX +XXX,XX @@
39
+/*
40
+ * Texas Instruments TMP421 temperature sensor.
41
+ *
23
+ *
42
+ * Copyright (c) 2016 IBM Corporation.
24
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
25
+ * and provide an implementation of at least the @translate method here
26
+ * to handle requests to the memory region. Other methods are optional.
43
+ *
27
+ *
44
+ * Largely inspired by :
28
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
29
+ * to report whenever mappings are changed, by calling
30
+ * memory_region_notify_iommu() (or, if necessary, by calling
31
+ * memory_region_notify_one() for each registered notifier).
32
+ */
33
typedef struct IOMMUMemoryRegionClass {
34
/* private */
35
struct DeviceClass parent_class;
36
37
/*
38
- * Return a TLB entry that contains a given address. Flag should
39
- * be the access permission of this translation operation. We can
40
- * set flag to IOMMU_NONE to mean that we don't need any
41
- * read/write permission checks, like, when for region replay.
42
+ * Return a TLB entry that contains a given address.
43
+ *
44
+ * The IOMMUAccessFlags indicated via @flag are optional and may
45
+ * be specified as IOMMU_NONE to indicate that the caller needs
46
+ * the full translation information for both reads and writes. If
47
+ * the access flags are specified then the IOMMU implementation
48
+ * may use this as an optimization, to stop doing a page table
49
+ * walk as soon as it knows that the requested permissions are not
50
+ * allowed. If IOMMU_NONE is passed then the IOMMU must do the
51
+ * full page table walk and report the permissions in the returned
52
+ * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
53
+ * return different mappings for reads and writes.)
54
+ *
55
+ * The returned information remains valid while the caller is
56
+ * holding the big QEMU lock or is inside an RCU critical section;
57
+ * if the caller wishes to cache the mapping beyond that it must
58
+ * register an IOMMU notifier so it can invalidate its cached
59
+ * information when the IOMMU mapping changes.
60
+ *
61
+ * @iommu: the IOMMUMemoryRegion
62
+ * @hwaddr: address to be translated within the memory region
63
+ * @flag: requested access permissions
64
*/
65
IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
66
IOMMUAccessFlags flag);
67
- /* Returns minimum supported page size */
68
+ /* Returns minimum supported page size in bytes.
69
+ * If this method is not provided then the minimum is assumed to
70
+ * be TARGET_PAGE_SIZE.
71
+ *
72
+ * @iommu: the IOMMUMemoryRegion
73
+ */
74
uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
75
- /* Called when IOMMU Notifier flag changed */
76
+ /* Called when IOMMU Notifier flag changes (ie when the set of
77
+ * events which IOMMU users are requesting notification for changes).
78
+ * Optional method -- need not be provided if the IOMMU does not
79
+ * need to know exactly which events must be notified.
80
+ *
81
+ * @iommu: the IOMMUMemoryRegion
82
+ * @old_flags: events which previously needed to be notified
83
+ * @new_flags: events which now need to be notified
84
+ */
85
void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
86
IOMMUNotifierFlag old_flags,
87
IOMMUNotifierFlag new_flags);
88
- /* Set this up to provide customized IOMMU replay function */
89
+ /* Called to handle memory_region_iommu_replay().
90
+ *
91
+ * The default implementation of memory_region_iommu_replay() is to
92
+ * call the IOMMU translate method for every page in the address space
93
+ * with flag == IOMMU_NONE and then call the notifier if translate
94
+ * returns a valid mapping. If this method is implemented then it
95
+ * overrides the default behaviour, and must provide the full semantics
96
+ * of memory_region_iommu_replay(), by calling @notifier for every
97
+ * translation present in the IOMMU.
98
+ *
99
+ * Optional method -- an IOMMU only needs to provide this method
100
+ * if the default is inefficient or produces undesirable side effects.
101
+ *
102
+ * Note: this is not related to record-and-replay functionality.
103
+ */
104
void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
105
106
- /* Get IOMMU misc attributes */
107
- int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
108
+ /* Get IOMMU misc attributes. This is an optional method that
109
+ * can be used to allow users of the IOMMU to get implementation-specific
110
+ * information. The IOMMU implements this method to handle calls
111
+ * by IOMMU users to memory_region_iommu_get_attr() by filling in
112
+ * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
113
+ * the IOMMU supports. If the method is unimplemented then
114
+ * memory_region_iommu_get_attr() will always return -EINVAL.
115
+ *
116
+ * @iommu: the IOMMUMemoryRegion
117
+ * @attr: attribute being queried
118
+ * @data: memory to fill in with the attribute data
119
+ *
120
+ * Returns 0 on success, or a negative errno; in particular
121
+ * returns -EINVAL for unrecognized or unimplemented attribute types.
122
+ */
123
+ int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
124
void *data);
125
} IOMMUMemoryRegionClass;
126
127
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
128
* An IOMMU region translates addresses and forwards accesses to a target
129
* memory region.
130
*
131
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
132
+ * @_iommu_mr should be a pointer to enough memory for an instance of
133
+ * that subclass, @instance_size is the size of that subclass, and
134
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
135
+ * instance of the subclass, and its methods will then be called to handle
136
+ * accesses to the memory region. See the documentation of
137
+ * #IOMMUMemoryRegionClass for further details.
45
+ *
138
+ *
46
+ * Texas Instruments TMP105 temperature sensor.
139
* @_iommu_mr: the #IOMMUMemoryRegion to be initialized
140
* @instance_size: the IOMMUMemoryRegion subclass instance size
141
* @mrtypename: the type name of the #IOMMUMemoryRegion
142
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
143
* a notifier with the minimum page granularity returned by
144
* mr->iommu_ops->get_page_size().
145
*
146
+ * Note: this is not related to record-and-replay functionality.
47
+ *
147
+ *
48
+ * Copyright (C) 2008 Nokia Corporation
148
* @iommu_mr: the memory region to observe
49
+ * Written by Andrzej Zaborowski <andrew@openedhand.com>
149
* @n: the notifier to which to replay iommu mappings
150
*/
151
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
152
* memory_region_iommu_replay_all: replay existing IOMMU translations
153
* to all the notifiers registered.
154
*
155
+ * Note: this is not related to record-and-replay functionality.
50
+ *
156
+ *
51
+ * This program is free software; you can redistribute it and/or
157
* @iommu_mr: the memory region to observe
52
+ * modify it under the terms of the GNU General Public License as
158
*/
53
+ * published by the Free Software Foundation; either version 2 or
159
void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
54
+ * (at your option) version 3 of the License.
160
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
55
+ *
161
* memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
56
+ * This program is distributed in the hope that it will be useful,
162
* defined on the IOMMU.
57
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
163
*
58
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
164
- * Returns 0 if succeded, error code otherwise.
59
+ * GNU General Public License for more details.
165
+ * Returns 0 on success, or a negative errno otherwise. In particular,
60
+ *
166
+ * -EINVAL indicates that the IOMMU does not support the requested
61
+ * You should have received a copy of the GNU General Public License along
167
+ * attribute.
62
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
168
*
63
+ */
169
* @iommu_mr: the memory region
64
+
170
* @attr: the requested attribute
65
+#include "qemu/osdep.h"
66
+#include "hw/hw.h"
67
+#include "hw/i2c/i2c.h"
68
+#include "qapi/error.h"
69
+#include "qapi/visitor.h"
70
+
71
+/* Manufacturer / Device ID's */
72
+#define TMP421_MANUFACTURER_ID 0x55
73
+#define TMP421_DEVICE_ID 0x21
74
+#define TMP422_DEVICE_ID 0x22
75
+#define TMP423_DEVICE_ID 0x23
76
+
77
+typedef struct DeviceInfo {
78
+ int model;
79
+ const char *name;
80
+} DeviceInfo;
81
+
82
+static const DeviceInfo devices[] = {
83
+ { TMP421_DEVICE_ID, "tmp421" },
84
+ { TMP422_DEVICE_ID, "tmp422" },
85
+ { TMP423_DEVICE_ID, "tmp423" },
86
+};
87
+
88
+typedef struct TMP421State {
89
+ /*< private >*/
90
+ I2CSlave i2c;
91
+ /*< public >*/
92
+
93
+ int16_t temperature[4];
94
+
95
+ uint8_t status;
96
+ uint8_t config[2];
97
+ uint8_t rate;
98
+
99
+ uint8_t len;
100
+ uint8_t buf[2];
101
+ uint8_t pointer;
102
+
103
+} TMP421State;
104
+
105
+typedef struct TMP421Class {
106
+ I2CSlaveClass parent_class;
107
+ DeviceInfo *dev;
108
+} TMP421Class;
109
+
110
+#define TYPE_TMP421 "tmp421-generic"
111
+#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421)
112
+
113
+#define TMP421_CLASS(klass) \
114
+ OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421)
115
+#define TMP421_GET_CLASS(obj) \
116
+ OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421)
117
+
118
+/* the TMP421 registers */
119
+#define TMP421_STATUS_REG 0x08
120
+#define TMP421_STATUS_BUSY (1 << 7)
121
+#define TMP421_CONFIG_REG_1 0x09
122
+#define TMP421_CONFIG_RANGE (1 << 2)
123
+#define TMP421_CONFIG_SHUTDOWN (1 << 6)
124
+#define TMP421_CONFIG_REG_2 0x0A
125
+#define TMP421_CONFIG_RC (1 << 2)
126
+#define TMP421_CONFIG_LEN (1 << 3)
127
+#define TMP421_CONFIG_REN (1 << 4)
128
+#define TMP421_CONFIG_REN2 (1 << 5)
129
+#define TMP421_CONFIG_REN3 (1 << 6)
130
+
131
+#define TMP421_CONVERSION_RATE_REG 0x0B
132
+#define TMP421_ONE_SHOT 0x0F
133
+
134
+#define TMP421_RESET 0xFC
135
+#define TMP421_MANUFACTURER_ID_REG 0xFE
136
+#define TMP421_DEVICE_ID_REG 0xFF
137
+
138
+#define TMP421_TEMP_MSB0 0x00
139
+#define TMP421_TEMP_MSB1 0x01
140
+#define TMP421_TEMP_MSB2 0x02
141
+#define TMP421_TEMP_MSB3 0x03
142
+#define TMP421_TEMP_LSB0 0x10
143
+#define TMP421_TEMP_LSB1 0x11
144
+#define TMP421_TEMP_LSB2 0x12
145
+#define TMP421_TEMP_LSB3 0x13
146
+
147
+static const int32_t mins[2] = { -40000, -55000 };
148
+static const int32_t maxs[2] = { 127000, 150000 };
149
+
150
+static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name,
151
+ void *opaque, Error **errp)
152
+{
153
+ TMP421State *s = TMP421(obj);
154
+ bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
155
+ int offset = ext_range * 64 * 256;
156
+ int64_t value;
157
+ int tempid;
158
+
159
+ if (sscanf(name, "temperature%d", &tempid) != 1) {
160
+ error_setg(errp, "error reading %s: %m", name);
161
+ return;
162
+ }
163
+
164
+ if (tempid >= 4 || tempid < 0) {
165
+ error_setg(errp, "error reading %s", name);
166
+ return;
167
+ }
168
+
169
+ value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256;
170
+
171
+ visit_type_int(v, name, &value, errp);
172
+}
173
+
174
+/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8
175
+ * fixed point, so units are 1/256 centigrades. A simple ratio will do.
176
+ */
177
+static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name,
178
+ void *opaque, Error **errp)
179
+{
180
+ TMP421State *s = TMP421(obj);
181
+ Error *local_err = NULL;
182
+ int64_t temp;
183
+ bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
184
+ int offset = ext_range * 64 * 256;
185
+ int tempid;
186
+
187
+ visit_type_int(v, name, &temp, &local_err);
188
+ if (local_err) {
189
+ error_propagate(errp, local_err);
190
+ return;
191
+ }
192
+
193
+ if (temp >= maxs[ext_range] || temp < mins[ext_range]) {
194
+ error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range",
195
+ temp / 1000, temp % 1000);
196
+ return;
197
+ }
198
+
199
+ if (sscanf(name, "temperature%d", &tempid) != 1) {
200
+ error_setg(errp, "error reading %s: %m", name);
201
+ return;
202
+ }
203
+
204
+ if (tempid >= 4 || tempid < 0) {
205
+ error_setg(errp, "error reading %s", name);
206
+ return;
207
+ }
208
+
209
+ s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset;
210
+}
211
+
212
+static void tmp421_read(TMP421State *s)
213
+{
214
+ TMP421Class *sc = TMP421_GET_CLASS(s);
215
+
216
+ s->len = 0;
217
+
218
+ switch (s->pointer) {
219
+ case TMP421_MANUFACTURER_ID_REG:
220
+ s->buf[s->len++] = TMP421_MANUFACTURER_ID;
221
+ break;
222
+ case TMP421_DEVICE_ID_REG:
223
+ s->buf[s->len++] = sc->dev->model;
224
+ break;
225
+ case TMP421_CONFIG_REG_1:
226
+ s->buf[s->len++] = s->config[0];
227
+ break;
228
+ case TMP421_CONFIG_REG_2:
229
+ s->buf[s->len++] = s->config[1];
230
+ break;
231
+ case TMP421_CONVERSION_RATE_REG:
232
+ s->buf[s->len++] = s->rate;
233
+ break;
234
+ case TMP421_STATUS_REG:
235
+ s->buf[s->len++] = s->status;
236
+ break;
237
+
238
+ /* FIXME: check for channel enablement in config registers */
239
+ case TMP421_TEMP_MSB0:
240
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8);
241
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
242
+ break;
243
+ case TMP421_TEMP_MSB1:
244
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8);
245
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
246
+ break;
247
+ case TMP421_TEMP_MSB2:
248
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8);
249
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
250
+ break;
251
+ case TMP421_TEMP_MSB3:
252
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8);
253
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
254
+ break;
255
+ case TMP421_TEMP_LSB0:
256
+ s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
257
+ break;
258
+ case TMP421_TEMP_LSB1:
259
+ s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
260
+ break;
261
+ case TMP421_TEMP_LSB2:
262
+ s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
263
+ break;
264
+ case TMP421_TEMP_LSB3:
265
+ s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
266
+ break;
267
+ }
268
+}
269
+
270
+static void tmp421_reset(I2CSlave *i2c);
271
+
272
+static void tmp421_write(TMP421State *s)
273
+{
274
+ switch (s->pointer) {
275
+ case TMP421_CONVERSION_RATE_REG:
276
+ s->rate = s->buf[0];
277
+ break;
278
+ case TMP421_CONFIG_REG_1:
279
+ s->config[0] = s->buf[0];
280
+ break;
281
+ case TMP421_CONFIG_REG_2:
282
+ s->config[1] = s->buf[0];
283
+ break;
284
+ case TMP421_RESET:
285
+ tmp421_reset(I2C_SLAVE(s));
286
+ break;
287
+ }
288
+}
289
+
290
+static int tmp421_rx(I2CSlave *i2c)
291
+{
292
+ TMP421State *s = TMP421(i2c);
293
+
294
+ if (s->len < 2) {
295
+ return s->buf[s->len++];
296
+ } else {
297
+ return 0xff;
298
+ }
299
+}
300
+
301
+static int tmp421_tx(I2CSlave *i2c, uint8_t data)
302
+{
303
+ TMP421State *s = TMP421(i2c);
304
+
305
+ if (s->len == 0) {
306
+ /* first byte is the register pointer for a read or write
307
+ * operation */
308
+ s->pointer = data;
309
+ s->len++;
310
+ } else if (s->len == 1) {
311
+ /* second byte is the data to write. The device only supports
312
+ * one byte writes */
313
+ s->buf[0] = data;
314
+ tmp421_write(s);
315
+ }
316
+
317
+ return 0;
318
+}
319
+
320
+static int tmp421_event(I2CSlave *i2c, enum i2c_event event)
321
+{
322
+ TMP421State *s = TMP421(i2c);
323
+
324
+ if (event == I2C_START_RECV) {
325
+ tmp421_read(s);
326
+ }
327
+
328
+ s->len = 0;
329
+ return 0;
330
+}
331
+
332
+static const VMStateDescription vmstate_tmp421 = {
333
+ .name = "TMP421",
334
+ .version_id = 0,
335
+ .minimum_version_id = 0,
336
+ .fields = (VMStateField[]) {
337
+ VMSTATE_UINT8(len, TMP421State),
338
+ VMSTATE_UINT8_ARRAY(buf, TMP421State, 2),
339
+ VMSTATE_UINT8(pointer, TMP421State),
340
+ VMSTATE_UINT8_ARRAY(config, TMP421State, 2),
341
+ VMSTATE_UINT8(status, TMP421State),
342
+ VMSTATE_UINT8(rate, TMP421State),
343
+ VMSTATE_INT16_ARRAY(temperature, TMP421State, 4),
344
+ VMSTATE_I2C_SLAVE(i2c, TMP421State),
345
+ VMSTATE_END_OF_LIST()
346
+ }
347
+};
348
+
349
+static void tmp421_reset(I2CSlave *i2c)
350
+{
351
+ TMP421State *s = TMP421(i2c);
352
+ TMP421Class *sc = TMP421_GET_CLASS(s);
353
+
354
+ memset(s->temperature, 0, sizeof(s->temperature));
355
+ s->pointer = 0;
356
+
357
+ s->config[0] = 0; /* TMP421_CONFIG_RANGE */
358
+
359
+ /* resistance correction and channel enablement */
360
+ switch (sc->dev->model) {
361
+ case TMP421_DEVICE_ID:
362
+ s->config[1] = 0x1c;
363
+ break;
364
+ case TMP422_DEVICE_ID:
365
+ s->config[1] = 0x3c;
366
+ break;
367
+ case TMP423_DEVICE_ID:
368
+ s->config[1] = 0x7c;
369
+ break;
370
+ }
371
+
372
+ s->rate = 0x7; /* 8Hz */
373
+ s->status = 0;
374
+}
375
+
376
+static int tmp421_init(I2CSlave *i2c)
377
+{
378
+ TMP421State *s = TMP421(i2c);
379
+
380
+ tmp421_reset(&s->i2c);
381
+
382
+ return 0;
383
+}
384
+
385
+static void tmp421_initfn(Object *obj)
386
+{
387
+ object_property_add(obj, "temperature0", "int",
388
+ tmp421_get_temperature,
389
+ tmp421_set_temperature, NULL, NULL, NULL);
390
+ object_property_add(obj, "temperature1", "int",
391
+ tmp421_get_temperature,
392
+ tmp421_set_temperature, NULL, NULL, NULL);
393
+ object_property_add(obj, "temperature2", "int",
394
+ tmp421_get_temperature,
395
+ tmp421_set_temperature, NULL, NULL, NULL);
396
+ object_property_add(obj, "temperature3", "int",
397
+ tmp421_get_temperature,
398
+ tmp421_set_temperature, NULL, NULL, NULL);
399
+}
400
+
401
+static void tmp421_class_init(ObjectClass *klass, void *data)
402
+{
403
+ DeviceClass *dc = DEVICE_CLASS(klass);
404
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
405
+ TMP421Class *sc = TMP421_CLASS(klass);
406
+
407
+ k->init = tmp421_init;
408
+ k->event = tmp421_event;
409
+ k->recv = tmp421_rx;
410
+ k->send = tmp421_tx;
411
+ dc->vmsd = &vmstate_tmp421;
412
+ sc->dev = (DeviceInfo *) data;
413
+}
414
+
415
+static const TypeInfo tmp421_info = {
416
+ .name = TYPE_TMP421,
417
+ .parent = TYPE_I2C_SLAVE,
418
+ .instance_size = sizeof(TMP421State),
419
+ .class_size = sizeof(TMP421Class),
420
+ .instance_init = tmp421_initfn,
421
+ .abstract = true,
422
+};
423
+
424
+static void tmp421_register_types(void)
425
+{
426
+ int i;
427
+
428
+ type_register_static(&tmp421_info);
429
+ for (i = 0; i < ARRAY_SIZE(devices); ++i) {
430
+ TypeInfo ti = {
431
+ .name = devices[i].name,
432
+ .parent = TYPE_TMP421,
433
+ .class_init = tmp421_class_init,
434
+ .class_data = (void *) &devices[i],
435
+ };
436
+ type_register(&ti);
437
+ }
438
+}
439
+
440
+type_init(tmp421_register_types)
441
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
442
index XXXXXXX..XXXXXXX 100644
443
--- a/default-configs/arm-softmmu.mak
444
+++ b/default-configs/arm-softmmu.mak
445
@@ -XXX,XX +XXX,XX @@ CONFIG_TWL92230=y
446
CONFIG_TSC2005=y
447
CONFIG_LM832X=y
448
CONFIG_TMP105=y
449
+CONFIG_TMP421=y
450
CONFIG_STELLARIS=y
451
CONFIG_STELLARIS_INPUT=y
452
CONFIG_STELLARIS_ENET=y
453
--
171
--
454
2.7.4
172
2.17.1
455
173
456
174
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/17] timer.h: Provide better monotonic time
[Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument
1
From: Pranith Kumar <bobby.prani@gmail.com>
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
2
5
3
Tested and confirmed that the stretch i386 debian qcow2 image on a
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
raspberry pi 2 works.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
10
---
11
include/exec/exec-all.h | 5 +++--
12
accel/tcg/translate-all.c | 2 +-
13
exec.c | 2 +-
14
target/xtensa/op_helper.c | 3 ++-
15
4 files changed, 7 insertions(+), 5 deletions(-)
5
16
6
Fixes: LP#: 893208 <https://bugs.launchpad.net/qemu/+bug/893208/>
17
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
7
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
8
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
9
Message-id: 20170418191817.10430-1-bobby.prani@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/qemu/timer.h | 5 ++---
13
1 file changed, 2 insertions(+), 3 deletions(-)
14
15
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/include/qemu/timer.h
19
--- a/include/exec/exec-all.h
18
+++ b/include/qemu/timer.h
20
+++ b/include/exec/exec-all.h
19
@@ -XXX,XX +XXX,XX @@ static inline int64_t cpu_get_host_ticks(void)
21
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
20
/* The host CPU doesn't have an easily accessible cycle counter.
22
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
21
Just return a monotonically increasing value. This will be
23
hwaddr paddr, int prot,
22
totally wrong, but hopefully better than nothing. */
24
int mmu_idx, target_ulong size);
23
-static inline int64_t cpu_get_host_ticks (void)
25
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
24
+static inline int64_t cpu_get_host_ticks(void)
26
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
27
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
28
uintptr_t retaddr);
29
#else
30
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
31
uint16_t idxmap)
25
{
32
{
26
- static int64_t ticks = 0;
33
}
27
- return ticks++;
34
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
28
+ return get_clock();
35
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
36
+ MemTxAttrs attrs)
37
{
29
}
38
}
30
#endif
39
#endif
40
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/accel/tcg/translate-all.c
43
+++ b/accel/tcg/translate-all.c
44
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
45
}
46
47
#if !defined(CONFIG_USER_ONLY)
48
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
49
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
50
{
51
ram_addr_t ram_addr;
52
MemoryRegion *mr;
53
diff --git a/exec.c b/exec.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/exec.c
56
+++ b/exec.c
57
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
58
if (phys != -1) {
59
/* Locks grabbed by tb_invalidate_phys_addr */
60
tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
61
- phys | (pc & ~TARGET_PAGE_MASK));
62
+ phys | (pc & ~TARGET_PAGE_MASK), attrs);
63
}
64
}
65
#endif
66
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/xtensa/op_helper.c
69
+++ b/target/xtensa/op_helper.c
70
@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
71
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
72
&paddr, &page_size, &access);
73
if (ret == 0) {
74
- tb_invalidate_phys_addr(&address_space_memory, paddr);
75
+ tb_invalidate_phys_addr(&address_space_memory, paddr,
76
+ MEMTXATTRS_UNSPECIFIED);
77
}
78
}
31
79
32
--
80
--
33
2.7.4
81
2.17.1
34
82
35
83
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument
1
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_translate()
3
and address_space_translate_cached(). Callers either have an
4
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 4 +++-
12
accel/tcg/translate-all.c | 2 +-
13
exec.c | 14 +++++++++-----
14
hw/vfio/common.c | 3 ++-
15
memory_ldst.inc.c | 18 +++++++++---------
16
target/riscv/helper.c | 2 +-
17
6 files changed, 25 insertions(+), 18 deletions(-)
18
19
diff --git a/include/exec/memory.h b/include/exec/memory.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/exec/memory.h
22
+++ b/include/exec/memory.h
23
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
24
* #MemoryRegion.
25
* @len: pointer to length
26
* @is_write: indicates the transfer direction
27
+ * @attrs: memory attributes
28
*/
29
MemoryRegion *flatview_translate(FlatView *fv,
30
hwaddr addr, hwaddr *xlat,
31
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
32
33
static inline MemoryRegion *address_space_translate(AddressSpace *as,
34
hwaddr addr, hwaddr *xlat,
35
- hwaddr *len, bool is_write)
36
+ hwaddr *len, bool is_write,
37
+ MemTxAttrs attrs)
38
{
39
return flatview_translate(address_space_to_flatview(as),
40
addr, xlat, len, is_write);
41
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/accel/tcg/translate-all.c
44
+++ b/accel/tcg/translate-all.c
45
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
46
hwaddr l = 1;
47
48
rcu_read_lock();
49
- mr = address_space_translate(as, addr, &addr, &l, false);
50
+ mr = address_space_translate(as, addr, &addr, &l, false, attrs);
51
if (!(memory_region_is_ram(mr)
52
|| memory_region_is_romd(mr))) {
53
rcu_read_unlock();
54
diff --git a/exec.c b/exec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/exec.c
57
+++ b/exec.c
58
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
59
rcu_read_lock();
60
while (len > 0) {
61
l = len;
62
- mr = address_space_translate(as, addr, &addr1, &l, true);
63
+ mr = address_space_translate(as, addr, &addr1, &l, true,
64
+ MEMTXATTRS_UNSPECIFIED);
65
66
if (!(memory_region_is_ram(mr) ||
67
memory_region_is_romd(mr))) {
68
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
69
*/
70
static inline MemoryRegion *address_space_translate_cached(
71
MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
72
- hwaddr *plen, bool is_write)
73
+ hwaddr *plen, bool is_write, MemTxAttrs attrs)
74
{
75
MemoryRegionSection section;
76
MemoryRegion *mr;
77
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
78
MemoryRegion *mr;
79
80
l = len;
81
- mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
82
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
83
+ MEMTXATTRS_UNSPECIFIED);
84
flatview_read_continue(cache->fv,
85
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
86
addr1, l, mr);
87
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
88
MemoryRegion *mr;
89
90
l = len;
91
- mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
92
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
93
+ MEMTXATTRS_UNSPECIFIED);
94
flatview_write_continue(cache->fv,
95
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
96
addr1, l, mr);
97
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
98
99
rcu_read_lock();
100
mr = address_space_translate(&address_space_memory,
101
- phys_addr, &phys_addr, &l, false);
102
+ phys_addr, &phys_addr, &l, false,
103
+ MEMTXATTRS_UNSPECIFIED);
104
105
res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
106
rcu_read_unlock();
107
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/vfio/common.c
110
+++ b/hw/vfio/common.c
111
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
112
*/
113
mr = address_space_translate(&address_space_memory,
114
iotlb->translated_addr,
115
- &xlat, &len, writable);
116
+ &xlat, &len, writable,
117
+ MEMTXATTRS_UNSPECIFIED);
118
if (!memory_region_is_ram(mr)) {
119
error_report("iommu map to non memory area %"HWADDR_PRIx"",
120
xlat);
121
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/memory_ldst.inc.c
124
+++ b/memory_ldst.inc.c
125
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
126
bool release_lock = false;
127
128
RCU_READ_LOCK();
129
- mr = TRANSLATE(addr, &addr1, &l, false);
130
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
131
if (l < 4 || !IS_DIRECT(mr, false)) {
132
release_lock |= prepare_mmio_access(mr);
133
134
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
135
bool release_lock = false;
136
137
RCU_READ_LOCK();
138
- mr = TRANSLATE(addr, &addr1, &l, false);
139
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
140
if (l < 8 || !IS_DIRECT(mr, false)) {
141
release_lock |= prepare_mmio_access(mr);
142
143
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
144
bool release_lock = false;
145
146
RCU_READ_LOCK();
147
- mr = TRANSLATE(addr, &addr1, &l, false);
148
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
149
if (!IS_DIRECT(mr, false)) {
150
release_lock |= prepare_mmio_access(mr);
151
152
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
153
bool release_lock = false;
154
155
RCU_READ_LOCK();
156
- mr = TRANSLATE(addr, &addr1, &l, false);
157
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
158
if (l < 2 || !IS_DIRECT(mr, false)) {
159
release_lock |= prepare_mmio_access(mr);
160
161
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
162
bool release_lock = false;
163
164
RCU_READ_LOCK();
165
- mr = TRANSLATE(addr, &addr1, &l, true);
166
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
167
if (l < 4 || !IS_DIRECT(mr, true)) {
168
release_lock |= prepare_mmio_access(mr);
169
170
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
171
bool release_lock = false;
172
173
RCU_READ_LOCK();
174
- mr = TRANSLATE(addr, &addr1, &l, true);
175
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
176
if (l < 4 || !IS_DIRECT(mr, true)) {
177
release_lock |= prepare_mmio_access(mr);
178
179
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
180
bool release_lock = false;
181
182
RCU_READ_LOCK();
183
- mr = TRANSLATE(addr, &addr1, &l, true);
184
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
185
if (!IS_DIRECT(mr, true)) {
186
release_lock |= prepare_mmio_access(mr);
187
r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
188
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
189
bool release_lock = false;
190
191
RCU_READ_LOCK();
192
- mr = TRANSLATE(addr, &addr1, &l, true);
193
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
194
if (l < 2 || !IS_DIRECT(mr, true)) {
195
release_lock |= prepare_mmio_access(mr);
196
197
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
198
bool release_lock = false;
199
200
RCU_READ_LOCK();
201
- mr = TRANSLATE(addr, &addr1, &l, true);
202
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
203
if (l < 8 || !IS_DIRECT(mr, true)) {
204
release_lock |= prepare_mmio_access(mr);
205
206
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
207
index XXXXXXX..XXXXXXX 100644
208
--- a/target/riscv/helper.c
209
+++ b/target/riscv/helper.c
210
@@ -XXX,XX +XXX,XX @@ restart:
211
MemoryRegion *mr;
212
hwaddr l = sizeof(target_ulong), addr1;
213
mr = address_space_translate(cs->as, pte_addr,
214
- &addr1, &l, false);
215
+ &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
216
if (memory_access_is_direct(mr, true)) {
217
target_ulong *pte_pa =
218
qemu_map_ram_ptr(mr->ram_block, addr1);
219
--
220
2.17.1
221
222
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_map().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 3 ++-
12
include/sysemu/dma.h | 3 ++-
13
exec.c | 6 ++++--
14
target/ppc/mmu-hash64.c | 3 ++-
15
4 files changed, 10 insertions(+), 5 deletions(-)
16
17
diff --git a/include/exec/memory.h b/include/exec/memory.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/memory.h
20
+++ b/include/exec/memory.h
21
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
22
* @addr: address within that address space
23
* @plen: pointer to length of buffer; updated on return
24
* @is_write: indicates the transfer direction
25
+ * @attrs: memory attributes
26
*/
27
void *address_space_map(AddressSpace *as, hwaddr addr,
28
- hwaddr *plen, bool is_write);
29
+ hwaddr *plen, bool is_write, MemTxAttrs attrs);
30
31
/* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
32
*
33
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/include/sysemu/dma.h
36
+++ b/include/sysemu/dma.h
37
@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
38
hwaddr xlen = *len;
39
void *p;
40
41
- p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
42
+ p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
43
+ MEMTXATTRS_UNSPECIFIED);
44
*len = xlen;
45
return p;
46
}
47
diff --git a/exec.c b/exec.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/exec.c
50
+++ b/exec.c
51
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
52
void *address_space_map(AddressSpace *as,
53
hwaddr addr,
54
hwaddr *plen,
55
- bool is_write)
56
+ bool is_write,
57
+ MemTxAttrs attrs)
58
{
59
hwaddr len = *plen;
60
hwaddr l, xlat;
61
@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
62
hwaddr *plen,
63
int is_write)
64
{
65
- return address_space_map(&address_space_memory, addr, plen, is_write);
66
+ return address_space_map(&address_space_memory, addr, plen, is_write,
67
+ MEMTXATTRS_UNSPECIFIED);
68
}
69
70
void cpu_physical_memory_unmap(void *buffer, hwaddr len,
71
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/ppc/mmu-hash64.c
74
+++ b/target/ppc/mmu-hash64.c
75
@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
76
return NULL;
77
}
78
79
- hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
80
+ hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
81
+ MEMTXATTRS_UNSPECIFIED);
82
if (plen < (n * HASH_PTE_SIZE_64)) {
83
hw_error("%s: Unable to map all requested HPTEs\n", __func__);
84
}
85
--
86
2.17.1
87
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/17] hw/misc/exynos4210_pmu: Add support for system poweroff
[Qemu-devel] [PULL 14/25] Make address_space_access_valid() take a MemTxAttrs argument
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_access_valid().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
2
5
3
On all Exynos-based boards, the system powers down itself by driving
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
PS_HOLD signal low - eight bit in PS_HOLD_CONTROL register of PMU.
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Handle writing to respective PMU register to fix power off failure:
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 4 +++-
12
include/sysemu/dma.h | 3 ++-
13
exec.c | 3 ++-
14
target/s390x/diag.c | 6 ++++--
15
target/s390x/excp_helper.c | 3 ++-
16
target/s390x/mmu_helper.c | 3 ++-
17
target/s390x/sigp.c | 3 ++-
18
7 files changed, 17 insertions(+), 8 deletions(-)
6
19
7
reboot: Power down
20
diff --git a/include/exec/memory.h b/include/exec/memory.h
8
Unable to poweroff system
9
shutdown: 31 output lines suppressed due to ratelimiting
10
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000000
11
12
CPU: 0 PID: 1 Comm: shutdown Not tainted 4.11.0-rc8 #846
13
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
14
[<c031050c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14)
15
[<c030ba6c>] (show_stack) from [<c05b2800>] (dump_stack+0x88/0x9c)
16
[<c05b2800>] (dump_stack) from [<c03d3140>] (panic+0xdc/0x268)
17
[<c03d3140>] (panic) from [<c0343614>] (do_exit+0xa90/0xab4)
18
[<c0343614>] (do_exit) from [<c035f2dc>] (SyS_reboot+0x164/0x1d0)
19
[<c035f2dc>] (SyS_reboot) from [<c0307c80>] (ret_fast_syscall+0x0/0x3c)
20
21
Additionally the initial value of PS_HOLD has to be changed because
22
recent Linux kernel (v4.12-rc1) uses regmap cache for this access.
23
When the register is kept at reset value, the kernel will not issue a
24
write to it. Usually the bootloader sets the eight bit of PS_HOLD high
25
so mimic its existence here.
26
27
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
32
hw/misc/exynos4210_pmu.c | 20 +++++++++++++++++++-
33
1 file changed, 19 insertions(+), 1 deletion(-)
34
35
diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c
36
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/misc/exynos4210_pmu.c
22
--- a/include/exec/memory.h
38
+++ b/hw/misc/exynos4210_pmu.c
23
+++ b/include/exec/memory.h
39
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
40
25
* @addr: address within that address space
41
#include "qemu/osdep.h"
26
* @len: length of the area to be checked
42
#include "hw/sysbus.h"
27
* @is_write: indicates the transfer direction
43
+#include "sysemu/sysemu.h"
28
+ * @attrs: memory attributes
44
29
*/
45
#ifndef DEBUG_PMU
30
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
46
#define DEBUG_PMU 0
31
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
47
@@ -XXX,XX +XXX,XX @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
32
+ bool is_write, MemTxAttrs attrs);
48
{"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000},
33
49
{"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000},
34
/* address_space_map: map a physical memory region into a host virtual address
50
{"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000},
35
*
51
- {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200},
36
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
52
+ /*
37
index XXXXXXX..XXXXXXX 100644
53
+ * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit.
38
--- a/include/sysemu/dma.h
54
+ * DATA bit high, set usually by bootloader, keeps system on.
39
+++ b/include/sysemu/dma.h
55
+ */
40
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
56
+ {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)},
41
DMADirection dir)
57
{"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001},
58
{"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001},
59
{"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000},
60
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210PmuState {
61
uint32_t reg[PMU_NUM_OF_REGISTERS];
62
} Exynos4210PmuState;
63
64
+static void exynos4210_pmu_poweroff(void)
65
+{
66
+ PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n");
67
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
68
+}
69
+
70
static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
71
unsigned size)
72
{
42
{
73
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
43
return address_space_access_valid(as, addr, len,
74
PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
44
- dir == DMA_DIRECTION_FROM_DEVICE);
75
(uint32_t)offset, (uint32_t)val);
45
+ dir == DMA_DIRECTION_FROM_DEVICE,
76
s->reg[i] = val;
46
+ MEMTXATTRS_UNSPECIFIED);
77
+ if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) {
47
}
78
+ /*
48
79
+ * We are interested only in setting data bit
49
static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
80
+ * of PS_HOLD_CONTROL register to indicate power off request.
50
diff --git a/exec.c b/exec.c
81
+ */
51
index XXXXXXX..XXXXXXX 100644
82
+ exynos4210_pmu_poweroff();
52
--- a/exec.c
83
+ }
53
+++ b/exec.c
54
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
55
}
56
57
bool address_space_access_valid(AddressSpace *as, hwaddr addr,
58
- int len, bool is_write)
59
+ int len, bool is_write,
60
+ MemTxAttrs attrs)
61
{
62
FlatView *fv;
63
bool result;
64
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/s390x/diag.c
67
+++ b/target/s390x/diag.c
68
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
84
return;
69
return;
85
}
70
}
86
reg_p++;
71
if (!address_space_access_valid(&address_space_memory, addr,
72
- sizeof(IplParameterBlock), false)) {
73
+ sizeof(IplParameterBlock), false,
74
+ MEMTXATTRS_UNSPECIFIED)) {
75
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
76
return;
77
}
78
@@ -XXX,XX +XXX,XX @@ out:
79
return;
80
}
81
if (!address_space_access_valid(&address_space_memory, addr,
82
- sizeof(IplParameterBlock), true)) {
83
+ sizeof(IplParameterBlock), true,
84
+ MEMTXATTRS_UNSPECIFIED)) {
85
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
86
return;
87
}
88
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/s390x/excp_helper.c
91
+++ b/target/s390x/excp_helper.c
92
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
93
94
/* check out of RAM access */
95
if (!address_space_access_valid(&address_space_memory, raddr,
96
- TARGET_PAGE_SIZE, rw)) {
97
+ TARGET_PAGE_SIZE, rw,
98
+ MEMTXATTRS_UNSPECIFIED)) {
99
DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
100
(uint64_t)raddr, (uint64_t)ram_size);
101
trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
102
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/s390x/mmu_helper.c
105
+++ b/target/s390x/mmu_helper.c
106
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
107
return ret;
108
}
109
if (!address_space_access_valid(&address_space_memory, pages[i],
110
- TARGET_PAGE_SIZE, is_write)) {
111
+ TARGET_PAGE_SIZE, is_write,
112
+ MEMTXATTRS_UNSPECIFIED)) {
113
trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
114
return -EFAULT;
115
}
116
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/s390x/sigp.c
119
+++ b/target/s390x/sigp.c
120
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
121
cpu_synchronize_state(cs);
122
123
if (!address_space_access_valid(&address_space_memory, addr,
124
- sizeof(struct LowCore), false)) {
125
+ sizeof(struct LowCore), false,
126
+ MEMTXATTRS_UNSPECIFIED)) {
127
set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
128
return;
129
}
87
--
130
--
88
2.7.4
131
2.17.1
89
132
90
133
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_extend_translation().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
10
---
11
exec.c | 15 ++++++++++-----
12
1 file changed, 10 insertions(+), 5 deletions(-)
13
14
diff --git a/exec.c b/exec.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/exec.c
17
+++ b/exec.c
18
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
19
20
static hwaddr
21
flatview_extend_translation(FlatView *fv, hwaddr addr,
22
- hwaddr target_len,
23
- MemoryRegion *mr, hwaddr base, hwaddr len,
24
- bool is_write)
25
+ hwaddr target_len,
26
+ MemoryRegion *mr, hwaddr base, hwaddr len,
27
+ bool is_write, MemTxAttrs attrs)
28
{
29
hwaddr done = 0;
30
hwaddr xlat;
31
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
32
33
memory_region_ref(mr);
34
*plen = flatview_extend_translation(fv, addr, len, mr, xlat,
35
- l, is_write);
36
+ l, is_write, attrs);
37
ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
38
rcu_read_unlock();
39
40
@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
41
mr = cache->mrs.mr;
42
memory_region_ref(mr);
43
if (memory_access_is_direct(mr, is_write)) {
44
+ /* We don't care about the memory attributes here as we're only
45
+ * doing this if we found actual RAM, which behaves the same
46
+ * regardless of attributes; so UNSPECIFIED is fine.
47
+ */
48
l = flatview_extend_translation(cache->fv, addr, len, mr,
49
- cache->xlat, l, is_write);
50
+ cache->xlat, l, is_write,
51
+ MEMTXATTRS_UNSPECIFIED);
52
cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
53
} else {
54
cache->ptr = NULL;
55
--
56
2.17.1
57
58
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to memory_region_access_valid().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
1
5
6
The callsite in flatview_access_valid() is part of a recursive
7
loop flatview_access_valid() -> memory_region_access_valid() ->
8
subpage_accepts() -> flatview_access_valid(); we make it pass
9
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
10
have plumbed an attrs parameter through the rest of the loop
11
and we can add an attrs parameter to flatview_access_valid().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
17
---
18
include/exec/memory-internal.h | 3 ++-
19
exec.c | 4 +++-
20
hw/s390x/s390-pci-inst.c | 3 ++-
21
memory.c | 7 ++++---
22
4 files changed, 11 insertions(+), 6 deletions(-)
23
24
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/exec/memory-internal.h
27
+++ b/include/exec/memory-internal.h
28
@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
29
extern const MemoryRegionOps unassigned_mem_ops;
30
31
bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
32
- unsigned size, bool is_write);
33
+ unsigned size, bool is_write,
34
+ MemTxAttrs attrs);
35
36
void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
37
AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
38
diff --git a/exec.c b/exec.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/exec.c
41
+++ b/exec.c
42
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
43
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
44
if (!memory_access_is_direct(mr, is_write)) {
45
l = memory_access_size(mr, l, addr);
46
- if (!memory_region_access_valid(mr, xlat, l, is_write)) {
47
+ /* When our callers all have attrs we'll pass them through here */
48
+ if (!memory_region_access_valid(mr, xlat, l, is_write,
49
+ MEMTXATTRS_UNSPECIFIED)) {
50
return false;
51
}
52
}
53
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/s390x/s390-pci-inst.c
56
+++ b/hw/s390x/s390-pci-inst.c
57
@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
58
mr = s390_get_subregion(mr, offset, len);
59
offset -= mr->addr;
60
61
- if (!memory_region_access_valid(mr, offset, len, true)) {
62
+ if (!memory_region_access_valid(mr, offset, len, true,
63
+ MEMTXATTRS_UNSPECIFIED)) {
64
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
65
return 0;
66
}
67
diff --git a/memory.c b/memory.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/memory.c
70
+++ b/memory.c
71
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
72
bool memory_region_access_valid(MemoryRegion *mr,
73
hwaddr addr,
74
unsigned size,
75
- bool is_write)
76
+ bool is_write,
77
+ MemTxAttrs attrs)
78
{
79
int access_size_min, access_size_max;
80
int access_size, i;
81
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
82
{
83
MemTxResult r;
84
85
- if (!memory_region_access_valid(mr, addr, size, false)) {
86
+ if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
87
*pval = unassigned_mem_read(mr, addr, size);
88
return MEMTX_DECODE_ERROR;
89
}
90
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
91
unsigned size,
92
MemTxAttrs attrs)
93
{
94
- if (!memory_region_access_valid(mr, addr, size, true)) {
95
+ if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
96
unassigned_mem_write(mr, addr, data, size);
97
return MEMTX_DECODE_ERROR;
98
}
99
--
100
2.17.1
101
102
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/17] hw/intc/arm_gicv3_its: Implement state save/restore
[Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
1
From: Eric Auger <eric.auger@redhat.com>
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
3
callback. We'll need this for subpage_accepts().
2
4
3
We need to handle both registers and ITS tables. While
5
We could take the approach we used with the read and write
4
register handling is standard, ITS table handling is more
6
callbacks and add new a new _with_attrs version, but since there
5
challenging since the kernel API is devised so that the
7
are so few implementations of the accepts hook we just change
6
tables are flushed into guest RAM and not in vmstate buffers.
8
them all.
7
9
8
Flushing the ITS tables on device pre_save() is too late
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
since the guest RAM is already saved at this point.
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
14
---
15
include/exec/memory.h | 3 ++-
16
exec.c | 9 ++++++---
17
hw/hppa/dino.c | 3 ++-
18
hw/nvram/fw_cfg.c | 12 ++++++++----
19
hw/scsi/esp.c | 3 ++-
20
hw/xen/xen_pt_msi.c | 3 ++-
21
memory.c | 5 +++--
22
7 files changed, 25 insertions(+), 13 deletions(-)
10
23
11
Table flushing needs to happen when we are sure the vcpus
24
diff --git a/include/exec/memory.h b/include/exec/memory.h
12
are stopped and before the last dirty page saving. The
13
right point is RUN_STATE_FINISH_MIGRATE but sometimes the
14
VM gets stopped before migration launch so let's simply
15
flush the tables each time the VM gets stopped.
16
17
For regular ITS registers we just can use vmstate pre_save()
18
and post_load() callbacks.
19
20
Signed-off-by: Eric Auger <eric.auger@redhat.com>
21
Message-id: 1497023553-18411-3-git-send-email-eric.auger@redhat.com
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
include/hw/intc/arm_gicv3_its_common.h | 8 +++
26
hw/intc/arm_gicv3_its_common.c | 10 ++++
27
hw/intc/arm_gicv3_its_kvm.c | 105 +++++++++++++++++++++++++++++++++
28
3 files changed, 123 insertions(+)
29
30
diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
31
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/intc/arm_gicv3_its_common.h
26
--- a/include/exec/memory.h
33
+++ b/include/hw/intc/arm_gicv3_its_common.h
27
+++ b/include/exec/memory.h
34
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
35
#define ITS_TRANS_SIZE 0x10000
29
* as a machine check exception).
36
#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
30
*/
37
31
bool (*accepts)(void *opaque, hwaddr addr,
38
+#define GITS_CTLR 0x0
32
- unsigned size, bool is_write);
39
+#define GITS_IIDR 0x4
33
+ unsigned size, bool is_write,
40
+#define GITS_CBASER 0x80
34
+ MemTxAttrs attrs);
41
+#define GITS_CWRITER 0x88
35
} valid;
42
+#define GITS_CREADR 0x90
36
/* Internal implementation constraints: */
43
+#define GITS_BASER 0x100
37
struct {
44
+
38
diff --git a/exec.c b/exec.c
45
struct GICv3ITSState {
46
SysBusDevice parent_obj;
47
48
@@ -XXX,XX +XXX,XX @@ struct GICv3ITSState {
49
50
/* Registers */
51
uint32_t ctlr;
52
+ uint32_t iidr;
53
uint64_t cbaser;
54
uint64_t cwriter;
55
uint64_t creadr;
56
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
57
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/arm_gicv3_its_common.c
40
--- a/exec.c
59
+++ b/hw/intc/arm_gicv3_its_common.c
41
+++ b/exec.c
60
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = {
42
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
61
.pre_save = gicv3_its_pre_save,
43
}
62
.post_load = gicv3_its_post_load,
44
63
.unmigratable = true,
45
static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
64
+ .fields = (VMStateField[]) {
46
- unsigned size, bool is_write)
65
+ VMSTATE_UINT32(ctlr, GICv3ITSState),
47
+ unsigned size, bool is_write,
66
+ VMSTATE_UINT32(iidr, GICv3ITSState),
48
+ MemTxAttrs attrs)
67
+ VMSTATE_UINT64(cbaser, GICv3ITSState),
49
{
68
+ VMSTATE_UINT64(cwriter, GICv3ITSState),
50
return is_write;
69
+ VMSTATE_UINT64(creadr, GICv3ITSState),
51
}
70
+ VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
52
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
71
+ VMSTATE_END_OF_LIST()
53
}
72
+ },
54
73
};
55
static bool subpage_accepts(void *opaque, hwaddr addr,
74
56
- unsigned len, bool is_write)
75
static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
57
+ unsigned len, bool is_write,
76
@@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev)
58
+ MemTxAttrs attrs)
77
s->cbaser = 0;
59
{
78
s->cwriter = 0;
60
subpage_t *subpage = opaque;
79
s->creadr = 0;
61
#if defined(DEBUG_SUBPAGE)
80
+ s->iidr = 0;
62
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
81
memset(&s->baser, 0, sizeof(s->baser));
63
}
82
64
83
gicv3_its_post_load(s, 0);
65
static bool readonly_mem_accepts(void *opaque, hwaddr addr,
84
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
66
- unsigned size, bool is_write)
67
+ unsigned size, bool is_write,
68
+ MemTxAttrs attrs)
69
{
70
return is_write;
71
}
72
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
85
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/intc/arm_gicv3_its_kvm.c
74
--- a/hw/hppa/dino.c
87
+++ b/hw/intc/arm_gicv3_its_kvm.c
75
+++ b/hw/hppa/dino.c
88
@@ -XXX,XX +XXX,XX @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
76
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
89
return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
90
}
77
}
91
78
92
+/**
79
static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
93
+ * vm_change_state_handler - VM change state callback aiming at flushing
80
- unsigned size, bool is_write)
94
+ * ITS tables into guest RAM
81
+ unsigned size, bool is_write,
95
+ *
82
+ MemTxAttrs attrs)
96
+ * The tables get flushed to guest RAM whenever the VM gets stopped.
97
+ */
98
+static void vm_change_state_handler(void *opaque, int running,
99
+ RunState state)
100
+{
101
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
102
+ Error *err = NULL;
103
+ int ret;
104
+
105
+ if (running) {
106
+ return;
107
+ }
108
+
109
+ ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
110
+ KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err);
111
+ if (err) {
112
+ error_report_err(err);
113
+ }
114
+ if (ret < 0 && ret != -EFAULT) {
115
+ abort();
116
+ }
117
+}
118
+
119
static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
120
{
83
{
121
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
84
switch (addr) {
122
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
85
case DINO_IAR0:
123
kvm_msi_use_devid = true;
86
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
124
kvm_gsi_direct_mapping = false;
87
index XXXXXXX..XXXXXXX 100644
125
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
88
--- a/hw/nvram/fw_cfg.c
126
+
89
+++ b/hw/nvram/fw_cfg.c
127
+ qemu_add_vm_change_state_handler(vm_change_state_handler, s);
90
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
128
}
91
}
129
92
130
static void kvm_arm_its_init(Object *obj)
93
static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
131
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_init(Object *obj)
94
- unsigned size, bool is_write)
132
&error_abort);
95
+ unsigned size, bool is_write,
96
+ MemTxAttrs attrs)
97
{
98
return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
99
(size == 8 && addr == 0));
133
}
100
}
134
101
135
+/**
102
static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
136
+ * kvm_arm_its_pre_save - handles the saving of ITS registers.
103
- unsigned size, bool is_write)
137
+ * ITS tables are flushed into guest RAM separately and earlier,
104
+ unsigned size, bool is_write,
138
+ * through the VM change state handler, since at the moment pre_save()
105
+ MemTxAttrs attrs)
139
+ * is called, the guest RAM has already been saved.
140
+ */
141
+static void kvm_arm_its_pre_save(GICv3ITSState *s)
142
+{
143
+ int i;
144
+
145
+ for (i = 0; i < 8; i++) {
146
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
147
+ GITS_BASER + i * 8, &s->baser[i], false,
148
+ &error_abort);
149
+ }
150
+
151
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
152
+ GITS_CTLR, &s->ctlr, false, &error_abort);
153
+
154
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
155
+ GITS_CBASER, &s->cbaser, false, &error_abort);
156
+
157
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
158
+ GITS_CREADR, &s->creadr, false, &error_abort);
159
+
160
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
161
+ GITS_CWRITER, &s->cwriter, false, &error_abort);
162
+
163
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
164
+ GITS_IIDR, &s->iidr, false, &error_abort);
165
+}
166
+
167
+/**
168
+ * kvm_arm_its_post_load - Restore both the ITS registers and tables
169
+ */
170
+static void kvm_arm_its_post_load(GICv3ITSState *s)
171
+{
172
+ int i;
173
+
174
+ if (!s->iidr) {
175
+ return;
176
+ }
177
+
178
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
179
+ GITS_IIDR, &s->iidr, true, &error_abort);
180
+
181
+ /*
182
+ * must be written before GITS_CREADR since GITS_CBASER write
183
+ * access resets GITS_CREADR.
184
+ */
185
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
186
+ GITS_CBASER, &s->cbaser, true, &error_abort);
187
+
188
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
189
+ GITS_CREADR, &s->creadr, true, &error_abort);
190
+
191
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
192
+ GITS_CWRITER, &s->cwriter, true, &error_abort);
193
+
194
+
195
+ for (i = 0; i < 8; i++) {
196
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
197
+ GITS_BASER + i * 8, &s->baser[i], true,
198
+ &error_abort);
199
+ }
200
+
201
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
202
+ KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true,
203
+ &error_abort);
204
+
205
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
206
+ GITS_CTLR, &s->ctlr, true, &error_abort);
207
+}
208
+
209
static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
210
{
106
{
211
DeviceClass *dc = DEVICE_CLASS(klass);
107
return addr == 0;
212
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
213
214
dc->realize = kvm_arm_its_realize;
215
icc->send_msi = kvm_its_send_msi;
216
+ icc->pre_save = kvm_arm_its_pre_save;
217
+ icc->post_load = kvm_arm_its_post_load;
218
}
108
}
219
109
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
220
static const TypeInfo kvm_arm_its_info = {
110
}
111
112
static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
113
- unsigned size, bool is_write)
114
+ unsigned size, bool is_write,
115
+ MemTxAttrs attrs)
116
{
117
return is_write && size == 2;
118
}
119
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
120
}
121
122
static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
123
- unsigned size, bool is_write)
124
+ unsigned size, bool is_write,
125
+ MemTxAttrs attrs)
126
{
127
return (size == 1) || (is_write && size == 2);
128
}
129
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/hw/scsi/esp.c
132
+++ b/hw/scsi/esp.c
133
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
134
}
135
136
static bool esp_mem_accepts(void *opaque, hwaddr addr,
137
- unsigned size, bool is_write)
138
+ unsigned size, bool is_write,
139
+ MemTxAttrs attrs)
140
{
141
return (size == 1) || (is_write && size == 4);
142
}
143
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/xen/xen_pt_msi.c
146
+++ b/hw/xen/xen_pt_msi.c
147
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
148
}
149
150
static bool pci_msix_accepts(void *opaque, hwaddr addr,
151
- unsigned size, bool is_write)
152
+ unsigned size, bool is_write,
153
+ MemTxAttrs attrs)
154
{
155
return !(addr & (size - 1));
156
}
157
diff --git a/memory.c b/memory.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/memory.c
160
+++ b/memory.c
161
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
162
}
163
164
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
165
- unsigned size, bool is_write)
166
+ unsigned size, bool is_write,
167
+ MemTxAttrs attrs)
168
{
169
return false;
170
}
171
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
172
access_size = MAX(MIN(size, access_size_max), access_size_min);
173
for (i = 0; i < size; i += access_size) {
174
if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
175
- is_write)) {
176
+ is_write, attrs)) {
177
return false;
178
}
179
}
221
--
180
--
222
2.7.4
181
2.17.1
223
182
224
183
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_access_valid().
3
Its callers now all have an attrs value to hand, so we can
4
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
10
---
11
exec.c | 12 +++++-------
12
1 file changed, 5 insertions(+), 7 deletions(-)
13
14
diff --git a/exec.c b/exec.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/exec.c
17
+++ b/exec.c
18
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
19
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
20
const uint8_t *buf, int len);
21
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
22
- bool is_write);
23
+ bool is_write, MemTxAttrs attrs);
24
25
static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
26
unsigned len, MemTxAttrs attrs)
27
@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
28
#endif
29
30
return flatview_access_valid(subpage->fv, addr + subpage->base,
31
- len, is_write);
32
+ len, is_write, attrs);
33
}
34
35
static const MemoryRegionOps subpage_ops = {
36
@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
37
}
38
39
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
40
- bool is_write)
41
+ bool is_write, MemTxAttrs attrs)
42
{
43
MemoryRegion *mr;
44
hwaddr l, xlat;
45
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
46
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
47
if (!memory_access_is_direct(mr, is_write)) {
48
l = memory_access_size(mr, l, addr);
49
- /* When our callers all have attrs we'll pass them through here */
50
- if (!memory_region_access_valid(mr, xlat, l, is_write,
51
- MEMTXATTRS_UNSPECIFIED)) {
52
+ if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
53
return false;
54
}
55
}
56
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
57
58
rcu_read_lock();
59
fv = address_space_to_flatview(as);
60
- result = flatview_access_valid(fv, addr, len, is_write);
61
+ result = flatview_access_valid(fv, addr, len, is_write, attrs);
62
rcu_read_unlock();
63
return result;
64
}
65
--
66
2.17.1
67
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/17] aspeed: add a temp sensor device on I2C bus 3
[Qemu-devel] [PULL 19/25] Make flatview_translate() take a MemTxAttrs argument
1
From: Cédric Le Goater <clg@kaod.org>
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_translate(); all its
3
callers now have attrs available.
2
4
3
Temperatures can be changed from the monitor with :
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
9
---
10
include/exec/memory.h | 7 ++++---
11
exec.c | 17 +++++++++--------
12
2 files changed, 13 insertions(+), 11 deletions(-)
4
13
5
    (qemu) qom-set /machine/unattached/device[2] temperature0 12000
14
diff --git a/include/exec/memory.h b/include/exec/memory.h
6
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 1496739230-32109-3-git-send-email-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/aspeed.c | 9 +++++++++
13
1 file changed, 9 insertions(+)
14
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed.c
16
--- a/include/exec/memory.h
18
+++ b/hw/arm/aspeed.c
17
+++ b/include/exec/memory.h
19
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
18
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
20
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
19
*/
20
MemoryRegion *flatview_translate(FlatView *fv,
21
hwaddr addr, hwaddr *xlat,
22
- hwaddr *len, bool is_write);
23
+ hwaddr *len, bool is_write,
24
+ MemTxAttrs attrs);
25
26
static inline MemoryRegion *address_space_translate(AddressSpace *as,
27
hwaddr addr, hwaddr *xlat,
28
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
29
MemTxAttrs attrs)
21
{
30
{
22
AspeedSoCState *soc = &bmc->soc;
31
return flatview_translate(address_space_to_flatview(as),
23
+ DeviceState *dev;
32
- addr, xlat, len, is_write);
24
33
+ addr, xlat, len, is_write, attrs);
25
/* The palmetto platform expects a ds3231 RTC but a ds1338 is
26
* enough to provide basic RTC features. Alarms will be missing */
27
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
28
+
29
+ /* add a TMP423 temperature sensor */
30
+ dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
31
+ "tmp423", 0x4c);
32
+ object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
33
+ object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
34
+ object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
35
+ object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
36
}
34
}
37
35
38
static void palmetto_bmc_init(MachineState *machine)
36
/* address_space_access_valid: check for validity of accessing an address
37
@@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
38
rcu_read_lock();
39
fv = address_space_to_flatview(as);
40
l = len;
41
- mr = flatview_translate(fv, addr, &addr1, &l, false);
42
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
43
if (len == l && memory_access_is_direct(mr, false)) {
44
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
45
memcpy(buf, ptr, len);
46
diff --git a/exec.c b/exec.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/exec.c
49
+++ b/exec.c
50
@@ -XXX,XX +XXX,XX @@ iotlb_fail:
51
52
/* Called from RCU critical section */
53
MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
54
- hwaddr *plen, bool is_write)
55
+ hwaddr *plen, bool is_write,
56
+ MemTxAttrs attrs)
57
{
58
MemoryRegion *mr;
59
MemoryRegionSection section;
60
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
61
}
62
63
l = len;
64
- mr = flatview_translate(fv, addr, &addr1, &l, true);
65
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
66
}
67
68
return result;
69
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
70
MemTxResult result = MEMTX_OK;
71
72
l = len;
73
- mr = flatview_translate(fv, addr, &addr1, &l, true);
74
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
75
result = flatview_write_continue(fv, addr, attrs, buf, len,
76
addr1, l, mr);
77
78
@@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
79
}
80
81
l = len;
82
- mr = flatview_translate(fv, addr, &addr1, &l, false);
83
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
84
}
85
86
return result;
87
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
88
MemoryRegion *mr;
89
90
l = len;
91
- mr = flatview_translate(fv, addr, &addr1, &l, false);
92
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
93
return flatview_read_continue(fv, addr, attrs, buf, len,
94
addr1, l, mr);
95
}
96
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
97
98
while (len > 0) {
99
l = len;
100
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
101
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
102
if (!memory_access_is_direct(mr, is_write)) {
103
l = memory_access_size(mr, l, addr);
104
if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
105
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
106
107
len = target_len;
108
this_mr = flatview_translate(fv, addr, &xlat,
109
- &len, is_write);
110
+ &len, is_write, attrs);
111
if (this_mr != mr || xlat != base + done) {
112
return done;
113
}
114
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
115
l = len;
116
rcu_read_lock();
117
fv = address_space_to_flatview(as);
118
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
119
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
120
121
if (!memory_access_is_direct(mr, is_write)) {
122
if (atomic_xchg(&bounce.in_use, true)) {
39
--
123
--
40
2.7.4
124
2.17.1
41
125
42
126
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_get_iotlb_entry().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
8
---
9
include/exec/memory.h | 2 +-
10
exec.c | 2 +-
11
hw/virtio/vhost.c | 3 ++-
12
3 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/include/exec/memory.h b/include/exec/memory.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/memory.h
17
+++ b/include/exec/memory.h
18
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
19
* entry. Should be called from an RCU critical section.
20
*/
21
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
22
- bool is_write);
23
+ bool is_write, MemTxAttrs attrs);
24
25
/* address_space_translate: translate an address range into an address space
26
* into a MemoryRegion and an address range into that section. Should be
27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
32
33
/* Called from RCU critical section */
34
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
35
- bool is_write)
36
+ bool is_write, MemTxAttrs attrs)
37
{
38
MemoryRegionSection section;
39
hwaddr xlat, page_mask;
40
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/virtio/vhost.c
43
+++ b/hw/virtio/vhost.c
44
@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
45
trace_vhost_iotlb_miss(dev, 1);
46
47
iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
48
- iova, write);
49
+ iova, write,
50
+ MEMTXATTRS_UNSPECIFIED);
51
if (iotlb.target_as != NULL) {
52
ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
53
&uaddr, &len);
54
--
55
2.17.1
56
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/17] hw/arm/exynos: Declare local variables in some order
[Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_do_translate().
2
3
3
Bring some more readability by declaring local function variables: first
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
initialized ones and then the rest (with reversed-christmas-tree order).
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
8
---
9
exec.c | 9 ++++++---
10
1 file changed, 6 insertions(+), 3 deletions(-)
5
11
6
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
12
diff --git a/exec.c b/exec.c
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/exynos4210.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4210.c
14
--- a/exec.c
16
+++ b/hw/arm/exynos4210.c
15
+++ b/exec.c
17
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
16
@@ -XXX,XX +XXX,XX @@ unassigned:
18
17
* @is_write: whether the translation operation is for write
19
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
18
* @is_mmio: whether this can be MMIO, set true if it can
19
* @target_as: the address space targeted by the IOMMU
20
+ * @attrs: memory transaction attributes
21
*
22
* This function is called from RCU critical section
23
*/
24
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
25
hwaddr *page_mask_out,
26
bool is_write,
27
bool is_mmio,
28
- AddressSpace **target_as)
29
+ AddressSpace **target_as,
30
+ MemTxAttrs attrs)
20
{
31
{
21
- int i, n;
32
MemoryRegionSection *section;
22
Exynos4210State *s = g_new(Exynos4210State, 1);
33
IOMMUMemoryRegion *iommu_mr;
23
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
34
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
24
- DeviceState *dev;
35
* but page mask.
25
SysBusDevice *busdev;
36
*/
26
ObjectClass *cpu_oc;
37
section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
27
+ DeviceState *dev;
38
- NULL, &page_mask, is_write, false, &as);
28
+ int i, n;
39
+ NULL, &page_mask, is_write, false, &as,
29
40
+ attrs);
30
cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
41
31
assert(cpu_oc);
42
/* Illegal translation */
43
if (section.mr == &io_mem_unassigned) {
44
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
45
46
/* This can be MMIO, so setup MMIO bit. */
47
section = flatview_do_translate(fv, addr, xlat, plen, NULL,
48
- is_write, true, &as);
49
+ is_write, true, &as, attrs);
50
mr = section.mr;
51
52
if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
32
--
53
--
33
2.7.4
54
2.17.1
34
55
35
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/17] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
[Qemu-devel] [PULL 22/25] Make address_space_translate_iommu take a MemTxAttrs argument
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_translate_iommu().
2
3
3
Statements under 'case' were in some places wrongly indented bringing
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
confusion and making the code less readable. Remove also few unneeded
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
blank lines. No functional changes.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
8
---
9
exec.c | 8 +++++---
10
1 file changed, 5 insertions(+), 3 deletions(-)
6
11
7
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
12
diff --git a/exec.c b/exec.c
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++-------------------------
13
1 file changed, 20 insertions(+), 25 deletions(-)
14
15
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/timer/exynos4210_mct.c
14
--- a/exec.c
18
+++ b/hw/timer/exynos4210_mct.c
15
+++ b/exec.c
19
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
16
@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
20
17
* @is_write: whether the translation operation is for write
21
case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
18
* @is_mmio: whether this can be MMIO, set true if it can
22
case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
19
* @target_as: the address space targeted by the IOMMU
23
- index = GET_G_COMP_IDX(offset);
20
+ * @attrs: transaction attributes
24
- shift = 8 * (offset & 0x4);
21
*
25
- value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
22
* This function is called from RCU critical section. It is the common
26
+ index = GET_G_COMP_IDX(offset);
23
* part of flatview_do_translate and address_space_translate_cached.
27
+ shift = 8 * (offset & 0x4);
24
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
28
+ value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
25
hwaddr *page_mask_out,
29
break;
26
bool is_write,
30
27
bool is_mmio,
31
case G_TCON:
28
- AddressSpace **target_as)
32
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
29
+ AddressSpace **target_as,
33
lt_i = GET_L_TIMER_IDX(offset);
30
+ MemTxAttrs attrs)
34
31
{
35
value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]);
32
MemoryRegionSection *section;
36
-
33
hwaddr page_mask = (hwaddr)-1;
37
break;
34
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
38
35
return address_space_translate_iommu(iommu_mr, xlat,
39
case L0_TCON: case L1_TCON:
36
plen_out, page_mask_out,
40
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
37
is_write, is_mmio,
41
38
- target_as);
42
case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
39
+ target_as, attrs);
43
case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
40
}
44
- index = GET_G_COMP_IDX(offset);
41
if (page_mask_out) {
45
- shift = 8 * (offset & 0x4);
42
/* Not behind an IOMMU, use default page size. */
46
- s->g_timer.reg.comp[index] =
43
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
47
- (s->g_timer.reg.comp[index] &
44
48
- (((uint64_t)UINT32_MAX << 32) >> shift)) +
45
section = address_space_translate_iommu(iommu_mr, xlat, plen,
49
- (value << shift);
46
NULL, is_write, true,
50
+ index = GET_G_COMP_IDX(offset);
47
- &target_as);
51
+ shift = 8 * (offset & 0x4);
48
+ &target_as, attrs);
52
+ s->g_timer.reg.comp[index] =
49
return section.mr;
53
+ (s->g_timer.reg.comp[index] &
50
}
54
+ (((uint64_t)UINT32_MAX << 32) >> shift)) +
55
+ (value << shift);
56
57
- DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
58
+ DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
59
60
- if (offset & 0x4) {
61
- s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
62
- } else {
63
- s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
64
- }
65
+ if (offset & 0x4) {
66
+ s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
67
+ } else {
68
+ s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
69
+ }
70
71
- exynos4210_gfrc_restart(s);
72
- break;
73
+ exynos4210_gfrc_restart(s);
74
+ break;
75
76
case G_TCON:
77
old_val = s->g_timer.reg.tcon;
78
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
79
break;
80
81
case G_INT_ENB:
82
-
83
/* Raise IRQ if transition from disabled to enabled and CSTAT pending */
84
for (i = 0; i < MCT_GT_CMP_NUM; i++) {
85
if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon &
86
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
87
break;
88
89
case L0_TCNTB: case L1_TCNTB:
90
-
91
lt_i = GET_L_TIMER_IDX(offset);
92
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
93
94
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
95
break;
96
97
case L0_ICNTB: case L1_ICNTB:
98
-
99
lt_i = GET_L_TIMER_IDX(offset);
100
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
101
102
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
103
if (icntb_max[lt_i] < value) {
104
icntb_max[lt_i] = value;
105
}
106
-DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
107
- lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
108
+ DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
109
+ lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
110
#endif
111
-break;
112
+ break;
113
114
case L0_FRCNTB: case L1_FRCNTB:
115
-
116
lt_i = GET_L_TIMER_IDX(offset);
117
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
118
51
119
--
52
--
120
2.7.4
53
2.17.1
121
54
122
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/17] hw/intc/arm_gicv3_its: Allow save/restore
[Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
1
From: Eric Auger <eric.auger@redhat.com>
1
Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
2
and friends.
2
3
3
We change the restoration priority of both the GICv3 and ITS. The
4
GICv3 must be restored before the ITS and the ITS needs to be restored
5
before PCIe devices since it translates their MSI transactions.
6
7
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
Reviewed-by: Juan Quintela <quintela@redhat.com>
9
Message-id: 1497023553-18411-5-git-send-email-eric.auger@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
11
---
7
---
12
include/migration/vmstate.h | 2 ++
8
include/migration/vmstate.h | 3 +++
13
hw/intc/arm_gicv3_common.c | 1 +
9
1 file changed, 3 insertions(+)
14
hw/intc/arm_gicv3_its_common.c | 2 +-
15
hw/intc/arm_gicv3_its_kvm.c | 24 ++++++++++++------------
16
4 files changed, 16 insertions(+), 13 deletions(-)
17
10
18
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
11
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
19
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
20
--- a/include/migration/vmstate.h
13
--- a/include/migration/vmstate.h
21
+++ b/include/migration/vmstate.h
14
+++ b/include/migration/vmstate.h
22
@@ -XXX,XX +XXX,XX @@ enum VMStateFlags {
15
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
23
typedef enum {
16
#define VMSTATE_BOOL_ARRAY(_f, _s, _n) \
24
MIG_PRI_DEFAULT = 0,
17
VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
25
MIG_PRI_IOMMU, /* Must happen before PCI devices */
18
26
+ MIG_PRI_GICV3_ITS, /* Must happen before PCI devices */
19
+#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num) \
27
+ MIG_PRI_GICV3, /* Must happen before the ITS */
20
+ VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
28
MIG_PRI_MAX,
29
} MigrationPriority;
30
31
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/intc/arm_gicv3_common.c
34
+++ b/hw/intc/arm_gicv3_common.c
35
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
36
.minimum_version_id = 1,
37
.pre_save = gicv3_pre_save,
38
.post_load = gicv3_post_load,
39
+ .priority = MIG_PRI_GICV3,
40
.fields = (VMStateField[]) {
41
VMSTATE_UINT32(gicd_ctlr, GICv3State),
42
VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
43
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/arm_gicv3_its_common.c
46
+++ b/hw/intc/arm_gicv3_its_common.c
47
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_its = {
48
.name = "arm_gicv3_its",
49
.pre_save = gicv3_its_pre_save,
50
.post_load = gicv3_its_post_load,
51
- .unmigratable = true,
52
+ .priority = MIG_PRI_GICV3_ITS,
53
.fields = (VMStateField[]) {
54
VMSTATE_UINT32(ctlr, GICv3ITSState),
55
VMSTATE_UINT32(iidr, GICv3ITSState),
56
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/arm_gicv3_its_kvm.c
59
+++ b/hw/intc/arm_gicv3_its_kvm.c
60
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
61
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
62
Error *local_err = NULL;
63
64
- /*
65
- * Block migration of a KVM GICv3 ITS device: the API for saving and
66
- * restoring the state in the kernel is not yet available
67
- */
68
- error_setg(&s->migration_blocker, "vITS migration is not implemented");
69
- migrate_add_blocker(s->migration_blocker, &local_err);
70
- if (local_err) {
71
- error_propagate(errp, local_err);
72
- error_free(s->migration_blocker);
73
- return;
74
- }
75
-
76
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
77
if (s->dev_fd < 0) {
78
error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
79
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
80
81
gicv3_its_init_mmio(s, NULL);
82
83
+ if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
84
+ GITS_CTLR)) {
85
+ error_setg(&s->migration_blocker, "This operating system kernel "
86
+ "does not support vITS migration");
87
+ migrate_add_blocker(s->migration_blocker, &local_err);
88
+ if (local_err) {
89
+ error_propagate(errp, local_err);
90
+ error_free(s->migration_blocker);
91
+ return;
92
+ }
93
+ }
94
+
21
+
95
kvm_msi_use_devid = true;
22
#define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v) \
96
kvm_gsi_direct_mapping = false;
23
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
97
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
24
98
--
25
--
99
2.7.4
26
2.17.1
100
27
101
28
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/17] timer/aspeed: fix timer enablement when a reload is not set
[Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
2
2
3
When a timer is enabled before a reload value is set, the controller
3
acpi_data_push uses g_array_set_size to resize the memory size. If there
4
waits for a reload value to be set before starting decrementing. This
4
is no enough contiguous memory, the address will be changed. So previous
5
fix tries to cover that case by changing the timer expiry only when
5
pointer could not be used any more. It must update the pointer and use
6
a reload value is valid.
6
the new one.
7
7
8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Also, previous codes wrongly use le32 conversion of iort->node_offset
9
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
9
for subsequent computations that will result incorrect value if host is
10
Message-id: 1496739312-32304-1-git-send-email-clg@kaod.org
10
not litlle endian. So use the non-converted one instead.
11
12
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
16
---
13
hw/timer/aspeed_timer.c | 37 +++++++++++++++++++++++++++++--------
17
hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
14
1 file changed, 29 insertions(+), 8 deletions(-)
18
1 file changed, 15 insertions(+), 5 deletions(-)
15
19
16
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
20
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/aspeed_timer.c
22
--- a/hw/arm/virt-acpi-build.c
19
+++ b/hw/timer/aspeed_timer.c
23
+++ b/hw/arm/virt-acpi-build.c
20
@@ -XXX,XX +XXX,XX @@ static uint64_t calculate_next(struct AspeedTimer *t)
24
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
21
next = seq[1];
25
AcpiIortItsGroup *its;
22
} else if (now < seq[2]) {
26
AcpiIortTable *iort;
23
next = seq[2];
27
AcpiIortSmmu3 *smmu;
24
- } else {
28
- size_t node_size, iort_length, smmu_offset = 0;
25
+ } else if (t->reload) {
29
+ size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
26
reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate);
30
AcpiIortRC *rc;
27
t->start = now - ((now - t->start) % reload_ns);
31
28
+ } else {
32
iort = acpi_data_push(table_data, sizeof(*iort));
29
+ /* no reload value, return 0 */
33
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
30
+ break;
34
31
}
35
iort_length = sizeof(*iort);
36
iort->node_count = cpu_to_le32(nb_nodes);
37
- iort->node_offset = cpu_to_le32(sizeof(*iort));
38
+ /*
39
+ * Use a copy in case table_data->data moves during acpi_data_push
40
+ * operations.
41
+ */
42
+ iort_node_offset = sizeof(*iort);
43
+ iort->node_offset = cpu_to_le32(iort_node_offset);
44
45
/* ITS group node */
46
node_size = sizeof(*its) + sizeof(uint32_t);
47
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
48
int irq = vms->irqmap[VIRT_SMMU];
49
50
/* SMMUv3 node */
51
- smmu_offset = iort->node_offset + node_size;
52
+ smmu_offset = iort_node_offset + node_size;
53
node_size = sizeof(*smmu) + sizeof(*idmap);
54
iort_length += node_size;
55
smmu = acpi_data_push(table_data, node_size);
56
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
57
idmap->id_count = cpu_to_le32(0xFFFF);
58
idmap->output_base = 0;
59
/* output IORT node is the ITS group node (the first node) */
60
- idmap->output_reference = cpu_to_le32(iort->node_offset);
61
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
32
}
62
}
33
63
34
return next;
64
/* Root Complex Node */
35
}
65
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
36
66
idmap->output_reference = cpu_to_le32(smmu_offset);
37
+static void aspeed_timer_mod(AspeedTimer *t)
67
} else {
38
+{
68
/* output IORT node is the ITS group node (the first node) */
39
+ uint64_t next = calculate_next(t);
69
- idmap->output_reference = cpu_to_le32(iort->node_offset);
40
+ if (next) {
70
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
41
+ timer_mod(&t->timer, next);
42
+ }
43
+}
44
+
45
static void aspeed_timer_expire(void *opaque)
46
{
47
AspeedTimer *t = opaque;
48
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_expire(void *opaque)
49
qemu_set_irq(t->irq, t->level);
50
}
71
}
51
72
52
- timer_mod(&t->timer, calculate_next(t));
73
+ /*
53
+ aspeed_timer_mod(t);
74
+ * Update the pointer address in case table_data->data moves during above
54
}
75
+ * acpi_data_push operations.
55
76
+ */
56
static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
77
+ iort = (AcpiIortTable *)(table_data->data + iort_start);
57
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
78
iort->length = cpu_to_le32(iort_length);
58
uint32_t value)
79
59
{
80
build_header(linker, table_data, (void *)(table_data->data + iort_start),
60
AspeedTimer *t;
61
+ uint32_t old_reload;
62
63
trace_aspeed_timer_set_value(timer, reg, value);
64
t = &s->timers[timer];
65
switch (reg) {
66
+ case TIMER_REG_RELOAD:
67
+ old_reload = t->reload;
68
+ t->reload = value;
69
+
70
+ /* If the reload value was not previously set, or zero, and
71
+ * the current value is valid, try to start the timer if it is
72
+ * enabled.
73
+ */
74
+ if (old_reload || !t->reload) {
75
+ break;
76
+ }
77
+
78
case TIMER_REG_STATUS:
79
if (timer_enabled(t)) {
80
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
81
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
82
uint32_t rate = calculate_rate(t);
83
84
t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
85
- timer_mod(&t->timer, calculate_next(t));
86
+ aspeed_timer_mod(t);
87
}
88
break;
89
- case TIMER_REG_RELOAD:
90
- t->reload = value;
91
- break;
92
case TIMER_REG_MATCH_FIRST:
93
case TIMER_REG_MATCH_SECOND:
94
t->match[reg - 2] = value;
95
if (timer_enabled(t)) {
96
- timer_mod(&t->timer, calculate_next(t));
97
+ aspeed_timer_mod(t);
98
}
99
break;
100
default:
101
@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable)
102
trace_aspeed_timer_ctrl_enable(t->id, enable);
103
if (enable) {
104
t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
105
- timer_mod(&t->timer, calculate_next(t));
106
+ aspeed_timer_mod(t);
107
} else {
108
timer_del(&t->timer);
109
}
110
--
81
--
111
2.7.4
82
2.17.1
112
83
113
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/17] kvm-all: Pass an error object to kvm_device_access
[Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
2
2
3
In some circumstances, we don't want to abort if the
3
kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
4
kvm_device_access fails. This will be the case during ITS
4
initialize global capability variables. If we call kvm_init_irq_routing in
5
migration, in case the ITS table save/restore fails because
5
GIC realize function, previous allocated memory will leak.
6
the guest did not program the vITS correctly. So let's pass an
7
error object to the function and return the ioctl value. New
8
callers will be able to make a decision upon this returned
9
value.
10
6
11
Existing callers pass &error_abort which will cause the
7
Fix this by deleting the unnecessary call.
12
function to abort on failure.
13
8
14
Signed-off-by: Eric Auger <eric.auger@redhat.com>
9
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
15
Reviewed-by: Juan Quintela <quintela@redhat.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
16
Reviewed-by: Peter Xu <peterx@redhat.com>
11
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
17
Message-id: 1497023553-18411-2-git-send-email-eric.auger@redhat.com
18
[PMM: wrapped long line]
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
13
---
21
include/sysemu/kvm.h | 11 +++++++----
14
hw/intc/arm_gic_kvm.c | 1 -
22
hw/intc/arm_gic_kvm.c | 9 +++++----
15
hw/intc/arm_gicv3_kvm.c | 1 -
23
hw/intc/arm_gicv3_its_kvm.c | 2 +-
16
2 files changed, 2 deletions(-)
24
hw/intc/arm_gicv3_kvm.c | 14 +++++++-------
25
kvm-all.c | 14 ++++++++------
26
5 files changed, 28 insertions(+), 22 deletions(-)
27
17
28
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/sysemu/kvm.h
31
+++ b/include/sysemu/kvm.h
32
@@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int fd, uint32_t group, uint64_t attr);
33
* @attr: the attribute of that group to set or get
34
* @val: pointer to a storage area for the value
35
* @write: true for set and false for get operation
36
+ * @errp: error object handle
37
*
38
- * This function is not allowed to fail. Use kvm_device_check_attr()
39
- * in order to check for the availability of optional attributes.
40
+ * Returns: 0 on success
41
+ * < 0 on error
42
+ * Use kvm_device_check_attr() in order to check for the availability
43
+ * of optional attributes.
44
*/
45
-void kvm_device_access(int fd, int group, uint64_t attr,
46
- void *val, bool write);
47
+int kvm_device_access(int fd, int group, uint64_t attr,
48
+ void *val, bool write, Error **errp);
49
50
/**
51
* kvm_create_device - create a KVM device for the device control API
52
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
18
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
53
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/intc/arm_gic_kvm.c
20
--- a/hw/intc/arm_gic_kvm.c
55
+++ b/hw/intc/arm_gic_kvm.c
21
+++ b/hw/intc/arm_gic_kvm.c
56
@@ -XXX,XX +XXX,XX @@ static void kvm_gicd_access(GICState *s, int offset, int cpu,
57
uint32_t *val, bool write)
58
{
59
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
60
- KVM_VGIC_ATTR(offset, cpu), val, write);
61
+ KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
62
}
63
64
static void kvm_gicc_access(GICState *s, int offset, int cpu,
65
uint32_t *val, bool write)
66
{
67
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
68
- KVM_VGIC_ATTR(offset, cpu), val, write);
69
+ KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
70
}
71
72
#define for_each_irq_reg(_ctr, _max_irq, _field_width) \
73
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
22
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
74
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
23
75
uint32_t numirqs = s->num_irq;
24
if (kvm_has_gsi_routing()) {
76
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0,
25
/* set up irq routing */
77
- &numirqs, true);
26
- kvm_init_irq_routing(kvm_state);
78
+ &numirqs, true, &error_abort);
27
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
28
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
79
}
29
}
80
/* Tell the kernel to complete VGIC initialization now */
81
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
82
KVM_DEV_ARM_VGIC_CTRL_INIT)) {
83
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
84
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
85
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
86
+ &error_abort);
87
}
88
} else if (ret != -ENODEV && ret != -ENOTSUP) {
89
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
90
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/hw/intc/arm_gicv3_its_kvm.c
93
+++ b/hw/intc/arm_gicv3_its_kvm.c
94
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
95
96
/* explicit init of the ITS */
97
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
98
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
99
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
100
101
/* register the base address */
102
kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
103
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
30
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
104
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
105
--- a/hw/intc/arm_gicv3_kvm.c
32
--- a/hw/intc/arm_gicv3_kvm.c
106
+++ b/hw/intc/arm_gicv3_kvm.c
33
+++ b/hw/intc/arm_gicv3_kvm.c
107
@@ -XXX,XX +XXX,XX @@ static inline void kvm_gicd_access(GICv3State *s, int offset,
108
{
109
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
110
KVM_VGIC_ATTR(offset, 0),
111
- val, write);
112
+ val, write, &error_abort);
113
}
114
115
static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
116
@@ -XXX,XX +XXX,XX @@ static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
117
{
118
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
119
KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
120
- val, write);
121
+ val, write, &error_abort);
122
}
123
124
static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
125
@@ -XXX,XX +XXX,XX @@ static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
126
{
127
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
128
KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
129
- val, write);
130
+ val, write, &error_abort);
131
}
132
133
static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
134
@@ -XXX,XX +XXX,XX @@ static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
135
KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
136
(VGIC_LEVEL_INFO_LINE_LEVEL <<
137
KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
138
- val, write);
139
+ val, write, &error_abort);
140
}
141
142
/* Loop through each distributor IRQ related register; since bits
143
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
144
/* Initialize to actual HW supported configuration */
145
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
146
KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
147
- &c->icc_ctlr_el1[GICV3_NS], false);
148
+ &c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
149
150
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
151
}
152
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
34
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
153
}
35
154
36
if (kvm_has_gsi_routing()) {
155
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
37
/* set up irq routing */
156
- 0, &s->num_irq, true);
38
- kvm_init_irq_routing(kvm_state);
157
+ 0, &s->num_irq, true, &error_abort);
39
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
158
40
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
159
/* Tell the kernel to complete VGIC initialization now */
41
}
160
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
161
- KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
162
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
163
164
kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
165
KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd);
166
diff --git a/kvm-all.c b/kvm-all.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/kvm-all.c
169
+++ b/kvm-all.c
170
@@ -XXX,XX +XXX,XX @@
171
#include "qemu/option.h"
172
#include "qemu/config-file.h"
173
#include "qemu/error-report.h"
174
+#include "qapi/error.h"
175
#include "hw/hw.h"
176
#include "hw/pci/msi.h"
177
#include "hw/pci/msix.h"
178
@@ -XXX,XX +XXX,XX @@ int kvm_device_check_attr(int dev_fd, uint32_t group, uint64_t attr)
179
return kvm_device_ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute) ? 0 : 1;
180
}
181
182
-void kvm_device_access(int fd, int group, uint64_t attr,
183
- void *val, bool write)
184
+int kvm_device_access(int fd, int group, uint64_t attr,
185
+ void *val, bool write, Error **errp)
186
{
187
struct kvm_device_attr kvmattr;
188
int err;
189
@@ -XXX,XX +XXX,XX @@ void kvm_device_access(int fd, int group, uint64_t attr,
190
write ? KVM_SET_DEVICE_ATTR : KVM_GET_DEVICE_ATTR,
191
&kvmattr);
192
if (err < 0) {
193
- error_report("KVM_%s_DEVICE_ATTR failed: %s",
194
- write ? "SET" : "GET", strerror(-err));
195
- error_printf("Group %d attr 0x%016" PRIx64 "\n", group, attr);
196
- abort();
197
+ error_setg_errno(errp, -err,
198
+ "KVM_%s_DEVICE_ATTR failed: Group %d "
199
+ "attr 0x%016" PRIx64,
200
+ write ? "SET" : "GET", group, attr);
201
}
202
+ return err;
203
}
204
205
/* Return 1 on success, 0 on failure */
206
--
42
--
207
2.7.4
43
2.17.1
208
44
209
45
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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