Series comparison

-[Qemu-devel] [PULL v2 00/25] target-arm queue
+[Qemu-devel] [PULL v2 00/23] target-arm queue
-Dropped the tmp421 patch and the following patch that
+v2: dropped patches that add the microbit nRF51 non-volatile memories
-depended on it; no other changes.
+and the test case for them.
 thanks
 -- PMM
-The following changes since commit 43771d5d92312504305c19abe29ec5bfabd55f01:
-  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-05-31' into staging (2017-06-01 16:39:16 +0100)
+The following changes since commit 3a183e330dbd7dbcac3841737ac874979552cca2:
-are available in the git repository at:
+  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging (2019-01-28 16:26:47 +0000)
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170602
+are available in the Git repository at:
-for you to fetch changes up to c7637c04be257968e6df30de961a6a23a0ac3dd8:
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190129
-  hw/arm/virt: fdt: generate distance-map when needed (2017-06-02 11:51:49 +0100)
+for you to fetch changes up to 46f5abc0a2566ac3dc954eeb62fd625f0eaca120:
   gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index (2019-01-29 11:46:06 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * virt: numa: provide ACPI distance info when needed
+ * Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f4a4)
- * aspeed: fix i2c controller bugs
+ * v8m: Ensure IDAU is respected if SAU is disabled
- * M profile: support MPU
+ * gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
- * gicv3: fix mishandling of BPR1, VBPR1
+ * exec.c: Use correct attrs in cpu_memory_rw_debug()
- * load_uboot_image: don't assume a full header read
+ * accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
- * libvixl: Correct build failures on NetBSD
+ * target/arm: Don't clear supported PMU events when initializing PMCEID1
  * memory: add memory_region_flush_rom_device()
  * microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
  * tests/microbit-test: extend testing of microbit devices
  * checkpatch: Don't emit spurious warnings about block comments
  * aspeed/smc: misc bug fixes
  * xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
  * xlnx-zynqmp: Realize cluster after putting RPUs in it
  * accel/tcg: Add cluster number to TCG TB hash so differently configured
    CPUs don't pick up cached TBs for the wrong kind of CPU
 ----------------------------------------------------------------
-Andrew Jones (3):
+Aaron Lindsay OS (1):
-      load_uboot_image: don't assume a full header read
+      target/arm: Don't clear supported PMU events when initializing PMCEID1
       hw/arm/virt-acpi-build: build SLIT when needed
       hw/arm/virt: fdt: generate distance-map when needed
 Cédric Le Goater (4):
-      aspeed/i2c: improve command handling
+      aspeed/smc: fix default read value
-      aspeed/i2c: handle LAST command under the RX command
+      aspeed/smc: define registers for all possible CS
-      aspeed/i2c: introduce a state machine
+      aspeed/smc: Add dummy data register
-      aspeed: add some I2C devices to the Aspeed machines
+      aspeed/smc: snoop SPI transfers to fake dummy cycles
-Kamil Rytarowski (1):
+Julia Suvorova (3):
-      libvixl: Correct build failures on NetBSD
+      tests/libqtest: Introduce qtest_init_with_serial()
       tests/microbit-test: Make test independent of global_qtest
       tests/microbit-test: Check nRF51 UART functionality
-Michael Davidsaver (4):
+Luc Michel (1):
-      armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
+      gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
       armv7m: Implement M profile default memory map
       armv7m: Classify faults as MemManage or BusFault
       arm: add MPU support to M profile CPUs
-Peter Maydell (12):
+Peter Maydell (8):
-      hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
+      exec.c: Use correct attrs in cpu_memory_rw_debug()
-      hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
+      accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
-      hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
+      checkpatch: Don't emit spurious warnings about block comments
-      arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
+      xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
-      arm: Add support for M profile CPUs having different MMU index semantics
+      hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
-      arm: Use different ARMMMUIdx values for M profile
+      qom/cpu: Add cluster_index to CPUState
-      arm: Clean up handling of no-MPU PMSA CPUs
+      accel/tcg: Add cluster number to TCG TB hash
-      arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
+      gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index
       arm: Don't let no-MPU PMSA cores write to SCTLR.M
       arm: Remove unnecessary check on cpu->pmsav7_dregion
       arm: All M profile cores are PMSA
       arm: Implement HFNMIENA support for M profile MPU
-Wei Huang (1):
+Richard Henderson (1):
-      target/arm: clear PMUVER field of AA64DFR0 when vPMU=off
+      target/arm: Fix validation of 32-bit address spaces for aa32
- disas/libvixl/Makefile.objs |   3 +
+Stefan Hajnoczi (3):
- target/arm/cpu.h            | 118 ++++++++++++++--
+      tests/microbit-test: add TWI stub device test
- target/arm/translate.h      |   2 +-
+      MAINTAINERS: update microbit ARM board files
- hw/arm/aspeed.c             |  27 ++++
+      memory: add memory_region_flush_rom_device()
  hw/arm/virt-acpi-build.c    |   4 +
  hw/arm/virt.c               |  21 +++
  hw/core/loader.c            |   3 +-
  hw/i2c/aspeed_i2c.c         |  65 +++++++--
  hw/intc/arm_gicv3_cpuif.c   |  50 ++++++-
  hw/intc/armv7m_nvic.c       | 104 ++++++++++++++
  target/arm/cpu.c            |  28 +++-
  target/arm/helper.c         | 338 ++++++++++++++++++++++++++++++--------------
  target/arm/machine.c        |   7 +-
  target/arm/op_helper.c      |   3 +-
  target/arm/translate-a64.c  |  18 ++-
  target/arm/translate.c      |  14 +-
 files changed, 648 insertions(+), 157 deletions(-)
+Steffen Görtz (1):
+      arm: Stub out NRF51 TWI magnetometer/accelerometer detection
+Thomas Roth (1):
+      target/arm: v8m: Ensure IDAU is respected if SAU is disabled
+ hw/i2c/Makefile.objs          |   1 +
+ include/exec/exec-all.h       |   4 +-
+ include/exec/memory.h         |  18 +++
+ include/hw/arm/nrf51.h        |   2 +
+ include/hw/arm/nrf51_soc.h    |   1 +
+ include/hw/cpu/cluster.h      |  24 +++
+ include/hw/i2c/microbit_i2c.h |  42 +++++
+ include/hw/ssi/aspeed_smc.h   |   3 +
+ include/qom/cpu.h             |   7 +
+ target/arm/cpu.h              |  11 +-
+ tests/libqtest.h              |  11 ++
+ accel/tcg/cpu-exec.c          |   3 +
+ accel/tcg/translate-all.c     |   3 +
+ accel/tcg/user-exec.c         |  66 ++++++--
+ exec.c                        |  19 ++-
+ gdbstub.c                     | 120 ++++++---------
+ hw/arm/microbit.c             |  16 ++
+ hw/arm/xlnx-zynqmp.c          |   9 +-
+ hw/cpu/cluster.c              |  46 ++++++
+ hw/i2c/microbit_i2c.c         | 127 +++++++++++++++
+ hw/ssi/aspeed_smc.c           | 128 ++++++++++++++-
+ qom/cpu.c                     |   1 +
+ target/arm/cpu.c              |   3 +-
+ target/arm/helper.c           |  67 ++++----
+ tests/libqtest.c              |  25 +++
+ tests/microbit-test.c         | 350 +++++++++++++++++++++++++++++-------------
+ MAINTAINERS                   |   8 +-
+ scripts/checkpatch.pl         |   2 +-
+files changed, 874 insertions(+), 243 deletions(-)
+ create mode 100644 include/hw/i2c/microbit_i2c.h
+ create mode 100644 hw/i2c/microbit_i2c.c

Dropped the tmp421 patch and the following patch that
depended on it; no other changes.

thanks
-- PMM

The following changes since commit 43771d5d92312504305c19abe29ec5bfabd55f01:

Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-05-31' into staging (2017-06-01 16:39:16 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170602

for you to fetch changes up to c7637c04be257968e6df30de961a6a23a0ac3dd8:

hw/arm/virt: fdt: generate distance-map when needed (2017-06-02 11:51:49 +0100)

----------------------------------------------------------------
target-arm queue:
 * virt: numa: provide ACPI distance info when needed
 * aspeed: fix i2c controller bugs
 * M profile: support MPU
 * gicv3: fix mishandling of BPR1, VBPR1
 * load_uboot_image: don't assume a full header read
 * libvixl: Correct build failures on NetBSD

----------------------------------------------------------------
Andrew Jones (3):
      load_uboot_image: don't assume a full header read
      hw/arm/virt-acpi-build: build SLIT when needed
      hw/arm/virt: fdt: generate distance-map when needed

Cédric Le Goater (4):
      aspeed/i2c: improve command handling
      aspeed/i2c: handle LAST command under the RX command
      aspeed/i2c: introduce a state machine
      aspeed: add some I2C devices to the Aspeed machines

Kamil Rytarowski (1):
      libvixl: Correct build failures on NetBSD

Michael Davidsaver (4):
      armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
      armv7m: Implement M profile default memory map
      armv7m: Classify faults as MemManage or BusFault
      arm: add MPU support to M profile CPUs

Peter Maydell (12):
      hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
      hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
      hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
      arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
      arm: Add support for M profile CPUs having different MMU index semantics
      arm: Use different ARMMMUIdx values for M profile
      arm: Clean up handling of no-MPU PMSA CPUs
      arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
      arm: Don't let no-MPU PMSA cores write to SCTLR.M
      arm: Remove unnecessary check on cpu->pmsav7_dregion
      arm: All M profile cores are PMSA
      arm: Implement HFNMIENA support for M profile MPU

Wei Huang (1):
      target/arm: clear PMUVER field of AA64DFR0 when vPMU=off

v2: dropped patches that add the microbit nRF51 non-volatile memories
and the test case for them.

thanks
-- PMM

The following changes since commit 3a183e330dbd7dbcac3841737ac874979552cca2:

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging (2019-01-28 16:26:47 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190129

for you to fetch changes up to 46f5abc0a2566ac3dc954eeb62fd625f0eaca120:

gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index (2019-01-29 11:46:06 +0000)

----------------------------------------------------------------
target-arm queue:
 * Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f4a4)
 * v8m: Ensure IDAU is respected if SAU is disabled
 * gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
 * exec.c: Use correct attrs in cpu_memory_rw_debug()
 * accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
 * target/arm: Don't clear supported PMU events when initializing PMCEID1
 * memory: add memory_region_flush_rom_device()
 * microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
 * tests/microbit-test: extend testing of microbit devices
 * checkpatch: Don't emit spurious warnings about block comments
 * aspeed/smc: misc bug fixes
 * xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
 * xlnx-zynqmp: Realize cluster after putting RPUs in it
 * accel/tcg: Add cluster number to TCG TB hash so differently configured
   CPUs don't pick up cached TBs for the wrong kind of CPU

----------------------------------------------------------------
Aaron Lindsay OS (1):
      target/arm: Don't clear supported PMU events when initializing PMCEID1

Cédric Le Goater (4):
      aspeed/smc: fix default read value
      aspeed/smc: define registers for all possible CS
      aspeed/smc: Add dummy data register
      aspeed/smc: snoop SPI transfers to fake dummy cycles

Julia Suvorova (3):
      tests/libqtest: Introduce qtest_init_with_serial()
      tests/microbit-test: Make test independent of global_qtest
      tests/microbit-test: Check nRF51 UART functionality

Luc Michel (1):
      gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0

Peter Maydell (8):
      exec.c: Use correct attrs in cpu_memory_rw_debug()
      accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
      checkpatch: Don't emit spurious warnings about block comments
      xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
      hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
      qom/cpu: Add cluster_index to CPUState
      accel/tcg: Add cluster number to TCG TB hash
      gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index

Richard Henderson (1):
      target/arm: Fix validation of 32-bit address spaces for aa32

Stefan Hajnoczi (3):
      tests/microbit-test: add TWI stub device test
      MAINTAINERS: update microbit ARM board files
      memory: add memory_region_flush_rom_device()

Steffen Görtz (1):
      arm: Stub out NRF51 TWI magnetometer/accelerometer detection

Thomas Roth (1):
      target/arm: v8m: Ensure IDAU is respected if SAU is disabled