Series comparison

-[Qemu-devel] [PULL 00/27] target-arm queue
+[Qemu-devel] [PULL 00/16] target-arm queue
-ARM pullreq; contains some patches that arrived while I
+The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
 was on holiday, plus the series I sent off before going
 away, which got reviewed while I was away.
-thanks
+  Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
 -- PMM
+are available in the Git repository at:
-The following changes since commit c077a998eb3fcae2d048e3baeb5bc592d30fddde:
+  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
-  Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20170531' into staging (2017-06-01 15:50:40 +0100)
+for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
-are available in the git repository at:
+  tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170601
 for you to fetch changes up to cdc58be430b0bdeaef282e2e70f8135ae531616d:
   hw/arm/virt: fdt: generate distance-map when needed (2017-06-01 17:27:07 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * virt: numa: provide ACPI distance info when needed
+ * Fix coverity nit in int_to_float code
- * aspeed: fix i2c controller bugs
+ * Don't set Invalid for float-to-int(MAXINT)
- * aspeed: add temperature sensor device
+ * Fix fp_status_f16 tininess before rounding
- * M profile: support MPU
+ * Add various missing insns from the v8.2-FP16 extension
- * gicv3: fix mishandling of BPR1, VBPR1
+ * Fix sqrt_f16 exception raising
- * load_uboot_image: don't assume a full header read
+ * sdcard: Correct CRC16 offset in sd_function_switch()
- * libvixl: Correct build failures on NetBSD
+ * tcg: Optionally log FPU state in TCG -d cpu logging
 ----------------------------------------------------------------
-Andrew Jones (3):
+Alex Bennée (5):
-      load_uboot_image: don't assume a full header read
+      fpu/softfloat: int_to_float ensure r fully initialised
-      hw/arm/virt-acpi-build: build SLIT when needed
+      target/arm: Implement FCMP for fp16
-      hw/arm/virt: fdt: generate distance-map when needed
+      target/arm: Implement FCSEL for fp16
       target/arm: Implement FMOV (immediate) for fp16
       target/arm: Fix sqrt_f16 exception raising
-Cédric Le Goater (6):
+Peter Maydell (3):
-      aspeed/i2c: improve command handling
+      fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
-      aspeed/i2c: handle LAST command under the RX command
+      target/arm: Fix fp_status_f16 tininess before rounding
-      aspeed/i2c: introduce a state machine
+      tcg: Optionally log FPU state in TCG -d cpu logging
       aspeed: add some I2C devices to the Aspeed machines
       hw/misc: add a TMP42{1,2,3} device model
       aspeed: add a temp sensor device on I2C bus 3
-Kamil Rytarowski (1):
+Philippe Mathieu-Daudé (1):
-      libvixl: Correct build failures on NetBSD
+      sdcard: Correct CRC16 offset in sd_function_switch()
-Michael Davidsaver (4):
+Richard Henderson (7):
-      armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
+      target/arm: Implement FMOV (general) for fp16
-      armv7m: Implement M profile default memory map
+      target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
-      armv7m: Classify faults as MemManage or BusFault
+      target/arm: Implement FCVT (scalar, integer) for fp16
-      arm: add MPU support to M profile CPUs
+      target/arm: Implement FCVT (scalar, fixed-point) for fp16
       target/arm: Introduce and use read_fp_hreg
       target/arm: Implement FP data-processing (2 source) for fp16
       target/arm: Implement FP data-processing (3 source) for fp16
-Peter Maydell (12):
+ include/qemu/log.h         |   1 +
-      hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
+ target/arm/helper-a64.h    |   2 +
-      hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
+ target/arm/helper.h        |   6 +
-      hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
+ accel/tcg/cpu-exec.c       |   9 +-
-      arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
+ fpu/softfloat.c            |   6 +-
-      arm: Add support for M profile CPUs having different MMU index semantics
+ hw/sd/sd.c                 |   2 +-
-      arm: Use different ARMMMUIdx values for M profile
+ target/arm/cpu.c           |   2 +
-      arm: Clean up handling of no-MPU PMSA CPUs
+ target/arm/helper-a64.c    |  10 ++
-      arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
+ target/arm/helper.c        |  38 +++-
-      arm: Don't let no-MPU PMSA cores write to SCTLR.M
+ target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
-      arm: Remove unnecessary check on cpu->pmsav7_dregion
+ util/log.c                 |   2 +
-      arm: All M profile cores are PMSA
+files changed, 428 insertions(+), 71 deletions(-)
       arm: Implement HFNMIENA support for M profile MPU
-Wei Huang (1):
-      target/arm: clear PMUVER field of AA64DFR0 when vPMU=off
- disas/libvixl/Makefile.objs     |   3 +
- hw/misc/Makefile.objs           |   1 +
- target/arm/cpu.h                | 118 ++++++++++--
- target/arm/translate.h          |   2 +-
- hw/arm/aspeed.c                 |  36 ++++
- hw/arm/virt-acpi-build.c        |   4 +
- hw/arm/virt.c                   |  21 +++
- hw/core/loader.c                |   3 +-
- hw/i2c/aspeed_i2c.c             |  65 ++++++-
- hw/intc/arm_gicv3_cpuif.c       |  50 ++++-
- hw/intc/armv7m_nvic.c           | 104 +++++++++++
- hw/misc/tmp421.c                | 401 ++++++++++++++++++++++++++++++++++++++++
- target/arm/cpu.c                |  28 ++-
- target/arm/helper.c             | 338 ++++++++++++++++++++++-----------
- target/arm/machine.c            |   7 +-
- target/arm/op_helper.c          |   3 +-
- target/arm/translate-a64.c      |  18 +-
- target/arm/translate.c          |  14 +-
- default-configs/arm-softmmu.mak |   1 +
-files changed, 1060 insertions(+), 157 deletions(-)
- create mode 100644 hw/misc/tmp421.c

-[Qemu-devel] [PULL 06/27] target/arm: clear PMUVER field of AA64DFR0 when vPMU=off
+[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
-From: Wei Huang <wei@redhat.com>
+From: Alex Bennée <alex.bennee@linaro.org>
-The PMUv3 driver of linux kernel (in arch/arm64/kernel/perf_event.c)
+Reported by Coverity (CID1390635). We ensure this for uint_to_float
-relies on the PMUVER field of id_aa64dfr0_el1 to decide if PMU support
+later on so we might as well mirror that.
 is present or not. This patch clears the PMUVER field under TCG mode
 when vPMU=off. Without it, PMUv3 will init insider guest VMs even
 with vPMU=off. This patch also removes a redundant line inside the
 if-statement.
-Signed-off-by: Wei Huang <wei@redhat.com>
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 1495123889-32301-1-git-send-email-wei@redhat.com
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c | 2 +-
+ fpu/softfloat.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/fpu/softfloat.c b/fpu/softfloat.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/fpu/softfloat.c
-+++ b/target/arm/cpu.c
++++ b/fpu/softfloat.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
-     }
+ static FloatParts int_to_float(int64_t a, float_status *status)
-     if (!cpu->has_pmu) {
+ {
--        cpu->has_pmu = false;
+-    FloatParts r;
-         unset_feature(env, ARM_FEATURE_PMU);
++    FloatParts r = {};
-+        cpu->id_aa64dfr0 &= ~0xf00;
+     if (a == 0) {
-     }
+         r.cls = float_class_zero;
+         r.sign = false;
      if (!arm_feature(env, ARM_FEATURE_EL2)) {
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 27/27] hw/arm/virt: fdt: generate distance-map when needed
+[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
-From: Andrew Jones <drjones@redhat.com>
+In float-to-integer conversion, if the floating point input
 converts exactly to the largest or smallest integer that
 fits in to the result type, this is not an overflow.
 In this situation we were producing the correct result value,
 but were incorrectly setting the Invalid flag.
 For example for Arm A64, "FCVTAS w0, d0" on an input of
 x41dfffffffc00000 should produce 0x7fffffff and set no flags.
-This is based on patch Shannon Zhao originally posted.
+Fix the boundary case to take the right half of the if()
 statements.
-Cc: Shannon Zhao <zhaoshenglong@huawei.com>
+This fixes a regression from 2.11 introduced by the softfloat
-Signed-off-by: Andrew Jones <drjones@redhat.com>
+refactoring.
-Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
-Message-id: 20170529173751.3443-3-drjones@redhat.com
+Cc: qemu-stable@nongnu.org
 Fixes: ab52f973a50
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
 ---
- hw/arm/virt.c | 21 +++++++++++++++++++++
+ fpu/softfloat.c | 4 ++--
-file changed, 21 insertions(+)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/fpu/softfloat.c b/fpu/softfloat.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/fpu/softfloat.c
-+++ b/hw/arm/virt.c
++++ b/fpu/softfloat.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
-                                 "clk24mhz");
+             r = UINT64_MAX;
-     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
+         }
+         if (p.sign) {
-+    if (have_numa_distance) {
+-            if (r < -(uint64_t) min) {
-+        int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
++            if (r <= -(uint64_t) min) {
-+        uint32_t *matrix = g_malloc0(size);
+                 return -r;
-+        int idx, i, j;
+             } else {
-+
+                 s->float_exception_flags = orig_flags | float_flag_invalid;
-+        for (i = 0; i < nb_numa_nodes; i++) {
+                 return min;
-+            for (j = 0; j < nb_numa_nodes; j++) {
+             }
-+                idx = (i * nb_numa_nodes + j) * 3;
+         } else {
-+                matrix[idx + 0] = cpu_to_be32(i);
+-            if (r < max) {
-+                matrix[idx + 1] = cpu_to_be32(j);
++            if (r <= max) {
-+                matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
+                 return r;
-+            }
+             } else {
-+        }
+                 s->float_exception_flags = orig_flags | float_flag_invalid;
 +
 +        qemu_fdt_add_subnode(fdt, "/distance-map");
 +        qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
 +                                "numa-distance-map-v1");
 +        qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
 +                         matrix, size);
 +        g_free(matrix);
 +    }
  }
  static void fdt_add_psci_node(const VirtMachineState *vms)
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 16/27] arm: All M profile cores are PMSA
+[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
-All M profile CPUs are PMSA, so set the feature bit.
+In commit d81ce0ef2c4f105 we added an extra float_status field
-(We haven't actually implemented the M profile MPU register
+fp_status_fp16 for Arm, but forgot to initialize it correctly
-interface yet, but setting this feature bit gives us closer
+by setting it to float_tininess_before_rounding. This currently
-to correct behaviour for the MPU-disabled case.)
+will only cause problems for the new V8_FP16 feature, since the
 float-to-float conversion code doesn't use it yet. The effect
 would be that we failed to set the Underflow IEEE exception flag
 in all the cases where we should.
+Add the missing initialization.
+Fixes: d81ce0ef2c4f105
+Cc: qemu-stable@nongnu.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
 Message-id: 1493122030-32191-11-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/cpu.c | 8 ++++++++
+ target/arm/cpu.c | 2 ++
-file changed, 8 insertions(+)
+file changed, 2 insertions(+)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
- {
+                               &env->vfp.fp_status);
-     ARMCPU *cpu = ARM_CPU(obj);
+     set_float_detect_tininess(float_tininess_before_rounding,
+                               &env->vfp.standard_fp_status);
-+    /* M profile implies PMSA. We have to do this here rather than
++    set_float_detect_tininess(float_tininess_before_rounding,
-+     * in realize with the other feature-implication checks because
++                              &env->vfp.fp_status_f16);
-+     * we look at the PMSA bit to see if we should add some properties.
+ #ifndef CONFIG_USER_ONLY
-+     */
+     if (kvm_enabled()) {
-+    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
+         kvm_arm_reset_vcpu(cpu);
 +        set_feature(&cpu->env, ARM_FEATURE_PMSA);
 +    }
 +
      if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
          arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
          qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 15/27] armv7m: Implement M profile default memory map
+[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
-From: Michael Davidsaver <mdavidsaver@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Add support for the M profile default memory map which is used
+Adding the fp16 moves to/from general registers.
 if the MPU is not present or disabled.
-The main differences in behaviour from implementing this
+Cc: qemu-stable@nongnu.org
-correctly are that we set the PAGE_EXEC attribute on
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-the right regions of memory, such that device regions
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
-are not executable.
+Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
 Message-id: 1493122030-32191-10-git-send-email-peter.maydell@linaro.org
 [PMM: rephrased comment and commit message; don't mark
  the flash memory region as not-writable; list all
  the cases in the default map explicitly rather than
  using a 'default' case for the non-executable regions]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 41 ++++++++++++++++++++++++++++++++---------
+ target/arm/translate-a64.c | 21 +++++++++++++++++++++
-file changed, 32 insertions(+), 9 deletions(-)
+file changed, 21 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/translate-a64.c
-+++ b/target/arm/helper.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
-                                                 ARMMMUIdx mmu_idx,
+             tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
-                                                 int32_t address, int *prot)
+             clear_vec_high(s, true, rd);
- {
+             break;
--    *prot = PAGE_READ | PAGE_WRITE;
++        case 3:
--    switch (address) {
++            /* 16 bit */
--    case 0xF0000000 ... 0xFFFFFFFF:
++            tmp = tcg_temp_new_i64();
--        if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
++            tcg_gen_ext16u_i64(tmp, tcg_rn);
-+    if (!arm_feature(env, ARM_FEATURE_M)) {
++            write_fp_dreg(s, rd, tmp);
-+        *prot = PAGE_READ | PAGE_WRITE;
++            tcg_temp_free_i64(tmp);
 +        switch (address) {
 +        case 0xF0000000 ... 0xFFFFFFFF:
 +            if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
 +                /* hivecs execing is ok */
 +                *prot |= PAGE_EXEC;
 +            }
 +            break;
 +        case 0x00000000 ... 0x7FFFFFFF:
              *prot |= PAGE_EXEC;
 +            break;
 +        }
 +    } else {
 +        /* Default system address map for M profile cores.
 +         * The architecture specifies which regions are execute-never;
 +         * at the MPU level no other checks are defined.
 +         */
 +        switch (address) {
 +        case 0x00000000 ... 0x1fffffff: /* ROM */
 +        case 0x20000000 ... 0x3fffffff: /* SRAM */
 +        case 0x60000000 ... 0x7fffffff: /* RAM */
 +        case 0x80000000 ... 0x9fffffff: /* RAM */
 +            *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 +            break;
 +        case 0x40000000 ... 0x5fffffff: /* Peripheral */
 +        case 0xa0000000 ... 0xbfffffff: /* Device */
 +        case 0xc0000000 ... 0xdfffffff: /* Device */
 +        case 0xe0000000 ... 0xffffffff: /* System */
 +            *prot = PAGE_READ | PAGE_WRITE;
 +            break;
 +        default:
 +            g_assert_not_reached();
          }
--        break;
+     } else {
--    case 0x00000000 ... 0x7FFFFFFF:
+         TCGv_i64 tcg_rd = cpu_reg(s, rd);
--        *prot |= PAGE_EXEC;
+@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
--        break;
+             /* 64 bits from top half */
              tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
              break;
 +        case 3:
 +            /* 16 bit */
 +            tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
 +            break;
 +        default:
 +            g_assert_not_reached();
          }
      }
--
  }
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
- static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
+         case 0xa: /* 64 bit */
          case 0xd: /* 64 bit to top half of quad */
              break;
 +        case 0x6: /* 16-bit float, 32-bit int */
 +        case 0xe: /* 16-bit float, 64-bit int */
 +            if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +                break;
 +            }
 +            /* fallthru */
          default:
              /* all other sf/type/rmode combinations are invalid */
              unallocated_encoding(s);
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 01/27] libvixl: Correct build failures on NetBSD
+[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
-From: Kamil Rytarowski <n54@gmx.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Ensure that C99 macros are defined regardless of the inclusion order of
+No sense in emitting code after the exception.
 headers in vixl. This is required at least on NetBSD.
-The vixl/globals.h headers defines __STDC_CONSTANT_MACROS and must be
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-included before other system headers.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
 This file defines unconditionally the following macros, without altering
 the original sources:
  - __STDC_CONSTANT_MACROS
  - __STDC_LIMIT_MACROS
  - __STDC_FORMAT_MACROS
 Signed-off-by: Kamil Rytarowski <n54@gmx.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20170514051820.15985-1-n54@gmx.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- disas/libvixl/Makefile.objs | 3 +++
+ target/arm/translate-a64.c | 2 +-
-file changed, 3 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/disas/libvixl/Makefile.objs b/disas/libvixl/Makefile.objs
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/disas/libvixl/Makefile.objs
+--- a/target/arm/translate-a64.c
-+++ b/disas/libvixl/Makefile.objs
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ libvixl_OBJS = vixl/utils.o \
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
- # The -Wno-sign-compare is needed only for gcc 4.6, which complains about
+         default:
- # some signed-unsigned equality comparisons which later gcc versions do not.
+             /* all other sf/type/rmode combinations are invalid */
- $(addprefix $(obj)/,$(libvixl_OBJS)): QEMU_CFLAGS := -I$(SRC_PATH)/disas/libvixl $(QEMU_CFLAGS) -Wno-sign-compare
+             unallocated_encoding(s);
-+# Ensure that C99 macros are defined regardless of the inclusion order of
+-            break;
-+# headers in vixl. This is required at least on NetBSD.
++            return;
-+$(addprefix $(obj)/,$(libvixl_OBJS)): QEMU_CFLAGS += -D__STDC_CONSTANT_MACROS -D__STDC_LIMIT_MACROS -D__STDC_FORMAT_MACROS
+         }
- common-obj-$(CONFIG_ARM_A64_DIS) += $(libvixl_OBJS)
+         if (!fp_access_check(s)) {
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 14/27] armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
+[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
-From: Michael Davidsaver <mdavidsaver@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Improve the "-d mmu" tracing for the PMSAv7 MPU translation
+Cc: qemu-stable@nongnu.org
-process as an aid in debugging guest MPU configurations:
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
- * fix a missing newline for a guest-error log
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
- * report the region number with guest-error or unimp
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
-   logs of bad region register values
+Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
  * add a log message for the overall result of the lookup
  * print "0x" prefix for hex values
 Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 1493122030-32191-9-git-send-email-peter.maydell@linaro.org
 [PMM: a little tidyup, report region number in all messages
  rather than just one]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 39 +++++++++++++++++++++++++++------------
+ target/arm/helper.h        |  6 +++
-file changed, 27 insertions(+), 12 deletions(-)
+ target/arm/helper.c        | 38 ++++++++++++++-
+ target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
 files changed, 122 insertions(+), 18 deletions(-)
 diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.h
 +++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
  DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
  DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
  DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
 +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
 +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
 +DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
 +DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
  DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
  DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
  DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
  DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
  DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
  DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
 +DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
 +DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
  DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
  DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
+@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
-             }
+ #undef VFP_CONV_FIX_A64
-             if (!rsize) {
+ /* Conversion to/from f16 can overflow to infinity before/after scaling.
--                qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
+- * Therefore we convert to f64 (which does not round), scale,
-+                qemu_log_mask(LOG_GUEST_ERROR,
+- * and then convert f64 to f16 (which may round).
-+                              "DRSR[%d]: Rsize field cannot be 0\n", n);
++ * Therefore we convert to f64, scale, and then convert f64 to f16; or
-                 continue;
++ * vice versa for conversion to integer.
-             }
++ *
-             rsize++;
++ * For 16- and 32-bit integers, the conversion to f64 never rounds.
-             rmask = (1ull << rsize) - 1;
++ * For 64-bit integers, any integer that would cause rounding will also
++ * overflow to f16 infinity, so there is no double rounding problem.
-             if (base & rmask) {
+  */
--                qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
--                              "to DRSR region size, mask = %" PRIx32,
+ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
--                              base, rmask);
+@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
-+                qemu_log_mask(LOG_GUEST_ERROR,
+     return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
-+                              "DRBAR[%d]: 0x%" PRIx32 " misaligned "
+ }
-+                              "to DRSR region size, mask = 0x%" PRIx32 "\n",
-+                              n, base, rmask);
++float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
-                 continue;
++{
-             }
++    return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
++}
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
++
 +float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +{
 +    return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
 +}
 +
  static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
  {
      if (unlikely(float16_is_any_nan(f))) {
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
      return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 +uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
 +{
 +    return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
 +}
 +
 +uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
 +{
 +    return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
 +}
 +
 +uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
 +{
 +    return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
 +}
 +
 +uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
 +{
 +    return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
 +}
 +
  /* Set the current fp rounding mode and return the old one.
   * The argument is a softfloat float_round_ value.
   */
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
                             bool itof, int rmode, int scale, int sf, int type)
  {
      bool is_signed = !(opcode & 1);
 -    bool is_double = type;
      TCGv_ptr tcg_fpstatus;
 -    TCGv_i32 tcg_shift;
 +    TCGv_i32 tcg_shift, tcg_single;
 +    TCGv_i64 tcg_double;
 -    tcg_fpstatus = get_fpstatus_ptr(false);
 +    tcg_fpstatus = get_fpstatus_ptr(type == 3);
      tcg_shift = tcg_const_i32(64 - scale);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
              tcg_int = tcg_extend;
          }
 -        if (is_double) {
 -            TCGv_i64 tcg_double = tcg_temp_new_i64();
 +        switch (type) {
 +        case 1: /* float64 */
 +            tcg_double = tcg_temp_new_i64();
              if (is_signed) {
                  gen_helper_vfp_sqtod(tcg_double, tcg_int,
                                       tcg_shift, tcg_fpstatus);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
              }
              write_fp_dreg(s, rd, tcg_double);
              tcg_temp_free_i64(tcg_double);
 -        } else {
 -            TCGv_i32 tcg_single = tcg_temp_new_i32();
 +            break;
 +
 +        case 0: /* float32 */
 +            tcg_single = tcg_temp_new_i32();
              if (is_signed) {
                  gen_helper_vfp_sqtos(tcg_single, tcg_int,
                                       tcg_shift, tcg_fpstatus);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
              }
              write_fp_sreg(s, rd, tcg_single);
              tcg_temp_free_i32(tcg_single);
 +            break;
 +
 +        case 3: /* float16 */
 +            tcg_single = tcg_temp_new_i32();
 +            if (is_signed) {
 +                gen_helper_vfp_sqtoh(tcg_single, tcg_int,
 +                                     tcg_shift, tcg_fpstatus);
 +            } else {
 +                gen_helper_vfp_uqtoh(tcg_single, tcg_int,
 +                                     tcg_shift, tcg_fpstatus);
 +            }
 +            write_fp_sreg(s, rd, tcg_single);
 +            tcg_temp_free_i32(tcg_single);
 +            break;
 +
 +        default:
 +            g_assert_not_reached();
          }
      } else {
          TCGv_i64 tcg_int = cpu_reg(s, rd);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
          gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
 -        if (is_double) {
 -            TCGv_i64 tcg_double = read_fp_dreg(s, rn);
 +        switch (type) {
 +        case 1: /* float64 */
 +            tcg_double = read_fp_dreg(s, rn);
              if (is_signed) {
                  if (!sf) {
                      gen_helper_vfp_tosld(tcg_int, tcg_double,
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
                                           tcg_shift, tcg_fpstatus);
                  }
              }
-             if (rsize < TARGET_PAGE_BITS) {
++            if (!sf) {
--                qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
++                tcg_gen_ext32u_i64(tcg_int, tcg_int);
-+                qemu_log_mask(LOG_UNIMP,
++            }
-+                              "DRSR[%d]: No support for MPU (sub)region "
+             tcg_temp_free_i64(tcg_double);
-                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
+-        } else {
--                              rsize, TARGET_PAGE_BITS);
+-            TCGv_i32 tcg_single = read_fp_sreg(s, rn);
-+                              n, rsize, TARGET_PAGE_BITS);
++            break;
-                 continue;
++
-             }
++        case 0: /* float32 */
-             if (srdis) {
++            tcg_single = read_fp_sreg(s, rn);
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
+             if (sf) {
-                     break;
+                 if (is_signed) {
-                 default:
+                     gen_helper_vfp_tosqs(tcg_int, tcg_single,
-                     qemu_log_mask(LOG_GUEST_ERROR,
+@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
--                                  "Bad value for AP bits in DRACR %"
+                 tcg_temp_free_i32(tcg_dest);
--                                  PRIx32 "\n", ap);
+             }
-+                                  "DRACR[%d]: Bad value for AP bits: 0x%"
+             tcg_temp_free_i32(tcg_single);
-+                                  PRIx32 "\n", n, ap);
++            break;
-                 }
++
-             } else { /* Priv. mode AP bits decoding */
++        case 3: /* float16 */
-                 switch (ap) {
++            tcg_single = read_fp_sreg(s, rn);
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
++            if (sf) {
-                     break;
++                if (is_signed) {
-                 default:
++                    gen_helper_vfp_tosqh(tcg_int, tcg_single,
-                     qemu_log_mask(LOG_GUEST_ERROR,
++                                         tcg_shift, tcg_fpstatus);
--                                  "Bad value for AP bits in DRACR %"
++                } else {
--                                  PRIx32 "\n", ap);
++                    gen_helper_vfp_touqh(tcg_int, tcg_single,
-+                                  "DRACR[%d]: Bad value for AP bits: 0x%"
++                                         tcg_shift, tcg_fpstatus);
-+                                  PRIx32 "\n", n, ap);
++                }
-                 }
++            } else {
-             }
++                TCGv_i32 tcg_dest = tcg_temp_new_i32();
++                if (is_signed) {
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
++                    gen_helper_vfp_toslh(tcg_dest, tcg_single,
-      */
++                                         tcg_shift, tcg_fpstatus);
-     if (arm_feature(env, ARM_FEATURE_PMSA) &&
++                } else {
-         arm_feature(env, ARM_FEATURE_V7)) {
++                    gen_helper_vfp_toulh(tcg_dest, tcg_single,
-+        bool ret;
++                                         tcg_shift, tcg_fpstatus);
-         *page_size = TARGET_PAGE_SIZE;
++                }
--        return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
++                tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
--                                    phys_ptr, prot, fsr);
++                tcg_temp_free_i32(tcg_dest);
-+        ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
++            }
-+                                   phys_ptr, prot, fsr);
++            tcg_temp_free_i32(tcg_single);
-+        qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32
++            break;
-+                      " mmu_idx %u -> %s (prot %c%c%c)\n",
++
-+                      access_type == 1 ? "reading" :
++        default:
-+                      (access_type == 2 ? "writing" : "execute"),
++            g_assert_not_reached();
-+                      (uint32_t)address, mmu_idx,
+         }
-+                      ret ? "Miss" : "Hit",
-+                      *prot & PAGE_READ ? 'r' : '-',
+         gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
-+                      *prot & PAGE_WRITE ? 'w' : '-',
+         tcg_temp_free_i32(tcg_rmode);
-+                      *prot & PAGE_EXEC ? 'x' : '-');
+-
-+
+-        if (!sf) {
-+        return ret;
+-            tcg_gen_ext32u_i64(tcg_int, tcg_int);
 -        }
      }
-     if (regime_translation_disabled(env, mmu_idx)) {
+     tcg_temp_free_ptr(tcg_fpstatus);
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
          /* actual FP conversions */
          bool itof = extract32(opcode, 1, 1);
 -        if (type > 1 || (rmode != 0 && opcode > 1)) {
 +        if (rmode != 0 && opcode > 1) {
 +            unallocated_encoding(s);
 +            return;
 +        }
 +        switch (type) {
 +        case 0: /* float32 */
 +        case 1: /* float64 */
 +            break;
 +        case 3: /* float16 */
 +            if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +                break;
 +            }
 +            /* fallthru */
 +        default:
              unallocated_encoding(s);
              return;
          }
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 26/27] hw/arm/virt-acpi-build: build SLIT when needed
+[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
-From: Andrew Jones <drjones@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Cc: Shannon Zhao <zhaoshenglong@huawei.com>
+Cc: qemu-stable@nongnu.org
-Signed-off-by: Andrew Jones <drjones@redhat.com>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Igor Mammedov <imammedo@redhat.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20170529173751.3443-2-drjones@redhat.com
+Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt-acpi-build.c | 4 ++++
+ target/arm/translate-a64.c | 17 +++++++++++++++--
-file changed, 4 insertions(+)
+file changed, 15 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt-acpi-build.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/arm/virt-acpi-build.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
-     if (nb_numa_nodes > 0) {
+     bool sf = extract32(insn, 31, 1);
-         acpi_add_table(table_offsets, tables_blob);
+     bool itof;
-         build_srat(tables_blob, tables->linker, vms);
-+        if (have_numa_distance) {
+-    if (sbit || (type > 1)
-+            acpi_add_table(table_offsets, tables_blob);
+-        || (!sf && scale < 32)) {
-+            build_slit(tables_blob, tables->linker);
++    if (sbit || (!sf && scale < 32)) {
 +        unallocated_encoding(s);
 +        return;
 +    }
 +
 +    switch (type) {
 +    case 0: /* float32 */
 +    case 1: /* float64 */
 +        break;
 +    case 3: /* float16 */
 +        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +            break;
 +        }
++        /* fallthru */
++    default:
+         unallocated_encoding(s);
+         return;
      }
-     if (its_class_name() && !vmc->no_its) {
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 22/27] aspeed/i2c: introduce a state machine
+[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
-From: Cédric Le Goater <clg@kaod.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-The Aspeed I2C controller maintains a state machine in the command
+Cc: qemu-stable@nongnu.org
-register, which is mostly used for debug.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Let's start adding a few states to handle abnormal STOP
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
-commands. Today, the model uses the busy status of the bus as a
+Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
 condition to do so but it is not precise enough.
 Also remove the ABNORMAL bit for failing TX commands. This is
 incorrect with respect to the specs.
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 1494827476-1487-4-git-send-email-clg@kaod.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/i2c/aspeed_i2c.c | 36 +++++++++++++++++++++++++++++++++---
+ target/arm/translate-a64.c | 30 ++++++++++++++----------------
-file changed, 33 insertions(+), 3 deletions(-)
+file changed, 14 insertions(+), 16 deletions(-)
-diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/aspeed_i2c.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/i2c/aspeed_i2c.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
-     }
+     return v;
  }
-+static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
++static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
 +{
-+    bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);
++    TCGv_i32 v = tcg_temp_new_i32();
-+    bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;
++
 +    tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
 +    return v;
 +}
 +
-+static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
+ /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
-+{
+  * If SVE is not enabled, then there are only 128 bits in the vector.
-+    return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
+  */
-+}
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
-+
+ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
 +/*
 + * The state machine needs some refinement. It is only used to track
 + * invalid STOP commands for the moment.
 + */
  static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
  {
-     bus->cmd &= ~0xFFFF;
+     TCGv_ptr fpst = NULL;
-@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
+-    TCGv_i32 tcg_op = tcg_temp_new_i32();
-     bus->intr_status = 0;
++    TCGv_i32 tcg_op = read_fp_hreg(s, rn);
+     TCGv_i32 tcg_res = tcg_temp_new_i32();
-     if (bus->cmd & I2CD_M_START_CMD) {
-+        uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
+-    read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-+            I2CD_MSTARTR : I2CD_MSTART;
+-
-+
+     switch (opcode) {
-+        aspeed_i2c_set_state(bus, state);
+     case 0x0: /* FMOV */
-+
+         tcg_gen_mov_i32(tcg_res, tcg_op);
-         if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
+@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
-                                extract32(bus->buf, 0, 1))) {
+         tcg_temp_free_i64(tcg_op2);
-             bus->intr_status |= I2CD_INTR_TX_NAK;
+         tcg_temp_free_i64(tcg_res);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
+     } else {
-         if (!i2c_bus_busy(bus->bus)) {
+-        TCGv_i32 tcg_op1 = tcg_temp_new_i32();
-             return;
+-        TCGv_i32 tcg_op2 = tcg_temp_new_i32();
-         }
++        TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
-+        aspeed_i2c_set_state(bus, I2CD_MACTIVE);
++        TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
          TCGv_i64 tcg_res = tcg_temp_new_i64();
 -        read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
 -        read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
 -
          gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
          gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
      fpst = get_fpstatus_ptr(true);
 -    tcg_op1 = tcg_temp_new_i32();
 -    tcg_op2 = tcg_temp_new_i32();
 +    tcg_op1 = read_fp_hreg(s, rn);
 +    tcg_op2 = read_fp_hreg(s, rm);
      tcg_res = tcg_temp_new_i32();
 -    read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
 -    read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
 -
      switch (fpopcode) {
      case 0x03: /* FMULX */
          gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
      }
-     if (bus->cmd & I2CD_M_TX_CMD) {
+     if (is_scalar) {
-+        aspeed_i2c_set_state(bus, I2CD_MTXD);
+-        TCGv_i32 tcg_op = tcg_temp_new_i32();
-         if (i2c_send(bus->bus, bus->buf)) {
++        TCGv_i32 tcg_op = read_fp_hreg(s, rn);
--            bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
+         TCGv_i32 tcg_res = tcg_temp_new_i32();
-+            bus->intr_status |= (I2CD_INTR_TX_NAK);
-             i2c_end_transfer(bus->bus);
+-        read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-         } else {
+-
-             bus->intr_status |= I2CD_INTR_TX_ACK;
+         switch (fpop) {
-         }
+         case 0x1a: /* FCVTNS */
-         bus->cmd &= ~I2CD_M_TX_CMD;
+         case 0x1b: /* FCVTMS */
 +        aspeed_i2c_set_state(bus, I2CD_MACTIVE);
      }
      if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
 -        int ret = i2c_recv(bus->bus);
 +        int ret;
 +
 +        aspeed_i2c_set_state(bus, I2CD_MRXD);
 +        ret = i2c_recv(bus->bus);
          if (ret < 0) {
              qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
              ret = 0xff;
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
              i2c_nack(bus->bus);
          }
          bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
 +        aspeed_i2c_set_state(bus, I2CD_MACTIVE);
      }
      if (bus->cmd & I2CD_M_STOP_CMD) {
 -        if (!i2c_bus_busy(bus->bus)) {
 +        if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
 +            qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
              bus->intr_status |= I2CD_INTR_ABNORMAL;
          } else {
 +            aspeed_i2c_set_state(bus, I2CD_MSTOP);
              i2c_end_transfer(bus->bus);
              bus->intr_status |= I2CD_INTR_NORMAL_STOP;
          }
          bus->cmd &= ~I2CD_M_STOP_CMD;
 +        aspeed_i2c_set_state(bus, I2CD_IDLE);
      }
  }
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 18/27] arm: add MPU support to M profile CPUs
+[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
-From: Michael Davidsaver <mdavidsaver@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-The M series MPU is almost the same as the already implemented R
+We missed all of the scalar fp16 binary operations.
 profile MPU (v7 PMSA).  So all we need to implement here is the MPU
 register interface in the system register space.
-This implementation has the same restriction as the R profile MPU
+Cc: qemu-stable@nongnu.org
-that it doesn't permit regions to be sized down smaller than 1K.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-We also do not yet implement support for MPU_CTRL.HFNMIENA; this
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
-bit should if zero disable use of the MPU when running HardFault,
+Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
 NMI or with FAULTMASK set to 1 (ie at an execution priority of
 less than zero) -- if the MPU is enabled we don't treat these
 cases any differently.
 Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
 Message-id: 1493122030-32191-13-git-send-email-peter.maydell@linaro.org
 [PMM: Keep all the bits in mpu_ctrl field, rather than
  using SCTLR bits for them; drop broken HFNMIENA support;
  various cleanup]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h      |   6 +++
+ target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
- hw/intc/armv7m_nvic.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++++++
+file changed, 65 insertions(+)
  target/arm/helper.c   |  25 +++++++++++-
  target/arm/machine.c  |   5 ++-
 files changed, 137 insertions(+), 3 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/target/arm/translate-a64.c
-+++ b/target/arm/cpu.h
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
+@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
-         uint32_t dfsr; /* Debug Fault Status Register */
+     tcg_temp_free_i64(tcg_res);
-         uint32_t mmfar; /* MemManage Fault Address */
+ }
-         uint32_t bfar; /* BusFault Address */
-+        unsigned mpu_ctrl; /* MPU_CTRL (some bits kept in sctlr_el[1]) */
++/* Floating-point data-processing (2 source) - half precision */
-         int exception;
++static void handle_fp_2src_half(DisasContext *s, int opcode,
-     } v7m;
++                                int rd, int rn, int rm)
++{
-@@ -XXX,XX +XXX,XX @@ FIELD(V7M_DFSR, DWTTRAP, 2, 1)
++    TCGv_i32 tcg_op1;
- FIELD(V7M_DFSR, VCATCH, 3, 1)
++    TCGv_i32 tcg_op2;
- FIELD(V7M_DFSR, EXTERNAL, 4, 1)
++    TCGv_i32 tcg_res;
++    TCGv_ptr fpst;
 +/* v7M MPU_CTRL bits */
 +FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
 +FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
 +FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
 +
- /* If adding a feature bit which corresponds to a Linux ELF
++    tcg_res = tcg_temp_new_i32();
-  * HWCAP bit, remember to update the feature-bit-to-hwcap
++    fpst = get_fpstatus_ptr(true);
-  * mapping in linux-user/elfload.c:get_elf_hwcap().
++    tcg_op1 = read_fp_hreg(s, rn);
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
++    tcg_op2 = read_fp_hreg(s, rm);
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/intc/armv7m_nvic.c
++    switch (opcode) {
-+++ b/hw/intc/armv7m_nvic.c
++    case 0x0: /* FMUL */
-@@ -XXX,XX +XXX,XX @@
++        gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
  #include "hw/arm/arm.h"
  #include "hw/arm/armv7m_nvic.h"
  #include "target/arm/cpu.h"
 +#include "exec/exec-all.h"
  #include "qemu/log.h"
  #include "trace.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
      case 0xd70: /* ISAR4.  */
          return 0x01310102;
      /* TODO: Implement debug registers.  */
 +    case 0xd90: /* MPU_TYPE */
 +        /* Unified MPU; if the MPU is not present this value is zero */
 +        return cpu->pmsav7_dregion << 8;
 +        break;
-+    case 0xd94: /* MPU_CTRL */
++    case 0x1: /* FDIV */
-+        return cpu->env.v7m.mpu_ctrl;
++        gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
-+    case 0xd98: /* MPU_RNR */
++        break;
-+        return cpu->env.cp15.c6_rgnr;
++    case 0x2: /* FADD */
-+    case 0xd9c: /* MPU_RBAR */
++        gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
-+    case 0xda4: /* MPU_RBAR_A1 */
++        break;
-+    case 0xdac: /* MPU_RBAR_A2 */
++    case 0x3: /* FSUB */
-+    case 0xdb4: /* MPU_RBAR_A3 */
++        gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
-+    {
++        break;
-+        int region = cpu->env.cp15.c6_rgnr;
++    case 0x4: /* FMAX */
 +        gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x5: /* FMIN */
 +        gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x6: /* FMAXNM */
 +        gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x7: /* FMINNM */
 +        gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        break;
 +    case 0x8: /* FNMUL */
 +        gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
 +        tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
-+        if (region >= cpu->pmsav7_dregion) {
++    write_fp_sreg(s, rd, tcg_res);
 +            return 0;
 +        }
 +        return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
 +    }
 +    case 0xda0: /* MPU_RASR */
 +    case 0xda8: /* MPU_RASR_A1 */
 +    case 0xdb0: /* MPU_RASR_A2 */
 +    case 0xdb8: /* MPU_RASR_A3 */
 +    {
 +        int region = cpu->env.cp15.c6_rgnr;
 +
-+        if (region >= cpu->pmsav7_dregion) {
++    tcg_temp_free_ptr(fpst);
-+            return 0;
++    tcg_temp_free_i32(tcg_op1);
-+        }
++    tcg_temp_free_i32(tcg_op2);
-+        return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) |
++    tcg_temp_free_i32(tcg_res);
-+            (cpu->env.pmsav7.drsr[region] & 0xffff);
++}
-+    }
++
-     default:
+ /* Floating point data-processing (2 source)
-         qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
+  *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
-         return 0;
+  * +---+---+---+-----------+------+---+------+--------+-----+------+------+
-@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
-         qemu_log_mask(LOG_UNIMP,
+         }
-                       "NVIC: Aux fault status registers unimplemented\n");
+         handle_fp_2src_double(s, opcode, rd, rn, rm);
          break;
-+    case 0xd90: /* MPU_TYPE */
++    case 3:
-+        return; /* RO */
++        if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-+    case 0xd94: /* MPU_CTRL */
++            unallocated_encoding(s);
 +        if ((value &
 +             (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK))
 +            == R_V7M_MPU_CTRL_HFNMIENA_MASK) {
 +            qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "
 +                          "UNPREDICTABLE\n");
 +        }
 +        cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
 +                                         R_V7M_MPU_CTRL_HFNMIENA_MASK |
 +                                         R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
 +        tlb_flush(CPU(cpu));
 +        break;
 +    case 0xd98: /* MPU_RNR */
 +        if (value >= cpu->pmsav7_dregion) {
 +            qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %"
 +                          PRIu32 "/%" PRIu32 "\n",
 +                          value, cpu->pmsav7_dregion);
 +        } else {
 +            cpu->env.cp15.c6_rgnr = value;
 +        }
 +        break;
 +    case 0xd9c: /* MPU_RBAR */
 +    case 0xda4: /* MPU_RBAR_A1 */
 +    case 0xdac: /* MPU_RBAR_A2 */
 +    case 0xdb4: /* MPU_RBAR_A3 */
 +    {
 +        int region;
 +
 +        if (value & (1 << 4)) {
 +            /* VALID bit means use the region number specified in this
 +             * value and also update MPU_RNR.REGION with that value.
 +             */
 +            region = extract32(value, 0, 4);
 +            if (region >= cpu->pmsav7_dregion) {
 +                qemu_log_mask(LOG_GUEST_ERROR,
 +                              "MPU region out of range %u/%" PRIu32 "\n",
 +                              region, cpu->pmsav7_dregion);
 +                return;
 +            }
 +            cpu->env.cp15.c6_rgnr = region;
 +        } else {
 +            region = cpu->env.cp15.c6_rgnr;
 +        }
 +
 +        if (region >= cpu->pmsav7_dregion) {
 +            return;
 +        }
-+
++        if (!fp_access_check(s)) {
 +        cpu->env.pmsav7.drbar[region] = value & ~0x1f;
 +        tlb_flush(CPU(cpu));
 +        break;
 +    }
 +    case 0xda0: /* MPU_RASR */
 +    case 0xda8: /* MPU_RASR_A1 */
 +    case 0xdb0: /* MPU_RASR_A2 */
 +    case 0xdb8: /* MPU_RASR_A3 */
 +    {
 +        int region = cpu->env.cp15.c6_rgnr;
 +
 +        if (region >= cpu->pmsav7_dregion) {
 +            return;
 +        }
-+
++        handle_fp_2src_half(s, opcode, rd, rn, rm);
 +        cpu->env.pmsav7.drsr[region] = value & 0xff3f;
 +        cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f;
 +        tlb_flush(CPU(cpu));
 +        break;
-+    }
+     default:
-     case 0xf00: /* Software Triggered Interrupt Register */
+         unallocated_encoding(s);
      {
          /* user mode can only write to STIR if CCR.USERSETMPEND permits it */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
  static inline bool regime_translation_disabled(CPUARMState *env,
                                                 ARMMMUIdx mmu_idx)
  {
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        return !(env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_ENABLE_MASK);
 +    }
 +
      if (mmu_idx == ARMMMUIdx_S2NS) {
          return (env->cp15.hcr_el2 & HCR_VM) == 0;
      }
@@ -XXX,XX +XXX,XX @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
      }
  }
 +static bool pmsav7_use_background_region(ARMCPU *cpu,
 +                                         ARMMMUIdx mmu_idx, bool is_user)
 +{
 +    /* Return true if we should use the default memory map as a
 +     * "background" region if there are no hits against any MPU regions.
 +     */
 +    CPUARMState *env = &cpu->env;
 +
 +    if (is_user) {
 +        return false;
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
 +    } else {
 +        return regime_sctlr(env, mmu_idx) & SCTLR_BR;
 +    }
 +}
 +
  static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                                   int access_type, ARMMMUIdx mmu_idx,
                                   hwaddr *phys_ptr, int *prot, uint32_t *fsr)
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
          }
          if (n == -1) { /* no hits */
 -            if (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR)) {
 +            if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
                  /* background fault */
                  *fsr = 0;
                  return true;
 diff --git a/target/arm/machine.c b/target/arm/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/machine.c
 +++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static bool m_needed(void *opaque)
  static const VMStateDescription vmstate_m = {
      .name = "cpu/m",
 -    .version_id = 3,
 -    .minimum_version_id = 3,
 +    .version_id = 4,
 +    .minimum_version_id = 4,
      .needed = m_needed,
      .fields = (VMStateField[]) {
          VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
          VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
          VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
          VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
 +        VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU),
          VMSTATE_INT32(env.v7m.exception, ARMCPU),
          VMSTATE_END_OF_LIST()
      }
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 24/27] hw/misc: add a TMP42{1, 2, 3} device model
+[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
-From: Cédric Le Goater <clg@kaod.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-Largely inspired by the TMP105 temperature sensor, here is a model for
+We missed all of the scalar fp16 fma operations.
 the TMP42{1,2,3} temperature sensors.
-Specs can be found here :
+Cc: qemu-stable@nongnu.org
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
 file changed, 48 insertions(+)
-    http://www.ti.com/lit/gpn/tmp421
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 1494827476-1487-6-git-send-email-clg@kaod.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/misc/Makefile.objs           |   1 +
  hw/misc/tmp421.c                | 401 ++++++++++++++++++++++++++++++++++++++++
  default-configs/arm-softmmu.mak |   1 +
 files changed, 403 insertions(+)
  create mode 100644 hw/misc/tmp421.c
 diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Makefile.objs
+--- a/target/arm/translate-a64.c
-+++ b/hw/misc/Makefile.objs
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
- common-obj-$(CONFIG_APPLESMC) += applesmc.o
+     tcg_temp_free_i64(tcg_res);
- common-obj-$(CONFIG_MAX111X) += max111x.o
+ }
- common-obj-$(CONFIG_TMP105) += tmp105.o
-+common-obj-$(CONFIG_TMP421) += tmp421.o
++/* Floating-point data-processing (3 source) - half precision */
- common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o
++static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
- common-obj-$(CONFIG_SGA) += sga.o
++                                int rd, int rn, int rm, int ra)
- common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
++{
-diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c
++    TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
-new file mode 100644
++    TCGv_i32 tcg_res = tcg_temp_new_i32();
-index XXXXXXX..XXXXXXX
++    TCGv_ptr fpst = get_fpstatus_ptr(true);
 --- /dev/null
 +++ b/hw/misc/tmp421.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Texas Instruments TMP421 temperature sensor.
 + *
 + * Copyright (c) 2016 IBM Corporation.
 + *
 + * Largely inspired by :
 + *
 + * Texas Instruments TMP105 temperature sensor.
 + *
 + * Copyright (C) 2008 Nokia Corporation
 + * Written by Andrzej Zaborowski <andrew@openedhand.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#include "qemu/osdep.h"
++    tcg_op1 = read_fp_hreg(s, rn);
-+#include "hw/hw.h"
++    tcg_op2 = read_fp_hreg(s, rm);
-+#include "hw/i2c/i2c.h"
++    tcg_op3 = read_fp_hreg(s, ra);
 +#include "qapi/error.h"
 +#include "qapi/visitor.h"
 +
-+/* Manufacturer / Device ID's */
++    /* These are fused multiply-add, and must be done as one
-+#define TMP421_MANUFACTURER_ID          0x55
++     * floating point operation with no rounding between the
-+#define TMP421_DEVICE_ID                0x21
++     * multiplication and addition steps.
-+#define TMP422_DEVICE_ID                0x22
++     * NB that doing the negations here as separate steps is
-+#define TMP423_DEVICE_ID                0x23
++     * correct : an input NaN should come out with its sign bit
-+
++     * flipped if it is a negated-input.
-+typedef struct DeviceInfo {
++     */
-+    int model;
++    if (o1 == true) {
-+    const char *name;
++        tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
 +} DeviceInfo;
 +
 +static const DeviceInfo devices[] = {
 +    { TMP421_DEVICE_ID, "tmp421" },
 +    { TMP422_DEVICE_ID, "tmp422" },
 +    { TMP423_DEVICE_ID, "tmp423" },
 +};
 +
 +typedef struct TMP421State {
 +    /*< private >*/
 +    I2CSlave i2c;
 +    /*< public >*/
 +
 +    int16_t temperature[4];
 +
 +    uint8_t status;
 +    uint8_t config[2];
 +    uint8_t rate;
 +
 +    uint8_t len;
 +    uint8_t buf[2];
 +    uint8_t pointer;
 +
 +} TMP421State;
 +
 +typedef struct TMP421Class {
 +    I2CSlaveClass parent_class;
 +    DeviceInfo *dev;
 +} TMP421Class;
 +
 +#define TYPE_TMP421 "tmp421-generic"
 +#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421)
 +
 +#define TMP421_CLASS(klass) \
 +     OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421)
 +#define TMP421_GET_CLASS(obj) \
 +     OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421)
 +
 +/* the TMP421 registers */
 +#define TMP421_STATUS_REG               0x08
 +#define    TMP421_STATUS_BUSY             (1 << 7)
 +#define TMP421_CONFIG_REG_1             0x09
 +#define    TMP421_CONFIG_RANGE            (1 << 2)
 +#define    TMP421_CONFIG_SHUTDOWN         (1 << 6)
 +#define TMP421_CONFIG_REG_2             0x0A
 +#define    TMP421_CONFIG_RC               (1 << 2)
 +#define    TMP421_CONFIG_LEN              (1 << 3)
 +#define    TMP421_CONFIG_REN              (1 << 4)
 +#define    TMP421_CONFIG_REN2             (1 << 5)
 +#define    TMP421_CONFIG_REN3             (1 << 6)
 +
 +#define TMP421_CONVERSION_RATE_REG      0x0B
 +#define TMP421_ONE_SHOT                 0x0F
 +
 +#define TMP421_RESET                    0xFC
 +#define TMP421_MANUFACTURER_ID_REG      0xFE
 +#define TMP421_DEVICE_ID_REG            0xFF
 +
 +#define TMP421_TEMP_MSB0                0x00
 +#define TMP421_TEMP_MSB1                0x01
 +#define TMP421_TEMP_MSB2                0x02
 +#define TMP421_TEMP_MSB3                0x03
 +#define TMP421_TEMP_LSB0                0x10
 +#define TMP421_TEMP_LSB1                0x11
 +#define TMP421_TEMP_LSB2                0x12
 +#define TMP421_TEMP_LSB3                0x13
 +
 +static const int32_t mins[2] = { -40000, -55000 };
 +static const int32_t maxs[2] = { 127000, 150000 };
 +
 +static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name,
 +                                   void *opaque, Error **errp)
 +{
 +    TMP421State *s = TMP421(obj);
 +    bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
 +    int offset = ext_range * 64 * 256;
 +    int64_t value;
 +    int tempid;
 +
 +    if (sscanf(name, "temperature%d", &tempid) != 1) {
 +        error_setg(errp, "error reading %s: %m", name);
 +        return;
 +    }
 +
-+    if (tempid >= 4 || tempid < 0) {
++    if (o0 != o1) {
-+        error_setg(errp, "error reading %s", name);
++        tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
 +        return;
 +    }
 +
-+    value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256;
++    gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
 +
-+    visit_type_int(v, name, &value, errp);
++    write_fp_sreg(s, rd, tcg_res);
 +
 +    tcg_temp_free_ptr(fpst);
 +    tcg_temp_free_i32(tcg_op1);
 +    tcg_temp_free_i32(tcg_op2);
 +    tcg_temp_free_i32(tcg_op3);
 +    tcg_temp_free_i32(tcg_res);
 +}
 +
-+/* Units are 0.001 centigrades relative to 0 C.  s->temperature is 8.8
+ /* Floating point data-processing (3 source)
-+ * fixed point, so units are 1/256 centigrades.  A simple ratio will do.
+  *   31  30  29 28       24 23  22  21  20  16  15  14  10 9    5 4    0
-+ */
+  * +---+---+---+-----------+------+----+------+----+------+------+------+
-+static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name,
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
-+                                   void *opaque, Error **errp)
+         }
-+{
+         handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
-+    TMP421State *s = TMP421(obj);
+         break;
-+    Error *local_err = NULL;
++    case 3:
-+    int64_t temp;
++        if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-+    bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
++            unallocated_encoding(s);
-+    int offset = ext_range * 64 * 256;
++            return;
-+    int tempid;
++        }
-+
++        if (!fp_access_check(s)) {
-+    visit_type_int(v, name, &temp, &local_err);
++            return;
-+    if (local_err) {
++        }
-+        error_propagate(errp, local_err);
++        handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
 +        return;
 +    }
 +
 +    if (temp >= maxs[ext_range] || temp < mins[ext_range]) {
 +        error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range",
 +                   temp / 1000, temp % 1000);
 +        return;
 +    }
 +
 +    if (sscanf(name, "temperature%d", &tempid) != 1) {
 +        error_setg(errp, "error reading %s: %m", name);
 +        return;
 +    }
 +
 +    if (tempid >= 4 || tempid < 0) {
 +        error_setg(errp, "error reading %s", name);
 +        return;
 +    }
 +
 +    s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset;
 +}
 +
 +static void tmp421_read(TMP421State *s)
 +{
 +    TMP421Class *sc = TMP421_GET_CLASS(s);
 +
 +    s->len = 0;
 +
 +    switch (s->pointer) {
 +    case TMP421_MANUFACTURER_ID_REG:
 +        s->buf[s->len++] = TMP421_MANUFACTURER_ID;
 +        break;
-+    case TMP421_DEVICE_ID_REG:
+     default:
-+        s->buf[s->len++] = sc->dev->model;
+         unallocated_encoding(s);
-+        break;
+     }
 +    case TMP421_CONFIG_REG_1:
 +        s->buf[s->len++] = s->config[0];
 +        break;
 +    case TMP421_CONFIG_REG_2:
 +        s->buf[s->len++] = s->config[1];
 +        break;
 +    case TMP421_CONVERSION_RATE_REG:
 +        s->buf[s->len++] = s->rate;
 +        break;
 +    case TMP421_STATUS_REG:
 +        s->buf[s->len++] = s->status;
 +        break;
 +
 +        /* FIXME: check for channel enablement in config registers */
 +    case TMP421_TEMP_MSB0:
 +        s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8);
 +        s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
 +        break;
 +    case TMP421_TEMP_MSB1:
 +        s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8);
 +        s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
 +        break;
 +    case TMP421_TEMP_MSB2:
 +        s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8);
 +        s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
 +        break;
 +    case TMP421_TEMP_MSB3:
 +        s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8);
 +        s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
 +        break;
 +    case TMP421_TEMP_LSB0:
 +        s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
 +        break;
 +    case TMP421_TEMP_LSB1:
 +        s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
 +        break;
 +    case TMP421_TEMP_LSB2:
 +        s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
 +        break;
 +    case TMP421_TEMP_LSB3:
 +        s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
 +        break;
 +    }
 +}
 +
 +static void tmp421_reset(I2CSlave *i2c);
 +
 +static void tmp421_write(TMP421State *s)
 +{
 +    switch (s->pointer) {
 +    case TMP421_CONVERSION_RATE_REG:
 +        s->rate = s->buf[0];
 +        break;
 +    case TMP421_CONFIG_REG_1:
 +        s->config[0] = s->buf[0];
 +        break;
 +    case TMP421_CONFIG_REG_2:
 +        s->config[1] = s->buf[0];
 +        break;
 +    case TMP421_RESET:
 +        tmp421_reset(I2C_SLAVE(s));
 +        break;
 +    }
 +}
 +
 +static int tmp421_rx(I2CSlave *i2c)
 +{
 +    TMP421State *s = TMP421(i2c);
 +
 +    if (s->len < 2) {
 +        return s->buf[s->len++];
 +    } else {
 +        return 0xff;
 +    }
 +}
 +
 +static int tmp421_tx(I2CSlave *i2c, uint8_t data)
 +{
 +    TMP421State *s = TMP421(i2c);
 +
 +    if (s->len == 0) {
 +        /* first byte is the register pointer for a read or write
 +         * operation */
 +        s->pointer = data;
 +        s->len++;
 +    } else if (s->len == 1) {
 +        /* second byte is the data to write. The device only supports
 +         * one byte writes */
 +        s->buf[0] = data;
 +        tmp421_write(s);
 +    }
 +
 +    return 0;
 +}
 +
 +static int tmp421_event(I2CSlave *i2c, enum i2c_event event)
 +{
 +    TMP421State *s = TMP421(i2c);
 +
 +    if (event == I2C_START_RECV) {
 +        tmp421_read(s);
 +    }
 +
 +    s->len = 0;
 +    return 0;
 +}
 +
 +static const VMStateDescription vmstate_tmp421 = {
 +    .name = "TMP421",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT8(len, TMP421State),
 +        VMSTATE_UINT8_ARRAY(buf, TMP421State, 2),
 +        VMSTATE_UINT8(pointer, TMP421State),
 +        VMSTATE_UINT8_ARRAY(config, TMP421State, 2),
 +        VMSTATE_UINT8(status, TMP421State),
 +        VMSTATE_UINT8(rate, TMP421State),
 +        VMSTATE_INT16_ARRAY(temperature, TMP421State, 4),
 +        VMSTATE_I2C_SLAVE(i2c, TMP421State),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void tmp421_reset(I2CSlave *i2c)
 +{
 +    TMP421State *s = TMP421(i2c);
 +    TMP421Class *sc = TMP421_GET_CLASS(s);
 +
 +    memset(s->temperature, 0, sizeof(s->temperature));
 +    s->pointer = 0;
 +
 +    s->config[0] = 0; /* TMP421_CONFIG_RANGE */
 +
 +     /* resistance correction and channel enablement */
 +    switch (sc->dev->model) {
 +    case TMP421_DEVICE_ID:
 +        s->config[1] = 0x1c;
 +        break;
 +    case TMP422_DEVICE_ID:
 +        s->config[1] = 0x3c;
 +        break;
 +    case TMP423_DEVICE_ID:
 +        s->config[1] = 0x7c;
 +        break;
 +    }
 +
 +    s->rate = 0x7;       /* 8Hz */
 +    s->status = 0;
 +}
 +
 +static int tmp421_init(I2CSlave *i2c)
 +{
 +    TMP421State *s = TMP421(i2c);
 +
 +    tmp421_reset(&s->i2c);
 +
 +    return 0;
 +}
 +
 +static void tmp421_initfn(Object *obj)
 +{
 +    object_property_add(obj, "temperature0", "int",
 +                        tmp421_get_temperature,
 +                        tmp421_set_temperature, NULL, NULL, NULL);
 +    object_property_add(obj, "temperature1", "int",
 +                        tmp421_get_temperature,
 +                        tmp421_set_temperature, NULL, NULL, NULL);
 +    object_property_add(obj, "temperature2", "int",
 +                        tmp421_get_temperature,
 +                        tmp421_set_temperature, NULL, NULL, NULL);
 +    object_property_add(obj, "temperature3", "int",
 +                        tmp421_get_temperature,
 +                        tmp421_set_temperature, NULL, NULL, NULL);
 +}
 +
 +static void tmp421_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
 +    TMP421Class *sc = TMP421_CLASS(klass);
 +
 +    k->init = tmp421_init;
 +    k->event = tmp421_event;
 +    k->recv = tmp421_rx;
 +    k->send = tmp421_tx;
 +    dc->vmsd = &vmstate_tmp421;
 +    sc->dev = (DeviceInfo *) data;
 +}
 +
 +static const TypeInfo tmp421_info = {
 +    .name          = TYPE_TMP421,
 +    .parent        = TYPE_I2C_SLAVE,
 +    .instance_size = sizeof(TMP421State),
 +    .instance_init = tmp421_initfn,
 +    .class_init    = tmp421_class_init,
 +};
 +
 +static void tmp421_register_types(void)
 +{
 +    int i;
 +
 +    type_register_static(&tmp421_info);
 +    for (i = 0; i < ARRAY_SIZE(devices); ++i) {
 +        TypeInfo ti = {
 +            .name       = devices[i].name,
 +            .parent     = TYPE_TMP421,
 +            .class_init = tmp421_class_init,
 +            .class_data = (void *) &devices[i],
 +        };
 +        type_register(&ti);
 +    }
 +}
 +
 +type_init(tmp421_register_types)
 diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/default-configs/arm-softmmu.mak
 +++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_TWL92230=y
  CONFIG_TSC2005=y
  CONFIG_LM832X=y
  CONFIG_TMP105=y
 +CONFIG_TMP421=y
  CONFIG_STELLARIS=y
  CONFIG_STELLARIS_INPUT=y
  CONFIG_STELLARIS_ENET=y
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 08/27] arm: Add support for M profile CPUs having different MMU index semantics
+[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
-The M profile CPU's MPU has an awkward corner case which we
+From: Alex Bennée <alex.bennee@linaro.org>
-would like to implement with a different MMU index.
+These where missed out from the rest of the half-precision work.
-We can avoid having to bump the number of MMU modes ARM
-uses, because some of our existing MMU indexes are only
+Cc: qemu-stable@nongnu.org
-used by non-M-profile CPUs, so we can borrow one.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-To avoid that getting too confusing, clean up the code
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-to try to keep the two meanings of the index separate.
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Instead of ARMMMUIdx enum values being identical to core QEMU
+Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
-MMU index values, they are now the core index values with some
+[rth: Diagnose lack of FP16 before fp_access_check]
-high bits set. Any particular CPU always uses the same high
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 bits (so eventually A profile cores and M profile cores will
 use different bits). New functions arm_to_core_mmu_idx()
 and core_to_arm_mmu_idx() convert between the two.
 In general core index values are stored in 'int' types, and
 ARM values are stored in ARMMMUIdx types.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1493122030-32191-3-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/cpu.h           |  71 ++++++++++++++++-----
+ target/arm/helper-a64.h    |  2 +
- target/arm/translate.h     |   2 +-
+ target/arm/helper-a64.c    | 10 +++++
- target/arm/helper.c        | 151 ++++++++++++++++++++++++---------------------
+ target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
- target/arm/op_helper.c     |   3 +-
+files changed, 83 insertions(+), 17 deletions(-)
- target/arm/translate-a64.c |  18 ++++--
- target/arm/translate.c     |  10 +--
+diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
 files changed, 156 insertions(+), 99 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/target/arm/helper-a64.h
-+++ b/target/arm/cpu.h
++++ b/target/arm/helper-a64.h
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
+@@ -XXX,XX +XXX,XX @@
-  * for the accesses done as part of a stage 1 page table walk, rather than
+ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-  * having to walk the stage 2 page table over and over.)
+ DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
-  *
+ DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
-+ * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
++DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
-+ * are not quite the same -- different CPU types (most notably M profile
++DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
-+ * vs A/R profile) would like to use MMU indexes with different semantics,
+ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
-+ * but since we don't ever need to use all of those in a single CPU we
+ DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
-+ * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
+ DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
-+ * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
+diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-+ * the same for any particular CPU.
+index XXXXXXX..XXXXXXX 100644
-+ * Variables of type ARMMUIdx are always full values, and the core
+--- a/target/arm/helper-a64.c
-+ * index values are in variables of type 'int'.
++++ b/target/arm/helper-a64.c
-+ *
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
-  * Our enumeration includes at the end some entries which are not "true"
+     return flags;
-  * mmu_idx values in that they don't have corresponding TLBs and are only
+ }
-  * valid for doing slow path page table walks.
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
++uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
   * of the AT/ATS operations.
   * The values used are carefully arranged to make mmu_idx => EL lookup easy.
   */
 +#define ARM_MMU_IDX_A 0x10 /* A profile (and M profile, for the moment) */
 +#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
 +
 +#define ARM_MMU_IDX_TYPE_MASK (~0x7)
 +#define ARM_MMU_IDX_COREIDX_MASK 0x7
 +
  typedef enum ARMMMUIdx {
 -    ARMMMUIdx_S12NSE0 = 0,
 -    ARMMMUIdx_S12NSE1 = 1,
 -    ARMMMUIdx_S1E2 = 2,
 -    ARMMMUIdx_S1E3 = 3,
 -    ARMMMUIdx_S1SE0 = 4,
 -    ARMMMUIdx_S1SE1 = 5,
 -    ARMMMUIdx_S2NS = 6,
 +    ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
 +    ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
      /* Indexes below here don't have TLBs and are used only for AT system
       * instructions or for the first stage of an S12 page table walk.
       */
 -    ARMMMUIdx_S1NSE0 = 7,
 -    ARMMMUIdx_S1NSE1 = 8,
 +    ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB,
 +    ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB,
  } ARMMMUIdx;
 +/* Bit macros for the core-mmu-index values for each index,
 + * for use when calling tlb_flush_by_mmuidx() and friends.
 + */
 +typedef enum ARMMMUIdxBit {
 +    ARMMMUIdxBit_S12NSE0 = 1 << 0,
 +    ARMMMUIdxBit_S12NSE1 = 1 << 1,
 +    ARMMMUIdxBit_S1E2 = 1 << 2,
 +    ARMMMUIdxBit_S1E3 = 1 << 3,
 +    ARMMMUIdxBit_S1SE0 = 1 << 4,
 +    ARMMMUIdxBit_S1SE1 = 1 << 5,
 +    ARMMMUIdxBit_S2NS = 1 << 6,
 +} ARMMMUIdxBit;
 +
  #define MMU_USER_IDX 0
 +static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
 +{
-+    return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
++    return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
 +}
 +
-+static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
++uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
 +{
-+    return mmu_idx | ARM_MMU_IDX_A;
++    return float_rel_to_flags(float16_compare(x, y, fp_status));
 +}
 +
- /* Return the exception level we're running at if this is our mmu_idx */
+ uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
  static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
  {
--    assert(mmu_idx < ARMMMUIdx_S2NS);
+     return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
 -    return mmu_idx & 3;
 +    switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
 +    case ARM_MMU_IDX_A:
 +        return mmu_idx & 3;
 +    default:
 +        g_assert_not_reached();
 +    }
  }
  /* Determine the current mmu_idx to use for normal loads/stores */
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
      int el = arm_current_el(env);
      if (el < 2 && arm_is_secure_below_el3(env)) {
 -        return ARMMMUIdx_S1SE0 + el;
 +        return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
      }
      return el;
  }
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
  static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                                          target_ulong *cs_base, uint32_t *flags)
  {
 -    ARMMMUIdx mmu_idx = cpu_mmu_index(env, false);
 +    ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
      if (is_a64(env)) {
          *pc = env->pc;
          *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                     << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
      }
 -    *flags |= (mmu_idx << ARM_TBFLAG_MMUIDX_SHIFT);
 +    *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT);
      /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
       * states defined in the ARM ARM for software singlestep:
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int arm_dc_feature(DisasContext *dc, int feature)
  static inline int get_mem_index(DisasContext *s)
  {
 -    return s->mmu_idx;
 +    return arm_to_core_mmu_idx(s->mmu_idx);
  }
  /* Function used to determine the target exception EL when otherwise not known
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
      CPUState *cs = ENV_GET_CPU(env);
      tlb_flush_by_mmuidx(cs,
 -                        (1 << ARMMMUIdx_S12NSE1) |
 -                        (1 << ARMMMUIdx_S12NSE0) |
 -                        (1 << ARMMMUIdx_S2NS));
 +                        ARMMMUIdxBit_S12NSE1 |
 +                        ARMMMUIdxBit_S12NSE0 |
 +                        ARMMMUIdxBit_S2NS);
  }
  static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      CPUState *cs = ENV_GET_CPU(env);
      tlb_flush_by_mmuidx_all_cpus_synced(cs,
 -                                        (1 << ARMMMUIdx_S12NSE1) |
 -                                        (1 << ARMMMUIdx_S12NSE0) |
 -                                        (1 << ARMMMUIdx_S2NS));
 +                                        ARMMMUIdxBit_S12NSE1 |
 +                                        ARMMMUIdxBit_S12NSE0 |
 +                                        ARMMMUIdxBit_S2NS);
  }
  static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
      pageaddr = sextract64(value << 12, 0, 40);
 -    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS));
 +    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
  }
  static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      pageaddr = sextract64(value << 12, 0, 40);
      tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                             (1 << ARMMMUIdx_S2NS));
 +                                             ARMMMUIdxBit_S2NS);
  }
  static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      CPUState *cs = ENV_GET_CPU(env);
 -    tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2));
 +    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
  }
  static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      CPUState *cs = ENV_GET_CPU(env);
 -    tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E2));
 +    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
  }
  static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
      CPUState *cs = ENV_GET_CPU(env);
      uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
 -    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2));
 +    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
  }
  static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
      tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                             (1 << ARMMMUIdx_S1E2));
 +                                             ARMMMUIdxBit_S1E2);
  }
  static const ARMCPRegInfo cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
      /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
      if (raw_read(env, ri) != value) {
          tlb_flush_by_mmuidx(cs,
 -                            (1 << ARMMMUIdx_S12NSE1) |
 -                            (1 << ARMMMUIdx_S12NSE0) |
 -                            (1 << ARMMMUIdx_S2NS));
 +                            ARMMMUIdxBit_S12NSE1 |
 +                            ARMMMUIdxBit_S12NSE0 |
 +                            ARMMMUIdxBit_S2NS);
          raw_write(env, ri, value);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
      if (arm_is_secure_below_el3(env)) {
          tlb_flush_by_mmuidx(cs,
 -                            (1 << ARMMMUIdx_S1SE1) |
 -                            (1 << ARMMMUIdx_S1SE0));
 +                            ARMMMUIdxBit_S1SE1 |
 +                            ARMMMUIdxBit_S1SE0);
      } else {
          tlb_flush_by_mmuidx(cs,
 -                            (1 << ARMMMUIdx_S12NSE1) |
 -                            (1 << ARMMMUIdx_S12NSE0));
 +                            ARMMMUIdxBit_S12NSE1 |
 +                            ARMMMUIdxBit_S12NSE0);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      if (sec) {
          tlb_flush_by_mmuidx_all_cpus_synced(cs,
 -                                            (1 << ARMMMUIdx_S1SE1) |
 -                                            (1 << ARMMMUIdx_S1SE0));
 +                                            ARMMMUIdxBit_S1SE1 |
 +                                            ARMMMUIdxBit_S1SE0);
      } else {
          tlb_flush_by_mmuidx_all_cpus_synced(cs,
 -                                            (1 << ARMMMUIdx_S12NSE1) |
 -                                            (1 << ARMMMUIdx_S12NSE0));
 +                                            ARMMMUIdxBit_S12NSE1 |
 +                                            ARMMMUIdxBit_S12NSE0);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
      if (arm_is_secure_below_el3(env)) {
          tlb_flush_by_mmuidx(cs,
 -                            (1 << ARMMMUIdx_S1SE1) |
 -                            (1 << ARMMMUIdx_S1SE0));
 +                            ARMMMUIdxBit_S1SE1 |
 +                            ARMMMUIdxBit_S1SE0);
      } else {
          if (arm_feature(env, ARM_FEATURE_EL2)) {
              tlb_flush_by_mmuidx(cs,
 -                                (1 << ARMMMUIdx_S12NSE1) |
 -                                (1 << ARMMMUIdx_S12NSE0) |
 -                                (1 << ARMMMUIdx_S2NS));
 +                                ARMMMUIdxBit_S12NSE1 |
 +                                ARMMMUIdxBit_S12NSE0 |
 +                                ARMMMUIdxBit_S2NS);
          } else {
              tlb_flush_by_mmuidx(cs,
 -                                (1 << ARMMMUIdx_S12NSE1) |
 -                                (1 << ARMMMUIdx_S12NSE0));
 +                                ARMMMUIdxBit_S12NSE1 |
 +                                ARMMMUIdxBit_S12NSE0);
          }
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
      ARMCPU *cpu = arm_env_get_cpu(env);
      CPUState *cs = CPU(cpu);
 -    tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2));
 +    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
  }
  static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
      ARMCPU *cpu = arm_env_get_cpu(env);
      CPUState *cs = CPU(cpu);
 -    tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E3));
 +    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
  }
  static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      if (sec) {
          tlb_flush_by_mmuidx_all_cpus_synced(cs,
 -                                            (1 << ARMMMUIdx_S1SE1) |
 -                                            (1 << ARMMMUIdx_S1SE0));
 +                                            ARMMMUIdxBit_S1SE1 |
 +                                            ARMMMUIdxBit_S1SE0);
      } else if (has_el2) {
          tlb_flush_by_mmuidx_all_cpus_synced(cs,
 -                                            (1 << ARMMMUIdx_S12NSE1) |
 -                                            (1 << ARMMMUIdx_S12NSE0) |
 -                                            (1 << ARMMMUIdx_S2NS));
 +                                            ARMMMUIdxBit_S12NSE1 |
 +                                            ARMMMUIdxBit_S12NSE0 |
 +                                            ARMMMUIdxBit_S2NS);
      } else {
            tlb_flush_by_mmuidx_all_cpus_synced(cs,
 -                                              (1 << ARMMMUIdx_S12NSE1) |
 -                                              (1 << ARMMMUIdx_S12NSE0));
 +                                              ARMMMUIdxBit_S12NSE1 |
 +                                              ARMMMUIdxBit_S12NSE0);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      CPUState *cs = ENV_GET_CPU(env);
 -    tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E2));
 +    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
  }
  static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      CPUState *cs = ENV_GET_CPU(env);
 -    tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E3));
 +    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
  }
  static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
      if (arm_is_secure_below_el3(env)) {
          tlb_flush_page_by_mmuidx(cs, pageaddr,
 -                                 (1 << ARMMMUIdx_S1SE1) |
 -                                 (1 << ARMMMUIdx_S1SE0));
 +                                 ARMMMUIdxBit_S1SE1 |
 +                                 ARMMMUIdxBit_S1SE0);
      } else {
          tlb_flush_page_by_mmuidx(cs, pageaddr,
 -                                 (1 << ARMMMUIdx_S12NSE1) |
 -                                 (1 << ARMMMUIdx_S12NSE0));
 +                                 ARMMMUIdxBit_S12NSE1 |
 +                                 ARMMMUIdxBit_S12NSE0);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
      CPUState *cs = CPU(cpu);
      uint64_t pageaddr = sextract64(value << 12, 0, 56);
 -    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2));
 +    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
  }
  static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
      CPUState *cs = CPU(cpu);
      uint64_t pageaddr = sextract64(value << 12, 0, 56);
 -    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E3));
 +    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
  }
  static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      if (sec) {
          tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                                 (1 << ARMMMUIdx_S1SE1) |
 -                                                 (1 << ARMMMUIdx_S1SE0));
 +                                                 ARMMMUIdxBit_S1SE1 |
 +                                                 ARMMMUIdxBit_S1SE0);
      } else {
          tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                                 (1 << ARMMMUIdx_S12NSE1) |
 -                                                 (1 << ARMMMUIdx_S12NSE0));
 +                                                 ARMMMUIdxBit_S12NSE1 |
 +                                                 ARMMMUIdxBit_S12NSE0);
      }
  }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      uint64_t pageaddr = sextract64(value << 12, 0, 56);
      tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                             (1 << ARMMMUIdx_S1E2));
 +                                             ARMMMUIdxBit_S1E2);
  }
  static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      uint64_t pageaddr = sextract64(value << 12, 0, 56);
      tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                             (1 << ARMMMUIdx_S1E3));
 +                                             ARMMMUIdxBit_S1E3);
  }
  static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
      pageaddr = sextract64(value << 12, 0, 48);
 -    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS));
 +    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
  }
  static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
      pageaddr = sextract64(value << 12, 0, 48);
      tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                             (1 << ARMMMUIdx_S2NS));
 +                                             ARMMMUIdxBit_S2NS);
  }
  static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
      return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
  }
 +/* Convert a possible stage1+2 MMU index into the appropriate
 + * stage 1 MMU index
 + */
 +static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
 +{
 +    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
 +        mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);
 +    }
 +    return mmu_idx;
 +}
 +
  /* Returns TBI0 value for current regime el */
  uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
  {
@@ -XXX,XX +XXX,XX @@ uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
      uint32_t el;
      /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
 -       * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
 -       */
 -    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
 -        mmu_idx += ARMMMUIdx_S1NSE0;
 -    }
 +     * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
 +     */
 +    mmu_idx = stage_1_mmu_idx(mmu_idx);
      tcr = regime_tcr(env, mmu_idx);
      el = regime_el(env, mmu_idx);
@@ -XXX,XX +XXX,XX @@ uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
      uint32_t el;
      /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
 -       * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
 -       */
 -    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
 -        mmu_idx += ARMMMUIdx_S1NSE0;
 -    }
 +     * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
 +     */
 +    mmu_idx = stage_1_mmu_idx(mmu_idx);
      tcr = regime_tcr(env, mmu_idx);
      el = regime_el(env, mmu_idx);
@@ -XXX,XX +XXX,XX @@ static inline bool regime_using_lpae_format(CPUARMState *env,
   * on whether the long or short descriptor format is in use. */
  bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
  {
 -    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
 -        mmu_idx += ARMMMUIdx_S1NSE0;
 -    }
 +    mmu_idx = stage_1_mmu_idx(mmu_idx);
      return regime_using_lpae_format(env, mmu_idx);
  }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
              int ret;
              ret = get_phys_addr(env, address, access_type,
 -                                mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
 +                                stage_1_mmu_idx(mmu_idx), &ipa, attrs,
                                  prot, page_size, fsr, fi);
              /* If S1 fails or S2 is disabled, return early.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
              /*
               * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
               */
 -            mmu_idx += ARMMMUIdx_S1NSE0;
 +            mmu_idx = stage_1_mmu_idx(mmu_idx);
          }
      }
@@ -XXX,XX +XXX,XX @@ bool arm_tlb_fill(CPUState *cs, vaddr address,
      int ret;
      MemTxAttrs attrs = {};
 -    ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
 +    ret = get_phys_addr(env, address, access_type,
 +                        core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
                          &attrs, &prot, &page_size, fsr, fi);
      if (!ret) {
          /* Map a single [sub]page.  */
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
      bool ret;
      uint32_t fsr;
      ARMMMUFaultInfo fi = {};
 +    ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
      *attrs = (MemTxAttrs) {};
 -    ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
 +    ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
                          attrs, &prot, &page_size, &fsr, &fi);
      if (ret) {
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/op_helper.c
 +++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
      int target_el;
      bool same_el;
      uint32_t syn;
 +    ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
      if (retaddr) {
          /* now we have a real cpu fault */
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
      /* the DFSR for an alignment fault depends on whether we're using
       * the LPAE long descriptor format, or the short descriptor format
       */
 -    if (arm_s1_regime_using_lpae_format(env, mmu_idx)) {
 +    if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
          env->exception.fsr = (1 << 9) | 0x21;
      } else {
          env->exception.fsr = 0x1;
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ void a64_translate_init(void)
+@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
-         offsetof(CPUARMState, exclusive_high), "exclusive_high");
+     }
  }
--static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s)
+-static void handle_fp_compare(DisasContext *s, bool is_double,
-+static inline int get_a64_user_mem_index(DisasContext *s)
++static void handle_fp_compare(DisasContext *s, int size,
                                unsigned int rn, unsigned int rm,
                                bool cmp_with_zero, bool signal_all_nans)
  {
--    /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
+     TCGv_i64 tcg_flags = tcg_temp_new_i64();
-+    /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
+-    TCGv_ptr fpst = get_fpstatus_ptr(false);
-      *  if EL1, access as if EL0; otherwise access at current EL
++    TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
-      */
-+    ARMMMUIdx useridx;
+-    if (is_double) {
-+
++    if (size == MO_64) {
-     switch (s->mmu_idx) {
+         TCGv_i64 tcg_vn, tcg_vm;
-     case ARMMMUIdx_S12NSE1:
--        return ARMMMUIdx_S12NSE0;
+         tcg_vn = read_fp_dreg(s, rn);
-+        useridx = ARMMMUIdx_S12NSE0;
+@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
-+        break;
+         tcg_temp_free_i64(tcg_vn);
-     case ARMMMUIdx_S1SE1:
+         tcg_temp_free_i64(tcg_vm);
--        return ARMMMUIdx_S1SE0;
+     } else {
-+        useridx = ARMMMUIdx_S1SE0;
+-        TCGv_i32 tcg_vn, tcg_vm;
-+        break;
++        TCGv_i32 tcg_vn = tcg_temp_new_i32();
-     case ARMMMUIdx_S2NS:
++        TCGv_i32 tcg_vm = tcg_temp_new_i32();
-         g_assert_not_reached();
-     default:
+-        tcg_vn = read_fp_sreg(s, rn);
--        return s->mmu_idx;
++        read_vec_element_i32(s, tcg_vn, rn, 0, size);
-+        useridx = s->mmu_idx;
+         if (cmp_with_zero) {
-+        break;
+-            tcg_vm = tcg_const_i32(0);
-     }
++            tcg_gen_movi_i32(tcg_vm, 0);
-+    return arm_to_core_mmu_idx(useridx);
+         } else {
 -            tcg_vm = read_fp_sreg(s, rm);
 +            read_vec_element_i32(s, tcg_vm, rm, 0, size);
          }
 -        if (signal_all_nans) {
 -            gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
 -        } else {
 -            gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
 +
 +        switch (size) {
 +        case MO_32:
 +            if (signal_all_nans) {
 +                gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
 +            } else {
 +                gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
 +            }
 +            break;
 +        case MO_16:
 +            if (signal_all_nans) {
 +                gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
 +            } else {
 +                gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
 +            }
 +            break;
 +        default:
 +            g_assert_not_reached();
          }
 +
          tcg_temp_free_i32(tcg_vn);
          tcg_temp_free_i32(tcg_vm);
      }
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
  static void disas_fp_compare(DisasContext *s, uint32_t insn)
  {
      unsigned int mos, type, rm, op, rn, opc, op2r;
 +    int size;
      mos = extract32(insn, 29, 3);
 -    type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
 +    type = extract32(insn, 22, 2);
      rm = extract32(insn, 16, 5);
      op = extract32(insn, 14, 2);
      rn = extract32(insn, 5, 5);
      opc = extract32(insn, 3, 2);
      op2r = extract32(insn, 0, 3);
 -    if (mos || op || op2r || type > 1) {
 +    if (mos || op || op2r) {
 +        unallocated_encoding(s);
 +        return;
 +    }
 +
 +    switch (type) {
 +    case 0:
 +        size = MO_32;
 +        break;
 +    case 1:
 +        size = MO_64;
 +        break;
 +    case 3:
 +        size = MO_16;
 +        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +            break;
 +        }
 +        /* fallthru */
 +    default:
          unallocated_encoding(s);
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
          return;
      }
 -    handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
 +    handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
  }
- void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
+ /* Floating point conditional compare
-@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
-     dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;
+     unsigned int mos, type, rm, cond, rn, op, nzcv;
-     dc->condexec_mask = 0;
+     TCGv_i64 tcg_flags;
-     dc->condexec_cond = 0;
+     TCGLabel *label_continue = NULL;
--    dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
++    int size;
-+    dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags));
-     dc->tbi0 = ARM_TBFLAG_TBI0(tb->flags);
+     mos = extract32(insn, 29, 3);
-     dc->tbi1 = ARM_TBFLAG_TBI1(tb->flags);
+-    type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
-     dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
++    type = extract32(insn, 22, 2);
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+     rm = extract32(insn, 16, 5);
-index XXXXXXX..XXXXXXX 100644
+     cond = extract32(insn, 12, 4);
---- a/target/arm/translate.c
+     rn = extract32(insn, 5, 5);
-+++ b/target/arm/translate.c
+     op = extract32(insn, 4, 1);
-@@ -XXX,XX +XXX,XX @@ static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
+     nzcv = extract32(insn, 0, 4);
-     disas_set_insn_syndrome(s, syn);
- }
+-    if (mos || type > 1) {
++    if (mos) {
--static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
++        unallocated_encoding(s);
-+static inline int get_a32_user_mem_index(DisasContext *s)
++        return;
- {
++    }
--    /* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
++
-+    /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store"
++    switch (type) {
-      * insns:
++    case 0:
-      *  if PL2, UNPREDICTABLE (we choose to implement as if PL0)
++        size = MO_32;
-      *  otherwise, access as if at PL0.
++        break;
-@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
++    case 1:
-     case ARMMMUIdx_S1E2:        /* this one is UNPREDICTABLE */
++        size = MO_64;
-     case ARMMMUIdx_S12NSE0:
++        break;
-     case ARMMMUIdx_S12NSE1:
++    case 3:
--        return ARMMMUIdx_S12NSE0;
++        size = MO_16;
-+        return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0);
++        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
-     case ARMMMUIdx_S1E3:
++            break;
-     case ARMMMUIdx_S1SE0:
++        }
-     case ARMMMUIdx_S1SE1:
++        /* fallthru */
--        return ARMMMUIdx_S1SE0;
++    default:
-+        return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0);
+         unallocated_encoding(s);
-     case ARMMMUIdx_S2NS:
+         return;
-     default:
+     }
-         g_assert_not_reached();
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
-@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
+         gen_set_label(label_match);
-     dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;
+     }
-     dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
-     dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
+-    handle_fp_compare(s, type, rn, rm, false, op);
--    dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
++    handle_fp_compare(s, size, rn, rm, false, op);
-+    dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags));
-     dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
+     if (cond < 0x0e) {
- #if !defined(CONFIG_USER_ONLY)
+         gen_set_label(label_continue);
      dc->user = (dc->current_el == 0);
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 20/27] aspeed/i2c: improve command handling
+[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
-From: Cédric Le Goater <clg@kaod.org>
+From: Alex Bennée <alex.bennee@linaro.org>
-Multiple I2C commands can be fired simultaneously and the controller
+These were missed out from the rest of the half-precision work.
 execute the commands following these priorities:
-  (1) Master Start Command
+Cc: qemu-stable@nongnu.org
-  (2) Master Transmit Command
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-  (3) Slave Transmit Command or Master Receive Command
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-  (4) Master Stop Command
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-The current code is incorrect with respect to the above sequence and
+Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
-needs to be reworked to handle each individual command.
+[rth: Fix erroneous check vs type]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 1494827476-1487-2-git-send-email-clg@kaod.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/i2c/aspeed_i2c.c | 24 ++++++++++++++++++------
+ target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
-file changed, 18 insertions(+), 6 deletions(-)
+file changed, 25 insertions(+), 6 deletions(-)
-diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/aspeed_i2c.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/i2c/aspeed_i2c.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
+     unsigned int mos, type, rm, cond, rn, rd;
- static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
+     TCGv_i64 t_true, t_false, t_zero;
- {
+     DisasCompare64 c;
-+    bus->cmd &= ~0xFFFF;
++    TCGMemOp sz;
-     bus->cmd |= value & 0xFFFF;
-     bus->intr_status = 0;
+     mos = extract32(insn, 29, 3);
+-    type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
-@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
++    type = extract32(insn, 22, 2);
-             bus->intr_status |= I2CD_INTR_TX_ACK;
+     rm = extract32(insn, 16, 5);
-         }
+     cond = extract32(insn, 12, 4);
+     rn = extract32(insn, 5, 5);
--    } else if (bus->cmd & I2CD_M_TX_CMD) {
+     rd = extract32(insn, 0, 5);
-+        /* START command is also a TX command, as the slave address is
-+         * sent on the bus */
+-    if (mos || type > 1) {
-+        bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
++    if (mos) {
-+
++        unallocated_encoding(s);
-+        /* No slave found */
++        return;
 +        if (!i2c_bus_busy(bus->bus)) {
 +            return;
 +        }
 +    }
 +
-+    if (bus->cmd & I2CD_M_TX_CMD) {
++    switch (type) {
-         if (i2c_send(bus->bus, bus->buf)) {
++    case 0:
-             bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
++        sz = MO_32;
-             i2c_end_transfer(bus->bus);
++        break;
-         } else {
++    case 1:
-             bus->intr_status |= I2CD_INTR_TX_ACK;
++        sz = MO_64;
-         }
++        break;
-+        bus->cmd &= ~I2CD_M_TX_CMD;
++    case 3:
-+    }
++        sz = MO_16;
++        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
--    } else if (bus->cmd & I2CD_M_RX_CMD) {
++            break;
-+    if (bus->cmd & I2CD_M_RX_CMD) {
++        }
-         int ret = i2c_recv(bus->bus);
++        /* fallthru */
-         if (ret < 0) {
++    default:
-             qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
+         unallocated_encoding(s);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
+         return;
              bus->intr_status |= I2CD_INTR_RX_DONE;
          }
          bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
 +        bus->cmd &= ~I2CD_M_RX_CMD;
      }
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
-     if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
+         return;
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
              i2c_end_transfer(bus->bus);
              bus->intr_status |= I2CD_INTR_NORMAL_STOP;
          }
 +        bus->cmd &= ~I2CD_M_STOP_CMD;
      }
--
--    /* command is handled, reset it and check for interrupts  */
+-    /* Zero extend sreg inputs to 64 bits now.  */
--    bus->cmd &= ~0xFFFF;
++    /* Zero extend sreg & hreg inputs to 64 bits now.  */
--    aspeed_i2c_bus_raise_interrupt(bus);
+     t_true = tcg_temp_new_i64();
- }
+     t_false = tcg_temp_new_i64();
+-    read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
- static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
+-    read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
++    read_vec_element(s, t_true, rn, 0, sz);
-         }
++    read_vec_element(s, t_false, rm, 0, sz);
-         aspeed_i2c_bus_handle_cmd(bus, value);
+     a64_test_cc(&c, cond);
-+        aspeed_i2c_bus_raise_interrupt(bus);
+     t_zero = tcg_const_i64(0);
-         break;
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
+     tcg_temp_free_i64(t_false);
-     default:
+     a64_free_cc(&c);
 -    /* Note that sregs write back zeros to the high bits,
 +    /* Note that sregs & hregs write back zeros to the high bits,
         and we've already done the zero-extension.  */
      write_fp_dreg(s, rd, t_true);
      tcg_temp_free_i64(t_true);
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 21/27] aspeed/i2c: handle LAST command under the RX command
+[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
-From: Cédric Le Goater <clg@kaod.org>
+From: Alex Bennée <alex.bennee@linaro.org>
-Today, the LAST command is handled with the STOP command but this is
+All the hard work is already done by vfp_expand_imm, we just need to
-incorrect. Also nack the I2C bus when a LAST is issued.
+make sure we pick up the correct size.
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Cc: qemu-stable@nongnu.org
-Message-id: 1494827476-1487-3-git-send-email-clg@kaod.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
 [rth: Merge unallocated_encoding check with TCGMemOp conversion.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/i2c/aspeed_i2c.c | 9 ++++++---
+ target/arm/translate-a64.c | 20 +++++++++++++++++---
-file changed, 6 insertions(+), 3 deletions(-)
+file changed, 17 insertions(+), 3 deletions(-)
-diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/aspeed_i2c.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/i2c/aspeed_i2c.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
-         bus->cmd &= ~I2CD_M_TX_CMD;
+ {
      int rd = extract32(insn, 0, 5);
      int imm8 = extract32(insn, 13, 8);
 -    int is_double = extract32(insn, 22, 2);
 +    int type = extract32(insn, 22, 2);
      uint64_t imm;
      TCGv_i64 tcg_res;
 +    TCGMemOp sz;
 -    if (is_double > 1) {
 +    switch (type) {
 +    case 0:
 +        sz = MO_32;
 +        break;
 +    case 1:
 +        sz = MO_64;
 +        break;
 +    case 3:
 +        sz = MO_16;
 +        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
 +            break;
 +        }
 +        /* fallthru */
 +    default:
          unallocated_encoding(s);
          return;
      }
+@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
--    if (bus->cmd & I2CD_M_RX_CMD) {
+         return;
 +    if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
          int ret = i2c_recv(bus->bus);
          if (ret < 0) {
              qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
              bus->intr_status |= I2CD_INTR_RX_DONE;
          }
          bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
 -        bus->cmd &= ~I2CD_M_RX_CMD;
 +        if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
 +            i2c_nack(bus->bus);
 +        }
 +        bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
      }
--    if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
+-    imm = vfp_expand_imm(MO_32 + is_double, imm8);
-+    if (bus->cmd & I2CD_M_STOP_CMD) {
++    imm = vfp_expand_imm(sz, imm8);
-         if (!i2c_bus_busy(bus->bus)) {
-             bus->intr_status |= I2CD_INTR_ABNORMAL;
+     tcg_res = tcg_const_i64(imm);
-         } else {
+     write_fp_dreg(s, rd, tcg_res);
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 02/27] load_uboot_image: don't assume a full header read
+[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
-From: Andrew Jones <drjones@redhat.com>
+From: Alex Bennée <alex.bennee@linaro.org>
-Don't allow load_uboot_image() to proceed when less bytes than
+We are meant to explicitly pass fpst, not cpu_env.
 header-size was read.
-Signed-off-by: Andrew Jones <drjones@redhat.com>
+Cc: qemu-stable@nongnu.org
-Message-id: 20170524091315.20284-1-drjones@redhat.com
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/core/loader.c | 3 ++-
+ target/arm/translate-a64.c | 3 ++-
 file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/core/loader.c b/hw/core/loader.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/loader.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/core/loader.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr,
+@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
-         return -1;
+         tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+         break;
-     size = read(fd, hdr, sizeof(uboot_image_header_t));
+     case 0x3: /* FSQRT */
--    if (size < 0)
+-        gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
-+    if (size < sizeof(uboot_image_header_t)) {
++        fpst = get_fpstatus_ptr(true);
-         goto out;
++        gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
-+    }
+         break;
+     case 0x8: /* FRINTN */
-     bswap_uboot_header(hdr);
+     case 0x9: /* FRINTP */
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 03/27] hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
+[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
-We were setting the VBPR1 field of VMCR_EL2 to icv_min_vbpr()
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 on reset, but this is not correct. The field should reset to
 the minimum value of ICV_BPR0_EL1 plus one.
+Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
+  The block length is predefined to 512 bits
+and "4.10.2 SD Status":
+  The SD Status contains status bits that are related to the SD Memory Card
+  proprietary features and may be used for future application-specific usage.
+  The size of the SD Status is one data block of 512 bit. The content of this
+  register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
+Thus the 16-bit CRC goes at offset 64.
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20180509060104.4458-3-f4bug@amsat.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1493226792-3237-2-git-send-email-peter.maydell@linaro.org
 ---
- hw/intc/arm_gicv3_cpuif.c | 2 +-
+ hw/sd/sd.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+diff --git a/hw/sd/sd.c b/hw/sd/sd.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
+--- a/hw/sd/sd.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
++++ b/hw/sd/sd.c
-@@ -XXX,XX +XXX,XX @@ static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
-     cs->ich_hcr_el2 = 0;
+         sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
-     memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2));
+     }
-     cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN |
+     memset(&sd->data[17], 0, 47);
--        (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR1_SHIFT) |
+-    stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
-+        ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) |
++    stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
          (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT);
  }
+ static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 04/27] hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
+Deleted patch
-icc_bpr_write() was not enforcing that writing a value below the
-minimum for the BPR should behave as if the BPR was set to the
-minimum value. This doesn't make a difference for the secure
-BPRs (since we define the minimum for the QEMU implementation
-as zero) but did mean we were allowing the NS BPR1 to be set to
-when 1 should be the lowest value.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1493226792-3237-3-git-send-email-peter.maydell@linaro.org
----
- hw/intc/arm_gicv3_cpuif.c | 6 ++++++
-file changed, 6 insertions(+)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
- {
-     GICv3CPUState *cs = icc_cs_from_env(env);
-     int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
-+    uint64_t minval;
-     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
-         icv_bpr_write(env, ri, value);
-@@ -XXX,XX +XXX,XX @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         return;
-     }
-+    minval = (grp == GICV3_G1NS) ? GIC_MIN_BPR_NS : GIC_MIN_BPR;
-+    if (value < minval) {
-+        value = minval;
-+    }
-+
-     cs->icc_bpr[grp] = value & 7;
-     gicv3_cpuif_update(cs);
- }
---
-.7.4

-[Qemu-devel] [PULL 05/27] hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
+Deleted patch
-When we calculate the mask to use to get the group priority from
-an interrupt priority, the way that NS BPR1 is handled differs
-from how BPR0 and S BPR1 work -- a BPR1 value of 1 means
-the group priority is in bits [7:1], whereas for BPR0 and S BPR1
-this is indicated by a 0 BPR value.
-Subtract 1 from the BPR value before creating the mask if
-we're using the NS BPR value, for both hardware and virtual
-interrupts, as the GICv3 pseudocode does, and fix the comments
-accordingly.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1493226792-3237-4-git-send-email-peter.maydell@linaro.org
----
- hw/intc/arm_gicv3_cpuif.c | 42 ++++++++++++++++++++++++++++++++++++++----
-file changed, 38 insertions(+), 4 deletions(-)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group)
- {
-     /* Return a mask word which clears the subpriority bits from
-      * a priority value for a virtual interrupt in the specified group.
--     * This depends on the VBPR value:
-+     * This depends on the VBPR value.
-+     * If using VBPR0 then:
-      *  a BPR of 0 means the group priority bits are [7:1];
-      *  a BPR of 1 means they are [7:2], and so on down to
-      *  a BPR of 7 meaning no group priority bits at all.
-+     * If using VBPR1 then:
-+     *  a BPR of 0 is impossible (the minimum value is 1)
-+     *  a BPR of 1 means the group priority bits are [7:1];
-+     *  a BPR of 2 means they are [7:2], and so on down to
-+     *  a BPR of 7 meaning the group priority is [7].
-+     *
-      * Which BPR to use depends on the group of the interrupt and
-      * the current ICH_VMCR_EL2.VCBPR settings.
-+     *
-+     * This corresponds to the VGroupBits() pseudocode.
-      */
-+    int bpr;
-+
-     if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
-         group = GICV3_G0;
-     }
--    return ~0U << (read_vbpr(cs, group) + 1);
-+    bpr = read_vbpr(cs, group);
-+    if (group == GICV3_G1NS) {
-+        assert(bpr > 0);
-+        bpr--;
-+    }
-+
-+    return ~0U << (bpr + 1);
- }
- static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
-@@ -XXX,XX +XXX,XX @@ static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group)
- {
-     /* Return a mask word which clears the subpriority bits from
-      * a priority value for an interrupt in the specified group.
--     * This depends on the BPR value:
-+     * This depends on the BPR value. For CBPR0 (S or NS):
-      *  a BPR of 0 means the group priority bits are [7:1];
-      *  a BPR of 1 means they are [7:2], and so on down to
-      *  a BPR of 7 meaning no group priority bits at all.
-+     * For CBPR1 NS:
-+     *  a BPR of 0 is impossible (the minimum value is 1)
-+     *  a BPR of 1 means the group priority bits are [7:1];
-+     *  a BPR of 2 means they are [7:2], and so on down to
-+     *  a BPR of 7 meaning the group priority is [7].
-+     *
-      * Which BPR to use depends on the group of the interrupt and
-      * the current ICC_CTLR.CBPR settings.
-+     *
-+     * This corresponds to the GroupBits() pseudocode.
-      */
-+    int bpr;
-+
-     if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) ||
-         (group == GICV3_G1NS &&
-          cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) {
-         group = GICV3_G0;
-     }
--    return ~0U << ((cs->icc_bpr[group] & 7) + 1);
-+    bpr = cs->icc_bpr[group] & 7;
-+
-+    if (group == GICV3_G1NS) {
-+        assert(bpr > 0);
-+        bpr--;
-+    }
-+
-+    return ~0U << (bpr + 1);
- }
- static bool icc_no_enabled_hppi(GICv3CPUState *cs)
---
-.7.4

-[Qemu-devel] [PULL 07/27] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
+Deleted patch
-When identifying the DFSR format for an alignment fault, use
-the mmu index that we are passed, rather than calling cpu_mmu_index()
-to get the mmu index for the current CPU state. This doesn't actually
-make any difference since the only cases where the current MMU index
-differs from the index used for the load are the "unprivileged
-load/store" instructions, and in that case the mmu index may
-differ but the translation regime is the same (apart from the
-"use from Hyp mode" case which is UNPREDICTABLE).
-However it's the more logical thing to do.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1493122030-32191-2-git-send-email-peter.maydell@linaro.org
----
- target/arm/op_helper.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/op_helper.c
-+++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
-     /* the DFSR for an alignment fault depends on whether we're using
-      * the LPAE long descriptor format, or the short descriptor format
-      */
--    if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
-+    if (arm_s1_regime_using_lpae_format(env, mmu_idx)) {
-         env->exception.fsr = (1 << 9) | 0x21;
-     } else {
-         env->exception.fsr = 0x1;
---
-.7.4

-[Qemu-devel] [PULL 09/27] arm: Use different ARMMMUIdx values for M profile
+Deleted patch
-Make M profile use completely separate ARMMMUIdx values from
-those that A profile CPUs use. This is a prelude to adding
-support for the MPU and for v8M, which together will require
-MMU indexes which don't map cleanly onto the A profile
-uses:
- non secure User
- non secure Privileged
- non secure Privileged, execution priority < 0
- secure User
- secure Privileged
- secure Privileged, execution priority < 0
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1493122030-32191-4-git-send-email-peter.maydell@linaro.org
----
- target/arm/cpu.h       | 21 +++++++++++++++++++--
- target/arm/helper.c    |  5 +++++
- target/arm/translate.c |  3 +++
-files changed, 27 insertions(+), 2 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
-  * of the AT/ATS operations.
-  * The values used are carefully arranged to make mmu_idx => EL lookup easy.
-  */
--#define ARM_MMU_IDX_A 0x10 /* A profile (and M profile, for the moment) */
-+#define ARM_MMU_IDX_A 0x10 /* A profile */
- #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
-+#define ARM_MMU_IDX_M 0x40 /* M profile */
- #define ARM_MMU_IDX_TYPE_MASK (~0x7)
- #define ARM_MMU_IDX_COREIDX_MASK 0x7
-@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
-     ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
-     ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
-     ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
-+    ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
-+    ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
-     /* Indexes below here don't have TLBs and are used only for AT system
-      * instructions or for the first stage of an S12 page table walk.
-      */
-@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
-     ARMMMUIdxBit_S1SE0 = 1 << 4,
-     ARMMMUIdxBit_S1SE1 = 1 << 5,
-     ARMMMUIdxBit_S2NS = 1 << 6,
-+    ARMMMUIdxBit_MUser = 1 << 0,
-+    ARMMMUIdxBit_MPriv = 1 << 1,
- } ARMMMUIdxBit;
- #define MMU_USER_IDX 0
-@@ -XXX,XX +XXX,XX @@ static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
- static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
- {
--    return mmu_idx | ARM_MMU_IDX_A;
-+    if (arm_feature(env, ARM_FEATURE_M)) {
-+        return mmu_idx | ARM_MMU_IDX_M;
-+    } else {
-+        return mmu_idx | ARM_MMU_IDX_A;
-+    }
- }
- /* Return the exception level we're running at if this is our mmu_idx */
-@@ -XXX,XX +XXX,XX @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
-     switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
-     case ARM_MMU_IDX_A:
-         return mmu_idx & 3;
-+    case ARM_MMU_IDX_M:
-+        return mmu_idx & 1;
-     default:
-         g_assert_not_reached();
-     }
-@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
- {
-     int el = arm_current_el(env);
-+    if (arm_feature(env, ARM_FEATURE_M)) {
-+        ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
-+
-+        return arm_to_core_mmu_idx(mmu_idx);
-+    }
-+
-     if (el < 2 && arm_is_secure_below_el3(env)) {
-         return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
-     }
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
-     case ARMMMUIdx_S1SE1:
-     case ARMMMUIdx_S1NSE0:
-     case ARMMMUIdx_S1NSE1:
-+    case ARMMMUIdx_MPriv:
-+    case ARMMMUIdx_MUser:
-         return 1;
-     default:
-         g_assert_not_reached();
-@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
-     case ARMMMUIdx_S1NSE1:
-     case ARMMMUIdx_S1E2:
-     case ARMMMUIdx_S2NS:
-+    case ARMMMUIdx_MPriv:
-+    case ARMMMUIdx_MUser:
-         return false;
-     case ARMMMUIdx_S1E3:
-     case ARMMMUIdx_S1SE0:
-@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
-     switch (mmu_idx) {
-     case ARMMMUIdx_S1SE0:
-     case ARMMMUIdx_S1NSE0:
-+    case ARMMMUIdx_MUser:
-         return true;
-     default:
-         return false;
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
-     case ARMMMUIdx_S1SE0:
-     case ARMMMUIdx_S1SE1:
-         return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0);
-+    case ARMMMUIdx_MUser:
-+    case ARMMMUIdx_MPriv:
-+        return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
-     case ARMMMUIdx_S2NS:
-     default:
-         g_assert_not_reached();
---
-.7.4

-[Qemu-devel] [PULL 10/27] arm: Clean up handling of no-MPU PMSA CPUs
+Deleted patch
-ARM CPUs come in two flavours:
- * proper MMU ("VMSA")
- * only an MPU ("PMSA")
-For PMSA, the MPU may be implemented, or not (in which case there
-is default "always acts the same" behaviour, but it isn't guest
-programmable).
-QEMU is a bit confused about how we indicate this: we have an
-ARM_FEATURE_MPU, but it's not clear whether this indicates
-"PMSA, not VMSA" or "PMSA and MPU present" , and sometimes we
-use it for one purpose and sometimes the other.
-Currently trying to implement a PMSA-without-MPU core won't
-work correctly because we turn off the ARM_FEATURE_MPU bit
-and then a lot of things which should still exist get
-turned off too.
-As the first step in cleaning this up, rename the feature
-bit to ARM_FEATURE_PMSA, which indicates a PMSA CPU (with
-or without MPU).
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1493122030-32191-5-git-send-email-peter.maydell@linaro.org
----
- target/arm/cpu.h     |  2 +-
- target/arm/cpu.c     | 12 ++++++------
- target/arm/helper.c  | 12 ++++++------
- target/arm/machine.c |  2 +-
-files changed, 14 insertions(+), 14 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ enum arm_features {
-     ARM_FEATURE_V6K,
-     ARM_FEATURE_V7,
-     ARM_FEATURE_THUMB2,
--    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
-+    ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
-     ARM_FEATURE_VFP3,
-     ARM_FEATURE_VFP_FP16,
-     ARM_FEATURE_NEON,
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
-                                  &error_abort);
-     }
--    if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
-+    if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
-         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
-                                  &error_abort);
-         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-     if (arm_feature(env, ARM_FEATURE_V7) &&
-         !arm_feature(env, ARM_FEATURE_M) &&
--        !arm_feature(env, ARM_FEATURE_MPU)) {
-+        !arm_feature(env, ARM_FEATURE_PMSA)) {
-         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
-          * can use 4K pages.
-          */
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-     }
-     if (!cpu->has_mpu) {
--        unset_feature(env, ARM_FEATURE_MPU);
-+        unset_feature(env, ARM_FEATURE_PMSA);
-     }
--    if (arm_feature(env, ARM_FEATURE_MPU) &&
-+    if (arm_feature(env, ARM_FEATURE_PMSA) &&
-         arm_feature(env, ARM_FEATURE_V7)) {
-         uint32_t nr = cpu->pmsav7_dregion;
-@@ -XXX,XX +XXX,XX @@ static void arm946_initfn(Object *obj)
-     cpu->dtb_compatible = "arm,arm946";
-     set_feature(&cpu->env, ARM_FEATURE_V5);
--    set_feature(&cpu->env, ARM_FEATURE_MPU);
-+    set_feature(&cpu->env, ARM_FEATURE_PMSA);
-     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
-     cpu->midr = 0x41059461;
-     cpu->ctr = 0x0f004006;
-@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
-     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
-     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
-     set_feature(&cpu->env, ARM_FEATURE_V7MP);
--    set_feature(&cpu->env, ARM_FEATURE_MPU);
-+    set_feature(&cpu->env, ARM_FEATURE_PMSA);
-     cpu->midr = 0x411fc153; /* r1p3 */
-     cpu->id_pfr0 = 0x0131;
-     cpu->id_pfr1 = 0x001;
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
- {
-     ARMCPU *cpu = arm_env_get_cpu(env);
--    if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
-+    if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
-         && !extended_addresses_enabled(env)) {
-         /* For VMSA (when not using the LPAE long descriptor page table
-          * format) this register includes the ASID, so do a TLB flush.
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-         define_arm_cp_regs(cpu, v6k_cp_reginfo);
-     }
-     if (arm_feature(env, ARM_FEATURE_V7MP) &&
--        !arm_feature(env, ARM_FEATURE_MPU)) {
-+        !arm_feature(env, ARM_FEATURE_PMSA)) {
-         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
-     }
-     if (arm_feature(env, ARM_FEATURE_V7)) {
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-         }
-     }
--    if (arm_feature(env, ARM_FEATURE_MPU)) {
-+    if (arm_feature(env, ARM_FEATURE_PMSA)) {
-         if (arm_feature(env, ARM_FEATURE_V6)) {
-             /* PMSAv6 not implemented */
-             assert(arm_feature(env, ARM_FEATURE_V7));
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
-         }
-         define_arm_cp_regs(cpu, id_cp_reginfo);
--        if (!arm_feature(env, ARM_FEATURE_MPU)) {
-+        if (!arm_feature(env, ARM_FEATURE_PMSA)) {
-             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
-         } else if (arm_feature(env, ARM_FEATURE_V7)) {
-             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
-     /* pmsav7 has special handling for when MPU is disabled so call it before
-      * the common MMU/MPU disabled check below.
-      */
--    if (arm_feature(env, ARM_FEATURE_MPU) &&
-+    if (arm_feature(env, ARM_FEATURE_PMSA) &&
-         arm_feature(env, ARM_FEATURE_V7)) {
-         *page_size = TARGET_PAGE_SIZE;
-         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
-         return 0;
-     }
--    if (arm_feature(env, ARM_FEATURE_MPU)) {
-+    if (arm_feature(env, ARM_FEATURE_PMSA)) {
-         /* Pre-v7 MPU */
-         *page_size = TARGET_PAGE_SIZE;
-         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
-diff --git a/target/arm/machine.c b/target/arm/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/machine.c
-+++ b/target/arm/machine.c
-@@ -XXX,XX +XXX,XX @@ static bool pmsav7_needed(void *opaque)
-     ARMCPU *cpu = opaque;
-     CPUARMState *env = &cpu->env;
--    return arm_feature(env, ARM_FEATURE_MPU) &&
-+    return arm_feature(env, ARM_FEATURE_PMSA) &&
-            arm_feature(env, ARM_FEATURE_V7);
- }
---
-.7.4

-[Qemu-devel] [PULL 11/27] arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
+Deleted patch
-Fix the handling of QOM properties for PMSA CPUs with no MPU:
-Allow no-MPU to be specified by either:
- * has-mpu = false
- * pmsav7_dregion = 0
-and make setting one imply the other. Don't clear the PMSA
-feature bit in this situation.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1493122030-32191-6-git-send-email-peter.maydell@linaro.org
----
- target/arm/cpu.c | 8 +++++++-
-file changed, 7 insertions(+), 1 deletion(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-         cpu->id_pfr1 &= ~0xf000;
-     }
-+    /* MPU can be configured out of a PMSA CPU either by setting has-mpu
-+     * to false or by setting pmsav7-dregion to 0.
-+     */
-     if (!cpu->has_mpu) {
--        unset_feature(env, ARM_FEATURE_PMSA);
-+        cpu->pmsav7_dregion = 0;
-+    }
-+    if (cpu->pmsav7_dregion == 0) {
-+        cpu->has_mpu = false;
-     }
-     if (arm_feature(env, ARM_FEATURE_PMSA) &&
---
-.7.4

-[Qemu-devel] [PULL 12/27] arm: Don't let no-MPU PMSA cores write to SCTLR.M
+Deleted patch
-If the CPU is a PMSA config with no MPU implemented, then the
-SCTLR.M bit should be RAZ/WI, so that the guest can never
-turn on the non-existent MPU.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1493122030-32191-7-git-send-email-peter.maydell@linaro.org
----
- target/arm/helper.c | 5 +++++
-file changed, 5 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         return;
-     }
-+    if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
-+        /* M bit is RAZ/WI for PMSA with no MPU implemented */
-+        value &= ~SCTLR_M;
-+    }
-+
-     raw_write(env, ri, value);
-     /* ??? Lots of these bits are not implemented.  */
-     /* This may enable/disable the MMU, so do a TLB flush.  */
---
-.7.4

-[Qemu-devel] [PULL 13/27] arm: Remove unnecessary check on cpu->pmsav7_dregion
+Deleted patch
-Now that we enforce both:
- * pmsav7_dregion == 0 implies has_mpu == false
- * PMSA with has_mpu == false means SCTLR.M cannot be set
-we can remove a check on pmsav7_dregion from get_phys_addr_pmsav7(),
-because we can only reach this code path if the MPU is enabled
-(and so region_translation_disabled() returned false).
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1493122030-32191-8-git-send-email-peter.maydell@linaro.org
----
- target/arm/helper.c | 3 +--
-file changed, 1 insertion(+), 2 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
-         }
-         if (n == -1) { /* no hits */
--            if (cpu->pmsav7_dregion &&
--                (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
-+            if (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR)) {
-                 /* background fault */
-                 *fsr = 0;
-                 return true;
---
-.7.4

-[Qemu-devel] [PULL 17/27] armv7m: Classify faults as MemManage or BusFault
+Deleted patch
-From: Michael Davidsaver <mdavidsaver@gmail.com>
-General logic is that operations stopped by the MPU are MemManage,
-and those which go through the MPU and are caught by the unassigned
-handle are BusFault. Distinguish these by looking at the
-exception.fsr values, and set the CFSR bits and (if appropriate)
-fill in the BFAR or MMFAR with the exception address.
-Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
-Message-id: 1493122030-32191-12-git-send-email-peter.maydell@linaro.org
-[PMM: i-side faults do not set BFAR/MMFAR, only d-side;
- added some CPU_LOG_INT logging]
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
----
- target/arm/helper.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
-file changed, 42 insertions(+), 3 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
-         break;
-     case EXCP_PREFETCH_ABORT:
-     case EXCP_DATA_ABORT:
--        /* TODO: if we implemented the MPU registers, this is where we
--         * should set the MMFAR, etc from exception.fsr and exception.vaddress.
-+        /* Note that for M profile we don't have a guest facing FSR, but
-+         * the env->exception.fsr will be populated by the code that
-+         * raises the fault, in the A profile short-descriptor format.
-          */
--        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
-+        switch (env->exception.fsr & 0xf) {
-+        case 0x8: /* External Abort */
-+            switch (cs->exception_index) {
-+            case EXCP_PREFETCH_ABORT:
-+                env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK;
-+                qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n");
-+                break;
-+            case EXCP_DATA_ABORT:
-+                env->v7m.cfsr |=
-+                    (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
-+                env->v7m.bfar = env->exception.vaddress;
-+                qemu_log_mask(CPU_LOG_INT,
-+                              "...with CFSR.IBUSERR and BFAR 0x%x\n",
-+                              env->v7m.bfar);
-+                break;
-+            }
-+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
-+            break;
-+        default:
-+            /* All other FSR values are either MPU faults or "can't happen
-+             * for M profile" cases.
-+             */
-+            switch (cs->exception_index) {
-+            case EXCP_PREFETCH_ABORT:
-+                env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK;
-+                qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n");
-+                break;
-+            case EXCP_DATA_ABORT:
-+                env->v7m.cfsr |=
-+                    (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);
-+                env->v7m.mmfar = env->exception.vaddress;
-+                qemu_log_mask(CPU_LOG_INT,
-+                              "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
-+                              env->v7m.mmfar);
-+                break;
-+            }
-+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
-+            break;
-+        }
-         break;
-     case EXCP_BKPT:
-         if (semihosting_enabled()) {
---
-.7.4

-[Qemu-devel] [PULL 19/27] arm: Implement HFNMIENA support for M profile MPU
+[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
-Implement HFNMIENA support for the M profile MPU. This bit controls
+Usually the logging of the CPU state produced by -d cpu is sufficient
-whether the MPU is treated as enabled when executing at execution
+to diagnose problems, but sometimes you want to see the state of
-priorities of less than zero (in NMI, HardFault or with the FAULTMASK
+the floating point registers as well. We don't want to enable that
-bit set).
+by default as it adds a lot of extra data to the log; instead,
+allow it to be optionally enabled via -d fpu.
 Doing this requires us to use a different MMU index for "running
 at execution priority < 0", because we will have different
 access permissions for that case versus the normal case.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1493122030-32191-14-git-send-email-peter.maydell@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
 ---
- target/arm/cpu.h       | 24 +++++++++++++++++++++++-
+ include/qemu/log.h   | 1 +
- target/arm/helper.c    | 18 +++++++++++++++++-
+ accel/tcg/cpu-exec.c | 9 ++++++---
- target/arm/translate.c |  1 +
+ util/log.c           | 2 ++
-files changed, 41 insertions(+), 2 deletions(-)
+files changed, 9 insertions(+), 3 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/include/qemu/log.h b/include/qemu/log.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/include/qemu/log.h
-+++ b/target/arm/cpu.h
++++ b/include/qemu/log.h
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
+@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
-  * for the accesses done as part of a stage 1 page table walk, rather than
+ #define CPU_LOG_PAGE       (1 << 14)
-  * having to walk the stage 2 page table over and over.)
+ /* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
-  *
+ #define CPU_LOG_TB_OP_IND  (1 << 16)
-+ * R profile CPUs have an MPU, but can use the same set of MMU indexes
++#define CPU_LOG_TB_FPU     (1 << 17)
-+ * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
-+ * NS EL2 if we ever model a Cortex-R52).
+ /* Lock output for a series of related logs.  Since this is not needed
-+ *
+  * for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
-+ * M profile CPUs are rather different as they do not have a true MMU.
+diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
-+ * They have the following different MMU indexes:
+index XXXXXXX..XXXXXXX 100644
-+ *  User
+--- a/accel/tcg/cpu-exec.c
-+ *  Privileged
++++ b/accel/tcg/cpu-exec.c
-+ *  Execution priority negative (this is like privileged, but the
+@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
-+ *  MPU HFNMIENA bit means that it may have different access permission
+     if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
-+ *  check results to normal privileged code, so can't share a TLB).
+         && qemu_log_in_addr_range(itb->pc)) {
-+ *
+         qemu_log_lock();
-  * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
++        int flags = 0;
-  * are not quite the same -- different CPU types (most notably M profile
++        if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
-  * vs A/R profile) would like to use MMU indexes with different semantics,
++            flags |= CPU_DUMP_FPU;
-@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
++        }
-     ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
+ #if defined(TARGET_I386)
-     ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
+-        log_cpu_state(cpu, CPU_DUMP_CCOP);
-     ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
+-#else
-+    ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M,
+-        log_cpu_state(cpu, 0);
-     /* Indexes below here don't have TLBs and are used only for AT system
++        flags |= CPU_DUMP_CCOP;
-      * instructions or for the first stage of an S12 page table walk.
+ #endif
-      */
++        log_cpu_state(cpu, flags);
-@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
+         qemu_log_unlock();
      ARMMMUIdxBit_S2NS = 1 << 6,
      ARMMMUIdxBit_MUser = 1 << 0,
      ARMMMUIdxBit_MPriv = 1 << 1,
 +    ARMMMUIdxBit_MNegPri = 1 << 2,
  } ARMMMUIdxBit;
  #define MMU_USER_IDX 0
@@ -XXX,XX +XXX,XX @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
      case ARM_MMU_IDX_A:
          return mmu_idx & 3;
      case ARM_MMU_IDX_M:
 -        return mmu_idx & 1;
 +        return mmu_idx == ARMMMUIdx_MUser ? 0 : 1;
      default:
          g_assert_not_reached();
      }
-@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
+ #endif /* DEBUG_DISAS */
-     if (arm_feature(env, ARM_FEATURE_M)) {
+diff --git a/util/log.c b/util/log.c
          ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
 +        /* Execution priority is negative if FAULTMASK is set or
 +         * we're in a HardFault or NMI handler.
 +         */
 +        if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
 +            || env->daif & PSTATE_F) {
 +            return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri);
 +        }
 +
          return arm_to_core_mmu_idx(mmu_idx);
      }
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/util/log.c
-+++ b/target/arm/helper.c
++++ b/util/log.c
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
+@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
-     case ARMMMUIdx_S1NSE0:
+       "show trace before each executed TB (lots of logs)" },
-     case ARMMMUIdx_S1NSE1:
+     { CPU_LOG_TB_CPU, "cpu",
-     case ARMMMUIdx_MPriv:
+       "show CPU registers before entering a TB (lots of logs)" },
-+    case ARMMMUIdx_MNegPri:
++    { CPU_LOG_TB_FPU, "fpu",
-     case ARMMMUIdx_MUser:
++      "include FPU registers in the 'cpu' logging" },
-         return 1;
+     { CPU_LOG_MMU, "mmu",
-     default:
+       "log MMU-related activities" },
-@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
+     { CPU_LOG_PCALL, "pcall",
      case ARMMMUIdx_S1E2:
      case ARMMMUIdx_S2NS:
      case ARMMMUIdx_MPriv:
 +    case ARMMMUIdx_MNegPri:
      case ARMMMUIdx_MUser:
          return false;
      case ARMMMUIdx_S1E3:
@@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env,
                                                 ARMMMUIdx mmu_idx)
  {
      if (arm_feature(env, ARM_FEATURE_M)) {
 -        return !(env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_ENABLE_MASK);
 +        switch (env->v7m.mpu_ctrl &
 +                (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
 +        case R_V7M_MPU_CTRL_ENABLE_MASK:
 +            /* Enabled, but not for HardFault and NMI */
 +            return mmu_idx == ARMMMUIdx_MNegPri;
 +        case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
 +            /* Enabled for all cases */
 +            return false;
 +        case 0:
 +        default:
 +            /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
 +             * we warned about that in armv7m_nvic.c when the guest set it.
 +             */
 +            return true;
 +        }
      }
      if (mmu_idx == ARMMMUIdx_S2NS) {
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
          return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0);
      case ARMMMUIdx_MUser:
      case ARMMMUIdx_MPriv:
 +    case ARMMMUIdx_MNegPri:
          return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
      case ARMMMUIdx_S2NS:
      default:
 --
-.7.4
+.17.0

-[Qemu-devel] [PULL 23/27] aspeed: add some I2C devices to the Aspeed machines
+Deleted patch
-From: Cédric Le Goater <clg@kaod.org>
-Let's add an RTC to the palmetto BMC and a LM75 temperature sensor to
-the AST2500 EVB to start with.
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 1494827476-1487-5-git-send-email-clg@kaod.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/aspeed.c | 27 +++++++++++++++++++++++++++
-file changed, 27 insertions(+)
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
-+++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardConfig {
-     const char *fmc_model;
-     const char *spi_model;
-     uint32_t num_cs;
-+    void (*i2c_init)(AspeedBoardState *bmc);
- } AspeedBoardConfig;
- enum {
-@@ -XXX,XX +XXX,XX @@ enum {
-         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
-         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
-+static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
-+static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
-+
- static const AspeedBoardConfig aspeed_boards[] = {
-     [PALMETTO_BMC] = {
-         .soc_name  = "ast2400-a1",
-@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
-         .fmc_model = "n25q256a",
-         .spi_model = "mx25l25635e",
-         .num_cs    = 1,
-+        .i2c_init  = palmetto_bmc_i2c_init,
-     },
-     [AST2500_EVB]  = {
-         .soc_name  = "ast2500-a1",
-@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
-         .fmc_model = "n25q256a",
-         .spi_model = "mx25l25635e",
-         .num_cs    = 1,
-+        .i2c_init  = ast2500_evb_i2c_init,
-     },
-     [ROMULUS_BMC]  = {
-         .soc_name  = "ast2500-a1",
-@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
-     aspeed_board_binfo.ram_size = ram_size;
-     aspeed_board_binfo.loader_start = sc->info->sdram_base;
-+    if (cfg->i2c_init) {
-+        cfg->i2c_init(bmc);
-+    }
-+
-     arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
- }
-+static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
-+{
-+    AspeedSoCState *soc = &bmc->soc;
-+
-+    /* The palmetto platform expects a ds3231 RTC but a ds1338 is
-+     * enough to provide basic RTC features. Alarms will be missing */
-+    i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
-+}
-+
- static void palmetto_bmc_init(MachineState *machine)
- {
-     aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]);
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo palmetto_bmc_type = {
-     .class_init = palmetto_bmc_class_init,
- };
-+static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
-+{
-+    AspeedSoCState *soc = &bmc->soc;
-+
-+    /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
-+    i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
-+}
-+
- static void ast2500_evb_init(MachineState *machine)
- {
-     aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]);
---
-.7.4

-[Qemu-devel] [PULL 25/27] aspeed: add a temp sensor device on I2C bus 3
+Deleted patch
-From: Cédric Le Goater <clg@kaod.org>
-Temperatures can be changed from the monitor with :
-    (qemu) qom-set /machine/unattached/device[2] temperature0 12000
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 1494827476-1487-7-git-send-email-clg@kaod.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/aspeed.c | 9 +++++++++
-file changed, 9 insertions(+)
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
-+++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
- static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
- {
-     AspeedSoCState *soc = &bmc->soc;
-+    DeviceState *dev;
-     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
-      * enough to provide basic RTC features. Alarms will be missing */
-     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
-+
-+    /* add a TMP423 temperature sensor */
-+    dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
-+                           "tmp423", 0x4c);
-+    object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
-+    object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
-+    object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
-+    object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
- }
- static void palmetto_bmc_init(MachineState *machine)
---
-.7.4

ARM pullreq; contains some patches that arrived while I
was on holiday, plus the series I sent off before going
away, which got reviewed while I was away.

thanks
-- PMM

The following changes since commit c077a998eb3fcae2d048e3baeb5bc592d30fddde:

Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20170531' into staging (2017-06-01 15:50:40 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170601

for you to fetch changes up to cdc58be430b0bdeaef282e2e70f8135ae531616d:

hw/arm/virt: fdt: generate distance-map when needed (2017-06-01 17:27:07 +0100)

----------------------------------------------------------------
target-arm queue:
 * virt: numa: provide ACPI distance info when needed
 * aspeed: fix i2c controller bugs
 * aspeed: add temperature sensor device
 * M profile: support MPU
 * gicv3: fix mishandling of BPR1, VBPR1
 * load_uboot_image: don't assume a full header read
 * libvixl: Correct build failures on NetBSD

----------------------------------------------------------------
Andrew Jones (3):
      load_uboot_image: don't assume a full header read
      hw/arm/virt-acpi-build: build SLIT when needed
      hw/arm/virt: fdt: generate distance-map when needed

Cédric Le Goater (6):
      aspeed/i2c: improve command handling
      aspeed/i2c: handle LAST command under the RX command
      aspeed/i2c: introduce a state machine
      aspeed: add some I2C devices to the Aspeed machines
      hw/misc: add a TMP42{1,2,3} device model
      aspeed: add a temp sensor device on I2C bus 3

Kamil Rytarowski (1):
      libvixl: Correct build failures on NetBSD

Michael Davidsaver (4):
      armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
      armv7m: Implement M profile default memory map
      armv7m: Classify faults as MemManage or BusFault
      arm: add MPU support to M profile CPUs

Peter Maydell (12):
      hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
      hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
      hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
      arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
      arm: Add support for M profile CPUs having different MMU index semantics
      arm: Use different ARMMMUIdx values for M profile
      arm: Clean up handling of no-MPU PMSA CPUs
      arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
      arm: Don't let no-MPU PMSA cores write to SCTLR.M
      arm: Remove unnecessary check on cpu->pmsav7_dregion
      arm: All M profile cores are PMSA
      arm: Implement HFNMIENA support for M profile MPU

Wei Huang (1):
      target/arm: clear PMUVER field of AA64DFR0 when vPMU=off

From: Kamil Rytarowski <n54@gmx.com>

Ensure that C99 macros are defined regardless of the inclusion order of
headers in vixl. This is required at least on NetBSD.

The vixl/globals.h headers defines __STDC_CONSTANT_MACROS and must be
included before other system headers.

This file defines unconditionally the following macros, without altering
the original sources:
 - __STDC_CONSTANT_MACROS
 - __STDC_LIMIT_MACROS
 - __STDC_FORMAT_MACROS

Signed-off-by: Kamil Rytarowski <n54@gmx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170514051820.15985-1-n54@gmx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 disas/libvixl/Makefile.objs | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/disas/libvixl/Makefile.objs b/disas/libvixl/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/disas/libvixl/Makefile.objs
+++ b/disas/libvixl/Makefile.objs
@@ -XXX,XX +XXX,XX @@ libvixl_OBJS = vixl/utils.o \
 # The -Wno-sign-compare is needed only for gcc 4.6, which complains about
 # some signed-unsigned equality comparisons which later gcc versions do not.
 $(addprefix $(obj)/,$(libvixl_OBJS)): QEMU_CFLAGS := -I$(SRC_PATH)/disas/libvixl $(QEMU_CFLAGS) -Wno-sign-compare
+# Ensure that C99 macros are defined regardless of the inclusion order of
+# headers in vixl. This is required at least on NetBSD.
+$(addprefix $(obj)/,$(libvixl_OBJS)): QEMU_CFLAGS += -D__STDC_CONSTANT_MACROS -D__STDC_LIMIT_MACROS -D__STDC_FORMAT_MACROS
 
 common-obj-$(CONFIG_ARM_A64_DIS) += $(libvixl_OBJS)
-- 
2.7.4

We were setting the VBPR1 field of VMCR_EL2 to icv_min_vbpr()
on reset, but this is not correct. The field should reset to
the minimum value of ICV_BPR0_EL1 plus one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493226792-3237-2-git-send-email-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
     cs->ich_hcr_el2 = 0;
     memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2));
     cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN |
-        (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR1_SHIFT) |
+        ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) |
         (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT);
 }
 
-- 
2.7.4

icc_bpr_write() was not enforcing that writing a value below the
minimum for the BPR should behave as if the BPR was set to the
minimum value. This doesn't make a difference for the secure
BPRs (since we define the minimum for the QEMU implementation
as zero) but did mean we were allowing the NS BPR1 to be set to
0 when 1 should be the lowest value.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493226792-3237-3-git-send-email-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
+    uint64_t minval;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         icv_bpr_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         return;
     }
 
+    minval = (grp == GICV3_G1NS) ? GIC_MIN_BPR_NS : GIC_MIN_BPR;
+    if (value < minval) {
+        value = minval;
+    }
+
     cs->icc_bpr[grp] = value & 7;
     gicv3_cpuif_update(cs);
 }
-- 
2.7.4

When we calculate the mask to use to get the group priority from
an interrupt priority, the way that NS BPR1 is handled differs
from how BPR0 and S BPR1 work -- a BPR1 value of 1 means
the group priority is in bits [7:1], whereas for BPR0 and S BPR1
this is indicated by a 0 BPR value.

Subtract 1 from the BPR value before creating the mask if
we're using the NS BPR value, for both hardware and virtual
interrupts, as the GICv3 pseudocode does, and fix the comments
accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493226792-3237-4-git-send-email-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 42 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 38 insertions(+), 4 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group)
 {
     /* Return a mask word which clears the subpriority bits from
      * a priority value for a virtual interrupt in the specified group.
-     * This depends on the VBPR value:
+     * This depends on the VBPR value.
+     * If using VBPR0 then:
      *  a BPR of 0 means the group priority bits are [7:1];
      *  a BPR of 1 means they are [7:2], and so on down to
      *  a BPR of 7 meaning no group priority bits at all.
+     * If using VBPR1 then:
+     *  a BPR of 0 is impossible (the minimum value is 1)
+     *  a BPR of 1 means the group priority bits are [7:1];
+     *  a BPR of 2 means they are [7:2], and so on down to
+     *  a BPR of 7 meaning the group priority is [7].
+     *
      * Which BPR to use depends on the group of the interrupt and
      * the current ICH_VMCR_EL2.VCBPR settings.
+     *
+     * This corresponds to the VGroupBits() pseudocode.
      */
+    int bpr;
+
     if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
         group = GICV3_G0;
     }
 
-    return ~0U << (read_vbpr(cs, group) + 1);
+    bpr = read_vbpr(cs, group);
+    if (group == GICV3_G1NS) {
+        assert(bpr > 0);
+        bpr--;
+    }
+
+    return ~0U << (bpr + 1);
 }
 
 static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
@@ -XXX,XX +XXX,XX @@ static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group)
 {
     /* Return a mask word which clears the subpriority bits from
      * a priority value for an interrupt in the specified group.
-     * This depends on the BPR value:
+     * This depends on the BPR value. For CBPR0 (S or NS):
      *  a BPR of 0 means the group priority bits are [7:1];
      *  a BPR of 1 means they are [7:2], and so on down to
      *  a BPR of 7 meaning no group priority bits at all.
+     * For CBPR1 NS:
+     *  a BPR of 0 is impossible (the minimum value is 1)
+     *  a BPR of 1 means the group priority bits are [7:1];
+     *  a BPR of 2 means they are [7:2], and so on down to
+     *  a BPR of 7 meaning the group priority is [7].
+     *
      * Which BPR to use depends on the group of the interrupt and
      * the current ICC_CTLR.CBPR settings.
+     *
+     * This corresponds to the GroupBits() pseudocode.
      */
+    int bpr;
+
     if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) ||
         (group == GICV3_G1NS &&
          cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) {
         group = GICV3_G0;
     }
 
-    return ~0U << ((cs->icc_bpr[group] & 7) + 1);
+    bpr = cs->icc_bpr[group] & 7;
+
+    if (group == GICV3_G1NS) {
+        assert(bpr > 0);
+        bpr--;
+    }
+
+    return ~0U << (bpr + 1);
 }
 
 static bool icc_no_enabled_hppi(GICv3CPUState *cs)
-- 
2.7.4

From: Wei Huang <wei@redhat.com>

The PMUv3 driver of linux kernel (in arch/arm64/kernel/perf_event.c)
relies on the PMUVER field of id_aa64dfr0_el1 to decide if PMU support
is present or not. This patch clears the PMUVER field under TCG mode
when vPMU=off. Without it, PMUv3 will init insider guest VMs even
with vPMU=off. This patch also removes a redundant line inside the
if-statement.

Signed-off-by: Wei Huang <wei@redhat.com>
Message-id: 1495123889-32301-1-git-send-email-wei@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     if (!cpu->has_pmu) {
-        cpu->has_pmu = false;
         unset_feature(env, ARM_FEATURE_PMU);
+        cpu->id_aa64dfr0 &= ~0xf00;
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
-- 
2.7.4

When identifying the DFSR format for an alignment fault, use
the mmu index that we are passed, rather than calling cpu_mmu_index()
to get the mmu index for the current CPU state. This doesn't actually
make any difference since the only cases where the current MMU index
differs from the index used for the load are the "unprivileged
load/store" instructions, and in that case the mmu index may
differ but the translation regime is the same (apart from the
"use from Hyp mode" case which is UNPREDICTABLE).
However it's the more logical thing to do.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-2-git-send-email-peter.maydell@linaro.org
---
 target/arm/op_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
     /* the DFSR for an alignment fault depends on whether we're using
      * the LPAE long descriptor format, or the short descriptor format
      */
-    if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
+    if (arm_s1_regime_using_lpae_format(env, mmu_idx)) {
         env->exception.fsr = (1 << 9) | 0x21;
     } else {
         env->exception.fsr = 0x1;
-- 
2.7.4

The M profile CPU's MPU has an awkward corner case which we
would like to implement with a different MMU index.

We can avoid having to bump the number of MMU modes ARM
uses, because some of our existing MMU indexes are only
used by non-M-profile CPUs, so we can borrow one.
To avoid that getting too confusing, clean up the code
to try to keep the two meanings of the index separate.

Instead of ARMMMUIdx enum values being identical to core QEMU
MMU index values, they are now the core index values with some
high bits set. Any particular CPU always uses the same high
bits (so eventually A profile cores and M profile cores will
use different bits). New functions arm_to_core_mmu_idx()
and core_to_arm_mmu_idx() convert between the two.

In general core index values are stored in 'int' types, and
ARM values are stored in ARMMMUIdx types.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1493122030-32191-3-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h           |  71 ++++++++++++++++-----
 target/arm/translate.h     |   2 +-
 target/arm/helper.c        | 151 ++++++++++++++++++++++++---------------------
 target/arm/op_helper.c     |   3 +-
 target/arm/translate-a64.c |  18 ++++--
 target/arm/translate.c     |  10 +--
 6 files changed, 156 insertions(+), 99 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
  * for the accesses done as part of a stage 1 page table walk, rather than
  * having to walk the stage 2 page table over and over.)
  *
+ * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
+ * are not quite the same -- different CPU types (most notably M profile
+ * vs A/R profile) would like to use MMU indexes with different semantics,
+ * but since we don't ever need to use all of those in a single CPU we
+ * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
+ * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
+ * the same for any particular CPU.
+ * Variables of type ARMMUIdx are always full values, and the core
+ * index values are in variables of type 'int'.
+ *
  * Our enumeration includes at the end some entries which are not "true"
  * mmu_idx values in that they don't have corresponding TLBs and are only
  * valid for doing slow path page table walks.
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
  * of the AT/ATS operations.
  * The values used are carefully arranged to make mmu_idx => EL lookup easy.
  */
+#define ARM_MMU_IDX_A 0x10 /* A profile (and M profile, for the moment) */
+#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
+
+#define ARM_MMU_IDX_TYPE_MASK (~0x7)
+#define ARM_MMU_IDX_COREIDX_MASK 0x7
+
 typedef enum ARMMMUIdx {
-    ARMMMUIdx_S12NSE0 = 0,
-    ARMMMUIdx_S12NSE1 = 1,
-    ARMMMUIdx_S1E2 = 2,
-    ARMMMUIdx_S1E3 = 3,
-    ARMMMUIdx_S1SE0 = 4,
-    ARMMMUIdx_S1SE1 = 5,
-    ARMMMUIdx_S2NS = 6,
+    ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
+    ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
+    ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
+    ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
+    ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
+    ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
+    ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
     /* Indexes below here don't have TLBs and are used only for AT system
      * instructions or for the first stage of an S12 page table walk.
      */
-    ARMMMUIdx_S1NSE0 = 7,
-    ARMMMUIdx_S1NSE1 = 8,
+    ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB,
+    ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB,
 } ARMMMUIdx;
 
+/* Bit macros for the core-mmu-index values for each index,
+ * for use when calling tlb_flush_by_mmuidx() and friends.
+ */
+typedef enum ARMMMUIdxBit {
+    ARMMMUIdxBit_S12NSE0 = 1 << 0,
+    ARMMMUIdxBit_S12NSE1 = 1 << 1,
+    ARMMMUIdxBit_S1E2 = 1 << 2,
+    ARMMMUIdxBit_S1E3 = 1 << 3,
+    ARMMMUIdxBit_S1SE0 = 1 << 4,
+    ARMMMUIdxBit_S1SE1 = 1 << 5,
+    ARMMMUIdxBit_S2NS = 1 << 6,
+} ARMMMUIdxBit;
+
 #define MMU_USER_IDX 0
 
+static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
+{
+    return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
+}
+
+static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
+{
+    return mmu_idx | ARM_MMU_IDX_A;
+}
+
 /* Return the exception level we're running at if this is our mmu_idx */
 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
 {
-    assert(mmu_idx < ARMMMUIdx_S2NS);
-    return mmu_idx & 3;
+    switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
+    case ARM_MMU_IDX_A:
+        return mmu_idx & 3;
+    default:
+        g_assert_not_reached();
+    }
 }
 
 /* Determine the current mmu_idx to use for normal loads/stores */
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
     int el = arm_current_el(env);
 
     if (el < 2 && arm_is_secure_below_el3(env)) {
-        return ARMMMUIdx_S1SE0 + el;
+        return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
     }
     return el;
 }
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                                         target_ulong *cs_base, uint32_t *flags)
 {
-    ARMMMUIdx mmu_idx = cpu_mmu_index(env, false);
+    ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
     if (is_a64(env)) {
         *pc = env->pc;
         *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                    << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
     }
 
-    *flags |= (mmu_idx << ARM_TBFLAG_MMUIDX_SHIFT);
+    *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT);
 
     /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
      * states defined in the ARM ARM for software singlestep:
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int arm_dc_feature(DisasContext *dc, int feature)
 
 static inline int get_mem_index(DisasContext *s)
 {
-    return s->mmu_idx;
+    return arm_to_core_mmu_idx(s->mmu_idx);
 }
 
 /* Function used to determine the target exception EL when otherwise not known
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *cs = ENV_GET_CPU(env);
 
     tlb_flush_by_mmuidx(cs,
-                        (1 << ARMMMUIdx_S12NSE1) |
-                        (1 << ARMMMUIdx_S12NSE0) |
-                        (1 << ARMMMUIdx_S2NS));
+                        ARMMMUIdxBit_S12NSE1 |
+                        ARMMMUIdxBit_S12NSE0 |
+                        ARMMMUIdxBit_S2NS);
 }
 
 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *cs = ENV_GET_CPU(env);
 
     tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                        (1 << ARMMMUIdx_S12NSE1) |
-                                        (1 << ARMMMUIdx_S12NSE0) |
-                                        (1 << ARMMMUIdx_S2NS));
+                                        ARMMMUIdxBit_S12NSE1 |
+                                        ARMMMUIdxBit_S12NSE0 |
+                                        ARMMMUIdxBit_S2NS);
 }
 
 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     pageaddr = sextract64(value << 12, 0, 40);
 
-    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS));
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
 }
 
 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     pageaddr = sextract64(value << 12, 0, 40);
 
     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             (1 << ARMMMUIdx_S2NS));
+                                             ARMMMUIdxBit_S2NS);
 }
 
 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = ENV_GET_CPU(env);
 
-    tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2));
+    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
 }
 
 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = ENV_GET_CPU(env);
 
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E2));
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
 }
 
 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *cs = ENV_GET_CPU(env);
     uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
 
-    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2));
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
 }
 
 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
 
     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             (1 << ARMMMUIdx_S1E2));
+                                             ARMMMUIdxBit_S1E2);
 }
 
 static const ARMCPRegInfo cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
     if (raw_read(env, ri) != value) {
         tlb_flush_by_mmuidx(cs,
-                            (1 << ARMMMUIdx_S12NSE1) |
-                            (1 << ARMMMUIdx_S12NSE0) |
-                            (1 << ARMMMUIdx_S2NS));
+                            ARMMMUIdxBit_S12NSE1 |
+                            ARMMMUIdxBit_S12NSE0 |
+                            ARMMMUIdxBit_S2NS);
         raw_write(env, ri, value);
     }
 }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     if (arm_is_secure_below_el3(env)) {
         tlb_flush_by_mmuidx(cs,
-                            (1 << ARMMMUIdx_S1SE1) |
-                            (1 << ARMMMUIdx_S1SE0));
+                            ARMMMUIdxBit_S1SE1 |
+                            ARMMMUIdxBit_S1SE0);
     } else {
         tlb_flush_by_mmuidx(cs,
-                            (1 << ARMMMUIdx_S12NSE1) |
-                            (1 << ARMMMUIdx_S12NSE0));
+                            ARMMMUIdxBit_S12NSE1 |
+                            ARMMMUIdxBit_S12NSE0);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     if (sec) {
         tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                            (1 << ARMMMUIdx_S1SE1) |
-                                            (1 << ARMMMUIdx_S1SE0));
+                                            ARMMMUIdxBit_S1SE1 |
+                                            ARMMMUIdxBit_S1SE0);
     } else {
         tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                            (1 << ARMMMUIdx_S12NSE1) |
-                                            (1 << ARMMMUIdx_S12NSE0));
+                                            ARMMMUIdxBit_S12NSE1 |
+                                            ARMMMUIdxBit_S12NSE0);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     if (arm_is_secure_below_el3(env)) {
         tlb_flush_by_mmuidx(cs,
-                            (1 << ARMMMUIdx_S1SE1) |
-                            (1 << ARMMMUIdx_S1SE0));
+                            ARMMMUIdxBit_S1SE1 |
+                            ARMMMUIdxBit_S1SE0);
     } else {
         if (arm_feature(env, ARM_FEATURE_EL2)) {
             tlb_flush_by_mmuidx(cs,
-                                (1 << ARMMMUIdx_S12NSE1) |
-                                (1 << ARMMMUIdx_S12NSE0) |
-                                (1 << ARMMMUIdx_S2NS));
+                                ARMMMUIdxBit_S12NSE1 |
+                                ARMMMUIdxBit_S12NSE0 |
+                                ARMMMUIdxBit_S2NS);
         } else {
             tlb_flush_by_mmuidx(cs,
-                                (1 << ARMMMUIdx_S12NSE1) |
-                                (1 << ARMMMUIdx_S12NSE0));
+                                ARMMMUIdxBit_S12NSE1 |
+                                ARMMMUIdxBit_S12NSE0);
         }
     }
 }
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
     ARMCPU *cpu = arm_env_get_cpu(env);
     CPUState *cs = CPU(cpu);
 
-    tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2));
+    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
 }
 
 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
     ARMCPU *cpu = arm_env_get_cpu(env);
     CPUState *cs = CPU(cpu);
 
-    tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E3));
+    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
 }
 
 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     if (sec) {
         tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                            (1 << ARMMMUIdx_S1SE1) |
-                                            (1 << ARMMMUIdx_S1SE0));
+                                            ARMMMUIdxBit_S1SE1 |
+                                            ARMMMUIdxBit_S1SE0);
     } else if (has_el2) {
         tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                            (1 << ARMMMUIdx_S12NSE1) |
-                                            (1 << ARMMMUIdx_S12NSE0) |
-                                            (1 << ARMMMUIdx_S2NS));
+                                            ARMMMUIdxBit_S12NSE1 |
+                                            ARMMMUIdxBit_S12NSE0 |
+                                            ARMMMUIdxBit_S2NS);
     } else {
           tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                              (1 << ARMMMUIdx_S12NSE1) |
-                                              (1 << ARMMMUIdx_S12NSE0));
+                                              ARMMMUIdxBit_S12NSE1 |
+                                              ARMMMUIdxBit_S12NSE0);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = ENV_GET_CPU(env);
 
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E2));
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
 }
 
 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     CPUState *cs = ENV_GET_CPU(env);
 
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E3));
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
 }
 
 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     if (arm_is_secure_below_el3(env)) {
         tlb_flush_page_by_mmuidx(cs, pageaddr,
-                                 (1 << ARMMMUIdx_S1SE1) |
-                                 (1 << ARMMMUIdx_S1SE0));
+                                 ARMMMUIdxBit_S1SE1 |
+                                 ARMMMUIdxBit_S1SE0);
     } else {
         tlb_flush_page_by_mmuidx(cs, pageaddr,
-                                 (1 << ARMMMUIdx_S12NSE1) |
-                                 (1 << ARMMMUIdx_S12NSE0));
+                                 ARMMMUIdxBit_S12NSE1 |
+                                 ARMMMUIdxBit_S12NSE0);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *cs = CPU(cpu);
     uint64_t pageaddr = sextract64(value << 12, 0, 56);
 
-    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2));
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
 }
 
 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPUState *cs = CPU(cpu);
     uint64_t pageaddr = sextract64(value << 12, 0, 56);
 
-    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E3));
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
 }
 
 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     if (sec) {
         tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                                 (1 << ARMMMUIdx_S1SE1) |
-                                                 (1 << ARMMMUIdx_S1SE0));
+                                                 ARMMMUIdxBit_S1SE1 |
+                                                 ARMMMUIdxBit_S1SE0);
     } else {
         tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                                 (1 << ARMMMUIdx_S12NSE1) |
-                                                 (1 << ARMMMUIdx_S12NSE0));
+                                                 ARMMMUIdxBit_S12NSE1 |
+                                                 ARMMMUIdxBit_S12NSE0);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     uint64_t pageaddr = sextract64(value << 12, 0, 56);
 
     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             (1 << ARMMMUIdx_S1E2));
+                                             ARMMMUIdxBit_S1E2);
 }
 
 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     uint64_t pageaddr = sextract64(value << 12, 0, 56);
 
     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             (1 << ARMMMUIdx_S1E3));
+                                             ARMMMUIdxBit_S1E3);
 }
 
 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     pageaddr = sextract64(value << 12, 0, 48);
 
-    tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS));
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
 }
 
 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     pageaddr = sextract64(value << 12, 0, 48);
 
     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             (1 << ARMMMUIdx_S2NS));
+                                             ARMMMUIdxBit_S2NS);
 }
 
 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
 }
 
+/* Convert a possible stage1+2 MMU index into the appropriate
+ * stage 1 MMU index
+ */
+static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
+{
+    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
+        mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);
+    }
+    return mmu_idx;
+}
+
 /* Returns TBI0 value for current regime el */
 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
@@ -XXX,XX +XXX,XX @@ uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
     uint32_t el;
 
     /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
-       * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
-       */
-    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
-        mmu_idx += ARMMMUIdx_S1NSE0;
-    }
+     * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
+     */
+    mmu_idx = stage_1_mmu_idx(mmu_idx);
 
     tcr = regime_tcr(env, mmu_idx);
     el = regime_el(env, mmu_idx);
@@ -XXX,XX +XXX,XX @@ uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
     uint32_t el;
 
     /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
-       * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
-       */
-    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
-        mmu_idx += ARMMMUIdx_S1NSE0;
-    }
+     * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
+     */
+    mmu_idx = stage_1_mmu_idx(mmu_idx);
 
     tcr = regime_tcr(env, mmu_idx);
     el = regime_el(env, mmu_idx);
@@ -XXX,XX +XXX,XX @@ static inline bool regime_using_lpae_format(CPUARMState *env,
  * on whether the long or short descriptor format is in use. */
 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
-    if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
-        mmu_idx += ARMMMUIdx_S1NSE0;
-    }
+    mmu_idx = stage_1_mmu_idx(mmu_idx);
 
     return regime_using_lpae_format(env, mmu_idx);
 }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
             int ret;
 
             ret = get_phys_addr(env, address, access_type,
-                                mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
+                                stage_1_mmu_idx(mmu_idx), &ipa, attrs,
                                 prot, page_size, fsr, fi);
 
             /* If S1 fails or S2 is disabled, return early.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
             /*
              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
              */
-            mmu_idx += ARMMMUIdx_S1NSE0;
+            mmu_idx = stage_1_mmu_idx(mmu_idx);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ bool arm_tlb_fill(CPUState *cs, vaddr address,
     int ret;
     MemTxAttrs attrs = {};
 
-    ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
+    ret = get_phys_addr(env, address, access_type,
+                        core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
                         &attrs, &prot, &page_size, fsr, fi);
     if (!ret) {
         /* Map a single [sub]page.  */
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
     bool ret;
     uint32_t fsr;
     ARMMMUFaultInfo fi = {};
+    ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
 
     *attrs = (MemTxAttrs) {};
 
-    ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
+    ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
                         attrs, &prot, &page_size, &fsr, &fi);
 
     if (ret) {
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
     int target_el;
     bool same_el;
     uint32_t syn;
+    ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
 
     if (retaddr) {
         /* now we have a real cpu fault */
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
     /* the DFSR for an alignment fault depends on whether we're using
      * the LPAE long descriptor format, or the short descriptor format
      */
-    if (arm_s1_regime_using_lpae_format(env, mmu_idx)) {
+    if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
         env->exception.fsr = (1 << 9) | 0x21;
     } else {
         env->exception.fsr = 0x1;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ void a64_translate_init(void)
         offsetof(CPUARMState, exclusive_high), "exclusive_high");
 }
 
-static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s)
+static inline int get_a64_user_mem_index(DisasContext *s)
 {
-    /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
+    /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
      *  if EL1, access as if EL0; otherwise access at current EL
      */
+    ARMMMUIdx useridx;
+
     switch (s->mmu_idx) {
     case ARMMMUIdx_S12NSE1:
-        return ARMMMUIdx_S12NSE0;
+        useridx = ARMMMUIdx_S12NSE0;
+        break;
     case ARMMMUIdx_S1SE1:
-        return ARMMMUIdx_S1SE0;
+        useridx = ARMMMUIdx_S1SE0;
+        break;
     case ARMMMUIdx_S2NS:
         g_assert_not_reached();
     default:
-        return s->mmu_idx;
+        useridx = s->mmu_idx;
+        break;
     }
+    return arm_to_core_mmu_idx(useridx);
 }
 
 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
     dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;
     dc->condexec_mask = 0;
     dc->condexec_cond = 0;
-    dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
+    dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags));
     dc->tbi0 = ARM_TBFLAG_TBI0(tb->flags);
     dc->tbi1 = ARM_TBFLAG_TBI1(tb->flags);
     dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
     disas_set_insn_syndrome(s, syn);
 }
 
-static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
+static inline int get_a32_user_mem_index(DisasContext *s)
 {
-    /* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
+    /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store"
      * insns:
      *  if PL2, UNPREDICTABLE (we choose to implement as if PL0)
      *  otherwise, access as if at PL0.
@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
     case ARMMMUIdx_S1E2:        /* this one is UNPREDICTABLE */
     case ARMMMUIdx_S12NSE0:
     case ARMMMUIdx_S12NSE1:
-        return ARMMMUIdx_S12NSE0;
+        return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0);
     case ARMMMUIdx_S1E3:
     case ARMMMUIdx_S1SE0:
     case ARMMMUIdx_S1SE1:
-        return ARMMMUIdx_S1SE0;
+        return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0);
     case ARMMMUIdx_S2NS:
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
     dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;
     dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
     dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
-    dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
+    dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags));
     dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
 #if !defined(CONFIG_USER_ONLY)
     dc->user = (dc->current_el == 0);
-- 
2.7.4

Make M profile use completely separate ARMMMUIdx values from
those that A profile CPUs use. This is a prelude to adding
support for the MPU and for v8M, which together will require
6 MMU indexes which don't map cleanly onto the A profile
uses:
 non secure User
 non secure Privileged
 non secure Privileged, execution priority < 0
 secure User
 secure Privileged
 secure Privileged, execution priority < 0

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1493122030-32191-4-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 21 +++++++++++++++++++--
 target/arm/helper.c    |  5 +++++
 target/arm/translate.c |  3 +++
 3 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
  * of the AT/ATS operations.
  * The values used are carefully arranged to make mmu_idx => EL lookup easy.
  */
-#define ARM_MMU_IDX_A 0x10 /* A profile (and M profile, for the moment) */
+#define ARM_MMU_IDX_A 0x10 /* A profile */
 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
+#define ARM_MMU_IDX_M 0x40 /* M profile */
 
 #define ARM_MMU_IDX_TYPE_MASK (~0x7)
 #define ARM_MMU_IDX_COREIDX_MASK 0x7
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
     ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
     ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
+    ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
+    ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
     /* Indexes below here don't have TLBs and are used only for AT system
      * instructions or for the first stage of an S12 page table walk.
      */
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
     ARMMMUIdxBit_S1SE0 = 1 << 4,
     ARMMMUIdxBit_S1SE1 = 1 << 5,
     ARMMMUIdxBit_S2NS = 1 << 6,
+    ARMMMUIdxBit_MUser = 1 << 0,
+    ARMMMUIdxBit_MPriv = 1 << 1,
 } ARMMMUIdxBit;
 
 #define MMU_USER_IDX 0
@@ -XXX,XX +XXX,XX @@ static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
 
 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
 {
-    return mmu_idx | ARM_MMU_IDX_A;
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        return mmu_idx | ARM_MMU_IDX_M;
+    } else {
+        return mmu_idx | ARM_MMU_IDX_A;
+    }
 }
 
 /* Return the exception level we're running at if this is our mmu_idx */
@@ -XXX,XX +XXX,XX @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
     switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
     case ARM_MMU_IDX_A:
         return mmu_idx & 3;
+    case ARM_MMU_IDX_M:
+        return mmu_idx & 1;
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
 {
     int el = arm_current_el(env);
 
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;
+
+        return arm_to_core_mmu_idx(mmu_idx);
+    }
+
     if (el < 2 && arm_is_secure_below_el3(env)) {
         return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
     }
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
     case ARMMMUIdx_S1SE1:
     case ARMMMUIdx_S1NSE0:
     case ARMMMUIdx_S1NSE1:
+    case ARMMMUIdx_MPriv:
+    case ARMMMUIdx_MUser:
         return 1;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
     case ARMMMUIdx_S1NSE1:
     case ARMMMUIdx_S1E2:
     case ARMMMUIdx_S2NS:
+    case ARMMMUIdx_MPriv:
+    case ARMMMUIdx_MUser:
         return false;
     case ARMMMUIdx_S1E3:
     case ARMMMUIdx_S1SE0:
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
     switch (mmu_idx) {
     case ARMMMUIdx_S1SE0:
     case ARMMMUIdx_S1NSE0:
+    case ARMMMUIdx_MUser:
         return true;
     default:
         return false;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
     case ARMMMUIdx_S1SE0:
     case ARMMMUIdx_S1SE1:
         return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0);
+    case ARMMMUIdx_MUser:
+    case ARMMMUIdx_MPriv:
+        return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
     case ARMMMUIdx_S2NS:
     default:
         g_assert_not_reached();
-- 
2.7.4

ARM CPUs come in two flavours:
 * proper MMU ("VMSA")
 * only an MPU ("PMSA")
For PMSA, the MPU may be implemented, or not (in which case there
is default "always acts the same" behaviour, but it isn't guest
programmable).

QEMU is a bit confused about how we indicate this: we have an
ARM_FEATURE_MPU, but it's not clear whether this indicates
"PMSA, not VMSA" or "PMSA and MPU present" , and sometimes we
use it for one purpose and sometimes the other.

Currently trying to implement a PMSA-without-MPU core won't
work correctly because we turn off the ARM_FEATURE_MPU bit
and then a lot of things which should still exist get
turned off too.

As the first step in cleaning this up, rename the feature
bit to ARM_FEATURE_PMSA, which indicates a PMSA CPU (with
or without MPU).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-5-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h     |  2 +-
 target/arm/cpu.c     | 12 ++++++------
 target/arm/helper.c  | 12 ++++++------
 target/arm/machine.c |  2 +-
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ enum arm_features {
     ARM_FEATURE_V6K,
     ARM_FEATURE_V7,
     ARM_FEATURE_THUMB2,
-    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
+    ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
     ARM_FEATURE_VFP3,
     ARM_FEATURE_VFP_FP16,
     ARM_FEATURE_NEON,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
                                  &error_abort);
     }
 
-    if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
+    if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
                                  &error_abort);
         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
     if (arm_feature(env, ARM_FEATURE_V7) &&
         !arm_feature(env, ARM_FEATURE_M) &&
-        !arm_feature(env, ARM_FEATURE_MPU)) {
+        !arm_feature(env, ARM_FEATURE_PMSA)) {
         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
          * can use 4K pages.
          */
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     if (!cpu->has_mpu) {
-        unset_feature(env, ARM_FEATURE_MPU);
+        unset_feature(env, ARM_FEATURE_PMSA);
     }
 
-    if (arm_feature(env, ARM_FEATURE_MPU) &&
+    if (arm_feature(env, ARM_FEATURE_PMSA) &&
         arm_feature(env, ARM_FEATURE_V7)) {
         uint32_t nr = cpu->pmsav7_dregion;
 
@@ -XXX,XX +XXX,XX @@ static void arm946_initfn(Object *obj)
 
     cpu->dtb_compatible = "arm,arm946";
     set_feature(&cpu->env, ARM_FEATURE_V5);
-    set_feature(&cpu->env, ARM_FEATURE_MPU);
+    set_feature(&cpu->env, ARM_FEATURE_PMSA);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     cpu->midr = 0x41059461;
     cpu->ctr = 0x0f004006;
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
     set_feature(&cpu->env, ARM_FEATURE_V7MP);
-    set_feature(&cpu->env, ARM_FEATURE_MPU);
+    set_feature(&cpu->env, ARM_FEATURE_PMSA);
     cpu->midr = 0x411fc153; /* r1p3 */
     cpu->id_pfr0 = 0x0131;
     cpu->id_pfr1 = 0x001;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     ARMCPU *cpu = arm_env_get_cpu(env);
 
-    if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
+    if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
         && !extended_addresses_enabled(env)) {
         /* For VMSA (when not using the LPAE long descriptor page table
          * format) this register includes the ASID, so do a TLB flush.
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, v6k_cp_reginfo);
     }
     if (arm_feature(env, ARM_FEATURE_V7MP) &&
-        !arm_feature(env, ARM_FEATURE_MPU)) {
+        !arm_feature(env, ARM_FEATURE_PMSA)) {
         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
     }
     if (arm_feature(env, ARM_FEATURE_V7)) {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
     }
 
-    if (arm_feature(env, ARM_FEATURE_MPU)) {
+    if (arm_feature(env, ARM_FEATURE_PMSA)) {
         if (arm_feature(env, ARM_FEATURE_V6)) {
             /* PMSAv6 not implemented */
             assert(arm_feature(env, ARM_FEATURE_V7));
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
         }
         define_arm_cp_regs(cpu, id_cp_reginfo);
-        if (!arm_feature(env, ARM_FEATURE_MPU)) {
+        if (!arm_feature(env, ARM_FEATURE_PMSA)) {
             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
         } else if (arm_feature(env, ARM_FEATURE_V7)) {
             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
     /* pmsav7 has special handling for when MPU is disabled so call it before
      * the common MMU/MPU disabled check below.
      */
-    if (arm_feature(env, ARM_FEATURE_MPU) &&
+    if (arm_feature(env, ARM_FEATURE_PMSA) &&
         arm_feature(env, ARM_FEATURE_V7)) {
         *page_size = TARGET_PAGE_SIZE;
         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
         return 0;
     }
 
-    if (arm_feature(env, ARM_FEATURE_MPU)) {
+    if (arm_feature(env, ARM_FEATURE_PMSA)) {
         /* Pre-v7 MPU */
         *page_size = TARGET_PAGE_SIZE;
         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_needed(void *opaque)
     ARMCPU *cpu = opaque;
     CPUARMState *env = &cpu->env;
 
-    return arm_feature(env, ARM_FEATURE_MPU) &&
+    return arm_feature(env, ARM_FEATURE_PMSA) &&
            arm_feature(env, ARM_FEATURE_V7);
 }
 
-- 
2.7.4

Fix the handling of QOM properties for PMSA CPUs with no MPU:

Allow no-MPU to be specified by either:
 * has-mpu = false
 * pmsav7_dregion = 0
and make setting one imply the other. Don't clear the PMSA
feature bit in this situation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-6-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->id_pfr1 &= ~0xf000;
     }
 
+    /* MPU can be configured out of a PMSA CPU either by setting has-mpu
+     * to false or by setting pmsav7-dregion to 0.
+     */
     if (!cpu->has_mpu) {
-        unset_feature(env, ARM_FEATURE_PMSA);
+        cpu->pmsav7_dregion = 0;
+    }
+    if (cpu->pmsav7_dregion == 0) {
+        cpu->has_mpu = false;
     }
 
     if (arm_feature(env, ARM_FEATURE_PMSA) &&
-- 
2.7.4

If the CPU is a PMSA config with no MPU implemented, then the
SCTLR.M bit should be RAZ/WI, so that the guest can never
turn on the non-existent MPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-7-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         return;
     }
 
+    if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
+        /* M bit is RAZ/WI for PMSA with no MPU implemented */
+        value &= ~SCTLR_M;
+    }
+
     raw_write(env, ri, value);
     /* ??? Lots of these bits are not implemented.  */
     /* This may enable/disable the MMU, so do a TLB flush.  */
-- 
2.7.4

Now that we enforce both:
 * pmsav7_dregion == 0 implies has_mpu == false
 * PMSA with has_mpu == false means SCTLR.M cannot be set
we can remove a check on pmsav7_dregion from get_phys_addr_pmsav7(),
because we can only reach this code path if the MPU is enabled
(and so region_translation_disabled() returned false).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-8-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
         }
 
         if (n == -1) { /* no hits */
-            if (cpu->pmsav7_dregion &&
-                (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
+            if (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR)) {
                 /* background fault */
                 *fsr = 0;
                 return true;
-- 
2.7.4

From: Michael Davidsaver <mdavidsaver@gmail.com>

Improve the "-d mmu" tracing for the PMSAv7 MPU translation
process as an aid in debugging guest MPU configurations:
 * fix a missing newline for a guest-error log
 * report the region number with guest-error or unimp
   logs of bad region register values
 * add a log message for the overall result of the lookup
 * print "0x" prefix for hex values

Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-9-git-send-email-peter.maydell@linaro.org
[PMM: a little tidyup, report region number in all messages
 rather than just one]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 39 +++++++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 12 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
             }
 
             if (!rsize) {
-                qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "DRSR[%d]: Rsize field cannot be 0\n", n);
                 continue;
             }
             rsize++;
             rmask = (1ull << rsize) - 1;
 
             if (base & rmask) {
-                qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
-                              "to DRSR region size, mask = %" PRIx32,
-                              base, rmask);
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "DRBAR[%d]: 0x%" PRIx32 " misaligned "
+                              "to DRSR region size, mask = 0x%" PRIx32 "\n",
+                              n, base, rmask);
                 continue;
             }
 
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                 }
             }
             if (rsize < TARGET_PAGE_BITS) {
-                qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
+                qemu_log_mask(LOG_UNIMP,
+                              "DRSR[%d]: No support for MPU (sub)region "
                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
-                              rsize, TARGET_PAGE_BITS);
+                              n, rsize, TARGET_PAGE_BITS);
                 continue;
             }
             if (srdis) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                     break;
                 default:
                     qemu_log_mask(LOG_GUEST_ERROR,
-                                  "Bad value for AP bits in DRACR %"
-                                  PRIx32 "\n", ap);
+                                  "DRACR[%d]: Bad value for AP bits: 0x%"
+                                  PRIx32 "\n", n, ap);
                 }
             } else { /* Priv. mode AP bits decoding */
                 switch (ap) {
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                     break;
                 default:
                     qemu_log_mask(LOG_GUEST_ERROR,
-                                  "Bad value for AP bits in DRACR %"
-                                  PRIx32 "\n", ap);
+                                  "DRACR[%d]: Bad value for AP bits: 0x%"
+                                  PRIx32 "\n", n, ap);
                 }
             }
 
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
      */
     if (arm_feature(env, ARM_FEATURE_PMSA) &&
         arm_feature(env, ARM_FEATURE_V7)) {
+        bool ret;
         *page_size = TARGET_PAGE_SIZE;
-        return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
-                                    phys_ptr, prot, fsr);
+        ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
+                                   phys_ptr, prot, fsr);
+        qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32
+                      " mmu_idx %u -> %s (prot %c%c%c)\n",
+                      access_type == 1 ? "reading" :
+                      (access_type == 2 ? "writing" : "execute"),
+                      (uint32_t)address, mmu_idx,
+                      ret ? "Miss" : "Hit",
+                      *prot & PAGE_READ ? 'r' : '-',
+                      *prot & PAGE_WRITE ? 'w' : '-',
+                      *prot & PAGE_EXEC ? 'x' : '-');
+
+        return ret;
     }
 
     if (regime_translation_disabled(env, mmu_idx)) {
-- 
2.7.4

From: Michael Davidsaver <mdavidsaver@gmail.com>

Add support for the M profile default memory map which is used
if the MPU is not present or disabled.

The main differences in behaviour from implementing this
correctly are that we set the PAGE_EXEC attribute on
the right regions of memory, such that device regions
are not executable.

Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Message-id: 1493122030-32191-10-git-send-email-peter.maydell@linaro.org
[PMM: rephrased comment and commit message; don't mark
 the flash memory region as not-writable; list all
 the cases in the default map explicitly rather than
 using a 'default' case for the non-executable regions]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 41 ++++++++++++++++++++++++++++++++---------
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
                                                 ARMMMUIdx mmu_idx,
                                                 int32_t address, int *prot)
 {
-    *prot = PAGE_READ | PAGE_WRITE;
-    switch (address) {
-    case 0xF0000000 ... 0xFFFFFFFF:
-        if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
+    if (!arm_feature(env, ARM_FEATURE_M)) {
+        *prot = PAGE_READ | PAGE_WRITE;
+        switch (address) {
+        case 0xF0000000 ... 0xFFFFFFFF:
+            if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
+                /* hivecs execing is ok */
+                *prot |= PAGE_EXEC;
+            }
+            break;
+        case 0x00000000 ... 0x7FFFFFFF:
             *prot |= PAGE_EXEC;
+            break;
+        }
+    } else {
+        /* Default system address map for M profile cores.
+         * The architecture specifies which regions are execute-never;
+         * at the MPU level no other checks are defined.
+         */
+        switch (address) {
+        case 0x00000000 ... 0x1fffffff: /* ROM */
+        case 0x20000000 ... 0x3fffffff: /* SRAM */
+        case 0x60000000 ... 0x7fffffff: /* RAM */
+        case 0x80000000 ... 0x9fffffff: /* RAM */
+            *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+            break;
+        case 0x40000000 ... 0x5fffffff: /* Peripheral */
+        case 0xa0000000 ... 0xbfffffff: /* Device */
+        case 0xc0000000 ... 0xdfffffff: /* Device */
+        case 0xe0000000 ... 0xffffffff: /* System */
+            *prot = PAGE_READ | PAGE_WRITE;
+            break;
+        default:
+            g_assert_not_reached();
         }
-        break;
-    case 0x00000000 ... 0x7FFFFFFF:
-        *prot |= PAGE_EXEC;
-        break;
     }
-
 }
 
 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
-- 
2.7.4

All M profile CPUs are PMSA, so set the feature bit.
(We haven't actually implemented the M profile MPU register
interface yet, but setting this feature bit gives us closer
to correct behaviour for the MPU-disabled case.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-11-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
+    /* M profile implies PMSA. We have to do this here rather than
+     * in realize with the other feature-implication checks because
+     * we look at the PMSA bit to see if we should add some properties.
+     */
+    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
+        set_feature(&cpu->env, ARM_FEATURE_PMSA);
+    }
+
     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
-- 
2.7.4

From: Michael Davidsaver <mdavidsaver@gmail.com>

General logic is that operations stopped by the MPU are MemManage,
and those which go through the MPU and are caught by the unassigned
handle are BusFault. Distinguish these by looking at the
exception.fsr values, and set the CFSR bits and (if appropriate)
fill in the BFAR or MMFAR with the exception address.

Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Message-id: 1493122030-32191-12-git-send-email-peter.maydell@linaro.org
[PMM: i-side faults do not set BFAR/MMFAR, only d-side;
 added some CPU_LOG_INT logging]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/helper.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 42 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
         break;
     case EXCP_PREFETCH_ABORT:
     case EXCP_DATA_ABORT:
-        /* TODO: if we implemented the MPU registers, this is where we
-         * should set the MMFAR, etc from exception.fsr and exception.vaddress.
+        /* Note that for M profile we don't have a guest facing FSR, but
+         * the env->exception.fsr will be populated by the code that
+         * raises the fault, in the A profile short-descriptor format.
          */
-        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
+        switch (env->exception.fsr & 0xf) {
+        case 0x8: /* External Abort */
+            switch (cs->exception_index) {
+            case EXCP_PREFETCH_ABORT:
+                env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK;
+                qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n");
+                break;
+            case EXCP_DATA_ABORT:
+                env->v7m.cfsr |=
+                    (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
+                env->v7m.bfar = env->exception.vaddress;
+                qemu_log_mask(CPU_LOG_INT,
+                              "...with CFSR.IBUSERR and BFAR 0x%x\n",
+                              env->v7m.bfar);
+                break;
+            }
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
+            break;
+        default:
+            /* All other FSR values are either MPU faults or "can't happen
+             * for M profile" cases.
+             */
+            switch (cs->exception_index) {
+            case EXCP_PREFETCH_ABORT:
+                env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK;
+                qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n");
+                break;
+            case EXCP_DATA_ABORT:
+                env->v7m.cfsr |=
+                    (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);
+                env->v7m.mmfar = env->exception.vaddress;
+                qemu_log_mask(CPU_LOG_INT,
+                              "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
+                              env->v7m.mmfar);
+                break;
+            }
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
+            break;
+        }
         break;
     case EXCP_BKPT:
         if (semihosting_enabled()) {
-- 
2.7.4

From: Michael Davidsaver <mdavidsaver@gmail.com>

The M series MPU is almost the same as the already implemented R
profile MPU (v7 PMSA).  So all we need to implement here is the MPU
register interface in the system register space.

This implementation has the same restriction as the R profile MPU
that it doesn't permit regions to be sized down smaller than 1K.

We also do not yet implement support for MPU_CTRL.HFNMIENA; this
bit should if zero disable use of the MPU when running HardFault,
NMI or with FAULTMASK set to 1 (ie at an execution priority of
less than zero) -- if the MPU is enabled we don't treat these
cases any differently.

Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Message-id: 1493122030-32191-13-git-send-email-peter.maydell@linaro.org
[PMM: Keep all the bits in mpu_ctrl field, rather than
 using SCTLR bits for them; drop broken HFNMIENA support;
 various cleanup]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h      |   6 +++
 hw/intc/armv7m_nvic.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++++++
 target/arm/helper.c   |  25 +++++++++++-
 target/arm/machine.c  |   5 ++-
 4 files changed, 137 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
         uint32_t dfsr; /* Debug Fault Status Register */
         uint32_t mmfar; /* MemManage Fault Address */
         uint32_t bfar; /* BusFault Address */
+        unsigned mpu_ctrl; /* MPU_CTRL (some bits kept in sctlr_el[1]) */
         int exception;
     } v7m;
 
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_DFSR, DWTTRAP, 2, 1)
 FIELD(V7M_DFSR, VCATCH, 3, 1)
 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
 
+/* v7M MPU_CTRL bits */
+FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
+FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
+FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
+
 /* If adding a feature bit which corresponds to a Linux ELF
  * HWCAP bit, remember to update the feature-bit-to-hwcap
  * mapping in linux-user/elfload.c:get_elf_hwcap().
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/arm.h"
 #include "hw/arm/armv7m_nvic.h"
 #include "target/arm/cpu.h"
+#include "exec/exec-all.h"
 #include "qemu/log.h"
 #include "trace.h"
 
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
     case 0xd70: /* ISAR4.  */
         return 0x01310102;
     /* TODO: Implement debug registers.  */
+    case 0xd90: /* MPU_TYPE */
+        /* Unified MPU; if the MPU is not present this value is zero */
+        return cpu->pmsav7_dregion << 8;
+        break;
+    case 0xd94: /* MPU_CTRL */
+        return cpu->env.v7m.mpu_ctrl;
+    case 0xd98: /* MPU_RNR */
+        return cpu->env.cp15.c6_rgnr;
+    case 0xd9c: /* MPU_RBAR */
+    case 0xda4: /* MPU_RBAR_A1 */
+    case 0xdac: /* MPU_RBAR_A2 */
+    case 0xdb4: /* MPU_RBAR_A3 */
+    {
+        int region = cpu->env.cp15.c6_rgnr;
+
+        if (region >= cpu->pmsav7_dregion) {
+            return 0;
+        }
+        return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
+    }
+    case 0xda0: /* MPU_RASR */
+    case 0xda8: /* MPU_RASR_A1 */
+    case 0xdb0: /* MPU_RASR_A2 */
+    case 0xdb8: /* MPU_RASR_A3 */
+    {
+        int region = cpu->env.cp15.c6_rgnr;
+
+        if (region >= cpu->pmsav7_dregion) {
+            return 0;
+        }
+        return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) |
+            (cpu->env.pmsav7.drsr[region] & 0xffff);
+    }
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
         return 0;
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
         qemu_log_mask(LOG_UNIMP,
                       "NVIC: Aux fault status registers unimplemented\n");
         break;
+    case 0xd90: /* MPU_TYPE */
+        return; /* RO */
+    case 0xd94: /* MPU_CTRL */
+        if ((value &
+             (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK))
+            == R_V7M_MPU_CTRL_HFNMIENA_MASK) {
+            qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "
+                          "UNPREDICTABLE\n");
+        }
+        cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
+                                         R_V7M_MPU_CTRL_HFNMIENA_MASK |
+                                         R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
+        tlb_flush(CPU(cpu));
+        break;
+    case 0xd98: /* MPU_RNR */
+        if (value >= cpu->pmsav7_dregion) {
+            qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %"
+                          PRIu32 "/%" PRIu32 "\n",
+                          value, cpu->pmsav7_dregion);
+        } else {
+            cpu->env.cp15.c6_rgnr = value;
+        }
+        break;
+    case 0xd9c: /* MPU_RBAR */
+    case 0xda4: /* MPU_RBAR_A1 */
+    case 0xdac: /* MPU_RBAR_A2 */
+    case 0xdb4: /* MPU_RBAR_A3 */
+    {
+        int region;
+
+        if (value & (1 << 4)) {
+            /* VALID bit means use the region number specified in this
+             * value and also update MPU_RNR.REGION with that value.
+             */
+            region = extract32(value, 0, 4);
+            if (region >= cpu->pmsav7_dregion) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "MPU region out of range %u/%" PRIu32 "\n",
+                              region, cpu->pmsav7_dregion);
+                return;
+            }
+            cpu->env.cp15.c6_rgnr = region;
+        } else {
+            region = cpu->env.cp15.c6_rgnr;
+        }
+
+        if (region >= cpu->pmsav7_dregion) {
+            return;
+        }
+
+        cpu->env.pmsav7.drbar[region] = value & ~0x1f;
+        tlb_flush(CPU(cpu));
+        break;
+    }
+    case 0xda0: /* MPU_RASR */
+    case 0xda8: /* MPU_RASR_A1 */
+    case 0xdb0: /* MPU_RASR_A2 */
+    case 0xdb8: /* MPU_RASR_A3 */
+    {
+        int region = cpu->env.cp15.c6_rgnr;
+
+        if (region >= cpu->pmsav7_dregion) {
+            return;
+        }
+
+        cpu->env.pmsav7.drsr[region] = value & 0xff3f;
+        cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f;
+        tlb_flush(CPU(cpu));
+        break;
+    }
     case 0xf00: /* Software Triggered Interrupt Register */
     {
         /* user mode can only write to STIR if CCR.USERSETMPEND permits it */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
 static inline bool regime_translation_disabled(CPUARMState *env,
                                                ARMMMUIdx mmu_idx)
 {
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        return !(env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_ENABLE_MASK);
+    }
+
     if (mmu_idx == ARMMMUIdx_S2NS) {
         return (env->cp15.hcr_el2 & HCR_VM) == 0;
     }
@@ -XXX,XX +XXX,XX @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
     }
 }
 
+static bool pmsav7_use_background_region(ARMCPU *cpu,
+                                         ARMMMUIdx mmu_idx, bool is_user)
+{
+    /* Return true if we should use the default memory map as a
+     * "background" region if there are no hits against any MPU regions.
+     */
+    CPUARMState *env = &cpu->env;
+
+    if (is_user) {
+        return false;
+    }
+
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
+    } else {
+        return regime_sctlr(env, mmu_idx) & SCTLR_BR;
+    }
+}
+
 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                                  int access_type, ARMMMUIdx mmu_idx,
                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
         }
 
         if (n == -1) { /* no hits */
-            if (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR)) {
+            if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
                 /* background fault */
                 *fsr = 0;
                 return true;
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static bool m_needed(void *opaque)
 
 static const VMStateDescription vmstate_m = {
     .name = "cpu/m",
-    .version_id = 3,
-    .minimum_version_id = 3,
+    .version_id = 4,
+    .minimum_version_id = 4,
     .needed = m_needed,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
         VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
         VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
         VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
+        VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU),
         VMSTATE_INT32(env.v7m.exception, ARMCPU),
         VMSTATE_END_OF_LIST()
     }
-- 
2.7.4

Implement HFNMIENA support for the M profile MPU. This bit controls
whether the MPU is treated as enabled when executing at execution
priorities of less than zero (in NMI, HardFault or with the FAULTMASK
bit set).

Doing this requires us to use a different MMU index for "running
at execution priority < 0", because we will have different
access permissions for that case versus the normal case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1493122030-32191-14-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 24 +++++++++++++++++++++++-
 target/arm/helper.c    | 18 +++++++++++++++++-
 target/arm/translate.c |  1 +
 3 files changed, 41 insertions(+), 2 deletions(-)

From: Cédric Le Goater <clg@kaod.org>

Multiple I2C commands can be fired simultaneously and the controller
execute the commands following these priorities:

(1) Master Start Command
  (2) Master Transmit Command
  (3) Slave Transmit Command or Master Receive Command
  (4) Master Stop Command

The current code is incorrect with respect to the above sequence and
needs to be reworked to handle each individual command.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1494827476-1487-2-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/aspeed_i2c.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
 
 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
 {
+    bus->cmd &= ~0xFFFF;
     bus->cmd |= value & 0xFFFF;
     bus->intr_status = 0;
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
             bus->intr_status |= I2CD_INTR_TX_ACK;
         }
 
-    } else if (bus->cmd & I2CD_M_TX_CMD) {
+        /* START command is also a TX command, as the slave address is
+         * sent on the bus */
+        bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
+
+        /* No slave found */
+        if (!i2c_bus_busy(bus->bus)) {
+            return;
+        }
+    }
+
+    if (bus->cmd & I2CD_M_TX_CMD) {
         if (i2c_send(bus->bus, bus->buf)) {
             bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
             i2c_end_transfer(bus->bus);
         } else {
             bus->intr_status |= I2CD_INTR_TX_ACK;
         }
+        bus->cmd &= ~I2CD_M_TX_CMD;
+    }
 
-    } else if (bus->cmd & I2CD_M_RX_CMD) {
+    if (bus->cmd & I2CD_M_RX_CMD) {
         int ret = i2c_recv(bus->bus);
         if (ret < 0) {
             qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
             bus->intr_status |= I2CD_INTR_RX_DONE;
         }
         bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
+        bus->cmd &= ~I2CD_M_RX_CMD;
     }
 
     if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
             i2c_end_transfer(bus->bus);
             bus->intr_status |= I2CD_INTR_NORMAL_STOP;
         }
+        bus->cmd &= ~I2CD_M_STOP_CMD;
     }
-
-    /* command is handled, reset it and check for interrupts  */
-    bus->cmd &= ~0xFFFF;
-    aspeed_i2c_bus_raise_interrupt(bus);
 }
 
 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
         }
 
         aspeed_i2c_bus_handle_cmd(bus, value);
+        aspeed_i2c_bus_raise_interrupt(bus);
         break;
 
     default:
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

Today, the LAST command is handled with the STOP command but this is
incorrect. Also nack the I2C bus when a LAST is issued.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1494827476-1487-3-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/aspeed_i2c.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
         bus->cmd &= ~I2CD_M_TX_CMD;
     }
 
-    if (bus->cmd & I2CD_M_RX_CMD) {
+    if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
         int ret = i2c_recv(bus->bus);
         if (ret < 0) {
             qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
             bus->intr_status |= I2CD_INTR_RX_DONE;
         }
         bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
-        bus->cmd &= ~I2CD_M_RX_CMD;
+        if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
+            i2c_nack(bus->bus);
+        }
+        bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
     }
 
-    if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
+    if (bus->cmd & I2CD_M_STOP_CMD) {
         if (!i2c_bus_busy(bus->bus)) {
             bus->intr_status |= I2CD_INTR_ABNORMAL;
         } else {
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

The Aspeed I2C controller maintains a state machine in the command
register, which is mostly used for debug.

Let's start adding a few states to handle abnormal STOP
commands. Today, the model uses the busy status of the bus as a
condition to do so but it is not precise enough.

Also remove the ABNORMAL bit for failing TX commands. This is
incorrect with respect to the specs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1494827476-1487-4-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/aspeed_i2c.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
     }
 }
 
+static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
+{
+    bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);
+    bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;
+}
+
+static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
+{
+    return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
+}
+
+/*
+ * The state machine needs some refinement. It is only used to track
+ * invalid STOP commands for the moment.
+ */
 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
 {
     bus->cmd &= ~0xFFFF;
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
     bus->intr_status = 0;
 
     if (bus->cmd & I2CD_M_START_CMD) {
+        uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
+            I2CD_MSTARTR : I2CD_MSTART;
+
+        aspeed_i2c_set_state(bus, state);
+
         if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
                                extract32(bus->buf, 0, 1))) {
             bus->intr_status |= I2CD_INTR_TX_NAK;
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
         if (!i2c_bus_busy(bus->bus)) {
             return;
         }
+        aspeed_i2c_set_state(bus, I2CD_MACTIVE);
     }
 
     if (bus->cmd & I2CD_M_TX_CMD) {
+        aspeed_i2c_set_state(bus, I2CD_MTXD);
         if (i2c_send(bus->bus, bus->buf)) {
-            bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
+            bus->intr_status |= (I2CD_INTR_TX_NAK);
             i2c_end_transfer(bus->bus);
         } else {
             bus->intr_status |= I2CD_INTR_TX_ACK;
         }
         bus->cmd &= ~I2CD_M_TX_CMD;
+        aspeed_i2c_set_state(bus, I2CD_MACTIVE);
     }
 
     if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
-        int ret = i2c_recv(bus->bus);
+        int ret;
+
+        aspeed_i2c_set_state(bus, I2CD_MRXD);
+        ret = i2c_recv(bus->bus);
         if (ret < 0) {
             qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
             ret = 0xff;
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
             i2c_nack(bus->bus);
         }
         bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
+        aspeed_i2c_set_state(bus, I2CD_MACTIVE);
     }
 
     if (bus->cmd & I2CD_M_STOP_CMD) {
-        if (!i2c_bus_busy(bus->bus)) {
+        if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
             bus->intr_status |= I2CD_INTR_ABNORMAL;
         } else {
+            aspeed_i2c_set_state(bus, I2CD_MSTOP);
             i2c_end_transfer(bus->bus);
             bus->intr_status |= I2CD_INTR_NORMAL_STOP;
         }
         bus->cmd &= ~I2CD_M_STOP_CMD;
+        aspeed_i2c_set_state(bus, I2CD_IDLE);
     }
 }
 
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

Let's add an RTC to the palmetto BMC and a LM75 temperature sensor to
the AST2500 EVB to start with.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1494827476-1487-5-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/aspeed.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardConfig {
     const char *fmc_model;
     const char *spi_model;
     uint32_t num_cs;
+    void (*i2c_init)(AspeedBoardState *bmc);
 } AspeedBoardConfig;
 
 enum {
@@ -XXX,XX +XXX,XX @@ enum {
         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
 
+static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
+static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
+
 static const AspeedBoardConfig aspeed_boards[] = {
     [PALMETTO_BMC] = {
         .soc_name  = "ast2400-a1",
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
         .fmc_model = "n25q256a",
         .spi_model = "mx25l25635e",
         .num_cs    = 1,
+        .i2c_init  = palmetto_bmc_i2c_init,
     },
     [AST2500_EVB]  = {
         .soc_name  = "ast2500-a1",
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
         .fmc_model = "n25q256a",
         .spi_model = "mx25l25635e",
         .num_cs    = 1,
+        .i2c_init  = ast2500_evb_i2c_init,
     },
     [ROMULUS_BMC]  = {
         .soc_name  = "ast2500-a1",
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
     aspeed_board_binfo.ram_size = ram_size;
     aspeed_board_binfo.loader_start = sc->info->sdram_base;
 
+    if (cfg->i2c_init) {
+        cfg->i2c_init(bmc);
+    }
+
     arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
 }
 
+static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
+{
+    AspeedSoCState *soc = &bmc->soc;
+
+    /* The palmetto platform expects a ds3231 RTC but a ds1338 is
+     * enough to provide basic RTC features. Alarms will be missing */
+    i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
+}
+
 static void palmetto_bmc_init(MachineState *machine)
 {
     aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo palmetto_bmc_type = {
     .class_init = palmetto_bmc_class_init,
 };
 
+static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
+{
+    AspeedSoCState *soc = &bmc->soc;
+
+    /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
+    i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
+}
+
 static void ast2500_evb_init(MachineState *machine)
 {
     aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]);
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

Largely inspired by the TMP105 temperature sensor, here is a model for
the TMP42{1,2,3} temperature sensors.

Specs can be found here :

http://www.ti.com/lit/gpn/tmp421

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1494827476-1487-6-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/Makefile.objs           |   1 +
 hw/misc/tmp421.c                | 401 ++++++++++++++++++++++++++++++++++++++++
 default-configs/arm-softmmu.mak |   1 +
 3 files changed, 403 insertions(+)
 create mode 100644 hw/misc/tmp421.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@
 common-obj-$(CONFIG_APPLESMC) += applesmc.o
 common-obj-$(CONFIG_MAX111X) += max111x.o
 common-obj-$(CONFIG_TMP105) += tmp105.o
+common-obj-$(CONFIG_TMP421) += tmp421.o
 common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o
 common-obj-$(CONFIG_SGA) += sga.o
 common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/tmp421.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Texas Instruments TMP421 temperature sensor.
+ *
+ * Copyright (c) 2016 IBM Corporation.
+ *
+ * Largely inspired by :
+ *
+ * Texas Instruments TMP105 temperature sensor.
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Written by Andrzej Zaborowski <andrew@openedhand.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/i2c/i2c.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+
+/* Manufacturer / Device ID's */
+#define TMP421_MANUFACTURER_ID          0x55
+#define TMP421_DEVICE_ID                0x21
+#define TMP422_DEVICE_ID                0x22
+#define TMP423_DEVICE_ID                0x23
+
+typedef struct DeviceInfo {
+    int model;
+    const char *name;
+} DeviceInfo;
+
+static const DeviceInfo devices[] = {
+    { TMP421_DEVICE_ID, "tmp421" },
+    { TMP422_DEVICE_ID, "tmp422" },
+    { TMP423_DEVICE_ID, "tmp423" },
+};
+
+typedef struct TMP421State {
+    /*< private >*/
+    I2CSlave i2c;
+    /*< public >*/
+
+    int16_t temperature[4];
+
+    uint8_t status;
+    uint8_t config[2];
+    uint8_t rate;
+
+    uint8_t len;
+    uint8_t buf[2];
+    uint8_t pointer;
+
+} TMP421State;
+
+typedef struct TMP421Class {
+    I2CSlaveClass parent_class;
+    DeviceInfo *dev;
+} TMP421Class;
+
+#define TYPE_TMP421 "tmp421-generic"
+#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421)
+
+#define TMP421_CLASS(klass) \
+     OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421)
+#define TMP421_GET_CLASS(obj) \
+     OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421)
+
+/* the TMP421 registers */
+#define TMP421_STATUS_REG               0x08
+#define    TMP421_STATUS_BUSY             (1 << 7)
+#define TMP421_CONFIG_REG_1             0x09
+#define    TMP421_CONFIG_RANGE            (1 << 2)
+#define    TMP421_CONFIG_SHUTDOWN         (1 << 6)
+#define TMP421_CONFIG_REG_2             0x0A
+#define    TMP421_CONFIG_RC               (1 << 2)
+#define    TMP421_CONFIG_LEN              (1 << 3)
+#define    TMP421_CONFIG_REN              (1 << 4)
+#define    TMP421_CONFIG_REN2             (1 << 5)
+#define    TMP421_CONFIG_REN3             (1 << 6)
+
+#define TMP421_CONVERSION_RATE_REG      0x0B
+#define TMP421_ONE_SHOT                 0x0F
+
+#define TMP421_RESET                    0xFC
+#define TMP421_MANUFACTURER_ID_REG      0xFE
+#define TMP421_DEVICE_ID_REG            0xFF
+
+#define TMP421_TEMP_MSB0                0x00
+#define TMP421_TEMP_MSB1                0x01
+#define TMP421_TEMP_MSB2                0x02
+#define TMP421_TEMP_MSB3                0x03
+#define TMP421_TEMP_LSB0                0x10
+#define TMP421_TEMP_LSB1                0x11
+#define TMP421_TEMP_LSB2                0x12
+#define TMP421_TEMP_LSB3                0x13
+
+static const int32_t mins[2] = { -40000, -55000 };
+static const int32_t maxs[2] = { 127000, 150000 };
+
+static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
+{
+    TMP421State *s = TMP421(obj);
+    bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
+    int offset = ext_range * 64 * 256;
+    int64_t value;
+    int tempid;
+
+    if (sscanf(name, "temperature%d", &tempid) != 1) {
+        error_setg(errp, "error reading %s: %m", name);
+        return;
+    }
+
+    if (tempid >= 4 || tempid < 0) {
+        error_setg(errp, "error reading %s", name);
+        return;
+    }
+
+    value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256;
+
+    visit_type_int(v, name, &value, errp);
+}
+
+/* Units are 0.001 centigrades relative to 0 C.  s->temperature is 8.8
+ * fixed point, so units are 1/256 centigrades.  A simple ratio will do.
+ */
+static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
+{
+    TMP421State *s = TMP421(obj);
+    Error *local_err = NULL;
+    int64_t temp;
+    bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE);
+    int offset = ext_range * 64 * 256;
+    int tempid;
+
+    visit_type_int(v, name, &temp, &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    if (temp >= maxs[ext_range] || temp < mins[ext_range]) {
+        error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range",
+                   temp / 1000, temp % 1000);
+        return;
+    }
+
+    if (sscanf(name, "temperature%d", &tempid) != 1) {
+        error_setg(errp, "error reading %s: %m", name);
+        return;
+    }
+
+    if (tempid >= 4 || tempid < 0) {
+        error_setg(errp, "error reading %s", name);
+        return;
+    }
+
+    s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset;
+}
+
+static void tmp421_read(TMP421State *s)
+{
+    TMP421Class *sc = TMP421_GET_CLASS(s);
+
+    s->len = 0;
+
+    switch (s->pointer) {
+    case TMP421_MANUFACTURER_ID_REG:
+        s->buf[s->len++] = TMP421_MANUFACTURER_ID;
+        break;
+    case TMP421_DEVICE_ID_REG:
+        s->buf[s->len++] = sc->dev->model;
+        break;
+    case TMP421_CONFIG_REG_1:
+        s->buf[s->len++] = s->config[0];
+        break;
+    case TMP421_CONFIG_REG_2:
+        s->buf[s->len++] = s->config[1];
+        break;
+    case TMP421_CONVERSION_RATE_REG:
+        s->buf[s->len++] = s->rate;
+        break;
+    case TMP421_STATUS_REG:
+        s->buf[s->len++] = s->status;
+        break;
+
+        /* FIXME: check for channel enablement in config registers */
+    case TMP421_TEMP_MSB0:
+        s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8);
+        s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
+        break;
+    case TMP421_TEMP_MSB1:
+        s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8);
+        s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
+        break;
+    case TMP421_TEMP_MSB2:
+        s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8);
+        s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
+        break;
+    case TMP421_TEMP_MSB3:
+        s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8);
+        s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
+        break;
+    case TMP421_TEMP_LSB0:
+        s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0;
+        break;
+    case TMP421_TEMP_LSB1:
+        s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0;
+        break;
+    case TMP421_TEMP_LSB2:
+        s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0;
+        break;
+    case TMP421_TEMP_LSB3:
+        s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0;
+        break;
+    }
+}
+
+static void tmp421_reset(I2CSlave *i2c);
+
+static void tmp421_write(TMP421State *s)
+{
+    switch (s->pointer) {
+    case TMP421_CONVERSION_RATE_REG:
+        s->rate = s->buf[0];
+        break;
+    case TMP421_CONFIG_REG_1:
+        s->config[0] = s->buf[0];
+        break;
+    case TMP421_CONFIG_REG_2:
+        s->config[1] = s->buf[0];
+        break;
+    case TMP421_RESET:
+        tmp421_reset(I2C_SLAVE(s));
+        break;
+    }
+}
+
+static int tmp421_rx(I2CSlave *i2c)
+{
+    TMP421State *s = TMP421(i2c);
+
+    if (s->len < 2) {
+        return s->buf[s->len++];
+    } else {
+        return 0xff;
+    }
+}
+
+static int tmp421_tx(I2CSlave *i2c, uint8_t data)
+{
+    TMP421State *s = TMP421(i2c);
+
+    if (s->len == 0) {
+        /* first byte is the register pointer for a read or write
+         * operation */
+        s->pointer = data;
+        s->len++;
+    } else if (s->len == 1) {
+        /* second byte is the data to write. The device only supports
+         * one byte writes */
+        s->buf[0] = data;
+        tmp421_write(s);
+    }
+
+    return 0;
+}
+
+static int tmp421_event(I2CSlave *i2c, enum i2c_event event)
+{
+    TMP421State *s = TMP421(i2c);
+
+    if (event == I2C_START_RECV) {
+        tmp421_read(s);
+    }
+
+    s->len = 0;
+    return 0;
+}
+
+static const VMStateDescription vmstate_tmp421 = {
+    .name = "TMP421",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8(len, TMP421State),
+        VMSTATE_UINT8_ARRAY(buf, TMP421State, 2),
+        VMSTATE_UINT8(pointer, TMP421State),
+        VMSTATE_UINT8_ARRAY(config, TMP421State, 2),
+        VMSTATE_UINT8(status, TMP421State),
+        VMSTATE_UINT8(rate, TMP421State),
+        VMSTATE_INT16_ARRAY(temperature, TMP421State, 4),
+        VMSTATE_I2C_SLAVE(i2c, TMP421State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void tmp421_reset(I2CSlave *i2c)
+{
+    TMP421State *s = TMP421(i2c);
+    TMP421Class *sc = TMP421_GET_CLASS(s);
+
+    memset(s->temperature, 0, sizeof(s->temperature));
+    s->pointer = 0;
+
+    s->config[0] = 0; /* TMP421_CONFIG_RANGE */
+
+     /* resistance correction and channel enablement */
+    switch (sc->dev->model) {
+    case TMP421_DEVICE_ID:
+        s->config[1] = 0x1c;
+        break;
+    case TMP422_DEVICE_ID:
+        s->config[1] = 0x3c;
+        break;
+    case TMP423_DEVICE_ID:
+        s->config[1] = 0x7c;
+        break;
+    }
+
+    s->rate = 0x7;       /* 8Hz */
+    s->status = 0;
+}
+
+static int tmp421_init(I2CSlave *i2c)
+{
+    TMP421State *s = TMP421(i2c);
+
+    tmp421_reset(&s->i2c);
+
+    return 0;
+}
+
+static void tmp421_initfn(Object *obj)
+{
+    object_property_add(obj, "temperature0", "int",
+                        tmp421_get_temperature,
+                        tmp421_set_temperature, NULL, NULL, NULL);
+    object_property_add(obj, "temperature1", "int",
+                        tmp421_get_temperature,
+                        tmp421_set_temperature, NULL, NULL, NULL);
+    object_property_add(obj, "temperature2", "int",
+                        tmp421_get_temperature,
+                        tmp421_set_temperature, NULL, NULL, NULL);
+    object_property_add(obj, "temperature3", "int",
+                        tmp421_get_temperature,
+                        tmp421_set_temperature, NULL, NULL, NULL);
+}
+
+static void tmp421_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+    TMP421Class *sc = TMP421_CLASS(klass);
+
+    k->init = tmp421_init;
+    k->event = tmp421_event;
+    k->recv = tmp421_rx;
+    k->send = tmp421_tx;
+    dc->vmsd = &vmstate_tmp421;
+    sc->dev = (DeviceInfo *) data;
+}
+
+static const TypeInfo tmp421_info = {
+    .name          = TYPE_TMP421,
+    .parent        = TYPE_I2C_SLAVE,
+    .instance_size = sizeof(TMP421State),
+    .instance_init = tmp421_initfn,
+    .class_init    = tmp421_class_init,
+};
+
+static void tmp421_register_types(void)
+{
+    int i;
+
+    type_register_static(&tmp421_info);
+    for (i = 0; i < ARRAY_SIZE(devices); ++i) {
+        TypeInfo ti = {
+            .name       = devices[i].name,
+            .parent     = TYPE_TMP421,
+            .class_init = tmp421_class_init,
+            .class_data = (void *) &devices[i],
+        };
+        type_register(&ti);
+    }
+}
+
+type_init(tmp421_register_types)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_TWL92230=y
 CONFIG_TSC2005=y
 CONFIG_LM832X=y
 CONFIG_TMP105=y
+CONFIG_TMP421=y
 CONFIG_STELLARIS=y
 CONFIG_STELLARIS_INPUT=y
 CONFIG_STELLARIS_ENET=y
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

Temperatures can be changed from the monitor with :

(qemu) qom-set /machine/unattached/device[2] temperature0 12000

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1494827476-1487-7-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/aspeed.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
 {
     AspeedSoCState *soc = &bmc->soc;
+    DeviceState *dev;
 
     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
      * enough to provide basic RTC features. Alarms will be missing */
     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
+
+    /* add a TMP423 temperature sensor */
+    dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
+                           "tmp423", 0x4c);
+    object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
+    object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
+    object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
+    object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
 }
 
 static void palmetto_bmc_init(MachineState *machine)
-- 
2.7.4

From: Andrew Jones <drjones@redhat.com>

Cc: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 20170529173751.3443-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
     if (nb_numa_nodes > 0) {
         acpi_add_table(table_offsets, tables_blob);
         build_srat(tables_blob, tables->linker, vms);
+        if (have_numa_distance) {
+            acpi_add_table(table_offsets, tables_blob);
+            build_slit(tables_blob, tables->linker);
+        }
     }
 
     if (its_class_name() && !vmc->no_its) {
-- 
2.7.4

From: Andrew Jones <drjones@redhat.com>

This is based on patch Shannon Zhao originally posted.

Cc: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 20170529173751.3443-3-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
                                 "clk24mhz");
     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
 
+    if (have_numa_distance) {
+        int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
+        uint32_t *matrix = g_malloc0(size);
+        int idx, i, j;
+
+        for (i = 0; i < nb_numa_nodes; i++) {
+            for (j = 0; j < nb_numa_nodes; j++) {
+                idx = (i * nb_numa_nodes + j) * 3;
+                matrix[idx + 0] = cpu_to_be32(i);
+                matrix[idx + 1] = cpu_to_be32(j);
+                matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
+            }
+        }
+
+        qemu_fdt_add_subnode(fdt, "/distance-map");
+        qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
+                                "numa-distance-map-v1");
+        qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
+                         matrix, size);
+        g_free(matrix);
+    }
 }
 
 static void fdt_add_psci_node(const VirtMachineState *vms)
-- 
2.7.4

The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:

Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515

for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:

tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix coverity nit in int_to_float code
 * Don't set Invalid for float-to-int(MAXINT)
 * Fix fp_status_f16 tininess before rounding
 * Add various missing insns from the v8.2-FP16 extension
 * Fix sqrt_f16 exception raising
 * sdcard: Correct CRC16 offset in sd_function_switch()
 * tcg: Optionally log FPU state in TCG -d cpu logging

----------------------------------------------------------------
Alex Bennée (5):
      fpu/softfloat: int_to_float ensure r fully initialised
      target/arm: Implement FCMP for fp16
      target/arm: Implement FCSEL for fp16
      target/arm: Implement FMOV (immediate) for fp16
      target/arm: Fix sqrt_f16 exception raising

Peter Maydell (3):
      fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
      target/arm: Fix fp_status_f16 tininess before rounding
      tcg: Optionally log FPU state in TCG -d cpu logging

Philippe Mathieu-Daudé (1):
      sdcard: Correct CRC16 offset in sd_function_switch()

Richard Henderson (7):
      target/arm: Implement FMOV (general) for fp16
      target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
      target/arm: Implement FCVT (scalar, integer) for fp16
      target/arm: Implement FCVT (scalar, fixed-point) for fp16
      target/arm: Introduce and use read_fp_hreg
      target/arm: Implement FP data-processing (2 source) for fp16
      target/arm: Implement FP data-processing (3 source) for fp16

In float-to-integer conversion, if the floating point input
converts exactly to the largest or smallest integer that
fits in to the result type, this is not an overflow.
In this situation we were producing the correct result value,
but were incorrectly setting the Invalid flag.
For example for Arm A64, "FCVTAS w0, d0" on an input of
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.

Fix the boundary case to take the right half of the if()
statements.

This fixes a regression from 2.11 introduced by the softfloat
refactoring.

Cc: qemu-stable@nongnu.org
Fixes: ab52f973a50
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
---
 fpu/softfloat.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index XXXXXXX..XXXXXXX 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
             r = UINT64_MAX;
         }
         if (p.sign) {
-            if (r < -(uint64_t) min) {
+            if (r <= -(uint64_t) min) {
                 return -r;
             } else {
                 s->float_exception_flags = orig_flags | float_flag_invalid;
                 return min;
             }
         } else {
-            if (r < max) {
+            if (r <= max) {
                 return r;
             } else {
                 s->float_exception_flags = orig_flags | float_flag_invalid;
-- 
2.17.0

In commit d81ce0ef2c4f105 we added an extra float_status field
fp_status_fp16 for Arm, but forgot to initialize it correctly
by setting it to float_tininess_before_rounding. This currently
will only cause problems for the new V8_FP16 feature, since the
float-to-float conversion code doesn't use it yet. The effect
would be that we failed to set the Underflow IEEE exception flag
in all the cases where we should.

Add the missing initialization.

Fixes: d81ce0ef2c4f105
Cc: qemu-stable@nongnu.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
---
 target/arm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
                               &env->vfp.fp_status);
     set_float_detect_tininess(float_tininess_before_rounding,
                               &env->vfp.standard_fp_status);
+    set_float_detect_tininess(float_tininess_before_rounding,
+                              &env->vfp.fp_status_f16);
 #ifndef CONFIG_USER_ONLY
     if (kvm_enabled()) {
         kvm_arm_reset_vcpu(cpu);
-- 
2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

Adding the fp16 moves to/from general registers.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
             tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
             clear_vec_high(s, true, rd);
             break;
+        case 3:
+            /* 16 bit */
+            tmp = tcg_temp_new_i64();
+            tcg_gen_ext16u_i64(tmp, tcg_rn);
+            write_fp_dreg(s, rd, tmp);
+            tcg_temp_free_i64(tmp);
+            break;
+        default:
+            g_assert_not_reached();
         }
     } else {
         TCGv_i64 tcg_rd = cpu_reg(s, rd);
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
             /* 64 bits from top half */
             tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
             break;
+        case 3:
+            /* 16 bit */
+            tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
+            break;
+        default:
+            g_assert_not_reached();
         }
     }
 }
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
         case 0xa: /* 64 bit */
         case 0xd: /* 64 bit to top half of quad */
             break;
+        case 0x6: /* 16-bit float, 32-bit int */
+        case 0xe: /* 16-bit float, 64-bit int */
+            if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+                break;
+            }
+            /* fallthru */
         default:
             /* all other sf/type/rmode combinations are invalid */
             unallocated_encoding(s);
-- 
2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

Cc: qemu-stable@nongnu.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  6 +++
 target/arm/helper.c        | 38 ++++++++++++++-
 target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
 3 files changed, 122 insertions(+), 18 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
 DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
 DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
 DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
 DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
 DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
 DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
 DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
 
 DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
 DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
 #undef VFP_CONV_FIX_A64
 
 /* Conversion to/from f16 can overflow to infinity before/after scaling.
- * Therefore we convert to f64 (which does not round), scale,
- * and then convert f64 to f16 (which may round).
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
+ * vice versa for conversion to integer.
+ *
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
+ * For 64-bit integers, any integer that would cause rounding will also
+ * overflow to f16 infinity, so there is no double rounding problem.
  */
 
 static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
     return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
 }
 
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
+{
+    return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
+}
+
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
+{
+    return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
+}
+
 static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
 {
     if (unlikely(float16_is_any_nan(f))) {
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
     return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
+{
+    return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
+}
+
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
+{
+    return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
+}
+
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
+{
+    return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
+}
+
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
+{
+    return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
+}
+
 /* Set the current fp rounding mode and return the old one.
  * The argument is a softfloat float_round_ value.
  */
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
                            bool itof, int rmode, int scale, int sf, int type)
 {
     bool is_signed = !(opcode & 1);
-    bool is_double = type;
     TCGv_ptr tcg_fpstatus;
-    TCGv_i32 tcg_shift;
+    TCGv_i32 tcg_shift, tcg_single;
+    TCGv_i64 tcg_double;
 
-    tcg_fpstatus = get_fpstatus_ptr(false);
+    tcg_fpstatus = get_fpstatus_ptr(type == 3);
 
     tcg_shift = tcg_const_i32(64 - scale);
 
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
             tcg_int = tcg_extend;
         }
 
-        if (is_double) {
-            TCGv_i64 tcg_double = tcg_temp_new_i64();
+        switch (type) {
+        case 1: /* float64 */
+            tcg_double = tcg_temp_new_i64();
             if (is_signed) {
                 gen_helper_vfp_sqtod(tcg_double, tcg_int,
                                      tcg_shift, tcg_fpstatus);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
             }
             write_fp_dreg(s, rd, tcg_double);
             tcg_temp_free_i64(tcg_double);
-        } else {
-            TCGv_i32 tcg_single = tcg_temp_new_i32();
+            break;
+
+        case 0: /* float32 */
+            tcg_single = tcg_temp_new_i32();
             if (is_signed) {
                 gen_helper_vfp_sqtos(tcg_single, tcg_int,
                                      tcg_shift, tcg_fpstatus);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
             }
             write_fp_sreg(s, rd, tcg_single);
             tcg_temp_free_i32(tcg_single);
+            break;
+
+        case 3: /* float16 */
+            tcg_single = tcg_temp_new_i32();
+            if (is_signed) {
+                gen_helper_vfp_sqtoh(tcg_single, tcg_int,
+                                     tcg_shift, tcg_fpstatus);
+            } else {
+                gen_helper_vfp_uqtoh(tcg_single, tcg_int,
+                                     tcg_shift, tcg_fpstatus);
+            }
+            write_fp_sreg(s, rd, tcg_single);
+            tcg_temp_free_i32(tcg_single);
+            break;
+
+        default:
+            g_assert_not_reached();
         }
     } else {
         TCGv_i64 tcg_int = cpu_reg(s, rd);
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
 
         gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
 
-        if (is_double) {
-            TCGv_i64 tcg_double = read_fp_dreg(s, rn);
+        switch (type) {
+        case 1: /* float64 */
+            tcg_double = read_fp_dreg(s, rn);
             if (is_signed) {
                 if (!sf) {
                     gen_helper_vfp_tosld(tcg_int, tcg_double,
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
                                          tcg_shift, tcg_fpstatus);
                 }
             }
+            if (!sf) {
+                tcg_gen_ext32u_i64(tcg_int, tcg_int);
+            }
             tcg_temp_free_i64(tcg_double);
-        } else {
-            TCGv_i32 tcg_single = read_fp_sreg(s, rn);
+            break;
+
+        case 0: /* float32 */
+            tcg_single = read_fp_sreg(s, rn);
             if (sf) {
                 if (is_signed) {
                     gen_helper_vfp_tosqs(tcg_int, tcg_single,
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
                 tcg_temp_free_i32(tcg_dest);
             }
             tcg_temp_free_i32(tcg_single);
+            break;
+
+        case 3: /* float16 */
+            tcg_single = read_fp_sreg(s, rn);
+            if (sf) {
+                if (is_signed) {
+                    gen_helper_vfp_tosqh(tcg_int, tcg_single,
+                                         tcg_shift, tcg_fpstatus);
+                } else {
+                    gen_helper_vfp_touqh(tcg_int, tcg_single,
+                                         tcg_shift, tcg_fpstatus);
+                }
+            } else {
+                TCGv_i32 tcg_dest = tcg_temp_new_i32();
+                if (is_signed) {
+                    gen_helper_vfp_toslh(tcg_dest, tcg_single,
+                                         tcg_shift, tcg_fpstatus);
+                } else {
+                    gen_helper_vfp_toulh(tcg_dest, tcg_single,
+                                         tcg_shift, tcg_fpstatus);
+                }
+                tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
+                tcg_temp_free_i32(tcg_dest);
+            }
+            tcg_temp_free_i32(tcg_single);
+            break;
+
+        default:
+            g_assert_not_reached();
         }
 
         gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
         tcg_temp_free_i32(tcg_rmode);
-
-        if (!sf) {
-            tcg_gen_ext32u_i64(tcg_int, tcg_int);
-        }
     }
 
     tcg_temp_free_ptr(tcg_fpstatus);
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
         /* actual FP conversions */
         bool itof = extract32(opcode, 1, 1);
 
-        if (type > 1 || (rmode != 0 && opcode > 1)) {
+        if (rmode != 0 && opcode > 1) {
+            unallocated_encoding(s);
+            return;
+        }
+        switch (type) {
+        case 0: /* float32 */
+        case 1: /* float64 */
+            break;
+        case 3: /* float16 */
+            if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+                break;
+            }
+            /* fallthru */
+        default:
             unallocated_encoding(s);
             return;
         }
-- 
2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

Cc: qemu-stable@nongnu.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
     bool sf = extract32(insn, 31, 1);
     bool itof;
 
-    if (sbit || (type > 1)
-        || (!sf && scale < 32)) {
+    if (sbit || (!sf && scale < 32)) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    switch (type) {
+    case 0: /* float32 */
+    case 1: /* float64 */
+        break;
+    case 3: /* float16 */
+        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            break;
+        }
+        /* fallthru */
+    default:
         unallocated_encoding(s);
         return;
     }
-- 
2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 30 ++++++++++++++----------------
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
     return v;
 }
 
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
+{
+    TCGv_i32 v = tcg_temp_new_i32();
+
+    tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
+    return v;
+}
+
 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
  * If SVE is not enabled, then there are only 128 bits in the vector.
  */
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
 static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
 {
     TCGv_ptr fpst = NULL;
-    TCGv_i32 tcg_op = tcg_temp_new_i32();
+    TCGv_i32 tcg_op = read_fp_hreg(s, rn);
     TCGv_i32 tcg_res = tcg_temp_new_i32();
 
-    read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-
     switch (opcode) {
     case 0x0: /* FMOV */
         tcg_gen_mov_i32(tcg_res, tcg_op);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
         tcg_temp_free_i64(tcg_op2);
         tcg_temp_free_i64(tcg_res);
     } else {
-        TCGv_i32 tcg_op1 = tcg_temp_new_i32();
-        TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+        TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
+        TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
         TCGv_i64 tcg_res = tcg_temp_new_i64();
 
-        read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
-        read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
-
         gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
         gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
 
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
 
     fpst = get_fpstatus_ptr(true);
 
-    tcg_op1 = tcg_temp_new_i32();
-    tcg_op2 = tcg_temp_new_i32();
+    tcg_op1 = read_fp_hreg(s, rn);
+    tcg_op2 = read_fp_hreg(s, rm);
     tcg_res = tcg_temp_new_i32();
 
-    read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
-    read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
-
     switch (fpopcode) {
     case 0x03: /* FMULX */
         gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
     }
 
     if (is_scalar) {
-        TCGv_i32 tcg_op = tcg_temp_new_i32();
+        TCGv_i32 tcg_op = read_fp_hreg(s, rn);
         TCGv_i32 tcg_res = tcg_temp_new_i32();
 
-        read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
-
         switch (fpop) {
         case 0x1a: /* FCVTNS */
         case 0x1b: /* FCVTMS */
-- 
2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

We missed all of the scalar fp16 binary operations.

Cc: qemu-stable@nongnu.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
     tcg_temp_free_i64(tcg_res);
 }
 
+/* Floating-point data-processing (2 source) - half precision */
+static void handle_fp_2src_half(DisasContext *s, int opcode,
+                                int rd, int rn, int rm)
+{
+    TCGv_i32 tcg_op1;
+    TCGv_i32 tcg_op2;
+    TCGv_i32 tcg_res;
+    TCGv_ptr fpst;
+
+    tcg_res = tcg_temp_new_i32();
+    fpst = get_fpstatus_ptr(true);
+    tcg_op1 = read_fp_hreg(s, rn);
+    tcg_op2 = read_fp_hreg(s, rm);
+
+    switch (opcode) {
+    case 0x0: /* FMUL */
+        gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+        break;
+    case 0x1: /* FDIV */
+        gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+        break;
+    case 0x2: /* FADD */
+        gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+        break;
+    case 0x3: /* FSUB */
+        gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+        break;
+    case 0x4: /* FMAX */
+        gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+        break;
+    case 0x5: /* FMIN */
+        gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+        break;
+    case 0x6: /* FMAXNM */
+        gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+        break;
+    case 0x7: /* FMINNM */
+        gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+        break;
+    case 0x8: /* FNMUL */
+        gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+        tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    write_fp_sreg(s, rd, tcg_res);
+
+    tcg_temp_free_ptr(fpst);
+    tcg_temp_free_i32(tcg_op1);
+    tcg_temp_free_i32(tcg_op2);
+    tcg_temp_free_i32(tcg_res);
+}
+
 /* Floating point data-processing (2 source)
  *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
  * +---+---+---+-----------+------+---+------+--------+-----+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
         }
         handle_fp_2src_double(s, opcode, rd, rn, rm);
         break;
+    case 3:
+        if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            unallocated_encoding(s);
+            return;
+        }
+        if (!fp_access_check(s)) {
+            return;
+        }
+        handle_fp_2src_half(s, opcode, rd, rn, rm);
+        break;
     default:
         unallocated_encoding(s);
     }
-- 
2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

We missed all of the scalar fp16 fma operations.

Cc: qemu-stable@nongnu.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
     tcg_temp_free_i64(tcg_res);
 }
 
+/* Floating-point data-processing (3 source) - half precision */
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
+                                int rd, int rn, int rm, int ra)
+{
+    TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
+    TCGv_i32 tcg_res = tcg_temp_new_i32();
+    TCGv_ptr fpst = get_fpstatus_ptr(true);
+
+    tcg_op1 = read_fp_hreg(s, rn);
+    tcg_op2 = read_fp_hreg(s, rm);
+    tcg_op3 = read_fp_hreg(s, ra);
+
+    /* These are fused multiply-add, and must be done as one
+     * floating point operation with no rounding between the
+     * multiplication and addition steps.
+     * NB that doing the negations here as separate steps is
+     * correct : an input NaN should come out with its sign bit
+     * flipped if it is a negated-input.
+     */
+    if (o1 == true) {
+        tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
+    }
+
+    if (o0 != o1) {
+        tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
+    }
+
+    gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
+
+    write_fp_sreg(s, rd, tcg_res);
+
+    tcg_temp_free_ptr(fpst);
+    tcg_temp_free_i32(tcg_op1);
+    tcg_temp_free_i32(tcg_op2);
+    tcg_temp_free_i32(tcg_op3);
+    tcg_temp_free_i32(tcg_res);
+}
+
 /* Floating point data-processing (3 source)
  *   31  30  29 28       24 23  22  21  20  16  15  14  10 9    5 4    0
  * +---+---+---+-----------+------+----+------+----+------+------+------+
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
         }
         handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
         break;
+    case 3:
+        if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            unallocated_encoding(s);
+            return;
+        }
+        if (!fp_access_check(s)) {
+            return;
+        }
+        handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
+        break;
     default:
         unallocated_encoding(s);
     }
-- 
2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

These where missed out from the rest of the half-precision work.

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
[rth: Diagnose lack of FP16 before fp_access_check]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.h    |  2 +
 target/arm/helper-a64.c    | 10 +++++
 target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
 3 files changed, 83 insertions(+), 17 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -XXX,XX +XXX,XX @@
 DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
 DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
 DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
 DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
 DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
     return flags;
 }
 
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
+{
+    return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
+}
+
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
+{
+    return float_rel_to_flags(float16_compare(x, y, fp_status));
+}
+
 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
 {
     return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
     }
 }
 
-static void handle_fp_compare(DisasContext *s, bool is_double,
+static void handle_fp_compare(DisasContext *s, int size,
                               unsigned int rn, unsigned int rm,
                               bool cmp_with_zero, bool signal_all_nans)
 {
     TCGv_i64 tcg_flags = tcg_temp_new_i64();
-    TCGv_ptr fpst = get_fpstatus_ptr(false);
+    TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
 
-    if (is_double) {
+    if (size == MO_64) {
         TCGv_i64 tcg_vn, tcg_vm;
 
         tcg_vn = read_fp_dreg(s, rn);
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
         tcg_temp_free_i64(tcg_vn);
         tcg_temp_free_i64(tcg_vm);
     } else {
-        TCGv_i32 tcg_vn, tcg_vm;
+        TCGv_i32 tcg_vn = tcg_temp_new_i32();
+        TCGv_i32 tcg_vm = tcg_temp_new_i32();
 
-        tcg_vn = read_fp_sreg(s, rn);
+        read_vec_element_i32(s, tcg_vn, rn, 0, size);
         if (cmp_with_zero) {
-            tcg_vm = tcg_const_i32(0);
+            tcg_gen_movi_i32(tcg_vm, 0);
         } else {
-            tcg_vm = read_fp_sreg(s, rm);
+            read_vec_element_i32(s, tcg_vm, rm, 0, size);
         }
-        if (signal_all_nans) {
-            gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
-        } else {
-            gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+
+        switch (size) {
+        case MO_32:
+            if (signal_all_nans) {
+                gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+            } else {
+                gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+            }
+            break;
+        case MO_16:
+            if (signal_all_nans) {
+                gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+            } else {
+                gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+            }
+            break;
+        default:
+            g_assert_not_reached();
         }
+
         tcg_temp_free_i32(tcg_vn);
         tcg_temp_free_i32(tcg_vm);
     }
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
 static void disas_fp_compare(DisasContext *s, uint32_t insn)
 {
     unsigned int mos, type, rm, op, rn, opc, op2r;
+    int size;
 
     mos = extract32(insn, 29, 3);
-    type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
+    type = extract32(insn, 22, 2);
     rm = extract32(insn, 16, 5);
     op = extract32(insn, 14, 2);
     rn = extract32(insn, 5, 5);
     opc = extract32(insn, 3, 2);
     op2r = extract32(insn, 0, 3);
 
-    if (mos || op || op2r || type > 1) {
+    if (mos || op || op2r) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    switch (type) {
+    case 0:
+        size = MO_32;
+        break;
+    case 1:
+        size = MO_64;
+        break;
+    case 3:
+        size = MO_16;
+        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            break;
+        }
+        /* fallthru */
+    default:
         unallocated_encoding(s);
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
         return;
     }
 
-    handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
+    handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
 }
 
 /* Floating point conditional compare
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
     unsigned int mos, type, rm, cond, rn, op, nzcv;
     TCGv_i64 tcg_flags;
     TCGLabel *label_continue = NULL;
+    int size;
 
     mos = extract32(insn, 29, 3);
-    type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
+    type = extract32(insn, 22, 2);
     rm = extract32(insn, 16, 5);
     cond = extract32(insn, 12, 4);
     rn = extract32(insn, 5, 5);
     op = extract32(insn, 4, 1);
     nzcv = extract32(insn, 0, 4);
 
-    if (mos || type > 1) {
+    if (mos) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    switch (type) {
+    case 0:
+        size = MO_32;
+        break;
+    case 1:
+        size = MO_64;
+        break;
+    case 3:
+        size = MO_16;
+        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            break;
+        }
+        /* fallthru */
+    default:
         unallocated_encoding(s);
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
         gen_set_label(label_match);
     }
 
-    handle_fp_compare(s, type, rn, rm, false, op);
+    handle_fp_compare(s, size, rn, rm, false, op);
 
     if (cond < 0x0e) {
         gen_set_label(label_continue);
-- 
2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

These were missed out from the rest of the half-precision work.

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
[rth: Fix erroneous check vs type]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
     unsigned int mos, type, rm, cond, rn, rd;
     TCGv_i64 t_true, t_false, t_zero;
     DisasCompare64 c;
+    TCGMemOp sz;
 
     mos = extract32(insn, 29, 3);
-    type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
+    type = extract32(insn, 22, 2);
     rm = extract32(insn, 16, 5);
     cond = extract32(insn, 12, 4);
     rn = extract32(insn, 5, 5);
     rd = extract32(insn, 0, 5);
 
-    if (mos || type > 1) {
+    if (mos) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    switch (type) {
+    case 0:
+        sz = MO_32;
+        break;
+    case 1:
+        sz = MO_64;
+        break;
+    case 3:
+        sz = MO_16;
+        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            break;
+        }
+        /* fallthru */
+    default:
         unallocated_encoding(s);
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
         return;
     }
 
-    /* Zero extend sreg inputs to 64 bits now.  */
+    /* Zero extend sreg & hreg inputs to 64 bits now.  */
     t_true = tcg_temp_new_i64();
     t_false = tcg_temp_new_i64();
-    read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
-    read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
+    read_vec_element(s, t_true, rn, 0, sz);
+    read_vec_element(s, t_false, rm, 0, sz);
 
     a64_test_cc(&c, cond);
     t_zero = tcg_const_i64(0);
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(t_false);
     a64_free_cc(&c);
 
-    /* Note that sregs write back zeros to the high bits,
+    /* Note that sregs & hregs write back zeros to the high bits,
        and we've already done the zero-extension.  */
     write_fp_dreg(s, rd, t_true);
     tcg_temp_free_i64(t_true);
-- 
2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

All the hard work is already done by vfp_expand_imm, we just need to
make sure we pick up the correct size.

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
 {
     int rd = extract32(insn, 0, 5);
     int imm8 = extract32(insn, 13, 8);
-    int is_double = extract32(insn, 22, 2);
+    int type = extract32(insn, 22, 2);
     uint64_t imm;
     TCGv_i64 tcg_res;
+    TCGMemOp sz;
 
-    if (is_double > 1) {
+    switch (type) {
+    case 0:
+        sz = MO_32;
+        break;
+    case 1:
+        sz = MO_64;
+        break;
+    case 3:
+        sz = MO_16;
+        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+            break;
+        }
+        /* fallthru */
+    default:
         unallocated_encoding(s);
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
         return;
     }
 
-    imm = vfp_expand_imm(MO_32 + is_double, imm8);
+    imm = vfp_expand_imm(sz, imm8);
 
     tcg_res = tcg_const_i64(imm);
     write_fp_dreg(s, rd, tcg_res);
-- 
2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

We are meant to explicitly pass fpst, not cpu_env.

Cc: qemu-stable@nongnu.org
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
         tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
         break;
     case 0x3: /* FSQRT */
-        gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
+        fpst = get_fpstatus_ptr(true);
+        gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
         break;
     case 0x8: /* FRINTN */
     case 0x9: /* FRINTP */
-- 
2.17.0

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":

The block length is predefined to 512 bits

and "4.10.2 SD Status":

The SD Status contains status bits that are related to the SD Memory Card
  proprietary features and may be used for future application-specific usage.
  The size of the SD Status is one data block of 512 bit. The content of this
  register is transmitted to the Host over the DAT bus along with a 16-bit CRC.

Thus the 16-bit CRC goes at offset 64.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180509060104.4458-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/sd/sd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
         sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
     }
     memset(&sd->data[17], 0, 47);
-    stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
+    stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
 }
 
 static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
-- 
2.17.0

Usually the logging of the CPU state produced by -d cpu is sufficient
to diagnose problems, but sometimes you want to see the state of
the floating point registers as well. We don't want to enable that
by default as it adds a lot of extra data to the log; instead,
allow it to be optionally enabled via -d fpu.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
---
 include/qemu/log.h   | 1 +
 accel/tcg/cpu-exec.c | 9 ++++++---
 util/log.c           | 2 ++
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/include/qemu/log.h b/include/qemu/log.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/log.h
+++ b/include/qemu/log.h
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
 #define CPU_LOG_PAGE       (1 << 14)
 /* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
 #define CPU_LOG_TB_OP_IND  (1 << 16)
+#define CPU_LOG_TB_FPU     (1 << 17)
 
 /* Lock output for a series of related logs.  Since this is not needed
  * for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
     if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
         && qemu_log_in_addr_range(itb->pc)) {
         qemu_log_lock();
+        int flags = 0;
+        if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
+            flags |= CPU_DUMP_FPU;
+        }
 #if defined(TARGET_I386)
-        log_cpu_state(cpu, CPU_DUMP_CCOP);
-#else
-        log_cpu_state(cpu, 0);
+        flags |= CPU_DUMP_CCOP;
 #endif
+        log_cpu_state(cpu, flags);
         qemu_log_unlock();
     }
 #endif /* DEBUG_DISAS */
diff --git a/util/log.c b/util/log.c
index XXXXXXX..XXXXXXX 100644
--- a/util/log.c
+++ b/util/log.c
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
       "show trace before each executed TB (lots of logs)" },
     { CPU_LOG_TB_CPU, "cpu",
       "show CPU registers before entering a TB (lots of logs)" },
+    { CPU_LOG_TB_FPU, "fpu",
+      "include FPU registers in the 'cpu' logging" },
     { CPU_LOG_MMU, "mmu",
       "log MMU-related activities" },
     { CPU_LOG_PCALL, "pcall",
-- 
2.17.0