1
First ARM pullreq of the 2.10 cycle...
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The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
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3
thanks
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
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-- PMM
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The following changes since commit 64c8ed97cceabac4fafe17fca8d88ef08183f439:
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are available in the Git repository at:
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Open 2.10 development tree (2017-04-20 15:42:31 +0100)
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
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are available in the git repository at:
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for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170420
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docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
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for you to fetch changes up to f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa:
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16
arm: Remove workarounds for old M-profile exception return implementation (2017-04-20 17:39:17 +0100)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* implement M profile exception return properly
15
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
21
* cadence GEM: fix multiqueue handling bugs
16
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
22
* pxa2xx.c: QOMify a device
17
* Fix some errors in SVE/SME handling of MTE tags
23
* arm/kvm: Remove trailing newlines from error_report()
18
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
24
* stellaris: Don't hw_error() on bad register accesses
19
* hw/block/tc58128: Don't emit deprecation warning under qtest
25
* Add assertion about FSC format for syndrome registers
20
* tests/qtest: Fix handling of npcm7xx and GMAC tests
26
* Move excnames[] array into arm_log_exceptions()
21
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
27
* exynos: minor code cleanups
22
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
28
* hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
23
* Don't assert on vmload/vmsave of M-profile CPUs
29
* Fix APSR writes via M profile MSR
24
* hw/arm/smmuv3: add support for stage 1 access fault
25
* hw/arm/stellaris: QOM cleanups
26
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
27
* Improve Cortex_R52 IMPDEF sysreg modelling
28
* Allow access to SPSR_hyp from hyp mode
29
* New board model mps3-an536 (Cortex-R52)
30
30
31
----------------------------------------------------------------
31
----------------------------------------------------------------
32
Alistair Francis (5):
32
Luc Michel (1):
33
cadence_gem: Read the correct queue descriptor
33
hw/arm/smmuv3: add support for stage 1 access fault
34
cadence_gem: Correct the multi-queue can rx logic
35
cadence_gem: Correct the interupt logic
36
cadence_gem: Make the revision a property
37
xlnx-zynqmp: Set the Cadence GEM revision
38
34
39
Ard Biesheuvel (1):
35
Nabih Estefan (1):
40
hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
36
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
41
37
42
Ishani Chugh (1):
38
Peter Maydell (22):
43
arm/kvm: Remove trailing newlines from error_report()
39
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
40
hw/block/tc58128: Don't emit deprecation warning under qtest
41
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
42
tests/qtest/bios-tables-test: Allow changes to virt GTDT
43
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
44
tests/qtest/bios-tables-tests: Update virt golden reference
45
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
46
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
47
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
48
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
49
target/arm: The Cortex-R52 has a read-only CBAR
50
target/arm: Add Cortex-R52 IMPDEF sysregs
51
target/arm: Allow access to SPSR_hyp from hyp mode
52
hw/misc/mps2-scc: Fix condition for CFG3 register
53
hw/misc/mps2-scc: Factor out which-board conditionals
54
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
55
hw/arm/mps3r: Initial skeleton for mps3-an536 board
56
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
57
hw/arm/mps3r: Add UARTs
58
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
59
hw/arm/mps3r: Add remaining devices
60
docs: Add documentation for the mps3-an536 board
44
61
45
Krzysztof Kozlowski (3):
62
Philippe Mathieu-Daudé (5):
46
hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
63
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
47
hw/char/exynos4210_uart: Constify static array and few arguments
64
hw/arm/stellaris: Convert ADC controller to Resettable interface
48
hw/misc/exynos4210_pmu: Reorder local variables for readability
65
hw/arm/stellaris: Convert I2C controller to Resettable interface
66
hw/arm/stellaris: Add missing QOM 'machine' parent
67
hw/arm/stellaris: Add missing QOM 'SoC' parent
49
68
50
Peter Maydell (13):
69
Richard Henderson (6):
51
target/arm: Add missing entries to excnames[] for log strings
70
linux-user/aarch64: Choose SYNC as the preferred MTE mode
52
arm: Move excnames[] array into arm_log_exceptions()
71
target/arm: Fix nregs computation in do_{ld,st}_zpa
53
target/arm: Add assertion about FSC format for syndrome registers
72
target/arm: Adjust and validate mtedesc sizem1
54
stellaris: Don't hw_error() on bad register accesses
73
target/arm: Split out make_svemte_desc
55
arm: Don't implement BXJ on M-profile CPUs
74
target/arm: Handle mte in do_ldrq, do_ldro
56
arm: Thumb shift operations should not permit interworking branches
75
target/arm: Fix SVE/SME gross MTE suppression checks
57
arm: Factor out "generate right kind of step exception"
58
arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
59
arm: Move condition-failed codepath generation out of if()
60
arm: Abstract out "are we singlestepping" test to utility function
61
arm: Track M profile handler mode state in TB flags
62
arm: Implement M profile exception return properly
63
arm: Remove workarounds for old M-profile exception return implementation
64
76
65
Suramya Shah (1):
77
MAINTAINERS | 3 +-
66
hw/arm: Qomify pxa2xx.c
78
docs/system/arm/mps2.rst | 37 +-
79
configs/devices/arm-softmmu/default.mak | 1 +
80
hw/arm/smmuv3-internal.h | 1 +
81
include/hw/arm/smmu-common.h | 1 +
82
include/hw/arm/virt.h | 2 +
83
include/hw/misc/mps2-scc.h | 1 +
84
linux-user/aarch64/target_prctl.h | 29 +-
85
target/arm/internals.h | 2 +-
86
target/arm/tcg/translate-a64.h | 2 +
87
hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++
88
hw/arm/npcm7xx.c | 1 +
89
hw/arm/smmu-common.c | 11 +
90
hw/arm/smmuv3.c | 1 +
91
hw/arm/stellaris.c | 47 ++-
92
hw/arm/virt-acpi-build.c | 20 +-
93
hw/arm/virt.c | 60 ++-
94
hw/arm/xilinx_zynq.c | 2 +
95
hw/block/tc58128.c | 4 +-
96
hw/misc/mps2-scc.c | 138 ++++++-
97
hw/pci-host/raven.c | 1 +
98
target/arm/helper.c | 14 +-
99
target/arm/tcg/cpu32.c | 109 ++++++
100
target/arm/tcg/op_helper.c | 43 ++-
101
target/arm/tcg/sme_helper.c | 8 +-
102
target/arm/tcg/sve_helper.c | 12 +-
103
target/arm/tcg/translate-sme.c | 15 +-
104
target/arm/tcg/translate-sve.c | 83 +++--
105
target/arm/tcg/translate.c | 19 +-
106
tests/qtest/npcm7xx_emc-test.c | 5 +-
107
tests/qtest/npcm_gmac-test.c | 84 +----
108
hw/arm/Kconfig | 5 +
109
hw/arm/meson.build | 1 +
110
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
111
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
112
tests/qtest/meson.build | 4 +-
113
36 files changed, 1184 insertions(+), 222 deletions(-)
114
create mode 100644 hw/arm/mps3r.c
67
115
68
include/hw/net/cadence_gem.h | 1 +
69
target/arm/cpu.h | 10 +++
70
target/arm/internals.h | 21 -----
71
target/arm/translate.h | 5 ++
72
hw/arm/boot.c | 64 ++++++++++++---
73
hw/arm/exynos4_boards.c | 7 +-
74
hw/arm/pxa2xx.c | 14 ++--
75
hw/arm/stellaris.c | 60 ++++++++------
76
hw/arm/xlnx-zynqmp.c | 6 +-
77
hw/char/exynos4210_uart.c | 8 +-
78
hw/misc/exynos4210_pmu.c | 4 +-
79
hw/net/cadence_gem.c | 45 +++++++----
80
hw/timer/exynos4210_mct.c | 6 +-
81
hw/timer/exynos4210_pwm.c | 13 ++--
82
hw/timer/exynos4210_rtc.c | 19 ++---
83
target/arm/cpu.c | 43 +---------
84
target/arm/helper.c | 19 +++++
85
target/arm/kvm64.c | 4 +-
86
target/arm/op_helper.c | 23 ++++--
87
target/arm/translate.c | 181 +++++++++++++++++++++++++++++--------------
88
20 files changed, 341 insertions(+), 212 deletions(-)
89
diff view generated by jsdifflib
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Short declaration of 'i' was in the middle of declarations with
3
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
4
assignments. Make it a little bit more readable. Additionally switch
4
connect FIQ output of the GIC CPU interfaces to the CPU.
5
from "unsigned" to "unsigned int" as this pattern is more widely used.
6
No functional change.
7
5
8
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20240130152548.17855-1-philmd@linaro.org
10
Message-id: 20170313184750.429-4-krzk@kernel.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/misc/exynos4210_pmu.c | 4 ++--
11
hw/arm/xilinx_zynq.c | 2 ++
15
1 file changed, 2 insertions(+), 2 deletions(-)
12
1 file changed, 2 insertions(+)
16
13
17
diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/exynos4210_pmu.c
16
--- a/hw/arm/xilinx_zynq.c
20
+++ b/hw/misc/exynos4210_pmu.c
17
+++ b/hw/arm/xilinx_zynq.c
21
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
18
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
22
unsigned size)
19
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
23
{
20
sysbus_connect_irq(busdev, 0,
24
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
21
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
25
- unsigned i;
22
+ sysbus_connect_irq(busdev, 1,
26
const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
23
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
27
+ unsigned int i;
24
28
25
for (n = 0; n < 64; n++) {
29
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
26
pic[n] = qdev_get_gpio_in(dev, n);
30
if (reg_p->offset == offset) {
31
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
32
uint64_t val, unsigned size)
33
{
34
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
35
- unsigned i;
36
const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
37
+ unsigned int i;
38
39
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
40
if (reg_p->offset == offset) {
41
--
27
--
42
2.7.4
28
2.34.1
43
29
44
30
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The API does not generate an error for setting ASYNC | SYNC; that merely
4
constrains the selection vs the per-cpu default. For qemu linux-user,
5
choose SYNC as the default.
6
7
Cc: qemu-stable@nongnu.org
8
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
11
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
15
1 file changed, 17 insertions(+), 12 deletions(-)
16
17
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/linux-user/aarch64/target_prctl.h
20
+++ b/linux-user/aarch64/target_prctl.h
21
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
22
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
23
24
if (cpu_isar_feature(aa64_mte, cpu)) {
25
- switch (arg2 & PR_MTE_TCF_MASK) {
26
- case PR_MTE_TCF_NONE:
27
- case PR_MTE_TCF_SYNC:
28
- case PR_MTE_TCF_ASYNC:
29
- break;
30
- default:
31
- return -EINVAL;
32
- }
33
-
34
/*
35
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
36
- * Note that the syscall values are consistent with hw.
37
+ *
38
+ * The kernel has a per-cpu configuration for the sysadmin,
39
+ * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
40
+ * which qemu does not implement.
41
+ *
42
+ * Because there is no performance difference between the modes, and
43
+ * because SYNC is most useful for debugging MTE errors, choose SYNC
44
+ * as the preferred mode. With this preference, and the way the API
45
+ * uses only two bits, there is no way for the program to select
46
+ * ASYMM mode.
47
*/
48
- env->cp15.sctlr_el[1] =
49
- deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
50
+ unsigned tcf = 0;
51
+ if (arg2 & PR_MTE_TCF_SYNC) {
52
+ tcf = 1;
53
+ } else if (arg2 & PR_MTE_TCF_ASYNC) {
54
+ tcf = 2;
55
+ }
56
+ env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
57
58
/*
59
* Write PR_MTE_TAG to GCR_EL1[Exclude].
60
--
61
2.34.1
diff view generated by jsdifflib
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The static array exynos4210_uart_regs with register values is not
3
The field is encoded as [0-3], which is convenient for
4
modified so it can be made const.
4
indexing our array of function pointers, but the true
5
value is [1-4]. Adjust before calling do_mem_zpa.
5
6
6
Few other functions accept driver or uart state as an argument but they
7
Add an assert, and move the comment re passing ZT to
7
do not change it and do not cast it so this can be made const for code
8
the helper back next to the relevant code.
8
safeness.
9
9
10
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
10
Cc: qemu-stable@nongnu.org
11
Message-id: 20170313184750.429-3-krzk@kernel.org
11
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
14
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
17
---
15
hw/char/exynos4210_uart.c | 8 ++++----
18
target/arm/tcg/translate-sve.c | 16 ++++++++--------
16
1 file changed, 4 insertions(+), 4 deletions(-)
19
1 file changed, 8 insertions(+), 8 deletions(-)
17
20
18
diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
21
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
19
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/exynos4210_uart.c
23
--- a/target/arm/tcg/translate-sve.c
21
+++ b/hw/char/exynos4210_uart.c
24
+++ b/target/arm/tcg/translate-sve.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210UartReg {
25
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
23
uint32_t reset_value;
26
TCGv_ptr t_pg;
24
} Exynos4210UartReg;
27
int desc = 0;
25
28
26
-static Exynos4210UartReg exynos4210_uart_regs[] = {
29
- /*
27
+static const Exynos4210UartReg exynos4210_uart_regs[] = {
30
- * For e.g. LD4, there are not enough arguments to pass all 4
28
{"ULCON", ULCON, 0x00000000},
31
- * registers as pointers, so encode the regno into the data field.
29
{"UCON", UCON, 0x00003000},
32
- * For consistency, do this even for LD1.
30
{"UFCON", UFCON, 0x00000000},
33
- */
31
@@ -XXX,XX +XXX,XX @@ static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
34
+ assert(mte_n >= 1 && mte_n <= 4);
32
return ret;
35
if (s->mte_active[0]) {
36
int msz = dtype_msz(dtype);
37
38
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
39
addr = clean_data_tbi(s, addr);
40
}
41
42
+ /*
43
+ * For e.g. LD4, there are not enough arguments to pass all 4
44
+ * registers as pointers, so encode the regno into the data field.
45
+ * For consistency, do this even for LD1.
46
+ */
47
desc = simd_desc(vsz, vsz, zt | desc);
48
t_pg = tcg_temp_new_ptr();
49
50
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
51
* accessible via the instruction encoding.
52
*/
53
assert(fn != NULL);
54
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
55
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
33
}
56
}
34
57
35
-static int fifo_elements_number(Exynos4210UartFIFO *q)
58
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
36
+static int fifo_elements_number(const Exynos4210UartFIFO *q)
59
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
37
{
60
if (nreg == 0) {
38
if (q->sp < q->rp) {
61
/* ST1 */
39
return q->size - q->rp + q->sp;
62
fn = fn_single[s->mte_active[0]][be][msz][esz];
40
@@ -XXX,XX +XXX,XX @@ static int fifo_elements_number(Exynos4210UartFIFO *q)
63
- nreg = 1;
41
return q->sp - q->rp;
64
} else {
65
/* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
66
assert(msz == esz);
67
fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
68
}
69
assert(fn != NULL);
70
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
71
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
42
}
72
}
43
73
44
-static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
74
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
45
+static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
46
{
47
return q->size - fifo_elements_number(q);
48
}
49
@@ -XXX,XX +XXX,XX @@ static void fifo_reset(Exynos4210UartFIFO *q)
50
q->rp = 0;
51
}
52
53
-static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
54
+static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
55
{
56
uint32_t level = 0;
57
uint32_t reg;
58
--
75
--
59
2.7.4
76
2.34.1
60
61
diff view generated by jsdifflib
1
Recent changes have added new EXCP_ values to ARM but forgot
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to update the excnames[] array which is used to provide
3
human-readable strings when printing information about the
4
exception for debug logging. Add the missing entries, and
5
add a comment to the list of #defines to help avoid the mistake
6
being repeated in future.
7
2
3
When we added SVE_MTEDESC_SHIFT, we effectively limited the
4
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
5
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
6
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
7
8
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Message-id: 1491486340-25988-1-git-send-email-peter.maydell@linaro.org
12
---
14
---
13
target/arm/cpu.h | 1 +
15
target/arm/internals.h | 2 +-
14
target/arm/internals.h | 2 ++
16
target/arm/tcg/translate-sve.c | 7 ++++---
15
2 files changed, 3 insertions(+)
17
2 files changed, 5 insertions(+), 4 deletions(-)
16
18
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@
22
#define EXCP_SEMIHOST 16 /* semihosting call */
23
#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
24
#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
25
+/* NB: new EXCP_ defines should be added to the excnames[] array too */
26
27
#define ARMV7M_EXCP_RESET 1
28
#define ARMV7M_EXCP_NMI 2
29
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
30
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/internals.h
21
--- a/target/arm/internals.h
32
+++ b/target/arm/internals.h
22
+++ b/target/arm/internals.h
33
@@ -XXX,XX +XXX,XX @@ static const char * const excnames[] = {
23
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2)
34
[EXCP_VIRQ] = "Virtual IRQ",
24
FIELD(MTEDESC, TCMA, 6, 2)
35
[EXCP_VFIQ] = "Virtual FIQ",
25
FIELD(MTEDESC, WRITE, 8, 1)
36
[EXCP_SEMIHOST] = "Semihosting call",
26
FIELD(MTEDESC, ALIGN, 9, 3)
37
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
27
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
38
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
28
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */
39
};
29
40
30
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
41
/* Scale factor for generic timers, ie number of ns per tick.
31
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
32
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/translate-sve.c
35
+++ b/target/arm/tcg/translate-sve.c
36
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
37
{
38
unsigned vsz = vec_full_reg_size(s);
39
TCGv_ptr t_pg;
40
+ uint32_t sizem1;
41
int desc = 0;
42
43
assert(mte_n >= 1 && mte_n <= 4);
44
+ sizem1 = (mte_n << dtype_msz(dtype)) - 1;
45
+ assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
46
if (s->mte_active[0]) {
47
- int msz = dtype_msz(dtype);
48
-
49
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
50
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
51
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
52
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
53
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
54
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
55
desc <<= SVE_MTEDESC_SHIFT;
56
} else {
57
addr = clean_data_tbi(s, addr);
42
--
58
--
43
2.7.4
59
2.34.1
44
45
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Share code that creates mtedesc and embeds within simd_desc.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/tcg/translate-a64.h | 2 ++
13
target/arm/tcg/translate-sme.c | 15 +++--------
14
target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
15
3 files changed, 31 insertions(+), 33 deletions(-)
16
17
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/tcg/translate-a64.h
20
+++ b/target/arm/tcg/translate-a64.h
21
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
22
bool sve_access_check(DisasContext *s);
23
bool sme_enabled_check(DisasContext *s);
24
bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
25
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
26
+ uint32_t msz, bool is_write, uint32_t data);
27
28
/* This function corresponds to CheckStreamingSVEEnabled. */
29
static inline bool sme_sm_enabled_check(DisasContext *s)
30
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/tcg/translate-sme.c
33
+++ b/target/arm/tcg/translate-sme.c
34
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
35
36
TCGv_ptr t_za, t_pg;
37
TCGv_i64 addr;
38
- int svl, desc = 0;
39
+ uint32_t desc;
40
bool be = s->be_data == MO_BE;
41
bool mte = s->mte_active[0];
42
43
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
44
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
45
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
46
47
- if (mte) {
48
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
49
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
50
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
51
- desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
52
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
53
- desc <<= SVE_MTEDESC_SHIFT;
54
- } else {
55
+ if (!mte) {
56
addr = clean_data_tbi(s, addr);
57
}
58
- svl = streaming_vec_reg_size(s);
59
- desc = simd_desc(svl, svl, desc);
60
+
61
+ desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
62
63
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
64
tcg_constant_i32(desc));
65
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/tcg/translate-sve.c
68
+++ b/target/arm/tcg/translate-sve.c
69
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
70
3, 2, 1, 3
71
};
72
73
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
74
- int dtype, uint32_t mte_n, bool is_write,
75
- gen_helper_gvec_mem *fn)
76
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
77
+ uint32_t msz, bool is_write, uint32_t data)
78
{
79
- unsigned vsz = vec_full_reg_size(s);
80
- TCGv_ptr t_pg;
81
uint32_t sizem1;
82
- int desc = 0;
83
+ uint32_t desc = 0;
84
85
- assert(mte_n >= 1 && mte_n <= 4);
86
- sizem1 = (mte_n << dtype_msz(dtype)) - 1;
87
+ /* Assert all of the data fits, with or without MTE enabled. */
88
+ assert(nregs >= 1 && nregs <= 4);
89
+ sizem1 = (nregs << msz) - 1;
90
assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
91
+ assert(data < 1u << SVE_MTEDESC_SHIFT);
92
+
93
if (s->mte_active[0]) {
94
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
95
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
96
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
97
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
98
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
99
desc <<= SVE_MTEDESC_SHIFT;
100
- } else {
101
+ }
102
+ return simd_desc(vsz, vsz, desc | data);
103
+}
104
+
105
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
106
+ int dtype, uint32_t nregs, bool is_write,
107
+ gen_helper_gvec_mem *fn)
108
+{
109
+ TCGv_ptr t_pg;
110
+ uint32_t desc;
111
+
112
+ if (!s->mte_active[0]) {
113
addr = clean_data_tbi(s, addr);
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
117
* registers as pointers, so encode the regno into the data field.
118
* For consistency, do this even for LD1.
119
*/
120
- desc = simd_desc(vsz, vsz, zt | desc);
121
+ desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
122
+ dtype_msz(dtype), is_write, zt);
123
t_pg = tcg_temp_new_ptr();
124
125
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
126
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
127
int scale, TCGv_i64 scalar, int msz, bool is_write,
128
gen_helper_gvec_mem_scatter *fn)
129
{
130
- unsigned vsz = vec_full_reg_size(s);
131
TCGv_ptr t_zm = tcg_temp_new_ptr();
132
TCGv_ptr t_pg = tcg_temp_new_ptr();
133
TCGv_ptr t_zt = tcg_temp_new_ptr();
134
- int desc = 0;
135
-
136
- if (s->mte_active[0]) {
137
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
138
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
139
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
140
- desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
141
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
142
- desc <<= SVE_MTEDESC_SHIFT;
143
- }
144
- desc = simd_desc(vsz, vsz, desc | scale);
145
+ uint32_t desc;
146
147
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
148
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
149
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
150
+
151
+ desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
152
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
153
}
154
155
--
156
2.34.1
diff view generated by jsdifflib
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
qemu_log_mask() and error_report() are preferred over fprintf() for
3
These functions "use the standard load helpers", but
4
logging errors. Also remove square brackets [] and additional new line
4
fail to clean_data_tbi or populate mtedesc.
5
characters in printed messages.
6
5
7
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
6
Cc: qemu-stable@nongnu.org
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20170313184750.429-2-krzk@kernel.org
10
[PMM: wrapped long line]
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
10
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
12
---
14
hw/arm/exynos4_boards.c | 7 ++++---
13
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
15
hw/timer/exynos4210_mct.c | 6 ++++--
14
1 file changed, 13 insertions(+), 2 deletions(-)
16
hw/timer/exynos4210_pwm.c | 13 +++++++------
17
hw/timer/exynos4210_rtc.c | 19 ++++++++++---------
18
4 files changed, 25 insertions(+), 20 deletions(-)
19
15
20
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
16
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/exynos4_boards.c
18
--- a/target/arm/tcg/translate-sve.c
23
+++ b/hw/arm/exynos4_boards.c
19
+++ b/target/arm/tcg/translate-sve.c
24
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
25
*/
21
unsigned vsz = vec_full_reg_size(s);
26
22
TCGv_ptr t_pg;
27
#include "qemu/osdep.h"
23
int poff;
28
+#include "qemu/error-report.h"
24
+ uint32_t desc;
29
#include "qemu-common.h"
25
30
#include "cpu.h"
26
/* Load the first quadword using the normal predicated load helpers. */
31
#include "sysemu/sysemu.h"
27
+ if (!s->mte_active[0]) {
32
@@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
28
+ addr = clean_data_tbi(s, addr);
33
MachineClass *mc = MACHINE_GET_CLASS(machine);
29
+ }
34
30
+
35
if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
31
poff = pred_full_reg_offset(s, pg);
36
- fprintf(stderr, "%s board supports only %d CPU cores. Ignoring smp_cpus"
32
if (vsz > 16) {
37
- " value.\n",
33
/*
38
- mc->name, EXYNOS4210_NCPUS);
34
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
39
+ error_report("%s board supports only %d CPU cores, ignoring smp_cpus"
35
40
+ " value",
36
gen_helper_gvec_mem *fn
41
+ mc->name, EXYNOS4210_NCPUS);
37
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
38
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
39
+ desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
40
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
41
42
/* Replicate that first quadword. */
43
if (vsz > 16) {
44
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
45
unsigned vsz_r32;
46
TCGv_ptr t_pg;
47
int poff, doff;
48
+ uint32_t desc;
49
50
if (vsz < 32) {
51
/*
52
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
42
}
53
}
43
54
44
exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
55
/* Load the first octaword using the normal predicated load helpers. */
45
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
56
+ if (!s->mte_active[0]) {
46
index XXXXXXX..XXXXXXX 100644
57
+ addr = clean_data_tbi(s, addr);
47
--- a/hw/timer/exynos4210_mct.c
58
+ }
48
+++ b/hw/timer/exynos4210_mct.c
59
49
@@ -XXX,XX +XXX,XX @@
60
poff = pred_full_reg_offset(s, pg);
50
*/
61
if (vsz > 32) {
51
62
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
52
#include "qemu/osdep.h"
63
53
+#include "qemu/log.h"
64
gen_helper_gvec_mem *fn
54
#include "hw/sysbus.h"
65
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
55
#include "qemu/timer.h"
66
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
56
#include "qemu/main-loop.h"
67
+ desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
57
@@ -XXX,XX +XXX,XX @@ break;
68
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
58
case L0_TCNTO: case L1_TCNTO:
69
59
case L0_ICNTO: case L1_ICNTO:
70
/*
60
case L0_FRCNTO: case L1_FRCNTO:
71
* Replicate that first octaword.
61
- fprintf(stderr, "\n[exynos4210.mct: write to RO register "
62
- TARGET_FMT_plx "]\n\n", offset);
63
+ qemu_log_mask(LOG_GUEST_ERROR,
64
+ "exynos4210.mct: write to RO register " TARGET_FMT_plx,
65
+ offset);
66
break;
67
68
case L0_INT_CSTAT: case L1_INT_CSTAT:
69
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/timer/exynos4210_pwm.c
72
+++ b/hw/timer/exynos4210_pwm.c
73
@@ -XXX,XX +XXX,XX @@
74
*/
75
76
#include "qemu/osdep.h"
77
+#include "qemu/log.h"
78
#include "hw/sysbus.h"
79
#include "qemu/timer.h"
80
#include "qemu-common.h"
81
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
82
break;
83
84
default:
85
- fprintf(stderr,
86
- "[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n",
87
- offset);
88
+ qemu_log_mask(LOG_GUEST_ERROR,
89
+ "exynos4210.pwm: bad read offset " TARGET_FMT_plx,
90
+ offset);
91
break;
92
}
93
return value;
94
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset,
95
break;
96
97
default:
98
- fprintf(stderr,
99
- "[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n",
100
- offset);
101
+ qemu_log_mask(LOG_GUEST_ERROR,
102
+ "exynos4210.pwm: bad write offset " TARGET_FMT_plx,
103
+ offset);
104
break;
105
106
}
107
diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/timer/exynos4210_rtc.c
110
+++ b/hw/timer/exynos4210_rtc.c
111
@@ -XXX,XX +XXX,XX @@
112
*/
113
114
#include "qemu/osdep.h"
115
+#include "qemu/log.h"
116
#include "hw/sysbus.h"
117
#include "qemu/timer.h"
118
#include "qemu-common.h"
119
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
120
break;
121
122
default:
123
- fprintf(stderr,
124
- "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n",
125
- offset);
126
+ qemu_log_mask(LOG_GUEST_ERROR,
127
+ "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
128
+ offset);
129
break;
130
}
131
return value;
132
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
133
if (value > TICNT_THRESHOLD) {
134
s->reg_ticcnt = value;
135
} else {
136
- fprintf(stderr,
137
- "[exynos4210.rtc: bad TICNT value %u ]\n",
138
- (uint32_t)value);
139
+ qemu_log_mask(LOG_GUEST_ERROR,
140
+ "exynos4210.rtc: bad TICNT value %u",
141
+ (uint32_t)value);
142
}
143
break;
144
145
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
146
break;
147
148
default:
149
- fprintf(stderr,
150
- "[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n",
151
- offset);
152
+ qemu_log_mask(LOG_GUEST_ERROR,
153
+ "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
154
+ offset);
155
break;
156
157
}
158
--
72
--
159
2.7.4
73
2.34.1
160
161
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Correct the buffer descriptor busy logic to work correctly when using
3
The TBI and TCMA bits are located within mtedesc, not desc.
4
multiple queues.
5
4
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
5
Cc: qemu-stable@nongnu.org
7
Message-id: 8a7e8059984e27d46a276a66299d035a0afd280f.1491947224.git.alistair.francis@xilinx.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/net/cadence_gem.c | 17 ++++++++++-------
12
target/arm/tcg/sme_helper.c | 8 ++++----
12
1 file changed, 10 insertions(+), 7 deletions(-)
13
target/arm/tcg/sve_helper.c | 12 ++++++------
14
2 files changed, 10 insertions(+), 10 deletions(-)
13
15
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
16
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
18
--- a/target/arm/tcg/sme_helper.c
17
+++ b/hw/net/cadence_gem.c
19
+++ b/target/arm/tcg/sme_helper.c
18
@@ -XXX,XX +XXX,XX @@ static int gem_can_receive(NetClientState *nc)
20
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
21
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
22
23
/* Perform gross MTE suppression early. */
24
- if (!tbi_check(desc, bit55) ||
25
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
26
+ if (!tbi_check(mtedesc, bit55) ||
27
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
28
mtedesc = 0;
19
}
29
}
20
30
21
for (i = 0; i < s->num_priority_queues; i++) {
31
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
22
- if (rx_desc_get_ownership(s->rx_desc[i]) == 1) {
32
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
23
- if (s->can_rx_state != 2) {
33
24
- s->can_rx_state = 2;
34
/* Perform gross MTE suppression early. */
25
- DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n",
35
- if (!tbi_check(desc, bit55) ||
26
- i, s->rx_desc_addr[i]);
36
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
27
- }
37
+ if (!tbi_check(mtedesc, bit55) ||
28
- return 0;
38
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
29
+ if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
39
mtedesc = 0;
30
+ break;
31
+ }
32
+ };
33
+
34
+ if (i == s->num_priority_queues) {
35
+ if (s->can_rx_state != 2) {
36
+ s->can_rx_state = 2;
37
+ DB_PRINT("can't receive - all the buffer descriptors are busy\n");
38
}
39
+ return 0;
40
}
40
}
41
41
42
if (s->can_rx_state != 0) {
42
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/tcg/sve_helper.c
45
+++ b/target/arm/tcg/sve_helper.c
46
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
47
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
48
49
/* Perform gross MTE suppression early. */
50
- if (!tbi_check(desc, bit55) ||
51
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
52
+ if (!tbi_check(mtedesc, bit55) ||
53
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
54
mtedesc = 0;
55
}
56
57
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
58
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
59
60
/* Perform gross MTE suppression early. */
61
- if (!tbi_check(desc, bit55) ||
62
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
63
+ if (!tbi_check(mtedesc, bit55) ||
64
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
65
mtedesc = 0;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
69
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
70
71
/* Perform gross MTE suppression early. */
72
- if (!tbi_check(desc, bit55) ||
73
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
74
+ if (!tbi_check(mtedesc, bit55) ||
75
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
76
mtedesc = 0;
77
}
78
43
--
79
--
44
2.7.4
80
2.34.1
45
46
diff view generated by jsdifflib
1
From: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
1
The raven_io_ops MemoryRegionOps is the only one in the source tree
2
which sets .valid.unaligned to indicate that it should support
3
unaligned accesses and which does not also set .impl.unaligned to
4
indicate that its read and write functions can do the unaligned
5
handling themselves. This is a problem, because at the moment the
6
core memory system does not implement the support for handling
7
unaligned accesses by doing a series of aligned accesses and
8
combining them (system/memory.c:access_with_adjusted_size() has a
9
TODO comment noting this).
2
10
3
Signed-off-by: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
11
Fortunately raven_io_read() and raven_io_write() will correctly deal
4
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
12
with the case of being passed an unaligned address, so we can fix the
5
Message-id: 1491629987-6826-1-git-send-email-chugh.ishani@research.iiit.ac.in
13
missing unaligned access support by setting .impl.unaligned in the
14
MemoryRegionOps struct.
15
16
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Tested-by: Cédric Le Goater <clg@redhat.com>
19
Reviewed-by: Cédric Le Goater <clg@redhat.com>
20
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
7
---
21
---
8
target/arm/kvm64.c | 4 ++--
22
hw/pci-host/raven.c | 1 +
9
1 file changed, 2 insertions(+), 2 deletions(-)
23
1 file changed, 1 insertion(+)
10
24
11
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
25
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
12
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/kvm64.c
27
--- a/hw/pci-host/raven.c
14
+++ b/target/arm/kvm64.c
28
+++ b/hw/pci-host/raven.c
15
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
16
* single step at this point so something has gone wrong.
30
.write = raven_io_write,
17
*/
31
.endianness = DEVICE_LITTLE_ENDIAN,
18
error_report("%s: guest single-step while debugging unsupported"
32
.impl.max_access_size = 4,
19
- " (%"PRIx64", %"PRIx32")\n",
33
+ .impl.unaligned = true,
20
+ " (%"PRIx64", %"PRIx32")",
34
.valid.unaligned = true,
21
__func__, env->pc, debug_exit->hsr);
35
};
22
return false;
23
}
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
25
break;
26
}
27
default:
28
- error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")\n",
29
+ error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")",
30
__func__, debug_exit->hsr, env->pc);
31
}
32
36
33
--
37
--
34
2.7.4
38
2.34.1
35
39
36
40
diff view generated by jsdifflib
1
For M-profile CPUs, the BXJ instruction does not exist at all, and
1
Suppress the deprecation warning when we're running under qtest,
2
the encoding should always UNDEF. We were accidentally implementing
2
to avoid "make check" including warning messages in its output.
3
it to behave like A-profile BXJ; correct the error.
4
3
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
6
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
8
Message-id: 1491844419-12485-2-git-send-email-peter.maydell@linaro.org
9
---
7
---
10
target/arm/translate.c | 7 ++++++-
8
hw/block/tc58128.c | 4 +++-
11
1 file changed, 6 insertions(+), 1 deletion(-)
9
1 file changed, 3 insertions(+), 1 deletion(-)
12
10
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
11
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
13
--- a/hw/block/tc58128.c
16
+++ b/target/arm/translate.c
14
+++ b/hw/block/tc58128.c
17
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
15
@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
18
}
16
19
break;
17
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
20
case 4: /* bxj */
18
{
21
- /* Trivial implementation equivalent to bx. */
19
- warn_report_once("The TC58128 flash device is deprecated");
22
+ /* Trivial implementation equivalent to bx.
20
+ if (!qtest_enabled()) {
23
+ * This instruction doesn't exist at all for M-profile.
21
+ warn_report_once("The TC58128 flash device is deprecated");
24
+ */
22
+ }
25
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
23
init_dev(&tc58128_devs[0], zone1);
26
+ goto illegal_op;
24
init_dev(&tc58128_devs[1], zone2);
27
+ }
25
return sh7750_register_io_device(s, &tc58128);
28
tmp = load_reg(s, rn);
29
gen_bx(s, tmp);
30
break;
31
--
26
--
32
2.7.4
27
2.34.1
33
28
34
29
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
2
because we already get the coverage of those tests via qtests_arm,
3
and we don't want to use extra CI minutes testing them twice.
2
4
3
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
5
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
that change.
5
Message-id: 026dbe01a1d42619eee30ce3f2079741bf04bc73.1491947224.git.alistair.francis@xilinx.com
7
8
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
7
---
12
---
8
hw/arm/xlnx-zynqmp.c | 6 +++++-
13
tests/qtest/meson.build | 1 -
9
1 file changed, 5 insertions(+), 1 deletion(-)
14
1 file changed, 1 deletion(-)
10
15
11
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/xlnx-zynqmp.c
18
--- a/tests/qtest/meson.build
14
+++ b/hw/arm/xlnx-zynqmp.c
19
+++ b/tests/qtest/meson.build
15
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
16
#define ARM_PHYS_TIMER_PPI 30
21
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
17
#define ARM_VIRT_TIMER_PPI 27
22
(config_all_accel.has_key('CONFIG_TCG') and \
18
23
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
19
+#define GEM_REVISION 0x40070106
24
- (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
20
+
25
['arm-cpu-features',
21
#define GIC_BASE_ADDR 0xf9000000
26
'numa-test',
22
#define GIC_DIST_ADDR 0xf9010000
27
'boot-serial-test',
23
#define GIC_CPU_ADDR 0xf9020000
24
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
25
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
26
qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
27
}
28
+ object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
29
+ &error_abort);
30
object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
31
- &error_abort);
32
+ &error_abort);
33
object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
34
if (err) {
35
error_propagate(errp, err);
36
--
28
--
37
2.7.4
29
2.34.1
38
30
39
31
diff view generated by jsdifflib
New patch
1
Allow changes to the virt GTDT -- we are going to add the IRQ
2
entry for a new timer to it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
6
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
7
---
8
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/bios-tables-test-allowed-diff.h
14
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
15
@@ -1 +1,3 @@
16
/* List of comma-separated changed AML files to ignore */
17
+"tests/data/acpi/virt/FACP",
18
+"tests/data/acpi/virt/GTDT",
19
--
20
2.34.1
diff view generated by jsdifflib
New patch
1
1
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
2
non-secure EL2 virtual timer. We implemented the timer itself in the
3
CPU model, but never wired up its IRQ line to the GIC.
4
5
Wire up the IRQ line (this is always safe whether the CPU has the
6
interrupt or not, since it always creates the outbound IRQ line).
7
Report it to the guest via dtb and ACPI if the CPU has the feature.
8
9
The DTB binding is documented in the kernel's
10
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
11
and the ACPI table entries are documented in the ACPI specification
12
version 6.3 or later.
13
14
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
15
FADT table rev to show that we might be using 6.3 features.
16
17
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
18
versions prior to edk2-stable202311, for users who use the virt board
19
with 'virtualization=on' to enable EL2 emulation and are booting an
20
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
21
that EDK2 will assert on bootup:
22
23
ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
24
25
If you see that assertion you should do one of:
26
* update your EDK2 binaries to edk2-stable202311 or newer
27
* use the 'virt-8.2' versioned machine type
28
* not use 'virtualization=on'
29
30
(The versions shipped with QEMU itself have the fix.)
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
34
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
35
---
36
include/hw/arm/virt.h | 2 ++
37
hw/arm/virt-acpi-build.c | 20 ++++++++++----
38
hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------
39
3 files changed, 67 insertions(+), 15 deletions(-)
40
41
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/virt.h
44
+++ b/include/hw/arm/virt.h
45
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
46
/* Machines < 6.2 have no support for describing cpu topology to guest */
47
bool no_cpu_topology;
48
bool no_tcg_lpa2;
49
+ bool no_ns_el2_virt_timer_irq;
50
};
51
52
struct VirtMachineState {
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
54
PCIBus *bus;
55
char *oem_id;
56
char *oem_table_id;
57
+ bool ns_el2_virt_timer_irq;
58
};
59
60
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
61
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/virt-acpi-build.c
64
+++ b/hw/arm/virt-acpi-build.c
65
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
}
67
68
/*
69
- * ACPI spec, Revision 5.1
70
- * 5.2.24 Generic Timer Description Table (GTDT)
71
+ * ACPI spec, Revision 6.5
72
+ * 5.2.25 Generic Timer Description Table (GTDT)
73
*/
74
static void
75
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
76
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
77
uint32_t irqflags = vmc->claim_edge_triggered_timers ?
78
1 : /* Interrupt is Edge triggered */
79
0; /* Interrupt is Level triggered */
80
- AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
81
+ AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
82
.oem_table_id = vms->oem_table_id };
83
84
acpi_table_begin(&table, table_data);
85
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
86
build_append_int_noprefix(table_data, 0, 4);
87
/* Platform Timer Offset */
88
build_append_int_noprefix(table_data, 0, 4);
89
-
90
+ if (vms->ns_el2_virt_timer_irq) {
91
+ /* Virtual EL2 Timer GSIV */
92
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
93
+ /* Virtual EL2 Timer Flags */
94
+ build_append_int_noprefix(table_data, irqflags, 4);
95
+ } else {
96
+ build_append_int_noprefix(table_data, 0, 4);
97
+ build_append_int_noprefix(table_data, 0, 4);
98
+ }
99
acpi_table_end(linker, &table);
100
}
101
102
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
103
static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
104
VirtMachineState *vms, unsigned dsdt_tbl_offset)
105
{
106
- /* ACPI v6.0 */
107
+ /* ACPI v6.3 */
108
AcpiFadtData fadt = {
109
.rev = 6,
110
- .minor_ver = 0,
111
+ .minor_ver = 3,
112
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
113
.xdsdt_tbl_offset = &dsdt_tbl_offset,
114
};
115
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/arm/virt.c
118
+++ b/hw/arm/virt.c
119
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
120
qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
121
}
122
123
+/*
124
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
125
+ * but we don't want to advertise it to the guest in the dtb or ACPI
126
+ * table unless it's really going to do something.
127
+ */
128
+static bool ns_el2_virt_timer_present(void)
129
+{
130
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
131
+ CPUARMState *env = &cpu->env;
132
+
133
+ return arm_feature(env, ARM_FEATURE_AARCH64) &&
134
+ arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
135
+}
136
+
137
static void create_fdt(VirtMachineState *vms)
138
{
139
MachineState *ms = MACHINE(vms);
140
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
141
"arm,armv7-timer");
142
}
143
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
144
- qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
145
- GIC_FDT_IRQ_TYPE_PPI,
146
- INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
147
- GIC_FDT_IRQ_TYPE_PPI,
148
- INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
149
- GIC_FDT_IRQ_TYPE_PPI,
150
- INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
151
- GIC_FDT_IRQ_TYPE_PPI,
152
- INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
153
+ if (vms->ns_el2_virt_timer_irq) {
154
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
155
+ GIC_FDT_IRQ_TYPE_PPI,
156
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
157
+ GIC_FDT_IRQ_TYPE_PPI,
158
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
159
+ GIC_FDT_IRQ_TYPE_PPI,
160
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
161
+ GIC_FDT_IRQ_TYPE_PPI,
162
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
163
+ GIC_FDT_IRQ_TYPE_PPI,
164
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
165
+ } else {
166
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
167
+ GIC_FDT_IRQ_TYPE_PPI,
168
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
169
+ GIC_FDT_IRQ_TYPE_PPI,
170
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
171
+ GIC_FDT_IRQ_TYPE_PPI,
172
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
173
+ GIC_FDT_IRQ_TYPE_PPI,
174
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
175
+ }
176
}
177
178
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
179
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
180
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
181
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
182
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
183
+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
184
};
185
186
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
187
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
188
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
189
object_unref(cpuobj);
190
}
191
+
192
+ /* Now we've created the CPUs we can see if they have the hypvirt timer */
193
+ vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
194
+ !vmc->no_ns_el2_virt_timer_irq;
195
+
196
fdt_add_timer_nodes(vms);
197
fdt_add_cpu_nodes(vms);
198
199
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
200
201
static void virt_machine_8_2_options(MachineClass *mc)
202
{
203
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
204
+
205
virt_machine_9_0_options(mc);
206
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
207
+ /*
208
+ * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
209
+ * earlier machines. (Exposing it tickles a bug in older EDK2
210
+ * guest BIOS binaries.)
211
+ */
212
+ vmc->no_ns_el2_virt_timer_irq = true;
213
}
214
DEFINE_VIRT_MACHINE(8, 2)
215
216
--
217
2.34.1
diff view generated by jsdifflib
New patch
1
1
Update the virt golden reference files to say that the FACP is ACPI
2
v6.3, and the GTDT table is a revision 3 table with space for the
3
virtual EL2 timer.
4
5
Diffs from iasl:
6
7
@@ -XXX,XX +XXX,XX @@
8
/*
9
* Intel ACPI Component Architecture
10
* AML/ASL+ Disassembler version 20200925 (64-bit version)
11
* Copyright (c) 2000 - 2020 Intel Corporation
12
*
13
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
14
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
15
*
16
* ACPI Data Table [FACP]
17
*
18
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
19
*/
20
21
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
22
[004h 0004 4] Table Length : 00000114
23
[008h 0008 1] Revision : 06
24
-[009h 0009 1] Checksum : 15
25
+[009h 0009 1] Checksum : 12
26
[00Ah 0010 6] Oem ID : "BOCHS "
27
[010h 0016 8] Oem Table ID : "BXPC "
28
[018h 0024 4] Oem Revision : 00000001
29
[01Ch 0028 4] Asl Compiler ID : "BXPC"
30
[020h 0032 4] Asl Compiler Revision : 00000001
31
32
[024h 0036 4] FACS Address : 00000000
33
[028h 0040 4] DSDT Address : 00000000
34
[02Ch 0044 1] Model : 00
35
[02Dh 0045 1] PM Profile : 00 [Unspecified]
36
[02Eh 0046 2] SCI Interrupt : 0000
37
[030h 0048 4] SMI Command Port : 00000000
38
[034h 0052 1] ACPI Enable Value : 00
39
[035h 0053 1] ACPI Disable Value : 00
40
[036h 0054 1] S4BIOS Command : 00
41
[037h 0055 1] P-State Control : 00
42
@@ -XXX,XX +XXX,XX @@
43
Use APIC Physical Destination Mode (V4) : 0
44
Hardware Reduced (V5) : 1
45
Low Power S0 Idle (V5) : 0
46
47
[074h 0116 12] Reset Register : [Generic Address Structure]
48
[074h 0116 1] Space ID : 00 [SystemMemory]
49
[075h 0117 1] Bit Width : 00
50
[076h 0118 1] Bit Offset : 00
51
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
52
[078h 0120 8] Address : 0000000000000000
53
54
[080h 0128 1] Value to cause reset : 00
55
[081h 0129 2] ARM Flags (decoded below) : 0003
56
PSCI Compliant : 1
57
Must use HVC for PSCI : 1
58
59
-[083h 0131 1] FADT Minor Revision : 00
60
+[083h 0131 1] FADT Minor Revision : 03
61
[084h 0132 8] FACS Address : 0000000000000000
62
[08Ch 0140 8] DSDT Address : 0000000000000000
63
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
64
[094h 0148 1] Space ID : 00 [SystemMemory]
65
[095h 0149 1] Bit Width : 00
66
[096h 0150 1] Bit Offset : 00
67
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
68
[098h 0152 8] Address : 0000000000000000
69
70
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
71
[0A0h 0160 1] Space ID : 00 [SystemMemory]
72
[0A1h 0161 1] Bit Width : 00
73
[0A2h 0162 1] Bit Offset : 00
74
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
75
[0A4h 0164 8] Address : 0000000000000000
76
77
@@ -XXX,XX +XXX,XX @@
78
[0F5h 0245 1] Bit Width : 00
79
[0F6h 0246 1] Bit Offset : 00
80
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
81
[0F8h 0248 8] Address : 0000000000000000
82
83
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
84
[100h 0256 1] Space ID : 00 [SystemMemory]
85
[101h 0257 1] Bit Width : 00
86
[102h 0258 1] Bit Offset : 00
87
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
88
[104h 0260 8] Address : 0000000000000000
89
90
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
91
92
Raw Table Data: Length 276 (0x114)
93
94
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
95
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
96
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
97
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
98
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
99
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
100
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
101
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
102
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
103
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
104
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
105
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
106
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
107
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
108
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
109
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
110
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
111
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
112
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
113
0110: 00 00 00 00 // ....
114
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
* Intel ACPI Component Architecture
118
* AML/ASL+ Disassembler version 20200925 (64-bit version)
119
* Copyright (c) 2000 - 2020 Intel Corporation
120
*
121
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
122
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
123
*
124
* ACPI Data Table [GTDT]
125
*
126
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
127
*/
128
129
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
130
-[004h 0004 4] Table Length : 00000060
131
-[008h 0008 1] Revision : 02
132
-[009h 0009 1] Checksum : 9C
133
+[004h 0004 4] Table Length : 00000068
134
+[008h 0008 1] Revision : 03
135
+[009h 0009 1] Checksum : 93
136
[00Ah 0010 6] Oem ID : "BOCHS "
137
[010h 0016 8] Oem Table ID : "BXPC "
138
[018h 0024 4] Oem Revision : 00000001
139
[01Ch 0028 4] Asl Compiler ID : "BXPC"
140
[020h 0032 4] Asl Compiler Revision : 00000001
141
142
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
143
[02Ch 0044 4] Reserved : 00000000
144
145
[030h 0048 4] Secure EL1 Interrupt : 0000001D
146
[034h 0052 4] EL1 Flags (decoded below) : 00000000
147
Trigger Mode : 0
148
Polarity : 0
149
Always On : 0
150
151
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
152
@@ -XXX,XX +XXX,XX @@
153
154
[040h 0064 4] Virtual Timer Interrupt : 0000001B
155
[044h 0068 4] VT Flags (decoded below) : 00000000
156
Trigger Mode : 0
157
Polarity : 0
158
Always On : 0
159
160
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
161
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
162
Trigger Mode : 0
163
Polarity : 0
164
Always On : 0
165
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
166
167
[058h 0088 4] Platform Timer Count : 00000000
168
[05Ch 0092 4] Platform Timer Offset : 00000000
169
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
170
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
171
172
-Raw Table Data: Length 96 (0x60)
173
+Raw Table Data: Length 104 (0x68)
174
175
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
176
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
177
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
178
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
179
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
180
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
181
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
182
+ 0060: 00 00 00 00 00 00 00 00 // ........
183
184
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
186
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
187
---
188
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
189
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
190
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
191
3 files changed, 2 deletions(-)
192
193
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/qtest/bios-tables-test-allowed-diff.h
196
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
197
@@ -1,3 +1 @@
198
/* List of comma-separated changed AML files to ignore */
199
-"tests/data/acpi/virt/FACP",
200
-"tests/data/acpi/virt/GTDT",
201
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
202
index XXXXXXX..XXXXXXX 100644
203
GIT binary patch
204
delta 25
205
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
206
207
delta 28
208
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
209
210
diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
211
index XXXXXXX..XXXXXXX 100644
212
GIT binary patch
213
delta 25
214
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
215
216
delta 16
217
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
218
219
--
220
2.34.1
diff view generated by jsdifflib
New patch
1
The patchset adding the GMAC ethernet to this SoC crossed in the
2
mail with the patchset cleaning up the NIC handling. When we
3
create the GMAC modules we must call qemu_configure_nic_device()
4
so that the user has the opportunity to use the -nic commandline
5
option to create a network backend and connect it to the GMACs.
1
6
7
Add the missing call.
8
9
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
12
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
13
---
14
hw/arm/npcm7xx.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/npcm7xx.c
20
+++ b/hw/arm/npcm7xx.c
21
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
22
for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
23
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
24
25
+ qemu_configure_nic_device(DEVICE(sbd), false, NULL);
26
/*
27
* The device exists regardless of whether it's connected to a QEMU
28
* netdev backend. So always instantiate it even if there is no
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
1
Currently QEMU will warn if there is a NIC on the board that
2
is not connected to a backend. By default the '-nic user' will
3
get used for all NICs, but if you manually connect a specific
4
NIC to a specific backend, then the other NICs on the board
5
have no backend and will be warned about:
1
6
7
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
8
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
9
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
10
11
So suppress those warnings by manually connecting every NIC
12
on the board to some backend.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
18
---
19
tests/qtest/npcm7xx_emc-test.c | 5 ++++-
20
1 file changed, 4 insertions(+), 1 deletion(-)
21
22
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/tests/qtest/npcm7xx_emc-test.c
25
+++ b/tests/qtest/npcm7xx_emc-test.c
26
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
27
* KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
28
* in the 'model' field to specify the device to match.
29
*/
30
- g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
31
+ g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
32
+ "-nic user,model=npcm7xx-emc "
33
+ "-nic user,model=npcm-gmac "
34
+ "-nic user,model=npcm-gmac",
35
test_sockets[1], module_num);
36
37
g_test_queue_destroy(packet_test_clear, test_sockets);
38
--
39
2.34.1
diff view generated by jsdifflib
1
The excnames[] array is defined in internals.h because we used
1
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
2
to use it from two different source files for handling logging
2
CPU, and in fact if you try to do it we will assert:
3
of AArch32 and AArch64 exception entry. Refactoring means that
4
it's now used only in arm_log_exception() in helper.c, so move
5
the array into that function.
6
3
7
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
#6 0x00007ffff4b95e96 in __GI___assert_fail
5
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
6
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
7
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
8
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
9
10
We might call pmu_counter_enabled() on an M-profile CPU (for example
11
from the migration pre/post hooks in machine.c); this should always
12
return false because these CPUs don't set ARM_FEATURE_PMU.
13
14
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
15
have done the early return for "PMU not present".
16
17
This fixes an assertion failure if you try to do a loadvm or
18
savevm for an M-profile board.
19
20
Cc: qemu-stable@nongnu.org
21
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 1491821097-5647-1-git-send-email-peter.maydell@linaro.org
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
11
---
26
---
12
target/arm/cpu.h | 2 +-
27
target/arm/helper.c | 12 ++++++++++--
13
target/arm/internals.h | 23 -----------------------
28
1 file changed, 10 insertions(+), 2 deletions(-)
14
target/arm/helper.c | 19 +++++++++++++++++++
15
3 files changed, 20 insertions(+), 24 deletions(-)
16
29
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@
22
#define EXCP_SEMIHOST 16 /* semihosting call */
23
#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
24
#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
25
-/* NB: new EXCP_ defines should be added to the excnames[] array too */
26
+/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
27
28
#define ARMV7M_EXCP_RESET 1
29
#define ARMV7M_EXCP_NMI 2
30
diff --git a/target/arm/internals.h b/target/arm/internals.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/internals.h
33
+++ b/target/arm/internals.h
34
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
35
|| excp == EXCP_SEMIHOST;
36
}
37
38
-/* Exception names for debug logging; note that not all of these
39
- * precisely correspond to architectural exceptions.
40
- */
41
-static const char * const excnames[] = {
42
- [EXCP_UDEF] = "Undefined Instruction",
43
- [EXCP_SWI] = "SVC",
44
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
45
- [EXCP_DATA_ABORT] = "Data Abort",
46
- [EXCP_IRQ] = "IRQ",
47
- [EXCP_FIQ] = "FIQ",
48
- [EXCP_BKPT] = "Breakpoint",
49
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
50
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
51
- [EXCP_HVC] = "Hypervisor Call",
52
- [EXCP_HYP_TRAP] = "Hypervisor Trap",
53
- [EXCP_SMC] = "Secure Monitor Call",
54
- [EXCP_VIRQ] = "Virtual IRQ",
55
- [EXCP_VFIQ] = "Virtual FIQ",
56
- [EXCP_SEMIHOST] = "Semihosting call",
57
- [EXCP_NOCP] = "v7M NOCP UsageFault",
58
- [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
59
-};
60
-
61
/* Scale factor for generic timers, ie number of ns per tick.
62
* This gives a 62.5MHz timer.
63
*/
64
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
65
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/helper.c
32
--- a/target/arm/helper.c
67
+++ b/target/arm/helper.c
33
+++ b/target/arm/helper.c
68
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
34
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
69
{
35
bool enabled, prohibited = false, filtered;
70
if (qemu_loglevel_mask(CPU_LOG_INT)) {
36
bool secure = arm_is_secure(env);
71
const char *exc = NULL;
37
int el = arm_current_el(env);
72
+ static const char * const excnames[] = {
38
- uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
73
+ [EXCP_UDEF] = "Undefined Instruction",
39
- uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
74
+ [EXCP_SWI] = "SVC",
40
+ uint64_t mdcr_el2;
75
+ [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
41
+ uint8_t hpmn;
76
+ [EXCP_DATA_ABORT] = "Data Abort",
42
77
+ [EXCP_IRQ] = "IRQ",
43
+ /*
78
+ [EXCP_FIQ] = "FIQ",
44
+ * We might be called for M-profile cores where MDCR_EL2 doesn't
79
+ [EXCP_BKPT] = "Breakpoint",
45
+ * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
80
+ [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
46
+ * must be before we read that value.
81
+ [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
47
+ */
82
+ [EXCP_HVC] = "Hypervisor Call",
48
if (!arm_feature(env, ARM_FEATURE_PMU)) {
83
+ [EXCP_HYP_TRAP] = "Hypervisor Trap",
49
return false;
84
+ [EXCP_SMC] = "Secure Monitor Call",
50
}
85
+ [EXCP_VIRQ] = "Virtual IRQ",
51
86
+ [EXCP_VFIQ] = "Virtual FIQ",
52
+ mdcr_el2 = arm_mdcr_el2_eff(env);
87
+ [EXCP_SEMIHOST] = "Semihosting call",
53
+ hpmn = mdcr_el2 & MDCR_HPMN;
88
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
54
+
89
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
55
if (!arm_feature(env, ARM_FEATURE_EL2) ||
90
+ };
56
(counter < hpmn || counter == 31)) {
91
57
e = env->cp15.c9_pmcr & PMCRE;
92
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
93
exc = excnames[idx];
94
--
58
--
95
2.7.4
59
2.34.1
96
60
97
61
diff view generated by jsdifflib
1
Now that we've rewritten M-profile exception return so that the magic
1
From: Nabih Estefan <nabihestefan@google.com>
2
PC values are not visible to other parts of QEMU, we can delete the
3
special casing of them elsewhere.
4
2
3
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
4
of 8xx. Also fix comments referencing this and values expecting 8xx.
5
6
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
7
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: commit message tweaks]
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Message-id: 1491844419-12485-10-git-send-email-peter.maydell@linaro.org
9
---
13
---
10
target/arm/cpu.c | 43 ++-----------------------------------------
14
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
11
target/arm/translate.c | 8 --------
15
tests/qtest/meson.build | 3 +-
12
2 files changed, 2 insertions(+), 49 deletions(-)
16
2 files changed, 4 insertions(+), 83 deletions(-)
13
17
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
20
--- a/tests/qtest/npcm_gmac-test.c
17
+++ b/target/arm/cpu.c
21
+++ b/tests/qtest/npcm_gmac-test.c
18
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
22
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
23
const GMACModule *module;
24
} TestData;
25
26
-/* Values extracted from hw/arm/npcm8xx.c */
27
+/* Values extracted from hw/arm/npcm7xx.c */
28
static const GMACModule gmac_module_list[] = {
29
{
30
.irq = 14,
31
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
32
.irq = 15,
33
.base_addr = 0xf0804000
34
},
35
- {
36
- .irq = 16,
37
- .base_addr = 0xf0806000
38
- },
39
- {
40
- .irq = 17,
41
- .base_addr = 0xf0808000
42
- }
43
};
44
45
/* Returns the index of the GMAC module. */
46
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
47
return qtest_readl(qts, mod->base_addr + regno);
19
}
48
}
20
49
21
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
50
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
22
-static void arm_v7m_unassigned_access(CPUState *cpu, hwaddr addr,
51
- NPCMRegister regno)
23
- bool is_write, bool is_exec, int opaque,
24
- unsigned size)
25
-{
52
-{
26
- ARMCPU *arm = ARM_CPU(cpu);
53
- uint32_t write_value = (regno & 0x3ffe00) >> 9;
27
- CPUARMState *env = &arm->env;
54
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
55
- uint32_t read_offset = regno & 0x1ff;
56
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
57
-}
28
-
58
-
29
- /* ARMv7-M interrupt return works by loading a magic value into the PC.
59
/* Check that GMAC registers are reset to default value */
30
- * On real hardware the load causes the return to occur. The qemu
60
static void test_init(gconstpointer test_data)
31
- * implementation performs the jump normally, then does the exception
61
{
32
- * return by throwing a special exception when when the CPU tries to
62
const TestData *td = test_data;
33
- * execute code at the magic address.
63
const GMACModule *mod = td->module;
34
- */
64
- QTestState *qts = qtest_init("-machine npcm845-evb");
35
- if (env->v7m.exception != 0 && addr >= 0xfffffff0 && is_exec) {
65
+ QTestState *qts = qtest_init("-machine npcm750-evb");
36
- cpu->exception_index = EXCP_EXCEPTION_EXIT;
66
37
- cpu_loop_exit(cpu);
67
#define CHECK_REG32(regno, value) \
68
do { \
69
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
70
} while (0)
71
72
-#define CHECK_REG_PCS(regno, value) \
73
- do { \
74
- g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
75
- } while (0)
76
-
77
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
78
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
79
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
80
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
81
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
82
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
83
84
- /* TODO Add registers PCS */
85
- if (mod->base_addr == 0xf0802000) {
86
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
87
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
88
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
89
-
90
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
91
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
92
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
93
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
94
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
95
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
96
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
97
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
98
-
99
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
100
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
101
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
102
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
103
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
104
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
105
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
106
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
107
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
108
-
109
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
110
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
111
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
112
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
113
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
114
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
115
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
116
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
117
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
118
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
119
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
120
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
121
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
122
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
123
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
124
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
125
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
126
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
127
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
128
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
129
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
130
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
131
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
132
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
133
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
134
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
135
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
136
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
137
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
138
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
139
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
38
- }
140
- }
39
-
141
-
40
- /* In real hardware an attempt to access parts of the address space
142
qtest_quit(qts);
41
- * with nothing there will usually cause an external abort.
42
- * However our QEMU board models are often missing device models where
43
- * the guest can boot anyway with the default read-as-zero/writes-ignored
44
- * behaviour that you get without a QEMU unassigned_access hook.
45
- * So just return here to retain that default behaviour.
46
- */
47
-}
48
-
49
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
50
{
51
CPUClass *cc = CPU_GET_CLASS(cs);
52
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
53
CPUARMState *env = &cpu->env;
54
bool ret = false;
55
56
- /* ARMv7-M interrupt return works by loading a magic value
57
- * into the PC. On real hardware the load causes the
58
- * return to occur. The qemu implementation performs the
59
- * jump normally, then does the exception return when the
60
- * CPU tries to execute code at the magic address.
61
- * This will cause the magic PC value to be pushed to
62
- * the stack if an interrupt occurred at the wrong time.
63
- * We avoid this by disabling interrupts when
64
- * pc contains a magic address.
65
- *
66
- * ARMv7-M interrupt masking works differently than -A or -R.
67
+ /* ARMv7-M interrupt masking works differently than -A or -R.
68
* There is no FIQ/IRQ distinction. Instead of I and F bits
69
* masking FIQ and IRQ interrupts, an exception is taken only
70
* if it is higher priority than the current execution priority
71
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
72
* currently active exception).
73
*/
74
if (interrupt_request & CPU_INTERRUPT_HARD
75
- && (armv7m_nvic_can_take_pending_exception(env->nvic))
76
- && (env->regs[15] < 0xfffffff0)) {
77
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
78
cs->exception_index = EXCP_IRQ;
79
cc->do_interrupt(cs);
80
ret = true;
81
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
82
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
83
#endif
84
85
- cc->do_unassigned_access = arm_v7m_unassigned_access;
86
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
87
}
143
}
88
144
89
diff --git a/target/arm/translate.c b/target/arm/translate.c
145
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
90
index XXXXXXX..XXXXXXX 100644
146
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/translate.c
147
--- a/tests/qtest/meson.build
92
+++ b/target/arm/translate.c
148
+++ b/tests/qtest/meson.build
93
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
149
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
94
dc->is_jmp = DISAS_EXC;
150
'npcm7xx_sdhci-test',
95
break;
151
'npcm7xx_smbus-test',
96
}
152
'npcm7xx_timer-test',
97
-#else
153
- 'npcm7xx_watchdog_timer-test'] + \
98
- if (arm_dc_feature(dc, ARM_FEATURE_M)) {
154
+ 'npcm7xx_watchdog_timer-test',
99
- /* Branches to the magic exception-return addresses should
155
+ 'npcm_gmac-test'] + \
100
- * already have been caught via the arm_v7m_unassigned_access hook,
156
(slirp.found() ? ['npcm7xx_emc-test'] : [])
101
- * and never get here.
157
qtests_aspeed = \
102
- */
158
['aspeed_hace-test',
103
- assert(dc->pc < 0xfffffff0);
104
- }
105
#endif
106
107
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
108
--
159
--
109
2.7.4
160
2.34.1
110
111
diff view generated by jsdifflib
New patch
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
An access fault is raised when the Access Flag is not set in the
4
looked-up PTE and the AFFD field is not set in the corresponding context
5
descriptor. This was already implemented for stage 2. Implement it for
6
stage 1 as well.
7
8
Signed-off-by: Luc Michel <luc.michel@amd.com>
9
Reviewed-by: Mostafa Saleh <smostafa@google.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Tested-by: Mostafa Saleh <smostafa@google.com>
12
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
13
[PMM: tweaked comment text]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/smmuv3-internal.h | 1 +
17
include/hw/arm/smmu-common.h | 1 +
18
hw/arm/smmu-common.c | 11 +++++++++++
19
hw/arm/smmuv3.c | 1 +
20
4 files changed, 14 insertions(+)
21
22
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/smmuv3-internal.h
25
+++ b/hw/arm/smmuv3-internal.h
26
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
27
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
28
#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
29
#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
30
+#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
31
#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
32
#define CD_HD(x) extract32((x)->word[1], 10 , 1)
33
#define CD_HA(x) extract32((x)->word[1], 11 , 1)
34
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/arm/smmu-common.h
37
+++ b/include/hw/arm/smmu-common.h
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
39
bool disabled; /* smmu is disabled */
40
bool bypassed; /* translation is bypassed */
41
bool aborted; /* translation is aborted */
42
+ bool affd; /* AF fault disable */
43
uint32_t iotlb_hits; /* counts IOTLB hits */
44
uint32_t iotlb_misses; /* counts IOTLB misses*/
45
/* Used by stage-1 only. */
46
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/smmu-common.c
49
+++ b/hw/arm/smmu-common.c
50
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
51
pte_addr, pte, iova, gpa,
52
block_size >> 20);
53
}
54
+
55
+ /*
56
+ * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
57
+ * are 0 we take an Access flag fault. (5.4. Context Descriptor)
58
+ * An Access flag fault takes priority over a Permission fault.
59
+ */
60
+ if (!PTE_AF(pte) && !cfg->affd) {
61
+ info->type = SMMU_PTW_ERR_ACCESS;
62
+ goto error;
63
+ }
64
+
65
ap = PTE_AP(pte);
66
if (is_permission_fault(ap, perm)) {
67
info->type = SMMU_PTW_ERR_PERMISSION;
68
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/smmuv3.c
71
+++ b/hw/arm/smmuv3.c
72
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
73
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
74
cfg->tbi = CD_TBI(cd);
75
cfg->asid = CD_ASID(cd);
76
+ cfg->affd = CD_AFFD(cd);
77
78
trace_smmuv3_decode_cd(cfg->oas);
79
80
--
81
2.34.1
diff view generated by jsdifflib
1
Current recommended style is to log a guest error on bad register
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
accesses, not kill the whole system with hw_error(). Change the
3
hw_error() calls to log as LOG_GUEST_ERROR or LOG_UNIMP or use
4
g_assert_not_reached() as appropriate.
5
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20240213155214.13619-2-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 1491486314-25823-1-git-send-email-peter.maydell@linaro.org
9
---
7
---
10
hw/arm/stellaris.c | 60 +++++++++++++++++++++++++++++++++---------------------
8
hw/arm/stellaris.c | 6 ++++--
11
1 file changed, 37 insertions(+), 23 deletions(-)
9
1 file changed, 4 insertions(+), 2 deletions(-)
12
10
13
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/stellaris.c
13
--- a/hw/arm/stellaris.c
16
+++ b/hw/arm/stellaris.c
14
+++ b/hw/arm/stellaris.c
17
@@ -XXX,XX +XXX,XX @@ static void gptm_reload(gptm_state *s, int n, int reset)
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
18
} else if (s->mode[n] == 0xa) {
19
/* PWM mode. Not implemented. */
20
} else {
21
- hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
22
+ qemu_log_mask(LOG_UNIMP,
23
+ "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
24
+ s->mode[n]);
25
+ return;
26
}
27
s->tick[n] = tick;
28
timer_mod(s->timer[n], tick);
29
@@ -XXX,XX +XXX,XX @@ static void gptm_tick(void *opaque)
30
} else if (s->mode[n] == 0xa) {
31
/* PWM mode. Not implemented. */
32
} else {
33
- hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
34
+ qemu_log_mask(LOG_UNIMP,
35
+ "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
36
+ s->mode[n]);
37
}
38
gptm_update_irq(s);
39
}
40
@@ -XXX,XX +XXX,XX @@ static void gptm_write(void *opaque, hwaddr offset,
41
s->match_prescale[0] = value;
42
break;
43
default:
44
- hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
45
+ qemu_log_mask(LOG_GUEST_ERROR,
46
+ "GPTM: read at bad offset 0x%x\n", (int)offset);
47
}
48
gptm_update_irq(s);
49
}
50
@@ -XXX,XX +XXX,XX @@ static int ssys_board_class(const ssys_state *s)
51
}
52
/* for unknown classes, fall through */
53
default:
54
- hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
55
+ /* This can only happen if the hardwired constant did0 value
56
+ * in this board's stellaris_board_info struct is wrong.
57
+ */
58
+ g_assert_not_reached();
59
}
16
}
60
}
17
}
61
18
62
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
19
-static void stellaris_adc_reset(StellarisADCState *s)
63
case DID0_CLASS_SANDSTORM:
20
+static void stellaris_adc_reset_hold(Object *obj)
64
return pllcfg_sandstorm[xtal];
21
{
65
default:
22
+ StellarisADCState *s = STELLARIS_ADC(obj);
66
- hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
23
int n;
67
- return 0;
24
68
+ g_assert_not_reached();
25
for (n = 0; n < 4; n++) {
69
}
26
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
70
}
27
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
71
case 0x070: /* RCC2 */
28
"adc", 0x1000);
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
29
sysbus_init_mmio(sbd, &s->iomem);
73
case 0x1e4: /* USER1 */
30
- stellaris_adc_reset(s);
74
return s->user1;
31
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
75
default:
76
- hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
77
+ qemu_log_mask(LOG_GUEST_ERROR,
78
+ "SSYS: read at bad offset 0x%x\n", (int)offset);
79
return 0;
80
}
81
}
32
}
82
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
33
83
s->ldoarst = value;
34
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
84
break;
35
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
85
default:
36
{
86
- hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
37
DeviceClass *dc = DEVICE_CLASS(klass);
87
+ qemu_log_mask(LOG_GUEST_ERROR,
38
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
88
+ "SSYS: write at bad offset 0x%x\n", (int)offset);
39
89
}
40
+ rc->phases.hold = stellaris_adc_reset_hold;
90
ssys_update(s);
41
dc->vmsd = &vmstate_stellaris_adc;
91
}
42
}
92
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
43
93
case 0x20: /* MCR */
94
return s->mcr;
95
default:
96
- hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
97
+ qemu_log_mask(LOG_GUEST_ERROR,
98
+ "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
99
return 0;
100
}
101
}
102
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
103
s->mris &= ~value;
104
break;
105
case 0x20: /* MCR */
106
- if (value & 1)
107
- hw_error(
108
- "stellaris_i2c_write: Loopback not implemented\n");
109
- if (value & 0x20)
110
- hw_error(
111
- "stellaris_i2c_write: Slave mode not implemented\n");
112
+ if (value & 1) {
113
+ qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
114
+ }
115
+ if (value & 0x20) {
116
+ qemu_log_mask(LOG_UNIMP,
117
+ "stellaris_i2c: Slave mode not implemented");
118
+ }
119
s->mcr = value & 0x31;
120
break;
121
default:
122
- hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
123
- (int)offset);
124
+ qemu_log_mask(LOG_GUEST_ERROR,
125
+ "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
126
}
127
stellaris_i2c_update(s);
128
}
129
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
130
case 0x30: /* SAC */
131
return s->sac;
132
default:
133
- hw_error("strllaris_adc_read: Bad offset 0x%x\n",
134
- (int)offset);
135
+ qemu_log_mask(LOG_GUEST_ERROR,
136
+ "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
137
return 0;
138
}
139
}
140
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
141
return;
142
case 0x04: /* SSCTL */
143
if (value != 6) {
144
- hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
145
- value);
146
+ qemu_log_mask(LOG_UNIMP,
147
+ "ADC: Unimplemented sequence %" PRIx64 "\n",
148
+ value);
149
}
150
s->ssctl[n] = value;
151
return;
152
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
153
s->sspri = value;
154
break;
155
case 0x28: /* PSSI */
156
- hw_error("Not implemented: ADC sample initiate\n");
157
+ qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
158
break;
159
case 0x30: /* SAC */
160
s->sac = value;
161
break;
162
default:
163
- hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
164
+ qemu_log_mask(LOG_GUEST_ERROR,
165
+ "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
166
}
167
stellaris_adc_update(s);
168
}
169
--
44
--
170
2.7.4
45
2.34.1
171
46
172
47
diff view generated by jsdifflib
1
From: Suramya Shah <shah.suramya@gmail.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Signed-off-by: Suramya Shah <shah.suramya@gmail.com>
3
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
4
Message-id: 20170415180316.2694-1-shah.suramya@gmail.com
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20240213155214.13619-3-philmd@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
---
8
hw/arm/pxa2xx.c | 14 ++++++--------
9
hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
9
1 file changed, 6 insertions(+), 8 deletions(-)
10
1 file changed, 22 insertions(+), 4 deletions(-)
10
11
11
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/pxa2xx.c
14
--- a/hw/arm/stellaris.c
14
+++ b/hw/arm/pxa2xx.c
15
+++ b/hw/arm/stellaris.c
15
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_reset(DeviceState *d)
16
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
16
s->rx_start = s->rx_level = 0;
17
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
17
}
18
}
18
19
19
-static int pxa2xx_ssp_init(SysBusDevice *sbd)
20
-/* I2C controller. */
20
+static void pxa2xx_ssp_init(Object *obj)
21
+/*
22
+ * I2C controller.
23
+ * ??? For now we only implement the master interface.
24
+ */
25
26
#define TYPE_STELLARIS_I2C "stellaris-i2c"
27
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
29
stellaris_i2c_update(s);
30
}
31
32
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
33
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
21
{
34
{
22
- DeviceState *dev = DEVICE(sbd);
35
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
23
- PXA2xxSSPState *s = PXA2XX_SSP(dev);
36
+
24
-
37
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
25
+ DeviceState *dev = DEVICE(obj);
38
i2c_end_transfer(s->bus);
26
+ PXA2xxSSPState *s = PXA2XX_SSP(obj);
39
+}
27
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
40
+
28
sysbus_init_irq(sbd, &s->irq);
41
+static void stellaris_i2c_reset_hold(Object *obj)
29
42
+{
30
- memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
43
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
31
+ memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
44
32
"pxa2xx-ssp", 0x1000);
45
s->msa = 0;
46
s->mcs = 0;
47
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
48
s->mimr = 0;
49
s->mris = 0;
50
s->mcr = 0;
51
+}
52
+
53
+static void stellaris_i2c_reset_exit(Object *obj)
54
+{
55
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
56
+
57
stellaris_i2c_update(s);
58
}
59
60
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
61
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
62
"i2c", 0x1000);
33
sysbus_init_mmio(sbd, &s->iomem);
63
sysbus_init_mmio(sbd, &s->iomem);
34
64
- /* ??? For now we only implement the master interface. */
35
s->bus = ssi_create_bus(dev, "ssi");
65
- stellaris_i2c_reset(s);
36
- return 0;
37
}
66
}
38
67
39
/* Real-Time Clock */
68
/* Analogue to Digital Converter. This is only partially implemented,
40
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
69
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
41
70
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
42
static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
43
{
71
{
44
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
45
DeviceClass *dc = DEVICE_CLASS(klass);
72
DeviceClass *dc = DEVICE_CLASS(klass);
46
73
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
47
- sdc->init = pxa2xx_ssp_init;
74
48
dc->reset = pxa2xx_ssp_reset;
75
+ rc->phases.enter = stellaris_i2c_reset_enter;
49
dc->vmsd = &vmstate_pxa2xx_ssp;
76
+ rc->phases.hold = stellaris_i2c_reset_hold;
77
+ rc->phases.exit = stellaris_i2c_reset_exit;
78
dc->vmsd = &vmstate_stellaris_i2c;
50
}
79
}
51
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pxa2xx_ssp_info = {
52
.name = TYPE_PXA2XX_SSP,
53
.parent = TYPE_SYS_BUS_DEVICE,
54
.instance_size = sizeof(PXA2xxSSPState),
55
+ .instance_init = pxa2xx_ssp_init,
56
.class_init = pxa2xx_ssp_class_init,
57
};
58
80
59
--
81
--
60
2.7.4
82
2.34.1
61
83
62
84
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Expose the Cadence GEM revision as a property.
3
QDev objects created with qdev_new() need to manually add
4
their parent relationship with object_property_add_child().
4
5
5
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
6
This commit plug the devices which aren't part of the SoC;
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
they will be plugged into a SoC container in the next one.
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 541324373cf87b50f8be0439a0cb89f5028b016f.1491947224.git.alistair.francis@xilinx.com
11
Message-id: 20240213155214.13619-4-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
include/hw/net/cadence_gem.h | 1 +
14
hw/arm/stellaris.c | 4 ++++
12
hw/net/cadence_gem.c | 6 +++++-
15
1 file changed, 4 insertions(+)
13
2 files changed, 6 insertions(+), 1 deletion(-)
14
16
15
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
17
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/net/cadence_gem.h
19
--- a/hw/arm/stellaris.c
18
+++ b/include/hw/net/cadence_gem.h
20
+++ b/hw/arm/stellaris.c
19
@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
21
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
20
uint8_t num_priority_queues;
22
&error_fatal);
21
uint8_t num_type1_screeners;
23
22
uint8_t num_type2_screeners;
24
ssddev = qdev_new("ssd0323");
23
+ uint32_t revision;
25
+ object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
24
26
qdev_prop_set_uint8(ssddev, "cs", 1);
25
/* GEM registers backing store */
27
qdev_realize_and_unref(ssddev, bus, &error_fatal);
26
uint32_t regs[CADENCE_GEM_MAXREG];
28
27
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
29
gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
28
index XXXXXXX..XXXXXXX 100644
30
+ object_property_add_child(OBJECT(ms), "splitter",
29
--- a/hw/net/cadence_gem.c
31
+ OBJECT(gpio_d_splitter));
30
+++ b/hw/net/cadence_gem.c
32
qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
31
@@ -XXX,XX +XXX,XX @@
33
qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
32
#define DESC_1_RX_SOF 0x00004000
34
qdev_connect_gpio_out(
33
#define DESC_1_RX_EOF 0x00008000
35
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
34
36
DeviceState *gpad;
35
+#define GEM_MODID_VALUE 0x00020118
37
36
+
38
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
37
static inline unsigned tx_desc_get_buffer(unsigned *desc)
39
+ object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
38
{
40
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
39
return desc[0];
41
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
40
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
42
}
41
s->regs[GEM_TXPAUSE] = 0x0000ffff;
42
s->regs[GEM_TXPARTIALSF] = 0x000003ff;
43
s->regs[GEM_RXPARTIALSF] = 0x000003ff;
44
- s->regs[GEM_MODID] = 0x00020118;
45
+ s->regs[GEM_MODID] = s->revision;
46
s->regs[GEM_DESCONF] = 0x02500111;
47
s->regs[GEM_DESCONF2] = 0x2ab13fff;
48
s->regs[GEM_DESCONF5] = 0x002f2145;
49
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_cadence_gem = {
50
51
static Property gem_properties[] = {
52
DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
53
+ DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
54
+ GEM_MODID_VALUE),
55
DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
56
num_priority_queues, 1),
57
DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
58
--
43
--
59
2.7.4
44
2.34.1
60
45
61
46
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Read the correct descriptor instead of hardcoding the first (q=0).
3
QDev objects created with qdev_new() need to manually add
4
their parent relationship with object_property_add_child().
4
5
5
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
6
Since we don't model the SoC, just use a QOM container.
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 988b183dcf951856d8b3379f7e911ec95233bbf4.1491947224.git.alistair.francis@xilinx.com
10
Message-id: 20240213155214.13619-5-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
hw/net/cadence_gem.c | 4 ++--
13
hw/arm/stellaris.c | 11 ++++++++++-
12
1 file changed, 2 insertions(+), 2 deletions(-)
14
1 file changed, 10 insertions(+), 1 deletion(-)
13
15
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
16
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
18
--- a/hw/arm/stellaris.c
17
+++ b/hw/net/cadence_gem.c
19
+++ b/hw/arm/stellaris.c
18
@@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
20
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
19
{
21
* 400fe000 system control
20
DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
22
*/
21
/* read current descriptor */
23
22
- cpu_physical_memory_read(s->rx_desc_addr[0],
24
+ Object *soc_container;
23
- (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0]));
25
DeviceState *gpio_dev[7], *nvic;
24
+ cpu_physical_memory_read(s->rx_desc_addr[q],
26
qemu_irq gpio_in[7][8];
25
+ (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q]));
27
qemu_irq gpio_out[7][8];
26
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
27
/* Descriptor owned by software ? */
29
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
28
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
30
sram_size = ((board->dc0 >> 18) + 1) * 1024;
31
32
+ soc_container = object_new("container");
33
+ object_property_add_child(OBJECT(ms), "soc", soc_container);
34
+
35
/* Flash programming is done via the SCU, so pretend it is ROM. */
36
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
37
&error_fatal);
38
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
39
* need its sysclk output.
40
*/
41
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
42
+ object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
43
44
/*
45
* Most devices come preprogrammed with a MAC address in the user data.
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
47
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
48
49
nvic = qdev_new(TYPE_ARMV7M);
50
+ object_property_add_child(soc_container, "v7m", OBJECT(nvic));
51
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
52
qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
53
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
54
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
55
56
dev = qdev_new(TYPE_STELLARIS_GPTM);
57
sbd = SYS_BUS_DEVICE(dev);
58
+ object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
59
qdev_connect_clock_in(dev, "clk",
60
qdev_get_clock_out(ssys_dev, "SYSCLK"));
61
sysbus_realize_and_unref(sbd, &error_fatal);
62
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
63
64
if (board->dc1 & (1 << 3)) { /* watchdog present */
65
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
66
-
67
+ object_property_add_child(soc_container, "wdg", OBJECT(dev));
68
qdev_connect_clock_in(dev, "WDOGCLK",
69
qdev_get_clock_out(ssys_dev, "SYSCLK"));
70
71
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
72
SysBusDevice *sbd;
73
74
dev = qdev_new("pl011_luminary");
75
+ object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
76
sbd = SYS_BUS_DEVICE(dev);
77
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
78
sysbus_realize_and_unref(sbd, &error_fatal);
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
DeviceState *enet;
81
82
enet = qdev_new("stellaris_enet");
83
+ object_property_add_child(soc_container, "enet", OBJECT(enet));
84
if (nd) {
85
qdev_set_nic_properties(enet, nd);
86
} else {
29
--
87
--
30
2.7.4
88
2.34.1
31
89
32
90
diff view generated by jsdifflib
New patch
1
We support two different encodings for the AArch32 IMPDEF
2
CBAR register -- older cores like the Cortex A9, A7, A15
3
have this at 4, c15, c0, 0; newer cores like the
4
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
1
5
6
When we implemented this we picked which encoding to
7
use based on whether the CPU set ARM_FEATURE_AARCH64.
8
However this isn't right for three cases:
9
* the qemu-system-arm 'max' CPU, which is supposed to be
10
a variant on a Cortex-A57; it ought to use the same
11
encoding the A57 does and which the AArch64 'max'
12
exposes to AArch32 guest code
13
* the Cortex-R52, which is AArch32-only but has the CBAR
14
at the newer encoding (and where we incorrectly are
15
not yet setting ARM_FEATURE_CBAR_RO anyway)
16
* any possible future support for other v8 AArch32
17
only CPUs, or for supporting "boot the CPU into
18
AArch32 mode" on our existing cores like the A57 etc
19
20
Make the decision of the encoding be based on whether
21
the CPU implements the ARM_FEATURE_V8 flag instead.
22
23
This changes the behaviour only for the qemu-system-arm
24
'-cpu max'. We don't expect anybody to be relying on the
25
old behaviour because:
26
* it's not what the real hardware Cortex-A57 does
27
(and that's what our ID register claims we are)
28
* we don't implement the memory-mapped GICv3 support
29
which is the only thing that exists at the peripheral
30
base address pointed to by the register
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
35
---
36
target/arm/helper.c | 2 +-
37
1 file changed, 1 insertion(+), 1 deletion(-)
38
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
44
* AArch64 cores we might need to add a specific feature flag
45
* to indicate cores with "flavour 2" CBAR.
46
*/
47
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
48
+ if (arm_feature(env, ARM_FEATURE_V8)) {
49
/* 32 bit view is [31:18] 0...0 [43:32]. */
50
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
51
| extract64(cpu->reset_cbar, 32, 12);
52
--
53
2.34.1
diff view generated by jsdifflib
New patch
1
The Cortex-R52 implements the Configuration Base Address Register
2
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
3
type, so that our implementation provides the register and the
4
associated qdev property.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
18
set_feature(&cpu->env, ARM_FEATURE_PMSA);
19
set_feature(&cpu->env, ARM_FEATURE_NEON);
20
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
21
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
22
cpu->midr = 0x411fd133; /* r1p3 */
23
cpu->revidr = 0x00000000;
24
cpu->reset_fpsid = 0x41034023;
25
--
26
2.34.1
diff view generated by jsdifflib
1
We currently have two places that do:
1
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
2
if (dc->ss_active) {
2
also by enabling the AUXCR feature which defines the ACTLR
3
gen_step_complete_exception(dc);
3
and HACTLR registers. As is our usual practice, we make these
4
} else {
4
simple reads-as-zero stubs for now.
5
gen_exception_internal(EXCP_DEBUG);
6
}
7
8
Factor this out into its own function, as we're about to add
9
a third place that needs the same logic.
10
5
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
14
Message-id: 1491844419-12485-4-git-send-email-peter.maydell@linaro.org
15
---
9
---
16
target/arm/translate.c | 28 ++++++++++++++++------------
10
target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
17
1 file changed, 16 insertions(+), 12 deletions(-)
11
1 file changed, 108 insertions(+)
18
12
19
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate.c
15
--- a/target/arm/tcg/cpu32.c
22
+++ b/target/arm/translate.c
16
+++ b/target/arm/tcg/cpu32.c
23
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
24
s->is_jmp = DISAS_EXC;
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
25
}
19
}
26
20
27
+static void gen_singlestep_exception(DisasContext *s)
21
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
28
+{
22
+ { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
29
+ /* Generate the right kind of exception for singlestep, which is
23
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
30
+ * either the architectural singlestep or EXCP_DEBUG for QEMU's
24
+ { .name = "IMP_ATCMREGIONR",
31
+ * gdb singlestepping.
25
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
32
+ */
26
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ if (s->ss_active) {
27
+ { .name = "IMP_BTCMREGIONR",
34
+ gen_step_complete_exception(s);
28
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
35
+ } else {
29
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ gen_exception_internal(EXCP_DEBUG);
30
+ { .name = "IMP_CTCMREGIONR",
37
+ }
31
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
38
+}
32
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ { .name = "IMP_CSCTLR",
34
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "IMP_BPCTLR",
37
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
38
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
+ { .name = "IMP_MEMPROTCLR",
40
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
41
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
+ { .name = "IMP_SLAVEPCTLR",
43
+ .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
44
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
+ { .name = "IMP_PERIPHREGIONR",
46
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
47
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
48
+ { .name = "IMP_FLASHIFREGIONR",
49
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "IMP_BUILDOPTR",
52
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
53
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "IMP_PINOPTR",
55
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
56
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ { .name = "IMP_QOSR",
58
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
59
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60
+ { .name = "IMP_BUSTIMEOUTR",
61
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
62
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
+ { .name = "IMP_INTMONR",
64
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
65
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66
+ { .name = "IMP_ICERR0",
67
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
68
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69
+ { .name = "IMP_ICERR1",
70
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
71
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
+ { .name = "IMP_DCERR0",
73
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
74
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
+ { .name = "IMP_DCERR1",
76
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
77
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78
+ { .name = "IMP_TCMERR0",
79
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
80
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
+ { .name = "IMP_TCMERR1",
82
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
83
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ { .name = "IMP_TCMSYNDR0",
85
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
86
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+ { .name = "IMP_TCMSYNDR1",
88
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
89
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
90
+ { .name = "IMP_FLASHERR0",
91
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
92
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
93
+ { .name = "IMP_FLASHERR1",
94
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
95
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
96
+ { .name = "IMP_CDBGDR0",
97
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
98
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
99
+ { .name = "IMP_CBDGBR1",
100
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
101
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
102
+ { .name = "IMP_TESTR0",
103
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
104
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
105
+ { .name = "IMP_TESTR1",
106
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
107
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
108
+ { .name = "IMP_CDBGDCI",
109
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
110
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
111
+ { .name = "IMP_CDBGDCT",
112
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
113
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
114
+ { .name = "IMP_CDBGICT",
115
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
116
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
117
+ { .name = "IMP_CDBGDCD",
118
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
119
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
120
+ { .name = "IMP_CDBGICD",
121
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
122
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
123
+};
39
+
124
+
40
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
125
+
126
static void cortex_r52_initfn(Object *obj)
41
{
127
{
42
TCGv_i32 tmp1 = tcg_temp_new_i32();
128
ARMCPU *cpu = ARM_CPU(obj);
43
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
129
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
44
gen_set_pc_im(dc, dc->pc);
130
set_feature(&cpu->env, ARM_FEATURE_NEON);
45
/* fall through */
131
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
46
default:
132
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
47
- if (dc->ss_active) {
133
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
48
- gen_step_complete_exception(dc);
134
cpu->midr = 0x411fd133; /* r1p3 */
49
- } else {
135
cpu->revidr = 0x00000000;
50
- /* FIXME: Single stepping a WFI insn will not halt
136
cpu->reset_fpsid = 0x41034023;
51
- the CPU. */
137
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
52
- gen_exception_internal(EXCP_DEBUG);
138
53
- }
139
cpu->pmsav7_dregion = 16;
54
+ /* FIXME: Single stepping a WFI insn will not halt the CPU. */
140
cpu->pmsav8r_hdregion = 16;
55
+ gen_singlestep_exception(dc);
141
+
56
}
142
+ define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
57
if (dc->condjmp) {
143
}
58
/* "Condition failed" instruction codepath. */
144
59
gen_set_label(dc->condlabel);
145
static void cortex_r5f_initfn(Object *obj)
60
gen_set_condexec(dc);
61
gen_set_pc_im(dc, dc->pc);
62
- if (dc->ss_active) {
63
- gen_step_complete_exception(dc);
64
- } else {
65
- gen_exception_internal(EXCP_DEBUG);
66
- }
67
+ gen_singlestep_exception(dc);
68
}
69
} else {
70
/* While branches must always occur at the end of an IT block,
71
--
146
--
72
2.7.4
147
2.34.1
73
74
diff view generated by jsdifflib
1
Move the code to generate the "condition failed" instruction
1
Architecturally, the AArch32 MSR/MRS to/from banked register
2
codepath out of the if (singlestepping) {} else {}. This
2
instructions are UNPREDICTABLE for attempts to access a banked
3
will allow adding support for handling a new is_jmp type
3
register that the guest could access in a more direct way (e.g.
4
which can't be neatly split into "singlestepping case"
4
using this insn to access r8_fiq when already in FIQ mode). QEMU has
5
versus "not singlestepping case".
5
chosen to UNDEF on all of these.
6
7
However, for the case of accessing SPSR_hyp from hyp mode, it turns
8
out that real hardware permits this, with the same effect as if the
9
guest had directly written to SPSR. Further, there is some
10
guest code out there that assumes it can do this, because it
11
happens to work on hardware: an example Cortex-R52 startup code
12
fragment uses this, and it got copied into various other places,
13
including Zephyr. Zephyr was fixed to not use this:
14
https://github.com/zephyrproject-rtos/zephyr/issues/47330
15
but other examples are still out there, like the selftest
16
binary for the MPS3-AN536.
17
18
For convenience of being able to run guest code, permit
19
this UNPREDICTABLE access instead of UNDEFing it.
6
20
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <rth@twiddle.net>
23
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
10
Message-id: 1491844419-12485-6-git-send-email-peter.maydell@linaro.org
11
---
24
---
12
target/arm/translate.c | 24 +++++++++++-------------
25
target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
13
1 file changed, 11 insertions(+), 13 deletions(-)
26
target/arm/tcg/translate.c | 19 +++++++++++------
27
2 files changed, 43 insertions(+), 19 deletions(-)
14
28
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
29
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
16
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
31
--- a/target/arm/tcg/op_helper.c
18
+++ b/target/arm/translate.c
32
+++ b/target/arm/tcg/op_helper.c
19
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
33
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
20
/* At this stage dc->condjmp will only be set when the skipped
34
*/
21
instruction was a conditional branch or trap, and the PC has
35
int curmode = env->uncached_cpsr & CPSR_M;
22
already been written. */
36
23
+ gen_set_condexec(dc);
37
- if (regno == 17) {
24
if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
38
- /* ELR_Hyp: a special case because access from tgtmode is OK */
25
/* Unconditional and "condition passed" instruction codepath. */
39
- if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
26
- gen_set_condexec(dc);
40
- goto undef;
27
switch (dc->is_jmp) {
41
+ if (tgtmode == ARM_CPU_MODE_HYP) {
28
case DISAS_SWI:
42
+ /*
29
gen_ss_advance(dc);
43
+ * Handle Hyp target regs first because some are special cases
30
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
44
+ * which don't want the usual "not accessible from tgtmode" check.
31
/* FIXME: Single stepping a WFI insn will not halt the CPU. */
45
+ */
32
gen_singlestep_exception(dc);
46
+ switch (regno) {
47
+ case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
48
+ if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
49
+ goto undef;
50
+ }
51
+ break;
52
+ case 13:
53
+ if (curmode != ARM_CPU_MODE_MON) {
54
+ goto undef;
55
+ }
56
+ break;
57
+ default:
58
+ g_assert_not_reached();
33
}
59
}
34
- if (dc->condjmp) {
60
return;
35
- /* "Condition failed" instruction codepath. */
61
}
36
- gen_set_label(dc->condlabel);
62
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
37
- gen_set_condexec(dc);
38
- gen_set_pc_im(dc, dc->pc);
39
- gen_singlestep_exception(dc);
40
- }
41
} else {
42
/* While branches must always occur at the end of an IT block,
43
there are a few other things that can cause us to terminate
44
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
45
- Hardware watchpoints.
46
Hardware breakpoints have already been handled and skip this code.
47
*/
48
- gen_set_condexec(dc);
49
switch(dc->is_jmp) {
50
case DISAS_NEXT:
51
gen_goto_tb(dc, 1, dc->pc);
52
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
53
gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
54
break;
55
}
56
- if (dc->condjmp) {
57
- gen_set_label(dc->condlabel);
58
- gen_set_condexec(dc);
59
+ }
60
+
61
+ if (dc->condjmp) {
62
+ /* "Condition failed" instruction codepath for the branch/trap insn */
63
+ gen_set_label(dc->condlabel);
64
+ gen_set_condexec(dc);
65
+ if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
66
+ gen_set_pc_im(dc, dc->pc);
67
+ gen_singlestep_exception(dc);
68
+ } else {
69
gen_goto_tb(dc, 1, dc->pc);
70
- dc->condjmp = 0;
71
}
63
}
72
}
64
}
73
65
66
- if (tgtmode == ARM_CPU_MODE_HYP) {
67
- /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
68
- if (curmode != ARM_CPU_MODE_MON) {
69
- goto undef;
70
- }
71
- }
72
-
73
return;
74
75
undef:
76
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
77
78
switch (regno) {
79
case 16: /* SPSRs */
80
- env->banked_spsr[bank_number(tgtmode)] = value;
81
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
82
+ /* Only happens for SPSR_Hyp access in Hyp mode */
83
+ env->spsr = value;
84
+ } else {
85
+ env->banked_spsr[bank_number(tgtmode)] = value;
86
+ }
87
break;
88
case 17: /* ELR_Hyp */
89
env->elr_el[2] = value;
90
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
91
92
switch (regno) {
93
case 16: /* SPSRs */
94
- return env->banked_spsr[bank_number(tgtmode)];
95
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
96
+ /* Only happens for SPSR_Hyp access in Hyp mode */
97
+ return env->spsr;
98
+ } else {
99
+ return env->banked_spsr[bank_number(tgtmode)];
100
+ }
101
case 17: /* ELR_Hyp */
102
return env->elr_el[2];
103
case 13:
104
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/tcg/translate.c
107
+++ b/target/arm/tcg/translate.c
108
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
109
break;
110
case ARM_CPU_MODE_HYP:
111
/*
112
- * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
113
- * (and so we can forbid accesses from EL2 or below). elr_hyp
114
- * can be accessed also from Hyp mode, so forbid accesses from
115
- * EL0 or EL1.
116
+ * r13_hyp can only be accessed from Monitor mode, and so we
117
+ * can forbid accesses from EL2 or below.
118
+ * elr_hyp can be accessed also from Hyp mode, so forbid
119
+ * accesses from EL0 or EL1.
120
+ * SPSR_hyp is supposed to be in the same category as r13_hyp
121
+ * and UNPREDICTABLE if accessed from anything except Monitor
122
+ * mode. However there is some real-world code that will do
123
+ * it because at least some hardware happens to permit the
124
+ * access. (Notably a standard Cortex-R52 startup code fragment
125
+ * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
126
+ * this (incorrect) guest code to run.
127
*/
128
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
129
- (s->current_el < 3 && *regno != 17)) {
130
+ if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
131
+ || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
132
goto undef;
133
}
134
break;
74
--
135
--
75
2.7.4
136
2.34.1
76
77
diff view generated by jsdifflib
1
In Thumb mode, the only instructions which can cause an interworking
1
We currently guard the CFG3 register read with
2
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
2
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
3
ARM mode, data processing instructions which target the PC do not
3
which is clearly wrong as it is never true.
4
cause interworking branches.
5
4
6
When we added support for doing interworking branches on writes to
5
This register is present on all board types except AN524
7
PC from data processing instructions in commit 21aeb3430ce7ba, we
6
and AN527; correct the condition.
8
accidentally changed a Thumb instruction to have interworking
9
branch behaviour for writes to PC. (MOV, MOVS register-shifted
10
register, encoding T2; this is the standard encoding for
11
LSL/LSR/ASR/ROR (register).)
12
7
13
For this encoding, behaviour with Rd == R15 is specified as
8
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
14
UNPREDICTABLE, so allowing an interworking branch is within
15
spec, but it's confusing and differs from our handling of this
16
class of UNPREDICTABLE for other Thumb ALU operations. Make
17
it perform a simple (non-interworking) branch like the others.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <rth@twiddle.net>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Message-id: 1491844419-12485-3-git-send-email-peter.maydell@linaro.org
12
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
23
---
13
---
24
target/arm/translate.c | 2 +-
14
hw/misc/mps2-scc.c | 2 +-
25
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
26
16
27
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
28
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/translate.c
19
--- a/hw/misc/mps2-scc.c
30
+++ b/target/arm/translate.c
20
+++ b/hw/misc/mps2-scc.c
31
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
21
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
32
gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
22
r = s->cfg2;
33
if (logic_cc)
23
break;
34
gen_logic_CC(tmp);
24
case A_CFG3:
35
- store_reg_bx(s, rd, tmp);
25
- if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
36
+ store_reg(s, rd, tmp);
26
+ if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
37
break;
27
/* CFG3 reserved on AN524 */
38
case 1: /* Sign/zero extend. */
28
goto bad_offset;
39
op = (insn >> 20) & 7;
29
}
40
--
30
--
41
2.7.4
31
2.34.1
42
32
43
33
diff view generated by jsdifflib
1
On M profile, return from exceptions happen when code in Handler mode
1
The MPS SCC device has a lot of different flavours for the various
2
executes one of the following function call return instructions:
2
different MPS FPGA images, which look mostly similar but have
3
* POP or LDM which loads the PC
3
differences in how particular registers are handled. Currently we
4
* LDR to PC
4
deal with this with a lot of open-coded checks on scc_partno(), but
5
* BX register
5
as we add more board types this is getting a bit hard to read.
6
and the new PC value is 0xFFxxxxxx.
7
6
8
QEMU tries to implement this by not treating the instruction
7
Factor out the conditions into some functions which we can
9
specially but then catching the attempt to execute from the magic
8
give more descriptive names to.
10
address value. This is not ideal, because:
11
* there are guest visible differences from the architecturally
12
specified behaviour (for instance jumping to 0xFFxxxxxx via a
13
different instruction should not cause an exception return but it
14
will in the QEMU implementation)
15
* we have to account for it in various places (like refusing to take
16
an interrupt if the PC is at a magic value, and making sure that
17
the MPU doesn't deny execution at the magic value addresses)
18
19
Drop these hacks, and instead implement exception return the way the
20
architecture specifies -- by having the relevant instructions check
21
for the magic value and raise the 'do an exception return' QEMU
22
internal exception immediately.
23
24
The effect on the generated code is minor:
25
26
bx lr, old code (and new code for Thread mode):
27
TCG:
28
mov_i32 tmp5,r14
29
movi_i32 tmp6,$0xfffffffffffffffe
30
and_i32 pc,tmp5,tmp6
31
movi_i32 tmp6,$0x1
32
and_i32 tmp5,tmp5,tmp6
33
st_i32 tmp5,env,$0x218
34
exit_tb $0x0
35
set_label $L0
36
exit_tb $0x7f2aabd61993
37
x86_64 generated code:
38
0x7f2aabe87019: mov %ebx,%ebp
39
0x7f2aabe8701b: and $0xfffffffffffffffe,%ebp
40
0x7f2aabe8701e: mov %ebp,0x3c(%r14)
41
0x7f2aabe87022: and $0x1,%ebx
42
0x7f2aabe87025: mov %ebx,0x218(%r14)
43
0x7f2aabe8702c: xor %eax,%eax
44
0x7f2aabe8702e: jmpq 0x7f2aabe7c016
45
46
bx lr, new code when in Handler mode:
47
TCG:
48
mov_i32 tmp5,r14
49
movi_i32 tmp6,$0xfffffffffffffffe
50
and_i32 pc,tmp5,tmp6
51
movi_i32 tmp6,$0x1
52
and_i32 tmp5,tmp5,tmp6
53
st_i32 tmp5,env,$0x218
54
movi_i32 tmp5,$0xffffffffff000000
55
brcond_i32 pc,tmp5,geu,$L1
56
exit_tb $0x0
57
set_label $L1
58
movi_i32 tmp5,$0x8
59
call exception_internal,$0x0,$0,env,tmp5
60
x86_64 generated code:
61
0x7fe8fa1264e3: mov %ebp,%ebx
62
0x7fe8fa1264e5: and $0xfffffffffffffffe,%ebx
63
0x7fe8fa1264e8: mov %ebx,0x3c(%r14)
64
0x7fe8fa1264ec: and $0x1,%ebp
65
0x7fe8fa1264ef: mov %ebp,0x218(%r14)
66
0x7fe8fa1264f6: cmp $0xff000000,%ebx
67
0x7fe8fa1264fc: jae 0x7fe8fa126509
68
0x7fe8fa126502: xor %eax,%eax
69
0x7fe8fa126504: jmpq 0x7fe8fa122016
70
0x7fe8fa126509: mov %r14,%rdi
71
0x7fe8fa12650c: mov $0x8,%esi
72
0x7fe8fa126511: mov $0x56095dbeccf5,%r10
73
0x7fe8fa12651b: callq *%r10
74
75
which is a difference of one cmp/branch-not-taken. This will
76
be lost in the noise of having to exit generated code and
77
look up the next TB anyway.
78
9
79
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80
Reviewed-by: Richard Henderson <rth@twiddle.net>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
81
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
82
Message-id: 1491844419-12485-9-git-send-email-peter.maydell@linaro.org
13
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
83
---
14
---
84
target/arm/translate.h | 4 +++
15
hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
85
target/arm/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++-----
16
1 file changed, 31 insertions(+), 14 deletions(-)
86
2 files changed, 64 insertions(+), 6 deletions(-)
87
17
88
diff --git a/target/arm/translate.h b/target/arm/translate.h
18
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
89
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/translate.h
20
--- a/hw/misc/mps2-scc.c
91
+++ b/target/arm/translate.h
21
+++ b/hw/misc/mps2-scc.c
92
@@ -XXX,XX +XXX,XX @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
22
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
93
#define DISAS_HVC 8
23
return extract32(s->id, 4, 8);
94
#define DISAS_SMC 9
95
#define DISAS_YIELD 10
96
+/* M profile branch which might be an exception return (and so needs
97
+ * custom end-of-TB code)
98
+ */
99
+#define DISAS_BX_EXCRET 11
100
101
#ifdef TARGET_AARCH64
102
void a64_translate_init(void);
103
diff --git a/target/arm/translate.c b/target/arm/translate.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/translate.c
106
+++ b/target/arm/translate.c
107
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
108
store_cpu_field(var, thumb);
109
}
24
}
110
25
111
+/* Set PC and Thumb state from var. var is marked as dead.
26
+/* Is CFG_REG2 present? */
112
+ * For M-profile CPUs, include logic to detect exception-return
27
+static bool have_cfg2(MPS2SCC *s)
113
+ * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
114
+ * and BX reg, and no others, and happens only for code in Handler mode.
115
+ */
116
+static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
117
+{
28
+{
118
+ /* Generate the same code here as for a simple bx, but flag via
29
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
119
+ * s->is_jmp that we need to do the rest of the work later.
120
+ */
121
+ gen_bx(s, var);
122
+ if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
123
+ s->is_jmp = DISAS_BX_EXCRET;
124
+ }
125
+}
30
+}
126
+
31
+
127
+static inline void gen_bx_excret_final_code(DisasContext *s)
32
+/* Is CFG_REG3 present? */
33
+static bool have_cfg3(MPS2SCC *s)
128
+{
34
+{
129
+ /* Generate the code to finish possible exception return and end the TB */
35
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
130
+ TCGLabel *excret_label = gen_new_label();
131
+
132
+ /* Is the new PC value in the magic range indicating exception return? */
133
+ tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
134
+ /* No: end the TB as we would for a DISAS_JMP */
135
+ if (is_singlestepping(s)) {
136
+ gen_singlestep_exception(s);
137
+ } else {
138
+ tcg_gen_exit_tb(0);
139
+ }
140
+ gen_set_label(excret_label);
141
+ /* Yes: this is an exception return.
142
+ * At this point in runtime env->regs[15] and env->thumb will hold
143
+ * the exception-return magic number, which do_v7m_exception_exit()
144
+ * will read. Nothing else will be able to see those values because
145
+ * the cpu-exec main loop guarantees that we will always go straight
146
+ * from raising the exception to the exception-handling code.
147
+ *
148
+ * gen_ss_advance(s) does nothing on M profile currently but
149
+ * calling it is conceptually the right thing as we have executed
150
+ * this instruction (compare SWI, HVC, SMC handling).
151
+ */
152
+ gen_ss_advance(s);
153
+ gen_exception_internal(EXCP_EXCEPTION_EXIT);
154
+}
36
+}
155
+
37
+
156
/* Variant of store_reg which uses branch&exchange logic when storing
38
+/* Is CFG_REG5 present? */
157
to r15 in ARM architecture v7 and above. The source must be a temporary
39
+static bool have_cfg5(MPS2SCC *s)
158
and will be marked as dead. */
40
+{
159
@@ -XXX,XX +XXX,XX @@ static inline void store_reg_bx(DisasContext *s, int reg, TCGv_i32 var)
41
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
160
static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
42
+}
161
{
43
+
162
if (reg == 15 && ENABLE_ARCH_5) {
44
+/* Is CFG_REG6 present? */
163
- gen_bx(s, var);
45
+static bool have_cfg6(MPS2SCC *s)
164
+ gen_bx_excret(s, var);
46
+{
165
} else {
47
+ return scc_partno(s) == 0x524;
166
store_reg(s, reg, var);
48
+}
167
}
49
+
168
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
50
/* Handle a write via the SYS_CFG channel to the specified function/device.
169
tmp = tcg_temp_new_i32();
51
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
170
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
52
*/
171
if (i == 15) {
53
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
172
- gen_bx(s, tmp);
54
r = s->cfg1;
173
+ gen_bx_excret(s, tmp);
55
break;
174
} else if (i == rn) {
56
case A_CFG2:
175
loaded_var = tmp;
57
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
176
loaded_base = 1;
58
- /* CFG2 reserved on other boards */
177
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
59
+ if (!have_cfg2(s)) {
178
goto illegal_op;
60
goto bad_offset;
179
}
61
}
180
if (rs == 15) {
62
r = s->cfg2;
181
- gen_bx(s, tmp);
63
break;
182
+ gen_bx_excret(s, tmp);
64
case A_CFG3:
183
} else {
65
- if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
184
store_reg(s, rs, tmp);
66
- /* CFG3 reserved on AN524 */
185
}
67
+ if (!have_cfg3(s)) {
186
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
68
goto bad_offset;
187
tmp2 = tcg_temp_new_i32();
69
}
188
tcg_gen_movi_i32(tmp2, val);
70
/* These are user-settable DIP switches on the board. We don't
189
store_reg(s, 14, tmp2);
71
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
190
+ gen_bx(s, tmp);
72
r = s->cfg4;
191
+ } else {
73
break;
192
+ /* Only BX works as exception-return, not BLX */
74
case A_CFG5:
193
+ gen_bx_excret(s, tmp);
75
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
194
}
76
- /* CFG5 reserved on other boards */
195
- /* already thumb, no need to check */
77
+ if (!have_cfg5(s)) {
196
- gen_bx(s, tmp);
78
goto bad_offset;
197
break;
79
}
198
}
80
r = s->cfg5;
199
break;
81
break;
200
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
82
case A_CFG6:
201
instruction was a conditional branch or trap, and the PC has
83
- if (scc_partno(s) != 0x524) {
202
already been written. */
84
- /* CFG6 reserved on other boards */
203
gen_set_condexec(dc);
85
+ if (!have_cfg6(s)) {
204
- if (unlikely(is_singlestepping(dc))) {
86
goto bad_offset;
205
+ if (dc->is_jmp == DISAS_BX_EXCRET) {
87
}
206
+ /* Exception return branches need some special case code at the
88
r = s->cfg6;
207
+ * end of the TB, which is complex enough that it has to
89
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
208
+ * handle the single-step vs not and the condition-failed
90
}
209
+ * insn codepath itself.
91
break;
210
+ */
92
case A_CFG2:
211
+ gen_bx_excret_final_code(dc);
93
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
212
+ } else if (unlikely(is_singlestepping(dc))) {
94
- /* CFG2 reserved on other boards */
213
/* Unconditional and "condition passed" instruction codepath. */
95
+ if (!have_cfg2(s)) {
214
switch (dc->is_jmp) {
96
goto bad_offset;
215
case DISAS_SWI:
97
}
98
/* AN524: QSPI Select signal */
99
s->cfg2 = value;
100
break;
101
case A_CFG5:
102
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
103
- /* CFG5 reserved on other boards */
104
+ if (!have_cfg5(s)) {
105
goto bad_offset;
106
}
107
/* AN524: ACLK frequency in Hz */
108
s->cfg5 = value;
109
break;
110
case A_CFG6:
111
- if (scc_partno(s) != 0x524) {
112
- /* CFG6 reserved on other boards */
113
+ if (!have_cfg6(s)) {
114
goto bad_offset;
115
}
116
/* AN524: Clock divider for BRAM */
216
--
117
--
217
2.7.4
118
2.34.1
218
119
219
120
diff view generated by jsdifflib
1
For M profile exception-return handling we'd like to generate different
1
The MPS2 SCC device is broadly the same for all FPGA images, but has
2
code for some instructions depending on whether we are in Handler
2
minor differences in the behaviour of the CFG registers depending on
3
mode or Thread mode. This isn't the same as "are we privileged
3
the image. In many cases we don't really care about the functionality
4
or user", so we need an extra bit in the TB flags to distinguish.
4
controlled by these registers and a reads-as-written or similar
5
behaviour is sufficient for the moment.
6
7
For the AN536 the required behaviour is:
8
9
* A_CFG0 has CPU reset and halt bits
10
- implement as reads-as-written for the moment
11
* A_CFG1 has flash or ATCM address 0 remap handling
12
- QEMU doesn't model this; implement as reads-as-written
13
* A_CFG2 has QSPI select (like AN524)
14
- implemented (no behaviour, as with AN524)
15
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
16
- QEMU doesn't care about these, so use the existing
17
RAZ behaviour for convenience
18
* A_CFG4 is board rev (like all other images)
19
- no change needed
20
* A_CFG5 is ACLK frq in hz (like AN524)
21
- implemented as reads-as-written, as for other boards
22
* A_CFG6 is core 0 vector table base address
23
- implemented as reads-as-written for the moment
24
* A_CFG7 is core 1 vector table base address
25
- implemented as reads-as-written for the moment
26
27
Make the changes necessary for this; leave TODO comments where
28
appropriate to indicate where we might want to come back and
29
implement things like CPU reset.
30
31
The other aspects of the device specific to this FPGA image (like the
32
values of the board ID and similar registers) will be set via the
33
device's qdev properties.
5
34
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 1491844419-12485-8-git-send-email-peter.maydell@linaro.org
38
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
10
---
39
---
11
target/arm/cpu.h | 9 +++++++++
40
include/hw/misc/mps2-scc.h | 1 +
12
target/arm/translate.h | 1 +
41
hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++----
13
target/arm/translate.c | 1 +
42
2 files changed, 92 insertions(+), 10 deletions(-)
14
3 files changed, 11 insertions(+)
43
15
44
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
46
--- a/include/hw/misc/mps2-scc.h
19
+++ b/target/arm/cpu.h
47
+++ b/include/hw/misc/mps2-scc.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
48
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
21
#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
49
uint32_t cfg4;
22
#define ARM_TBFLAG_BE_DATA_SHIFT 20
50
uint32_t cfg5;
23
#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
51
uint32_t cfg6;
24
+/* For M profile only, Handler (ie not Thread) mode */
52
+ uint32_t cfg7;
25
+#define ARM_TBFLAG_HANDLER_SHIFT 21
53
uint32_t cfgdata_rtn;
26
+#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
54
uint32_t cfgdata_out;
27
55
uint32_t cfgctrl;
28
/* Bit usage when in AArch64 state */
56
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
29
#define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */
57
index XXXXXXX..XXXXXXX 100644
30
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
58
--- a/hw/misc/mps2-scc.c
31
(((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
59
+++ b/hw/misc/mps2-scc.c
32
#define ARM_TBFLAG_BE_DATA(F) \
60
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
33
(((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
61
REG32(CFG4, 0x10)
34
+#define ARM_TBFLAG_HANDLER(F) \
62
REG32(CFG5, 0x14)
35
+ (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
63
REG32(CFG6, 0x18)
36
#define ARM_TBFLAG_TBI0(F) \
64
+REG32(CFG7, 0x1c)
37
(((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
65
REG32(CFGDATA_RTN, 0xa0)
38
#define ARM_TBFLAG_TBI1(F) \
66
REG32(CFGDATA_OUT, 0xa4)
39
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
67
REG32(CFGCTRL, 0xa8)
68
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
69
/* Is CFG_REG2 present? */
70
static bool have_cfg2(MPS2SCC *s)
71
{
72
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
73
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
74
+ scc_partno(s) == 0x536;
75
}
76
77
/* Is CFG_REG3 present? */
78
static bool have_cfg3(MPS2SCC *s)
79
{
80
- return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
81
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
82
+ scc_partno(s) != 0x536;
83
}
84
85
/* Is CFG_REG5 present? */
86
static bool have_cfg5(MPS2SCC *s)
87
{
88
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
89
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
90
+ scc_partno(s) == 0x536;
91
}
92
93
/* Is CFG_REG6 present? */
94
static bool have_cfg6(MPS2SCC *s)
95
{
96
- return scc_partno(s) == 0x524;
97
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
98
+}
99
+
100
+/* Is CFG_REG7 present? */
101
+static bool have_cfg7(MPS2SCC *s)
102
+{
103
+ return scc_partno(s) == 0x536;
104
+}
105
+
106
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
107
+static bool cfg0_is_remap(MPS2SCC *s)
108
+{
109
+ return scc_partno(s) != 0x536;
110
+}
111
+
112
+/* Is CFG_REG1 driving a set of LEDs? */
113
+static bool cfg1_is_leds(MPS2SCC *s)
114
+{
115
+ return scc_partno(s) != 0x536;
116
}
117
118
/* Handle a write via the SYS_CFG channel to the specified function/device.
119
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
120
if (!have_cfg3(s)) {
121
goto bad_offset;
122
}
123
- /* These are user-settable DIP switches on the board. We don't
124
+ /*
125
+ * These are user-settable DIP switches on the board. We don't
126
* model that, so just return zeroes.
127
+ *
128
+ * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
129
+ * bits". These change which part of the DDR4 the motherboard
130
+ * configuration controller can see in its memory map (see the
131
+ * appnote section 2.4). QEMU doesn't model the MCC at all, so these
132
+ * bits are not interesting to us; read-as-zero is as good as anything
133
+ * else.
134
*/
135
r = 0;
136
break;
137
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
138
}
139
r = s->cfg6;
140
break;
141
+ case A_CFG7:
142
+ if (!have_cfg7(s)) {
143
+ goto bad_offset;
144
+ }
145
+ r = s->cfg7;
146
+ break;
147
case A_CFGDATA_RTN:
148
r = s->cfgdata_rtn;
149
break;
150
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
151
* we always reflect bit 0 in the 'remap' GPIO output line,
152
* and let the board wire it up or not as it chooses.
153
* TODO on some boards bit 1 is CPU_WAIT.
154
+ *
155
+ * TODO: on the AN536 this register controls reset and halt
156
+ * for both CPUs. For the moment we don't implement this, so the
157
+ * register just reads as written.
158
*/
159
s->cfg0 = value;
160
- qemu_set_irq(s->remap, s->cfg0 & 1);
161
+ if (cfg0_is_remap(s)) {
162
+ qemu_set_irq(s->remap, s->cfg0 & 1);
163
+ }
164
break;
165
case A_CFG1:
166
s->cfg1 = value;
167
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
168
- led_set_state(s->led[i], extract32(value, i, 1));
169
+ /*
170
+ * On most boards this register drives LEDs.
171
+ *
172
+ * TODO: for AN536 this controls whether flash and ATCM are
173
+ * enabled or disabled on reset. QEMU doesn't model this, and
174
+ * always wires up RAM in the ATCM area and ROM in the flash area.
175
+ */
176
+ if (cfg1_is_leds(s)) {
177
+ for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
178
+ led_set_state(s->led[i], extract32(value, i, 1));
179
+ }
180
}
181
break;
182
case A_CFG2:
183
if (!have_cfg2(s)) {
184
goto bad_offset;
185
}
186
- /* AN524: QSPI Select signal */
187
+ /* AN524, AN536: QSPI Select signal */
188
s->cfg2 = value;
189
break;
190
case A_CFG5:
191
if (!have_cfg5(s)) {
192
goto bad_offset;
193
}
194
- /* AN524: ACLK frequency in Hz */
195
+ /* AN524, AN536: ACLK frequency in Hz */
196
s->cfg5 = value;
197
break;
198
case A_CFG6:
199
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
200
goto bad_offset;
201
}
202
/* AN524: Clock divider for BRAM */
203
+ /* AN536: Core 0 vector table base address */
204
+ s->cfg6 = value;
205
+ break;
206
+ case A_CFG7:
207
+ if (!have_cfg7(s)) {
208
+ goto bad_offset;
209
+ }
210
+ /* AN536: Core 1 vector table base address */
211
s->cfg6 = value;
212
break;
213
case A_CFGDATA_OUT:
214
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
215
g_free(s->oscclk_reset);
216
}
217
218
+static bool cfg7_needed(void *opaque)
219
+{
220
+ MPS2SCC *s = opaque;
221
+
222
+ return have_cfg7(s);
223
+}
224
+
225
+static const VMStateDescription vmstate_cfg7 = {
226
+ .name = "mps2-scc/cfg7",
227
+ .version_id = 1,
228
+ .minimum_version_id = 1,
229
+ .needed = cfg7_needed,
230
+ .fields = (const VMStateField[]) {
231
+ VMSTATE_UINT32(cfg7, MPS2SCC),
232
+ VMSTATE_END_OF_LIST()
233
+ }
234
+};
235
+
236
static const VMStateDescription mps2_scc_vmstate = {
237
.name = "mps2-scc",
238
.version_id = 3,
239
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
240
VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
241
0, vmstate_info_uint32, uint32_t),
242
VMSTATE_END_OF_LIST()
243
+ },
244
+ .subsections = (const VMStateDescription * const []) {
245
+ &vmstate_cfg7,
246
+ NULL
40
}
247
}
41
*flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
248
};
42
43
+ if (env->v7m.exception != 0) {
44
+ *flags |= ARM_TBFLAG_HANDLER_MASK;
45
+ }
46
+
47
*cs_base = 0;
48
}
49
50
diff --git a/target/arm/translate.h b/target/arm/translate.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate.h
53
+++ b/target/arm/translate.h
54
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
55
bool vfp_enabled; /* FP enabled via FPSCR.EN */
56
int vec_len;
57
int vec_stride;
58
+ bool v7m_handler_mode;
59
/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
60
* so that top level loop can generate correct syndrome information.
61
*/
62
diff --git a/target/arm/translate.c b/target/arm/translate.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/translate.c
65
+++ b/target/arm/translate.c
66
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
67
dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
68
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
69
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
70
+ dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
71
dc->cp_regs = cpu->cp_regs;
72
dc->features = env->features;
73
249
74
--
250
--
75
2.7.4
251
2.34.1
76
252
77
253
diff view generated by jsdifflib
New patch
1
1
The AN536 is another FPGA image for the MPS3 development board. Unlike
2
the existing FPGA images we already model, this board uses a Cortex-R
3
family CPU, and it does not use any equivalent to the M-profile
4
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
5
It's therefore more convenient for us to model it as a completely
6
separate C file.
7
8
This commit adds the basic skeleton of the board model, and the
9
code to create all the RAM and ROM. We assume that we're probably
10
going to want to add more images in future, so use the same
11
base class/subclass setup that mps2-tz.c uses, even though at
12
the moment there's only a single subclass.
13
14
Following commits will add the CPUs and the peripherals.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
19
---
20
MAINTAINERS | 3 +-
21
configs/devices/arm-softmmu/default.mak | 1 +
22
hw/arm/mps3r.c | 239 ++++++++++++++++++++++++
23
hw/arm/Kconfig | 5 +
24
hw/arm/meson.build | 1 +
25
5 files changed, 248 insertions(+), 1 deletion(-)
26
create mode 100644 hw/arm/mps3r.c
27
28
diff --git a/MAINTAINERS b/MAINTAINERS
29
index XXXXXXX..XXXXXXX 100644
30
--- a/MAINTAINERS
31
+++ b/MAINTAINERS
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
33
F: hw/pci-host/designware.c
34
F: include/hw/pci-host/designware.h
35
36
-MPS2
37
+MPS2 / MPS3
38
M: Peter Maydell <peter.maydell@linaro.org>
39
L: qemu-arm@nongnu.org
40
S: Maintained
41
F: hw/arm/mps2.c
42
F: hw/arm/mps2-tz.c
43
+F: hw/arm/mps3r.c
44
F: hw/misc/mps2-*.c
45
F: include/hw/misc/mps2-*.h
46
F: hw/arm/armsse.c
47
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
48
index XXXXXXX..XXXXXXX 100644
49
--- a/configs/devices/arm-softmmu/default.mak
50
+++ b/configs/devices/arm-softmmu/default.mak
51
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
52
# CONFIG_INTEGRATOR=n
53
# CONFIG_FSL_IMX31=n
54
# CONFIG_MUSICPAL=n
55
+# CONFIG_MPS3R=n
56
# CONFIG_MUSCA=n
57
# CONFIG_CHEETAH=n
58
# CONFIG_SX1=n
59
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
60
new file mode 100644
61
index XXXXXXX..XXXXXXX
62
--- /dev/null
63
+++ b/hw/arm/mps3r.c
64
@@ -XXX,XX +XXX,XX @@
65
+/*
66
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
67
+ * (For M-profile images see mps2.c and mps2tz.c.)
68
+ *
69
+ * Copyright (c) 2017 Linaro Limited
70
+ * Written by Peter Maydell
71
+ *
72
+ * This program is free software; you can redistribute it and/or modify
73
+ * it under the terms of the GNU General Public License version 2 or
74
+ * (at your option) any later version.
75
+ */
76
+
77
+/*
78
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
79
+ * which use the Cortex-R CPUs. We model these separately from the
80
+ * M-profile images, because on M-profile the FPGA image is based on
81
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
82
+ * the R-profile FPGA images don't have that abstraction layer.
83
+ *
84
+ * We model the following FPGA images here:
85
+ * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
86
+ *
87
+ * Application Note AN536:
88
+ * https://developer.arm.com/documentation/dai0536/latest/
89
+ */
90
+
91
+#include "qemu/osdep.h"
92
+#include "qemu/units.h"
93
+#include "qapi/error.h"
94
+#include "exec/address-spaces.h"
95
+#include "cpu.h"
96
+#include "hw/boards.h"
97
+#include "hw/arm/boot.h"
98
+
99
+/* Define the layout of RAM and ROM in a board */
100
+typedef struct RAMInfo {
101
+ const char *name;
102
+ hwaddr base;
103
+ hwaddr size;
104
+ int mrindex; /* index into rams[]; -1 for the system RAM block */
105
+ int flags;
106
+} RAMInfo;
107
+
108
+/*
109
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
110
+ * emulation of that much guest RAM, so artificially make it smaller.
111
+ */
112
+#if HOST_LONG_BITS == 32
113
+#define MPS3_DDR_SIZE (1 * GiB)
114
+#else
115
+#define MPS3_DDR_SIZE (3 * GiB)
116
+#endif
117
+
118
+/*
119
+ * Flag values:
120
+ * IS_MAIN: this is the main machine RAM
121
+ * IS_ROM: this area is read-only
122
+ */
123
+#define IS_MAIN 1
124
+#define IS_ROM 2
125
+
126
+#define MPS3R_RAM_MAX 9
127
+
128
+typedef enum MPS3RFPGAType {
129
+ FPGA_AN536,
130
+} MPS3RFPGAType;
131
+
132
+struct MPS3RMachineClass {
133
+ MachineClass parent;
134
+ MPS3RFPGAType fpga_type;
135
+ const RAMInfo *raminfo;
136
+};
137
+
138
+struct MPS3RMachineState {
139
+ MachineState parent;
140
+ MemoryRegion ram[MPS3R_RAM_MAX];
141
+};
142
+
143
+#define TYPE_MPS3R_MACHINE "mps3r"
144
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
145
+
146
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
147
+
148
+static const RAMInfo an536_raminfo[] = {
149
+ {
150
+ .name = "ATCM",
151
+ .base = 0x00000000,
152
+ .size = 0x00008000,
153
+ .mrindex = 0,
154
+ }, {
155
+ /* We model the QSPI flash as simple ROM for now */
156
+ .name = "QSPI",
157
+ .base = 0x08000000,
158
+ .size = 0x00800000,
159
+ .flags = IS_ROM,
160
+ .mrindex = 1,
161
+ }, {
162
+ .name = "BRAM",
163
+ .base = 0x10000000,
164
+ .size = 0x00080000,
165
+ .mrindex = 2,
166
+ }, {
167
+ .name = "DDR",
168
+ .base = 0x20000000,
169
+ .size = MPS3_DDR_SIZE,
170
+ .mrindex = -1,
171
+ }, {
172
+ .name = "ATCM0",
173
+ .base = 0xee000000,
174
+ .size = 0x00008000,
175
+ .mrindex = 3,
176
+ }, {
177
+ .name = "BTCM0",
178
+ .base = 0xee100000,
179
+ .size = 0x00008000,
180
+ .mrindex = 4,
181
+ }, {
182
+ .name = "CTCM0",
183
+ .base = 0xee200000,
184
+ .size = 0x00008000,
185
+ .mrindex = 5,
186
+ }, {
187
+ .name = "ATCM1",
188
+ .base = 0xee400000,
189
+ .size = 0x00008000,
190
+ .mrindex = 6,
191
+ }, {
192
+ .name = "BTCM1",
193
+ .base = 0xee500000,
194
+ .size = 0x00008000,
195
+ .mrindex = 7,
196
+ }, {
197
+ .name = "CTCM1",
198
+ .base = 0xee600000,
199
+ .size = 0x00008000,
200
+ .mrindex = 8,
201
+ }, {
202
+ .name = NULL,
203
+ }
204
+};
205
+
206
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
207
+ const RAMInfo *raminfo)
208
+{
209
+ /* Return an initialized MemoryRegion for the RAMInfo. */
210
+ MemoryRegion *ram;
211
+
212
+ if (raminfo->mrindex < 0) {
213
+ /* Means this RAMInfo is for QEMU's "system memory" */
214
+ MachineState *machine = MACHINE(mms);
215
+ assert(!(raminfo->flags & IS_ROM));
216
+ return machine->ram;
217
+ }
218
+
219
+ assert(raminfo->mrindex < MPS3R_RAM_MAX);
220
+ ram = &mms->ram[raminfo->mrindex];
221
+
222
+ memory_region_init_ram(ram, NULL, raminfo->name,
223
+ raminfo->size, &error_fatal);
224
+ if (raminfo->flags & IS_ROM) {
225
+ memory_region_set_readonly(ram, true);
226
+ }
227
+ return ram;
228
+}
229
+
230
+static void mps3r_common_init(MachineState *machine)
231
+{
232
+ MPS3RMachineState *mms = MPS3R_MACHINE(machine);
233
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
234
+ MemoryRegion *sysmem = get_system_memory();
235
+
236
+ for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
237
+ MemoryRegion *mr = mr_for_raminfo(mms, ri);
238
+ memory_region_add_subregion(sysmem, ri->base, mr);
239
+ }
240
+}
241
+
242
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
243
+{
244
+ /*
245
+ * Set mc->default_ram_size and default_ram_id from the
246
+ * information in mmc->raminfo.
247
+ */
248
+ MachineClass *mc = MACHINE_CLASS(mmc);
249
+ const RAMInfo *p;
250
+
251
+ for (p = mmc->raminfo; p->name; p++) {
252
+ if (p->mrindex < 0) {
253
+ /* Found the entry for "system memory" */
254
+ mc->default_ram_size = p->size;
255
+ mc->default_ram_id = p->name;
256
+ return;
257
+ }
258
+ }
259
+ g_assert_not_reached();
260
+}
261
+
262
+static void mps3r_class_init(ObjectClass *oc, void *data)
263
+{
264
+ MachineClass *mc = MACHINE_CLASS(oc);
265
+
266
+ mc->init = mps3r_common_init;
267
+}
268
+
269
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
270
+{
271
+ MachineClass *mc = MACHINE_CLASS(oc);
272
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
273
+ static const char * const valid_cpu_types[] = {
274
+ ARM_CPU_TYPE_NAME("cortex-r52"),
275
+ NULL
276
+ };
277
+
278
+ mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
279
+ mc->default_cpus = 2;
280
+ mc->min_cpus = mc->default_cpus;
281
+ mc->max_cpus = mc->default_cpus;
282
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
283
+ mc->valid_cpu_types = valid_cpu_types;
284
+ mmc->raminfo = an536_raminfo;
285
+ mps3r_set_default_ram_info(mmc);
286
+}
287
+
288
+static const TypeInfo mps3r_machine_types[] = {
289
+ {
290
+ .name = TYPE_MPS3R_MACHINE,
291
+ .parent = TYPE_MACHINE,
292
+ .abstract = true,
293
+ .instance_size = sizeof(MPS3RMachineState),
294
+ .class_size = sizeof(MPS3RMachineClass),
295
+ .class_init = mps3r_class_init,
296
+ }, {
297
+ .name = TYPE_MPS3R_AN536_MACHINE,
298
+ .parent = TYPE_MPS3R_MACHINE,
299
+ .class_init = mps3r_an536_class_init,
300
+ },
301
+};
302
+
303
+DEFINE_TYPES(mps3r_machine_types);
304
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
305
index XXXXXXX..XXXXXXX 100644
306
--- a/hw/arm/Kconfig
307
+++ b/hw/arm/Kconfig
308
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
309
select PFLASH_CFI01
310
select SMC91C111
311
312
+config MPS3R
313
+ bool
314
+ default y
315
+ depends on TCG && ARM
316
+
317
config MUSCA
318
bool
319
default y
320
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/arm/meson.build
323
+++ b/hw/arm/meson.build
324
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
325
arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
326
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
327
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
328
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
329
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
330
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
331
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
332
--
333
2.34.1
334
335
diff view generated by jsdifflib
1
Move the utility routines gen_set_condexec() and gen_set_pc_im()
1
Create the CPUs, the GIC, and the per-CPU RAM block for
2
up in the file, as we will want to use them from a function
2
the mps3-an536 board.
3
placed earlier in the file than their current location.
4
3
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Message-id: 1491844419-12485-5-git-send-email-peter.maydell@linaro.org
9
---
6
---
10
target/arm/translate.c | 31 +++++++++++++++----------------
7
hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
11
1 file changed, 15 insertions(+), 16 deletions(-)
8
1 file changed, 177 insertions(+), 3 deletions(-)
12
9
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
10
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
12
--- a/hw/arm/mps3r.c
16
+++ b/target/arm/translate.c
13
+++ b/hw/arm/mps3r.c
17
@@ -XXX,XX +XXX,XX @@ static const uint8_t table_logic_cc[16] = {
14
@@ -XXX,XX +XXX,XX @@
18
1, /* mvn */
15
#include "qemu/osdep.h"
16
#include "qemu/units.h"
17
#include "qapi/error.h"
18
+#include "qapi/qmp/qlist.h"
19
#include "exec/address-spaces.h"
20
#include "cpu.h"
21
#include "hw/boards.h"
22
+#include "hw/qdev-properties.h"
23
#include "hw/arm/boot.h"
24
+#include "hw/arm/bsa.h"
25
+#include "hw/intc/arm_gicv3.h"
26
27
/* Define the layout of RAM and ROM in a board */
28
typedef struct RAMInfo {
29
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
30
#define IS_ROM 2
31
32
#define MPS3R_RAM_MAX 9
33
+#define MPS3R_CPU_MAX 2
34
+
35
+#define PERIPHBASE 0xf0000000
36
+#define NUM_SPIS 96
37
38
typedef enum MPS3RFPGAType {
39
FPGA_AN536,
40
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
41
MachineClass parent;
42
MPS3RFPGAType fpga_type;
43
const RAMInfo *raminfo;
44
+ hwaddr loader_start;
19
};
45
};
20
46
21
+static inline void gen_set_condexec(DisasContext *s)
47
struct MPS3RMachineState {
48
MachineState parent;
49
+ struct arm_boot_info bootinfo;
50
MemoryRegion ram[MPS3R_RAM_MAX];
51
+ Object *cpu[MPS3R_CPU_MAX];
52
+ MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
53
+ MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
54
+ MemoryRegion cpu_ram[MPS3R_CPU_MAX];
55
+ GICv3State gic;
56
};
57
58
#define TYPE_MPS3R_MACHINE "mps3r"
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
60
return ram;
61
}
62
63
+/*
64
+ * There is no defined secondary boot protocol for Linux for the AN536,
65
+ * because real hardware has a restriction that atomic operations between
66
+ * the two CPUs do not function correctly, and so true SMP is not
67
+ * possible. Therefore for cases where the user is directly booting
68
+ * a kernel, we treat the system as essentially uniprocessor, and
69
+ * put the secondary CPU into power-off state (as if the user on the
70
+ * real hardware had configured the secondary to be halted via the
71
+ * SCC config registers).
72
+ *
73
+ * Note that the default secondary boot code would not work here anyway
74
+ * as it assumes a GICv2, and we have a GICv3.
75
+ */
76
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
77
+ const struct arm_boot_info *info)
22
+{
78
+{
23
+ if (s->condexec_mask) {
79
+ /*
24
+ uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
80
+ * Power the secondary CPU off. This means we don't need to write any
25
+ TCGv_i32 tmp = tcg_temp_new_i32();
81
+ * boot code into guest memory. Note that the 'cpu' argument to this
26
+ tcg_gen_movi_i32(tmp, val);
82
+ * function is the primary CPU we passed to arm_load_kernel(), not
27
+ store_cpu_field(tmp, condexec_bits);
83
+ * the secondary. Loop around all the other CPUs, as the boot.c
84
+ * code does for the "disable secondaries if PSCI is enabled" case.
85
+ */
86
+ for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
87
+ if (cs != first_cpu) {
88
+ object_property_set_bool(OBJECT(cs), "start-powered-off", true,
89
+ &error_abort);
90
+ }
28
+ }
91
+ }
29
+}
92
+}
30
+
93
+
31
+static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
94
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
32
+{
96
+{
33
+ tcg_gen_movi_i32(cpu_R[15], val);
97
+ /* We don't need to do anything here because the CPU will be off */
34
+}
98
+}
35
+
99
+
36
/* Set PC and Thumb state from an immediate address. */
100
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
37
static inline void gen_bx_im(DisasContext *s, uint32_t addr)
101
+{
102
+ MachineState *machine = MACHINE(mms);
103
+ DeviceState *gicdev;
104
+ QList *redist_region_count;
105
+
106
+ object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
107
+ gicdev = DEVICE(&mms->gic);
108
+ qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
109
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
110
+ redist_region_count = qlist_new();
111
+ qlist_append_int(redist_region_count, machine->smp.cpus);
112
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
113
+ object_property_set_link(OBJECT(&mms->gic), "sysmem",
114
+ OBJECT(sysmem), &error_fatal);
115
+ sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
116
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
118
+ /*
119
+ * Wire the outputs from each CPU's generic timer and the GICv3
120
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
121
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
122
+ */
123
+ for (int i = 0; i < machine->smp.cpus; i++) {
124
+ DeviceState *cpudev = DEVICE(mms->cpu[i]);
125
+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
126
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
127
+ int irq;
128
+ /*
129
+ * Mapping from the output timer irq lines from the CPU to the
130
+ * GIC PPI inputs used for this board. This isn't a BSA board,
131
+ * but it uses the standard convention for the PPI numbers.
132
+ */
133
+ const int timer_irq[] = {
134
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
135
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
136
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
137
+ };
138
+
139
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
140
+ qdev_connect_gpio_out(cpudev, irq,
141
+ qdev_get_gpio_in(gicdev,
142
+ intidbase + timer_irq[irq]));
143
+ }
144
+
145
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
146
+ qdev_get_gpio_in(gicdev,
147
+ intidbase + ARCH_GIC_MAINT_IRQ));
148
+
149
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
150
+ qdev_get_gpio_in(gicdev,
151
+ intidbase + VIRTUAL_PMU_IRQ));
152
+
153
+ sysbus_connect_irq(gicsbd, i,
154
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
155
+ sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
156
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
157
+ sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
158
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
159
+ sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
160
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
161
+ }
162
+}
163
+
164
static void mps3r_common_init(MachineState *machine)
38
{
165
{
39
@@ -XXX,XX +XXX,XX @@ DO_GEN_ST(8, MO_UB)
166
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
40
DO_GEN_ST(16, MO_UW)
167
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
41
DO_GEN_ST(32, MO_UL)
168
MemoryRegion *mr = mr_for_raminfo(mms, ri);
42
169
memory_region_add_subregion(sysmem, ri->base, mr);
43
-static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
170
}
44
-{
171
+
45
- tcg_gen_movi_i32(cpu_R[15], val);
172
+ assert(machine->smp.cpus <= MPS3R_CPU_MAX);
46
-}
173
+ for (int i = 0; i < machine->smp.cpus; i++) {
47
-
174
+ g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
48
static inline void gen_hvc(DisasContext *s, int imm16)
175
+ g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
49
{
176
+ g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
50
/* The pre HVC helper handles cases when HVC gets trapped
177
+
51
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
178
+ /*
52
s->is_jmp = DISAS_SMC;
179
+ * Each CPU has some private RAM/peripherals, so create the container
180
+ * which will house those, with the whole-machine system memory being
181
+ * used where there's no CPU-specific device. Note that we need the
182
+ * sysmem_alias aliases because we can't put one MR (the original
183
+ * 'sysmem') into more than one other MR.
184
+ */
185
+ memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
186
+ sysmem_name, UINT64_MAX);
187
+ memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
188
+ alias_name, sysmem, 0, UINT64_MAX);
189
+ memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
190
+ &mms->sysmem_alias[i], -1);
191
+
192
+ mms->cpu[i] = object_new(machine->cpu_type);
193
+ object_property_set_link(mms->cpu[i], "memory",
194
+ OBJECT(&mms->cpu_sysmem[i]), &error_abort);
195
+ object_property_set_int(mms->cpu[i], "reset-cbar",
196
+ PERIPHBASE, &error_abort);
197
+ qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
198
+ object_unref(mms->cpu[i]);
199
+
200
+ /* Per-CPU RAM */
201
+ memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
202
+ 0x1000, &error_fatal);
203
+ memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
204
+ &mms->cpu_ram[i]);
205
+ }
206
+
207
+ create_gic(mms, sysmem);
208
+
209
+ mms->bootinfo.ram_size = machine->ram_size;
210
+ mms->bootinfo.board_id = -1;
211
+ mms->bootinfo.loader_start = mmc->loader_start;
212
+ mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
213
+ mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
214
+ arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
53
}
215
}
54
216
55
-static inline void
217
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
56
-gen_set_condexec (DisasContext *s)
218
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
57
-{
219
/* Found the entry for "system memory" */
58
- if (s->condexec_mask) {
220
mc->default_ram_size = p->size;
59
- uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
221
mc->default_ram_id = p->name;
60
- TCGv_i32 tmp = tcg_temp_new_i32();
222
+ mmc->loader_start = p->base;
61
- tcg_gen_movi_i32(tmp, val);
223
return;
62
- store_cpu_field(tmp, condexec_bits);
224
}
63
- }
225
}
64
-}
226
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
65
-
227
};
66
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
228
67
{
229
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
68
gen_set_condexec(s);
230
- mc->default_cpus = 2;
231
- mc->min_cpus = mc->default_cpus;
232
- mc->max_cpus = mc->default_cpus;
233
+ /*
234
+ * In the real FPGA image there are always two cores, but the standard
235
+ * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
236
+ * that the second core is held in reset and halted. Many images built for
237
+ * the board do not expect the second core to run at startup (especially
238
+ * since on the real FPGA image it is not possible to use LDREX/STREX
239
+ * in RAM between the two cores, so a true SMP setup isn't supported).
240
+ *
241
+ * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
242
+ * with the default being -smp 1. This seems a more intuitive UI for
243
+ * QEMU users than, for instance, having a machine property to allow
244
+ * the user to set the initial value of the SYSCON 0x000 register.
245
+ */
246
+ mc->default_cpus = 1;
247
+ mc->min_cpus = 1;
248
+ mc->max_cpus = 2;
249
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
250
mc->valid_cpu_types = valid_cpu_types;
251
mmc->raminfo = an536_raminfo;
69
--
252
--
70
2.7.4
253
2.34.1
71
72
diff view generated by jsdifflib
1
We now test for "are we singlestepping" in several places and
1
This board has a lot of UARTs: there is one UART per CPU in the
2
it's not a trivial check because we need to care about both
2
per-CPU peripheral part of the address map, whose interrupts are
3
architectural singlestep and QEMU gdbstub singlestep. We're
3
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
4
also about to add another place that needs to make this check,
4
normal part of the peripheral space, whose interrupts are shared
5
so pull the condition out into a function.
5
peripheral interrupts.
6
7
Connect and wire them all up; this involves some OR gates where
8
multiple overflow interrupts are wired into one GIC input.
6
9
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <rth@twiddle.net>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
10
Message-id: 1491844419-12485-7-git-send-email-peter.maydell@linaro.org
11
---
13
---
12
target/arm/translate.c | 20 +++++++++++++++-----
14
hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 15 insertions(+), 5 deletions(-)
15
1 file changed, 94 insertions(+)
14
16
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
19
--- a/hw/arm/mps3r.c
18
+++ b/target/arm/translate.c
20
+++ b/hw/arm/mps3r.c
19
@@ -XXX,XX +XXX,XX @@ static void gen_singlestep_exception(DisasContext *s)
21
@@ -XXX,XX +XXX,XX @@
22
#include "qapi/qmp/qlist.h"
23
#include "exec/address-spaces.h"
24
#include "cpu.h"
25
+#include "sysemu/sysemu.h"
26
#include "hw/boards.h"
27
+#include "hw/or-irq.h"
28
#include "hw/qdev-properties.h"
29
#include "hw/arm/boot.h"
30
#include "hw/arm/bsa.h"
31
+#include "hw/char/cmsdk-apb-uart.h"
32
#include "hw/intc/arm_gicv3.h"
33
34
/* Define the layout of RAM and ROM in a board */
35
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
36
37
#define MPS3R_RAM_MAX 9
38
#define MPS3R_CPU_MAX 2
39
+#define MPS3R_UART_MAX 4 /* shared UART count */
40
41
#define PERIPHBASE 0xf0000000
42
#define NUM_SPIS 96
43
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
44
MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
45
MemoryRegion cpu_ram[MPS3R_CPU_MAX];
46
GICv3State gic;
47
+ /* per-CPU UARTs followed by the shared UARTs */
48
+ CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
49
+ OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
50
+ OrIRQState uart_oflow;
51
};
52
53
#define TYPE_MPS3R_MACHINE "mps3r"
54
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
55
56
OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
57
58
+/*
59
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
60
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
61
+ * model we just roll them all into one.
62
+ */
63
+#define CLK_FRQ 50000000
64
+
65
static const RAMInfo an536_raminfo[] = {
66
{
67
.name = "ATCM",
68
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
20
}
69
}
21
}
70
}
22
71
23
+static inline bool is_singlestepping(DisasContext *s)
72
+/*
73
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
74
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
75
+ */
76
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
77
+ hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
78
+ qemu_irq txoverirq, qemu_irq rxoverirq,
79
+ qemu_irq combirq)
24
+{
80
+{
25
+ /* Return true if we are singlestepping either because of
81
+ g_autofree char *s = g_strdup_printf("uart%d", uartno);
26
+ * architectural singlestep or QEMU gdbstub singlestep. This does
82
+ SysBusDevice *sbd;
27
+ * not include the command line '-singlestep' mode which is rather
83
+
28
+ * misnamed as it only means "one instruction per TB" and doesn't
84
+ assert(uartno < ARRAY_SIZE(mms->uart));
29
+ * affect the code we generate.
85
+ object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
30
+ */
86
+ TYPE_CMSDK_APB_UART);
31
+ return s->singlestep_enabled || s->ss_active;
87
+ qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
88
+ qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
89
+ sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
90
+ sysbus_realize(sbd, &error_fatal);
91
+ memory_region_add_subregion(mem, baseaddr,
92
+ sysbus_mmio_get_region(sbd, 0));
93
+ sysbus_connect_irq(sbd, 0, txirq);
94
+ sysbus_connect_irq(sbd, 1, rxirq);
95
+ sysbus_connect_irq(sbd, 2, txoverirq);
96
+ sysbus_connect_irq(sbd, 3, rxoverirq);
97
+ sysbus_connect_irq(sbd, 4, combirq);
32
+}
98
+}
33
+
99
+
34
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
100
static void mps3r_common_init(MachineState *machine)
35
{
101
{
36
TCGv_i32 tmp1 = tcg_temp_new_i32();
102
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
37
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
103
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
38
104
MemoryRegion *sysmem = get_system_memory();
39
static inline void gen_jmp (DisasContext *s, uint32_t dest)
105
+ DeviceState *gicdev;
40
{
106
41
- if (unlikely(s->singlestep_enabled || s->ss_active)) {
107
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
42
+ if (unlikely(is_singlestepping(s))) {
108
MemoryRegion *mr = mr_for_raminfo(mms, ri);
43
/* An indirect jump so that we still trigger the debug exception. */
109
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
44
if (s->thumb)
110
}
45
dest |= 1;
111
46
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
112
create_gic(mms, sysmem);
47
((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));
113
+ gicdev = DEVICE(&mms->gic);
48
114
+
49
} while (!dc->is_jmp && !tcg_op_buf_full() &&
115
+ /*
50
- !cs->singlestep_enabled &&
116
+ * UARTs 0 and 1 are per-CPU; their interrupts are wired to
51
+ !is_singlestepping(dc) &&
117
+ * the relevant CPU's PPI 0..3, aka INTID 16..19
52
!singlestep &&
118
+ */
53
- !dc->ss_active &&
119
+ for (int i = 0; i < machine->smp.cpus; i++) {
54
!end_of_page &&
120
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
55
num_insns < max_insns);
121
+ g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
56
122
+ DeviceState *orgate;
57
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
123
+
58
instruction was a conditional branch or trap, and the PC has
124
+ /* The two overflow IRQs from the UART are ORed together into PPI 3 */
59
already been written. */
125
+ object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
60
gen_set_condexec(dc);
126
+ TYPE_OR_IRQ);
61
- if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
127
+ orgate = DEVICE(&mms->cpu_uart_oflow[i]);
62
+ if (unlikely(is_singlestepping(dc))) {
128
+ qdev_prop_set_uint32(orgate, "num-lines", 2);
63
/* Unconditional and "condition passed" instruction codepath. */
129
+ qdev_realize(orgate, NULL, &error_fatal);
64
switch (dc->is_jmp) {
130
+ qdev_connect_gpio_out(orgate, 0,
65
case DISAS_SWI:
131
+ qdev_get_gpio_in(gicdev, intidbase + 19));
66
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
132
+
67
/* "Condition failed" instruction codepath for the branch/trap insn */
133
+ create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
68
gen_set_label(dc->condlabel);
134
+ qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
69
gen_set_condexec(dc);
135
+ qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
70
- if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
136
+ qdev_get_gpio_in(orgate, 0), /* txover */
71
+ if (unlikely(is_singlestepping(dc))) {
137
+ qdev_get_gpio_in(orgate, 1), /* rxover */
72
gen_set_pc_im(dc, dc->pc);
138
+ qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
73
gen_singlestep_exception(dc);
139
+ }
74
} else {
140
+ /*
141
+ * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
142
+ * together into IRQ 17
143
+ */
144
+ object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
145
+ &mms->uart_oflow, TYPE_OR_IRQ);
146
+ qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
147
+ MPS3R_UART_MAX * 2);
148
+ qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
149
+ qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
150
+ qdev_get_gpio_in(gicdev, 17));
151
+
152
+ for (int i = 0; i < MPS3R_UART_MAX; i++) {
153
+ hwaddr baseaddr = 0xe0205000 + i * 0x1000;
154
+ int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
155
+
156
+ create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
157
+ qdev_get_gpio_in(gicdev, txirq),
158
+ qdev_get_gpio_in(gicdev, rxirq),
159
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
160
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
161
+ qdev_get_gpio_in(gicdev, combirq));
162
+ }
163
164
mms->bootinfo.ram_size = machine->ram_size;
165
mms->bootinfo.board_id = -1;
75
--
166
--
76
2.7.4
167
2.34.1
77
168
78
169
diff view generated by jsdifflib
1
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
1
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
2
board. These are all simple devices that just need to be created and
3
wired up.
2
4
3
The arm64 boot protocol stipulates that the kernel must be loaded
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
TEXT_OFFSET bytes beyond a 2 MB aligned base address, where TEXT_OFFSET
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
could be any 4 KB multiple between 0 and 2 MB, and whose value can be
7
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
6
found in the header of the Image file.
8
---
9
hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 59 insertions(+)
7
11
8
So after attempts to load the arm64 kernel image as an ELF file or as a
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
9
U-Boot image have failed (both of which have their own way of specifying
10
the load offset), try to determine the TEXT_OFFSET from the image after
11
loading it but before mapping it as a ROM mapping into the guest address
12
space.
13
14
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 1489414630-21609-1-git-send-email-ard.biesheuvel@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
hw/arm/boot.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++----------
20
1 file changed, 53 insertions(+), 11 deletions(-)
21
22
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
23
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/boot.c
14
--- a/hw/arm/mps3r.c
25
+++ b/hw/arm/boot.c
15
+++ b/hw/arm/mps3r.c
26
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@
27
#define KERNEL_LOAD_ADDR 0x00010000
17
#include "sysemu/sysemu.h"
28
#define KERNEL64_LOAD_ADDR 0x00080000
18
#include "hw/boards.h"
29
19
#include "hw/or-irq.h"
30
+#define ARM64_TEXT_OFFSET_OFFSET 8
20
+#include "hw/qdev-clock.h"
31
+#define ARM64_MAGIC_OFFSET 56
21
#include "hw/qdev-properties.h"
22
#include "hw/arm/boot.h"
23
#include "hw/arm/bsa.h"
24
#include "hw/char/cmsdk-apb-uart.h"
25
+#include "hw/i2c/arm_sbcon_i2c.h"
26
#include "hw/intc/arm_gicv3.h"
27
+#include "hw/misc/unimp.h"
28
+#include "hw/timer/cmsdk-apb-dualtimer.h"
29
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
30
31
/* Define the layout of RAM and ROM in a board */
32
typedef struct RAMInfo {
33
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
34
CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
35
OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
36
OrIRQState uart_oflow;
37
+ CMSDKAPBWatchdog watchdog;
38
+ CMSDKAPBDualTimer dualtimer;
39
+ ArmSbconI2CState i2c[5];
40
+ Clock *clk;
41
};
42
43
#define TYPE_MPS3R_MACHINE "mps3r"
44
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
45
MemoryRegion *sysmem = get_system_memory();
46
DeviceState *gicdev;
47
48
+ mms->clk = clock_new(OBJECT(machine), "CLK");
49
+ clock_set_hz(mms->clk, CLK_FRQ);
32
+
50
+
33
typedef enum {
51
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
34
FIXUP_NONE = 0, /* do nothing */
52
MemoryRegion *mr = mr_for_raminfo(mms, ri);
35
FIXUP_TERMINATOR, /* end of insns */
53
memory_region_add_subregion(sysmem, ri->base, mr);
36
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
54
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
37
return ret;
55
qdev_get_gpio_in(gicdev, combirq));
38
}
56
}
39
57
40
+static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
58
+ for (int i = 0; i < 4; i++) {
41
+ hwaddr *entry)
59
+ /* CMSDK GPIO controllers */
42
+{
60
+ g_autofree char *s = g_strdup_printf("gpio%d", i);
43
+ hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
61
+ create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
44
+ uint8_t *buffer;
45
+ int size;
46
+
47
+ /* On aarch64, it's the bootloader's job to uncompress the kernel. */
48
+ size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
49
+ &buffer);
50
+
51
+ if (size < 0) {
52
+ gsize len;
53
+
54
+ /* Load as raw file otherwise */
55
+ if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
56
+ return -1;
57
+ }
58
+ size = len;
59
+ }
62
+ }
60
+
63
+
61
+ /* check the arm64 magic header value -- very old kernels may not have it */
64
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
62
+ if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
65
+ TYPE_CMSDK_APB_WATCHDOG);
63
+ uint64_t hdrvals[2];
66
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
67
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
68
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
69
+ qdev_get_gpio_in(gicdev, 0));
70
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
64
+
71
+
65
+ /* The arm64 Image header has text_offset and image_size fields at 8 and
72
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
66
+ * 16 bytes into the Image header, respectively. The text_offset field
73
+ TYPE_CMSDK_APB_DUALTIMER);
67
+ * is only valid if the image_size is non-zero.
74
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
68
+ */
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
69
+ memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
76
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
70
+ if (hdrvals[1] != 0) {
77
+ qdev_get_gpio_in(gicdev, 3));
71
+ kernel_load_offset = le64_to_cpu(hdrvals[0]);
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
79
+ qdev_get_gpio_in(gicdev, 1));
80
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
81
+ qdev_get_gpio_in(gicdev, 2));
82
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
83
+
84
+ for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
85
+ static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
86
+ 0xe0103000, /* Audio */
87
+ 0xe0107000, /* Shield0 */
88
+ 0xe0108000, /* Shield1 */
89
+ 0xe0109000}; /* DDR4 EEPROM */
90
+ g_autofree char *s = g_strdup_printf("i2c%d", i);
91
+
92
+ object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
93
+ TYPE_ARM_SBCON_I2C);
94
+ sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
95
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
96
+ if (i != 2 && i != 3) {
97
+ /*
98
+ * internal-only bus: mark it full to avoid user-created
99
+ * i2c devices being plugged into it.
100
+ */
101
+ qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
72
+ }
102
+ }
73
+ }
103
+ }
74
+
104
+
75
+ *entry = mem_base + kernel_load_offset;
105
mms->bootinfo.ram_size = machine->ram_size;
76
+ rom_add_blob_fixed(filename, buffer, size, *entry);
106
mms->bootinfo.board_id = -1;
77
+
107
mms->bootinfo.loader_start = mmc->loader_start;
78
+ g_free(buffer);
79
+
80
+ return size;
81
+}
82
+
83
static void arm_load_kernel_notify(Notifier *notifier, void *data)
84
{
85
CPUState *cs;
86
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
87
int is_linux = 0;
88
uint64_t elf_entry, elf_low_addr, elf_high_addr;
89
int elf_machine;
90
- hwaddr entry, kernel_load_offset;
91
+ hwaddr entry;
92
static const ARMInsnFixup *primary_loader;
93
ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier,
94
notifier, notifier);
95
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
96
97
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
98
primary_loader = bootloader_aarch64;
99
- kernel_load_offset = KERNEL64_LOAD_ADDR;
100
elf_machine = EM_AARCH64;
101
} else {
102
primary_loader = bootloader;
103
if (!info->write_board_setup) {
104
primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
105
}
106
- kernel_load_offset = KERNEL_LOAD_ADDR;
107
elf_machine = EM_ARM;
108
}
109
110
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
111
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
112
&is_linux, NULL, NULL);
113
}
114
- /* On aarch64, it's the bootloader's job to uncompress the kernel. */
115
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
116
- entry = info->loader_start + kernel_load_offset;
117
- kernel_size = load_image_gzipped(info->kernel_filename, entry,
118
- info->ram_size - kernel_load_offset);
119
+ kernel_size = load_aarch64_image(info->kernel_filename,
120
+ info->loader_start, &entry);
121
is_linux = 1;
122
- }
123
- if (kernel_size < 0) {
124
- entry = info->loader_start + kernel_load_offset;
125
+ } else if (kernel_size < 0) {
126
+ /* 32-bit ARM */
127
+ entry = info->loader_start + KERNEL_LOAD_ADDR;
128
kernel_size = load_image_targphys(info->kernel_filename, entry,
129
- info->ram_size - kernel_load_offset);
130
+ info->ram_size - KERNEL_LOAD_ADDR);
131
is_linux = 1;
132
}
133
if (kernel_size < 0) {
134
--
108
--
135
2.7.4
109
2.34.1
136
110
137
111
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
Add the remaining devices (or unimplemented-device stubs) for
2
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
3
QSPI write-config block, and ethernet.
2
4
3
This patch fixes two mistakes in the interrupt logic.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
8
---
9
hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 74 insertions(+)
4
11
5
First we only trigger single-queue or multi-queue interrupts if the status
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
6
register is set. This logic was already used for non multi-queue interrupts
7
but it also applies to multi-queue interrupts.
8
9
Secondly we need to lower the interrupts if the ISR isn't set. As part
10
of this we can remove the other interrupt lowering logic and consolidate
11
it inside gem_update_int_status().
12
13
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
14
Message-id: 438bcc014f8f8a2f8f68f322cb6a53f4c04688c2.1491947224.git.alistair.francis@xilinx.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/net/cadence_gem.c | 18 +++++++++++++-----
19
1 file changed, 13 insertions(+), 5 deletions(-)
20
21
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
22
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/net/cadence_gem.c
14
--- a/hw/arm/mps3r.c
24
+++ b/hw/net/cadence_gem.c
15
+++ b/hw/arm/mps3r.c
25
@@ -XXX,XX +XXX,XX @@ static void gem_update_int_status(CadenceGEMState *s)
16
@@ -XXX,XX +XXX,XX @@
17
#include "hw/char/cmsdk-apb-uart.h"
18
#include "hw/i2c/arm_sbcon_i2c.h"
19
#include "hw/intc/arm_gicv3.h"
20
+#include "hw/misc/mps2-scc.h"
21
+#include "hw/misc/mps2-fpgaio.h"
22
#include "hw/misc/unimp.h"
23
+#include "hw/net/lan9118.h"
24
+#include "hw/rtc/pl031.h"
25
+#include "hw/ssi/pl022.h"
26
#include "hw/timer/cmsdk-apb-dualtimer.h"
27
#include "hw/watchdog/cmsdk-apb-watchdog.h"
28
29
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
30
CMSDKAPBWatchdog watchdog;
31
CMSDKAPBDualTimer dualtimer;
32
ArmSbconI2CState i2c[5];
33
+ PL022State spi[3];
34
+ MPS2SCC scc;
35
+ MPS2FPGAIO fpgaio;
36
+ UnimplementedDeviceState i2s_audio;
37
+ PL031State rtc;
38
Clock *clk;
39
};
40
41
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
42
}
43
};
44
45
+static const int an536_oscclk[] = {
46
+ 24000000, /* 24MHz reference for RTC and timers */
47
+ 50000000, /* 50MHz ACLK */
48
+ 50000000, /* 50MHz MCLK */
49
+ 50000000, /* 50MHz GPUCLK */
50
+ 24576000, /* 24.576MHz AUDCLK */
51
+ 23750000, /* 23.75MHz HDLCDCLK */
52
+ 100000000, /* 100MHz DDR4_REF_CLK */
53
+};
54
+
55
static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
56
const RAMInfo *raminfo)
26
{
57
{
27
int i;
58
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
28
59
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
29
- if ((s->num_priority_queues == 1) && s->regs[GEM_ISR]) {
60
MemoryRegion *sysmem = get_system_memory();
30
+ if (!s->regs[GEM_ISR]) {
61
DeviceState *gicdev;
31
+ /* ISR isn't set, clear all the interrupts */
62
+ QList *oscclk;
32
+ for (i = 0; i < s->num_priority_queues; ++i) {
63
33
+ qemu_set_irq(s->irq[i], 0);
64
mms->clk = clock_new(OBJECT(machine), "CLK");
34
+ }
65
clock_set_hz(mms->clk, CLK_FRQ);
35
+ return;
66
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
67
}
68
}
69
70
+ for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
71
+ g_autofree char *s = g_strdup_printf("spi%d", i);
72
+ hwaddr baseaddr = 0xe0104000 + i * 0x1000;
73
+
74
+ object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
77
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
78
+ qdev_get_gpio_in(gicdev, 22 + i));
36
+ }
79
+ }
37
+
80
+
38
+ /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
81
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
39
+ * check it again.
82
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
83
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
84
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
85
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
86
+ oscclk = qlist_new();
87
+ for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
88
+ qlist_append_int(oscclk, an536_oscclk[i]);
89
+ }
90
+ qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
91
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
92
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
93
+
94
+ create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
95
+
96
+ object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
97
+ TYPE_MPS2_FPGAIO);
98
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
99
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
100
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
101
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
102
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
104
+
105
+ create_unimplemented_device("clcd", 0xe0209000, 0x1000);
106
+
107
+ object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
108
+ sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
109
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
110
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
111
+ qdev_get_gpio_in(gicdev, 4));
112
+
113
+ /*
114
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
115
+ * except that it doesn't support the checksum-offload feature.
40
+ */
116
+ */
41
+ if (s->num_priority_queues == 1) {
117
+ lan9118_init(0xe0300000,
42
/* No priority queues, just trigger the interrupt */
118
+ qdev_get_gpio_in(gicdev, 18));
43
DB_PRINT("asserting int.\n");
119
+
44
qemu_set_irq(s->irq[0], 1);
120
+ create_unimplemented_device("usb", 0xe0301000, 0x1000);
45
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
121
+ create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
46
{
122
+
47
CadenceGEMState *s;
123
mms->bootinfo.ram_size = machine->ram_size;
48
uint32_t retval;
124
mms->bootinfo.board_id = -1;
49
- int i;
125
mms->bootinfo.loader_start = mmc->loader_start;
50
s = (CadenceGEMState *)opaque;
51
52
offset >>= 2;
53
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
54
switch (offset) {
55
case GEM_ISR:
56
DB_PRINT("lowering irqs on ISR read\n");
57
- for (i = 0; i < s->num_priority_queues; ++i) {
58
- qemu_set_irq(s->irq[i], 0);
59
- }
60
+ /* The interrupts get updated at the end of the function. */
61
break;
62
case GEM_PHYMNTNC:
63
if (retval & GEM_PHYMNTNC_OP_R) {
64
--
126
--
65
2.7.4
127
2.34.1
66
128
67
129
diff view generated by jsdifflib
1
In tlb_fill() we construct a syndrome register value from a
1
Add documentation for the mps3-an536 board type.
2
fault status register value which is filled in by arm_tlb_fill().
3
arm_tlb_fill() returns FSR values which might be in the format
4
used with short-format page descriptors, or the format used
5
with long-format (LPAE) descriptors. The syndrome register
6
always uses LPAE-format FSR status codes.
7
8
It isn't actually possible to end up delivering a syndrome
9
register value to the guest for a fault which is reported
10
with a short-format FSR (that kind of stage 1 fault will only
11
happen for an AArch32 translation regime which doesn't have
12
a syndrome register, and can never be redirected to an AArch64
13
or Hyp exception level). Add an assertion which checks this,
14
and adjust the code so that we construct a syndrome with
15
an invalid status code, rather than allowing set bits in
16
the FSR input to randomly corrupt other fields in the syndrome.
17
2
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
20
Message-id: 1491486152-24304-1-git-send-email-peter.maydell@linaro.org
5
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
21
---
6
---
22
target/arm/op_helper.c | 23 ++++++++++++++++++-----
7
docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
23
1 file changed, 18 insertions(+), 5 deletions(-)
8
1 file changed, 34 insertions(+), 3 deletions(-)
24
9
25
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
10
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
26
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/op_helper.c
12
--- a/docs/system/arm/mps2.rst
28
+++ b/target/arm/op_helper.c
13
+++ b/docs/system/arm/mps2.rst
29
@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
14
@@ -XXX,XX +XXX,XX @@
30
if (unlikely(ret)) {
15
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
31
ARMCPU *cpu = ARM_CPU(cs);
16
-=========================================================================================================================================================
32
CPUARMState *env = &cpu->env;
17
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
33
- uint32_t syn, exc;
18
+=========================================================================================================================================================================
34
+ uint32_t syn, exc, fsc;
19
35
unsigned int target_el;
20
-These board models all use Arm M-profile CPUs.
36
bool same_el;
21
+These board models use Arm M-profile or R-profile CPUs.
37
22
38
@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
23
The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
39
env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
24
bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
40
}
25
@@ -XXX,XX +XXX,XX @@ FPGA image.
41
same_el = arm_current_el(env) == target_el;
26
42
- /* AArch64 syndrome does not have an LPAE bit */
27
QEMU models the following FPGA images:
43
- syn = fsr & ~(1 << 9);
28
29
+FPGA images using M-profile CPUs:
44
+
30
+
45
+ if (fsr & (1 << 9)) {
31
``mps2-an385``
46
+ /* LPAE format fault status register : bottom 6 bits are
32
Cortex-M3 as documented in Arm Application Note AN385
47
+ * status code in the same form as needed for syndrome
33
``mps2-an386``
48
+ */
34
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
49
+ fsc = extract32(fsr, 0, 6);
35
``mps3-an547``
50
+ } else {
36
Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
51
+ /* Short format FSR : this fault will never actually be reported
37
52
+ * to an EL that uses a syndrome register. Check that here,
38
+FPGA images using R-profile CPUs:
53
+ * and use a (currently) reserved FSR code in case the constructed
39
+
54
+ * syndrome does leak into the guest somehow.
40
+``mps3-an536``
55
+ */
41
+ Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
56
+ assert(target_el != 2 && !arm_el_is_aa64(env, target_el));
42
+
57
+ fsc = 0x3f;
43
Differences between QEMU and real hardware:
58
+ }
44
59
45
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
60
/* For insn and data aborts we assume there is no instruction syndrome
46
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
61
* information; this is always true for exceptions reported to EL1.
47
flash, but only as simple ROM, so attempting to rewrite the flash
62
*/
48
from the guest will fail
63
if (access_type == MMU_INST_FETCH) {
49
- QEMU does not model the USB controller in MPS3 boards
64
- syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
50
+- AN536 does not support runtime control of CPU reset and halt via
65
+ syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc);
51
+ the SCC CFG_REG0 register.
66
exc = EXCP_PREFETCH_ABORT;
52
+- AN536 does not support enabling or disabling the flash and ATCM
67
} else {
53
+ interfaces via the SCC CFG_REG1 register.
68
syn = merge_syn_data_abort(env->exception.syndrome, target_el,
54
+- AN536 does not support setting of the initial vector table
69
same_el, fi.s1ptw,
55
+ base address via the SCC CFG_REG6 and CFG_REG7 register config,
70
- access_type == MMU_DATA_STORE, syn);
56
+ and does not provide a mechanism for specifying these values at
71
+ access_type == MMU_DATA_STORE, fsc);
57
+ startup, so all guest images must be built to start from TCM
72
if (access_type == MMU_DATA_STORE
58
+ (i.e. to expect the interrupt vector base at 0 from reset).
73
&& arm_feature(env, ARM_FEATURE_V6)) {
59
+- AN536 defaults to only creating a single CPU; this is the equivalent
74
fsr |= (1 << 11);
60
+ of the way the real FPGA image usually runs with the second Cortex-R52
61
+ held in halt via the initial SCC CFG_REG0 register setting. You can
62
+ create the second CPU with ``-smp 2``; both CPUs will then start
63
+ execution immediately on startup.
64
+
65
+Note that for the AN536 the first UART is accessible only by
66
+CPU0, and the second UART is accessible only by CPU1. The
67
+first UART accessible shared between both CPUs is the third
68
+UART. Guest software might therefore be built to use either
69
+the first UART or the third UART; if you don't see any output
70
+from the UART you are looking at, try one of the others.
71
+(Even if the AN536 machine is started with a single CPU and so
72
+no "CPU1-only UART", the UART numbering remains the same,
73
+with the third UART being the first of the shared ones.)
74
75
Machine-specific options
76
""""""""""""""""""""""""
75
--
77
--
76
2.7.4
78
2.34.1
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