Series comparison

-[Qemu-devel] [PULL 00/24] target-arm queue
+[PULL 0/8] target-arm queue
-First ARM pullreq of the 2.10 cycle...
+Handful of bugfixes for rc2. None of these are particularly critical
 or exciting.
-thanks
 -- PMM
-The following changes since commit 64c8ed97cceabac4fafe17fca8d88ef08183f439:
+The following changes since commit 45a150aa2b3492acf6691c7bdbeb25a8545d8345:
-  Open 2.10 development tree (2017-04-20 15:42:31 +0100)
+  Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' into staging (2020-08-03 15:13:49 +0100)
-are available in the git repository at:
+are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170420
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200803
-for you to fetch changes up to f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa:
+for you to fetch changes up to 13557fd392890cbd985bceba7f717e01efd674b8:
-  arm: Remove workarounds for old M-profile exception return implementation (2017-04-20 17:39:17 +0100)
+  hw/timer/imx_epit: Avoid assertion when CR.SWR is written (2020-08-03 17:56:11 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * implement M profile exception return properly
+ * hw/timer/imx_epit: Avoid assertion when CR.SWR is written
- * cadence GEM: fix multiqueue handling bugs
+ * netduino2, netduinoplus2, microbit: set system_clock_scale so that
- * pxa2xx.c: QOMify a device
+   SysTick running on the CPU clock works
- * arm/kvm: Remove trailing newlines from error_report()
+ * target/arm: Avoid maybe-uninitialized warning with gcc 4.9
- * stellaris: Don't hw_error() on bad register accesses
+ * target/arm: Fix AddPAC error indication
- * Add assertion about FSC format for syndrome registers
+ * Make AIRCR.SYSRESETREQ actually reset the system for the
- * Move excnames[] array into arm_log_exceptions()
+   microbit, mps2-*, musca-*, netduino* boards
  * exynos: minor code cleanups
  * hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
  * Fix APSR writes via M profile MSR
 ----------------------------------------------------------------
-Alistair Francis (5):
+Kaige Li (1):
-      cadence_gem: Read the correct queue descriptor
+      target/arm: Avoid maybe-uninitialized warning with gcc 4.9
       cadence_gem: Correct the multi-queue can rx logic
       cadence_gem: Correct the interupt logic
       cadence_gem: Make the revision a property
       xlnx-zynqmp: Set the Cadence GEM revision
-Ard Biesheuvel (1):
+Peter Maydell (6):
-      hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
+      hw/arm/netduino2, netduinoplus2: Set system_clock_scale
       include/hw/irq.h: New function qemu_irq_is_connected()
       hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
       msf2-soc, stellaris: Don't wire up SYSRESETREQ
       hw/arm/nrf51_soc: Set system_clock_scale
       hw/timer/imx_epit: Avoid assertion when CR.SWR is written
-Ishani Chugh (1):
+Richard Henderson (1):
-      arm/kvm: Remove trailing newlines from error_report()
+      target/arm: Fix AddPAC error indication
-Krzysztof Kozlowski (3):
+ include/hw/arm/armv7m.h           |  4 +++-
-      hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
+ include/hw/irq.h                  | 18 ++++++++++++++++++
-      hw/char/exynos4210_uart: Constify static array and few arguments
+ hw/arm/msf2-soc.c                 | 11 -----------
-      hw/misc/exynos4210_pmu: Reorder local variables for readability
+ hw/arm/netduino2.c                | 10 ++++++++++
  hw/arm/netduinoplus2.c            | 10 ++++++++++
  hw/arm/nrf51_soc.c                |  5 +++++
  hw/arm/stellaris.c                | 12 ------------
  hw/intc/armv7m_nvic.c             | 17 ++++++++++++++++-
  hw/timer/imx_epit.c               | 13 ++++++++++---
  target/arm/pauth_helper.c         |  6 +++++-
  target/arm/translate-a64.c        |  2 +-
  tests/tcg/aarch64/pauth-5.c       | 33 +++++++++++++++++++++++++++++++++
  tests/tcg/aarch64/Makefile.target |  2 +-
 files changed, 112 insertions(+), 31 deletions(-)
  create mode 100644 tests/tcg/aarch64/pauth-5.c
-Peter Maydell (13):
-      target/arm: Add missing entries to excnames[] for log strings
-      arm: Move excnames[] array into arm_log_exceptions()
-      target/arm: Add assertion about FSC format for syndrome registers
-      stellaris: Don't hw_error() on bad register accesses
-      arm: Don't implement BXJ on M-profile CPUs
-      arm: Thumb shift operations should not permit interworking branches
-      arm: Factor out "generate right kind of step exception"
-      arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
-      arm: Move condition-failed codepath generation out of if()
-      arm: Abstract out "are we singlestepping" test to utility function
-      arm: Track M profile handler mode state in TB flags
-      arm: Implement M profile exception return properly
-      arm: Remove workarounds for old M-profile exception return implementation
-Suramya Shah (1):
-      hw/arm: Qomify pxa2xx.c
- include/hw/net/cadence_gem.h |   1 +
- target/arm/cpu.h             |  10 +++
- target/arm/internals.h       |  21 -----
- target/arm/translate.h       |   5 ++
- hw/arm/boot.c                |  64 ++++++++++++---
- hw/arm/exynos4_boards.c      |   7 +-
- hw/arm/pxa2xx.c              |  14 ++--
- hw/arm/stellaris.c           |  60 ++++++++------
- hw/arm/xlnx-zynqmp.c         |   6 +-
- hw/char/exynos4210_uart.c    |   8 +-
- hw/misc/exynos4210_pmu.c     |   4 +-
- hw/net/cadence_gem.c         |  45 +++++++----
- hw/timer/exynos4210_mct.c    |   6 +-
- hw/timer/exynos4210_pwm.c    |  13 ++--
- hw/timer/exynos4210_rtc.c    |  19 ++---
- target/arm/cpu.c             |  43 +---------
- target/arm/helper.c          |  19 +++++
- target/arm/kvm64.c           |   4 +-
- target/arm/op_helper.c       |  23 ++++--
- target/arm/translate.c       | 181 +++++++++++++++++++++++++++++--------------
-files changed, 341 insertions(+), 212 deletions(-)

-[Qemu-devel] [PULL 01/24] hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
+Deleted patch
-From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-The arm64 boot protocol stipulates that the kernel must be loaded
-TEXT_OFFSET bytes beyond a 2 MB aligned base address, where TEXT_OFFSET
-could be any 4 KB multiple between 0 and 2 MB, and whose value can be
-found in the header of the Image file.
-So after attempts to load the arm64 kernel image as an ELF file or as a
-U-Boot image have failed (both of which have their own way of specifying
-the load offset), try to determine the TEXT_OFFSET from the image after
-loading it but before mapping it as a ROM mapping into the guest address
-space.
-Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1489414630-21609-1-git-send-email-ard.biesheuvel@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/boot.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++----------
-file changed, 53 insertions(+), 11 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
-+++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@
- #define KERNEL_LOAD_ADDR 0x00010000
- #define KERNEL64_LOAD_ADDR 0x00080000
-+#define ARM64_TEXT_OFFSET_OFFSET    8
-+#define ARM64_MAGIC_OFFSET          56
-+
- typedef enum {
-     FIXUP_NONE = 0,     /* do nothing */
-     FIXUP_TERMINATOR,   /* end of insns */
-@@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
-     return ret;
- }
-+static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
-+                                   hwaddr *entry)
-+{
-+    hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
-+    uint8_t *buffer;
-+    int size;
-+
-+    /* On aarch64, it's the bootloader's job to uncompress the kernel. */
-+    size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
-+                                     &buffer);
-+
-+    if (size < 0) {
-+        gsize len;
-+
-+        /* Load as raw file otherwise */
-+        if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
-+            return -1;
-+        }
-+        size = len;
-+    }
-+
-+    /* check the arm64 magic header value -- very old kernels may not have it */
-+    if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
-+        uint64_t hdrvals[2];
-+
-+        /* The arm64 Image header has text_offset and image_size fields at 8 and
-+         * 16 bytes into the Image header, respectively. The text_offset field
-+         * is only valid if the image_size is non-zero.
-+         */
-+        memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
-+        if (hdrvals[1] != 0) {
-+            kernel_load_offset = le64_to_cpu(hdrvals[0]);
-+        }
-+    }
-+
-+    *entry = mem_base + kernel_load_offset;
-+    rom_add_blob_fixed(filename, buffer, size, *entry);
-+
-+    g_free(buffer);
-+
-+    return size;
-+}
-+
- static void arm_load_kernel_notify(Notifier *notifier, void *data)
- {
-     CPUState *cs;
-@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
-     int is_linux = 0;
-     uint64_t elf_entry, elf_low_addr, elf_high_addr;
-     int elf_machine;
--    hwaddr entry, kernel_load_offset;
-+    hwaddr entry;
-     static const ARMInsnFixup *primary_loader;
-     ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier,
-                                          notifier, notifier);
-@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
-     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-         primary_loader = bootloader_aarch64;
--        kernel_load_offset = KERNEL64_LOAD_ADDR;
-         elf_machine = EM_AARCH64;
-     } else {
-         primary_loader = bootloader;
-         if (!info->write_board_setup) {
-             primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
-         }
--        kernel_load_offset = KERNEL_LOAD_ADDR;
-         elf_machine = EM_ARM;
-     }
-@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
-         kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
-                                   &is_linux, NULL, NULL);
-     }
--    /* On aarch64, it's the bootloader's job to uncompress the kernel. */
-     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
--        entry = info->loader_start + kernel_load_offset;
--        kernel_size = load_image_gzipped(info->kernel_filename, entry,
--                                         info->ram_size - kernel_load_offset);
-+        kernel_size = load_aarch64_image(info->kernel_filename,
-+                                         info->loader_start, &entry);
-         is_linux = 1;
--    }
--    if (kernel_size < 0) {
--        entry = info->loader_start + kernel_load_offset;
-+    } else if (kernel_size < 0) {
-+        /* 32-bit ARM */
-+        entry = info->loader_start + KERNEL_LOAD_ADDR;
-         kernel_size = load_image_targphys(info->kernel_filename, entry,
--                                          info->ram_size - kernel_load_offset);
-+                                          info->ram_size - KERNEL_LOAD_ADDR);
-         is_linux = 1;
-     }
-     if (kernel_size < 0) {
---
-.7.4

-[Qemu-devel] [PULL 24/24] arm: Remove workarounds for old M-profile exception return implementation
+[PULL 1/8] hw/arm/netduino2, netduinoplus2: Set system_clock_scale
-Now that we've rewritten M-profile exception return so that the magic
+The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
-PC values are not visible to other parts of QEMU, we can delete the
+global, which meant that if guest code used the systick timer in "use
-special casing of them elsewhere.
+the processor clock" mode it would hang because time never advances.
+Set the global to match the documented CPU clock speed of these boards.
+Judging by the data sheet this is slightly simplistic because the
+SoC allows configuration of the SYSCLK source and frequency via the
+RCC (reset and clock control) module, but we don't model that.
+Fixes: https://bugs.launchpad.net/qemu/+bug/1876187
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
+Message-id: 20200727162617.26227-1-peter.maydell@linaro.org
 Message-id: 1491844419-12485-10-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/cpu.c       | 43 ++-----------------------------------------
+ hw/arm/netduino2.c     | 10 ++++++++++
- target/arm/translate.c |  8 --------
+ hw/arm/netduinoplus2.c | 10 ++++++++++
-files changed, 2 insertions(+), 49 deletions(-)
+files changed, 20 insertions(+)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/hw/arm/netduino2.c
-+++ b/target/arm/cpu.c
++++ b/hw/arm/netduino2.c
-@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+@@ -XXX,XX +XXX,XX @@
- }
+ #include "hw/arm/stm32f205_soc.h"
+ #include "hw/arm/boot.h"
- #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
--static void arm_v7m_unassigned_access(CPUState *cpu, hwaddr addr,
++/* Main SYSCLK frequency in Hz (120MHz) */
--                                      bool is_write, bool is_exec, int opaque,
++#define SYSCLK_FRQ 120000000ULL
--                                      unsigned size)
++
--{
+ static void netduino2_init(MachineState *machine)
 -    ARMCPU *arm = ARM_CPU(cpu);
 -    CPUARMState *env = &arm->env;
 -
 -    /* ARMv7-M interrupt return works by loading a magic value into the PC.
 -     * On real hardware the load causes the return to occur.  The qemu
 -     * implementation performs the jump normally, then does the exception
 -     * return by throwing a special exception when when the CPU tries to
 -     * execute code at the magic address.
 -     */
 -    if (env->v7m.exception != 0 && addr >= 0xfffffff0 && is_exec) {
 -        cpu->exception_index = EXCP_EXCEPTION_EXIT;
 -        cpu_loop_exit(cpu);
 -    }
 -
 -    /* In real hardware an attempt to access parts of the address space
 -     * with nothing there will usually cause an external abort.
 -     * However our QEMU board models are often missing device models where
 -     * the guest can boot anyway with the default read-as-zero/writes-ignored
 -     * behaviour that you get without a QEMU unassigned_access hook.
 -     * So just return here to retain that default behaviour.
 -     */
 -}
 -
  static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  {
-     CPUClass *cc = CPU_GET_CLASS(cs);
+     DeviceState *dev;
-@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-     CPUARMState *env = &cpu->env;
++    /*
-     bool ret = false;
++     * TODO: ideally we would model the SoC RCC and let it handle
++     * system_clock_scale, including its ability to define different
--    /* ARMv7-M interrupt return works by loading a magic value
++     * possible SYSCLK sources.
--     * into the PC.  On real hardware the load causes the
++     */
--     * return to occur.  The qemu implementation performs the
++    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
--     * jump normally, then does the exception return when the
++
--     * CPU tries to execute code at the magic address.
+     dev = qdev_new(TYPE_STM32F205_SOC);
--     * This will cause the magic PC value to be pushed to
+     qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
--     * the stack if an interrupt occurred at the wrong time.
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
--     * We avoid this by disabling interrupts when
+diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
 -     * pc contains a magic address.
 -     *
 -     * ARMv7-M interrupt masking works differently than -A or -R.
 +    /* ARMv7-M interrupt masking works differently than -A or -R.
       * There is no FIQ/IRQ distinction. Instead of I and F bits
       * masking FIQ and IRQ interrupts, an exception is taken only
       * if it is higher priority than the current execution priority
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
       * currently active exception).
       */
      if (interrupt_request & CPU_INTERRUPT_HARD
 -        && (armv7m_nvic_can_take_pending_exception(env->nvic))
 -        && (env->regs[15] < 0xfffffff0)) {
 +        && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
          cs->exception_index = EXCP_IRQ;
          cc->do_interrupt(cs);
          ret = true;
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
      cc->do_interrupt = arm_v7m_cpu_do_interrupt;
  #endif
 -    cc->do_unassigned_access = arm_v7m_unassigned_access;
      cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
  }
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/hw/arm/netduinoplus2.c
-+++ b/target/arm/translate.c
++++ b/hw/arm/netduinoplus2.c
-@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
+@@ -XXX,XX +XXX,XX @@
-             dc->is_jmp = DISAS_EXC;
+ #include "hw/arm/stm32f405_soc.h"
-             break;
+ #include "hw/arm/boot.h"
-         }
--#else
++/* Main SYSCLK frequency in Hz (168MHz) */
--        if (arm_dc_feature(dc, ARM_FEATURE_M)) {
++#define SYSCLK_FRQ 168000000ULL
--            /* Branches to the magic exception-return addresses should
++
--             * already have been caught via the arm_v7m_unassigned_access hook,
+ static void netduinoplus2_init(MachineState *machine)
--             * and never get here.
+ {
--             */
+     DeviceState *dev;
--            assert(dc->pc < 0xfffffff0);
--        }
++    /*
- #endif
++     * TODO: ideally we would model the SoC RCC and let it handle
++     * system_clock_scale, including its ability to define different
-         if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
++     * possible SYSCLK sources.
 +     */
 +    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
 +
      dev = qdev_new(TYPE_STM32F405_SOC);
      qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 18/24] arm: Factor out "generate right kind of step exception"
+[PULL 2/8] include/hw/irq.h: New function qemu_irq_is_connected()
-We currently have two places that do:
+Mostly devices don't need to care whether one of their output
-            if (dc->ss_active) {
+qemu_irq lines is connected, because functions like qemu_set_irq()
-                gen_step_complete_exception(dc);
+silently do nothing if there is nothing on the other end.  However
-            } else {
+sometimes a device might want to implement default behaviour for the
-                gen_exception_internal(EXCP_DEBUG);
+case where the machine hasn't wired the line up to anywhere.
             }
-Factor this out into its own function, as we're about to add
+Provide a function qemu_irq_is_connected() that devices can use for
-a third place that needs the same logic.
+this purpose.  (The test is trivial but encapsulating it in a
 function makes it easier to see where we're doing it in case we need
 to change the implementation later.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1491844419-12485-4-git-send-email-peter.maydell@linaro.org
+Message-id: 20200728103744.6909-2-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 28 ++++++++++++++++------------
+ include/hw/irq.h | 18 ++++++++++++++++++
-file changed, 16 insertions(+), 12 deletions(-)
+file changed, 18 insertions(+)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/hw/irq.h b/include/hw/irq.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/hw/irq.h
-+++ b/target/arm/translate.c
++++ b/include/hw/irq.h
-@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
-     s->is_jmp = DISAS_EXC;
+    on an existing vector of qemu_irq.  */
- }
+ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
-+static void gen_singlestep_exception(DisasContext *s)
++/**
 + * qemu_irq_is_connected: Return true if IRQ line is wired up
 + *
 + * If a qemu_irq has a device on the other (receiving) end of it,
 + * return true; otherwise return false.
 + *
 + * Usually device models don't need to care whether the machine model
 + * has wired up their outbound qemu_irq lines, because functions like
 + * qemu_set_irq() silently do nothing if there is nothing on the other
 + * end of the line. However occasionally a device model will want to
 + * provide default behaviour if its output is left floating, and
 + * it can use this function to identify when that is the case.
 + */
 +static inline bool qemu_irq_is_connected(qemu_irq irq)
 +{
-+    /* Generate the right kind of exception for singlestep, which is
++    return irq != NULL;
 +     * either the architectural singlestep or EXCP_DEBUG for QEMU's
 +     * gdb singlestepping.
 +     */
 +    if (s->ss_active) {
 +        gen_step_complete_exception(s);
 +    } else {
 +        gen_exception_internal(EXCP_DEBUG);
 +    }
 +}
 +
- static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
+ #endif
  {
      TCGv_i32 tmp1 = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
              gen_set_pc_im(dc, dc->pc);
              /* fall through */
          default:
 -            if (dc->ss_active) {
 -                gen_step_complete_exception(dc);
 -            } else {
 -                /* FIXME: Single stepping a WFI insn will not halt
 -                   the CPU.  */
 -                gen_exception_internal(EXCP_DEBUG);
 -            }
 +            /* FIXME: Single stepping a WFI insn will not halt the CPU. */
 +            gen_singlestep_exception(dc);
          }
          if (dc->condjmp) {
              /* "Condition failed" instruction codepath. */
              gen_set_label(dc->condlabel);
              gen_set_condexec(dc);
              gen_set_pc_im(dc, dc->pc);
 -            if (dc->ss_active) {
 -                gen_step_complete_exception(dc);
 -            } else {
 -                gen_exception_internal(EXCP_DEBUG);
 -            }
 +            gen_singlestep_exception(dc);
          }
      } else {
          /* While branches must always occur at the end of an IT block,
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 19/24] arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
+[PULL 3/8] hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
-Move the utility routines gen_set_condexec() and gen_set_pc_im()
+The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals
-up in the file, as we will want to use them from a function
+when the guest sets the SYSRESETREQ bit in the AIRCR register.  This
-placed earlier in the file than their current location.
+matches the hardware design (where the CPU has a signal of this name
 and it is up to the SoC to connect that up to an actual reset
 mechanism), but in QEMU it mostly results in duplicated code in SoC
 objects and bugs where SoC model implementors forget to wire up the
 SYSRESETREQ line.
 Provide a default behaviour for the case where SYSRESETREQ is not
 actually connected to anything: use qemu_system_reset_request() to
 perform a system reset.  This will allow us to remove the
 implementations of SYSRESETREQ handling from the boards where that's
 exactly what it does, and also fixes the bugs in the board models
 which forgot to wire up the signal:
  * microbit
  * mps2-an385
  * mps2-an505
  * mps2-an511
  * mps2-an521
  * musca-a
  * musca-b1
  * netduino
  * netduinoplus2
 We still allow the board to wire up the signal if it needs to, in case
 we need to model more complicated reset controller logic or to model
 buggy SoC hardware which forgot to wire up the line itself. But
 defaulting to "reset the system" is more often going to be correct
 than defaulting to "do nothing".
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1491844419-12485-5-git-send-email-peter.maydell@linaro.org
+Message-id: 20200728103744.6909-3-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 31 +++++++++++++++----------------
+ include/hw/arm/armv7m.h |  4 +++-
-file changed, 15 insertions(+), 16 deletions(-)
+ hw/intc/armv7m_nvic.c   | 17 ++++++++++++++++-
 files changed, 19 insertions(+), 2 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/hw/arm/armv7m.h
-+++ b/target/arm/translate.c
++++ b/include/hw/arm/armv7m.h
-@@ -XXX,XX +XXX,XX @@ static const uint8_t table_logic_cc[16] = {
+@@ -XXX,XX +XXX,XX @@ typedef struct {
-, /* mvn */
  /* ARMv7M container object.
   * + Unnamed GPIO input lines: external IRQ lines for the NVIC
 - * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
 + * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
 + *   If this GPIO is not wired up then the NVIC will default to performing
 + *   a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
   * + Property "cpu-type": CPU type to instantiate
   * + Property "num-irq": number of external IRQ lines
   * + Property "memory": MemoryRegion defining the physical address space
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/intc/armv7m_nvic.h"
  #include "hw/irq.h"
  #include "hw/qdev-properties.h"
 +#include "sysemu/runstate.h"
  #include "target/arm/cpu.h"
  #include "exec/exec-all.h"
  #include "exec/memop.h"
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
 x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
  };
-+static inline void gen_set_condexec(DisasContext *s)
++static void signal_sysresetreq(NVICState *s)
 +{
-+    if (s->condexec_mask) {
++    if (qemu_irq_is_connected(s->sysresetreq)) {
-+        uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
++        qemu_irq_pulse(s->sysresetreq);
-+        TCGv_i32 tmp = tcg_temp_new_i32();
++    } else {
-+        tcg_gen_movi_i32(tmp, val);
++        /*
-+        store_cpu_field(tmp, condexec_bits);
++         * Default behaviour if the SoC doesn't need to wire up
 +         * SYSRESETREQ (eg to a system reset controller of some kind):
 +         * perform a system reset via the usual QEMU API.
 +         */
 +        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 +    }
 +}
 +
-+static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
+ static int nvic_pending_prio(NVICState *s)
 +{
 +    tcg_gen_movi_i32(cpu_R[15], val);
 +}
 +
  /* Set PC and Thumb state from an immediate address.  */
  static inline void gen_bx_im(DisasContext *s, uint32_t addr)
  {
-@@ -XXX,XX +XXX,XX @@ DO_GEN_ST(8, MO_UB)
+     /* return the group priority of the current pending interrupt,
- DO_GEN_ST(16, MO_UW)
+@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
- DO_GEN_ST(32, MO_UL)
+             if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
+                 if (attrs.secure ||
--static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
+                     !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
--{
+-                    qemu_irq_pulse(s->sysresetreq);
--    tcg_gen_movi_i32(cpu_R[15], val);
++                    signal_sysresetreq(s);
--}
+                 }
--
+             }
- static inline void gen_hvc(DisasContext *s, int imm16)
+             if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
  {
      /* The pre HVC helper handles cases when HVC gets trapped
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
      s->is_jmp = DISAS_SMC;
  }
 -static inline void
 -gen_set_condexec (DisasContext *s)
 -{
 -    if (s->condexec_mask) {
 -        uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
 -        TCGv_i32 tmp = tcg_temp_new_i32();
 -        tcg_gen_movi_i32(tmp, val);
 -        store_cpu_field(tmp, condexec_bits);
 -    }
 -}
 -
  static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
  {
      gen_set_condexec(s);
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 08/24] stellaris: Don't hw_error() on bad register accesses
+[PULL 4/8] msf2-soc, stellaris: Don't wire up SYSRESETREQ
-Current recommended style is to log a guest error on bad register
+The MSF2 SoC model and the Stellaris board code both wire
-accesses, not kill the whole system with hw_error().  Change the
+SYSRESETREQ up to a function that just invokes
-hw_error() calls to log as LOG_GUEST_ERROR or LOG_UNIMP or use
+    qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-g_assert_not_reached() as appropriate.
+This is now the default action that the NVIC does if the line is
 not connected, so we can delete the handling code.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1491486314-25823-1-git-send-email-peter.maydell@linaro.org
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20200728103744.6909-4-peter.maydell@linaro.org
 ---
- hw/arm/stellaris.c | 60 +++++++++++++++++++++++++++++++++---------------------
+ hw/arm/msf2-soc.c  | 11 -----------
-file changed, 37 insertions(+), 23 deletions(-)
+ hw/arm/stellaris.c | 12 ------------
 files changed, 23 deletions(-)
+diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/msf2-soc.c
++++ b/hw/arm/msf2-soc.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/irq.h"
+ #include "hw/arm/msf2-soc.h"
+ #include "hw/misc/unimp.h"
+-#include "sysemu/runstate.h"
+ #include "sysemu/sysemu.h"
+ #define MSF2_TIMER_BASE       0x40004000
+@@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
+ static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
+ static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
+-static void do_sys_reset(void *opaque, int n, int level)
+-{
+-    if (level) {
+-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+-    }
+-}
+-
+ static void m2sxxx_soc_initfn(Object *obj)
+ {
+     MSF2State *s = MSF2_SOC(obj);
+@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
+         return;
+     }
+-    qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
+-                                qemu_allocate_irq(&do_sys_reset, NULL, 0));
+-
+     system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
+     for (i = 0; i < MSF2_NUM_UARTS; i++) {
 diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/stellaris.c
 +++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@ static void gptm_reload(gptm_state *s, int n, int reset)
+@@ -XXX,XX +XXX,XX @@
-     } else if (s->mode[n] == 0xa) {
+ #include "hw/boards.h"
-         /* PWM mode.  Not implemented.  */
+ #include "qemu/log.h"
-     } else {
+ #include "exec/address-spaces.h"
--        hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
+-#include "sysemu/runstate.h"
-+        qemu_log_mask(LOG_UNIMP,
+ #include "sysemu/sysemu.h"
-+                      "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
+ #include "hw/arm/armv7m.h"
-+                      s->mode[n]);
+ #include "hw/char/pl011.h"
-+        return;
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
-     }
+     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
      s->tick[n] = tick;
      timer_mod(s->timer[n], tick);
@@ -XXX,XX +XXX,XX @@ static void gptm_tick(void *opaque)
      } else if (s->mode[n] == 0xa) {
          /* PWM mode.  Not implemented.  */
      } else {
 -        hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 +        qemu_log_mask(LOG_UNIMP,
 +                      "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 +                      s->mode[n]);
      }
      gptm_update_irq(s);
  }
-@@ -XXX,XX +XXX,XX @@ static void gptm_write(void *opaque, hwaddr offset,
-         s->match_prescale[0] = value;
+-static
-         break;
+-void do_sys_reset(void *opaque, int n, int level)
-     default:
+-{
--        hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
+-    if (level) {
-+        qemu_log_mask(LOG_GUEST_ERROR,
+-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-+                      "GPTM: read at bad offset 0x%x\n", (int)offset);
+-    }
-     }
+-}
-     gptm_update_irq(s);
+-
- }
+ /* Board init.  */
-@@ -XXX,XX +XXX,XX @@ static int ssys_board_class(const ssys_state *s)
+ static stellaris_board_info stellaris_boards[] = {
-         }
+   { "LM3S811EVB",
-         /* for unknown classes, fall through */
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-     default:
+     /* This will exit with an error if the user passed us a bad cpu_type */
--        hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
-+        /* This can only happen if the hardwired constant did0 value
-+         * in this board's stellaris_board_info struct is wrong.
+-    qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
-+         */
+-                                qemu_allocate_irq(&do_sys_reset, NULL, 0));
-+        g_assert_not_reached();
+-
-     }
+     if (board->dc1 & (1 << 16)) {
- }
+         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
+                                     qdev_get_gpio_in(nvic, 14),
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
              case DID0_CLASS_SANDSTORM:
                  return pllcfg_sandstorm[xtal];
              default:
 -                hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
 -                return 0;
 +                g_assert_not_reached();
              }
          }
      case 0x070: /* RCC2 */
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
      case 0x1e4: /* USER1 */
          return s->user1;
      default:
 -        hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSYS: read at bad offset 0x%x\n", (int)offset);
          return 0;
      }
  }
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
          s->ldoarst = value;
          break;
      default:
 -        hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSYS: write at bad offset 0x%x\n", (int)offset);
      }
      ssys_update(s);
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
      case 0x20: /* MCR */
          return s->mcr;
      default:
 -        hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
          return 0;
      }
  }
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
          s->mris &= ~value;
          break;
      case 0x20: /* MCR */
 -        if (value & 1)
 -            hw_error(
 -                      "stellaris_i2c_write: Loopback not implemented\n");
 -        if (value & 0x20)
 -            hw_error(
 -                      "stellaris_i2c_write: Slave mode not implemented\n");
 +        if (value & 1) {
 +            qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
 +        }
 +        if (value & 0x20) {
 +            qemu_log_mask(LOG_UNIMP,
 +                          "stellaris_i2c: Slave mode not implemented");
 +        }
          s->mcr = value & 0x31;
          break;
      default:
 -        hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
 -                  (int)offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
      }
      stellaris_i2c_update(s);
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
      case 0x30: /* SAC */
          return s->sac;
      default:
 -        hw_error("strllaris_adc_read: Bad offset 0x%x\n",
 -                  (int)offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
          return 0;
      }
  }
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
              return;
          case 0x04: /* SSCTL */
              if (value != 6) {
 -                hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
 -                          value);
 +                qemu_log_mask(LOG_UNIMP,
 +                              "ADC: Unimplemented sequence %" PRIx64 "\n",
 +                              value);
              }
              s->ssctl[n] = value;
              return;
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
          s->sspri = value;
          break;
      case 0x28: /* PSSI */
 -        hw_error("Not implemented:  ADC sample initiate\n");
 +        qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
          break;
      case 0x30: /* SAC */
          s->sac = value;
          break;
      default:
 -        hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
      }
      stellaris_adc_update(s);
  }
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 02/24] hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
+[PULL 5/8] target/arm: Fix AddPAC error indication
-From: Krzysztof Kozlowski <krzk@kernel.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-qemu_log_mask() and error_report() are preferred over fprintf() for
+The definition of top_bit used in this function is one higher
-logging errors.  Also remove square brackets [] and additional new line
+than that used in the Arm ARM psuedo-code, which put the error
-characters in printed messages.
+indication at top_bit - 1 at the wrong place, which meant that
 it wasn't visible to Auth.
-Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+Fixing the definition of top_bit requires more changes, because
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+its most common use is for the count of bits in top_bit:bot_bit,
-Message-id: 20170313184750.429-2-krzk@kernel.org
+which would then need to be computed as top_bit - bot_bit + 1.
-[PMM: wrapped long line]
 For now, prefer the minimal fix to the error indication alone.
 Fixes: 63ff0ca94cb
 Reported-by: Derrick McKee <derrick.mckee@gmail.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200728195706.11087-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+[PMM: added comment about the divergence from the pseudocode]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/exynos4_boards.c   |  7 ++++---
+ target/arm/pauth_helper.c         |  6 +++++-
- hw/timer/exynos4210_mct.c |  6 ++++--
+ tests/tcg/aarch64/pauth-5.c       | 33 +++++++++++++++++++++++++++++++
- hw/timer/exynos4210_pwm.c | 13 +++++++------
+ tests/tcg/aarch64/Makefile.target |  2 +-
- hw/timer/exynos4210_rtc.c | 19 ++++++++++---------
+files changed, 39 insertions(+), 2 deletions(-)
-files changed, 25 insertions(+), 20 deletions(-)
+ create mode 100644 tests/tcg/aarch64/pauth-5.c
-diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
+diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/exynos4_boards.c
+--- a/target/arm/pauth_helper.c
-+++ b/hw/arm/exynos4_boards.c
++++ b/target/arm/pauth_helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
       */
      test = sextract64(ptr, bot_bit, top_bit - bot_bit);
      if (test != 0 && test != -1) {
 -        pac ^= MAKE_64BIT_MASK(top_bit - 1, 1);
 +        /*
 +         * Note that our top_bit is one greater than the pseudocode's
 +         * version, hence "- 2" here.
 +         */
 +        pac ^= MAKE_64BIT_MASK(top_bit - 2, 1);
      }
      /*
 diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/tcg/aarch64/pauth-5.c
 @@ -XXX,XX +XXX,XX @@
-  */
++#include <assert.h>
++
- #include "qemu/osdep.h"
++static int x;
-+#include "qemu/error-report.h"
++
- #include "qemu-common.h"
++int main()
- #include "cpu.h"
++{
- #include "sysemu/sysemu.h"
++    int *p0 = &x, *p1, *p2, *p3;
-@@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
++    unsigned long salt = 0;
-     MachineClass *mc = MACHINE_GET_CLASS(machine);
++
++    /*
-     if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
++     * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so
--        fprintf(stderr, "%s board supports only %d CPU cores. Ignoring smp_cpus"
++     * a 1/128 chance of auth = pac(ptr,key,salt) producing zero.
--                " value.\n",
++     * Find a salt that creates auth != 0.
--                mc->name, EXYNOS4210_NCPUS);
++     */
-+        error_report("%s board supports only %d CPU cores, ignoring smp_cpus"
++    do {
-+                     " value",
++        salt++;
-+                     mc->name, EXYNOS4210_NCPUS);
++        asm("pacda %0, %1" : "=r"(p1) : "r"(salt), "0"(p0));
-     }
++    } while (p0 == p1);
++
-     exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
++    /*
-diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
++     * This pac must fail, because the input pointer bears an encryption,
 +     * and so is not properly extended within bits [55:47].  This will
 +     * toggle bit 54 in the output...
 +     */
 +    asm("pacda %0, %1" : "=r"(p2) : "r"(salt), "0"(p1));
 +
 +    /* ... so that the aut must fail, setting bit 53 in the output ... */
 +    asm("autda %0, %1" : "=r"(p3) : "r"(salt), "0"(p2));
 +
 +    /* ... which means this equality must not hold. */
 +    assert(p3 != p0);
 +    return 0;
 +}
 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/exynos4210_mct.c
+--- a/tests/tcg/aarch64/Makefile.target
-+++ b/hw/timer/exynos4210_mct.c
++++ b/tests/tcg/aarch64/Makefile.target
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
-  */
+ # Pauth Tests
- #include "qemu/osdep.h"
+ ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_3),)
-+#include "qemu/log.h"
+-AARCH64_TESTS += pauth-1 pauth-2 pauth-4
- #include "hw/sysbus.h"
++AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5
- #include "qemu/timer.h"
+ pauth-%: CFLAGS += -march=armv8.3-a
- #include "qemu/main-loop.h"
+ run-pauth-%: QEMU_OPTS += -cpu max
-@@ -XXX,XX +XXX,XX @@ break;
+ run-plugin-pauth-%: QEMU_OPTS += -cpu max
      case L0_TCNTO: case L1_TCNTO:
      case L0_ICNTO: case L1_ICNTO:
      case L0_FRCNTO: case L1_FRCNTO:
 -        fprintf(stderr, "\n[exynos4210.mct: write to RO register "
 -                TARGET_FMT_plx "]\n\n", offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "exynos4210.mct: write to RO register " TARGET_FMT_plx,
 +                      offset);
          break;
      case L0_INT_CSTAT: case L1_INT_CSTAT:
 diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/exynos4210_pwm.c
 +++ b/hw/timer/exynos4210_pwm.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
 +#include "qemu/log.h"
  #include "hw/sysbus.h"
  #include "qemu/timer.h"
  #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
          break;
      default:
 -        fprintf(stderr,
 -                "[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n",
 -                offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "exynos4210.pwm: bad read offset " TARGET_FMT_plx,
 +                      offset);
          break;
      }
      return value;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset,
          break;
      default:
 -        fprintf(stderr,
 -                "[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n",
 -                offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "exynos4210.pwm: bad write offset " TARGET_FMT_plx,
 +                      offset);
          break;
      }
 diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/exynos4210_rtc.c
 +++ b/hw/timer/exynos4210_rtc.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
 +#include "qemu/log.h"
  #include "hw/sysbus.h"
  #include "qemu/timer.h"
  #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
          break;
      default:
 -        fprintf(stderr,
 -                "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n",
 -                offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
 +                      offset);
          break;
      }
      return value;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
          if (value > TICNT_THRESHOLD) {
              s->reg_ticcnt = value;
          } else {
 -            fprintf(stderr,
 -                    "[exynos4210.rtc: bad TICNT value %u ]\n",
 -                    (uint32_t)value);
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "exynos4210.rtc: bad TICNT value %u",
 +                          (uint32_t)value);
          }
          break;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
          break;
      default:
 -        fprintf(stderr,
 -                "[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n",
 -                offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
 +                      offset);
          break;
      }
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 03/24] hw/char/exynos4210_uart: Constify static array and few arguments
+Deleted patch
-From: Krzysztof Kozlowski <krzk@kernel.org>
-The static array exynos4210_uart_regs with register values is not
-modified so it can be made const.
-Few other functions accept driver or uart state as an argument but they
-do not change it and do not cast it so this can be made const for code
-safeness.
-Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-Message-id: 20170313184750.429-3-krzk@kernel.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/char/exynos4210_uart.c | 8 ++++----
-file changed, 4 insertions(+), 4 deletions(-)
-diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/exynos4210_uart.c
-+++ b/hw/char/exynos4210_uart.c
-@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210UartReg {
-     uint32_t            reset_value;
- } Exynos4210UartReg;
--static Exynos4210UartReg exynos4210_uart_regs[] = {
-+static const Exynos4210UartReg exynos4210_uart_regs[] = {
-     {"ULCON",    ULCON,    0x00000000},
-     {"UCON",     UCON,     0x00003000},
-     {"UFCON",    UFCON,    0x00000000},
-@@ -XXX,XX +XXX,XX @@ static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
-     return  ret;
- }
--static int fifo_elements_number(Exynos4210UartFIFO *q)
-+static int fifo_elements_number(const Exynos4210UartFIFO *q)
- {
-     if (q->sp < q->rp) {
-         return q->size - q->rp + q->sp;
-@@ -XXX,XX +XXX,XX @@ static int fifo_elements_number(Exynos4210UartFIFO *q)
-     return q->sp - q->rp;
- }
--static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
-+static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
- {
-     return q->size - fifo_elements_number(q);
- }
-@@ -XXX,XX +XXX,XX @@ static void fifo_reset(Exynos4210UartFIFO *q)
-     q->rp = 0;
- }
--static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
-+static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
- {
-     uint32_t level = 0;
-     uint32_t reg;
---
-.7.4

-[Qemu-devel] [PULL 04/24] hw/misc/exynos4210_pmu: Reorder local variables for readability
+Deleted patch
-From: Krzysztof Kozlowski <krzk@kernel.org>
-Short declaration of 'i' was in the middle of declarations with
-assignments.  Make it a little bit more readable.  Additionally switch
-from "unsigned" to "unsigned int" as this pattern is more widely used.
-No functional change.
-Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20170313184750.429-4-krzk@kernel.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/misc/exynos4210_pmu.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/exynos4210_pmu.c
-+++ b/hw/misc/exynos4210_pmu.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
-                                     unsigned size)
- {
-     Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
--    unsigned i;
-     const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
-+    unsigned int i;
-     for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
-         if (reg_p->offset == offset) {
-@@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
-                                  uint64_t val, unsigned size)
- {
-     Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
--    unsigned i;
-     const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
-+    unsigned int i;
-     for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
-         if (reg_p->offset == offset) {
---
-.7.4

-[Qemu-devel] [PULL 05/24] target/arm: Add missing entries to excnames[] for log strings
+Deleted patch
-Recent changes have added new EXCP_ values to ARM but forgot
-to update the excnames[] array which is used to provide
-human-readable strings when printing information about the
-exception for debug logging. Add the missing entries, and
-add a comment to the list of #defines to help avoid the mistake
-being repeated in future.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Message-id: 1491486340-25988-1-git-send-email-peter.maydell@linaro.org
----
- target/arm/cpu.h       | 1 +
- target/arm/internals.h | 2 ++
-files changed, 3 insertions(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
- #define EXCP_SEMIHOST       16   /* semihosting call */
- #define EXCP_NOCP           17   /* v7M NOCP UsageFault */
- #define EXCP_INVSTATE       18   /* v7M INVSTATE UsageFault */
-+/* NB: new EXCP_ defines should be added to the excnames[] array too */
- #define ARMV7M_EXCP_RESET   1
- #define ARMV7M_EXCP_NMI     2
-diff --git a/target/arm/internals.h b/target/arm/internals.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
-+++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ static const char * const excnames[] = {
-     [EXCP_VIRQ] = "Virtual IRQ",
-     [EXCP_VFIQ] = "Virtual FIQ",
-     [EXCP_SEMIHOST] = "Semihosting call",
-+    [EXCP_NOCP] = "v7M NOCP UsageFault",
-+    [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
- };
- /* Scale factor for generic timers, ie number of ns per tick.
---
-.7.4

-[Qemu-devel] [PULL 06/24] arm: Move excnames[] array into arm_log_exceptions()
+Deleted patch
-The excnames[] array is defined in internals.h because we used
-to use it from two different source files for handling logging
-of AArch32 and AArch64 exception entry. Refactoring means that
-it's now used only in arm_log_exception() in helper.c, so move
-the array into that function.
-Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1491821097-5647-1-git-send-email-peter.maydell@linaro.org
----
- target/arm/cpu.h       |  2 +-
- target/arm/internals.h | 23 -----------------------
- target/arm/helper.c    | 19 +++++++++++++++++++
-files changed, 20 insertions(+), 24 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
- #define EXCP_SEMIHOST       16   /* semihosting call */
- #define EXCP_NOCP           17   /* v7M NOCP UsageFault */
- #define EXCP_INVSTATE       18   /* v7M INVSTATE UsageFault */
--/* NB: new EXCP_ defines should be added to the excnames[] array too */
-+/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
- #define ARMV7M_EXCP_RESET   1
- #define ARMV7M_EXCP_NMI     2
-diff --git a/target/arm/internals.h b/target/arm/internals.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
-+++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
-         || excp == EXCP_SEMIHOST;
- }
--/* Exception names for debug logging; note that not all of these
-- * precisely correspond to architectural exceptions.
-- */
--static const char * const excnames[] = {
--    [EXCP_UDEF] = "Undefined Instruction",
--    [EXCP_SWI] = "SVC",
--    [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
--    [EXCP_DATA_ABORT] = "Data Abort",
--    [EXCP_IRQ] = "IRQ",
--    [EXCP_FIQ] = "FIQ",
--    [EXCP_BKPT] = "Breakpoint",
--    [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
--    [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
--    [EXCP_HVC] = "Hypervisor Call",
--    [EXCP_HYP_TRAP] = "Hypervisor Trap",
--    [EXCP_SMC] = "Secure Monitor Call",
--    [EXCP_VIRQ] = "Virtual IRQ",
--    [EXCP_VFIQ] = "Virtual FIQ",
--    [EXCP_SEMIHOST] = "Semihosting call",
--    [EXCP_NOCP] = "v7M NOCP UsageFault",
--    [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
--};
--
- /* Scale factor for generic timers, ie number of ns per tick.
-  * This gives a 62.5MHz timer.
-  */
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
- {
-     if (qemu_loglevel_mask(CPU_LOG_INT)) {
-         const char *exc = NULL;
-+        static const char * const excnames[] = {
-+            [EXCP_UDEF] = "Undefined Instruction",
-+            [EXCP_SWI] = "SVC",
-+            [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
-+            [EXCP_DATA_ABORT] = "Data Abort",
-+            [EXCP_IRQ] = "IRQ",
-+            [EXCP_FIQ] = "FIQ",
-+            [EXCP_BKPT] = "Breakpoint",
-+            [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
-+            [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
-+            [EXCP_HVC] = "Hypervisor Call",
-+            [EXCP_HYP_TRAP] = "Hypervisor Trap",
-+            [EXCP_SMC] = "Secure Monitor Call",
-+            [EXCP_VIRQ] = "Virtual IRQ",
-+            [EXCP_VFIQ] = "Virtual FIQ",
-+            [EXCP_SEMIHOST] = "Semihosting call",
-+            [EXCP_NOCP] = "v7M NOCP UsageFault",
-+            [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
-+        };
-         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
-             exc = excnames[idx];
---
-.7.4

-[Qemu-devel] [PULL 07/24] target/arm: Add assertion about FSC format for syndrome registers
+Deleted patch
-In tlb_fill() we construct a syndrome register value from a
-fault status register value which is filled in by arm_tlb_fill().
-arm_tlb_fill() returns FSR values which might be in the format
-used with short-format page descriptors, or the format used
-with long-format (LPAE) descriptors. The syndrome register
-always uses LPAE-format FSR status codes.
-It isn't actually possible to end up delivering a syndrome
-register value to the guest for a fault which is reported
-with a short-format FSR (that kind of stage 1 fault will only
-happen for an AArch32 translation regime which doesn't have
-a syndrome register, and can never be redirected to an AArch64
-or Hyp exception level). Add an assertion which checks this,
-and adjust the code so that we construct a syndrome with
-an invalid status code, rather than allowing set bits in
-the FSR input to randomly corrupt other fields in the syndrome.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Message-id: 1491486152-24304-1-git-send-email-peter.maydell@linaro.org
----
- target/arm/op_helper.c | 23 ++++++++++++++++++-----
-file changed, 18 insertions(+), 5 deletions(-)
-diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/op_helper.c
-+++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
-     if (unlikely(ret)) {
-         ARMCPU *cpu = ARM_CPU(cs);
-         CPUARMState *env = &cpu->env;
--        uint32_t syn, exc;
-+        uint32_t syn, exc, fsc;
-         unsigned int target_el;
-         bool same_el;
-@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
-             env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
-         }
-         same_el = arm_current_el(env) == target_el;
--        /* AArch64 syndrome does not have an LPAE bit */
--        syn = fsr & ~(1 << 9);
-+
-+        if (fsr & (1 << 9)) {
-+            /* LPAE format fault status register : bottom 6 bits are
-+             * status code in the same form as needed for syndrome
-+             */
-+            fsc = extract32(fsr, 0, 6);
-+        } else {
-+            /* Short format FSR : this fault will never actually be reported
-+             * to an EL that uses a syndrome register. Check that here,
-+             * and use a (currently) reserved FSR code in case the constructed
-+             * syndrome does leak into the guest somehow.
-+             */
-+            assert(target_el != 2 && !arm_el_is_aa64(env, target_el));
-+            fsc = 0x3f;
-+        }
-         /* For insn and data aborts we assume there is no instruction syndrome
-          * information; this is always true for exceptions reported to EL1.
-          */
-         if (access_type == MMU_INST_FETCH) {
--            syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
-+            syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc);
-             exc = EXCP_PREFETCH_ABORT;
-         } else {
-             syn = merge_syn_data_abort(env->exception.syndrome, target_el,
-                                        same_el, fi.s1ptw,
--                                       access_type == MMU_DATA_STORE, syn);
-+                                       access_type == MMU_DATA_STORE, fsc);
-             if (access_type == MMU_DATA_STORE
-                 && arm_feature(env, ARM_FEATURE_V6)) {
-                 fsr |= (1 << 11);
---
-.7.4

-[Qemu-devel] [PULL 09/24] arm/kvm: Remove trailing newlines from error_report()
+Deleted patch
-From: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
-Signed-off-by: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
-Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
-Message-id: 1491629987-6826-1-git-send-email-chugh.ishani@research.iiit.ac.in
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/kvm64.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm64.c
-+++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
-              * single step at this point so something has gone wrong.
-              */
-             error_report("%s: guest single-step while debugging unsupported"
--                         " (%"PRIx64", %"PRIx32")\n",
-+                         " (%"PRIx64", %"PRIx32")",
-                          __func__, env->pc, debug_exit->hsr);
-             return false;
-         }
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
-         break;
-     }
-     default:
--        error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")\n",
-+        error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")",
-                      __func__, debug_exit->hsr, env->pc);
-     }
---
-.7.4

-[Qemu-devel] [PULL 10/24] hw/arm: Qomify pxa2xx.c
+Deleted patch
-From: Suramya Shah <shah.suramya@gmail.com>
-Signed-off-by: Suramya Shah <shah.suramya@gmail.com>
-Message-id: 20170415180316.2694-1-shah.suramya@gmail.com
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/pxa2xx.c | 14 ++++++--------
-file changed, 6 insertions(+), 8 deletions(-)
-diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx.c
-+++ b/hw/arm/pxa2xx.c
-@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_reset(DeviceState *d)
-     s->rx_start = s->rx_level = 0;
- }
--static int pxa2xx_ssp_init(SysBusDevice *sbd)
-+static void pxa2xx_ssp_init(Object *obj)
- {
--    DeviceState *dev = DEVICE(sbd);
--    PXA2xxSSPState *s = PXA2XX_SSP(dev);
--
-+    DeviceState *dev = DEVICE(obj);
-+    PXA2xxSSPState *s = PXA2XX_SSP(obj);
-+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-     sysbus_init_irq(sbd, &s->irq);
--    memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
-+    memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
-                           "pxa2xx-ssp", 0x1000);
-     sysbus_init_mmio(sbd, &s->iomem);
-     s->bus = ssi_create_bus(dev, "ssi");
--    return 0;
- }
- /* Real-Time Clock */
-@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
- static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
- {
--    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
-     DeviceClass *dc = DEVICE_CLASS(klass);
--    sdc->init = pxa2xx_ssp_init;
-     dc->reset = pxa2xx_ssp_reset;
-     dc->vmsd = &vmstate_pxa2xx_ssp;
- }
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo pxa2xx_ssp_info = {
-     .name          = TYPE_PXA2XX_SSP,
-     .parent        = TYPE_SYS_BUS_DEVICE,
-     .instance_size = sizeof(PXA2xxSSPState),
-+    .instance_init = pxa2xx_ssp_init,
-     .class_init    = pxa2xx_ssp_class_init,
- };
---
-.7.4

-[Qemu-devel] [PULL 11/24] cadence_gem: Read the correct queue descriptor
+Deleted patch
-From: Alistair Francis <alistair.francis@xilinx.com>
-Read the correct descriptor instead of hardcoding the first (q=0).
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 988b183dcf951856d8b3379f7e911ec95233bbf4.1491947224.git.alistair.francis@xilinx.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/net/cadence_gem.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/net/cadence_gem.c
-+++ b/hw/net/cadence_gem.c
-@@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
- {
-     DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
-     /* read current descriptor */
--    cpu_physical_memory_read(s->rx_desc_addr[0],
--                             (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0]));
-+    cpu_physical_memory_read(s->rx_desc_addr[q],
-+                             (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q]));
-     /* Descriptor owned by software ? */
-     if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
---
-.7.4

-[Qemu-devel] [PULL 12/24] cadence_gem: Correct the multi-queue can rx logic
+Deleted patch
-From: Alistair Francis <alistair.francis@xilinx.com>
-Correct the buffer descriptor busy logic to work correctly when using
-multiple queues.
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
-Message-id: 8a7e8059984e27d46a276a66299d035a0afd280f.1491947224.git.alistair.francis@xilinx.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/net/cadence_gem.c | 17 ++++++++++-------
-file changed, 10 insertions(+), 7 deletions(-)
-diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/net/cadence_gem.c
-+++ b/hw/net/cadence_gem.c
-@@ -XXX,XX +XXX,XX @@ static int gem_can_receive(NetClientState *nc)
-     }
-     for (i = 0; i < s->num_priority_queues; i++) {
--        if (rx_desc_get_ownership(s->rx_desc[i]) == 1) {
--            if (s->can_rx_state != 2) {
--                s->can_rx_state = 2;
--                DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n",
--                         i, s->rx_desc_addr[i]);
--             }
--            return 0;
-+        if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
-+            break;
-+        }
-+    };
-+
-+    if (i == s->num_priority_queues) {
-+        if (s->can_rx_state != 2) {
-+            s->can_rx_state = 2;
-+            DB_PRINT("can't receive - all the buffer descriptors are busy\n");
-         }
-+        return 0;
-     }
-     if (s->can_rx_state != 0) {
---
-.7.4

-[Qemu-devel] [PULL 13/24] cadence_gem: Correct the interupt logic
+Deleted patch
-From: Alistair Francis <alistair.francis@xilinx.com>
-This patch fixes two mistakes in the interrupt logic.
-First we only trigger single-queue or multi-queue interrupts if the status
-register is set. This logic was already used for non multi-queue interrupts
-but it also applies to multi-queue interrupts.
-Secondly we need to lower the interrupts if the ISR isn't set. As part
-of this we can remove the other interrupt lowering logic and consolidate
-it inside gem_update_int_status().
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
-Message-id: 438bcc014f8f8a2f8f68f322cb6a53f4c04688c2.1491947224.git.alistair.francis@xilinx.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/net/cadence_gem.c | 18 +++++++++++++-----
-file changed, 13 insertions(+), 5 deletions(-)
-diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/net/cadence_gem.c
-+++ b/hw/net/cadence_gem.c
-@@ -XXX,XX +XXX,XX @@ static void gem_update_int_status(CadenceGEMState *s)
- {
-     int i;
--    if ((s->num_priority_queues == 1) && s->regs[GEM_ISR]) {
-+    if (!s->regs[GEM_ISR]) {
-+        /* ISR isn't set, clear all the interrupts */
-+        for (i = 0; i < s->num_priority_queues; ++i) {
-+            qemu_set_irq(s->irq[i], 0);
-+        }
-+        return;
-+    }
-+
-+    /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
-+     * check it again.
-+     */
-+    if (s->num_priority_queues == 1) {
-         /* No priority queues, just trigger the interrupt */
-         DB_PRINT("asserting int.\n");
-         qemu_set_irq(s->irq[0], 1);
-@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
- {
-     CadenceGEMState *s;
-     uint32_t retval;
--    int i;
-     s = (CadenceGEMState *)opaque;
-     offset >>= 2;
-@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
-     switch (offset) {
-     case GEM_ISR:
-         DB_PRINT("lowering irqs on ISR read\n");
--        for (i = 0; i < s->num_priority_queues; ++i) {
--            qemu_set_irq(s->irq[i], 0);
--        }
-+        /* The interrupts get updated at the end of the function. */
-         break;
-     case GEM_PHYMNTNC:
-         if (retval & GEM_PHYMNTNC_OP_R) {
---
-.7.4

-[Qemu-devel] [PULL 14/24] cadence_gem: Make the revision a property
+Deleted patch
-From: Alistair Francis <alistair.francis@xilinx.com>
-Expose the Cadence GEM revision as a property.
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 541324373cf87b50f8be0439a0cb89f5028b016f.1491947224.git.alistair.francis@xilinx.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/net/cadence_gem.h | 1 +
- hw/net/cadence_gem.c         | 6 +++++-
-files changed, 6 insertions(+), 1 deletion(-)
-diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/net/cadence_gem.h
-+++ b/include/hw/net/cadence_gem.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
-     uint8_t num_priority_queues;
-     uint8_t num_type1_screeners;
-     uint8_t num_type2_screeners;
-+    uint32_t revision;
-     /* GEM registers backing store */
-     uint32_t regs[CADENCE_GEM_MAXREG];
-diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/net/cadence_gem.c
-+++ b/hw/net/cadence_gem.c
-@@ -XXX,XX +XXX,XX @@
- #define DESC_1_RX_SOF 0x00004000
- #define DESC_1_RX_EOF 0x00008000
-+#define GEM_MODID_VALUE 0x00020118
-+
- static inline unsigned tx_desc_get_buffer(unsigned *desc)
- {
-     return desc[0];
-@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
-     s->regs[GEM_TXPAUSE] = 0x0000ffff;
-     s->regs[GEM_TXPARTIALSF] = 0x000003ff;
-     s->regs[GEM_RXPARTIALSF] = 0x000003ff;
--    s->regs[GEM_MODID] = 0x00020118;
-+    s->regs[GEM_MODID] = s->revision;
-     s->regs[GEM_DESCONF] = 0x02500111;
-     s->regs[GEM_DESCONF2] = 0x2ab13fff;
-     s->regs[GEM_DESCONF5] = 0x002f2145;
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_cadence_gem = {
- static Property gem_properties[] = {
-     DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
-+    DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
-+                       GEM_MODID_VALUE),
-     DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
-                       num_priority_queues, 1),
-     DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
---
-.7.4

-[Qemu-devel] [PULL 15/24] xlnx-zynqmp: Set the Cadence GEM revision
+Deleted patch
-From: Alistair Francis <alistair.francis@xilinx.com>
-Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 026dbe01a1d42619eee30ce3f2079741bf04bc73.1491947224.git.alistair.francis@xilinx.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/xlnx-zynqmp.c | 6 +++++-
-file changed, 5 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-zynqmp.c
-+++ b/hw/arm/xlnx-zynqmp.c
-@@ -XXX,XX +XXX,XX @@
- #define ARM_PHYS_TIMER_PPI  30
- #define ARM_VIRT_TIMER_PPI  27
-+#define GEM_REVISION        0x40070106
-+
- #define GIC_BASE_ADDR       0xf9000000
- #define GIC_DIST_ADDR       0xf9010000
- #define GIC_CPU_ADDR        0xf9020000
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
-             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
-             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
-         }
-+        object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
-+                                &error_abort);
-         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
--                                  &error_abort);
-+                                &error_abort);
-         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
-         if (err) {
-             error_propagate(errp, err);
---
-.7.4

-[Qemu-devel] [PULL 16/24] arm: Don't implement BXJ on M-profile CPUs
+Deleted patch
-For M-profile CPUs, the BXJ instruction does not exist at all, and
-the encoding should always UNDEF. We were accidentally implementing
-it to behave like A-profile BXJ; correct the error.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
-Message-id: 1491844419-12485-2-git-send-email-peter.maydell@linaro.org
----
- target/arm/translate.c | 7 ++++++-
-file changed, 6 insertions(+), 1 deletion(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
-                         }
-                         break;
-                     case 4: /* bxj */
--                        /* Trivial implementation equivalent to bx.  */
-+                        /* Trivial implementation equivalent to bx.
-+                         * This instruction doesn't exist at all for M-profile.
-+                         */
-+                        if (arm_dc_feature(s, ARM_FEATURE_M)) {
-+                            goto illegal_op;
-+                        }
-                         tmp = load_reg(s, rn);
-                         gen_bx(s, tmp);
-                         break;
---
-.7.4

-[Qemu-devel] [PULL 17/24] arm: Thumb shift operations should not permit interworking branches
+[PULL 6/8] target/arm: Avoid maybe-uninitialized warning with gcc 4.9
-In Thumb mode, the only instructions which can cause an interworking
+From: Kaige Li <likaige@loongson.cn>
 branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
 ARM mode, data processing instructions which target the PC do not
 cause interworking branches.
-When we added support for doing interworking branches on writes to
+GCC version 4.9.4 isn't clever enough to figure out that all
-PC from data processing instructions in commit 21aeb3430ce7ba, we
+execution paths in disas_ldst() that use 'fn' will have initialized
-accidentally changed a Thumb instruction to have interworking
+it first, and so it warns:
 branch behaviour for writes to PC. (MOV, MOVS register-shifted
 register, encoding T2; this is the standard encoding for
 LSL/LSR/ASR/ROR (register).)
-For this encoding, behaviour with Rd == R15 is specified as
+/home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’:
-UNPREDICTABLE, so allowing an interworking branch is within
+/home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
-spec, but it's confusing and differs from our handling of this
+     fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
-class of UNPREDICTABLE for other Thumb ALU operations. Make
+     ^
-it perform a simple (non-interworking) branch like the others.
+/home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here
      AtomicThreeOpFn *fn;
                       ^
+Make it happy by initializing the variable to NULL.
+Signed-off-by: Kaige Li <likaige@loongson.cn>
+Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+[PMM: Clean up commit message and note which gcc version this was]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1491844419-12485-3-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 2 +-
+ target/arm/translate-a64.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/translate-a64.c
-+++ b/target/arm/translate.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
+@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
-             gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
+     bool r = extract32(insn, 22, 1);
-             if (logic_cc)
+     bool a = extract32(insn, 23, 1);
-                 gen_logic_CC(tmp);
+     TCGv_i64 tcg_rs, clean_addr;
--            store_reg_bx(s, rd, tmp);
+-    AtomicThreeOpFn *fn;
-+            store_reg(s, rd, tmp);
++    AtomicThreeOpFn *fn = NULL;
-             break;
-         case 1: /* Sign/zero extend.  */
+     if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
-             op = (insn >> 20) & 7;
+         unallocated_encoding(s);
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 20/24] arm: Move condition-failed codepath generation out of if()
+[PULL 7/8] hw/arm/nrf51_soc: Set system_clock_scale
-Move the code to generate the "condition failed" instruction
+The nrf51 SoC model wasn't setting the system_clock_scale
-codepath out of the if (singlestepping) {} else {}. This
+global.which meant that if guest code used the systick timer in "use
-will allow adding support for handling a new is_jmp type
+the processor clock" mode it would hang because time never advances.
-which can't be neatly split into "singlestepping case"
-versus "not singlestepping case".
+Set the global to match the documented CPU clock speed for this SoC.
 This SoC in fact doesn't have a SysTick timer (which is the only thing
 currently that cares about the system_clock_scale), because it's
 a configurable option in the Cortex-M0. However our Cortex-M0 and
 thus our nrf51 and our micro:bit board do provide a SysTick, so
 we ought to provide a functional one rather than a broken one.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
+Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
 Message-id: 1491844419-12485-6-git-send-email-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 24 +++++++++++-------------
+ hw/arm/nrf51_soc.c | 5 +++++
-file changed, 11 insertions(+), 13 deletions(-)
+file changed, 5 insertions(+)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/hw/arm/nrf51_soc.c
-+++ b/target/arm/translate.c
++++ b/hw/arm/nrf51_soc.c
-@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
+@@ -XXX,XX +XXX,XX @@
-     /* At this stage dc->condjmp will only be set when the skipped
-        instruction was a conditional branch or trap, and the PC has
+ #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
-        already been written.  */
-+    gen_set_condexec(dc);
++/* HCLK (the main CPU clock) on this SoC is always 16MHz */
-     if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
++#define HCLK_FRQ 16000000
          /* Unconditional and "condition passed" instruction codepath. */
 -        gen_set_condexec(dc);
          switch (dc->is_jmp) {
          case DISAS_SWI:
              gen_ss_advance(dc);
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
              /* FIXME: Single stepping a WFI insn will not halt the CPU. */
              gen_singlestep_exception(dc);
          }
 -        if (dc->condjmp) {
 -            /* "Condition failed" instruction codepath. */
 -            gen_set_label(dc->condlabel);
 -            gen_set_condexec(dc);
 -            gen_set_pc_im(dc, dc->pc);
 -            gen_singlestep_exception(dc);
 -        }
      } else {
          /* While branches must always occur at the end of an IT block,
             there are a few other things that can cause us to terminate
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
              - Hardware watchpoints.
             Hardware breakpoints have already been handled and skip this code.
           */
 -        gen_set_condexec(dc);
          switch(dc->is_jmp) {
          case DISAS_NEXT:
              gen_goto_tb(dc, 1, dc->pc);
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
              gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
              break;
          }
 -        if (dc->condjmp) {
 -            gen_set_label(dc->condlabel);
 -            gen_set_condexec(dc);
 +    }
 +
-+    if (dc->condjmp) {
+ static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
-+        /* "Condition failed" instruction codepath for the branch/trap insn */
+ {
-+        gen_set_label(dc->condlabel);
+     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
-+        gen_set_condexec(dc);
+@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
-+        if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
+         return;
 +            gen_set_pc_im(dc, dc->pc);
 +            gen_singlestep_exception(dc);
 +        } else {
              gen_goto_tb(dc, 1, dc->pc);
 -            dc->condjmp = 0;
          }
      }
++    system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
++
+     object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
+                              &error_abort);
+     if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 21/24] arm: Abstract out "are we singlestepping" test to utility function
+Deleted patch
-We now test for "are we singlestepping" in several places and
-it's not a trivial check because we need to care about both
-architectural singlestep and QEMU gdbstub singlestep. We're
-also about to add another place that needs to make this check,
-so pull the condition out into a function.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1491844419-12485-7-git-send-email-peter.maydell@linaro.org
----
- target/arm/translate.c | 20 +++++++++++++++-----
-file changed, 15 insertions(+), 5 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_singlestep_exception(DisasContext *s)
-     }
- }
-+static inline bool is_singlestepping(DisasContext *s)
-+{
-+    /* Return true if we are singlestepping either because of
-+     * architectural singlestep or QEMU gdbstub singlestep. This does
-+     * not include the command line '-singlestep' mode which is rather
-+     * misnamed as it only means "one instruction per TB" and doesn't
-+     * affect the code we generate.
-+     */
-+    return s->singlestep_enabled || s->ss_active;
-+}
-+
- static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
- {
-     TCGv_i32 tmp1 = tcg_temp_new_i32();
-@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
- static inline void gen_jmp (DisasContext *s, uint32_t dest)
- {
--    if (unlikely(s->singlestep_enabled || s->ss_active)) {
-+    if (unlikely(is_singlestepping(s))) {
-         /* An indirect jump so that we still trigger the debug exception.  */
-         if (s->thumb)
-             dest |= 1;
-@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
-             ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));
-     } while (!dc->is_jmp && !tcg_op_buf_full() &&
--             !cs->singlestep_enabled &&
-+             !is_singlestepping(dc) &&
-              !singlestep &&
--             !dc->ss_active &&
-              !end_of_page &&
-              num_insns < max_insns);
-@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
-        instruction was a conditional branch or trap, and the PC has
-        already been written.  */
-     gen_set_condexec(dc);
--    if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
-+    if (unlikely(is_singlestepping(dc))) {
-         /* Unconditional and "condition passed" instruction codepath. */
-         switch (dc->is_jmp) {
-         case DISAS_SWI:
-@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
-         /* "Condition failed" instruction codepath for the branch/trap insn */
-         gen_set_label(dc->condlabel);
-         gen_set_condexec(dc);
--        if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
-+        if (unlikely(is_singlestepping(dc))) {
-             gen_set_pc_im(dc, dc->pc);
-             gen_singlestep_exception(dc);
-         } else {
---
-.7.4

-[Qemu-devel] [PULL 22/24] arm: Track M profile handler mode state in TB flags
+[PULL 8/8] hw/timer/imx_epit: Avoid assertion when CR.SWR is written
-For M profile exception-return handling we'd like to generate different
+The imx_epit device has a software-controllable reset triggered by
-code for some instructions depending on whether we are in Handler
+setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
-mode or Thread mode. This isn't the same as "are we privileged
+means that we will end up assert()ing if the guest does this, because
-or user", so we need an extra bit in the TB flags to distinguish.
+the code in imx_epit_write() starts ptimer transactions, and then
 imx_epit_reset() also starts ptimer transactions, triggering
 "ptimer_transaction_begin: Assertion `!s->in_transaction' failed".
+The cleanest way to avoid this double-transaction is to move the
+start-transaction for the CR write handling down below the check of
+the SWR bit.
+Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
+Fixes: cc2722ec83ad944505fe
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1491844419-12485-8-git-send-email-peter.maydell@linaro.org
+Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
 ---
- target/arm/cpu.h       | 9 +++++++++
+ hw/timer/imx_epit.c | 13 ++++++++++---
- target/arm/translate.h | 1 +
+file changed, 10 insertions(+), 3 deletions(-)
  target/arm/translate.c | 1 +
 files changed, 11 insertions(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/timer/imx_epit.c
-+++ b/target/arm/cpu.h
++++ b/hw/timer/imx_epit.c
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
+@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
- #define ARM_TBFLAG_NS_MASK          (1 << ARM_TBFLAG_NS_SHIFT)
- #define ARM_TBFLAG_BE_DATA_SHIFT    20
+     switch (offset >> 2) {
- #define ARM_TBFLAG_BE_DATA_MASK     (1 << ARM_TBFLAG_BE_DATA_SHIFT)
+     case 0: /* CR */
-+/* For M profile only, Handler (ie not Thread) mode */
+-        ptimer_transaction_begin(s->timer_cmp);
-+#define ARM_TBFLAG_HANDLER_SHIFT    21
+-        ptimer_transaction_begin(s->timer_reload);
-+#define ARM_TBFLAG_HANDLER_MASK     (1 << ARM_TBFLAG_HANDLER_SHIFT)
+         oldcr = s->cr;
- /* Bit usage when in AArch64 state */
+         s->cr = value & 0x03ffffff;
- #define ARM_TBFLAG_TBI0_SHIFT 0        /* TBI0 for EL0/1 or TBI for EL2/3 */
+         if (s->cr & CR_SWR) {
-@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
+             /* handle the reset */
-     (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
+             imx_epit_reset(DEVICE(s));
- #define ARM_TBFLAG_BE_DATA(F) \
+-        } else {
-     (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
++            /*
-+#define ARM_TBFLAG_HANDLER(F) \
++             * TODO: could we 'break' here? following operations appear
-+    (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
++             * to duplicate the work imx_epit_reset() already did.
- #define ARM_TBFLAG_TBI0(F) \
++             */
-     (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
++        }
  #define ARM_TBFLAG_TBI1(F) \
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
      }
      *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
 +    if (env->v7m.exception != 0) {
 +        *flags |= ARM_TBFLAG_HANDLER_MASK;
 +    }
 +
-     *cs_base = 0;
++        ptimer_transaction_begin(s->timer_cmp);
- }
++        ptimer_transaction_begin(s->timer_reload);
++
-diff --git a/target/arm/translate.h b/target/arm/translate.h
++        if (!(s->cr & CR_SWR)) {
-index XXXXXXX..XXXXXXX 100644
+             imx_epit_set_freq(s);
---- a/target/arm/translate.h
+         }
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      bool vfp_enabled; /* FP enabled via FPSCR.EN */
      int vec_len;
      int vec_stride;
 +    bool v7m_handler_mode;
      /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
       * so that top level loop can generate correct syndrome information.
       */
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
      dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
      dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
      dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
 +    dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
      dc->cp_regs = cpu->cp_regs;
      dc->features = env->features;
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 23/24] arm: Implement M profile exception return properly
+Deleted patch
-On M profile, return from exceptions happen when code in Handler mode
-executes one of the following function call return instructions:
- * POP or LDM which loads the PC
- * LDR to PC
- * BX register
-and the new PC value is 0xFFxxxxxx.
-QEMU tries to implement this by not treating the instruction
-specially but then catching the attempt to execute from the magic
-address value.  This is not ideal, because:
- * there are guest visible differences from the architecturally
-   specified behaviour (for instance jumping to 0xFFxxxxxx via a
-   different instruction should not cause an exception return but it
-   will in the QEMU implementation)
- * we have to account for it in various places (like refusing to take
-   an interrupt if the PC is at a magic value, and making sure that
-   the MPU doesn't deny execution at the magic value addresses)
-Drop these hacks, and instead implement exception return the way the
-architecture specifies -- by having the relevant instructions check
-for the magic value and raise the 'do an exception return' QEMU
-internal exception immediately.
-The effect on the generated code is minor:
- bx lr, old code (and new code for Thread mode):
-  TCG:
-   mov_i32 tmp5,r14
-   movi_i32 tmp6,$0xfffffffffffffffe
-   and_i32 pc,tmp5,tmp6
-   movi_i32 tmp6,$0x1
-   and_i32 tmp5,tmp5,tmp6
-   st_i32 tmp5,env,$0x218
-   exit_tb $0x0
-   set_label $L0
-   exit_tb $0x7f2aabd61993
-  x86_64 generated code:
-x7f2aabe87019:  mov    %ebx,%ebp
-x7f2aabe8701b:  and    $0xfffffffffffffffe,%ebp
-x7f2aabe8701e:  mov    %ebp,0x3c(%r14)
-x7f2aabe87022:  and    $0x1,%ebx
-x7f2aabe87025:  mov    %ebx,0x218(%r14)
-x7f2aabe8702c:  xor    %eax,%eax
-x7f2aabe8702e:  jmpq   0x7f2aabe7c016
- bx lr, new code when in Handler mode:
-  TCG:
-   mov_i32 tmp5,r14
-   movi_i32 tmp6,$0xfffffffffffffffe
-   and_i32 pc,tmp5,tmp6
-   movi_i32 tmp6,$0x1
-   and_i32 tmp5,tmp5,tmp6
-   st_i32 tmp5,env,$0x218
-   movi_i32 tmp5,$0xffffffffff000000
-   brcond_i32 pc,tmp5,geu,$L1
-   exit_tb $0x0
-   set_label $L1
-   movi_i32 tmp5,$0x8
-   call exception_internal,$0x0,$0,env,tmp5
-  x86_64 generated code:
-x7fe8fa1264e3:  mov    %ebp,%ebx
-x7fe8fa1264e5:  and    $0xfffffffffffffffe,%ebx
-x7fe8fa1264e8:  mov    %ebx,0x3c(%r14)
-x7fe8fa1264ec:  and    $0x1,%ebp
-x7fe8fa1264ef:  mov    %ebp,0x218(%r14)
-x7fe8fa1264f6:  cmp    $0xff000000,%ebx
-x7fe8fa1264fc:  jae    0x7fe8fa126509
-x7fe8fa126502:  xor    %eax,%eax
-x7fe8fa126504:  jmpq   0x7fe8fa122016
-x7fe8fa126509:  mov    %r14,%rdi
-x7fe8fa12650c:  mov    $0x8,%esi
-x7fe8fa126511:  mov    $0x56095dbeccf5,%r10
-x7fe8fa12651b:  callq  *%r10
-which is a difference of one cmp/branch-not-taken. This will
-be lost in the noise of having to exit generated code and
-look up the next TB anyway.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <rth@twiddle.net>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 1491844419-12485-9-git-send-email-peter.maydell@linaro.org
----
- target/arm/translate.h |  4 +++
- target/arm/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++-----
-files changed, 64 insertions(+), 6 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
- #define DISAS_HVC 8
- #define DISAS_SMC 9
- #define DISAS_YIELD 10
-+/* M profile branch which might be an exception return (and so needs
-+ * custom end-of-TB code)
-+ */
-+#define DISAS_BX_EXCRET 11
- #ifdef TARGET_AARCH64
- void a64_translate_init(void);
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
-     store_cpu_field(var, thumb);
- }
-+/* Set PC and Thumb state from var. var is marked as dead.
-+ * For M-profile CPUs, include logic to detect exception-return
-+ * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
-+ * and BX reg, and no others, and happens only for code in Handler mode.
-+ */
-+static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
-+{
-+    /* Generate the same code here as for a simple bx, but flag via
-+     * s->is_jmp that we need to do the rest of the work later.
-+     */
-+    gen_bx(s, var);
-+    if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
-+        s->is_jmp = DISAS_BX_EXCRET;
-+    }
-+}
-+
-+static inline void gen_bx_excret_final_code(DisasContext *s)
-+{
-+    /* Generate the code to finish possible exception return and end the TB */
-+    TCGLabel *excret_label = gen_new_label();
-+
-+    /* Is the new PC value in the magic range indicating exception return? */
-+    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
-+    /* No: end the TB as we would for a DISAS_JMP */
-+    if (is_singlestepping(s)) {
-+        gen_singlestep_exception(s);
-+    } else {
-+        tcg_gen_exit_tb(0);
-+    }
-+    gen_set_label(excret_label);
-+    /* Yes: this is an exception return.
-+     * At this point in runtime env->regs[15] and env->thumb will hold
-+     * the exception-return magic number, which do_v7m_exception_exit()
-+     * will read. Nothing else will be able to see those values because
-+     * the cpu-exec main loop guarantees that we will always go straight
-+     * from raising the exception to the exception-handling code.
-+     *
-+     * gen_ss_advance(s) does nothing on M profile currently but
-+     * calling it is conceptually the right thing as we have executed
-+     * this instruction (compare SWI, HVC, SMC handling).
-+     */
-+    gen_ss_advance(s);
-+    gen_exception_internal(EXCP_EXCEPTION_EXIT);
-+}
-+
- /* Variant of store_reg which uses branch&exchange logic when storing
-    to r15 in ARM architecture v7 and above. The source must be a temporary
-    and will be marked as dead. */
-@@ -XXX,XX +XXX,XX @@ static inline void store_reg_bx(DisasContext *s, int reg, TCGv_i32 var)
- static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
- {
-     if (reg == 15 && ENABLE_ARCH_5) {
--        gen_bx(s, var);
-+        gen_bx_excret(s, var);
-     } else {
-         store_reg(s, reg, var);
-     }
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
-                         tmp = tcg_temp_new_i32();
-                         gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
-                         if (i == 15) {
--                            gen_bx(s, tmp);
-+                            gen_bx_excret(s, tmp);
-                         } else if (i == rn) {
-                             loaded_var = tmp;
-                             loaded_base = 1;
-@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
-                 goto illegal_op;
-             }
-             if (rs == 15) {
--                gen_bx(s, tmp);
-+                gen_bx_excret(s, tmp);
-             } else {
-                 store_reg(s, rs, tmp);
-             }
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
-                     tmp2 = tcg_temp_new_i32();
-                     tcg_gen_movi_i32(tmp2, val);
-                     store_reg(s, 14, tmp2);
-+                    gen_bx(s, tmp);
-+                } else {
-+                    /* Only BX works as exception-return, not BLX */
-+                    gen_bx_excret(s, tmp);
-                 }
--                /* already thumb, no need to check */
--                gen_bx(s, tmp);
-                 break;
-             }
-             break;
-@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
-        instruction was a conditional branch or trap, and the PC has
-        already been written.  */
-     gen_set_condexec(dc);
--    if (unlikely(is_singlestepping(dc))) {
-+    if (dc->is_jmp == DISAS_BX_EXCRET) {
-+        /* Exception return branches need some special case code at the
-+         * end of the TB, which is complex enough that it has to
-+         * handle the single-step vs not and the condition-failed
-+         * insn codepath itself.
-+         */
-+        gen_bx_excret_final_code(dc);
-+    } else if (unlikely(is_singlestepping(dc))) {
-         /* Unconditional and "condition passed" instruction codepath. */
-         switch (dc->is_jmp) {
-         case DISAS_SWI:
---
-.7.4

First ARM pullreq of the 2.10 cycle...

thanks
-- PMM

The following changes since commit 64c8ed97cceabac4fafe17fca8d88ef08183f439:

Open 2.10 development tree (2017-04-20 15:42:31 +0100)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170420

for you to fetch changes up to f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa:

arm: Remove workarounds for old M-profile exception return implementation (2017-04-20 17:39:17 +0100)

----------------------------------------------------------------
target-arm queue:
 * implement M profile exception return properly
 * cadence GEM: fix multiqueue handling bugs
 * pxa2xx.c: QOMify a device
 * arm/kvm: Remove trailing newlines from error_report()
 * stellaris: Don't hw_error() on bad register accesses
 * Add assertion about FSC format for syndrome registers
 * Move excnames[] array into arm_log_exceptions()
 * exynos: minor code cleanups
 * hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
 * Fix APSR writes via M profile MSR

----------------------------------------------------------------
Alistair Francis (5):
      cadence_gem: Read the correct queue descriptor
      cadence_gem: Correct the multi-queue can rx logic
      cadence_gem: Correct the interupt logic
      cadence_gem: Make the revision a property
      xlnx-zynqmp: Set the Cadence GEM revision

Ard Biesheuvel (1):
      hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account

Ishani Chugh (1):
      arm/kvm: Remove trailing newlines from error_report()

Krzysztof Kozlowski (3):
      hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
      hw/char/exynos4210_uart: Constify static array and few arguments
      hw/misc/exynos4210_pmu: Reorder local variables for readability

Peter Maydell (13):
      target/arm: Add missing entries to excnames[] for log strings
      arm: Move excnames[] array into arm_log_exceptions()
      target/arm: Add assertion about FSC format for syndrome registers
      stellaris: Don't hw_error() on bad register accesses
      arm: Don't implement BXJ on M-profile CPUs
      arm: Thumb shift operations should not permit interworking branches
      arm: Factor out "generate right kind of step exception"
      arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
      arm: Move condition-failed codepath generation out of if()
      arm: Abstract out "are we singlestepping" test to utility function
      arm: Track M profile handler mode state in TB flags
      arm: Implement M profile exception return properly
      arm: Remove workarounds for old M-profile exception return implementation

Suramya Shah (1):
      hw/arm: Qomify pxa2xx.c

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

The arm64 boot protocol stipulates that the kernel must be loaded
TEXT_OFFSET bytes beyond a 2 MB aligned base address, where TEXT_OFFSET
could be any 4 KB multiple between 0 and 2 MB, and whose value can be
found in the header of the Image file.

So after attempts to load the arm64 kernel image as an ELF file or as a
U-Boot image have failed (both of which have their own way of specifying
the load offset), try to determine the TEXT_OFFSET from the image after
loading it but before mapping it as a ROM mapping into the guest address
space.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1489414630-21609-1-git-send-email-ard.biesheuvel@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 53 insertions(+), 11 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@
 #define KERNEL_LOAD_ADDR 0x00010000
 #define KERNEL64_LOAD_ADDR 0x00080000
 
+#define ARM64_TEXT_OFFSET_OFFSET    8
+#define ARM64_MAGIC_OFFSET          56
+
 typedef enum {
     FIXUP_NONE = 0,     /* do nothing */
     FIXUP_TERMINATOR,   /* end of insns */
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
     return ret;
 }
 
+static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
+                                   hwaddr *entry)
+{
+    hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
+    uint8_t *buffer;
+    int size;
+
+    /* On aarch64, it's the bootloader's job to uncompress the kernel. */
+    size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
+                                     &buffer);
+
+    if (size < 0) {
+        gsize len;
+
+        /* Load as raw file otherwise */
+        if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
+            return -1;
+        }
+        size = len;
+    }
+
+    /* check the arm64 magic header value -- very old kernels may not have it */
+    if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
+        uint64_t hdrvals[2];
+
+        /* The arm64 Image header has text_offset and image_size fields at 8 and
+         * 16 bytes into the Image header, respectively. The text_offset field
+         * is only valid if the image_size is non-zero.
+         */
+        memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
+        if (hdrvals[1] != 0) {
+            kernel_load_offset = le64_to_cpu(hdrvals[0]);
+        }
+    }
+
+    *entry = mem_base + kernel_load_offset;
+    rom_add_blob_fixed(filename, buffer, size, *entry);
+
+    g_free(buffer);
+
+    return size;
+}
+
 static void arm_load_kernel_notify(Notifier *notifier, void *data)
 {
     CPUState *cs;
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
     int is_linux = 0;
     uint64_t elf_entry, elf_low_addr, elf_high_addr;
     int elf_machine;
-    hwaddr entry, kernel_load_offset;
+    hwaddr entry;
     static const ARMInsnFixup *primary_loader;
     ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier,
                                          notifier, notifier);
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
 
     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
         primary_loader = bootloader_aarch64;
-        kernel_load_offset = KERNEL64_LOAD_ADDR;
         elf_machine = EM_AARCH64;
     } else {
         primary_loader = bootloader;
         if (!info->write_board_setup) {
             primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
         }
-        kernel_load_offset = KERNEL_LOAD_ADDR;
         elf_machine = EM_ARM;
     }
 
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
         kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
                                   &is_linux, NULL, NULL);
     }
-    /* On aarch64, it's the bootloader's job to uncompress the kernel. */
     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
-        entry = info->loader_start + kernel_load_offset;
-        kernel_size = load_image_gzipped(info->kernel_filename, entry,
-                                         info->ram_size - kernel_load_offset);
+        kernel_size = load_aarch64_image(info->kernel_filename,
+                                         info->loader_start, &entry);
         is_linux = 1;
-    }
-    if (kernel_size < 0) {
-        entry = info->loader_start + kernel_load_offset;
+    } else if (kernel_size < 0) {
+        /* 32-bit ARM */
+        entry = info->loader_start + KERNEL_LOAD_ADDR;
         kernel_size = load_image_targphys(info->kernel_filename, entry,
-                                          info->ram_size - kernel_load_offset);
+                                          info->ram_size - KERNEL_LOAD_ADDR);
         is_linux = 1;
     }
     if (kernel_size < 0) {
-- 
2.7.4

From: Krzysztof Kozlowski <krzk@kernel.org>

qemu_log_mask() and error_report() are preferred over fprintf() for
logging errors.  Also remove square brackets [] and additional new line
characters in printed messages.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170313184750.429-2-krzk@kernel.org
[PMM: wrapped long line]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c   |  7 ++++---
 hw/timer/exynos4210_mct.c |  6 ++++--
 hw/timer/exynos4210_pwm.c | 13 +++++++------
 hw/timer/exynos4210_rtc.c | 19 ++++++++++---------
 4 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/error-report.h"
 #include "qemu-common.h"
 #include "cpu.h"
 #include "sysemu/sysemu.h"
@@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
     MachineClass *mc = MACHINE_GET_CLASS(machine);
 
     if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
-        fprintf(stderr, "%s board supports only %d CPU cores. Ignoring smp_cpus"
-                " value.\n",
-                mc->name, EXYNOS4210_NCPUS);
+        error_report("%s board supports only %d CPU cores, ignoring smp_cpus"
+                     " value",
+                     mc->name, EXYNOS4210_NCPUS);
     }
 
     exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/log.h"
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
 #include "qemu/main-loop.h"
@@ -XXX,XX +XXX,XX @@ break;
     case L0_TCNTO: case L1_TCNTO:
     case L0_ICNTO: case L1_ICNTO:
     case L0_FRCNTO: case L1_FRCNTO:
-        fprintf(stderr, "\n[exynos4210.mct: write to RO register "
-                TARGET_FMT_plx "]\n\n", offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "exynos4210.mct: write to RO register " TARGET_FMT_plx,
+                      offset);
         break;
 
     case L0_INT_CSTAT: case L1_INT_CSTAT:
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/exynos4210_pwm.c
+++ b/hw/timer/exynos4210_pwm.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/log.h"
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
 #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
         break;
 
     default:
-        fprintf(stderr,
-                "[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n",
-                offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "exynos4210.pwm: bad read offset " TARGET_FMT_plx,
+                      offset);
         break;
     }
     return value;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset,
         break;
 
     default:
-        fprintf(stderr,
-                "[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n",
-                offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "exynos4210.pwm: bad write offset " TARGET_FMT_plx,
+                      offset);
         break;
 
     }
diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/exynos4210_rtc.c
+++ b/hw/timer/exynos4210_rtc.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/log.h"
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
 #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
         break;
 
     default:
-        fprintf(stderr,
-                "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n",
-                offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
+                      offset);
         break;
     }
     return value;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
         if (value > TICNT_THRESHOLD) {
             s->reg_ticcnt = value;
         } else {
-            fprintf(stderr,
-                    "[exynos4210.rtc: bad TICNT value %u ]\n",
-                    (uint32_t)value);
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "exynos4210.rtc: bad TICNT value %u",
+                          (uint32_t)value);
         }
         break;
 
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
         break;
 
     default:
-        fprintf(stderr,
-                "[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n",
-                offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
+                      offset);
         break;
 
     }
-- 
2.7.4

From: Krzysztof Kozlowski <krzk@kernel.org>

The static array exynos4210_uart_regs with register values is not
modified so it can be made const.

Few other functions accept driver or uart state as an argument but they
do not change it and do not cast it so this can be made const for code
safeness.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Message-id: 20170313184750.429-3-krzk@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/exynos4210_uart.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/exynos4210_uart.c
+++ b/hw/char/exynos4210_uart.c
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210UartReg {
     uint32_t            reset_value;
 } Exynos4210UartReg;
 
-static Exynos4210UartReg exynos4210_uart_regs[] = {
+static const Exynos4210UartReg exynos4210_uart_regs[] = {
     {"ULCON",    ULCON,    0x00000000},
     {"UCON",     UCON,     0x00003000},
     {"UFCON",    UFCON,    0x00000000},
@@ -XXX,XX +XXX,XX @@ static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
     return  ret;
 }
 
-static int fifo_elements_number(Exynos4210UartFIFO *q)
+static int fifo_elements_number(const Exynos4210UartFIFO *q)
 {
     if (q->sp < q->rp) {
         return q->size - q->rp + q->sp;
@@ -XXX,XX +XXX,XX @@ static int fifo_elements_number(Exynos4210UartFIFO *q)
     return q->sp - q->rp;
 }
 
-static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
+static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
 {
     return q->size - fifo_elements_number(q);
 }
@@ -XXX,XX +XXX,XX @@ static void fifo_reset(Exynos4210UartFIFO *q)
     q->rp = 0;
 }
 
-static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
+static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
 {
     uint32_t level = 0;
     uint32_t reg;
-- 
2.7.4

From: Krzysztof Kozlowski <krzk@kernel.org>

Short declaration of 'i' was in the middle of declarations with
assignments.  Make it a little bit more readable.  Additionally switch
from "unsigned" to "unsigned int" as this pattern is more widely used.
No functional change.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170313184750.429-4-krzk@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/exynos4210_pmu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/exynos4210_pmu.c
+++ b/hw/misc/exynos4210_pmu.c
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
                                     unsigned size)
 {
     Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
-    unsigned i;
     const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
+    unsigned int i;
 
     for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
         if (reg_p->offset == offset) {
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
                                  uint64_t val, unsigned size)
 {
     Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
-    unsigned i;
     const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
+    unsigned int i;
 
     for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
         if (reg_p->offset == offset) {
-- 
2.7.4

Recent changes have added new EXCP_ values to ARM but forgot
to update the excnames[] array which is used to provide
human-readable strings when printing information about the
exception for debug logging. Add the missing entries, and
add a comment to the list of #defines to help avoid the mistake
being repeated in future.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1491486340-25988-1-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 1 +
 target/arm/internals.h | 2 ++
 2 files changed, 3 insertions(+)

The excnames[] array is defined in internals.h because we used
to use it from two different source files for handling logging
of AArch32 and AArch64 exception entry. Refactoring means that
it's now used only in arm_log_exception() in helper.c, so move
the array into that function.

Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491821097-5647-1-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h       |  2 +-
 target/arm/internals.h | 23 -----------------------
 target/arm/helper.c    | 19 +++++++++++++++++++
 3 files changed, 20 insertions(+), 24 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define EXCP_SEMIHOST       16   /* semihosting call */
 #define EXCP_NOCP           17   /* v7M NOCP UsageFault */
 #define EXCP_INVSTATE       18   /* v7M INVSTATE UsageFault */
-/* NB: new EXCP_ defines should be added to the excnames[] array too */
+/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
 
 #define ARMV7M_EXCP_RESET   1
 #define ARMV7M_EXCP_NMI     2
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
         || excp == EXCP_SEMIHOST;
 }
 
-/* Exception names for debug logging; note that not all of these
- * precisely correspond to architectural exceptions.
- */
-static const char * const excnames[] = {
-    [EXCP_UDEF] = "Undefined Instruction",
-    [EXCP_SWI] = "SVC",
-    [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
-    [EXCP_DATA_ABORT] = "Data Abort",
-    [EXCP_IRQ] = "IRQ",
-    [EXCP_FIQ] = "FIQ",
-    [EXCP_BKPT] = "Breakpoint",
-    [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
-    [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
-    [EXCP_HVC] = "Hypervisor Call",
-    [EXCP_HYP_TRAP] = "Hypervisor Trap",
-    [EXCP_SMC] = "Secure Monitor Call",
-    [EXCP_VIRQ] = "Virtual IRQ",
-    [EXCP_VFIQ] = "Virtual FIQ",
-    [EXCP_SEMIHOST] = "Semihosting call",
-    [EXCP_NOCP] = "v7M NOCP UsageFault",
-    [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
-};
-
 /* Scale factor for generic timers, ie number of ns per tick.
  * This gives a 62.5MHz timer.
  */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
 {
     if (qemu_loglevel_mask(CPU_LOG_INT)) {
         const char *exc = NULL;
+        static const char * const excnames[] = {
+            [EXCP_UDEF] = "Undefined Instruction",
+            [EXCP_SWI] = "SVC",
+            [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
+            [EXCP_DATA_ABORT] = "Data Abort",
+            [EXCP_IRQ] = "IRQ",
+            [EXCP_FIQ] = "FIQ",
+            [EXCP_BKPT] = "Breakpoint",
+            [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
+            [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
+            [EXCP_HVC] = "Hypervisor Call",
+            [EXCP_HYP_TRAP] = "Hypervisor Trap",
+            [EXCP_SMC] = "Secure Monitor Call",
+            [EXCP_VIRQ] = "Virtual IRQ",
+            [EXCP_VFIQ] = "Virtual FIQ",
+            [EXCP_SEMIHOST] = "Semihosting call",
+            [EXCP_NOCP] = "v7M NOCP UsageFault",
+            [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
+        };
 
         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
             exc = excnames[idx];
-- 
2.7.4

In tlb_fill() we construct a syndrome register value from a
fault status register value which is filled in by arm_tlb_fill().
arm_tlb_fill() returns FSR values which might be in the format
used with short-format page descriptors, or the format used
with long-format (LPAE) descriptors. The syndrome register
always uses LPAE-format FSR status codes.

It isn't actually possible to end up delivering a syndrome
register value to the guest for a fault which is reported
with a short-format FSR (that kind of stage 1 fault will only
happen for an AArch32 translation regime which doesn't have
a syndrome register, and can never be redirected to an AArch64
or Hyp exception level). Add an assertion which checks this,
and adjust the code so that we construct a syndrome with
an invalid status code, rather than allowing set bits in
the FSR input to randomly corrupt other fields in the syndrome.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1491486152-24304-1-git-send-email-peter.maydell@linaro.org
---
 target/arm/op_helper.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
     if (unlikely(ret)) {
         ARMCPU *cpu = ARM_CPU(cs);
         CPUARMState *env = &cpu->env;
-        uint32_t syn, exc;
+        uint32_t syn, exc, fsc;
         unsigned int target_el;
         bool same_el;
 
@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
             env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
         }
         same_el = arm_current_el(env) == target_el;
-        /* AArch64 syndrome does not have an LPAE bit */
-        syn = fsr & ~(1 << 9);
+
+        if (fsr & (1 << 9)) {
+            /* LPAE format fault status register : bottom 6 bits are
+             * status code in the same form as needed for syndrome
+             */
+            fsc = extract32(fsr, 0, 6);
+        } else {
+            /* Short format FSR : this fault will never actually be reported
+             * to an EL that uses a syndrome register. Check that here,
+             * and use a (currently) reserved FSR code in case the constructed
+             * syndrome does leak into the guest somehow.
+             */
+            assert(target_el != 2 && !arm_el_is_aa64(env, target_el));
+            fsc = 0x3f;
+        }
 
         /* For insn and data aborts we assume there is no instruction syndrome
          * information; this is always true for exceptions reported to EL1.
          */
         if (access_type == MMU_INST_FETCH) {
-            syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
+            syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc);
             exc = EXCP_PREFETCH_ABORT;
         } else {
             syn = merge_syn_data_abort(env->exception.syndrome, target_el,
                                        same_el, fi.s1ptw,
-                                       access_type == MMU_DATA_STORE, syn);
+                                       access_type == MMU_DATA_STORE, fsc);
             if (access_type == MMU_DATA_STORE
                 && arm_feature(env, ARM_FEATURE_V6)) {
                 fsr |= (1 << 11);
-- 
2.7.4

Current recommended style is to log a guest error on bad register
accesses, not kill the whole system with hw_error().  Change the
hw_error() calls to log as LOG_GUEST_ERROR or LOG_UNIMP or use
g_assert_not_reached() as appropriate.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491486314-25823-1-git-send-email-peter.maydell@linaro.org
---
 hw/arm/stellaris.c | 60 +++++++++++++++++++++++++++++++++---------------------
 1 file changed, 37 insertions(+), 23 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void gptm_reload(gptm_state *s, int n, int reset)
     } else if (s->mode[n] == 0xa) {
         /* PWM mode.  Not implemented.  */
     } else {
-        hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
+        qemu_log_mask(LOG_UNIMP,
+                      "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
+                      s->mode[n]);
+        return;
     }
     s->tick[n] = tick;
     timer_mod(s->timer[n], tick);
@@ -XXX,XX +XXX,XX @@ static void gptm_tick(void *opaque)
     } else if (s->mode[n] == 0xa) {
         /* PWM mode.  Not implemented.  */
     } else {
-        hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
+        qemu_log_mask(LOG_UNIMP,
+                      "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
+                      s->mode[n]);
     }
     gptm_update_irq(s);
 }
@@ -XXX,XX +XXX,XX @@ static void gptm_write(void *opaque, hwaddr offset,
         s->match_prescale[0] = value;
         break;
     default:
-        hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "GPTM: read at bad offset 0x%x\n", (int)offset);
     }
     gptm_update_irq(s);
 }
@@ -XXX,XX +XXX,XX @@ static int ssys_board_class(const ssys_state *s)
         }
         /* for unknown classes, fall through */
     default:
-        hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
+        /* This can only happen if the hardwired constant did0 value
+         * in this board's stellaris_board_info struct is wrong.
+         */
+        g_assert_not_reached();
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
             case DID0_CLASS_SANDSTORM:
                 return pllcfg_sandstorm[xtal];
             default:
-                hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
-                return 0;
+                g_assert_not_reached();
             }
         }
     case 0x070: /* RCC2 */
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
     case 0x1e4: /* USER1 */
         return s->user1;
     default:
-        hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSYS: read at bad offset 0x%x\n", (int)offset);
         return 0;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
         s->ldoarst = value;
         break;
     default:
-        hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSYS: write at bad offset 0x%x\n", (int)offset);
     }
     ssys_update(s);
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
     case 0x20: /* MCR */
         return s->mcr;
     default:
-        hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
         return 0;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
         s->mris &= ~value;
         break;
     case 0x20: /* MCR */
-        if (value & 1)
-            hw_error(
-                      "stellaris_i2c_write: Loopback not implemented\n");
-        if (value & 0x20)
-            hw_error(
-                      "stellaris_i2c_write: Slave mode not implemented\n");
+        if (value & 1) {
+            qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
+        }
+        if (value & 0x20) {
+            qemu_log_mask(LOG_UNIMP,
+                          "stellaris_i2c: Slave mode not implemented");
+        }
         s->mcr = value & 0x31;
         break;
     default:
-        hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
-                  (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
     }
     stellaris_i2c_update(s);
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
     case 0x30: /* SAC */
         return s->sac;
     default:
-        hw_error("strllaris_adc_read: Bad offset 0x%x\n",
-                  (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
         return 0;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
             return;
         case 0x04: /* SSCTL */
             if (value != 6) {
-                hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
-                          value);
+                qemu_log_mask(LOG_UNIMP,
+                              "ADC: Unimplemented sequence %" PRIx64 "\n",
+                              value);
             }
             s->ssctl[n] = value;
             return;
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
         s->sspri = value;
         break;
     case 0x28: /* PSSI */
-        hw_error("Not implemented:  ADC sample initiate\n");
+        qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
         break;
     case 0x30: /* SAC */
         s->sac = value;
         break;
     default:
-        hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
     }
     stellaris_adc_update(s);
 }
-- 
2.7.4

From: Ishani Chugh <chugh.ishani@research.iiit.ac.in>

Signed-off-by: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 1491629987-6826-1-git-send-email-chugh.ishani@research.iiit.ac.in
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm64.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
              * single step at this point so something has gone wrong.
              */
             error_report("%s: guest single-step while debugging unsupported"
-                         " (%"PRIx64", %"PRIx32")\n",
+                         " (%"PRIx64", %"PRIx32")",
                          __func__, env->pc, debug_exit->hsr);
             return false;
         }
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
         break;
     }
     default:
-        error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")\n",
+        error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")",
                      __func__, debug_exit->hsr, env->pc);
     }
 
-- 
2.7.4

From: Suramya Shah <shah.suramya@gmail.com>

Signed-off-by: Suramya Shah <shah.suramya@gmail.com>
Message-id: 20170415180316.2694-1-shah.suramya@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/pxa2xx.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_reset(DeviceState *d)
     s->rx_start = s->rx_level = 0;
 }
 
-static int pxa2xx_ssp_init(SysBusDevice *sbd)
+static void pxa2xx_ssp_init(Object *obj)
 {
-    DeviceState *dev = DEVICE(sbd);
-    PXA2xxSSPState *s = PXA2XX_SSP(dev);
-
+    DeviceState *dev = DEVICE(obj);
+    PXA2xxSSPState *s = PXA2XX_SSP(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     sysbus_init_irq(sbd, &s->irq);
 
-    memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
+    memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
                           "pxa2xx-ssp", 0x1000);
     sysbus_init_mmio(sbd, &s->iomem);
 
     s->bus = ssi_create_bus(dev, "ssi");
-    return 0;
 }
 
 /* Real-Time Clock */
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
 
 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
 {
-    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
     DeviceClass *dc = DEVICE_CLASS(klass);
 
-    sdc->init = pxa2xx_ssp_init;
     dc->reset = pxa2xx_ssp_reset;
     dc->vmsd = &vmstate_pxa2xx_ssp;
 }
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pxa2xx_ssp_info = {
     .name          = TYPE_PXA2XX_SSP,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(PXA2xxSSPState),
+    .instance_init = pxa2xx_ssp_init,
     .class_init    = pxa2xx_ssp_class_init,
 };
 
-- 
2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

Read the correct descriptor instead of hardcoding the first (q=0).

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 988b183dcf951856d8b3379f7e911ec95233bbf4.1491947224.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/cadence_gem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
 {
     DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
     /* read current descriptor */
-    cpu_physical_memory_read(s->rx_desc_addr[0],
-                             (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0]));
+    cpu_physical_memory_read(s->rx_desc_addr[q],
+                             (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q]));
 
     /* Descriptor owned by software ? */
     if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
-- 
2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

Correct the buffer descriptor busy logic to work correctly when using
multiple queues.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 8a7e8059984e27d46a276a66299d035a0afd280f.1491947224.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/cadence_gem.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@ static int gem_can_receive(NetClientState *nc)
     }
 
     for (i = 0; i < s->num_priority_queues; i++) {
-        if (rx_desc_get_ownership(s->rx_desc[i]) == 1) {
-            if (s->can_rx_state != 2) {
-                s->can_rx_state = 2;
-                DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n",
-                         i, s->rx_desc_addr[i]);
-             }
-            return 0;
+        if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
+            break;
+        }
+    };
+
+    if (i == s->num_priority_queues) {
+        if (s->can_rx_state != 2) {
+            s->can_rx_state = 2;
+            DB_PRINT("can't receive - all the buffer descriptors are busy\n");
         }
+        return 0;
     }
 
     if (s->can_rx_state != 0) {
-- 
2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

This patch fixes two mistakes in the interrupt logic.

First we only trigger single-queue or multi-queue interrupts if the status
register is set. This logic was already used for non multi-queue interrupts
but it also applies to multi-queue interrupts.

Secondly we need to lower the interrupts if the ISR isn't set. As part
of this we can remove the other interrupt lowering logic and consolidate
it inside gem_update_int_status().

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 438bcc014f8f8a2f8f68f322cb6a53f4c04688c2.1491947224.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/cadence_gem.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@ static void gem_update_int_status(CadenceGEMState *s)
 {
     int i;
 
-    if ((s->num_priority_queues == 1) && s->regs[GEM_ISR]) {
+    if (!s->regs[GEM_ISR]) {
+        /* ISR isn't set, clear all the interrupts */
+        for (i = 0; i < s->num_priority_queues; ++i) {
+            qemu_set_irq(s->irq[i], 0);
+        }
+        return;
+    }
+
+    /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
+     * check it again.
+     */
+    if (s->num_priority_queues == 1) {
         /* No priority queues, just trigger the interrupt */
         DB_PRINT("asserting int.\n");
         qemu_set_irq(s->irq[0], 1);
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
 {
     CadenceGEMState *s;
     uint32_t retval;
-    int i;
     s = (CadenceGEMState *)opaque;
 
     offset >>= 2;
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
     switch (offset) {
     case GEM_ISR:
         DB_PRINT("lowering irqs on ISR read\n");
-        for (i = 0; i < s->num_priority_queues; ++i) {
-            qemu_set_irq(s->irq[i], 0);
-        }
+        /* The interrupts get updated at the end of the function. */
         break;
     case GEM_PHYMNTNC:
         if (retval & GEM_PHYMNTNC_OP_R) {
-- 
2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

Expose the Cadence GEM revision as a property.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 541324373cf87b50f8be0439a0cb89f5028b016f.1491947224.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/net/cadence_gem.h | 1 +
 hw/net/cadence_gem.c         | 6 +++++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
     uint8_t num_priority_queues;
     uint8_t num_type1_screeners;
     uint8_t num_type2_screeners;
+    uint32_t revision;
 
     /* GEM registers backing store */
     uint32_t regs[CADENCE_GEM_MAXREG];
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@
 #define DESC_1_RX_SOF 0x00004000
 #define DESC_1_RX_EOF 0x00008000
 
+#define GEM_MODID_VALUE 0x00020118
+
 static inline unsigned tx_desc_get_buffer(unsigned *desc)
 {
     return desc[0];
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
     s->regs[GEM_TXPAUSE] = 0x0000ffff;
     s->regs[GEM_TXPARTIALSF] = 0x000003ff;
     s->regs[GEM_RXPARTIALSF] = 0x000003ff;
-    s->regs[GEM_MODID] = 0x00020118;
+    s->regs[GEM_MODID] = s->revision;
     s->regs[GEM_DESCONF] = 0x02500111;
     s->regs[GEM_DESCONF2] = 0x2ab13fff;
     s->regs[GEM_DESCONF5] = 0x002f2145;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_cadence_gem = {
 
 static Property gem_properties[] = {
     DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
+    DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
+                       GEM_MODID_VALUE),
     DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
                       num_priority_queues, 1),
     DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
-- 
2.7.4

From: Alistair Francis <alistair.francis@xilinx.com>

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 026dbe01a1d42619eee30ce3f2079741bf04bc73.1491947224.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-zynqmp.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@
 #define ARM_PHYS_TIMER_PPI  30
 #define ARM_VIRT_TIMER_PPI  27
 
+#define GEM_REVISION        0x40070106
+
 #define GIC_BASE_ADDR       0xf9000000
 #define GIC_DIST_ADDR       0xf9010000
 #define GIC_CPU_ADDR        0xf9020000
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
         }
+        object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
+                                &error_abort);
         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
-                                  &error_abort);
+                                &error_abort);
         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
         if (err) {
             error_propagate(errp, err);
-- 
2.7.4

For M-profile CPUs, the BXJ instruction does not exist at all, and
the encoding should always UNDEF. We were accidentally implementing
it to behave like A-profile BXJ; correct the error.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1491844419-12485-2-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                         }
                         break;
                     case 4: /* bxj */
-                        /* Trivial implementation equivalent to bx.  */
+                        /* Trivial implementation equivalent to bx.
+                         * This instruction doesn't exist at all for M-profile.
+                         */
+                        if (arm_dc_feature(s, ARM_FEATURE_M)) {
+                            goto illegal_op;
+                        }
                         tmp = load_reg(s, rn);
                         gen_bx(s, tmp);
                         break;
-- 
2.7.4

In Thumb mode, the only instructions which can cause an interworking
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
ARM mode, data processing instructions which target the PC do not
cause interworking branches.

When we added support for doing interworking branches on writes to
PC from data processing instructions in commit 21aeb3430ce7ba, we
accidentally changed a Thumb instruction to have interworking
branch behaviour for writes to PC. (MOV, MOVS register-shifted
register, encoding T2; this is the standard encoding for
LSL/LSR/ASR/ROR (register).)

For this encoding, behaviour with Rd == R15 is specified as
UNPREDICTABLE, so allowing an interworking branch is within
spec, but it's confusing and differs from our handling of this
class of UNPREDICTABLE for other Thumb ALU operations. Make
it perform a simple (non-interworking) branch like the others.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491844419-12485-3-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
             gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
             if (logic_cc)
                 gen_logic_CC(tmp);
-            store_reg_bx(s, rd, tmp);
+            store_reg(s, rd, tmp);
             break;
         case 1: /* Sign/zero extend.  */
             op = (insn >> 20) & 7;
-- 
2.7.4

We currently have two places that do:
            if (dc->ss_active) {
                gen_step_complete_exception(dc);
            } else {
                gen_exception_internal(EXCP_DEBUG);
            }

Factor this out into its own function, as we're about to add
a third place that needs the same logic.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1491844419-12485-4-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
     s->is_jmp = DISAS_EXC;
 }
 
+static void gen_singlestep_exception(DisasContext *s)
+{
+    /* Generate the right kind of exception for singlestep, which is
+     * either the architectural singlestep or EXCP_DEBUG for QEMU's
+     * gdb singlestepping.
+     */
+    if (s->ss_active) {
+        gen_step_complete_exception(s);
+    } else {
+        gen_exception_internal(EXCP_DEBUG);
+    }
+}
+
 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
 {
     TCGv_i32 tmp1 = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             gen_set_pc_im(dc, dc->pc);
             /* fall through */
         default:
-            if (dc->ss_active) {
-                gen_step_complete_exception(dc);
-            } else {
-                /* FIXME: Single stepping a WFI insn will not halt
-                   the CPU.  */
-                gen_exception_internal(EXCP_DEBUG);
-            }
+            /* FIXME: Single stepping a WFI insn will not halt the CPU. */
+            gen_singlestep_exception(dc);
         }
         if (dc->condjmp) {
             /* "Condition failed" instruction codepath. */
             gen_set_label(dc->condlabel);
             gen_set_condexec(dc);
             gen_set_pc_im(dc, dc->pc);
-            if (dc->ss_active) {
-                gen_step_complete_exception(dc);
-            } else {
-                gen_exception_internal(EXCP_DEBUG);
-            }
+            gen_singlestep_exception(dc);
         }
     } else {
         /* While branches must always occur at the end of an IT block,
-- 
2.7.4

Move the utility routines gen_set_condexec() and gen_set_pc_im()
up in the file, as we will want to use them from a function
placed earlier in the file than their current location.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1491844419-12485-5-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 31 +++++++++++++++----------------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t table_logic_cc[16] = {
     1, /* mvn */
 };
 
+static inline void gen_set_condexec(DisasContext *s)
+{
+    if (s->condexec_mask) {
+        uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        tcg_gen_movi_i32(tmp, val);
+        store_cpu_field(tmp, condexec_bits);
+    }
+}
+
+static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
+{
+    tcg_gen_movi_i32(cpu_R[15], val);
+}
+
 /* Set PC and Thumb state from an immediate address.  */
 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
 {
@@ -XXX,XX +XXX,XX @@ DO_GEN_ST(8, MO_UB)
 DO_GEN_ST(16, MO_UW)
 DO_GEN_ST(32, MO_UL)
 
-static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
-{
-    tcg_gen_movi_i32(cpu_R[15], val);
-}
-
 static inline void gen_hvc(DisasContext *s, int imm16)
 {
     /* The pre HVC helper handles cases when HVC gets trapped
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
     s->is_jmp = DISAS_SMC;
 }
 
-static inline void
-gen_set_condexec (DisasContext *s)
-{
-    if (s->condexec_mask) {
-        uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_movi_i32(tmp, val);
-        store_cpu_field(tmp, condexec_bits);
-    }
-}
-
 static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
 {
     gen_set_condexec(s);
-- 
2.7.4

Move the code to generate the "condition failed" instruction
codepath out of the if (singlestepping) {} else {}. This
will allow adding support for handling a new is_jmp type
which can't be neatly split into "singlestepping case"
versus "not singlestepping case".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1491844419-12485-6-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
     /* At this stage dc->condjmp will only be set when the skipped
        instruction was a conditional branch or trap, and the PC has
        already been written.  */
+    gen_set_condexec(dc);
     if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
         /* Unconditional and "condition passed" instruction codepath. */
-        gen_set_condexec(dc);
         switch (dc->is_jmp) {
         case DISAS_SWI:
             gen_ss_advance(dc);
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             /* FIXME: Single stepping a WFI insn will not halt the CPU. */
             gen_singlestep_exception(dc);
         }
-        if (dc->condjmp) {
-            /* "Condition failed" instruction codepath. */
-            gen_set_label(dc->condlabel);
-            gen_set_condexec(dc);
-            gen_set_pc_im(dc, dc->pc);
-            gen_singlestep_exception(dc);
-        }
     } else {
         /* While branches must always occur at the end of an IT block,
            there are a few other things that can cause us to terminate
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             - Hardware watchpoints.
            Hardware breakpoints have already been handled and skip this code.
          */
-        gen_set_condexec(dc);
         switch(dc->is_jmp) {
         case DISAS_NEXT:
             gen_goto_tb(dc, 1, dc->pc);
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
             break;
         }
-        if (dc->condjmp) {
-            gen_set_label(dc->condlabel);
-            gen_set_condexec(dc);
+    }
+
+    if (dc->condjmp) {
+        /* "Condition failed" instruction codepath for the branch/trap insn */
+        gen_set_label(dc->condlabel);
+        gen_set_condexec(dc);
+        if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
+            gen_set_pc_im(dc, dc->pc);
+            gen_singlestep_exception(dc);
+        } else {
             gen_goto_tb(dc, 1, dc->pc);
-            dc->condjmp = 0;
         }
     }
 
-- 
2.7.4

We now test for "are we singlestepping" in several places and
it's not a trivial check because we need to care about both
architectural singlestep and QEMU gdbstub singlestep. We're
also about to add another place that needs to make this check,
so pull the condition out into a function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491844419-12485-7-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_singlestep_exception(DisasContext *s)
     }
 }
 
+static inline bool is_singlestepping(DisasContext *s)
+{
+    /* Return true if we are singlestepping either because of
+     * architectural singlestep or QEMU gdbstub singlestep. This does
+     * not include the command line '-singlestep' mode which is rather
+     * misnamed as it only means "one instruction per TB" and doesn't
+     * affect the code we generate.
+     */
+    return s->singlestep_enabled || s->ss_active;
+}
+
 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
 {
     TCGv_i32 tmp1 = tcg_temp_new_i32();
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
 
 static inline void gen_jmp (DisasContext *s, uint32_t dest)
 {
-    if (unlikely(s->singlestep_enabled || s->ss_active)) {
+    if (unlikely(is_singlestepping(s))) {
         /* An indirect jump so that we still trigger the debug exception.  */
         if (s->thumb)
             dest |= 1;
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));
 
     } while (!dc->is_jmp && !tcg_op_buf_full() &&
-             !cs->singlestep_enabled &&
+             !is_singlestepping(dc) &&
              !singlestep &&
-             !dc->ss_active &&
              !end_of_page &&
              num_insns < max_insns);
 
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
        instruction was a conditional branch or trap, and the PC has
        already been written.  */
     gen_set_condexec(dc);
-    if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
+    if (unlikely(is_singlestepping(dc))) {
         /* Unconditional and "condition passed" instruction codepath. */
         switch (dc->is_jmp) {
         case DISAS_SWI:
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
         /* "Condition failed" instruction codepath for the branch/trap insn */
         gen_set_label(dc->condlabel);
         gen_set_condexec(dc);
-        if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
+        if (unlikely(is_singlestepping(dc))) {
             gen_set_pc_im(dc, dc->pc);
             gen_singlestep_exception(dc);
         } else {
-- 
2.7.4

For M profile exception-return handling we'd like to generate different
code for some instructions depending on whether we are in Handler
mode or Thread mode. This isn't the same as "are we privileged
or user", so we need an extra bit in the TB flags to distinguish.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491844419-12485-8-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 9 +++++++++
 target/arm/translate.h | 1 +
 target/arm/translate.c | 1 +
 3 files changed, 11 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
 #define ARM_TBFLAG_NS_MASK          (1 << ARM_TBFLAG_NS_SHIFT)
 #define ARM_TBFLAG_BE_DATA_SHIFT    20
 #define ARM_TBFLAG_BE_DATA_MASK     (1 << ARM_TBFLAG_BE_DATA_SHIFT)
+/* For M profile only, Handler (ie not Thread) mode */
+#define ARM_TBFLAG_HANDLER_SHIFT    21
+#define ARM_TBFLAG_HANDLER_MASK     (1 << ARM_TBFLAG_HANDLER_SHIFT)
 
 /* Bit usage when in AArch64 state */
 #define ARM_TBFLAG_TBI0_SHIFT 0        /* TBI0 for EL0/1 or TBI for EL2/3 */
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
     (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
 #define ARM_TBFLAG_BE_DATA(F) \
     (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
+#define ARM_TBFLAG_HANDLER(F) \
+    (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
 #define ARM_TBFLAG_TBI0(F) \
     (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
 #define ARM_TBFLAG_TBI1(F) \
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
     }
     *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
 
+    if (env->v7m.exception != 0) {
+        *flags |= ARM_TBFLAG_HANDLER_MASK;
+    }
+
     *cs_base = 0;
 }
 
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool vfp_enabled; /* FP enabled via FPSCR.EN */
     int vec_len;
     int vec_stride;
+    bool v7m_handler_mode;
     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
      * so that top level loop can generate correct syndrome information.
      */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
     dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
     dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
     dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
+    dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
     dc->cp_regs = cpu->cp_regs;
     dc->features = env->features;
 
-- 
2.7.4

On M profile, return from exceptions happen when code in Handler mode
executes one of the following function call return instructions:
 * POP or LDM which loads the PC
 * LDR to PC
 * BX register
and the new PC value is 0xFFxxxxxx.

QEMU tries to implement this by not treating the instruction
specially but then catching the attempt to execute from the magic
address value.  This is not ideal, because:
 * there are guest visible differences from the architecturally
   specified behaviour (for instance jumping to 0xFFxxxxxx via a
   different instruction should not cause an exception return but it
   will in the QEMU implementation)
 * we have to account for it in various places (like refusing to take
   an interrupt if the PC is at a magic value, and making sure that
   the MPU doesn't deny execution at the magic value addresses)

Drop these hacks, and instead implement exception return the way the
architecture specifies -- by having the relevant instructions check
for the magic value and raise the 'do an exception return' QEMU
internal exception immediately.

The effect on the generated code is minor:

bx lr, old code (and new code for Thread mode):
  TCG:
   mov_i32 tmp5,r14
   movi_i32 tmp6,$0xfffffffffffffffe
   and_i32 pc,tmp5,tmp6
   movi_i32 tmp6,$0x1
   and_i32 tmp5,tmp5,tmp6
   st_i32 tmp5,env,$0x218
   exit_tb $0x0
   set_label $L0
   exit_tb $0x7f2aabd61993
  x86_64 generated code:
   0x7f2aabe87019:  mov    %ebx,%ebp
   0x7f2aabe8701b:  and    $0xfffffffffffffffe,%ebp
   0x7f2aabe8701e:  mov    %ebp,0x3c(%r14)
   0x7f2aabe87022:  and    $0x1,%ebx
   0x7f2aabe87025:  mov    %ebx,0x218(%r14)
   0x7f2aabe8702c:  xor    %eax,%eax
   0x7f2aabe8702e:  jmpq   0x7f2aabe7c016

bx lr, new code when in Handler mode:
  TCG:
   mov_i32 tmp5,r14
   movi_i32 tmp6,$0xfffffffffffffffe
   and_i32 pc,tmp5,tmp6
   movi_i32 tmp6,$0x1
   and_i32 tmp5,tmp5,tmp6
   st_i32 tmp5,env,$0x218
   movi_i32 tmp5,$0xffffffffff000000
   brcond_i32 pc,tmp5,geu,$L1
   exit_tb $0x0
   set_label $L1
   movi_i32 tmp5,$0x8
   call exception_internal,$0x0,$0,env,tmp5
  x86_64 generated code:
   0x7fe8fa1264e3:  mov    %ebp,%ebx
   0x7fe8fa1264e5:  and    $0xfffffffffffffffe,%ebx
   0x7fe8fa1264e8:  mov    %ebx,0x3c(%r14)
   0x7fe8fa1264ec:  and    $0x1,%ebp
   0x7fe8fa1264ef:  mov    %ebp,0x218(%r14)
   0x7fe8fa1264f6:  cmp    $0xff000000,%ebx
   0x7fe8fa1264fc:  jae    0x7fe8fa126509
   0x7fe8fa126502:  xor    %eax,%eax
   0x7fe8fa126504:  jmpq   0x7fe8fa122016
   0x7fe8fa126509:  mov    %r14,%rdi
   0x7fe8fa12650c:  mov    $0x8,%esi
   0x7fe8fa126511:  mov    $0x56095dbeccf5,%r10
   0x7fe8fa12651b:  callq  *%r10

which is a difference of one cmp/branch-not-taken. This will
be lost in the noise of having to exit generated code and
look up the next TB anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491844419-12485-9-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.h |  4 +++
 target/arm/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++-----
 2 files changed, 64 insertions(+), 6 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 #define DISAS_HVC 8
 #define DISAS_SMC 9
 #define DISAS_YIELD 10
+/* M profile branch which might be an exception return (and so needs
+ * custom end-of-TB code)
+ */
+#define DISAS_BX_EXCRET 11
 
 #ifdef TARGET_AARCH64
 void a64_translate_init(void);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
     store_cpu_field(var, thumb);
 }
 
+/* Set PC and Thumb state from var. var is marked as dead.
+ * For M-profile CPUs, include logic to detect exception-return
+ * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
+ * and BX reg, and no others, and happens only for code in Handler mode.
+ */
+static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
+{
+    /* Generate the same code here as for a simple bx, but flag via
+     * s->is_jmp that we need to do the rest of the work later.
+     */
+    gen_bx(s, var);
+    if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
+        s->is_jmp = DISAS_BX_EXCRET;
+    }
+}
+
+static inline void gen_bx_excret_final_code(DisasContext *s)
+{
+    /* Generate the code to finish possible exception return and end the TB */
+    TCGLabel *excret_label = gen_new_label();
+
+    /* Is the new PC value in the magic range indicating exception return? */
+    tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
+    /* No: end the TB as we would for a DISAS_JMP */
+    if (is_singlestepping(s)) {
+        gen_singlestep_exception(s);
+    } else {
+        tcg_gen_exit_tb(0);
+    }
+    gen_set_label(excret_label);
+    /* Yes: this is an exception return.
+     * At this point in runtime env->regs[15] and env->thumb will hold
+     * the exception-return magic number, which do_v7m_exception_exit()
+     * will read. Nothing else will be able to see those values because
+     * the cpu-exec main loop guarantees that we will always go straight
+     * from raising the exception to the exception-handling code.
+     *
+     * gen_ss_advance(s) does nothing on M profile currently but
+     * calling it is conceptually the right thing as we have executed
+     * this instruction (compare SWI, HVC, SMC handling).
+     */
+    gen_ss_advance(s);
+    gen_exception_internal(EXCP_EXCEPTION_EXIT);
+}
+
 /* Variant of store_reg which uses branch&exchange logic when storing
    to r15 in ARM architecture v7 and above. The source must be a temporary
    and will be marked as dead. */
@@ -XXX,XX +XXX,XX @@ static inline void store_reg_bx(DisasContext *s, int reg, TCGv_i32 var)
 static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
 {
     if (reg == 15 && ENABLE_ARCH_5) {
-        gen_bx(s, var);
+        gen_bx_excret(s, var);
     } else {
         store_reg(s, reg, var);
     }
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                         tmp = tcg_temp_new_i32();
                         gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
                         if (i == 15) {
-                            gen_bx(s, tmp);
+                            gen_bx_excret(s, tmp);
                         } else if (i == rn) {
                             loaded_var = tmp;
                             loaded_base = 1;
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                 goto illegal_op;
             }
             if (rs == 15) {
-                gen_bx(s, tmp);
+                gen_bx_excret(s, tmp);
             } else {
                 store_reg(s, rs, tmp);
             }
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
                     tmp2 = tcg_temp_new_i32();
                     tcg_gen_movi_i32(tmp2, val);
                     store_reg(s, 14, tmp2);
+                    gen_bx(s, tmp);
+                } else {
+                    /* Only BX works as exception-return, not BLX */
+                    gen_bx_excret(s, tmp);
                 }
-                /* already thumb, no need to check */
-                gen_bx(s, tmp);
                 break;
             }
             break;
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
        instruction was a conditional branch or trap, and the PC has
        already been written.  */
     gen_set_condexec(dc);
-    if (unlikely(is_singlestepping(dc))) {
+    if (dc->is_jmp == DISAS_BX_EXCRET) {
+        /* Exception return branches need some special case code at the
+         * end of the TB, which is complex enough that it has to
+         * handle the single-step vs not and the condition-failed
+         * insn codepath itself.
+         */
+        gen_bx_excret_final_code(dc);
+    } else if (unlikely(is_singlestepping(dc))) {
         /* Unconditional and "condition passed" instruction codepath. */
         switch (dc->is_jmp) {
         case DISAS_SWI:
-- 
2.7.4

Now that we've rewritten M-profile exception return so that the magic
PC values are not visible to other parts of QEMU, we can delete the
special casing of them elsewhere.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1491844419-12485-10-git-send-email-peter.maydell@linaro.org
---
 target/arm/cpu.c       | 43 ++-----------------------------------------
 target/arm/translate.c |  8 --------
 2 files changed, 2 insertions(+), 49 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 }
 
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void arm_v7m_unassigned_access(CPUState *cpu, hwaddr addr,
-                                      bool is_write, bool is_exec, int opaque,
-                                      unsigned size)
-{
-    ARMCPU *arm = ARM_CPU(cpu);
-    CPUARMState *env = &arm->env;
-
-    /* ARMv7-M interrupt return works by loading a magic value into the PC.
-     * On real hardware the load causes the return to occur.  The qemu
-     * implementation performs the jump normally, then does the exception
-     * return by throwing a special exception when when the CPU tries to
-     * execute code at the magic address.
-     */
-    if (env->v7m.exception != 0 && addr >= 0xfffffff0 && is_exec) {
-        cpu->exception_index = EXCP_EXCEPTION_EXIT;
-        cpu_loop_exit(cpu);
-    }
-
-    /* In real hardware an attempt to access parts of the address space
-     * with nothing there will usually cause an external abort.
-     * However our QEMU board models are often missing device models where
-     * the guest can boot anyway with the default read-as-zero/writes-ignored
-     * behaviour that you get without a QEMU unassigned_access hook.
-     * So just return here to retain that default behaviour.
-     */
-}
-
 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 {
     CPUClass *cc = CPU_GET_CLASS(cs);
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     CPUARMState *env = &cpu->env;
     bool ret = false;
 
-    /* ARMv7-M interrupt return works by loading a magic value
-     * into the PC.  On real hardware the load causes the
-     * return to occur.  The qemu implementation performs the
-     * jump normally, then does the exception return when the
-     * CPU tries to execute code at the magic address.
-     * This will cause the magic PC value to be pushed to
-     * the stack if an interrupt occurred at the wrong time.
-     * We avoid this by disabling interrupts when
-     * pc contains a magic address.
-     *
-     * ARMv7-M interrupt masking works differently than -A or -R.
+    /* ARMv7-M interrupt masking works differently than -A or -R.
      * There is no FIQ/IRQ distinction. Instead of I and F bits
      * masking FIQ and IRQ interrupts, an exception is taken only
      * if it is higher priority than the current execution priority
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
      * currently active exception).
      */
     if (interrupt_request & CPU_INTERRUPT_HARD
-        && (armv7m_nvic_can_take_pending_exception(env->nvic))
-        && (env->regs[15] < 0xfffffff0)) {
+        && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
         cs->exception_index = EXCP_IRQ;
         cc->do_interrupt(cs);
         ret = true;
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 #endif
 
-    cc->do_unassigned_access = arm_v7m_unassigned_access;
     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 }
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             dc->is_jmp = DISAS_EXC;
             break;
         }
-#else
-        if (arm_dc_feature(dc, ARM_FEATURE_M)) {
-            /* Branches to the magic exception-return addresses should
-             * already have been caught via the arm_v7m_unassigned_access hook,
-             * and never get here.
-             */
-            assert(dc->pc < 0xfffffff0);
-        }
 #endif
 
         if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
-- 
2.7.4

Handful of bugfixes for rc2. None of these are particularly critical
or exciting.

-- PMM

The following changes since commit 45a150aa2b3492acf6691c7bdbeb25a8545d8345:

Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' into staging (2020-08-03 15:13:49 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200803

for you to fetch changes up to 13557fd392890cbd985bceba7f717e01efd674b8:

hw/timer/imx_epit: Avoid assertion when CR.SWR is written (2020-08-03 17:56:11 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/timer/imx_epit: Avoid assertion when CR.SWR is written
 * netduino2, netduinoplus2, microbit: set system_clock_scale so that
   SysTick running on the CPU clock works
 * target/arm: Avoid maybe-uninitialized warning with gcc 4.9
 * target/arm: Fix AddPAC error indication
 * Make AIRCR.SYSRESETREQ actually reset the system for the
   microbit, mps2-*, musca-*, netduino* boards

----------------------------------------------------------------
Kaige Li (1):
      target/arm: Avoid maybe-uninitialized warning with gcc 4.9

Peter Maydell (6):
      hw/arm/netduino2, netduinoplus2: Set system_clock_scale
      include/hw/irq.h: New function qemu_irq_is_connected()
      hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
      msf2-soc, stellaris: Don't wire up SYSRESETREQ
      hw/arm/nrf51_soc: Set system_clock_scale
      hw/timer/imx_epit: Avoid assertion when CR.SWR is written

Richard Henderson (1):
      target/arm: Fix AddPAC error indication

include/hw/arm/armv7m.h           |  4 +++-
 include/hw/irq.h                  | 18 ++++++++++++++++++
 hw/arm/msf2-soc.c                 | 11 -----------
 hw/arm/netduino2.c                | 10 ++++++++++
 hw/arm/netduinoplus2.c            | 10 ++++++++++
 hw/arm/nrf51_soc.c                |  5 +++++
 hw/arm/stellaris.c                | 12 ------------
 hw/intc/armv7m_nvic.c             | 17 ++++++++++++++++-
 hw/timer/imx_epit.c               | 13 ++++++++++---
 target/arm/pauth_helper.c         |  6 +++++-
 target/arm/translate-a64.c        |  2 +-
 tests/tcg/aarch64/pauth-5.c       | 33 +++++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  2 +-
 13 files changed, 112 insertions(+), 31 deletions(-)
 create mode 100644 tests/tcg/aarch64/pauth-5.c

The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
global, which meant that if guest code used the systick timer in "use
the processor clock" mode it would hang because time never advances.

Set the global to match the documented CPU clock speed of these boards.
Judging by the data sheet this is slightly simplistic because the
SoC allows configuration of the SYSCLK source and frequency via the
RCC (reset and clock control) module, but we don't model that.

Fixes: https://bugs.launchpad.net/qemu/+bug/1876187
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200727162617.26227-1-peter.maydell@linaro.org
---
 hw/arm/netduino2.c     | 10 ++++++++++
 hw/arm/netduinoplus2.c | 10 ++++++++++
 2 files changed, 20 insertions(+)

diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/stm32f205_soc.h"
 #include "hw/arm/boot.h"
 
+/* Main SYSCLK frequency in Hz (120MHz) */
+#define SYSCLK_FRQ 120000000ULL
+
 static void netduino2_init(MachineState *machine)
 {
     DeviceState *dev;
 
+    /*
+     * TODO: ideally we would model the SoC RCC and let it handle
+     * system_clock_scale, including its ability to define different
+     * possible SYSCLK sources.
+     */
+    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+
     dev = qdev_new(TYPE_STM32F205_SOC);
     qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/stm32f405_soc.h"
 #include "hw/arm/boot.h"
 
+/* Main SYSCLK frequency in Hz (168MHz) */
+#define SYSCLK_FRQ 168000000ULL
+
 static void netduinoplus2_init(MachineState *machine)
 {
     DeviceState *dev;
 
+    /*
+     * TODO: ideally we would model the SoC RCC and let it handle
+     * system_clock_scale, including its ability to define different
+     * possible SYSCLK sources.
+     */
+    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+
     dev = qdev_new(TYPE_STM32F405_SOC);
     qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-- 
2.20.1

Mostly devices don't need to care whether one of their output
qemu_irq lines is connected, because functions like qemu_set_irq()
silently do nothing if there is nothing on the other end.  However
sometimes a device might want to implement default behaviour for the
case where the machine hasn't wired the line up to anywhere.

Provide a function qemu_irq_is_connected() that devices can use for
this purpose.  (The test is trivial but encapsulating it in a
function makes it easier to see where we're doing it in case we need
to change the implementation later.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200728103744.6909-2-peter.maydell@linaro.org
---
 include/hw/irq.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/include/hw/irq.h b/include/hw/irq.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
    on an existing vector of qemu_irq.  */
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
 
+/**
+ * qemu_irq_is_connected: Return true if IRQ line is wired up
+ *
+ * If a qemu_irq has a device on the other (receiving) end of it,
+ * return true; otherwise return false.
+ *
+ * Usually device models don't need to care whether the machine model
+ * has wired up their outbound qemu_irq lines, because functions like
+ * qemu_set_irq() silently do nothing if there is nothing on the other
+ * end of the line. However occasionally a device model will want to
+ * provide default behaviour if its output is left floating, and
+ * it can use this function to identify when that is the case.
+ */
+static inline bool qemu_irq_is_connected(qemu_irq irq)
+{
+    return irq != NULL;
+}
+
 #endif
-- 
2.20.1

The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals
when the guest sets the SYSRESETREQ bit in the AIRCR register.  This
matches the hardware design (where the CPU has a signal of this name
and it is up to the SoC to connect that up to an actual reset
mechanism), but in QEMU it mostly results in duplicated code in SoC
objects and bugs where SoC model implementors forget to wire up the
SYSRESETREQ line.

Provide a default behaviour for the case where SYSRESETREQ is not
actually connected to anything: use qemu_system_reset_request() to
perform a system reset.  This will allow us to remove the
implementations of SYSRESETREQ handling from the boards where that's
exactly what it does, and also fixes the bugs in the board models
which forgot to wire up the signal:

* microbit
 * mps2-an385
 * mps2-an505
 * mps2-an511
 * mps2-an521
 * musca-a
 * musca-b1
 * netduino
 * netduinoplus2

We still allow the board to wire up the signal if it needs to, in case
we need to model more complicated reset controller logic or to model
buggy SoC hardware which forgot to wire up the line itself. But
defaulting to "reset the system" is more often going to be correct
than defaulting to "do nothing".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200728103744.6909-3-peter.maydell@linaro.org
---
 include/hw/arm/armv7m.h |  4 +++-
 hw/intc/armv7m_nvic.c   | 17 ++++++++++++++++-
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 /* ARMv7M container object.
  * + Unnamed GPIO input lines: external IRQ lines for the NVIC
- * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
+ *   If this GPIO is not wired up then the NVIC will default to performing
+ *   a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
  * + Property "cpu-type": CPU type to instantiate
  * + Property "num-irq": number of external IRQ lines
  * + Property "memory": MemoryRegion defining the physical address space
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/intc/armv7m_nvic.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
+#include "sysemu/runstate.h"
 #include "target/arm/cpu.h"
 #include "exec/exec-all.h"
 #include "exec/memop.h"
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
     0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
 };
 
+static void signal_sysresetreq(NVICState *s)
+{
+    if (qemu_irq_is_connected(s->sysresetreq)) {
+        qemu_irq_pulse(s->sysresetreq);
+    } else {
+        /*
+         * Default behaviour if the SoC doesn't need to wire up
+         * SYSRESETREQ (eg to a system reset controller of some kind):
+         * perform a system reset via the usual QEMU API.
+         */
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+    }
+}
+
 static int nvic_pending_prio(NVICState *s)
 {
     /* return the group priority of the current pending interrupt,
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
             if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
                 if (attrs.secure ||
                     !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
-                    qemu_irq_pulse(s->sysresetreq);
+                    signal_sysresetreq(s);
                 }
             }
             if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
-- 
2.20.1

The MSF2 SoC model and the Stellaris board code both wire
SYSRESETREQ up to a function that just invokes
    qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
This is now the default action that the NVIC does if the line is
not connected, so we can delete the handling code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200728103744.6909-4-peter.maydell@linaro.org
---
 hw/arm/msf2-soc.c  | 11 -----------
 hw/arm/stellaris.c | 12 ------------
 2 files changed, 23 deletions(-)

diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "hw/arm/msf2-soc.h"
 #include "hw/misc/unimp.h"
-#include "sysemu/runstate.h"
 #include "sysemu/sysemu.h"
 
 #define MSF2_TIMER_BASE       0x40004000
@@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
 static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
 static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
 
-static void do_sys_reset(void *opaque, int n, int level)
-{
-    if (level) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-    }
-}
-
 static void m2sxxx_soc_initfn(Object *obj)
 {
     MSF2State *s = MSF2_SOC(obj);
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
         return;
     }
 
-    qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
-                                qemu_allocate_irq(&do_sys_reset, NULL, 0));
-
     system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
 
     for (i = 0; i < MSF2_NUM_UARTS; i++) {
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "qemu/log.h"
 #include "exec/address-spaces.h"
-#include "sysemu/runstate.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/armv7m.h"
 #include "hw/char/pl011.h"
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
 }
 
-static
-void do_sys_reset(void *opaque, int n, int level)
-{
-    if (level) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-    }
-}
-
 /* Board init.  */
 static stellaris_board_info stellaris_boards[] = {
   { "LM3S811EVB",
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
     /* This will exit with an error if the user passed us a bad cpu_type */
     sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
 
-    qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
-                                qemu_allocate_irq(&do_sys_reset, NULL, 0));
-
     if (board->dc1 & (1 << 16)) {
         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
                                     qdev_get_gpio_in(nvic, 14),
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The definition of top_bit used in this function is one higher
than that used in the Arm ARM psuedo-code, which put the error
indication at top_bit - 1 at the wrong place, which meant that
it wasn't visible to Auth.

Fixing the definition of top_bit requires more changes, because
its most common use is for the count of bits in top_bit:bot_bit,
which would then need to be computed as top_bit - bot_bit + 1.

For now, prefer the minimal fix to the error indication alone.

Fixes: 63ff0ca94cb
Reported-by: Derrick McKee <derrick.mckee@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200728195706.11087-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: added comment about the divergence from the pseudocode]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/pauth_helper.c         |  6 +++++-
 tests/tcg/aarch64/pauth-5.c       | 33 +++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  2 +-
 3 files changed, 39 insertions(+), 2 deletions(-)
 create mode 100644 tests/tcg/aarch64/pauth-5.c

diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/pauth_helper.c
+++ b/target/arm/pauth_helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
      */
     test = sextract64(ptr, bot_bit, top_bit - bot_bit);
     if (test != 0 && test != -1) {
-        pac ^= MAKE_64BIT_MASK(top_bit - 1, 1);
+        /*
+         * Note that our top_bit is one greater than the pseudocode's
+         * version, hence "- 2" here.
+         */
+        pac ^= MAKE_64BIT_MASK(top_bit - 2, 1);
     }
 
     /*
diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/aarch64/pauth-5.c
@@ -XXX,XX +XXX,XX @@
+#include <assert.h>
+
+static int x;
+
+int main()
+{
+    int *p0 = &x, *p1, *p2, *p3;
+    unsigned long salt = 0;
+
+    /*
+     * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so
+     * a 1/128 chance of auth = pac(ptr,key,salt) producing zero.
+     * Find a salt that creates auth != 0.
+     */
+    do {
+        salt++;
+        asm("pacda %0, %1" : "=r"(p1) : "r"(salt), "0"(p0));
+    } while (p0 == p1);
+
+    /*
+     * This pac must fail, because the input pointer bears an encryption,
+     * and so is not properly extended within bits [55:47].  This will
+     * toggle bit 54 in the output...
+     */
+    asm("pacda %0, %1" : "=r"(p2) : "r"(salt), "0"(p1));
+
+    /* ... so that the aut must fail, setting bit 53 in the output ... */
+    asm("autda %0, %1" : "=r"(p3) : "r"(salt), "0"(p2));
+
+    /* ... which means this equality must not hold. */
+    assert(p3 != p0);
+    return 0;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
 
 # Pauth Tests
 ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_3),)
-AARCH64_TESTS += pauth-1 pauth-2 pauth-4
+AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5
 pauth-%: CFLAGS += -march=armv8.3-a
 run-pauth-%: QEMU_OPTS += -cpu max
 run-plugin-pauth-%: QEMU_OPTS += -cpu max
-- 
2.20.1

From: Kaige Li <likaige@loongson.cn>

GCC version 4.9.4 isn't clever enough to figure out that all
execution paths in disas_ldst() that use 'fn' will have initialized
it first, and so it warns:

/home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’:
/home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
     fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
     ^
/home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here
     AtomicThreeOpFn *fn;
                      ^

Make it happy by initializing the variable to NULL.

Signed-off-by: Kaige Li <likaige@loongson.cn>
Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Clean up commit message and note which gcc version this was]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
     bool r = extract32(insn, 22, 1);
     bool a = extract32(insn, 23, 1);
     TCGv_i64 tcg_rs, clean_addr;
-    AtomicThreeOpFn *fn;
+    AtomicThreeOpFn *fn = NULL;
 
     if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
         unallocated_encoding(s);
-- 
2.20.1

The nrf51 SoC model wasn't setting the system_clock_scale
global.which meant that if guest code used the systick timer in "use
the processor clock" mode it would hang because time never advances.

Set the global to match the documented CPU clock speed for this SoC.

This SoC in fact doesn't have a SysTick timer (which is the only thing
currently that cares about the system_clock_scale), because it's
a configurable option in the Cortex-M0. However our Cortex-M0 and
thus our nrf51 and our micro:bit board do provide a SysTick, so
we ought to provide a functional one rather than a broken one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
---
 hw/arm/nrf51_soc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -XXX,XX +XXX,XX @@
 
 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
 
+/* HCLK (the main CPU clock) on this SoC is always 16MHz */
+#define HCLK_FRQ 16000000
+
 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
 {
     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
         return;
     }
 
+    system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
+
     object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
                              &error_abort);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
-- 
2.20.1

The imx_epit device has a software-controllable reset triggered by
setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
means that we will end up assert()ing if the guest does this, because
the code in imx_epit_write() starts ptimer transactions, and then
imx_epit_reset() also starts ptimer transactions, triggering
"ptimer_transaction_begin: Assertion `!s->in_transaction' failed".

The cleanest way to avoid this double-transaction is to move the
start-transaction for the CR write handling down below the check of
the SWR bit.

Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
Fixes: cc2722ec83ad944505fe
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
---
 hw/timer/imx_epit.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
 
     switch (offset >> 2) {
     case 0: /* CR */
-        ptimer_transaction_begin(s->timer_cmp);
-        ptimer_transaction_begin(s->timer_reload);
 
         oldcr = s->cr;
         s->cr = value & 0x03ffffff;
         if (s->cr & CR_SWR) {
             /* handle the reset */
             imx_epit_reset(DEVICE(s));
-        } else {
+            /*
+             * TODO: could we 'break' here? following operations appear
+             * to duplicate the work imx_epit_reset() already did.
+             */
+        }
+
+        ptimer_transaction_begin(s->timer_cmp);
+        ptimer_transaction_begin(s->timer_reload);
+
+        if (!(s->cr & CR_SWR)) {
             imx_epit_set_freq(s);
         }
 
-- 
2.20.1