[Qemu-devel] [PULL 00/24] target-arm queue
[Qemu-devel] [PULL 00/10] target-arm queue
1
First ARM pullreq of the 2.10 cycle...
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target-arm queue for rc1 -- these are all bug fixes.
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3
thanks
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 64c8ed97cceabac4fafe17fca8d88ef08183f439:
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The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2:
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Open 2.10 development tree (2017-04-20 15:42:31 +0100)
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Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170420
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715
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for you to fetch changes up to f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa:
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for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19:
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arm: Remove workarounds for old M-profile exception return implementation (2017-04-20 17:39:17 +0100)
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target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100)
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----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* implement M profile exception return properly
20
* report ARMv8-A FP support for AArch32 -cpu max
21
* cadence GEM: fix multiqueue handling bugs
21
* hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
22
* pxa2xx.c: QOMify a device
22
* hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
23
* arm/kvm: Remove trailing newlines from error_report()
23
* hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
24
* stellaris: Don't hw_error() on bad register accesses
24
* hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
25
* Add assertion about FSC format for syndrome registers
25
* hw/arm/virt: Fix non-secure flash mode
26
* Move excnames[] array into arm_log_exceptions()
26
* pl031: Correctly migrate state when using -rtc clock=host
27
* exynos: minor code cleanups
27
* fix regression that meant arm926 and arm1026 lost VFP
28
* hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
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double-precision support
29
* Fix APSR writes via M profile MSR
29
* v8M: NS BusFault on vector table fetch escalates to NS HardFault
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30
31
----------------------------------------------------------------
31
----------------------------------------------------------------
32
Alistair Francis (5):
32
Alex Bennée (1):
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cadence_gem: Read the correct queue descriptor
33
target/arm: report ARMv8-A FP support for AArch32 -cpu max
34
cadence_gem: Correct the multi-queue can rx logic
35
cadence_gem: Correct the interupt logic
36
cadence_gem: Make the revision a property
37
xlnx-zynqmp: Set the Cadence GEM revision
38
34
39
Ard Biesheuvel (1):
35
David Engraf (1):
40
hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
36
hw/arm/virt: Fix non-secure flash mode
41
37
42
Ishani Chugh (1):
38
Peter Maydell (3):
43
arm/kvm: Remove trailing newlines from error_report()
39
pl031: Correctly migrate state when using -rtc clock=host
40
target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
41
target/arm: NS BusFault on vector table fetch escalates to NS HardFault
44
42
45
Krzysztof Kozlowski (3):
43
Philippe Mathieu-Daudé (5):
46
hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
44
hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
47
hw/char/exynos4210_uart: Constify static array and few arguments
45
hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
48
hw/misc/exynos4210_pmu: Reorder local variables for readability
46
hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
47
hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
48
hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
49
49
50
Peter Maydell (13):
50
include/hw/timer/pl031.h | 2 ++
51
target/arm: Add missing entries to excnames[] for log strings
51
hw/arm/virt.c | 2 +-
52
arm: Move excnames[] array into arm_log_exceptions()
52
hw/core/machine.c | 1 +
53
target/arm: Add assertion about FSC format for syndrome registers
53
hw/display/xlnx_dp.c | 15 +++++---
54
stellaris: Don't hw_error() on bad register accesses
54
hw/ssi/mss-spi.c | 8 ++++-
55
arm: Don't implement BXJ on M-profile CPUs
55
hw/ssi/xilinx_spips.c | 43 +++++++++++++++-------
56
arm: Thumb shift operations should not permit interworking branches
56
hw/timer/pl031.c | 92 +++++++++++++++++++++++++++++++++++++++++++++---
57
arm: Factor out "generate right kind of step exception"
57
target/arm/cpu.c | 16 +++++++++
58
arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
58
target/arm/m_helper.c | 21 ++++++++---
59
arm: Move condition-failed codepath generation out of if()
59
9 files changed, 174 insertions(+), 26 deletions(-)
60
arm: Abstract out "are we singlestepping" test to utility function
61
arm: Track M profile handler mode state in TB flags
62
arm: Implement M profile exception return properly
63
arm: Remove workarounds for old M-profile exception return implementation
64
60
65
Suramya Shah (1):
66
hw/arm: Qomify pxa2xx.c
67
68
include/hw/net/cadence_gem.h | 1 +
69
target/arm/cpu.h | 10 +++
70
target/arm/internals.h | 21 -----
71
target/arm/translate.h | 5 ++
72
hw/arm/boot.c | 64 ++++++++++++---
73
hw/arm/exynos4_boards.c | 7 +-
74
hw/arm/pxa2xx.c | 14 ++--
75
hw/arm/stellaris.c | 60 ++++++++------
76
hw/arm/xlnx-zynqmp.c | 6 +-
77
hw/char/exynos4210_uart.c | 8 +-
78
hw/misc/exynos4210_pmu.c | 4 +-
79
hw/net/cadence_gem.c | 45 +++++++----
80
hw/timer/exynos4210_mct.c | 6 +-
81
hw/timer/exynos4210_pwm.c | 13 ++--
82
hw/timer/exynos4210_rtc.c | 19 ++---
83
target/arm/cpu.c | 43 +---------
84
target/arm/helper.c | 19 +++++
85
target/arm/kvm64.c | 4 +-
86
target/arm/op_helper.c | 23 ++++--
87
target/arm/translate.c | 181 +++++++++++++++++++++++++++++--------------
88
20 files changed, 341 insertions(+), 212 deletions(-)
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/24] arm/kvm: Remove trailing newlines from error_report()
[Qemu-devel] [PULL 01/10] target/arm: report ARMv8-A FP support for AArch32 -cpu max
1
From: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Signed-off-by: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
3
When we converted to using feature bits in 602f6e42cfbf we missed out
4
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
4
the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for
5
Message-id: 1491629987-6826-1-git-send-email-chugh.ishani@research.iiit.ac.in
5
-cpu max configurations. This caused a regression in the GCC test
6
suite. Fix this by setting the appropriate bits in mvfr1.FPHP to
7
report ARMv8-A with FP support (but not ARMv8.2-FP16).
8
9
Fixes: https://bugs.launchpad.net/qemu/+bug/1836078
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20190711103737.10017-1-alex.bennee@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
14
---
8
target/arm/kvm64.c | 4 ++--
15
target/arm/cpu.c | 4 ++++
9
1 file changed, 2 insertions(+), 2 deletions(-)
16
1 file changed, 4 insertions(+)
10
17
11
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
18
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/kvm64.c
20
--- a/target/arm/cpu.c
14
+++ b/target/arm/kvm64.c
21
+++ b/target/arm/cpu.c
15
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
22
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
16
* single step at this point so something has gone wrong.
23
t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
17
*/
24
cpu->isar.id_isar6 = t;
18
error_report("%s: guest single-step while debugging unsupported"
25
19
- " (%"PRIx64", %"PRIx32")\n",
26
+ t = cpu->isar.mvfr1;
20
+ " (%"PRIx64", %"PRIx32")",
27
+ t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */
21
__func__, env->pc, debug_exit->hsr);
28
+ cpu->isar.mvfr1 = t;
22
return false;
29
+
23
}
30
t = cpu->isar.mvfr2;
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
31
t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
25
break;
32
t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
26
}
27
default:
28
- error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")\n",
29
+ error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")",
30
__func__, debug_exit->hsr, env->pc);
31
}
32
33
--
33
--
34
2.7.4
34
2.20.1
35
35
36
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/24] hw/char/exynos4210_uart: Constify static array and few arguments
[Qemu-devel] [PULL 02/10] hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
The static array exynos4210_uart_regs with register values is not
3
In the next commit we will implement the write_with_attrs()
4
modified so it can be made const.
4
handler. To avoid using different APIs, convert the read()
5
handler first.
5
6
6
Few other functions accept driver or uart state as an argument but they
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
do not change it and do not cast it so this can be made const for code
8
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
safeness.
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
10
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
11
Message-id: 20170313184750.429-3-krzk@kernel.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
hw/char/exynos4210_uart.c | 8 ++++----
12
hw/ssi/xilinx_spips.c | 23 +++++++++++------------
16
1 file changed, 4 insertions(+), 4 deletions(-)
13
1 file changed, 11 insertions(+), 12 deletions(-)
17
14
18
diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
15
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/exynos4210_uart.c
17
--- a/hw/ssi/xilinx_spips.c
21
+++ b/hw/char/exynos4210_uart.c
18
+++ b/hw/ssi/xilinx_spips.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210UartReg {
19
@@ -XXX,XX +XXX,XX @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
23
uint32_t reset_value;
20
}
24
} Exynos4210UartReg;
25
26
-static Exynos4210UartReg exynos4210_uart_regs[] = {
27
+static const Exynos4210UartReg exynos4210_uart_regs[] = {
28
{"ULCON", ULCON, 0x00000000},
29
{"UCON", UCON, 0x00003000},
30
{"UFCON", UFCON, 0x00000000},
31
@@ -XXX,XX +XXX,XX @@ static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
32
return ret;
33
}
21
}
34
22
35
-static int fifo_elements_number(Exynos4210UartFIFO *q)
23
-static uint64_t
36
+static int fifo_elements_number(const Exynos4210UartFIFO *q)
24
-lqspi_read(void *opaque, hwaddr addr, unsigned int size)
25
+static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
26
+ unsigned size, MemTxAttrs attrs)
37
{
27
{
38
if (q->sp < q->rp) {
28
- XilinxQSPIPS *q = opaque;
39
return q->size - q->rp + q->sp;
29
- uint32_t ret;
40
@@ -XXX,XX +XXX,XX @@ static int fifo_elements_number(Exynos4210UartFIFO *q)
30
+ XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
41
return q->sp - q->rp;
31
32
if (addr >= q->lqspi_cached_addr &&
33
addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
34
uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
35
- ret = cpu_to_le32(*(uint32_t *)retp);
36
- DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
37
- (unsigned)ret);
38
- return ret;
39
- } else {
40
- lqspi_load_cache(opaque, addr);
41
- return lqspi_read(opaque, addr, size);
42
+ *value = cpu_to_le32(*(uint32_t *)retp);
43
+ DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n",
44
+ addr, *value);
45
+ return MEMTX_OK;
46
}
47
+
48
+ lqspi_load_cache(opaque, addr);
49
+ return lqspi_read(opaque, addr, value, size, attrs);
42
}
50
}
43
51
44
-static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
52
static const MemoryRegionOps lqspi_ops = {
45
+static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
53
- .read = lqspi_read,
46
{
54
+ .read_with_attrs = lqspi_read,
47
return q->size - fifo_elements_number(q);
55
.endianness = DEVICE_NATIVE_ENDIAN,
48
}
56
.valid = {
49
@@ -XXX,XX +XXX,XX @@ static void fifo_reset(Exynos4210UartFIFO *q)
57
.min_access_size = 1,
50
q->rp = 0;
51
}
52
53
-static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
54
+static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
55
{
56
uint32_t level = 0;
57
uint32_t reg;
58
--
58
--
59
2.7.4
59
2.20.1
60
60
61
61
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/24] arm: Implement M profile exception return properly
[Qemu-devel] [PULL 03/10] hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
1
On M profile, return from exceptions happen when code in Handler mode
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
executes one of the following function call return instructions:
3
* POP or LDM which loads the PC
4
* LDR to PC
5
* BX register
6
and the new PC value is 0xFFxxxxxx.
7
2
8
QEMU tries to implement this by not treating the instruction
3
Lei Sun found while auditing the code that a CPU write would
9
specially but then catching the attempt to execute from the magic
4
trigger a NULL pointer dereference.
10
address value. This is not ideal, because:
11
* there are guest visible differences from the architecturally
12
specified behaviour (for instance jumping to 0xFFxxxxxx via a
13
different instruction should not cause an exception return but it
14
will in the QEMU implementation)
15
* we have to account for it in various places (like refusing to take
16
an interrupt if the PC is at a magic value, and making sure that
17
the MPU doesn't deny execution at the magic value addresses)
18
5
19
Drop these hacks, and instead implement exception return the way the
6
>From UG1085 datasheet [*] AXI writes in this region are ignored
20
architecture specifies -- by having the relevant instructions check
7
and generates an AXI Slave Error (SLVERR).
21
for the magic value and raise the 'do an exception return' QEMU
22
internal exception immediately.
23
8
24
The effect on the generated code is minor:
9
Fix by implementing the write_with_attrs() handler.
10
Return MEMTX_ERROR when the region is accessed (this error maps
11
to an AXI slave error).
25
12
26
bx lr, old code (and new code for Thread mode):
13
[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
27
TCG:
28
mov_i32 tmp5,r14
29
movi_i32 tmp6,$0xfffffffffffffffe
30
and_i32 pc,tmp5,tmp6
31
movi_i32 tmp6,$0x1
32
and_i32 tmp5,tmp5,tmp6
33
st_i32 tmp5,env,$0x218
34
exit_tb $0x0
35
set_label $L0
36
exit_tb $0x7f2aabd61993
37
x86_64 generated code:
38
0x7f2aabe87019: mov %ebx,%ebp
39
0x7f2aabe8701b: and $0xfffffffffffffffe,%ebp
40
0x7f2aabe8701e: mov %ebp,0x3c(%r14)
41
0x7f2aabe87022: and $0x1,%ebx
42
0x7f2aabe87025: mov %ebx,0x218(%r14)
43
0x7f2aabe8702c: xor %eax,%eax
44
0x7f2aabe8702e: jmpq 0x7f2aabe7c016
45
14
46
bx lr, new code when in Handler mode:
15
Reported-by: Lei Sun <slei.casper@gmail.com>
47
TCG:
16
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
48
mov_i32 tmp5,r14
17
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
49
movi_i32 tmp6,$0xfffffffffffffffe
18
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
50
and_i32 pc,tmp5,tmp6
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
51
movi_i32 tmp6,$0x1
20
---
52
and_i32 tmp5,tmp5,tmp6
21
hw/ssi/xilinx_spips.c | 16 ++++++++++++++++
53
st_i32 tmp5,env,$0x218
22
1 file changed, 16 insertions(+)
54
movi_i32 tmp5,$0xffffffffff000000
55
brcond_i32 pc,tmp5,geu,$L1
56
exit_tb $0x0
57
set_label $L1
58
movi_i32 tmp5,$0x8
59
call exception_internal,$0x0,$0,env,tmp5
60
x86_64 generated code:
61
0x7fe8fa1264e3: mov %ebp,%ebx
62
0x7fe8fa1264e5: and $0xfffffffffffffffe,%ebx
63
0x7fe8fa1264e8: mov %ebx,0x3c(%r14)
64
0x7fe8fa1264ec: and $0x1,%ebp
65
0x7fe8fa1264ef: mov %ebp,0x218(%r14)
66
0x7fe8fa1264f6: cmp $0xff000000,%ebx
67
0x7fe8fa1264fc: jae 0x7fe8fa126509
68
0x7fe8fa126502: xor %eax,%eax
69
0x7fe8fa126504: jmpq 0x7fe8fa122016
70
0x7fe8fa126509: mov %r14,%rdi
71
0x7fe8fa12650c: mov $0x8,%esi
72
0x7fe8fa126511: mov $0x56095dbeccf5,%r10
73
0x7fe8fa12651b: callq *%r10
74
23
75
which is a difference of one cmp/branch-not-taken. This will
24
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
76
be lost in the noise of having to exit generated code and
77
look up the next TB anyway.
78
79
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80
Reviewed-by: Richard Henderson <rth@twiddle.net>
81
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
82
Message-id: 1491844419-12485-9-git-send-email-peter.maydell@linaro.org
83
---
84
target/arm/translate.h | 4 +++
85
target/arm/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++-----
86
2 files changed, 64 insertions(+), 6 deletions(-)
87
88
diff --git a/target/arm/translate.h b/target/arm/translate.h
89
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/translate.h
26
--- a/hw/ssi/xilinx_spips.c
91
+++ b/target/arm/translate.h
27
+++ b/hw/ssi/xilinx_spips.c
92
@@ -XXX,XX +XXX,XX @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
28
@@ -XXX,XX +XXX,XX @@ static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
93
#define DISAS_HVC 8
29
return lqspi_read(opaque, addr, value, size, attrs);
94
#define DISAS_SMC 9
95
#define DISAS_YIELD 10
96
+/* M profile branch which might be an exception return (and so needs
97
+ * custom end-of-TB code)
98
+ */
99
+#define DISAS_BX_EXCRET 11
100
101
#ifdef TARGET_AARCH64
102
void a64_translate_init(void);
103
diff --git a/target/arm/translate.c b/target/arm/translate.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/translate.c
106
+++ b/target/arm/translate.c
107
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
108
store_cpu_field(var, thumb);
109
}
30
}
110
31
111
+/* Set PC and Thumb state from var. var is marked as dead.
32
+static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
112
+ * For M-profile CPUs, include logic to detect exception-return
33
+ unsigned size, MemTxAttrs attrs)
113
+ * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
114
+ * and BX reg, and no others, and happens only for code in Handler mode.
115
+ */
116
+static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
117
+{
34
+{
118
+ /* Generate the same code here as for a simple bx, but flag via
35
+ /*
119
+ * s->is_jmp that we need to do the rest of the work later.
36
+ * From UG1085, Chapter 24 (Quad-SPI controllers):
37
+ * - Writes are ignored
38
+ * - AXI writes generate an external AXI slave error (SLVERR)
120
+ */
39
+ */
121
+ gen_bx(s, var);
40
+ qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64
122
+ if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
41
+ " (value: 0x%" PRIx64 "\n",
123
+ s->is_jmp = DISAS_BX_EXCRET;
42
+ __func__, size << 3, offset, value);
124
+ }
43
+
44
+ return MEMTX_ERROR;
125
+}
45
+}
126
+
46
+
127
+static inline void gen_bx_excret_final_code(DisasContext *s)
47
static const MemoryRegionOps lqspi_ops = {
128
+{
48
.read_with_attrs = lqspi_read,
129
+ /* Generate the code to finish possible exception return and end the TB */
49
+ .write_with_attrs = lqspi_write,
130
+ TCGLabel *excret_label = gen_new_label();
50
.endianness = DEVICE_NATIVE_ENDIAN,
131
+
51
.valid = {
132
+ /* Is the new PC value in the magic range indicating exception return? */
52
.min_access_size = 1,
133
+ tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
134
+ /* No: end the TB as we would for a DISAS_JMP */
135
+ if (is_singlestepping(s)) {
136
+ gen_singlestep_exception(s);
137
+ } else {
138
+ tcg_gen_exit_tb(0);
139
+ }
140
+ gen_set_label(excret_label);
141
+ /* Yes: this is an exception return.
142
+ * At this point in runtime env->regs[15] and env->thumb will hold
143
+ * the exception-return magic number, which do_v7m_exception_exit()
144
+ * will read. Nothing else will be able to see those values because
145
+ * the cpu-exec main loop guarantees that we will always go straight
146
+ * from raising the exception to the exception-handling code.
147
+ *
148
+ * gen_ss_advance(s) does nothing on M profile currently but
149
+ * calling it is conceptually the right thing as we have executed
150
+ * this instruction (compare SWI, HVC, SMC handling).
151
+ */
152
+ gen_ss_advance(s);
153
+ gen_exception_internal(EXCP_EXCEPTION_EXIT);
154
+}
155
+
156
/* Variant of store_reg which uses branch&exchange logic when storing
157
to r15 in ARM architecture v7 and above. The source must be a temporary
158
and will be marked as dead. */
159
@@ -XXX,XX +XXX,XX @@ static inline void store_reg_bx(DisasContext *s, int reg, TCGv_i32 var)
160
static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
161
{
162
if (reg == 15 && ENABLE_ARCH_5) {
163
- gen_bx(s, var);
164
+ gen_bx_excret(s, var);
165
} else {
166
store_reg(s, reg, var);
167
}
168
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
169
tmp = tcg_temp_new_i32();
170
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
171
if (i == 15) {
172
- gen_bx(s, tmp);
173
+ gen_bx_excret(s, tmp);
174
} else if (i == rn) {
175
loaded_var = tmp;
176
loaded_base = 1;
177
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
178
goto illegal_op;
179
}
180
if (rs == 15) {
181
- gen_bx(s, tmp);
182
+ gen_bx_excret(s, tmp);
183
} else {
184
store_reg(s, rs, tmp);
185
}
186
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
187
tmp2 = tcg_temp_new_i32();
188
tcg_gen_movi_i32(tmp2, val);
189
store_reg(s, 14, tmp2);
190
+ gen_bx(s, tmp);
191
+ } else {
192
+ /* Only BX works as exception-return, not BLX */
193
+ gen_bx_excret(s, tmp);
194
}
195
- /* already thumb, no need to check */
196
- gen_bx(s, tmp);
197
break;
198
}
199
break;
200
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
201
instruction was a conditional branch or trap, and the PC has
202
already been written. */
203
gen_set_condexec(dc);
204
- if (unlikely(is_singlestepping(dc))) {
205
+ if (dc->is_jmp == DISAS_BX_EXCRET) {
206
+ /* Exception return branches need some special case code at the
207
+ * end of the TB, which is complex enough that it has to
208
+ * handle the single-step vs not and the condition-failed
209
+ * insn codepath itself.
210
+ */
211
+ gen_bx_excret_final_code(dc);
212
+ } else if (unlikely(is_singlestepping(dc))) {
213
/* Unconditional and "condition passed" instruction codepath. */
214
switch (dc->is_jmp) {
215
case DISAS_SWI:
216
--
53
--
217
2.7.4
54
2.20.1
218
55
219
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/24] xlnx-zynqmp: Set the Cadence GEM revision
[Qemu-devel] [PULL 04/10] hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
3
Both lqspi_read() and lqspi_load_cache() expect a 32-bit
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
aligned address.
5
Message-id: 026dbe01a1d42619eee30ce3f2079741bf04bc73.1491947224.git.alistair.francis@xilinx.com
5
6
>From UG1085 datasheet [*] chapter on 'Quad-SPI Controller':
7
8
Transfer Size Limitations
9
10
Because of the 32-bit wide TX, RX, and generic FIFO, all
11
APB/AXI transfers must be an integer multiple of 4-bytes.
12
Shorter transfers are not possible.
13
14
Set MemoryRegionOps.impl values to force 32-bit accesses,
15
this way we are sure we do not access the lqspi_buf[] array
16
out of bound.
17
18
[*] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
19
20
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
21
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
22
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
24
---
8
hw/arm/xlnx-zynqmp.c | 6 +++++-
25
hw/ssi/xilinx_spips.c | 4 ++++
9
1 file changed, 5 insertions(+), 1 deletion(-)
26
1 file changed, 4 insertions(+)
10
27
11
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
28
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
12
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/xlnx-zynqmp.c
30
--- a/hw/ssi/xilinx_spips.c
14
+++ b/hw/arm/xlnx-zynqmp.c
31
+++ b/hw/ssi/xilinx_spips.c
15
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps lqspi_ops = {
16
#define ARM_PHYS_TIMER_PPI 30
33
.read_with_attrs = lqspi_read,
17
#define ARM_VIRT_TIMER_PPI 27
34
.write_with_attrs = lqspi_write,
18
35
.endianness = DEVICE_NATIVE_ENDIAN,
19
+#define GEM_REVISION 0x40070106
36
+ .impl = {
20
+
37
+ .min_access_size = 4,
21
#define GIC_BASE_ADDR 0xf9000000
38
+ .max_access_size = 4,
22
#define GIC_DIST_ADDR 0xf9010000
39
+ },
23
#define GIC_CPU_ADDR 0xf9020000
40
.valid = {
24
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
41
.min_access_size = 1,
25
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
42
.max_access_size = 4
26
qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
27
}
28
+ object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
29
+ &error_abort);
30
object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
31
- &error_abort);
32
+ &error_abort);
33
object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
34
if (err) {
35
error_propagate(errp, err);
36
--
43
--
37
2.7.4
44
2.20.1
38
45
39
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/24] hw/misc/exynos4210_pmu: Reorder local variables for readability
[Qemu-devel] [PULL 05/10] hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
Short declaration of 'i' was in the middle of declarations with
3
Reading the RX_DATA register when the RX_FIFO is empty triggers
4
assignments. Make it a little bit more readable. Additionally switch
4
an abort. This can be easily reproduced:
5
from "unsigned" to "unsigned int" as this pattern is more widely used.
6
No functional change.
7
5
8
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
6
$ qemu-system-arm -M emcraft-sf2 -monitor stdio -S
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
QEMU 4.0.50 monitor - type 'help' for more information
10
Message-id: 20170313184750.429-4-krzk@kernel.org
8
(qemu) x 0x40001010
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Aborted (core dumped)
10
11
(gdb) bt
12
#1 0x00007f035874f895 in abort () at /lib64/libc.so.6
13
#2 0x00005628686591ff in fifo8_pop (fifo=0x56286a9a4c68) at util/fifo8.c:66
14
#3 0x00005628683e0b8e in fifo32_pop (fifo=0x56286a9a4c68) at include/qemu/fifo32.h:137
15
#4 0x00005628683e0efb in spi_read (opaque=0x56286a9a4850, addr=4, size=4) at hw/ssi/mss-spi.c:168
16
#5 0x0000562867f96801 in memory_region_read_accessor (mr=0x56286a9a4b60, addr=16, value=0x7ffeecb0c5c8, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
17
#6 0x0000562867f96cdb in access_with_adjusted_size (addr=16, value=0x7ffeecb0c5c8, size=4, access_size_min=1, access_size_max=4, access_fn=0x562867f967c3 <memory_region_read_accessor>, mr=0x56286a9a4b60, attrs=...) at memory.c:569
18
#7 0x0000562867f99940 in memory_region_dispatch_read1 (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1420
19
#8 0x0000562867f99a08 in memory_region_dispatch_read (mr=0x56286a9a4b60, addr=16, pval=0x7ffeecb0c5c8, size=4, attrs=...) at memory.c:1447
20
#9 0x0000562867f38721 in flatview_read_continue (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, addr1=16, l=4, mr=0x56286a9a4b60) at exec.c:3385
21
#10 0x0000562867f38874 in flatview_read (fv=0x56286aec6360, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3423
22
#11 0x0000562867f388ea in address_space_read_full (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4) at exec.c:3436
23
#12 0x0000562867f389c5 in address_space_rw (as=0x56286aa3e890, addr=1073745936, attrs=..., buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=false) at exec.c:3466
24
#13 0x0000562867f3bdd7 in cpu_memory_rw_debug (cpu=0x56286aa19d00, addr=1073745936, buf=0x7ffeecb0c7c0 "\340ǰ\354\376\177", len=4, is_write=0) at exec.c:3976
25
#14 0x000056286811ed51 in memory_dump (mon=0x56286a8c32d0, count=1, format=120, wsize=4, addr=1073745936, is_physical=0) at monitor/misc.c:730
26
#15 0x000056286811eff1 in hmp_memory_dump (mon=0x56286a8c32d0, qdict=0x56286b15c400) at monitor/misc.c:785
27
#16 0x00005628684740ee in handle_hmp_command (mon=0x56286a8c32d0, cmdline=0x56286a8caeb2 "0x40001010") at monitor/hmp.c:1082
28
29
From the datasheet "Actel SmartFusion Microcontroller Subsystem
30
User's Guide" Rev.1, Table 13-3 "SPI Register Summary", this
31
register has a reset value of 0.
32
33
Check the FIFO is not empty before accessing it, else log an
34
error message.
35
36
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
37
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
38
Message-id: 20190709113715.7761-3-philmd@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
40
---
14
hw/misc/exynos4210_pmu.c | 4 ++--
41
hw/ssi/mss-spi.c | 8 +++++++-
15
1 file changed, 2 insertions(+), 2 deletions(-)
42
1 file changed, 7 insertions(+), 1 deletion(-)
16
43
17
diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c
44
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
18
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/exynos4210_pmu.c
46
--- a/hw/ssi/mss-spi.c
20
+++ b/hw/misc/exynos4210_pmu.c
47
+++ b/hw/ssi/mss-spi.c
21
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
48
@@ -XXX,XX +XXX,XX @@ spi_read(void *opaque, hwaddr addr, unsigned int size)
22
unsigned size)
49
case R_SPI_RX:
23
{
50
s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
24
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
51
s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
25
- unsigned i;
52
- ret = fifo32_pop(&s->rx_fifo);
26
const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
53
+ if (fifo32_is_empty(&s->rx_fifo)) {
27
+ unsigned int i;
54
+ qemu_log_mask(LOG_GUEST_ERROR,
28
55
+ "%s: Reading empty RX_FIFO\n",
29
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
56
+ __func__);
30
if (reg_p->offset == offset) {
57
+ } else {
31
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
58
+ ret = fifo32_pop(&s->rx_fifo);
32
uint64_t val, unsigned size)
59
+ }
33
{
60
if (fifo32_is_empty(&s->rx_fifo)) {
34
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
61
s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
35
- unsigned i;
62
}
36
const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
37
+ unsigned int i;
38
39
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
40
if (reg_p->offset == offset) {
41
--
63
--
42
2.7.4
64
2.20.1
43
65
44
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/24] hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
[Qemu-devel] [PULL 06/10] hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
1
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
The arm64 boot protocol stipulates that the kernel must be loaded
3
In the previous commit we fixed a crash when the guest read a
4
TEXT_OFFSET bytes beyond a 2 MB aligned base address, where TEXT_OFFSET
4
register that pop from an empty FIFO.
5
could be any 4 KB multiple between 0 and 2 MB, and whose value can be
5
By auditing the repository, we found another similar use with
6
found in the header of the Image file.
6
an easy way to reproduce:
7
7
8
So after attempts to load the arm64 kernel image as an ELF file or as a
8
$ qemu-system-aarch64 -M xlnx-zcu102 -monitor stdio -S
9
U-Boot image have failed (both of which have their own way of specifying
9
QEMU 4.0.50 monitor - type 'help' for more information
10
the load offset), try to determine the TEXT_OFFSET from the image after
10
(qemu) xp/b 0xfd4a0134
11
loading it but before mapping it as a ROM mapping into the guest address
11
Aborted (core dumped)
12
space.
13
12
14
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
13
(gdb) bt
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
#0 0x00007f6936dea57f in raise () at /lib64/libc.so.6
16
Message-id: 1489414630-21609-1-git-send-email-ard.biesheuvel@linaro.org
15
#1 0x00007f6936dd4895 in abort () at /lib64/libc.so.6
16
#2 0x0000561ad32975ec in xlnx_dp_aux_pop_rx_fifo (s=0x7f692babee70) at hw/display/xlnx_dp.c:431
17
#3 0x0000561ad3297dc0 in xlnx_dp_read (opaque=0x7f692babee70, offset=77, size=4) at hw/display/xlnx_dp.c:667
18
#4 0x0000561ad321b896 in memory_region_read_accessor (mr=0x7f692babf620, addr=308, value=0x7ffe05c1db88, size=4, shift=0, mask=4294967295, attrs=...) at memory.c:439
19
#5 0x0000561ad321bd70 in access_with_adjusted_size (addr=308, value=0x7ffe05c1db88, size=1, access_size_min=4, access_size_max=4, access_fn=0x561ad321b858 <memory_region_read_accessor>, mr=0x7f692babf620, attrs=...) at memory.c:569
20
#6 0x0000561ad321e9d5 in memory_region_dispatch_read1 (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1420
21
#7 0x0000561ad321ea9d in memory_region_dispatch_read (mr=0x7f692babf620, addr=308, pval=0x7ffe05c1db88, size=1, attrs=...) at memory.c:1447
22
#8 0x0000561ad31bd742 in flatview_read_continue (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1, addr1=308, l=1, mr=0x7f692babf620) at exec.c:3385
23
#9 0x0000561ad31bd895 in flatview_read (fv=0x561ad69c04f0, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3423
24
#10 0x0000561ad31bd90b in address_space_read_full (as=0x561ad5bb3020, addr=4249485620, attrs=..., buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", len=1) at exec.c:3436
25
#11 0x0000561ad33b1c42 in address_space_read (len=1, buf=0x7ffe05c1dcf0 "\020\335\301\005\376\177", attrs=..., addr=4249485620, as=0x561ad5bb3020) at include/exec/memory.h:2131
26
#12 0x0000561ad33b1c42 in memory_dump (mon=0x561ad59c4530, count=1, format=120, wsize=1, addr=4249485620, is_physical=1) at monitor/misc.c:723
27
#13 0x0000561ad33b1fc1 in hmp_physical_memory_dump (mon=0x561ad59c4530, qdict=0x561ad6c6fd00) at monitor/misc.c:795
28
#14 0x0000561ad37b4a9f in handle_hmp_command (mon=0x561ad59c4530, cmdline=0x561ad59d0f22 "/b 0x00000000fd4a0134") at monitor/hmp.c:1082
29
30
Fix by checking the FIFO is not empty before popping from it.
31
32
The datasheet is not clear about the reset value of this register,
33
we choose to return '0'.
34
35
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
36
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
37
Message-id: 20190709113715.7761-4-philmd@redhat.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
39
---
19
hw/arm/boot.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++----------
40
hw/display/xlnx_dp.c | 15 +++++++++++----
20
1 file changed, 53 insertions(+), 11 deletions(-)
41
1 file changed, 11 insertions(+), 4 deletions(-)
21
42
22
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
43
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
23
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/boot.c
45
--- a/hw/display/xlnx_dp.c
25
+++ b/hw/arm/boot.c
46
+++ b/hw/display/xlnx_dp.c
26
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@ static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
27
#define KERNEL_LOAD_ADDR 0x00010000
48
uint8_t ret;
28
#define KERNEL64_LOAD_ADDR 0x00080000
49
29
50
if (fifo8_is_empty(&s->rx_fifo)) {
30
+#define ARM64_TEXT_OFFSET_OFFSET 8
51
- DPRINTF("rx_fifo underflow..\n");
31
+#define ARM64_MAGIC_OFFSET 56
52
- abort();
32
+
53
+ qemu_log_mask(LOG_GUEST_ERROR,
33
typedef enum {
54
+ "%s: Reading empty RX_FIFO\n",
34
FIXUP_NONE = 0, /* do nothing */
55
+ __func__);
35
FIXUP_TERMINATOR, /* end of insns */
56
+ /*
36
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
57
+ * The datasheet is not clear about the reset value, it seems
58
+ * to be unspecified. We choose to return '0'.
59
+ */
60
+ ret = 0;
61
+ } else {
62
+ ret = fifo8_pop(&s->rx_fifo);
63
+ DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
64
}
65
- ret = fifo8_pop(&s->rx_fifo);
66
- DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
37
return ret;
67
return ret;
38
}
68
}
39
69
40
+static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
41
+ hwaddr *entry)
42
+{
43
+ hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
44
+ uint8_t *buffer;
45
+ int size;
46
+
47
+ /* On aarch64, it's the bootloader's job to uncompress the kernel. */
48
+ size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
49
+ &buffer);
50
+
51
+ if (size < 0) {
52
+ gsize len;
53
+
54
+ /* Load as raw file otherwise */
55
+ if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
56
+ return -1;
57
+ }
58
+ size = len;
59
+ }
60
+
61
+ /* check the arm64 magic header value -- very old kernels may not have it */
62
+ if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
63
+ uint64_t hdrvals[2];
64
+
65
+ /* The arm64 Image header has text_offset and image_size fields at 8 and
66
+ * 16 bytes into the Image header, respectively. The text_offset field
67
+ * is only valid if the image_size is non-zero.
68
+ */
69
+ memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
70
+ if (hdrvals[1] != 0) {
71
+ kernel_load_offset = le64_to_cpu(hdrvals[0]);
72
+ }
73
+ }
74
+
75
+ *entry = mem_base + kernel_load_offset;
76
+ rom_add_blob_fixed(filename, buffer, size, *entry);
77
+
78
+ g_free(buffer);
79
+
80
+ return size;
81
+}
82
+
83
static void arm_load_kernel_notify(Notifier *notifier, void *data)
84
{
85
CPUState *cs;
86
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
87
int is_linux = 0;
88
uint64_t elf_entry, elf_low_addr, elf_high_addr;
89
int elf_machine;
90
- hwaddr entry, kernel_load_offset;
91
+ hwaddr entry;
92
static const ARMInsnFixup *primary_loader;
93
ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier,
94
notifier, notifier);
95
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
96
97
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
98
primary_loader = bootloader_aarch64;
99
- kernel_load_offset = KERNEL64_LOAD_ADDR;
100
elf_machine = EM_AARCH64;
101
} else {
102
primary_loader = bootloader;
103
if (!info->write_board_setup) {
104
primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
105
}
106
- kernel_load_offset = KERNEL_LOAD_ADDR;
107
elf_machine = EM_ARM;
108
}
109
110
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
111
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
112
&is_linux, NULL, NULL);
113
}
114
- /* On aarch64, it's the bootloader's job to uncompress the kernel. */
115
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
116
- entry = info->loader_start + kernel_load_offset;
117
- kernel_size = load_image_gzipped(info->kernel_filename, entry,
118
- info->ram_size - kernel_load_offset);
119
+ kernel_size = load_aarch64_image(info->kernel_filename,
120
+ info->loader_start, &entry);
121
is_linux = 1;
122
- }
123
- if (kernel_size < 0) {
124
- entry = info->loader_start + kernel_load_offset;
125
+ } else if (kernel_size < 0) {
126
+ /* 32-bit ARM */
127
+ entry = info->loader_start + KERNEL_LOAD_ADDR;
128
kernel_size = load_image_targphys(info->kernel_filename, entry,
129
- info->ram_size - kernel_load_offset);
130
+ info->ram_size - KERNEL_LOAD_ADDR);
131
is_linux = 1;
132
}
133
if (kernel_size < 0) {
134
--
70
--
135
2.7.4
71
2.20.1
136
72
137
73
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/24] hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
[Qemu-devel] [PULL 07/10] hw/arm/virt: Fix non-secure flash mode
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: David Engraf <david.engraf@sysgo.com>
2
2
3
qemu_log_mask() and error_report() are preferred over fprintf() for
3
Using the whole 128 MiB flash in non-secure mode is not working because
4
logging errors. Also remove square brackets [] and additional new line
4
virt_flash_fdt() expects the same address for secure_sysmem and sysmem.
5
characters in printed messages.
5
This is not correctly handled by caller because it forwards NULL for
6
secure_sysmem in non-secure flash mode.
6
7
7
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
8
Fixed by using sysmem when secure_sysmem is NULL.
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
9
Message-id: 20170313184750.429-2-krzk@kernel.org
10
Signed-off-by: David Engraf <david.engraf@sysgo.com>
10
[PMM: wrapped long line]
11
Message-id: 20190712075002.14326-1-david.engraf@sysgo.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
---
14
hw/arm/exynos4_boards.c | 7 ++++---
15
hw/arm/virt.c | 2 +-
15
hw/timer/exynos4210_mct.c | 6 ++++--
16
1 file changed, 1 insertion(+), 1 deletion(-)
16
hw/timer/exynos4210_pwm.c | 13 +++++++------
17
hw/timer/exynos4210_rtc.c | 19 ++++++++++---------
18
4 files changed, 25 insertions(+), 20 deletions(-)
19
17
20
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/exynos4_boards.c
20
--- a/hw/arm/virt.c
23
+++ b/hw/arm/exynos4_boards.c
21
+++ b/hw/arm/virt.c
24
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
25
*/
23
&machine->device_memory->mr);
26
27
#include "qemu/osdep.h"
28
+#include "qemu/error-report.h"
29
#include "qemu-common.h"
30
#include "cpu.h"
31
#include "sysemu/sysemu.h"
32
@@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
33
MachineClass *mc = MACHINE_GET_CLASS(machine);
34
35
if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
36
- fprintf(stderr, "%s board supports only %d CPU cores. Ignoring smp_cpus"
37
- " value.\n",
38
- mc->name, EXYNOS4210_NCPUS);
39
+ error_report("%s board supports only %d CPU cores, ignoring smp_cpus"
40
+ " value",
41
+ mc->name, EXYNOS4210_NCPUS);
42
}
24
}
43
25
44
exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
26
- virt_flash_fdt(vms, sysmem, secure_sysmem);
45
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
27
+ virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
46
index XXXXXXX..XXXXXXX 100644
28
47
--- a/hw/timer/exynos4210_mct.c
29
create_gic(vms, pic);
48
+++ b/hw/timer/exynos4210_mct.c
30
49
@@ -XXX,XX +XXX,XX @@
50
*/
51
52
#include "qemu/osdep.h"
53
+#include "qemu/log.h"
54
#include "hw/sysbus.h"
55
#include "qemu/timer.h"
56
#include "qemu/main-loop.h"
57
@@ -XXX,XX +XXX,XX @@ break;
58
case L0_TCNTO: case L1_TCNTO:
59
case L0_ICNTO: case L1_ICNTO:
60
case L0_FRCNTO: case L1_FRCNTO:
61
- fprintf(stderr, "\n[exynos4210.mct: write to RO register "
62
- TARGET_FMT_plx "]\n\n", offset);
63
+ qemu_log_mask(LOG_GUEST_ERROR,
64
+ "exynos4210.mct: write to RO register " TARGET_FMT_plx,
65
+ offset);
66
break;
67
68
case L0_INT_CSTAT: case L1_INT_CSTAT:
69
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/timer/exynos4210_pwm.c
72
+++ b/hw/timer/exynos4210_pwm.c
73
@@ -XXX,XX +XXX,XX @@
74
*/
75
76
#include "qemu/osdep.h"
77
+#include "qemu/log.h"
78
#include "hw/sysbus.h"
79
#include "qemu/timer.h"
80
#include "qemu-common.h"
81
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
82
break;
83
84
default:
85
- fprintf(stderr,
86
- "[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n",
87
- offset);
88
+ qemu_log_mask(LOG_GUEST_ERROR,
89
+ "exynos4210.pwm: bad read offset " TARGET_FMT_plx,
90
+ offset);
91
break;
92
}
93
return value;
94
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset,
95
break;
96
97
default:
98
- fprintf(stderr,
99
- "[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n",
100
- offset);
101
+ qemu_log_mask(LOG_GUEST_ERROR,
102
+ "exynos4210.pwm: bad write offset " TARGET_FMT_plx,
103
+ offset);
104
break;
105
106
}
107
diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/timer/exynos4210_rtc.c
110
+++ b/hw/timer/exynos4210_rtc.c
111
@@ -XXX,XX +XXX,XX @@
112
*/
113
114
#include "qemu/osdep.h"
115
+#include "qemu/log.h"
116
#include "hw/sysbus.h"
117
#include "qemu/timer.h"
118
#include "qemu-common.h"
119
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
120
break;
121
122
default:
123
- fprintf(stderr,
124
- "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n",
125
- offset);
126
+ qemu_log_mask(LOG_GUEST_ERROR,
127
+ "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
128
+ offset);
129
break;
130
}
131
return value;
132
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
133
if (value > TICNT_THRESHOLD) {
134
s->reg_ticcnt = value;
135
} else {
136
- fprintf(stderr,
137
- "[exynos4210.rtc: bad TICNT value %u ]\n",
138
- (uint32_t)value);
139
+ qemu_log_mask(LOG_GUEST_ERROR,
140
+ "exynos4210.rtc: bad TICNT value %u",
141
+ (uint32_t)value);
142
}
143
break;
144
145
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
146
break;
147
148
default:
149
- fprintf(stderr,
150
- "[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n",
151
- offset);
152
+ qemu_log_mask(LOG_GUEST_ERROR,
153
+ "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
154
+ offset);
155
break;
156
157
}
158
--
31
--
159
2.7.4
32
2.20.1
160
33
161
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/24] target/arm: Add missing entries to excnames[] for log strings
Deleted patch
1
Recent changes have added new EXCP_ values to ARM but forgot
2
to update the excnames[] array which is used to provide
3
human-readable strings when printing information about the
4
exception for debug logging. Add the missing entries, and
5
add a comment to the list of #defines to help avoid the mistake
6
being repeated in future.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Message-id: 1491486340-25988-1-git-send-email-peter.maydell@linaro.org
12
---
13
target/arm/cpu.h | 1 +
14
target/arm/internals.h | 2 ++
15
2 files changed, 3 insertions(+)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@
22
#define EXCP_SEMIHOST 16 /* semihosting call */
23
#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
24
#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
25
+/* NB: new EXCP_ defines should be added to the excnames[] array too */
26
27
#define ARMV7M_EXCP_RESET 1
28
#define ARMV7M_EXCP_NMI 2
29
diff --git a/target/arm/internals.h b/target/arm/internals.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/internals.h
32
+++ b/target/arm/internals.h
33
@@ -XXX,XX +XXX,XX @@ static const char * const excnames[] = {
34
[EXCP_VIRQ] = "Virtual IRQ",
35
[EXCP_VFIQ] = "Virtual FIQ",
36
[EXCP_SEMIHOST] = "Semihosting call",
37
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
38
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
39
};
40
41
/* Scale factor for generic timers, ie number of ns per tick.
42
--
43
2.7.4
44
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/24] arm: Move excnames[] array into arm_log_exceptions()
Deleted patch
1
The excnames[] array is defined in internals.h because we used
2
to use it from two different source files for handling logging
3
of AArch32 and AArch64 exception entry. Refactoring means that
4
it's now used only in arm_log_exception() in helper.c, so move
5
the array into that function.
6
1
7
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 1491821097-5647-1-git-send-email-peter.maydell@linaro.org
11
---
12
target/arm/cpu.h | 2 +-
13
target/arm/internals.h | 23 -----------------------
14
target/arm/helper.c | 19 +++++++++++++++++++
15
3 files changed, 20 insertions(+), 24 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@
22
#define EXCP_SEMIHOST 16 /* semihosting call */
23
#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
24
#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
25
-/* NB: new EXCP_ defines should be added to the excnames[] array too */
26
+/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
27
28
#define ARMV7M_EXCP_RESET 1
29
#define ARMV7M_EXCP_NMI 2
30
diff --git a/target/arm/internals.h b/target/arm/internals.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/internals.h
33
+++ b/target/arm/internals.h
34
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
35
|| excp == EXCP_SEMIHOST;
36
}
37
38
-/* Exception names for debug logging; note that not all of these
39
- * precisely correspond to architectural exceptions.
40
- */
41
-static const char * const excnames[] = {
42
- [EXCP_UDEF] = "Undefined Instruction",
43
- [EXCP_SWI] = "SVC",
44
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
45
- [EXCP_DATA_ABORT] = "Data Abort",
46
- [EXCP_IRQ] = "IRQ",
47
- [EXCP_FIQ] = "FIQ",
48
- [EXCP_BKPT] = "Breakpoint",
49
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
50
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
51
- [EXCP_HVC] = "Hypervisor Call",
52
- [EXCP_HYP_TRAP] = "Hypervisor Trap",
53
- [EXCP_SMC] = "Secure Monitor Call",
54
- [EXCP_VIRQ] = "Virtual IRQ",
55
- [EXCP_VFIQ] = "Virtual FIQ",
56
- [EXCP_SEMIHOST] = "Semihosting call",
57
- [EXCP_NOCP] = "v7M NOCP UsageFault",
58
- [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
59
-};
60
-
61
/* Scale factor for generic timers, ie number of ns per tick.
62
* This gives a 62.5MHz timer.
63
*/
64
diff --git a/target/arm/helper.c b/target/arm/helper.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/helper.c
67
+++ b/target/arm/helper.c
68
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
69
{
70
if (qemu_loglevel_mask(CPU_LOG_INT)) {
71
const char *exc = NULL;
72
+ static const char * const excnames[] = {
73
+ [EXCP_UDEF] = "Undefined Instruction",
74
+ [EXCP_SWI] = "SVC",
75
+ [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
76
+ [EXCP_DATA_ABORT] = "Data Abort",
77
+ [EXCP_IRQ] = "IRQ",
78
+ [EXCP_FIQ] = "FIQ",
79
+ [EXCP_BKPT] = "Breakpoint",
80
+ [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
81
+ [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
82
+ [EXCP_HVC] = "Hypervisor Call",
83
+ [EXCP_HYP_TRAP] = "Hypervisor Trap",
84
+ [EXCP_SMC] = "Secure Monitor Call",
85
+ [EXCP_VIRQ] = "Virtual IRQ",
86
+ [EXCP_VFIQ] = "Virtual FIQ",
87
+ [EXCP_SEMIHOST] = "Semihosting call",
88
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
89
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
90
+ };
91
92
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
93
exc = excnames[idx];
94
--
95
2.7.4
96
97
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/24] target/arm: Add assertion about FSC format for syndrome registers
Deleted patch
1
In tlb_fill() we construct a syndrome register value from a
2
fault status register value which is filled in by arm_tlb_fill().
3
arm_tlb_fill() returns FSR values which might be in the format
4
used with short-format page descriptors, or the format used
5
with long-format (LPAE) descriptors. The syndrome register
6
always uses LPAE-format FSR status codes.
7
1
8
It isn't actually possible to end up delivering a syndrome
9
register value to the guest for a fault which is reported
10
with a short-format FSR (that kind of stage 1 fault will only
11
happen for an AArch32 translation regime which doesn't have
12
a syndrome register, and can never be redirected to an AArch64
13
or Hyp exception level). Add an assertion which checks this,
14
and adjust the code so that we construct a syndrome with
15
an invalid status code, rather than allowing set bits in
16
the FSR input to randomly corrupt other fields in the syndrome.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
20
Message-id: 1491486152-24304-1-git-send-email-peter.maydell@linaro.org
21
---
22
target/arm/op_helper.c | 23 ++++++++++++++++++-----
23
1 file changed, 18 insertions(+), 5 deletions(-)
24
25
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/op_helper.c
28
+++ b/target/arm/op_helper.c
29
@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
30
if (unlikely(ret)) {
31
ARMCPU *cpu = ARM_CPU(cs);
32
CPUARMState *env = &cpu->env;
33
- uint32_t syn, exc;
34
+ uint32_t syn, exc, fsc;
35
unsigned int target_el;
36
bool same_el;
37
38
@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
39
env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
40
}
41
same_el = arm_current_el(env) == target_el;
42
- /* AArch64 syndrome does not have an LPAE bit */
43
- syn = fsr & ~(1 << 9);
44
+
45
+ if (fsr & (1 << 9)) {
46
+ /* LPAE format fault status register : bottom 6 bits are
47
+ * status code in the same form as needed for syndrome
48
+ */
49
+ fsc = extract32(fsr, 0, 6);
50
+ } else {
51
+ /* Short format FSR : this fault will never actually be reported
52
+ * to an EL that uses a syndrome register. Check that here,
53
+ * and use a (currently) reserved FSR code in case the constructed
54
+ * syndrome does leak into the guest somehow.
55
+ */
56
+ assert(target_el != 2 && !arm_el_is_aa64(env, target_el));
57
+ fsc = 0x3f;
58
+ }
59
60
/* For insn and data aborts we assume there is no instruction syndrome
61
* information; this is always true for exceptions reported to EL1.
62
*/
63
if (access_type == MMU_INST_FETCH) {
64
- syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
65
+ syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc);
66
exc = EXCP_PREFETCH_ABORT;
67
} else {
68
syn = merge_syn_data_abort(env->exception.syndrome, target_el,
69
same_el, fi.s1ptw,
70
- access_type == MMU_DATA_STORE, syn);
71
+ access_type == MMU_DATA_STORE, fsc);
72
if (access_type == MMU_DATA_STORE
73
&& arm_feature(env, ARM_FEATURE_V6)) {
74
fsr |= (1 << 11);
75
--
76
2.7.4
77
78
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/24] stellaris: Don't hw_error() on bad register accesses
Deleted patch
1
Current recommended style is to log a guest error on bad register
2
accesses, not kill the whole system with hw_error(). Change the
3
hw_error() calls to log as LOG_GUEST_ERROR or LOG_UNIMP or use
4
g_assert_not_reached() as appropriate.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 1491486314-25823-1-git-send-email-peter.maydell@linaro.org
9
---
10
hw/arm/stellaris.c | 60 +++++++++++++++++++++++++++++++++---------------------
11
1 file changed, 37 insertions(+), 23 deletions(-)
12
13
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/stellaris.c
16
+++ b/hw/arm/stellaris.c
17
@@ -XXX,XX +XXX,XX @@ static void gptm_reload(gptm_state *s, int n, int reset)
18
} else if (s->mode[n] == 0xa) {
19
/* PWM mode. Not implemented. */
20
} else {
21
- hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
22
+ qemu_log_mask(LOG_UNIMP,
23
+ "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
24
+ s->mode[n]);
25
+ return;
26
}
27
s->tick[n] = tick;
28
timer_mod(s->timer[n], tick);
29
@@ -XXX,XX +XXX,XX @@ static void gptm_tick(void *opaque)
30
} else if (s->mode[n] == 0xa) {
31
/* PWM mode. Not implemented. */
32
} else {
33
- hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
34
+ qemu_log_mask(LOG_UNIMP,
35
+ "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
36
+ s->mode[n]);
37
}
38
gptm_update_irq(s);
39
}
40
@@ -XXX,XX +XXX,XX @@ static void gptm_write(void *opaque, hwaddr offset,
41
s->match_prescale[0] = value;
42
break;
43
default:
44
- hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
45
+ qemu_log_mask(LOG_GUEST_ERROR,
46
+ "GPTM: read at bad offset 0x%x\n", (int)offset);
47
}
48
gptm_update_irq(s);
49
}
50
@@ -XXX,XX +XXX,XX @@ static int ssys_board_class(const ssys_state *s)
51
}
52
/* for unknown classes, fall through */
53
default:
54
- hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
55
+ /* This can only happen if the hardwired constant did0 value
56
+ * in this board's stellaris_board_info struct is wrong.
57
+ */
58
+ g_assert_not_reached();
59
}
60
}
61
62
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
63
case DID0_CLASS_SANDSTORM:
64
return pllcfg_sandstorm[xtal];
65
default:
66
- hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
67
- return 0;
68
+ g_assert_not_reached();
69
}
70
}
71
case 0x070: /* RCC2 */
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
73
case 0x1e4: /* USER1 */
74
return s->user1;
75
default:
76
- hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
77
+ qemu_log_mask(LOG_GUEST_ERROR,
78
+ "SSYS: read at bad offset 0x%x\n", (int)offset);
79
return 0;
80
}
81
}
82
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
83
s->ldoarst = value;
84
break;
85
default:
86
- hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
87
+ qemu_log_mask(LOG_GUEST_ERROR,
88
+ "SSYS: write at bad offset 0x%x\n", (int)offset);
89
}
90
ssys_update(s);
91
}
92
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
93
case 0x20: /* MCR */
94
return s->mcr;
95
default:
96
- hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
97
+ qemu_log_mask(LOG_GUEST_ERROR,
98
+ "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
99
return 0;
100
}
101
}
102
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
103
s->mris &= ~value;
104
break;
105
case 0x20: /* MCR */
106
- if (value & 1)
107
- hw_error(
108
- "stellaris_i2c_write: Loopback not implemented\n");
109
- if (value & 0x20)
110
- hw_error(
111
- "stellaris_i2c_write: Slave mode not implemented\n");
112
+ if (value & 1) {
113
+ qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
114
+ }
115
+ if (value & 0x20) {
116
+ qemu_log_mask(LOG_UNIMP,
117
+ "stellaris_i2c: Slave mode not implemented");
118
+ }
119
s->mcr = value & 0x31;
120
break;
121
default:
122
- hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
123
- (int)offset);
124
+ qemu_log_mask(LOG_GUEST_ERROR,
125
+ "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
126
}
127
stellaris_i2c_update(s);
128
}
129
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
130
case 0x30: /* SAC */
131
return s->sac;
132
default:
133
- hw_error("strllaris_adc_read: Bad offset 0x%x\n",
134
- (int)offset);
135
+ qemu_log_mask(LOG_GUEST_ERROR,
136
+ "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
137
return 0;
138
}
139
}
140
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
141
return;
142
case 0x04: /* SSCTL */
143
if (value != 6) {
144
- hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
145
- value);
146
+ qemu_log_mask(LOG_UNIMP,
147
+ "ADC: Unimplemented sequence %" PRIx64 "\n",
148
+ value);
149
}
150
s->ssctl[n] = value;
151
return;
152
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
153
s->sspri = value;
154
break;
155
case 0x28: /* PSSI */
156
- hw_error("Not implemented: ADC sample initiate\n");
157
+ qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
158
break;
159
case 0x30: /* SAC */
160
s->sac = value;
161
break;
162
default:
163
- hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
164
+ qemu_log_mask(LOG_GUEST_ERROR,
165
+ "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
166
}
167
stellaris_adc_update(s);
168
}
169
--
170
2.7.4
171
172
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/24] hw/arm: Qomify pxa2xx.c
Deleted patch
1
From: Suramya Shah <shah.suramya@gmail.com>
2
1
3
Signed-off-by: Suramya Shah <shah.suramya@gmail.com>
4
Message-id: 20170415180316.2694-1-shah.suramya@gmail.com
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/pxa2xx.c | 14 ++++++--------
9
1 file changed, 6 insertions(+), 8 deletions(-)
10
11
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/pxa2xx.c
14
+++ b/hw/arm/pxa2xx.c
15
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_reset(DeviceState *d)
16
s->rx_start = s->rx_level = 0;
17
}
18
19
-static int pxa2xx_ssp_init(SysBusDevice *sbd)
20
+static void pxa2xx_ssp_init(Object *obj)
21
{
22
- DeviceState *dev = DEVICE(sbd);
23
- PXA2xxSSPState *s = PXA2XX_SSP(dev);
24
-
25
+ DeviceState *dev = DEVICE(obj);
26
+ PXA2xxSSPState *s = PXA2XX_SSP(obj);
27
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
28
sysbus_init_irq(sbd, &s->irq);
29
30
- memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
31
+ memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
32
"pxa2xx-ssp", 0x1000);
33
sysbus_init_mmio(sbd, &s->iomem);
34
35
s->bus = ssi_create_bus(dev, "ssi");
36
- return 0;
37
}
38
39
/* Real-Time Clock */
40
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
41
42
static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
43
{
44
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
45
DeviceClass *dc = DEVICE_CLASS(klass);
46
47
- sdc->init = pxa2xx_ssp_init;
48
dc->reset = pxa2xx_ssp_reset;
49
dc->vmsd = &vmstate_pxa2xx_ssp;
50
}
51
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pxa2xx_ssp_info = {
52
.name = TYPE_PXA2XX_SSP,
53
.parent = TYPE_SYS_BUS_DEVICE,
54
.instance_size = sizeof(PXA2xxSSPState),
55
+ .instance_init = pxa2xx_ssp_init,
56
.class_init = pxa2xx_ssp_class_init,
57
};
58
59
--
60
2.7.4
61
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/24] cadence_gem: Read the correct queue descriptor
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
Read the correct descriptor instead of hardcoding the first (q=0).
4
5
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 988b183dcf951856d8b3379f7e911ec95233bbf4.1491947224.git.alistair.francis@xilinx.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/net/cadence_gem.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
17
+++ b/hw/net/cadence_gem.c
18
@@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
19
{
20
DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
21
/* read current descriptor */
22
- cpu_physical_memory_read(s->rx_desc_addr[0],
23
- (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0]));
24
+ cpu_physical_memory_read(s->rx_desc_addr[q],
25
+ (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q]));
26
27
/* Descriptor owned by software ? */
28
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
29
--
30
2.7.4
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/24] cadence_gem: Correct the multi-queue can rx logic
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
Correct the buffer descriptor busy logic to work correctly when using
4
multiple queues.
5
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 8a7e8059984e27d46a276a66299d035a0afd280f.1491947224.git.alistair.francis@xilinx.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/net/cadence_gem.c | 17 ++++++++++-------
12
1 file changed, 10 insertions(+), 7 deletions(-)
13
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
17
+++ b/hw/net/cadence_gem.c
18
@@ -XXX,XX +XXX,XX @@ static int gem_can_receive(NetClientState *nc)
19
}
20
21
for (i = 0; i < s->num_priority_queues; i++) {
22
- if (rx_desc_get_ownership(s->rx_desc[i]) == 1) {
23
- if (s->can_rx_state != 2) {
24
- s->can_rx_state = 2;
25
- DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n",
26
- i, s->rx_desc_addr[i]);
27
- }
28
- return 0;
29
+ if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
30
+ break;
31
+ }
32
+ };
33
+
34
+ if (i == s->num_priority_queues) {
35
+ if (s->can_rx_state != 2) {
36
+ s->can_rx_state = 2;
37
+ DB_PRINT("can't receive - all the buffer descriptors are busy\n");
38
}
39
+ return 0;
40
}
41
42
if (s->can_rx_state != 0) {
43
--
44
2.7.4
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/24] cadence_gem: Correct the interupt logic
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
This patch fixes two mistakes in the interrupt logic.
4
5
First we only trigger single-queue or multi-queue interrupts if the status
6
register is set. This logic was already used for non multi-queue interrupts
7
but it also applies to multi-queue interrupts.
8
9
Secondly we need to lower the interrupts if the ISR isn't set. As part
10
of this we can remove the other interrupt lowering logic and consolidate
11
it inside gem_update_int_status().
12
13
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
14
Message-id: 438bcc014f8f8a2f8f68f322cb6a53f4c04688c2.1491947224.git.alistair.francis@xilinx.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/net/cadence_gem.c | 18 +++++++++++++-----
19
1 file changed, 13 insertions(+), 5 deletions(-)
20
21
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/net/cadence_gem.c
24
+++ b/hw/net/cadence_gem.c
25
@@ -XXX,XX +XXX,XX @@ static void gem_update_int_status(CadenceGEMState *s)
26
{
27
int i;
28
29
- if ((s->num_priority_queues == 1) && s->regs[GEM_ISR]) {
30
+ if (!s->regs[GEM_ISR]) {
31
+ /* ISR isn't set, clear all the interrupts */
32
+ for (i = 0; i < s->num_priority_queues; ++i) {
33
+ qemu_set_irq(s->irq[i], 0);
34
+ }
35
+ return;
36
+ }
37
+
38
+ /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
39
+ * check it again.
40
+ */
41
+ if (s->num_priority_queues == 1) {
42
/* No priority queues, just trigger the interrupt */
43
DB_PRINT("asserting int.\n");
44
qemu_set_irq(s->irq[0], 1);
45
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
46
{
47
CadenceGEMState *s;
48
uint32_t retval;
49
- int i;
50
s = (CadenceGEMState *)opaque;
51
52
offset >>= 2;
53
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
54
switch (offset) {
55
case GEM_ISR:
56
DB_PRINT("lowering irqs on ISR read\n");
57
- for (i = 0; i < s->num_priority_queues; ++i) {
58
- qemu_set_irq(s->irq[i], 0);
59
- }
60
+ /* The interrupts get updated at the end of the function. */
61
break;
62
case GEM_PHYMNTNC:
63
if (retval & GEM_PHYMNTNC_OP_R) {
64
--
65
2.7.4
66
67
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/24] cadence_gem: Make the revision a property
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
Expose the Cadence GEM revision as a property.
4
5
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 541324373cf87b50f8be0439a0cb89f5028b016f.1491947224.git.alistair.francis@xilinx.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/net/cadence_gem.h | 1 +
12
hw/net/cadence_gem.c | 6 +++++-
13
2 files changed, 6 insertions(+), 1 deletion(-)
14
15
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/net/cadence_gem.h
18
+++ b/include/hw/net/cadence_gem.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
20
uint8_t num_priority_queues;
21
uint8_t num_type1_screeners;
22
uint8_t num_type2_screeners;
23
+ uint32_t revision;
24
25
/* GEM registers backing store */
26
uint32_t regs[CADENCE_GEM_MAXREG];
27
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/net/cadence_gem.c
30
+++ b/hw/net/cadence_gem.c
31
@@ -XXX,XX +XXX,XX @@
32
#define DESC_1_RX_SOF 0x00004000
33
#define DESC_1_RX_EOF 0x00008000
34
35
+#define GEM_MODID_VALUE 0x00020118
36
+
37
static inline unsigned tx_desc_get_buffer(unsigned *desc)
38
{
39
return desc[0];
40
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
41
s->regs[GEM_TXPAUSE] = 0x0000ffff;
42
s->regs[GEM_TXPARTIALSF] = 0x000003ff;
43
s->regs[GEM_RXPARTIALSF] = 0x000003ff;
44
- s->regs[GEM_MODID] = 0x00020118;
45
+ s->regs[GEM_MODID] = s->revision;
46
s->regs[GEM_DESCONF] = 0x02500111;
47
s->regs[GEM_DESCONF2] = 0x2ab13fff;
48
s->regs[GEM_DESCONF5] = 0x002f2145;
49
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_cadence_gem = {
50
51
static Property gem_properties[] = {
52
DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
53
+ DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
54
+ GEM_MODID_VALUE),
55
DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
56
num_priority_queues, 1),
57
DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
58
--
59
2.7.4
60
61
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/24] arm: Don't implement BXJ on M-profile CPUs
Deleted patch
1
For M-profile CPUs, the BXJ instruction does not exist at all, and
2
the encoding should always UNDEF. We were accidentally implementing
3
it to behave like A-profile BXJ; correct the error.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Message-id: 1491844419-12485-2-git-send-email-peter.maydell@linaro.org
9
---
10
target/arm/translate.c | 7 ++++++-
11
1 file changed, 6 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
18
}
19
break;
20
case 4: /* bxj */
21
- /* Trivial implementation equivalent to bx. */
22
+ /* Trivial implementation equivalent to bx.
23
+ * This instruction doesn't exist at all for M-profile.
24
+ */
25
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
26
+ goto illegal_op;
27
+ }
28
tmp = load_reg(s, rn);
29
gen_bx(s, tmp);
30
break;
31
--
32
2.7.4
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/24] arm: Thumb shift operations should not permit interworking branches
Deleted patch
1
In Thumb mode, the only instructions which can cause an interworking
2
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
3
ARM mode, data processing instructions which target the PC do not
4
cause interworking branches.
5
1
6
When we added support for doing interworking branches on writes to
7
PC from data processing instructions in commit 21aeb3430ce7ba, we
8
accidentally changed a Thumb instruction to have interworking
9
branch behaviour for writes to PC. (MOV, MOVS register-shifted
10
register, encoding T2; this is the standard encoding for
11
LSL/LSR/ASR/ROR (register).)
12
13
For this encoding, behaviour with Rd == R15 is specified as
14
UNPREDICTABLE, so allowing an interworking branch is within
15
spec, but it's confusing and differs from our handling of this
16
class of UNPREDICTABLE for other Thumb ALU operations. Make
17
it perform a simple (non-interworking) branch like the others.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <rth@twiddle.net>
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Message-id: 1491844419-12485-3-git-send-email-peter.maydell@linaro.org
23
---
24
target/arm/translate.c | 2 +-
25
1 file changed, 1 insertion(+), 1 deletion(-)
26
27
diff --git a/target/arm/translate.c b/target/arm/translate.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/translate.c
30
+++ b/target/arm/translate.c
31
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
32
gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
33
if (logic_cc)
34
gen_logic_CC(tmp);
35
- store_reg_bx(s, rd, tmp);
36
+ store_reg(s, rd, tmp);
37
break;
38
case 1: /* Sign/zero extend. */
39
op = (insn >> 20) & 7;
40
--
41
2.7.4
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/24] arm: Factor out "generate right kind of step exception"
Deleted patch
1
We currently have two places that do:
2
if (dc->ss_active) {
3
gen_step_complete_exception(dc);
4
} else {
5
gen_exception_internal(EXCP_DEBUG);
6
}
7
1
8
Factor this out into its own function, as we're about to add
9
a third place that needs the same logic.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <rth@twiddle.net>
14
Message-id: 1491844419-12485-4-git-send-email-peter.maydell@linaro.org
15
---
16
target/arm/translate.c | 28 ++++++++++++++++------------
17
1 file changed, 16 insertions(+), 12 deletions(-)
18
19
diff --git a/target/arm/translate.c b/target/arm/translate.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate.c
22
+++ b/target/arm/translate.c
23
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
24
s->is_jmp = DISAS_EXC;
25
}
26
27
+static void gen_singlestep_exception(DisasContext *s)
28
+{
29
+ /* Generate the right kind of exception for singlestep, which is
30
+ * either the architectural singlestep or EXCP_DEBUG for QEMU's
31
+ * gdb singlestepping.
32
+ */
33
+ if (s->ss_active) {
34
+ gen_step_complete_exception(s);
35
+ } else {
36
+ gen_exception_internal(EXCP_DEBUG);
37
+ }
38
+}
39
+
40
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
41
{
42
TCGv_i32 tmp1 = tcg_temp_new_i32();
43
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
44
gen_set_pc_im(dc, dc->pc);
45
/* fall through */
46
default:
47
- if (dc->ss_active) {
48
- gen_step_complete_exception(dc);
49
- } else {
50
- /* FIXME: Single stepping a WFI insn will not halt
51
- the CPU. */
52
- gen_exception_internal(EXCP_DEBUG);
53
- }
54
+ /* FIXME: Single stepping a WFI insn will not halt the CPU. */
55
+ gen_singlestep_exception(dc);
56
}
57
if (dc->condjmp) {
58
/* "Condition failed" instruction codepath. */
59
gen_set_label(dc->condlabel);
60
gen_set_condexec(dc);
61
gen_set_pc_im(dc, dc->pc);
62
- if (dc->ss_active) {
63
- gen_step_complete_exception(dc);
64
- } else {
65
- gen_exception_internal(EXCP_DEBUG);
66
- }
67
+ gen_singlestep_exception(dc);
68
}
69
} else {
70
/* While branches must always occur at the end of an IT block,
71
--
72
2.7.4
73
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/24] arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
[Qemu-devel] [PULL 08/10] pl031: Correctly migrate state when using -rtc clock=host
1
Move the utility routines gen_set_condexec() and gen_set_pc_im()
1
The PL031 RTC tracks the difference between the guest RTC
2
up in the file, as we will want to use them from a function
2
and the host RTC using a tick_offset field. For migration,
3
placed earlier in the file than their current location.
3
however, we currently always migrate the offset between
4
4
the guest and the vm_clock, even if the RTC clock is not
5
the same as the vm_clock; this was an attempt to retain
6
migration backwards compatibility.
7
8
Unfortunately this results in the RTC behaving oddly across
9
a VM state save and restore -- since the VM clock stands still
10
across save-then-restore, regardless of how much real world
11
time has elapsed, the guest RTC ends up out of sync with the
12
host RTC in the restored VM.
13
14
Fix this by migrating the raw tick_offset. To retain migration
15
compatibility as far as possible, we have a new property
16
migrate-tick-offset; by default this is 'true' and we will
17
migrate the true tick offset in a new subsection; if the
18
incoming data has no subsection we fall back to the old
19
vm_clock-based offset information, so old->new migration
20
compatibility is preserved. For complete new->old migration
21
compatibility, the property is set to 'false' for 4.0 and
22
earlier machine types (this will only affect 'virt-4.0'
23
and below, as none of the other pl031-using machines are
24
versioned).
25
26
Reported-by: Russell King <rmk@armlinux.org.uk>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
29
Message-id: 20190709143912.28905-1-peter.maydell@linaro.org
8
Message-id: 1491844419-12485-5-git-send-email-peter.maydell@linaro.org
9
---
30
---
10
target/arm/translate.c | 31 +++++++++++++++----------------
31
include/hw/timer/pl031.h | 2 +
11
1 file changed, 15 insertions(+), 16 deletions(-)
32
hw/core/machine.c | 1 +
12
33
hw/timer/pl031.c | 92 ++++++++++++++++++++++++++++++++++++++--
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
34
3 files changed, 91 insertions(+), 4 deletions(-)
35
36
diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h
14
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
38
--- a/include/hw/timer/pl031.h
16
+++ b/target/arm/translate.c
39
+++ b/include/hw/timer/pl031.h
17
@@ -XXX,XX +XXX,XX @@ static const uint8_t table_logic_cc[16] = {
40
@@ -XXX,XX +XXX,XX @@ typedef struct PL031State {
18
1, /* mvn */
41
*/
42
uint32_t tick_offset_vmstate;
43
uint32_t tick_offset;
44
+ bool tick_offset_migrated;
45
+ bool migrate_tick_offset;
46
47
uint32_t mr;
48
uint32_t lr;
49
diff --git a/hw/core/machine.c b/hw/core/machine.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/core/machine.c
52
+++ b/hw/core/machine.c
53
@@ -XXX,XX +XXX,XX @@ GlobalProperty hw_compat_4_0[] = {
54
{ "virtio-gpu-pci", "edid", "false" },
55
{ "virtio-device", "use-started", "false" },
56
{ "virtio-balloon-device", "qemu-4-0-config-size", "true" },
57
+ { "pl031", "migrate-tick-offset", "false" },
19
};
58
};
20
59
const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
21
+static inline void gen_set_condexec(DisasContext *s)
60
61
diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/timer/pl031.c
64
+++ b/hw/timer/pl031.c
65
@@ -XXX,XX +XXX,XX @@ static int pl031_pre_save(void *opaque)
66
{
67
PL031State *s = opaque;
68
69
- /* tick_offset is base_time - rtc_clock base time. Instead, we want to
70
- * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */
71
+ /*
72
+ * The PL031 device model code uses the tick_offset field, which is
73
+ * the offset between what the guest RTC should read and what the
74
+ * QEMU rtc_clock reads:
75
+ * guest_rtc = rtc_clock + tick_offset
76
+ * and so
77
+ * tick_offset = guest_rtc - rtc_clock
78
+ *
79
+ * We want to migrate this offset, which sounds straightforward.
80
+ * Unfortunately older versions of QEMU migrated a conversion of this
81
+ * offset into an offset from the vm_clock. (This was in turn an
82
+ * attempt to be compatible with even older QEMU versions, but it
83
+ * has incorrect behaviour if the rtc_clock is not the same as the
84
+ * vm_clock.) So we put the actual tick_offset into a migration
85
+ * subsection, and the backwards-compatible time-relative-to-vm_clock
86
+ * in the main migration state.
87
+ *
88
+ * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
89
+ */
90
int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
91
s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
92
93
return 0;
94
}
95
96
+static int pl031_pre_load(void *opaque)
22
+{
97
+{
23
+ if (s->condexec_mask) {
98
+ PL031State *s = opaque;
24
+ uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
99
+
25
+ TCGv_i32 tmp = tcg_temp_new_i32();
100
+ s->tick_offset_migrated = false;
26
+ tcg_gen_movi_i32(tmp, val);
101
+ return 0;
27
+ store_cpu_field(tmp, condexec_bits);
102
+}
103
+
104
static int pl031_post_load(void *opaque, int version_id)
105
{
106
PL031State *s = opaque;
107
108
- int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
109
- s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
110
+ /*
111
+ * If we got the tick_offset subsection, then we can just use
112
+ * the value in that. Otherwise the source is an older QEMU and
113
+ * has given us the offset from the vm_clock; convert it back to
114
+ * an offset from the rtc_clock. This will cause time to incorrectly
115
+ * go backwards compared to the host RTC, but this is unavoidable.
116
+ */
117
+
118
+ if (!s->tick_offset_migrated) {
119
+ int64_t delta = qemu_clock_get_ns(rtc_clock) -
120
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
121
+ s->tick_offset = s->tick_offset_vmstate -
122
+ delta / NANOSECONDS_PER_SECOND;
28
+ }
123
+ }
124
pl031_set_alarm(s);
125
return 0;
126
}
127
128
+static int pl031_tick_offset_post_load(void *opaque, int version_id)
129
+{
130
+ PL031State *s = opaque;
131
+
132
+ s->tick_offset_migrated = true;
133
+ return 0;
29
+}
134
+}
30
+
135
+
31
+static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
136
+static bool pl031_tick_offset_needed(void *opaque)
32
+{
137
+{
33
+ tcg_gen_movi_i32(cpu_R[15], val);
138
+ PL031State *s = opaque;
139
+
140
+ return s->migrate_tick_offset;
34
+}
141
+}
35
+
142
+
36
/* Set PC and Thumb state from an immediate address. */
143
+static const VMStateDescription vmstate_pl031_tick_offset = {
37
static inline void gen_bx_im(DisasContext *s, uint32_t addr)
144
+ .name = "pl031/tick-offset",
145
+ .version_id = 1,
146
+ .minimum_version_id = 1,
147
+ .needed = pl031_tick_offset_needed,
148
+ .post_load = pl031_tick_offset_post_load,
149
+ .fields = (VMStateField[]) {
150
+ VMSTATE_UINT32(tick_offset, PL031State),
151
+ VMSTATE_END_OF_LIST()
152
+ }
153
+};
154
+
155
static const VMStateDescription vmstate_pl031 = {
156
.name = "pl031",
157
.version_id = 1,
158
.minimum_version_id = 1,
159
.pre_save = pl031_pre_save,
160
+ .pre_load = pl031_pre_load,
161
.post_load = pl031_post_load,
162
.fields = (VMStateField[]) {
163
VMSTATE_UINT32(tick_offset_vmstate, PL031State),
164
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl031 = {
165
VMSTATE_UINT32(im, PL031State),
166
VMSTATE_UINT32(is, PL031State),
167
VMSTATE_END_OF_LIST()
168
+ },
169
+ .subsections = (const VMStateDescription*[]) {
170
+ &vmstate_pl031_tick_offset,
171
+ NULL
172
}
173
};
174
175
+static Property pl031_properties[] = {
176
+ /*
177
+ * True to correctly migrate the tick offset of the RTC. False to
178
+ * obtain backward migration compatibility with older QEMU versions,
179
+ * at the expense of the guest RTC going backwards compared with the
180
+ * host RTC when the VM is saved/restored if using -rtc host.
181
+ * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
182
+ * 'false' also permits newer QEMU to migrate to older QEMU.)
183
+ */
184
+ DEFINE_PROP_BOOL("migrate-tick-offset",
185
+ PL031State, migrate_tick_offset, true),
186
+ DEFINE_PROP_END_OF_LIST()
187
+};
188
+
189
static void pl031_class_init(ObjectClass *klass, void *data)
38
{
190
{
39
@@ -XXX,XX +XXX,XX @@ DO_GEN_ST(8, MO_UB)
191
DeviceClass *dc = DEVICE_CLASS(klass);
40
DO_GEN_ST(16, MO_UW)
192
41
DO_GEN_ST(32, MO_UL)
193
dc->vmsd = &vmstate_pl031;
42
194
+ dc->props = pl031_properties;
43
-static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
44
-{
45
- tcg_gen_movi_i32(cpu_R[15], val);
46
-}
47
-
48
static inline void gen_hvc(DisasContext *s, int imm16)
49
{
50
/* The pre HVC helper handles cases when HVC gets trapped
51
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
52
s->is_jmp = DISAS_SMC;
53
}
195
}
54
196
55
-static inline void
197
static const TypeInfo pl031_info = {
56
-gen_set_condexec (DisasContext *s)
57
-{
58
- if (s->condexec_mask) {
59
- uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
60
- TCGv_i32 tmp = tcg_temp_new_i32();
61
- tcg_gen_movi_i32(tmp, val);
62
- store_cpu_field(tmp, condexec_bits);
63
- }
64
-}
65
-
66
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
67
{
68
gen_set_condexec(s);
69
--
198
--
70
2.7.4
199
2.20.1
71
200
72
201
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/24] arm: Remove workarounds for old M-profile exception return implementation
[Qemu-devel] [PULL 09/10] target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
1
Now that we've rewritten M-profile exception return so that the magic
1
The ARMv5 architecture didn't specify detailed per-feature ID
2
PC values are not visible to other parts of QEMU, we can delete the
2
registers. Now that we're using the MVFR0 register fields to
3
special casing of them elsewhere.
3
gate the existence of VFP instructions, we need to set up
4
the correct values in the cpu->isar structure so that we still
5
provide an FPU to the guest.
4
6
7
This fixes a regression in the arm926 and arm1026 CPUs, which
8
are the only ones that both have VFP and are ARMv5 or earlier.
9
This regression was introduced by the VFP refactoring, and more
10
specifically by commits 1120827fa182f0e76 and 266bd25c485597c,
11
which accidentally disabled VFP short-vector support and
12
double-precision support on these CPUs.
13
14
Fixes: 1120827fa182f0e
15
Fixes: 266bd25c485597c
16
Fixes: https://bugs.launchpad.net/qemu/+bug/1836192
17
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
20
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 1491844419-12485-10-git-send-email-peter.maydell@linaro.org
21
Tested-by: Christophe Lyon <christophe.lyon@linaro.org>
22
Message-id: 20190711131241.22231-1-peter.maydell@linaro.org
9
---
23
---
10
target/arm/cpu.c | 43 ++-----------------------------------------
24
target/arm/cpu.c | 12 ++++++++++++
11
target/arm/translate.c | 8 --------
25
1 file changed, 12 insertions(+)
12
2 files changed, 2 insertions(+), 49 deletions(-)
13
26
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
27
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
29
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
30
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
31
@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
32
* set the field to indicate Jazelle support within QEMU.
33
*/
34
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
35
+ /*
36
+ * Similarly, we need to set MVFR0 fields to enable double precision
37
+ * and short vector support even though ARMv5 doesn't have this register.
38
+ */
39
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
40
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
19
}
41
}
20
42
21
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
43
static void arm946_initfn(Object *obj)
22
-static void arm_v7m_unassigned_access(CPUState *cpu, hwaddr addr,
44
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
23
- bool is_write, bool is_exec, int opaque,
45
* set the field to indicate Jazelle support within QEMU.
24
- unsigned size)
25
-{
26
- ARMCPU *arm = ARM_CPU(cpu);
27
- CPUARMState *env = &arm->env;
28
-
29
- /* ARMv7-M interrupt return works by loading a magic value into the PC.
30
- * On real hardware the load causes the return to occur. The qemu
31
- * implementation performs the jump normally, then does the exception
32
- * return by throwing a special exception when when the CPU tries to
33
- * execute code at the magic address.
34
- */
35
- if (env->v7m.exception != 0 && addr >= 0xfffffff0 && is_exec) {
36
- cpu->exception_index = EXCP_EXCEPTION_EXIT;
37
- cpu_loop_exit(cpu);
38
- }
39
-
40
- /* In real hardware an attempt to access parts of the address space
41
- * with nothing there will usually cause an external abort.
42
- * However our QEMU board models are often missing device models where
43
- * the guest can boot anyway with the default read-as-zero/writes-ignored
44
- * behaviour that you get without a QEMU unassigned_access hook.
45
- * So just return here to retain that default behaviour.
46
- */
47
-}
48
-
49
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
50
{
51
CPUClass *cc = CPU_GET_CLASS(cs);
52
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
53
CPUARMState *env = &cpu->env;
54
bool ret = false;
55
56
- /* ARMv7-M interrupt return works by loading a magic value
57
- * into the PC. On real hardware the load causes the
58
- * return to occur. The qemu implementation performs the
59
- * jump normally, then does the exception return when the
60
- * CPU tries to execute code at the magic address.
61
- * This will cause the magic PC value to be pushed to
62
- * the stack if an interrupt occurred at the wrong time.
63
- * We avoid this by disabling interrupts when
64
- * pc contains a magic address.
65
- *
66
- * ARMv7-M interrupt masking works differently than -A or -R.
67
+ /* ARMv7-M interrupt masking works differently than -A or -R.
68
* There is no FIQ/IRQ distinction. Instead of I and F bits
69
* masking FIQ and IRQ interrupts, an exception is taken only
70
* if it is higher priority than the current execution priority
71
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
72
* currently active exception).
73
*/
46
*/
74
if (interrupt_request & CPU_INTERRUPT_HARD
47
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
75
- && (armv7m_nvic_can_take_pending_exception(env->nvic))
48
+ /*
76
- && (env->regs[15] < 0xfffffff0)) {
49
+ * Similarly, we need to set MVFR0 fields to enable double precision
77
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
50
+ * and short vector support even though ARMv5 doesn't have this register.
78
cs->exception_index = EXCP_IRQ;
51
+ */
79
cc->do_interrupt(cs);
52
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
80
ret = true;
53
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
81
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
54
82
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
55
{
83
#endif
56
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
84
85
- cc->do_unassigned_access = arm_v7m_unassigned_access;
86
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
87
}
88
89
diff --git a/target/arm/translate.c b/target/arm/translate.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/translate.c
92
+++ b/target/arm/translate.c
93
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
94
dc->is_jmp = DISAS_EXC;
95
break;
96
}
97
-#else
98
- if (arm_dc_feature(dc, ARM_FEATURE_M)) {
99
- /* Branches to the magic exception-return addresses should
100
- * already have been caught via the arm_v7m_unassigned_access hook,
101
- * and never get here.
102
- */
103
- assert(dc->pc < 0xfffffff0);
104
- }
105
#endif
106
107
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
108
--
57
--
109
2.7.4
58
2.20.1
110
59
111
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/24] arm: Move condition-failed codepath generation out of if()
[Qemu-devel] [PULL 10/10] target/arm: NS BusFault on vector table fetch escalates to NS HardFault
1
Move the code to generate the "condition failed" instruction
1
In the M-profile architecture, when we do a vector table fetch and it
2
codepath out of the if (singlestepping) {} else {}. This
2
fails, we need to report a HardFault. Whether this is a Secure HF or
3
will allow adding support for handling a new is_jmp type
3
a NonSecure HF depends on several things. If AIRCR.BFHFNMINS is 0
4
which can't be neatly split into "singlestepping case"
4
then HF is always Secure, because there is no NonSecure HardFault.
5
versus "not singlestepping case".
5
Otherwise, the answer depends on whether the 'underlying exception'
6
(MemManage, BusFault, SecureFault) targets Secure or NonSecure. (In
7
the pseudocode, this is handled in the Vector() function: the final
8
exc.isSecure is calculated by looking at the exc.isSecure from the
9
exception returned from the memory access, not the isSecure input
10
argument.)
11
12
We weren't doing this correctly, because we were looking at
13
the target security domain of the exception we were trying to
14
load the vector table entry for. This produces errors of two kinds:
15
* a load from the NS vector table which hits the "NS access
16
to S memory" SecureFault should end up as a Secure HardFault,
17
but we were raising an NS HardFault
18
* a load from the S vector table which causes a BusFault
19
should raise an NS HardFault if BFHFNMINS == 1 (because
20
in that case all BusFaults are NonSecure), but we were raising
21
a Secure HardFault
22
23
Correct the logic.
24
25
We also fix a comment error where we claimed that we might
26
be escalating MemManage to HardFault, and forgot about SecureFault.
27
(Vector loads can never hit MPU access faults, because they're
28
always aligned and always use the default address map.)
6
29
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
31
Message-id: 20190705094823.28905-1-peter.maydell@linaro.org
9
Reviewed-by: Richard Henderson <rth@twiddle.net>
10
Message-id: 1491844419-12485-6-git-send-email-peter.maydell@linaro.org
11
---
32
---
12
target/arm/translate.c | 24 +++++++++++-------------
33
target/arm/m_helper.c | 21 +++++++++++++++++----
13
1 file changed, 11 insertions(+), 13 deletions(-)
34
1 file changed, 17 insertions(+), 4 deletions(-)
14
35
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
36
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
16
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
38
--- a/target/arm/m_helper.c
18
+++ b/target/arm/translate.c
39
+++ b/target/arm/m_helper.c
19
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
40
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
20
/* At this stage dc->condjmp will only be set when the skipped
41
if (sattrs.ns) {
21
instruction was a conditional branch or trap, and the PC has
42
attrs.secure = false;
22
already been written. */
43
} else if (!targets_secure) {
23
+ gen_set_condexec(dc);
44
- /* NS access to S memory */
24
if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
45
+ /*
25
/* Unconditional and "condition passed" instruction codepath. */
46
+ * NS access to S memory: the underlying exception which we escalate
26
- gen_set_condexec(dc);
47
+ * to HardFault is SecureFault, which always targets Secure.
27
switch (dc->is_jmp) {
48
+ */
28
case DISAS_SWI:
49
+ exc_secure = true;
29
gen_ss_advance(dc);
50
goto load_fail;
30
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
31
/* FIXME: Single stepping a WFI insn will not halt the CPU. */
32
gen_singlestep_exception(dc);
33
}
34
- if (dc->condjmp) {
35
- /* "Condition failed" instruction codepath. */
36
- gen_set_label(dc->condlabel);
37
- gen_set_condexec(dc);
38
- gen_set_pc_im(dc, dc->pc);
39
- gen_singlestep_exception(dc);
40
- }
41
} else {
42
/* While branches must always occur at the end of an IT block,
43
there are a few other things that can cause us to terminate
44
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
45
- Hardware watchpoints.
46
Hardware breakpoints have already been handled and skip this code.
47
*/
48
- gen_set_condexec(dc);
49
switch(dc->is_jmp) {
50
case DISAS_NEXT:
51
gen_goto_tb(dc, 1, dc->pc);
52
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
53
gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
54
break;
55
}
56
- if (dc->condjmp) {
57
- gen_set_label(dc->condlabel);
58
- gen_set_condexec(dc);
59
+ }
60
+
61
+ if (dc->condjmp) {
62
+ /* "Condition failed" instruction codepath for the branch/trap insn */
63
+ gen_set_label(dc->condlabel);
64
+ gen_set_condexec(dc);
65
+ if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
66
+ gen_set_pc_im(dc, dc->pc);
67
+ gen_singlestep_exception(dc);
68
+ } else {
69
gen_goto_tb(dc, 1, dc->pc);
70
- dc->condjmp = 0;
71
}
51
}
72
}
52
}
73
53
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
54
vector_entry = address_space_ldl(arm_addressspace(cs, attrs), addr,
55
attrs, &result);
56
if (result != MEMTX_OK) {
57
+ /*
58
+ * Underlying exception is BusFault: its target security state
59
+ * depends on BFHFNMINS.
60
+ */
61
+ exc_secure = !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
62
goto load_fail;
63
}
64
*pvec = vector_entry;
65
@@ -XXX,XX +XXX,XX @@ load_fail:
66
/*
67
* All vector table fetch fails are reported as HardFault, with
68
* HFSR.VECTTBL and .FORCED set. (FORCED is set because
69
- * technically the underlying exception is a MemManage or BusFault
70
+ * technically the underlying exception is a SecureFault or BusFault
71
* that is escalated to HardFault.) This is a terminal exception,
72
* so we will either take the HardFault immediately or else enter
73
* lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
74
+ * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
75
+ * secure); otherwise it targets the same security state as the
76
+ * underlying exception.
77
*/
78
- exc_secure = targets_secure ||
79
- !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
80
+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
81
+ exc_secure = true;
82
+ }
83
env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
84
armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
85
return false;
74
--
86
--
75
2.7.4
87
2.20.1
76
88
77
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/24] arm: Abstract out "are we singlestepping" test to utility function
Deleted patch
1
We now test for "are we singlestepping" in several places and
2
it's not a trivial check because we need to care about both
3
architectural singlestep and QEMU gdbstub singlestep. We're
4
also about to add another place that needs to make this check,
5
so pull the condition out into a function.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <rth@twiddle.net>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 1491844419-12485-7-git-send-email-peter.maydell@linaro.org
11
---
12
target/arm/translate.c | 20 +++++++++++++++-----
13
1 file changed, 15 insertions(+), 5 deletions(-)
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
18
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static void gen_singlestep_exception(DisasContext *s)
20
}
21
}
22
23
+static inline bool is_singlestepping(DisasContext *s)
24
+{
25
+ /* Return true if we are singlestepping either because of
26
+ * architectural singlestep or QEMU gdbstub singlestep. This does
27
+ * not include the command line '-singlestep' mode which is rather
28
+ * misnamed as it only means "one instruction per TB" and doesn't
29
+ * affect the code we generate.
30
+ */
31
+ return s->singlestep_enabled || s->ss_active;
32
+}
33
+
34
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
35
{
36
TCGv_i32 tmp1 = tcg_temp_new_i32();
37
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
38
39
static inline void gen_jmp (DisasContext *s, uint32_t dest)
40
{
41
- if (unlikely(s->singlestep_enabled || s->ss_active)) {
42
+ if (unlikely(is_singlestepping(s))) {
43
/* An indirect jump so that we still trigger the debug exception. */
44
if (s->thumb)
45
dest |= 1;
46
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
47
((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));
48
49
} while (!dc->is_jmp && !tcg_op_buf_full() &&
50
- !cs->singlestep_enabled &&
51
+ !is_singlestepping(dc) &&
52
!singlestep &&
53
- !dc->ss_active &&
54
!end_of_page &&
55
num_insns < max_insns);
56
57
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
58
instruction was a conditional branch or trap, and the PC has
59
already been written. */
60
gen_set_condexec(dc);
61
- if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
62
+ if (unlikely(is_singlestepping(dc))) {
63
/* Unconditional and "condition passed" instruction codepath. */
64
switch (dc->is_jmp) {
65
case DISAS_SWI:
66
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
67
/* "Condition failed" instruction codepath for the branch/trap insn */
68
gen_set_label(dc->condlabel);
69
gen_set_condexec(dc);
70
- if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
71
+ if (unlikely(is_singlestepping(dc))) {
72
gen_set_pc_im(dc, dc->pc);
73
gen_singlestep_exception(dc);
74
} else {
75
--
76
2.7.4
77
78
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/24] arm: Track M profile handler mode state in TB flags
Deleted patch
1
For M profile exception-return handling we'd like to generate different
2
code for some instructions depending on whether we are in Handler
3
mode or Thread mode. This isn't the same as "are we privileged
4
or user", so we need an extra bit in the TB flags to distinguish.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 1491844419-12485-8-git-send-email-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 9 +++++++++
12
target/arm/translate.h | 1 +
13
target/arm/translate.c | 1 +
14
3 files changed, 11 insertions(+)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
21
#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
22
#define ARM_TBFLAG_BE_DATA_SHIFT 20
23
#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
24
+/* For M profile only, Handler (ie not Thread) mode */
25
+#define ARM_TBFLAG_HANDLER_SHIFT 21
26
+#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
27
28
/* Bit usage when in AArch64 state */
29
#define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */
30
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
31
(((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
32
#define ARM_TBFLAG_BE_DATA(F) \
33
(((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
34
+#define ARM_TBFLAG_HANDLER(F) \
35
+ (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
36
#define ARM_TBFLAG_TBI0(F) \
37
(((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
38
#define ARM_TBFLAG_TBI1(F) \
39
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
40
}
41
*flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
42
43
+ if (env->v7m.exception != 0) {
44
+ *flags |= ARM_TBFLAG_HANDLER_MASK;
45
+ }
46
+
47
*cs_base = 0;
48
}
49
50
diff --git a/target/arm/translate.h b/target/arm/translate.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate.h
53
+++ b/target/arm/translate.h
54
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
55
bool vfp_enabled; /* FP enabled via FPSCR.EN */
56
int vec_len;
57
int vec_stride;
58
+ bool v7m_handler_mode;
59
/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
60
* so that top level loop can generate correct syndrome information.
61
*/
62
diff --git a/target/arm/translate.c b/target/arm/translate.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/translate.c
65
+++ b/target/arm/translate.c
66
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
67
dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
68
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
69
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
70
+ dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
71
dc->cp_regs = cpu->cp_regs;
72
dc->features = env->features;
73
74
--
75
2.7.4
76
77
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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