[Qemu-devel] [PULL 00/24] target-arm queue
[Qemu-devel] [PULL 00/16] target-arm queue
1
First ARM pullreq of the 2.10 cycle...
1
The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
2
2
3
thanks
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
4
-- PMM
5
4
6
The following changes since commit 64c8ed97cceabac4fafe17fca8d88ef08183f439:
5
are available in the Git repository at:
7
6
8
Open 2.10 development tree (2017-04-20 15:42:31 +0100)
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
9
8
10
are available in the git repository at:
9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
11
10
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170420
11
tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
13
14
for you to fetch changes up to f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa:
15
16
arm: Remove workarounds for old M-profile exception return implementation (2017-04-20 17:39:17 +0100)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* implement M profile exception return properly
15
* Fix coverity nit in int_to_float code
21
* cadence GEM: fix multiqueue handling bugs
16
* Don't set Invalid for float-to-int(MAXINT)
22
* pxa2xx.c: QOMify a device
17
* Fix fp_status_f16 tininess before rounding
23
* arm/kvm: Remove trailing newlines from error_report()
18
* Add various missing insns from the v8.2-FP16 extension
24
* stellaris: Don't hw_error() on bad register accesses
19
* Fix sqrt_f16 exception raising
25
* Add assertion about FSC format for syndrome registers
20
* sdcard: Correct CRC16 offset in sd_function_switch()
26
* Move excnames[] array into arm_log_exceptions()
21
* tcg: Optionally log FPU state in TCG -d cpu logging
27
* exynos: minor code cleanups
28
* hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
29
* Fix APSR writes via M profile MSR
30
22
31
----------------------------------------------------------------
23
----------------------------------------------------------------
32
Alistair Francis (5):
24
Alex Bennée (5):
33
cadence_gem: Read the correct queue descriptor
25
fpu/softfloat: int_to_float ensure r fully initialised
34
cadence_gem: Correct the multi-queue can rx logic
26
target/arm: Implement FCMP for fp16
35
cadence_gem: Correct the interupt logic
27
target/arm: Implement FCSEL for fp16
36
cadence_gem: Make the revision a property
28
target/arm: Implement FMOV (immediate) for fp16
37
xlnx-zynqmp: Set the Cadence GEM revision
29
target/arm: Fix sqrt_f16 exception raising
38
30
39
Ard Biesheuvel (1):
31
Peter Maydell (3):
40
hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
33
target/arm: Fix fp_status_f16 tininess before rounding
34
tcg: Optionally log FPU state in TCG -d cpu logging
41
35
42
Ishani Chugh (1):
36
Philippe Mathieu-Daudé (1):
43
arm/kvm: Remove trailing newlines from error_report()
37
sdcard: Correct CRC16 offset in sd_function_switch()
44
38
45
Krzysztof Kozlowski (3):
39
Richard Henderson (7):
46
hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
40
target/arm: Implement FMOV (general) for fp16
47
hw/char/exynos4210_uart: Constify static array and few arguments
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
48
hw/misc/exynos4210_pmu: Reorder local variables for readability
42
target/arm: Implement FCVT (scalar, integer) for fp16
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
44
target/arm: Introduce and use read_fp_hreg
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
49
47
50
Peter Maydell (13):
48
include/qemu/log.h | 1 +
51
target/arm: Add missing entries to excnames[] for log strings
49
target/arm/helper-a64.h | 2 +
52
arm: Move excnames[] array into arm_log_exceptions()
50
target/arm/helper.h | 6 +
53
target/arm: Add assertion about FSC format for syndrome registers
51
accel/tcg/cpu-exec.c | 9 +-
54
stellaris: Don't hw_error() on bad register accesses
52
fpu/softfloat.c | 6 +-
55
arm: Don't implement BXJ on M-profile CPUs
53
hw/sd/sd.c | 2 +-
56
arm: Thumb shift operations should not permit interworking branches
54
target/arm/cpu.c | 2 +
57
arm: Factor out "generate right kind of step exception"
55
target/arm/helper-a64.c | 10 ++
58
arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
56
target/arm/helper.c | 38 +++-
59
arm: Move condition-failed codepath generation out of if()
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
60
arm: Abstract out "are we singlestepping" test to utility function
58
util/log.c | 2 +
61
arm: Track M profile handler mode state in TB flags
59
11 files changed, 428 insertions(+), 71 deletions(-)
62
arm: Implement M profile exception return properly
63
arm: Remove workarounds for old M-profile exception return implementation
64
60
65
Suramya Shah (1):
66
hw/arm: Qomify pxa2xx.c
67
68
include/hw/net/cadence_gem.h | 1 +
69
target/arm/cpu.h | 10 +++
70
target/arm/internals.h | 21 -----
71
target/arm/translate.h | 5 ++
72
hw/arm/boot.c | 64 ++++++++++++---
73
hw/arm/exynos4_boards.c | 7 +-
74
hw/arm/pxa2xx.c | 14 ++--
75
hw/arm/stellaris.c | 60 ++++++++------
76
hw/arm/xlnx-zynqmp.c | 6 +-
77
hw/char/exynos4210_uart.c | 8 +-
78
hw/misc/exynos4210_pmu.c | 4 +-
79
hw/net/cadence_gem.c | 45 +++++++----
80
hw/timer/exynos4210_mct.c | 6 +-
81
hw/timer/exynos4210_pwm.c | 13 ++--
82
hw/timer/exynos4210_rtc.c | 19 ++---
83
target/arm/cpu.c | 43 +---------
84
target/arm/helper.c | 19 +++++
85
target/arm/kvm64.c | 4 +-
86
target/arm/op_helper.c | 23 ++++--
87
target/arm/translate.c | 181 +++++++++++++++++++++++++++++--------------
88
20 files changed, 341 insertions(+), 212 deletions(-)
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/24] hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
qemu_log_mask() and error_report() are preferred over fprintf() for
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
4
logging errors. Also remove square brackets [] and additional new line
4
later on so we might as well mirror that.
5
characters in printed messages.
6
5
7
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20170313184750.429-2-krzk@kernel.org
10
[PMM: wrapped long line]
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/arm/exynos4_boards.c | 7 ++++---
11
fpu/softfloat.c | 2 +-
15
hw/timer/exynos4210_mct.c | 6 ++++--
12
1 file changed, 1 insertion(+), 1 deletion(-)
16
hw/timer/exynos4210_pwm.c | 13 +++++++------
17
hw/timer/exynos4210_rtc.c | 19 ++++++++++---------
18
4 files changed, 25 insertions(+), 20 deletions(-)
19
13
20
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/exynos4_boards.c
16
--- a/fpu/softfloat.c
23
+++ b/hw/arm/exynos4_boards.c
17
+++ b/fpu/softfloat.c
24
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
25
*/
19
26
20
static FloatParts int_to_float(int64_t a, float_status *status)
27
#include "qemu/osdep.h"
21
{
28
+#include "qemu/error-report.h"
22
- FloatParts r;
29
#include "qemu-common.h"
23
+ FloatParts r = {};
30
#include "cpu.h"
24
if (a == 0) {
31
#include "sysemu/sysemu.h"
25
r.cls = float_class_zero;
32
@@ -XXX,XX +XXX,XX @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine,
26
r.sign = false;
33
MachineClass *mc = MACHINE_GET_CLASS(machine);
34
35
if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
36
- fprintf(stderr, "%s board supports only %d CPU cores. Ignoring smp_cpus"
37
- " value.\n",
38
- mc->name, EXYNOS4210_NCPUS);
39
+ error_report("%s board supports only %d CPU cores, ignoring smp_cpus"
40
+ " value",
41
+ mc->name, EXYNOS4210_NCPUS);
42
}
43
44
exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
45
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/timer/exynos4210_mct.c
48
+++ b/hw/timer/exynos4210_mct.c
49
@@ -XXX,XX +XXX,XX @@
50
*/
51
52
#include "qemu/osdep.h"
53
+#include "qemu/log.h"
54
#include "hw/sysbus.h"
55
#include "qemu/timer.h"
56
#include "qemu/main-loop.h"
57
@@ -XXX,XX +XXX,XX @@ break;
58
case L0_TCNTO: case L1_TCNTO:
59
case L0_ICNTO: case L1_ICNTO:
60
case L0_FRCNTO: case L1_FRCNTO:
61
- fprintf(stderr, "\n[exynos4210.mct: write to RO register "
62
- TARGET_FMT_plx "]\n\n", offset);
63
+ qemu_log_mask(LOG_GUEST_ERROR,
64
+ "exynos4210.mct: write to RO register " TARGET_FMT_plx,
65
+ offset);
66
break;
67
68
case L0_INT_CSTAT: case L1_INT_CSTAT:
69
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/timer/exynos4210_pwm.c
72
+++ b/hw/timer/exynos4210_pwm.c
73
@@ -XXX,XX +XXX,XX @@
74
*/
75
76
#include "qemu/osdep.h"
77
+#include "qemu/log.h"
78
#include "hw/sysbus.h"
79
#include "qemu/timer.h"
80
#include "qemu-common.h"
81
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
82
break;
83
84
default:
85
- fprintf(stderr,
86
- "[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n",
87
- offset);
88
+ qemu_log_mask(LOG_GUEST_ERROR,
89
+ "exynos4210.pwm: bad read offset " TARGET_FMT_plx,
90
+ offset);
91
break;
92
}
93
return value;
94
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset,
95
break;
96
97
default:
98
- fprintf(stderr,
99
- "[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n",
100
- offset);
101
+ qemu_log_mask(LOG_GUEST_ERROR,
102
+ "exynos4210.pwm: bad write offset " TARGET_FMT_plx,
103
+ offset);
104
break;
105
106
}
107
diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/timer/exynos4210_rtc.c
110
+++ b/hw/timer/exynos4210_rtc.c
111
@@ -XXX,XX +XXX,XX @@
112
*/
113
114
#include "qemu/osdep.h"
115
+#include "qemu/log.h"
116
#include "hw/sysbus.h"
117
#include "qemu/timer.h"
118
#include "qemu-common.h"
119
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
120
break;
121
122
default:
123
- fprintf(stderr,
124
- "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n",
125
- offset);
126
+ qemu_log_mask(LOG_GUEST_ERROR,
127
+ "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
128
+ offset);
129
break;
130
}
131
return value;
132
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
133
if (value > TICNT_THRESHOLD) {
134
s->reg_ticcnt = value;
135
} else {
136
- fprintf(stderr,
137
- "[exynos4210.rtc: bad TICNT value %u ]\n",
138
- (uint32_t)value);
139
+ qemu_log_mask(LOG_GUEST_ERROR,
140
+ "exynos4210.rtc: bad TICNT value %u",
141
+ (uint32_t)value);
142
}
143
break;
144
145
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset,
146
break;
147
148
default:
149
- fprintf(stderr,
150
- "[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n",
151
- offset);
152
+ qemu_log_mask(LOG_GUEST_ERROR,
153
+ "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
154
+ offset);
155
break;
156
157
}
158
--
27
--
159
2.7.4
28
2.17.0
160
29
161
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/24] cadence_gem: Read the correct queue descriptor
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
In float-to-integer conversion, if the floating point input
2
converts exactly to the largest or smallest integer that
3
fits in to the result type, this is not an overflow.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
2
8
3
Read the correct descriptor instead of hardcoding the first (q=0).
9
Fix the boundary case to take the right half of the if()
10
statements.
4
11
5
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
12
This fixes a regression from 2.11 introduced by the softfloat
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
refactoring.
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
8
Message-id: 988b183dcf951856d8b3379f7e911ec95233bbf4.1491947224.git.alistair.francis@xilinx.com
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
10
---
20
---
11
hw/net/cadence_gem.c | 4 ++--
21
fpu/softfloat.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
22
1 file changed, 2 insertions(+), 2 deletions(-)
13
23
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
15
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
26
--- a/fpu/softfloat.c
17
+++ b/hw/net/cadence_gem.c
27
+++ b/fpu/softfloat.c
18
@@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
19
{
29
r = UINT64_MAX;
20
DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
30
}
21
/* read current descriptor */
31
if (p.sign) {
22
- cpu_physical_memory_read(s->rx_desc_addr[0],
32
- if (r < -(uint64_t) min) {
23
- (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0]));
33
+ if (r <= -(uint64_t) min) {
24
+ cpu_physical_memory_read(s->rx_desc_addr[q],
34
return -r;
25
+ (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q]));
35
} else {
26
36
s->float_exception_flags = orig_flags | float_flag_invalid;
27
/* Descriptor owned by software ? */
37
return min;
28
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
38
}
39
} else {
40
- if (r < max) {
41
+ if (r <= max) {
42
return r;
43
} else {
44
s->float_exception_flags = orig_flags | float_flag_invalid;
29
--
45
--
30
2.7.4
46
2.17.0
31
47
32
48
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/24] arm: Remove workarounds for old M-profile exception return implementation
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
1
Now that we've rewritten M-profile exception return so that the magic
1
In commit d81ce0ef2c4f105 we added an extra float_status field
2
PC values are not visible to other parts of QEMU, we can delete the
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
3
special casing of them elsewhere.
3
by setting it to float_tininess_before_rounding. This currently
4
will only cause problems for the new V8_FP16 feature, since the
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
4
8
9
Add the missing initialization.
10
11
Fixes: d81ce0ef2c4f105
12
Cc: qemu-stable@nongnu.org
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Message-id: 1491844419-12485-10-git-send-email-peter.maydell@linaro.org
9
---
17
---
10
target/arm/cpu.c | 43 ++-----------------------------------------
18
target/arm/cpu.c | 2 ++
11
target/arm/translate.c | 8 --------
19
1 file changed, 2 insertions(+)
12
2 files changed, 2 insertions(+), 49 deletions(-)
13
20
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
23
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
19
}
26
&env->vfp.fp_status);
20
27
set_float_detect_tininess(float_tininess_before_rounding,
21
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
28
&env->vfp.standard_fp_status);
22
-static void arm_v7m_unassigned_access(CPUState *cpu, hwaddr addr,
29
+ set_float_detect_tininess(float_tininess_before_rounding,
23
- bool is_write, bool is_exec, int opaque,
30
+ &env->vfp.fp_status_f16);
24
- unsigned size)
31
#ifndef CONFIG_USER_ONLY
25
-{
32
if (kvm_enabled()) {
26
- ARMCPU *arm = ARM_CPU(cpu);
33
kvm_arm_reset_vcpu(cpu);
27
- CPUARMState *env = &arm->env;
28
-
29
- /* ARMv7-M interrupt return works by loading a magic value into the PC.
30
- * On real hardware the load causes the return to occur. The qemu
31
- * implementation performs the jump normally, then does the exception
32
- * return by throwing a special exception when when the CPU tries to
33
- * execute code at the magic address.
34
- */
35
- if (env->v7m.exception != 0 && addr >= 0xfffffff0 && is_exec) {
36
- cpu->exception_index = EXCP_EXCEPTION_EXIT;
37
- cpu_loop_exit(cpu);
38
- }
39
-
40
- /* In real hardware an attempt to access parts of the address space
41
- * with nothing there will usually cause an external abort.
42
- * However our QEMU board models are often missing device models where
43
- * the guest can boot anyway with the default read-as-zero/writes-ignored
44
- * behaviour that you get without a QEMU unassigned_access hook.
45
- * So just return here to retain that default behaviour.
46
- */
47
-}
48
-
49
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
50
{
51
CPUClass *cc = CPU_GET_CLASS(cs);
52
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
53
CPUARMState *env = &cpu->env;
54
bool ret = false;
55
56
- /* ARMv7-M interrupt return works by loading a magic value
57
- * into the PC. On real hardware the load causes the
58
- * return to occur. The qemu implementation performs the
59
- * jump normally, then does the exception return when the
60
- * CPU tries to execute code at the magic address.
61
- * This will cause the magic PC value to be pushed to
62
- * the stack if an interrupt occurred at the wrong time.
63
- * We avoid this by disabling interrupts when
64
- * pc contains a magic address.
65
- *
66
- * ARMv7-M interrupt masking works differently than -A or -R.
67
+ /* ARMv7-M interrupt masking works differently than -A or -R.
68
* There is no FIQ/IRQ distinction. Instead of I and F bits
69
* masking FIQ and IRQ interrupts, an exception is taken only
70
* if it is higher priority than the current execution priority
71
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
72
* currently active exception).
73
*/
74
if (interrupt_request & CPU_INTERRUPT_HARD
75
- && (armv7m_nvic_can_take_pending_exception(env->nvic))
76
- && (env->regs[15] < 0xfffffff0)) {
77
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
78
cs->exception_index = EXCP_IRQ;
79
cc->do_interrupt(cs);
80
ret = true;
81
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
82
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
83
#endif
84
85
- cc->do_unassigned_access = arm_v7m_unassigned_access;
86
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
87
}
88
89
diff --git a/target/arm/translate.c b/target/arm/translate.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/translate.c
92
+++ b/target/arm/translate.c
93
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
94
dc->is_jmp = DISAS_EXC;
95
break;
96
}
97
-#else
98
- if (arm_dc_feature(dc, ARM_FEATURE_M)) {
99
- /* Branches to the magic exception-return addresses should
100
- * already have been caught via the arm_v7m_unassigned_access hook,
101
- * and never get here.
102
- */
103
- assert(dc->pc < 0xfffffff0);
104
- }
105
#endif
106
107
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
108
--
34
--
109
2.7.4
35
2.17.0
110
36
111
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/24] arm: Abstract out "are we singlestepping" test to utility function
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
1
We now test for "are we singlestepping" in several places and
1
From: Richard Henderson <richard.henderson@linaro.org>
2
it's not a trivial check because we need to care about both
3
architectural singlestep and QEMU gdbstub singlestep. We're
4
also about to add another place that needs to make this check,
5
so pull the condition out into a function.
6
2
3
Adding the fp16 moves to/from general registers.
4
5
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <rth@twiddle.net>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 1491844419-12485-7-git-send-email-peter.maydell@linaro.org
11
---
11
---
12
target/arm/translate.c | 20 +++++++++++++++-----
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
13
1 file changed, 15 insertions(+), 5 deletions(-)
13
1 file changed, 21 insertions(+)
14
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void gen_singlestep_exception(DisasContext *s)
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
21
clear_vec_high(s, true, rd);
22
break;
23
+ case 3:
24
+ /* 16 bit */
25
+ tmp = tcg_temp_new_i64();
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
27
+ write_fp_dreg(s, rd, tmp);
28
+ tcg_temp_free_i64(tmp);
29
+ break;
30
+ default:
31
+ g_assert_not_reached();
32
}
33
} else {
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
36
/* 64 bits from top half */
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
38
break;
39
+ case 3:
40
+ /* 16 bit */
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
42
+ break;
43
+ default:
44
+ g_assert_not_reached();
45
}
20
}
46
}
21
}
47
}
22
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
23
+static inline bool is_singlestepping(DisasContext *s)
49
case 0xa: /* 64 bit */
24
+{
50
case 0xd: /* 64 bit to top half of quad */
25
+ /* Return true if we are singlestepping either because of
51
break;
26
+ * architectural singlestep or QEMU gdbstub singlestep. This does
52
+ case 0x6: /* 16-bit float, 32-bit int */
27
+ * not include the command line '-singlestep' mode which is rather
53
+ case 0xe: /* 16-bit float, 64-bit int */
28
+ * misnamed as it only means "one instruction per TB" and doesn't
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
29
+ * affect the code we generate.
55
+ break;
30
+ */
56
+ }
31
+ return s->singlestep_enabled || s->ss_active;
57
+ /* fallthru */
32
+}
58
default:
33
+
59
/* all other sf/type/rmode combinations are invalid */
34
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
60
unallocated_encoding(s);
35
{
36
TCGv_i32 tmp1 = tcg_temp_new_i32();
37
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
38
39
static inline void gen_jmp (DisasContext *s, uint32_t dest)
40
{
41
- if (unlikely(s->singlestep_enabled || s->ss_active)) {
42
+ if (unlikely(is_singlestepping(s))) {
43
/* An indirect jump so that we still trigger the debug exception. */
44
if (s->thumb)
45
dest |= 1;
46
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
47
((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));
48
49
} while (!dc->is_jmp && !tcg_op_buf_full() &&
50
- !cs->singlestep_enabled &&
51
+ !is_singlestepping(dc) &&
52
!singlestep &&
53
- !dc->ss_active &&
54
!end_of_page &&
55
num_insns < max_insns);
56
57
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
58
instruction was a conditional branch or trap, and the PC has
59
already been written. */
60
gen_set_condexec(dc);
61
- if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
62
+ if (unlikely(is_singlestepping(dc))) {
63
/* Unconditional and "condition passed" instruction codepath. */
64
switch (dc->is_jmp) {
65
case DISAS_SWI:
66
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
67
/* "Condition failed" instruction codepath for the branch/trap insn */
68
gen_set_label(dc->condlabel);
69
gen_set_condexec(dc);
70
- if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
71
+ if (unlikely(is_singlestepping(dc))) {
72
gen_set_pc_im(dc, dc->pc);
73
gen_singlestep_exception(dc);
74
} else {
75
--
61
--
76
2.7.4
62
2.17.0
77
63
78
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/24] hw/misc/exynos4210_pmu: Reorder local variables for readability
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Short declaration of 'i' was in the middle of declarations with
3
No sense in emitting code after the exception.
4
assignments. Make it a little bit more readable. Additionally switch
5
from "unsigned" to "unsigned int" as this pattern is more widely used.
6
No functional change.
7
4
8
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20170313184750.429-4-krzk@kernel.org
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/misc/exynos4210_pmu.c | 4 ++--
11
target/arm/translate-a64.c | 2 +-
15
1 file changed, 2 insertions(+), 2 deletions(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
16
13
17
diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/exynos4210_pmu.c
16
--- a/target/arm/translate-a64.c
20
+++ b/hw/misc/exynos4210_pmu.c
17
+++ b/target/arm/translate-a64.c
21
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
22
unsigned size)
19
default:
23
{
20
/* all other sf/type/rmode combinations are invalid */
24
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
21
unallocated_encoding(s);
25
- unsigned i;
22
- break;
26
const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
23
+ return;
27
+ unsigned int i;
24
}
28
25
29
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
26
if (!fp_access_check(s)) {
30
if (reg_p->offset == offset) {
31
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset,
32
uint64_t val, unsigned size)
33
{
34
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
35
- unsigned i;
36
const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
37
+ unsigned int i;
38
39
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
40
if (reg_p->offset == offset) {
41
--
27
--
42
2.7.4
28
2.17.0
43
29
44
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/24] arm: Move excnames[] array into arm_log_exceptions()
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
1
The excnames[] array is defined in internals.h because we used
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to use it from two different source files for handling logging
2
3
of AArch32 and AArch64 exception entry. Refactoring means that
3
Cc: qemu-stable@nongnu.org
4
it's now used only in arm_log_exception() in helper.c, so move
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
the array into that function.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 1491821097-5647-1-git-send-email-peter.maydell@linaro.org
11
---
9
---
12
target/arm/cpu.h | 2 +-
10
target/arm/helper.h | 6 +++
13
target/arm/internals.h | 23 -----------------------
11
target/arm/helper.c | 38 ++++++++++++++-
14
target/arm/helper.c | 19 +++++++++++++++++++
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
15
3 files changed, 20 insertions(+), 24 deletions(-)
13
3 files changed, 122 insertions(+), 18 deletions(-)
16
14
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
17
--- a/target/arm/helper.h
20
+++ b/target/arm/cpu.h
18
+++ b/target/arm/helper.h
21
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
22
#define EXCP_SEMIHOST 16 /* semihosting call */
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
23
#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
24
#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
25
-/* NB: new EXCP_ defines should be added to the excnames[] array too */
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
26
+/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
27
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
28
#define ARMV7M_EXCP_RESET 1
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
29
#define ARMV7M_EXCP_NMI 2
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
30
diff --git a/target/arm/internals.h b/target/arm/internals.h
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
31
index XXXXXXX..XXXXXXX 100644
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
32
--- a/target/arm/internals.h
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
33
+++ b/target/arm/internals.h
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
34
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
35
|| excp == EXCP_SEMIHOST;
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
36
}
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
37
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
38
-/* Exception names for debug logging; note that not all of these
36
39
- * precisely correspond to architectural exceptions.
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
40
- */
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
41
-static const char * const excnames[] = {
42
- [EXCP_UDEF] = "Undefined Instruction",
43
- [EXCP_SWI] = "SVC",
44
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
45
- [EXCP_DATA_ABORT] = "Data Abort",
46
- [EXCP_IRQ] = "IRQ",
47
- [EXCP_FIQ] = "FIQ",
48
- [EXCP_BKPT] = "Breakpoint",
49
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
50
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
51
- [EXCP_HVC] = "Hypervisor Call",
52
- [EXCP_HYP_TRAP] = "Hypervisor Trap",
53
- [EXCP_SMC] = "Secure Monitor Call",
54
- [EXCP_VIRQ] = "Virtual IRQ",
55
- [EXCP_VFIQ] = "Virtual FIQ",
56
- [EXCP_SEMIHOST] = "Semihosting call",
57
- [EXCP_NOCP] = "v7M NOCP UsageFault",
58
- [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
59
-};
60
-
61
/* Scale factor for generic timers, ie number of ns per tick.
62
* This gives a 62.5MHz timer.
63
*/
64
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
65
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
67
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
68
@@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx)
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
44
#undef VFP_CONV_FIX_A64
45
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
47
- * Therefore we convert to f64 (which does not round), scale,
48
- * and then convert f64 to f16 (which may round).
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
50
+ * vice versa for conversion to integer.
51
+ *
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
53
+ * For 64-bit integers, any integer that would cause rounding will also
54
+ * overflow to f16 infinity, so there is no double rounding problem.
55
*/
56
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
60
}
61
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
63
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
65
+}
66
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
68
+{
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
70
+}
71
+
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
69
{
73
{
70
if (qemu_loglevel_mask(CPU_LOG_INT)) {
74
if (unlikely(float16_is_any_nan(f))) {
71
const char *exc = NULL;
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
72
+ static const char * const excnames[] = {
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
73
+ [EXCP_UDEF] = "Undefined Instruction",
77
}
74
+ [EXCP_SWI] = "SVC",
78
75
+ [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
76
+ [EXCP_DATA_ABORT] = "Data Abort",
80
+{
77
+ [EXCP_IRQ] = "IRQ",
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
78
+ [EXCP_FIQ] = "FIQ",
82
+}
79
+ [EXCP_BKPT] = "Breakpoint",
83
+
80
+ [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
81
+ [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
85
+{
82
+ [EXCP_HVC] = "Hypervisor Call",
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
83
+ [EXCP_HYP_TRAP] = "Hypervisor Trap",
87
+}
84
+ [EXCP_SMC] = "Secure Monitor Call",
88
+
85
+ [EXCP_VIRQ] = "Virtual IRQ",
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
86
+ [EXCP_VFIQ] = "Virtual FIQ",
90
+{
87
+ [EXCP_SEMIHOST] = "Semihosting call",
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
88
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
92
+}
89
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
93
+
90
+ };
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
91
95
+{
92
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
93
exc = excnames[idx];
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
94
--
265
--
95
2.7.4
266
2.17.0
96
267
97
268
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/24] arm: Track M profile handler mode state in TB flags
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
1
For M profile exception-return handling we'd like to generate different
1
From: Richard Henderson <richard.henderson@linaro.org>
2
code for some instructions depending on whether we are in Handler
3
mode or Thread mode. This isn't the same as "are we privileged
4
or user", so we need an extra bit in the TB flags to distinguish.
5
2
3
Cc: qemu-stable@nongnu.org
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 1491844419-12485-8-git-send-email-peter.maydell@linaro.org
10
---
9
---
11
target/arm/cpu.h | 9 +++++++++
10
target/arm/translate-a64.c | 17 +++++++++++++++--
12
target/arm/translate.h | 1 +
11
1 file changed, 15 insertions(+), 2 deletions(-)
13
target/arm/translate.c | 1 +
14
3 files changed, 11 insertions(+)
15
12
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
15
--- a/target/arm/translate-a64.c
19
+++ b/target/arm/cpu.h
16
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
21
#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
18
bool sf = extract32(insn, 31, 1);
22
#define ARM_TBFLAG_BE_DATA_SHIFT 20
19
bool itof;
23
#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
20
24
+/* For M profile only, Handler (ie not Thread) mode */
21
- if (sbit || (type > 1)
25
+#define ARM_TBFLAG_HANDLER_SHIFT 21
22
- || (!sf && scale < 32)) {
26
+#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
23
+ if (sbit || (!sf && scale < 32)) {
27
24
+ unallocated_encoding(s);
28
/* Bit usage when in AArch64 state */
25
+ return;
29
#define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */
30
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
31
(((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
32
#define ARM_TBFLAG_BE_DATA(F) \
33
(((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
34
+#define ARM_TBFLAG_HANDLER(F) \
35
+ (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
36
#define ARM_TBFLAG_TBI0(F) \
37
(((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
38
#define ARM_TBFLAG_TBI1(F) \
39
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
40
}
41
*flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
42
43
+ if (env->v7m.exception != 0) {
44
+ *flags |= ARM_TBFLAG_HANDLER_MASK;
45
+ }
26
+ }
46
+
27
+
47
*cs_base = 0;
28
+ switch (type) {
48
}
29
+ case 0: /* float32 */
49
30
+ case 1: /* float64 */
50
diff --git a/target/arm/translate.h b/target/arm/translate.h
31
+ break;
51
index XXXXXXX..XXXXXXX 100644
32
+ case 3: /* float16 */
52
--- a/target/arm/translate.h
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
53
+++ b/target/arm/translate.h
34
+ break;
54
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
35
+ }
55
bool vfp_enabled; /* FP enabled via FPSCR.EN */
36
+ /* fallthru */
56
int vec_len;
37
+ default:
57
int vec_stride;
38
unallocated_encoding(s);
58
+ bool v7m_handler_mode;
39
return;
59
/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
40
}
60
* so that top level loop can generate correct syndrome information.
61
*/
62
diff --git a/target/arm/translate.c b/target/arm/translate.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/translate.c
65
+++ b/target/arm/translate.c
66
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
67
dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
68
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
69
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
70
+ dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
71
dc->cp_regs = cpu->cp_regs;
72
dc->features = env->features;
73
74
--
41
--
75
2.7.4
42
2.17.0
76
43
77
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/24] arm: Implement M profile exception return properly
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
1
On M profile, return from exceptions happen when code in Handler mode
1
From: Richard Henderson <richard.henderson@linaro.org>
2
executes one of the following function call return instructions:
3
* POP or LDM which loads the PC
4
* LDR to PC
5
* BX register
6
and the new PC value is 0xFFxxxxxx.
7
2
8
QEMU tries to implement this by not treating the instruction
3
Cc: qemu-stable@nongnu.org
9
specially but then catching the attempt to execute from the magic
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
address value. This is not ideal, because:
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
* there are guest visible differences from the architecturally
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
specified behaviour (for instance jumping to 0xFFxxxxxx via a
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
13
different instruction should not cause an exception return but it
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
will in the QEMU implementation)
9
---
15
* we have to account for it in various places (like refusing to take
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
16
an interrupt if the PC is at a magic value, and making sure that
11
1 file changed, 14 insertions(+), 16 deletions(-)
17
the MPU doesn't deny execution at the magic value addresses)
18
12
19
Drop these hacks, and instead implement exception return the way the
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
architecture specifies -- by having the relevant instructions check
21
for the magic value and raise the 'do an exception return' QEMU
22
internal exception immediately.
23
24
The effect on the generated code is minor:
25
26
bx lr, old code (and new code for Thread mode):
27
TCG:
28
mov_i32 tmp5,r14
29
movi_i32 tmp6,$0xfffffffffffffffe
30
and_i32 pc,tmp5,tmp6
31
movi_i32 tmp6,$0x1
32
and_i32 tmp5,tmp5,tmp6
33
st_i32 tmp5,env,$0x218
34
exit_tb $0x0
35
set_label $L0
36
exit_tb $0x7f2aabd61993
37
x86_64 generated code:
38
0x7f2aabe87019: mov %ebx,%ebp
39
0x7f2aabe8701b: and $0xfffffffffffffffe,%ebp
40
0x7f2aabe8701e: mov %ebp,0x3c(%r14)
41
0x7f2aabe87022: and $0x1,%ebx
42
0x7f2aabe87025: mov %ebx,0x218(%r14)
43
0x7f2aabe8702c: xor %eax,%eax
44
0x7f2aabe8702e: jmpq 0x7f2aabe7c016
45
46
bx lr, new code when in Handler mode:
47
TCG:
48
mov_i32 tmp5,r14
49
movi_i32 tmp6,$0xfffffffffffffffe
50
and_i32 pc,tmp5,tmp6
51
movi_i32 tmp6,$0x1
52
and_i32 tmp5,tmp5,tmp6
53
st_i32 tmp5,env,$0x218
54
movi_i32 tmp5,$0xffffffffff000000
55
brcond_i32 pc,tmp5,geu,$L1
56
exit_tb $0x0
57
set_label $L1
58
movi_i32 tmp5,$0x8
59
call exception_internal,$0x0,$0,env,tmp5
60
x86_64 generated code:
61
0x7fe8fa1264e3: mov %ebp,%ebx
62
0x7fe8fa1264e5: and $0xfffffffffffffffe,%ebx
63
0x7fe8fa1264e8: mov %ebx,0x3c(%r14)
64
0x7fe8fa1264ec: and $0x1,%ebp
65
0x7fe8fa1264ef: mov %ebp,0x218(%r14)
66
0x7fe8fa1264f6: cmp $0xff000000,%ebx
67
0x7fe8fa1264fc: jae 0x7fe8fa126509
68
0x7fe8fa126502: xor %eax,%eax
69
0x7fe8fa126504: jmpq 0x7fe8fa122016
70
0x7fe8fa126509: mov %r14,%rdi
71
0x7fe8fa12650c: mov $0x8,%esi
72
0x7fe8fa126511: mov $0x56095dbeccf5,%r10
73
0x7fe8fa12651b: callq *%r10
74
75
which is a difference of one cmp/branch-not-taken. This will
76
be lost in the noise of having to exit generated code and
77
look up the next TB anyway.
78
79
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80
Reviewed-by: Richard Henderson <rth@twiddle.net>
81
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
82
Message-id: 1491844419-12485-9-git-send-email-peter.maydell@linaro.org
83
---
84
target/arm/translate.h | 4 +++
85
target/arm/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++-----
86
2 files changed, 64 insertions(+), 6 deletions(-)
87
88
diff --git a/target/arm/translate.h b/target/arm/translate.h
89
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/translate.h
15
--- a/target/arm/translate-a64.c
91
+++ b/target/arm/translate.h
16
+++ b/target/arm/translate-a64.c
92
@@ -XXX,XX +XXX,XX @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
93
#define DISAS_HVC 8
18
return v;
94
#define DISAS_SMC 9
95
#define DISAS_YIELD 10
96
+/* M profile branch which might be an exception return (and so needs
97
+ * custom end-of-TB code)
98
+ */
99
+#define DISAS_BX_EXCRET 11
100
101
#ifdef TARGET_AARCH64
102
void a64_translate_init(void);
103
diff --git a/target/arm/translate.c b/target/arm/translate.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/translate.c
106
+++ b/target/arm/translate.c
107
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
108
store_cpu_field(var, thumb);
109
}
19
}
110
20
111
+/* Set PC and Thumb state from var. var is marked as dead.
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
112
+ * For M-profile CPUs, include logic to detect exception-return
113
+ * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
114
+ * and BX reg, and no others, and happens only for code in Handler mode.
115
+ */
116
+static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)
117
+{
22
+{
118
+ /* Generate the same code here as for a simple bx, but flag via
23
+ TCGv_i32 v = tcg_temp_new_i32();
119
+ * s->is_jmp that we need to do the rest of the work later.
24
+
120
+ */
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
121
+ gen_bx(s, var);
26
+ return v;
122
+ if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {
123
+ s->is_jmp = DISAS_BX_EXCRET;
124
+ }
125
+}
27
+}
126
+
28
+
127
+static inline void gen_bx_excret_final_code(DisasContext *s)
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
128
+{
30
* If SVE is not enabled, then there are only 128 bits in the vector.
129
+ /* Generate the code to finish possible exception return and end the TB */
31
*/
130
+ TCGLabel *excret_label = gen_new_label();
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
131
+
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
132
+ /* Is the new PC value in the magic range indicating exception return? */
133
+ tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);
134
+ /* No: end the TB as we would for a DISAS_JMP */
135
+ if (is_singlestepping(s)) {
136
+ gen_singlestep_exception(s);
137
+ } else {
138
+ tcg_gen_exit_tb(0);
139
+ }
140
+ gen_set_label(excret_label);
141
+ /* Yes: this is an exception return.
142
+ * At this point in runtime env->regs[15] and env->thumb will hold
143
+ * the exception-return magic number, which do_v7m_exception_exit()
144
+ * will read. Nothing else will be able to see those values because
145
+ * the cpu-exec main loop guarantees that we will always go straight
146
+ * from raising the exception to the exception-handling code.
147
+ *
148
+ * gen_ss_advance(s) does nothing on M profile currently but
149
+ * calling it is conceptually the right thing as we have executed
150
+ * this instruction (compare SWI, HVC, SMC handling).
151
+ */
152
+ gen_ss_advance(s);
153
+ gen_exception_internal(EXCP_EXCEPTION_EXIT);
154
+}
155
+
156
/* Variant of store_reg which uses branch&exchange logic when storing
157
to r15 in ARM architecture v7 and above. The source must be a temporary
158
and will be marked as dead. */
159
@@ -XXX,XX +XXX,XX @@ static inline void store_reg_bx(DisasContext *s, int reg, TCGv_i32 var)
160
static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
161
{
34
{
162
if (reg == 15 && ENABLE_ARCH_5) {
35
TCGv_ptr fpst = NULL;
163
- gen_bx(s, var);
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
164
+ gen_bx_excret(s, var);
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
39
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
41
-
42
switch (opcode) {
43
case 0x0: /* FMOV */
44
tcg_gen_mov_i32(tcg_res, tcg_op);
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
46
tcg_temp_free_i64(tcg_op2);
47
tcg_temp_free_i64(tcg_res);
165
} else {
48
} else {
166
store_reg(s, reg, var);
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
54
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
167
}
78
}
168
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
79
169
tmp = tcg_temp_new_i32();
80
if (is_scalar) {
170
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
171
if (i == 15) {
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
172
- gen_bx(s, tmp);
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
173
+ gen_bx_excret(s, tmp);
84
174
} else if (i == rn) {
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
175
loaded_var = tmp;
86
-
176
loaded_base = 1;
87
switch (fpop) {
177
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
88
case 0x1a: /* FCVTNS */
178
goto illegal_op;
89
case 0x1b: /* FCVTMS */
179
}
180
if (rs == 15) {
181
- gen_bx(s, tmp);
182
+ gen_bx_excret(s, tmp);
183
} else {
184
store_reg(s, rs, tmp);
185
}
186
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
187
tmp2 = tcg_temp_new_i32();
188
tcg_gen_movi_i32(tmp2, val);
189
store_reg(s, 14, tmp2);
190
+ gen_bx(s, tmp);
191
+ } else {
192
+ /* Only BX works as exception-return, not BLX */
193
+ gen_bx_excret(s, tmp);
194
}
195
- /* already thumb, no need to check */
196
- gen_bx(s, tmp);
197
break;
198
}
199
break;
200
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
201
instruction was a conditional branch or trap, and the PC has
202
already been written. */
203
gen_set_condexec(dc);
204
- if (unlikely(is_singlestepping(dc))) {
205
+ if (dc->is_jmp == DISAS_BX_EXCRET) {
206
+ /* Exception return branches need some special case code at the
207
+ * end of the TB, which is complex enough that it has to
208
+ * handle the single-step vs not and the condition-failed
209
+ * insn codepath itself.
210
+ */
211
+ gen_bx_excret_final_code(dc);
212
+ } else if (unlikely(is_singlestepping(dc))) {
213
/* Unconditional and "condition passed" instruction codepath. */
214
switch (dc->is_jmp) {
215
case DISAS_SWI:
216
--
90
--
217
2.7.4
91
2.17.0
218
92
219
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/24] arm: Factor out "generate right kind of step exception"
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
1
We currently have two places that do:
1
From: Richard Henderson <richard.henderson@linaro.org>
2
if (dc->ss_active) {
3
gen_step_complete_exception(dc);
4
} else {
5
gen_exception_internal(EXCP_DEBUG);
6
}
7
2
8
Factor this out into its own function, as we're about to add
3
We missed all of the scalar fp16 binary operations.
9
a third place that needs the same logic.
10
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <rth@twiddle.net>
14
Message-id: 1491844419-12485-4-git-send-email-peter.maydell@linaro.org
15
---
11
---
16
target/arm/translate.c | 28 ++++++++++++++++------------
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
17
1 file changed, 16 insertions(+), 12 deletions(-)
13
1 file changed, 65 insertions(+)
18
14
19
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate.c
17
--- a/target/arm/translate-a64.c
22
+++ b/target/arm/translate.c
18
+++ b/target/arm/translate-a64.c
23
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
24
s->is_jmp = DISAS_EXC;
20
tcg_temp_free_i64(tcg_res);
25
}
21
}
26
22
27
+static void gen_singlestep_exception(DisasContext *s)
23
+/* Floating-point data-processing (2 source) - half precision */
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
25
+ int rd, int rn, int rm)
28
+{
26
+{
29
+ /* Generate the right kind of exception for singlestep, which is
27
+ TCGv_i32 tcg_op1;
30
+ * either the architectural singlestep or EXCP_DEBUG for QEMU's
28
+ TCGv_i32 tcg_op2;
31
+ * gdb singlestepping.
29
+ TCGv_i32 tcg_res;
32
+ */
30
+ TCGv_ptr fpst;
33
+ if (s->ss_active) {
31
+
34
+ gen_step_complete_exception(s);
32
+ tcg_res = tcg_temp_new_i32();
35
+ } else {
33
+ fpst = get_fpstatus_ptr(true);
36
+ gen_exception_internal(EXCP_DEBUG);
34
+ tcg_op1 = read_fp_hreg(s, rn);
35
+ tcg_op2 = read_fp_hreg(s, rm);
36
+
37
+ switch (opcode) {
38
+ case 0x0: /* FMUL */
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
40
+ break;
41
+ case 0x1: /* FDIV */
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
43
+ break;
44
+ case 0x2: /* FADD */
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
66
+ default:
67
+ g_assert_not_reached();
37
+ }
68
+ }
69
+
70
+ write_fp_sreg(s, rd, tcg_res);
71
+
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
38
+}
76
+}
39
+
77
+
40
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
78
/* Floating point data-processing (2 source)
41
{
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
42
TCGv_i32 tmp1 = tcg_temp_new_i32();
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
43
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
44
gen_set_pc_im(dc, dc->pc);
45
/* fall through */
46
default:
47
- if (dc->ss_active) {
48
- gen_step_complete_exception(dc);
49
- } else {
50
- /* FIXME: Single stepping a WFI insn will not halt
51
- the CPU. */
52
- gen_exception_internal(EXCP_DEBUG);
53
- }
54
+ /* FIXME: Single stepping a WFI insn will not halt the CPU. */
55
+ gen_singlestep_exception(dc);
56
}
82
}
57
if (dc->condjmp) {
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
58
/* "Condition failed" instruction codepath. */
84
break;
59
gen_set_label(dc->condlabel);
85
+ case 3:
60
gen_set_condexec(dc);
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
61
gen_set_pc_im(dc, dc->pc);
87
+ unallocated_encoding(s);
62
- if (dc->ss_active) {
88
+ return;
63
- gen_step_complete_exception(dc);
89
+ }
64
- } else {
90
+ if (!fp_access_check(s)) {
65
- gen_exception_internal(EXCP_DEBUG);
91
+ return;
66
- }
92
+ }
67
+ gen_singlestep_exception(dc);
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
68
}
94
+ break;
69
} else {
95
default:
70
/* While branches must always occur at the end of an IT block,
96
unallocated_encoding(s);
97
}
71
--
98
--
72
2.7.4
99
2.17.0
73
100
74
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/24] hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
1
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The arm64 boot protocol stipulates that the kernel must be loaded
3
We missed all of the scalar fp16 fma operations.
4
TEXT_OFFSET bytes beyond a 2 MB aligned base address, where TEXT_OFFSET
5
could be any 4 KB multiple between 0 and 2 MB, and whose value can be
6
found in the header of the Image file.
7
4
8
So after attempts to load the arm64 kernel image as an ELF file or as a
5
Cc: qemu-stable@nongnu.org
9
U-Boot image have failed (both of which have their own way of specifying
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
the load offset), try to determine the TEXT_OFFSET from the image after
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
loading it but before mapping it as a ROM mapping into the guest address
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
space.
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
13
14
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 1489414630-21609-1-git-send-email-ard.biesheuvel@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
hw/arm/boot.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++----------
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
20
1 file changed, 53 insertions(+), 11 deletions(-)
13
1 file changed, 48 insertions(+)
21
14
22
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/boot.c
17
--- a/target/arm/translate-a64.c
25
+++ b/hw/arm/boot.c
18
+++ b/target/arm/translate-a64.c
26
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
27
#define KERNEL_LOAD_ADDR 0x00010000
20
tcg_temp_free_i64(tcg_res);
28
#define KERNEL64_LOAD_ADDR 0x00080000
21
}
29
22
30
+#define ARM64_TEXT_OFFSET_OFFSET 8
23
+/* Floating-point data-processing (3 source) - half precision */
31
+#define ARM64_MAGIC_OFFSET 56
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
25
+ int rd, int rn, int rm, int ra)
26
+{
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
32
+
30
+
33
typedef enum {
31
+ tcg_op1 = read_fp_hreg(s, rn);
34
FIXUP_NONE = 0, /* do nothing */
32
+ tcg_op2 = read_fp_hreg(s, rm);
35
FIXUP_TERMINATOR, /* end of insns */
33
+ tcg_op3 = read_fp_hreg(s, ra);
36
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
37
return ret;
38
}
39
40
+static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
41
+ hwaddr *entry)
42
+{
43
+ hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
44
+ uint8_t *buffer;
45
+ int size;
46
+
34
+
47
+ /* On aarch64, it's the bootloader's job to uncompress the kernel. */
35
+ /* These are fused multiply-add, and must be done as one
48
+ size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
36
+ * floating point operation with no rounding between the
49
+ &buffer);
37
+ * multiplication and addition steps.
50
+
38
+ * NB that doing the negations here as separate steps is
51
+ if (size < 0) {
39
+ * correct : an input NaN should come out with its sign bit
52
+ gsize len;
40
+ * flipped if it is a negated-input.
53
+
41
+ */
54
+ /* Load as raw file otherwise */
42
+ if (o1 == true) {
55
+ if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
56
+ return -1;
57
+ }
58
+ size = len;
59
+ }
44
+ }
60
+
45
+
61
+ /* check the arm64 magic header value -- very old kernels may not have it */
46
+ if (o0 != o1) {
62
+ if (memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
63
+ uint64_t hdrvals[2];
64
+
65
+ /* The arm64 Image header has text_offset and image_size fields at 8 and
66
+ * 16 bytes into the Image header, respectively. The text_offset field
67
+ * is only valid if the image_size is non-zero.
68
+ */
69
+ memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
70
+ if (hdrvals[1] != 0) {
71
+ kernel_load_offset = le64_to_cpu(hdrvals[0]);
72
+ }
73
+ }
48
+ }
74
+
49
+
75
+ *entry = mem_base + kernel_load_offset;
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
76
+ rom_add_blob_fixed(filename, buffer, size, *entry);
77
+
51
+
78
+ g_free(buffer);
52
+ write_fp_sreg(s, rd, tcg_res);
79
+
53
+
80
+ return size;
54
+ tcg_temp_free_ptr(fpst);
55
+ tcg_temp_free_i32(tcg_op1);
56
+ tcg_temp_free_i32(tcg_op2);
57
+ tcg_temp_free_i32(tcg_op3);
58
+ tcg_temp_free_i32(tcg_res);
81
+}
59
+}
82
+
60
+
83
static void arm_load_kernel_notify(Notifier *notifier, void *data)
61
/* Floating point data-processing (3 source)
84
{
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
85
CPUState *cs;
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
86
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
87
int is_linux = 0;
88
uint64_t elf_entry, elf_low_addr, elf_high_addr;
89
int elf_machine;
90
- hwaddr entry, kernel_load_offset;
91
+ hwaddr entry;
92
static const ARMInsnFixup *primary_loader;
93
ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier,
94
notifier, notifier);
95
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
96
97
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
98
primary_loader = bootloader_aarch64;
99
- kernel_load_offset = KERNEL64_LOAD_ADDR;
100
elf_machine = EM_AARCH64;
101
} else {
102
primary_loader = bootloader;
103
if (!info->write_board_setup) {
104
primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
105
}
65
}
106
- kernel_load_offset = KERNEL_LOAD_ADDR;
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
107
elf_machine = EM_ARM;
67
break;
68
+ case 3:
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
70
+ unallocated_encoding(s);
71
+ return;
72
+ }
73
+ if (!fp_access_check(s)) {
74
+ return;
75
+ }
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
77
+ break;
78
default:
79
unallocated_encoding(s);
108
}
80
}
109
110
@@ -XXX,XX +XXX,XX @@ static void arm_load_kernel_notify(Notifier *notifier, void *data)
111
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
112
&is_linux, NULL, NULL);
113
}
114
- /* On aarch64, it's the bootloader's job to uncompress the kernel. */
115
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
116
- entry = info->loader_start + kernel_load_offset;
117
- kernel_size = load_image_gzipped(info->kernel_filename, entry,
118
- info->ram_size - kernel_load_offset);
119
+ kernel_size = load_aarch64_image(info->kernel_filename,
120
+ info->loader_start, &entry);
121
is_linux = 1;
122
- }
123
- if (kernel_size < 0) {
124
- entry = info->loader_start + kernel_load_offset;
125
+ } else if (kernel_size < 0) {
126
+ /* 32-bit ARM */
127
+ entry = info->loader_start + KERNEL_LOAD_ADDR;
128
kernel_size = load_image_targphys(info->kernel_filename, entry,
129
- info->ram_size - kernel_load_offset);
130
+ info->ram_size - KERNEL_LOAD_ADDR);
131
is_linux = 1;
132
}
133
if (kernel_size < 0) {
134
--
81
--
135
2.7.4
82
2.17.0
136
83
137
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/24] hw/arm: Qomify pxa2xx.c
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
1
From: Suramya Shah <shah.suramya@gmail.com>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Signed-off-by: Suramya Shah <shah.suramya@gmail.com>
3
These where missed out from the rest of the half-precision work.
4
Message-id: 20170415180316.2694-1-shah.suramya@gmail.com
4
5
Cc: qemu-stable@nongnu.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
14
---
8
hw/arm/pxa2xx.c | 14 ++++++--------
15
target/arm/helper-a64.h | 2 +
9
1 file changed, 6 insertions(+), 8 deletions(-)
16
target/arm/helper-a64.c | 10 +++++
10
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
11
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/pxa2xx.c
22
--- a/target/arm/helper-a64.h
14
+++ b/hw/arm/pxa2xx.c
23
+++ b/target/arm/helper-a64.h
15
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_reset(DeviceState *d)
24
@@ -XXX,XX +XXX,XX @@
16
s->rx_start = s->rx_level = 0;
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
36
+++ b/target/arm/helper-a64.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
38
return flags;
17
}
39
}
18
40
19
-static int pxa2xx_ssp_init(SysBusDevice *sbd)
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
20
+static void pxa2xx_ssp_init(Object *obj)
42
+{
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
44
+}
45
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
47
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
49
+}
50
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
21
{
52
{
22
- DeviceState *dev = DEVICE(sbd);
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
23
- PXA2xxSSPState *s = PXA2XX_SSP(dev);
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
24
-
55
index XXXXXXX..XXXXXXX 100644
25
+ DeviceState *dev = DEVICE(obj);
56
--- a/target/arm/translate-a64.c
26
+ PXA2xxSSPState *s = PXA2XX_SSP(obj);
57
+++ b/target/arm/translate-a64.c
27
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
28
sysbus_init_irq(sbd, &s->irq);
59
}
29
30
- memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
31
+ memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
32
"pxa2xx-ssp", 0x1000);
33
sysbus_init_mmio(sbd, &s->iomem);
34
35
s->bus = ssi_create_bus(dev, "ssi");
36
- return 0;
37
}
60
}
38
61
39
/* Real-Time Clock */
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
40
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
63
+static void handle_fp_compare(DisasContext *s, int size,
41
64
unsigned int rn, unsigned int rm,
42
static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
65
bool cmp_with_zero, bool signal_all_nans)
43
{
66
{
44
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
45
DeviceClass *dc = DEVICE_CLASS(klass);
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
46
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
47
- sdc->init = pxa2xx_ssp_init;
70
48
dc->reset = pxa2xx_ssp_reset;
71
- if (is_double) {
49
dc->vmsd = &vmstate_pxa2xx_ssp;
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
50
}
164
}
51
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pxa2xx_ssp_info = {
165
52
.name = TYPE_PXA2XX_SSP,
166
/* Floating point conditional compare
53
.parent = TYPE_SYS_BUS_DEVICE,
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
54
.instance_size = sizeof(PXA2xxSSPState),
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
55
+ .instance_init = pxa2xx_ssp_init,
169
TCGv_i64 tcg_flags;
56
.class_init = pxa2xx_ssp_class_init,
170
TCGLabel *label_continue = NULL;
57
};
171
+ int size;
58
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
59
--
214
--
60
2.7.4
215
2.17.0
61
216
62
217
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/24] cadence_gem: Correct the interupt logic
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
This patch fixes two mistakes in the interrupt logic.
3
These were missed out from the rest of the half-precision work.
4
4
5
First we only trigger single-queue or multi-queue interrupts if the status
5
Cc: qemu-stable@nongnu.org
6
register is set. This logic was already used for non multi-queue interrupts
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
but it also applies to multi-queue interrupts.
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
16
1 file changed, 25 insertions(+), 6 deletions(-)
8
17
9
Secondly we need to lower the interrupts if the ISR isn't set. As part
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
of this we can remove the other interrupt lowering logic and consolidate
11
it inside gem_update_int_status().
12
13
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
14
Message-id: 438bcc014f8f8a2f8f68f322cb6a53f4c04688c2.1491947224.git.alistair.francis@xilinx.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/net/cadence_gem.c | 18 +++++++++++++-----
19
1 file changed, 13 insertions(+), 5 deletions(-)
20
21
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
22
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/net/cadence_gem.c
20
--- a/target/arm/translate-a64.c
24
+++ b/hw/net/cadence_gem.c
21
+++ b/target/arm/translate-a64.c
25
@@ -XXX,XX +XXX,XX @@ static void gem_update_int_status(CadenceGEMState *s)
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
26
{
23
unsigned int mos, type, rm, cond, rn, rd;
27
int i;
24
TCGv_i64 t_true, t_false, t_zero;
28
25
DisasCompare64 c;
29
- if ((s->num_priority_queues == 1) && s->regs[GEM_ISR]) {
26
+ TCGMemOp sz;
30
+ if (!s->regs[GEM_ISR]) {
27
31
+ /* ISR isn't set, clear all the interrupts */
28
mos = extract32(insn, 29, 3);
32
+ for (i = 0; i < s->num_priority_queues; ++i) {
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
33
+ qemu_set_irq(s->irq[i], 0);
30
+ type = extract32(insn, 22, 2);
34
+ }
31
rm = extract32(insn, 16, 5);
32
cond = extract32(insn, 12, 4);
33
rn = extract32(insn, 5, 5);
34
rd = extract32(insn, 0, 5);
35
36
- if (mos || type > 1) {
37
+ if (mos) {
38
+ unallocated_encoding(s);
35
+ return;
39
+ return;
36
+ }
40
+ }
37
+
41
+
38
+ /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
42
+ switch (type) {
39
+ * check it again.
43
+ case 0:
40
+ */
44
+ sz = MO_32;
41
+ if (s->num_priority_queues == 1) {
45
+ break;
42
/* No priority queues, just trigger the interrupt */
46
+ case 1:
43
DB_PRINT("asserting int.\n");
47
+ sz = MO_64;
44
qemu_set_irq(s->irq[0], 1);
48
+ break;
45
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
49
+ case 3:
46
{
50
+ sz = MO_16;
47
CadenceGEMState *s;
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
48
uint32_t retval;
52
+ break;
49
- int i;
53
+ }
50
s = (CadenceGEMState *)opaque;
54
+ /* fallthru */
51
55
+ default:
52
offset >>= 2;
56
unallocated_encoding(s);
53
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
57
return;
54
switch (offset) {
58
}
55
case GEM_ISR:
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
56
DB_PRINT("lowering irqs on ISR read\n");
60
return;
57
- for (i = 0; i < s->num_priority_queues; ++i) {
61
}
58
- qemu_set_irq(s->irq[i], 0);
62
59
- }
63
- /* Zero extend sreg inputs to 64 bits now. */
60
+ /* The interrupts get updated at the end of the function. */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
61
break;
65
t_true = tcg_temp_new_i64();
62
case GEM_PHYMNTNC:
66
t_false = tcg_temp_new_i64();
63
if (retval & GEM_PHYMNTNC_OP_R) {
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
64
--
83
--
65
2.7.4
84
2.17.0
66
85
67
86
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/24] arm/kvm: Remove trailing newlines from error_report()
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
1
From: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Signed-off-by: Ishani Chugh <chugh.ishani@research.iiit.ac.in>
3
All the hard work is already done by vfp_expand_imm, we just need to
4
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
4
make sure we pick up the correct size.
5
Message-id: 1491629987-6826-1-git-send-email-chugh.ishani@research.iiit.ac.in
5
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
15
---
8
target/arm/kvm64.c | 4 ++--
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
9
1 file changed, 2 insertions(+), 2 deletions(-)
17
1 file changed, 17 insertions(+), 3 deletions(-)
10
18
11
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/kvm64.c
21
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/kvm64.c
22
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
16
* single step at this point so something has gone wrong.
24
{
17
*/
25
int rd = extract32(insn, 0, 5);
18
error_report("%s: guest single-step while debugging unsupported"
26
int imm8 = extract32(insn, 13, 8);
19
- " (%"PRIx64", %"PRIx32")\n",
27
- int is_double = extract32(insn, 22, 2);
20
+ " (%"PRIx64", %"PRIx32")",
28
+ int type = extract32(insn, 22, 2);
21
__func__, env->pc, debug_exit->hsr);
29
uint64_t imm;
22
return false;
30
TCGv_i64 tcg_res;
23
}
31
+ TCGMemOp sz;
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
32
25
break;
33
- if (is_double > 1) {
34
+ switch (type) {
35
+ case 0:
36
+ sz = MO_32;
37
+ break;
38
+ case 1:
39
+ sz = MO_64;
40
+ break;
41
+ case 3:
42
+ sz = MO_16;
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
44
+ break;
45
+ }
46
+ /* fallthru */
47
+ default:
48
unallocated_encoding(s);
49
return;
26
}
50
}
27
default:
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
28
- error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")\n",
52
return;
29
+ error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")",
30
__func__, debug_exit->hsr, env->pc);
31
}
53
}
32
54
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
56
+ imm = vfp_expand_imm(sz, imm8);
57
58
tcg_res = tcg_const_i64(imm);
59
write_fp_dreg(s, rd, tcg_res);
33
--
60
--
34
2.7.4
61
2.17.0
35
62
36
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/24] xlnx-zynqmp: Set the Cadence GEM revision
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
1
From: Alistair Francis <alistair.francis@xilinx.com>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
3
We are meant to explicitly pass fpst, not cpu_env.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
5
Message-id: 026dbe01a1d42619eee30ce3f2079741bf04bc73.1491947224.git.alistair.francis@xilinx.com
5
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
hw/arm/xlnx-zynqmp.c | 6 +++++-
13
target/arm/translate-a64.c | 3 ++-
9
1 file changed, 5 insertions(+), 1 deletion(-)
14
1 file changed, 2 insertions(+), 1 deletion(-)
10
15
11
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/xlnx-zynqmp.c
18
--- a/target/arm/translate-a64.c
14
+++ b/hw/arm/xlnx-zynqmp.c
19
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
16
#define ARM_PHYS_TIMER_PPI 30
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
17
#define ARM_VIRT_TIMER_PPI 27
22
break;
18
23
case 0x3: /* FSQRT */
19
+#define GEM_REVISION 0x40070106
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
20
+
25
+ fpst = get_fpstatus_ptr(true);
21
#define GIC_BASE_ADDR 0xf9000000
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
22
#define GIC_DIST_ADDR 0xf9010000
27
break;
23
#define GIC_CPU_ADDR 0xf9020000
28
case 0x8: /* FRINTN */
24
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
29
case 0x9: /* FRINTP */
25
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
26
qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
27
}
28
+ object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
29
+ &error_abort);
30
object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
31
- &error_abort);
32
+ &error_abort);
33
object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
34
if (err) {
35
error_propagate(errp, err);
36
--
30
--
37
2.7.4
31
2.17.0
38
32
39
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/24] hw/char/exynos4210_uart: Constify static array and few arguments
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
1
From: Krzysztof Kozlowski <krzk@kernel.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The static array exynos4210_uart_regs with register values is not
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
4
modified so it can be made const.
5
4
6
Few other functions accept driver or uart state as an argument but they
5
The block length is predefined to 512 bits
7
do not change it and do not cast it so this can be made const for code
8
safeness.
9
6
10
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
7
and "4.10.2 SD Status":
11
Message-id: 20170313184750.429-3-krzk@kernel.org
8
9
The SD Status contains status bits that are related to the SD Memory Card
10
proprietary features and may be used for future application-specific usage.
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
20
---
15
hw/char/exynos4210_uart.c | 8 ++++----
21
hw/sd/sd.c | 2 +-
16
1 file changed, 4 insertions(+), 4 deletions(-)
22
1 file changed, 1 insertion(+), 1 deletion(-)
17
23
18
diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/exynos4210_uart.c
26
--- a/hw/sd/sd.c
21
+++ b/hw/char/exynos4210_uart.c
27
+++ b/hw/sd/sd.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210UartReg {
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
23
uint32_t reset_value;
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
24
} Exynos4210UartReg;
30
}
25
31
memset(&sd->data[17], 0, 47);
26
-static Exynos4210UartReg exynos4210_uart_regs[] = {
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
27
+static const Exynos4210UartReg exynos4210_uart_regs[] = {
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
28
{"ULCON", ULCON, 0x00000000},
29
{"UCON", UCON, 0x00003000},
30
{"UFCON", UFCON, 0x00000000},
31
@@ -XXX,XX +XXX,XX @@ static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
32
return ret;
33
}
34
}
34
35
35
-static int fifo_elements_number(Exynos4210UartFIFO *q)
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
36
+static int fifo_elements_number(const Exynos4210UartFIFO *q)
37
{
38
if (q->sp < q->rp) {
39
return q->size - q->rp + q->sp;
40
@@ -XXX,XX +XXX,XX @@ static int fifo_elements_number(Exynos4210UartFIFO *q)
41
return q->sp - q->rp;
42
}
43
44
-static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
45
+static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
46
{
47
return q->size - fifo_elements_number(q);
48
}
49
@@ -XXX,XX +XXX,XX @@ static void fifo_reset(Exynos4210UartFIFO *q)
50
q->rp = 0;
51
}
52
53
-static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
54
+static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
55
{
56
uint32_t level = 0;
57
uint32_t reg;
58
--
37
--
59
2.7.4
38
2.17.0
60
39
61
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/24] target/arm: Add missing entries to excnames[] for log strings
Deleted patch
1
Recent changes have added new EXCP_ values to ARM but forgot
2
to update the excnames[] array which is used to provide
3
human-readable strings when printing information about the
4
exception for debug logging. Add the missing entries, and
5
add a comment to the list of #defines to help avoid the mistake
6
being repeated in future.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Message-id: 1491486340-25988-1-git-send-email-peter.maydell@linaro.org
12
---
13
target/arm/cpu.h | 1 +
14
target/arm/internals.h | 2 ++
15
2 files changed, 3 insertions(+)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@
22
#define EXCP_SEMIHOST 16 /* semihosting call */
23
#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
24
#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
25
+/* NB: new EXCP_ defines should be added to the excnames[] array too */
26
27
#define ARMV7M_EXCP_RESET 1
28
#define ARMV7M_EXCP_NMI 2
29
diff --git a/target/arm/internals.h b/target/arm/internals.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/internals.h
32
+++ b/target/arm/internals.h
33
@@ -XXX,XX +XXX,XX @@ static const char * const excnames[] = {
34
[EXCP_VIRQ] = "Virtual IRQ",
35
[EXCP_VFIQ] = "Virtual FIQ",
36
[EXCP_SEMIHOST] = "Semihosting call",
37
+ [EXCP_NOCP] = "v7M NOCP UsageFault",
38
+ [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
39
};
40
41
/* Scale factor for generic timers, ie number of ns per tick.
42
--
43
2.7.4
44
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/24] target/arm: Add assertion about FSC format for syndrome registers
Deleted patch
1
In tlb_fill() we construct a syndrome register value from a
2
fault status register value which is filled in by arm_tlb_fill().
3
arm_tlb_fill() returns FSR values which might be in the format
4
used with short-format page descriptors, or the format used
5
with long-format (LPAE) descriptors. The syndrome register
6
always uses LPAE-format FSR status codes.
7
1
8
It isn't actually possible to end up delivering a syndrome
9
register value to the guest for a fault which is reported
10
with a short-format FSR (that kind of stage 1 fault will only
11
happen for an AArch32 translation regime which doesn't have
12
a syndrome register, and can never be redirected to an AArch64
13
or Hyp exception level). Add an assertion which checks this,
14
and adjust the code so that we construct a syndrome with
15
an invalid status code, rather than allowing set bits in
16
the FSR input to randomly corrupt other fields in the syndrome.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
20
Message-id: 1491486152-24304-1-git-send-email-peter.maydell@linaro.org
21
---
22
target/arm/op_helper.c | 23 ++++++++++++++++++-----
23
1 file changed, 18 insertions(+), 5 deletions(-)
24
25
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/op_helper.c
28
+++ b/target/arm/op_helper.c
29
@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
30
if (unlikely(ret)) {
31
ARMCPU *cpu = ARM_CPU(cs);
32
CPUARMState *env = &cpu->env;
33
- uint32_t syn, exc;
34
+ uint32_t syn, exc, fsc;
35
unsigned int target_el;
36
bool same_el;
37
38
@@ -XXX,XX +XXX,XX @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
39
env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
40
}
41
same_el = arm_current_el(env) == target_el;
42
- /* AArch64 syndrome does not have an LPAE bit */
43
- syn = fsr & ~(1 << 9);
44
+
45
+ if (fsr & (1 << 9)) {
46
+ /* LPAE format fault status register : bottom 6 bits are
47
+ * status code in the same form as needed for syndrome
48
+ */
49
+ fsc = extract32(fsr, 0, 6);
50
+ } else {
51
+ /* Short format FSR : this fault will never actually be reported
52
+ * to an EL that uses a syndrome register. Check that here,
53
+ * and use a (currently) reserved FSR code in case the constructed
54
+ * syndrome does leak into the guest somehow.
55
+ */
56
+ assert(target_el != 2 && !arm_el_is_aa64(env, target_el));
57
+ fsc = 0x3f;
58
+ }
59
60
/* For insn and data aborts we assume there is no instruction syndrome
61
* information; this is always true for exceptions reported to EL1.
62
*/
63
if (access_type == MMU_INST_FETCH) {
64
- syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
65
+ syn = syn_insn_abort(same_el, 0, fi.s1ptw, fsc);
66
exc = EXCP_PREFETCH_ABORT;
67
} else {
68
syn = merge_syn_data_abort(env->exception.syndrome, target_el,
69
same_el, fi.s1ptw,
70
- access_type == MMU_DATA_STORE, syn);
71
+ access_type == MMU_DATA_STORE, fsc);
72
if (access_type == MMU_DATA_STORE
73
&& arm_feature(env, ARM_FEATURE_V6)) {
74
fsr |= (1 << 11);
75
--
76
2.7.4
77
78
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/24] stellaris: Don't hw_error() on bad register accesses
Deleted patch
1
Current recommended style is to log a guest error on bad register
2
accesses, not kill the whole system with hw_error(). Change the
3
hw_error() calls to log as LOG_GUEST_ERROR or LOG_UNIMP or use
4
g_assert_not_reached() as appropriate.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 1491486314-25823-1-git-send-email-peter.maydell@linaro.org
9
---
10
hw/arm/stellaris.c | 60 +++++++++++++++++++++++++++++++++---------------------
11
1 file changed, 37 insertions(+), 23 deletions(-)
12
13
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/stellaris.c
16
+++ b/hw/arm/stellaris.c
17
@@ -XXX,XX +XXX,XX @@ static void gptm_reload(gptm_state *s, int n, int reset)
18
} else if (s->mode[n] == 0xa) {
19
/* PWM mode. Not implemented. */
20
} else {
21
- hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
22
+ qemu_log_mask(LOG_UNIMP,
23
+ "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
24
+ s->mode[n]);
25
+ return;
26
}
27
s->tick[n] = tick;
28
timer_mod(s->timer[n], tick);
29
@@ -XXX,XX +XXX,XX @@ static void gptm_tick(void *opaque)
30
} else if (s->mode[n] == 0xa) {
31
/* PWM mode. Not implemented. */
32
} else {
33
- hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
34
+ qemu_log_mask(LOG_UNIMP,
35
+ "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
36
+ s->mode[n]);
37
}
38
gptm_update_irq(s);
39
}
40
@@ -XXX,XX +XXX,XX @@ static void gptm_write(void *opaque, hwaddr offset,
41
s->match_prescale[0] = value;
42
break;
43
default:
44
- hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
45
+ qemu_log_mask(LOG_GUEST_ERROR,
46
+ "GPTM: read at bad offset 0x%x\n", (int)offset);
47
}
48
gptm_update_irq(s);
49
}
50
@@ -XXX,XX +XXX,XX @@ static int ssys_board_class(const ssys_state *s)
51
}
52
/* for unknown classes, fall through */
53
default:
54
- hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
55
+ /* This can only happen if the hardwired constant did0 value
56
+ * in this board's stellaris_board_info struct is wrong.
57
+ */
58
+ g_assert_not_reached();
59
}
60
}
61
62
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
63
case DID0_CLASS_SANDSTORM:
64
return pllcfg_sandstorm[xtal];
65
default:
66
- hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
67
- return 0;
68
+ g_assert_not_reached();
69
}
70
}
71
case 0x070: /* RCC2 */
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
73
case 0x1e4: /* USER1 */
74
return s->user1;
75
default:
76
- hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
77
+ qemu_log_mask(LOG_GUEST_ERROR,
78
+ "SSYS: read at bad offset 0x%x\n", (int)offset);
79
return 0;
80
}
81
}
82
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
83
s->ldoarst = value;
84
break;
85
default:
86
- hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
87
+ qemu_log_mask(LOG_GUEST_ERROR,
88
+ "SSYS: write at bad offset 0x%x\n", (int)offset);
89
}
90
ssys_update(s);
91
}
92
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
93
case 0x20: /* MCR */
94
return s->mcr;
95
default:
96
- hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
97
+ qemu_log_mask(LOG_GUEST_ERROR,
98
+ "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
99
return 0;
100
}
101
}
102
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
103
s->mris &= ~value;
104
break;
105
case 0x20: /* MCR */
106
- if (value & 1)
107
- hw_error(
108
- "stellaris_i2c_write: Loopback not implemented\n");
109
- if (value & 0x20)
110
- hw_error(
111
- "stellaris_i2c_write: Slave mode not implemented\n");
112
+ if (value & 1) {
113
+ qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
114
+ }
115
+ if (value & 0x20) {
116
+ qemu_log_mask(LOG_UNIMP,
117
+ "stellaris_i2c: Slave mode not implemented");
118
+ }
119
s->mcr = value & 0x31;
120
break;
121
default:
122
- hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
123
- (int)offset);
124
+ qemu_log_mask(LOG_GUEST_ERROR,
125
+ "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
126
}
127
stellaris_i2c_update(s);
128
}
129
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
130
case 0x30: /* SAC */
131
return s->sac;
132
default:
133
- hw_error("strllaris_adc_read: Bad offset 0x%x\n",
134
- (int)offset);
135
+ qemu_log_mask(LOG_GUEST_ERROR,
136
+ "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
137
return 0;
138
}
139
}
140
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
141
return;
142
case 0x04: /* SSCTL */
143
if (value != 6) {
144
- hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
145
- value);
146
+ qemu_log_mask(LOG_UNIMP,
147
+ "ADC: Unimplemented sequence %" PRIx64 "\n",
148
+ value);
149
}
150
s->ssctl[n] = value;
151
return;
152
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
153
s->sspri = value;
154
break;
155
case 0x28: /* PSSI */
156
- hw_error("Not implemented: ADC sample initiate\n");
157
+ qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
158
break;
159
case 0x30: /* SAC */
160
s->sac = value;
161
break;
162
default:
163
- hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
164
+ qemu_log_mask(LOG_GUEST_ERROR,
165
+ "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
166
}
167
stellaris_adc_update(s);
168
}
169
--
170
2.7.4
171
172
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/24] cadence_gem: Correct the multi-queue can rx logic
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
Correct the buffer descriptor busy logic to work correctly when using
4
multiple queues.
5
6
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 8a7e8059984e27d46a276a66299d035a0afd280f.1491947224.git.alistair.francis@xilinx.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/net/cadence_gem.c | 17 ++++++++++-------
12
1 file changed, 10 insertions(+), 7 deletions(-)
13
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
17
+++ b/hw/net/cadence_gem.c
18
@@ -XXX,XX +XXX,XX @@ static int gem_can_receive(NetClientState *nc)
19
}
20
21
for (i = 0; i < s->num_priority_queues; i++) {
22
- if (rx_desc_get_ownership(s->rx_desc[i]) == 1) {
23
- if (s->can_rx_state != 2) {
24
- s->can_rx_state = 2;
25
- DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n",
26
- i, s->rx_desc_addr[i]);
27
- }
28
- return 0;
29
+ if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
30
+ break;
31
+ }
32
+ };
33
+
34
+ if (i == s->num_priority_queues) {
35
+ if (s->can_rx_state != 2) {
36
+ s->can_rx_state = 2;
37
+ DB_PRINT("can't receive - all the buffer descriptors are busy\n");
38
}
39
+ return 0;
40
}
41
42
if (s->can_rx_state != 0) {
43
--
44
2.7.4
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/24] cadence_gem: Make the revision a property
Deleted patch
1
From: Alistair Francis <alistair.francis@xilinx.com>
2
1
3
Expose the Cadence GEM revision as a property.
4
5
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 541324373cf87b50f8be0439a0cb89f5028b016f.1491947224.git.alistair.francis@xilinx.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/net/cadence_gem.h | 1 +
12
hw/net/cadence_gem.c | 6 +++++-
13
2 files changed, 6 insertions(+), 1 deletion(-)
14
15
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/net/cadence_gem.h
18
+++ b/include/hw/net/cadence_gem.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
20
uint8_t num_priority_queues;
21
uint8_t num_type1_screeners;
22
uint8_t num_type2_screeners;
23
+ uint32_t revision;
24
25
/* GEM registers backing store */
26
uint32_t regs[CADENCE_GEM_MAXREG];
27
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/net/cadence_gem.c
30
+++ b/hw/net/cadence_gem.c
31
@@ -XXX,XX +XXX,XX @@
32
#define DESC_1_RX_SOF 0x00004000
33
#define DESC_1_RX_EOF 0x00008000
34
35
+#define GEM_MODID_VALUE 0x00020118
36
+
37
static inline unsigned tx_desc_get_buffer(unsigned *desc)
38
{
39
return desc[0];
40
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
41
s->regs[GEM_TXPAUSE] = 0x0000ffff;
42
s->regs[GEM_TXPARTIALSF] = 0x000003ff;
43
s->regs[GEM_RXPARTIALSF] = 0x000003ff;
44
- s->regs[GEM_MODID] = 0x00020118;
45
+ s->regs[GEM_MODID] = s->revision;
46
s->regs[GEM_DESCONF] = 0x02500111;
47
s->regs[GEM_DESCONF2] = 0x2ab13fff;
48
s->regs[GEM_DESCONF5] = 0x002f2145;
49
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_cadence_gem = {
50
51
static Property gem_properties[] = {
52
DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
53
+ DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
54
+ GEM_MODID_VALUE),
55
DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
56
num_priority_queues, 1),
57
DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
58
--
59
2.7.4
60
61
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/24] arm: Don't implement BXJ on M-profile CPUs
Deleted patch
1
For M-profile CPUs, the BXJ instruction does not exist at all, and
2
the encoding should always UNDEF. We were accidentally implementing
3
it to behave like A-profile BXJ; correct the error.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Message-id: 1491844419-12485-2-git-send-email-peter.maydell@linaro.org
9
---
10
target/arm/translate.c | 7 ++++++-
11
1 file changed, 6 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
18
}
19
break;
20
case 4: /* bxj */
21
- /* Trivial implementation equivalent to bx. */
22
+ /* Trivial implementation equivalent to bx.
23
+ * This instruction doesn't exist at all for M-profile.
24
+ */
25
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
26
+ goto illegal_op;
27
+ }
28
tmp = load_reg(s, rn);
29
gen_bx(s, tmp);
30
break;
31
--
32
2.7.4
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/24] arm: Thumb shift operations should not permit interworking branches
Deleted patch
1
In Thumb mode, the only instructions which can cause an interworking
2
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
3
ARM mode, data processing instructions which target the PC do not
4
cause interworking branches.
5
1
6
When we added support for doing interworking branches on writes to
7
PC from data processing instructions in commit 21aeb3430ce7ba, we
8
accidentally changed a Thumb instruction to have interworking
9
branch behaviour for writes to PC. (MOV, MOVS register-shifted
10
register, encoding T2; this is the standard encoding for
11
LSL/LSR/ASR/ROR (register).)
12
13
For this encoding, behaviour with Rd == R15 is specified as
14
UNPREDICTABLE, so allowing an interworking branch is within
15
spec, but it's confusing and differs from our handling of this
16
class of UNPREDICTABLE for other Thumb ALU operations. Make
17
it perform a simple (non-interworking) branch like the others.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <rth@twiddle.net>
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Message-id: 1491844419-12485-3-git-send-email-peter.maydell@linaro.org
23
---
24
target/arm/translate.c | 2 +-
25
1 file changed, 1 insertion(+), 1 deletion(-)
26
27
diff --git a/target/arm/translate.c b/target/arm/translate.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/translate.c
30
+++ b/target/arm/translate.c
31
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
32
gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
33
if (logic_cc)
34
gen_logic_CC(tmp);
35
- store_reg_bx(s, rd, tmp);
36
+ store_reg(s, rd, tmp);
37
break;
38
case 1: /* Sign/zero extend. */
39
op = (insn >> 20) & 7;
40
--
41
2.7.4
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/24] arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
Deleted patch
1
Move the utility routines gen_set_condexec() and gen_set_pc_im()
2
up in the file, as we will want to use them from a function
3
placed earlier in the file than their current location.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <rth@twiddle.net>
8
Message-id: 1491844419-12485-5-git-send-email-peter.maydell@linaro.org
9
---
10
target/arm/translate.c | 31 +++++++++++++++----------------
11
1 file changed, 15 insertions(+), 16 deletions(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static const uint8_t table_logic_cc[16] = {
18
1, /* mvn */
19
};
20
21
+static inline void gen_set_condexec(DisasContext *s)
22
+{
23
+ if (s->condexec_mask) {
24
+ uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
25
+ TCGv_i32 tmp = tcg_temp_new_i32();
26
+ tcg_gen_movi_i32(tmp, val);
27
+ store_cpu_field(tmp, condexec_bits);
28
+ }
29
+}
30
+
31
+static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
32
+{
33
+ tcg_gen_movi_i32(cpu_R[15], val);
34
+}
35
+
36
/* Set PC and Thumb state from an immediate address. */
37
static inline void gen_bx_im(DisasContext *s, uint32_t addr)
38
{
39
@@ -XXX,XX +XXX,XX @@ DO_GEN_ST(8, MO_UB)
40
DO_GEN_ST(16, MO_UW)
41
DO_GEN_ST(32, MO_UL)
42
43
-static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
44
-{
45
- tcg_gen_movi_i32(cpu_R[15], val);
46
-}
47
-
48
static inline void gen_hvc(DisasContext *s, int imm16)
49
{
50
/* The pre HVC helper handles cases when HVC gets trapped
51
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
52
s->is_jmp = DISAS_SMC;
53
}
54
55
-static inline void
56
-gen_set_condexec (DisasContext *s)
57
-{
58
- if (s->condexec_mask) {
59
- uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
60
- TCGv_i32 tmp = tcg_temp_new_i32();
61
- tcg_gen_movi_i32(tmp, val);
62
- store_cpu_field(tmp, condexec_bits);
63
- }
64
-}
65
-
66
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
67
{
68
gen_set_condexec(s);
69
--
70
2.7.4
71
72
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/24] arm: Move condition-failed codepath generation out of if()
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
1
Move the code to generate the "condition failed" instruction
1
Usually the logging of the CPU state produced by -d cpu is sufficient
2
codepath out of the if (singlestepping) {} else {}. This
2
to diagnose problems, but sometimes you want to see the state of
3
will allow adding support for handling a new is_jmp type
3
the floating point registers as well. We don't want to enable that
4
which can't be neatly split into "singlestepping case"
4
by default as it adds a lot of extra data to the log; instead,
5
versus "not singlestepping case".
5
allow it to be optionally enabled via -d fpu.
6
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <rth@twiddle.net>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
10
Message-id: 1491844419-12485-6-git-send-email-peter.maydell@linaro.org
11
---
10
---
12
target/arm/translate.c | 24 +++++++++++-------------
11
include/qemu/log.h | 1 +
13
1 file changed, 11 insertions(+), 13 deletions(-)
12
accel/tcg/cpu-exec.c | 9 ++++++---
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
14
15
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
18
--- a/include/qemu/log.h
18
+++ b/target/arm/translate.c
19
+++ b/include/qemu/log.h
19
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
20
/* At this stage dc->condjmp will only be set when the skipped
21
#define CPU_LOG_PAGE (1 << 14)
21
instruction was a conditional branch or trap, and the PC has
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
22
already been written. */
23
#define CPU_LOG_TB_OP_IND (1 << 16)
23
+ gen_set_condexec(dc);
24
+#define CPU_LOG_TB_FPU (1 << 17)
24
if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
25
25
/* Unconditional and "condition passed" instruction codepath. */
26
/* Lock output for a series of related logs. Since this is not needed
26
- gen_set_condexec(dc);
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
27
switch (dc->is_jmp) {
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
28
case DISAS_SWI:
29
index XXXXXXX..XXXXXXX 100644
29
gen_ss_advance(dc);
30
--- a/accel/tcg/cpu-exec.c
30
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
31
+++ b/accel/tcg/cpu-exec.c
31
/* FIXME: Single stepping a WFI insn will not halt the CPU. */
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
32
gen_singlestep_exception(dc);
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
33
}
34
&& qemu_log_in_addr_range(itb->pc)) {
34
- if (dc->condjmp) {
35
qemu_log_lock();
35
- /* "Condition failed" instruction codepath. */
36
+ int flags = 0;
36
- gen_set_label(dc->condlabel);
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
37
- gen_set_condexec(dc);
38
+ flags |= CPU_DUMP_FPU;
38
- gen_set_pc_im(dc, dc->pc);
39
+ }
39
- gen_singlestep_exception(dc);
40
#if defined(TARGET_I386)
40
- }
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
41
} else {
42
-#else
42
/* While branches must always occur at the end of an IT block,
43
- log_cpu_state(cpu, 0);
43
there are a few other things that can cause us to terminate
44
+ flags |= CPU_DUMP_CCOP;
44
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
45
#endif
45
- Hardware watchpoints.
46
+ log_cpu_state(cpu, flags);
46
Hardware breakpoints have already been handled and skip this code.
47
qemu_log_unlock();
47
*/
48
- gen_set_condexec(dc);
49
switch(dc->is_jmp) {
50
case DISAS_NEXT:
51
gen_goto_tb(dc, 1, dc->pc);
52
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
53
gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
54
break;
55
}
56
- if (dc->condjmp) {
57
- gen_set_label(dc->condlabel);
58
- gen_set_condexec(dc);
59
+ }
60
+
61
+ if (dc->condjmp) {
62
+ /* "Condition failed" instruction codepath for the branch/trap insn */
63
+ gen_set_label(dc->condlabel);
64
+ gen_set_condexec(dc);
65
+ if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
66
+ gen_set_pc_im(dc, dc->pc);
67
+ gen_singlestep_exception(dc);
68
+ } else {
69
gen_goto_tb(dc, 1, dc->pc);
70
- dc->condjmp = 0;
71
}
72
}
48
}
73
49
#endif /* DEBUG_DISAS */
50
diff --git a/util/log.c b/util/log.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/util/log.c
53
+++ b/util/log.c
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
55
"show trace before each executed TB (lots of logs)" },
56
{ CPU_LOG_TB_CPU, "cpu",
57
"show CPU registers before entering a TB (lots of logs)" },
58
+ { CPU_LOG_TB_FPU, "fpu",
59
+ "include FPU registers in the 'cpu' logging" },
60
{ CPU_LOG_MMU, "mmu",
61
"log MMU-related activities" },
62
{ CPU_LOG_PCALL, "pcall",
74
--
63
--
75
2.7.4
64
2.17.0
76
65
77
66
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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