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[Qemu-devel] [PATCH] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read

Bernhard Kaindl posted 1 patch 7 years ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/1492620502-71509-1-git-send-email-bernhard.kaindl@thalesgroup.com
Test checkpatch failed
Test docker passed
Test s390x passed
target/ppc/translate_init.c | 10 ++++++++++
1 file changed, 10 insertions(+)
[Qemu-devel] [PATCH] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read
Posted by Bernhard Kaindl 7 years ago 
This patch registers mfspr 259 for Book3S and e500 family cores
following this research:

mfspr 259 provides read-only mapped user access to SPRG3(SPR 275) according to:

- PowerISA 2.02, Book III (documents implementation starting with POWER4+ @ p20)
- IBM PowerPC 970MP RISC Microprocessor User's Manual v2.1, page 48
- Amit Singh: "Mac OS X Internals: A Systems Approach" on 970 and 970FX cores:
  He demonstrates mfspr 259 reading TLS data from Mac OS X on G5 on page 588
- NXP documents it in the Core Reference Manuals of: e500, e500mc and e5500
- getcpu() of the 32 & 64-bit Book3S Linux vDSOs use it to read the core number

mfspr 259 does not appear to be implemented in these cores according to:

- 74xx series: MPC7410/MPC7400 and MPC7450 RISC Microprocessor Reference Manuals
- 4xx series:  PPC440 Processor User's Manual, Revision 1.09 by AMCC
- 750 series:  IBM PowerPC 750CL RISC Microprocessor User's Manual
- e200 series: e200z4 Power Architectureâ Core Reference Manual

Implementation: gen_spr_usprg3() is called from init_proc_book3s_common()
(covers the 970 and POWER cores) and init_proc_e500() (covers the e500 family)
to register spr_read_ureg() in the same way which it already provides
the mapped SPR access for SPR_USPRG4-7 in gen_spr_usprgh() for cores
which have the same read-only mapped SPRG register access for SPRG4-7.

Verified using Linux by pinning a thread to a core and checking sched_getcpu()
using qemu-system-ppc64 -M pseries -cpu POWER8 using MTTCG on a x86_64 host.

Signed-off-by: Bernhard Kaindl <bernhard.kaindl@thalesgroup.com>
Reviewed-by: Stefan Resch <stefan.resch@thalesgroup.com>
---
 target/ppc/translate_init.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 77e5463..0ecf541 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -1640,6 +1640,14 @@ static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
 }
 #endif
 
+static void gen_spr_usprg3 (CPUPPCState *env)
+{
+    spr_register(env, SPR_USPRG3, "USPRG3",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+}
+
 static void gen_spr_usprgh (CPUPPCState *env)
 {
     spr_register(env, SPR_USPRG4, "USPRG4",
@@ -4914,6 +4922,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
             break;
     }
     gen_spr_BookE(env, ivor_mask);
+    gen_spr_usprg3(env);
     /* Processor identification */
     spr_register(env, SPR_BOOKE_PIR, "PIR",
                  SPR_NOACCESS, SPR_NOACCESS,
@@ -8245,6 +8254,7 @@ static void init_proc_book3s_common(CPUPPCState *env)
 {
     gen_spr_ne_601(env);
     gen_tbl(env);
+    gen_spr_usprg3(env);
     gen_spr_book3s_altivec(env);
     gen_spr_book3s_pmu_sup(env);
     gen_spr_book3s_pmu_user(env);
-- 
1.9.1
Re: [Qemu-devel] [PATCH] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read
Posted by no-reply@patchew.org 7 years ago 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1492620502-71509-1-git-send-email-bernhard.kaindl@thalesgroup.com
Subject: [Qemu-devel] [PATCH] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/1491277689-24949-1-git-send-email-Ashish.Mittal@veritas.com -> patchew/1491277689-24949-1-git-send-email-Ashish.Mittal@veritas.com
 * [new tag]         patchew/1492620502-71509-1-git-send-email-bernhard.kaindl@thalesgroup.com -> patchew/1492620502-71509-1-git-send-email-bernhard.kaindl@thalesgroup.com
Switched to a new branch 'test'
67b6203 e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read

=== OUTPUT BEGIN ===
Checking PATCH 1/1: e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read...
ERROR: space prohibited between function name and open parenthesis '('
#50: FILE: target/ppc/translate_init.c:1637:
+static void gen_spr_usprg3 (CPUPPCState *env)

total: 1 errors, 0 warnings, 28 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


---
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Re: [Qemu-devel] [PATCH] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read
Posted by David Gibson 7 years ago 
On Wed, Apr 19, 2017 at 06:48:22PM +0200, Bernhard Kaindl wrote:
> This patch registers mfspr 259 for Book3S and e500 family cores
> following this research:
> 
> mfspr 259 provides read-only mapped user access to SPRG3(SPR 275) according to:
> 
> - PowerISA 2.02, Book III (documents implementation starting with POWER4+ @ p20)
> - IBM PowerPC 970MP RISC Microprocessor User's Manual v2.1, page 48
> - Amit Singh: "Mac OS X Internals: A Systems Approach" on 970 and 970FX cores:
>   He demonstrates mfspr 259 reading TLS data from Mac OS X on G5 on page 588
> - NXP documents it in the Core Reference Manuals of: e500, e500mc and e5500
> - getcpu() of the 32 & 64-bit Book3S Linux vDSOs use it to read the core number
> 
> mfspr 259 does not appear to be implemented in these cores according to:
> 
> - 74xx series: MPC7410/MPC7400 and MPC7450 RISC Microprocessor Reference Manuals
> - 4xx series:  PPC440 Processor User's Manual, Revision 1.09 by AMCC
> - 750 series:  IBM PowerPC 750CL RISC Microprocessor User's Manual
> - e200 series: e200z4 Power Architectureâ Core Reference Manual
> 
> Implementation: gen_spr_usprg3() is called from init_proc_book3s_common()
> (covers the 970 and POWER cores) and init_proc_e500() (covers the e500 family)
> to register spr_read_ureg() in the same way which it already provides
> the mapped SPR access for SPR_USPRG4-7 in gen_spr_usprgh() for cores
> which have the same read-only mapped SPRG register access for SPRG4-7.
> 
> Verified using Linux by pinning a thread to a core and checking sched_getcpu()
> using qemu-system-ppc64 -M pseries -cpu POWER8 using MTTCG on a x86_64 host.
> 
> Signed-off-by: Bernhard Kaindl <bernhard.kaindl@thalesgroup.com>
> Reviewed-by: Stefan Resch <stefan.resch@thalesgroup.com>

Applied to ppc-for-2.10. thanks.

> ---
>  target/ppc/translate_init.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 77e5463..0ecf541 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -1640,6 +1640,14 @@ static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
>  }
>  #endif
>  
> +static void gen_spr_usprg3 (CPUPPCState *env)
> +{
> +    spr_register(env, SPR_USPRG3, "USPRG3",
> +                 &spr_read_ureg, SPR_NOACCESS,
> +                 &spr_read_ureg, SPR_NOACCESS,
> +                 0x00000000);
> +}
> +
>  static void gen_spr_usprgh (CPUPPCState *env)
>  {
>      spr_register(env, SPR_USPRG4, "USPRG4",
> @@ -4914,6 +4922,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
>              break;
>      }
>      gen_spr_BookE(env, ivor_mask);
> +    gen_spr_usprg3(env);
>      /* Processor identification */
>      spr_register(env, SPR_BOOKE_PIR, "PIR",
>                   SPR_NOACCESS, SPR_NOACCESS,
> @@ -8245,6 +8254,7 @@ static void init_proc_book3s_common(CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
>      gen_tbl(env);
> +    gen_spr_usprg3(env);
>      gen_spr_book3s_altivec(env);
>      gen_spr_book3s_pmu_sup(env);
>      gen_spr_book3s_pmu_user(env);

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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