[Qemu-devel] [PULL for-2.9 0/4] target-arm queue
[PULL v2 00/57] target-arm queue
1
Small target-arm queue for 2.9: just the patches
1
Squashed in a trivial fix for 32-bit hosts:
2
which fix bugs in our MRS/MSR decoding for M profile,
3
including a fix for a regression introduced in commit
4
58117c9bb429cd.
5
2
6
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
7
-- PMM
15
-- PMM
8
16
9
The following changes since commit 00e7c07b06d004cf54b19724f82afde8a7a37f37:
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
10
18
11
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170320' into staging (2017-03-20 10:51:30 +0000)
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
12
20
13
are available in the git repository at:
21
are available in the Git repository at:
14
22
15
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170320
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
16
24
17
for you to fetch changes up to b28b3377d7e9ba35611d454d5a63ef50cab1f8c5:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
18
26
19
arm: Fix APSR writes via M profile MSR (2017-03-20 12:41:44 +0000)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
20
28
21
----------------------------------------------------------------
29
----------------------------------------------------------------
22
target-arm queue:
30
target-arm queue:
23
* fix MSR/MRS decoding for M profile CPUs
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
32
* docs: Document which architecture extensions we emulate
33
* Fix bugs in M-profile FPCXT_NS accesses
34
* First slice of MVE patches
35
* Implement MTE3
36
* docs/system: arm: Add nRF boards description
24
37
25
----------------------------------------------------------------
38
----------------------------------------------------------------
26
Peter Maydell (4):
39
Alexandre Iooss (1):
27
arm: HVC and SMC encodings don't exist for M profile
40
docs/system: arm: Add nRF boards description
28
arm: Don't decode MRS(banked) or MSR(banked) for M profile
29
arm: Enforce should-be-1 bits in MRS decoding
30
arm: Fix APSR writes via M profile MSR
31
41
32
target/arm/helper.c | 26 ++++++++++++++++++++++----
42
Peter Collingbourne (1):
33
target/arm/translate.c | 26 +++++++++++++++++++++++---
43
target/arm: Implement MTE3
34
2 files changed, 45 insertions(+), 7 deletions(-)
35
44
45
Peter Maydell (55):
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
47
hw/acpi: Provide function acpi_ghes_present()
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
101
102
docs/system/arm/emulation.rst | 103 ++++
103
docs/system/arm/nrf.rst | 51 ++
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
135
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/4] arm: HVC and SMC encodings don't exist for M profile
Deleted patch
1
M profile doesn't have the HVC or SMC encodings, so make them always
2
UNDEF rather than generating calls to helper functions that assume
3
A/R profile.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1487616072-9226-2-git-send-email-peter.maydell@linaro.org
8
---
9
target/arm/translate.c | 3 +++
10
1 file changed, 3 insertions(+)
11
12
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate.c
15
+++ b/target/arm/translate.c
16
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
17
goto illegal_op;
18
19
if (insn & (1 << 26)) {
20
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
21
+ goto illegal_op;
22
+ }
23
if (!(insn & (1 << 20))) {
24
/* Hypervisor call (v7) */
25
int imm16 = extract32(insn, 16, 4) << 12
26
--
27
2.7.4
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/4] arm: Don't decode MRS(banked) or MSR(banked) for M profile
Deleted patch
1
M profile doesn't have the MSR(banked) and MRS(banked) instructions
2
and uses the encodings for different kinds of M-profile MRS/MSR.
3
Guard the relevant bits of the decode logic to make sure we don't
4
accidentally fall into them by accident on M-profile.
5
1
6
(The bit being checked for this (bit 5) is part of the SYSm field on
7
M-profile, but since no currently allocated system registers have
8
encodings with bit 5 of SYSm set, this hasn't been a problem in
9
practice.)
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 1487616072-9226-3-git-send-email-peter.maydell@linaro.org
14
---
15
target/arm/translate.c | 6 ++++--
16
1 file changed, 4 insertions(+), 2 deletions(-)
17
18
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate.c
21
+++ b/target/arm/translate.c
22
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
23
gen_exception_return(s, tmp);
24
break;
25
case 6: /* MRS */
26
- if (extract32(insn, 5, 1)) {
27
+ if (extract32(insn, 5, 1) &&
28
+ !arm_dc_feature(s, ARM_FEATURE_M)) {
29
/* MRS (banked) */
30
int sysm = extract32(insn, 16, 4) |
31
(extract32(insn, 4, 1) << 4);
32
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
33
store_reg(s, rd, tmp);
34
break;
35
case 7: /* MRS */
36
- if (extract32(insn, 5, 1)) {
37
+ if (extract32(insn, 5, 1) &&
38
+ !arm_dc_feature(s, ARM_FEATURE_M)) {
39
/* MRS (banked) */
40
int sysm = extract32(insn, 16, 4) |
41
(extract32(insn, 4, 1) << 4);
42
--
43
2.7.4
44
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/4] arm: Enforce should-be-1 bits in MRS decoding
Deleted patch
1
The MRS instruction requires that bits [19..16] are all 1s, and for
2
A/R profile also that bits [7..0] are all 0s. At this point in the
3
decode tree we have checked all of the rest of the instruction but
4
were allowing these to be any value. If these bits are not set then
5
the result is architecturally UNPREDICTABLE, but choosing to UNDEF is
6
more helpful to the user and avoids unexpected odd behaviour if the
7
encodings are used for some purpose in future architecture versions.
8
1
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 1487616072-9226-4-git-send-email-peter.maydell@linaro.org
12
---
13
target/arm/translate.c | 14 ++++++++++++++
14
1 file changed, 14 insertions(+)
15
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate.c
19
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
21
break;
22
}
23
24
+ if (extract32(insn, 16, 4) != 0xf) {
25
+ goto illegal_op;
26
+ }
27
+ if (!arm_dc_feature(s, ARM_FEATURE_M) &&
28
+ extract32(insn, 0, 8) != 0) {
29
+ goto illegal_op;
30
+ }
31
+
32
/* mrs cpsr */
33
tmp = tcg_temp_new_i32();
34
if (arm_dc_feature(s, ARM_FEATURE_M)) {
35
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
36
if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
37
goto illegal_op;
38
}
39
+
40
+ if (extract32(insn, 16, 4) != 0xf ||
41
+ extract32(insn, 0, 8) != 0) {
42
+ goto illegal_op;
43
+ }
44
+
45
tmp = load_cpu_field(spsr);
46
store_reg(s, rd, tmp);
47
break;
48
--
49
2.7.4
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/4] arm: Fix APSR writes via M profile MSR
Deleted patch
1
Our implementation of writes to the APSR for M-profile via the MSR
2
instruction was badly broken.
3
1
4
First and worst, we had the sense wrong on the test of bit 2 of the
5
SYSm field -- this is supposed to request an APSR write if bit 2 is 0
6
but we were doing it if bit 2 was 1. This bug was introduced in
7
commit 58117c9bb429cd, so hasn't been in a QEMU release.
8
9
Secondly, the choice of exactly which parts of APSR should be written
10
is defined by bits in the 'mask' field. We were not passing these
11
through from instruction decode, making it impossible to check them
12
in the helper.
13
14
Pass the mask bits through from the instruction decode to the helper
15
function and process them appropriately; fix the wrong sense of the
16
SYSm bit 2 check.
17
18
Invalid mask values and invalid combinations of mask and register
19
number are UNPREDICTABLE; we choose to treat them as if the mask
20
values were valid.
21
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Message-id: 1487616072-9226-5-git-send-email-peter.maydell@linaro.org
24
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
25
---
26
target/arm/helper.c | 26 ++++++++++++++++++++++----
27
target/arm/translate.c | 3 ++-
28
2 files changed, 24 insertions(+), 5 deletions(-)
29
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
35
}
36
}
37
38
-void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
39
-{
40
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
41
+{
42
+ /* We're passed bits [11..0] of the instruction; extract
43
+ * SYSm and the mask bits.
44
+ * Invalid combinations of SYSm and mask are UNPREDICTABLE;
45
+ * we choose to treat them as if the mask bits were valid.
46
+ * NB that the pseudocode 'mask' variable is bits [11..10],
47
+ * whereas ours is [11..8].
48
+ */
49
+ uint32_t mask = extract32(maskreg, 8, 4);
50
+ uint32_t reg = extract32(maskreg, 0, 8);
51
+
52
if (arm_current_el(env) == 0 && reg > 7) {
53
/* only xPSR sub-fields may be written by unprivileged */
54
return;
55
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
56
switch (reg) {
57
case 0 ... 7: /* xPSR sub-fields */
58
/* only APSR is actually writable */
59
- if (reg & 4) {
60
- xpsr_write(env, val, 0xf8000000); /* APSR */
61
+ if (!(reg & 4)) {
62
+ uint32_t apsrmask = 0;
63
+
64
+ if (mask & 8) {
65
+ apsrmask |= 0xf8000000; /* APSR NZCVQ */
66
+ }
67
+ if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
68
+ apsrmask |= 0x000f0000; /* APSR GE[3:0] */
69
+ }
70
+ xpsr_write(env, val, apsrmask);
71
}
72
break;
73
case 8: /* MSP */
74
diff --git a/target/arm/translate.c b/target/arm/translate.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/translate.c
77
+++ b/target/arm/translate.c
78
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
79
case 0: /* msr cpsr. */
80
if (arm_dc_feature(s, ARM_FEATURE_M)) {
81
tmp = load_reg(s, rn);
82
- addr = tcg_const_i32(insn & 0xff);
83
+ /* the constant is the mask and SYSm fields */
84
+ addr = tcg_const_i32(insn & 0xfff);
85
gen_helper_v7m_msr(cpu_env, addr, tmp);
86
tcg_temp_free_i32(addr);
87
tcg_temp_free_i32(tmp);
88
--
89
2.7.4
90
91
diff view generated by jsdifflib

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