[Qemu-devel] [PULL for-2.9 0/4] target-arm queue
[PULL v2 00/11] target-arm queue
1
Small target-arm queue for 2.9: just the patches
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
2
which fix bugs in our MRS/MSR decoding for M profile,
2
ethernet device failed 'make check' on big-endian hosts.
3
including a fix for a regression introduced in commit
4
58117c9bb429cd.
5
3
6
thanks
7
-- PMM
4
-- PMM
8
5
9
The following changes since commit 00e7c07b06d004cf54b19724f82afde8a7a37f37:
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
10
7
11
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170320' into staging (2017-03-20 10:51:30 +0000)
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
12
9
13
are available in the git repository at:
10
are available in the Git repository at:
14
11
15
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170320
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
16
13
17
for you to fetch changes up to b28b3377d7e9ba35611d454d5a63ef50cab1f8c5:
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
18
15
19
arm: Fix APSR writes via M profile MSR (2017-03-20 12:41:44 +0000)
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
20
17
21
----------------------------------------------------------------
18
----------------------------------------------------------------
22
target-arm queue:
19
target-arm queue:
23
* fix MSR/MRS decoding for M profile CPUs
20
* Correctly initialize MDCR_EL2.HPMN
21
* versal: Use nr_apu_cpus in favor of hard coding 2
22
* accel/tcg: Add URL of clang bug to comment about our workaround
23
* Add support for FEAT_DIT, Data Independent Timing
24
* Remove GPIO from unimplemented NPCM7XX
25
* Fix SCR RES1 handling
26
* Don't migrate CPUARMState.features
24
27
25
----------------------------------------------------------------
28
----------------------------------------------------------------
26
Peter Maydell (4):
29
Aaron Lindsay (1):
27
arm: HVC and SMC encodings don't exist for M profile
30
target/arm: Don't migrate CPUARMState.features
28
arm: Don't decode MRS(banked) or MSR(banked) for M profile
29
arm: Enforce should-be-1 bits in MRS decoding
30
arm: Fix APSR writes via M profile MSR
31
31
32
target/arm/helper.c | 26 ++++++++++++++++++++++----
32
Daniel Müller (1):
33
target/arm/translate.c | 26 +++++++++++++++++++++++---
33
target/arm: Correctly initialize MDCR_EL2.HPMN
34
2 files changed, 45 insertions(+), 7 deletions(-)
35
34
35
Edgar E. Iglesias (1):
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
37
38
Hao Wu (1):
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
40
41
Mike Nawrocki (1):
42
target/arm: Fix SCR RES1 handling
43
44
Peter Maydell (2):
45
arm: Update infocenter.arm.com URLs
46
accel/tcg: Add URL of clang bug to comment about our workaround
47
48
Rebecca Cran (4):
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
53
54
include/hw/dma/pl080.h | 7 ++--
55
include/hw/misc/arm_integrator_debug.h | 2 +-
56
include/hw/ssi/pl022.h | 5 ++-
57
target/arm/cpu.h | 17 ++++++++
58
target/arm/internals.h | 6 +++
59
accel/tcg/cpu-exec.c | 25 +++++++++---
60
hw/arm/aspeed_ast2600.c | 2 +-
61
hw/arm/musca.c | 4 +-
62
hw/arm/npcm7xx.c | 8 ----
63
hw/arm/xlnx-versal.c | 4 +-
64
hw/misc/arm_integrator_debug.c | 2 +-
65
hw/timer/arm_timer.c | 7 ++--
66
target/arm/cpu.c | 4 ++
67
target/arm/cpu64.c | 5 +++
68
target/arm/helper-a64.c | 27 +++++++++++--
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
70
target/arm/machine.c | 2 +-
71
target/arm/op_helper.c | 9 +----
72
target/arm/translate-a64.c | 12 ++++++
73
19 files changed, 164 insertions(+), 55 deletions(-)
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/4] arm: HVC and SMC encodings don't exist for M profile
Deleted patch
1
M profile doesn't have the HVC or SMC encodings, so make them always
2
UNDEF rather than generating calls to helper functions that assume
3
A/R profile.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1487616072-9226-2-git-send-email-peter.maydell@linaro.org
8
---
9
target/arm/translate.c | 3 +++
10
1 file changed, 3 insertions(+)
11
12
diff --git a/target/arm/translate.c b/target/arm/translate.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate.c
15
+++ b/target/arm/translate.c
16
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
17
goto illegal_op;
18
19
if (insn & (1 << 26)) {
20
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
21
+ goto illegal_op;
22
+ }
23
if (!(insn & (1 << 20))) {
24
/* Hypervisor call (v7) */
25
int imm16 = extract32(insn, 16, 4) << 12
26
--
27
2.7.4
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/4] arm: Don't decode MRS(banked) or MSR(banked) for M profile
Deleted patch
1
M profile doesn't have the MSR(banked) and MRS(banked) instructions
2
and uses the encodings for different kinds of M-profile MRS/MSR.
3
Guard the relevant bits of the decode logic to make sure we don't
4
accidentally fall into them by accident on M-profile.
5
1
6
(The bit being checked for this (bit 5) is part of the SYSm field on
7
M-profile, but since no currently allocated system registers have
8
encodings with bit 5 of SYSm set, this hasn't been a problem in
9
practice.)
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 1487616072-9226-3-git-send-email-peter.maydell@linaro.org
14
---
15
target/arm/translate.c | 6 ++++--
16
1 file changed, 4 insertions(+), 2 deletions(-)
17
18
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate.c
21
+++ b/target/arm/translate.c
22
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
23
gen_exception_return(s, tmp);
24
break;
25
case 6: /* MRS */
26
- if (extract32(insn, 5, 1)) {
27
+ if (extract32(insn, 5, 1) &&
28
+ !arm_dc_feature(s, ARM_FEATURE_M)) {
29
/* MRS (banked) */
30
int sysm = extract32(insn, 16, 4) |
31
(extract32(insn, 4, 1) << 4);
32
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
33
store_reg(s, rd, tmp);
34
break;
35
case 7: /* MRS */
36
- if (extract32(insn, 5, 1)) {
37
+ if (extract32(insn, 5, 1) &&
38
+ !arm_dc_feature(s, ARM_FEATURE_M)) {
39
/* MRS (banked) */
40
int sysm = extract32(insn, 16, 4) |
41
(extract32(insn, 4, 1) << 4);
42
--
43
2.7.4
44
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/4] arm: Enforce should-be-1 bits in MRS decoding
Deleted patch
1
The MRS instruction requires that bits [19..16] are all 1s, and for
2
A/R profile also that bits [7..0] are all 0s. At this point in the
3
decode tree we have checked all of the rest of the instruction but
4
were allowing these to be any value. If these bits are not set then
5
the result is architecturally UNPREDICTABLE, but choosing to UNDEF is
6
more helpful to the user and avoids unexpected odd behaviour if the
7
encodings are used for some purpose in future architecture versions.
8
1
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 1487616072-9226-4-git-send-email-peter.maydell@linaro.org
12
---
13
target/arm/translate.c | 14 ++++++++++++++
14
1 file changed, 14 insertions(+)
15
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate.c
19
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
21
break;
22
}
23
24
+ if (extract32(insn, 16, 4) != 0xf) {
25
+ goto illegal_op;
26
+ }
27
+ if (!arm_dc_feature(s, ARM_FEATURE_M) &&
28
+ extract32(insn, 0, 8) != 0) {
29
+ goto illegal_op;
30
+ }
31
+
32
/* mrs cpsr */
33
tmp = tcg_temp_new_i32();
34
if (arm_dc_feature(s, ARM_FEATURE_M)) {
35
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
36
if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
37
goto illegal_op;
38
}
39
+
40
+ if (extract32(insn, 16, 4) != 0xf ||
41
+ extract32(insn, 0, 8) != 0) {
42
+ goto illegal_op;
43
+ }
44
+
45
tmp = load_cpu_field(spsr);
46
store_reg(s, rd, tmp);
47
break;
48
--
49
2.7.4
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/4] arm: Fix APSR writes via M profile MSR
Deleted patch
1
Our implementation of writes to the APSR for M-profile via the MSR
2
instruction was badly broken.
3
1
4
First and worst, we had the sense wrong on the test of bit 2 of the
5
SYSm field -- this is supposed to request an APSR write if bit 2 is 0
6
but we were doing it if bit 2 was 1. This bug was introduced in
7
commit 58117c9bb429cd, so hasn't been in a QEMU release.
8
9
Secondly, the choice of exactly which parts of APSR should be written
10
is defined by bits in the 'mask' field. We were not passing these
11
through from instruction decode, making it impossible to check them
12
in the helper.
13
14
Pass the mask bits through from the instruction decode to the helper
15
function and process them appropriately; fix the wrong sense of the
16
SYSm bit 2 check.
17
18
Invalid mask values and invalid combinations of mask and register
19
number are UNPREDICTABLE; we choose to treat them as if the mask
20
values were valid.
21
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Message-id: 1487616072-9226-5-git-send-email-peter.maydell@linaro.org
24
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
25
---
26
target/arm/helper.c | 26 ++++++++++++++++++++++----
27
target/arm/translate.c | 3 ++-
28
2 files changed, 24 insertions(+), 5 deletions(-)
29
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
35
}
36
}
37
38
-void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
39
-{
40
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
41
+{
42
+ /* We're passed bits [11..0] of the instruction; extract
43
+ * SYSm and the mask bits.
44
+ * Invalid combinations of SYSm and mask are UNPREDICTABLE;
45
+ * we choose to treat them as if the mask bits were valid.
46
+ * NB that the pseudocode 'mask' variable is bits [11..10],
47
+ * whereas ours is [11..8].
48
+ */
49
+ uint32_t mask = extract32(maskreg, 8, 4);
50
+ uint32_t reg = extract32(maskreg, 0, 8);
51
+
52
if (arm_current_el(env) == 0 && reg > 7) {
53
/* only xPSR sub-fields may be written by unprivileged */
54
return;
55
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
56
switch (reg) {
57
case 0 ... 7: /* xPSR sub-fields */
58
/* only APSR is actually writable */
59
- if (reg & 4) {
60
- xpsr_write(env, val, 0xf8000000); /* APSR */
61
+ if (!(reg & 4)) {
62
+ uint32_t apsrmask = 0;
63
+
64
+ if (mask & 8) {
65
+ apsrmask |= 0xf8000000; /* APSR NZCVQ */
66
+ }
67
+ if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
68
+ apsrmask |= 0x000f0000; /* APSR GE[3:0] */
69
+ }
70
+ xpsr_write(env, val, apsrmask);
71
}
72
break;
73
case 8: /* MSP */
74
diff --git a/target/arm/translate.c b/target/arm/translate.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/translate.c
77
+++ b/target/arm/translate.c
78
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
79
case 0: /* msr cpsr. */
80
if (arm_dc_feature(s, ARM_FEATURE_M)) {
81
tmp = load_reg(s, rn);
82
- addr = tcg_const_i32(insn & 0xff);
83
+ /* the constant is the mask and SYSm fields */
84
+ addr = tcg_const_i32(insn & 0xfff);
85
gen_helper_v7m_msr(cpu_env, addr, tmp);
86
tcg_temp_free_i32(addr);
87
tcg_temp_free_i32(tmp);
88
--
89
2.7.4
90
91
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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