[Qemu-devel] [PULL 0/2] target-arm queue
[PULL 0/2] target-arm queue
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Couple of minor patches to sneak in before rc0. The PSCI return
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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values fix is the most important one.
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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thanks
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-- PMM
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-- PMM
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The following changes since commit 94b5d57d2f5a3c849cecd65e424bb6f50b998df9:
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging (2017-03-14 10:13:19 +0000)
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170314
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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for you to fetch changes up to d5affb0d8677e1a8a8fe03fa25005b669e7cdc02:
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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target/arm/arm-powerctl: Fix psci info return values (2017-03-14 11:28:54 +0000)
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm: Fix bug where we weren't initializing
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* arm-powerctl: Fix psci info return values
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guarded bit state when combining S1/S2 attrs
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* implement armv8 PMUSERENR (user-mode enable bits)
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Baumann (1):
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Richard Henderson (2):
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target/arm: implement armv8 PMUSERENR (user-mode enable bits)
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target/arm: PTE bit GP only applies to stage1
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target/arm: Copy guarded bit in combine_cacheattrs
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Andrew Jones (1):
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target/arm/ptw.c | 11 ++++++-----
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target/arm/arm-powerctl: Fix psci info return values
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1 file changed, 6 insertions(+), 5 deletions(-)
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target/arm/cpu.h | 4 +--
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target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
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2 files changed, 73 insertions(+), 10 deletions(-)
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diff view generated by jsdifflib
[Qemu-devel] [PULL 2/2] target/arm/arm-powerctl: Fix psci info return values
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
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From: Andrew Jones <drjones@redhat.com>
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From: Richard Henderson <richard.henderson@linaro.org>
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The power state spec section 5.1.5 AFFINITY_INFO defines the
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Only perform the extract of GP during the stage1 walk.
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affinity info return values as
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0 ON
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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1 OFF
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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2 ON_PENDING
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I grepped QEMU for power_state to ensure that no assumptions
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of OFF=0 were being made.
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Signed-off-by: Andrew Jones <drjones@redhat.com>
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Message-id: 20170303123232.4967-1-drjones@redhat.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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---
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target/arm/cpu.h | 4 ++--
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 2 insertions(+), 2 deletions(-)
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1 file changed, 5 insertions(+), 5 deletions(-)
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13
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/cpu.h
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--- a/target/arm/ptw.c
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+++ b/target/arm/cpu.h
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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/* These values map onto the return values for
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result->f.attrs.secure = false;
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* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
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}
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typedef enum ARMPSCIState {
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- PSCI_OFF = 0,
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- PSCI_ON = 1,
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ PSCI_ON = 0,
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ PSCI_OFF = 1,
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- }
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PSCI_ON_PENDING = 2
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-
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} ARMPSCIState;
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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--
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2.7.4
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2.34.1
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diff view generated by jsdifflib
[Qemu-devel] [PULL 1/2] target/arm: implement armv8 PMUSERENR (user-mode enable bits)
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
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From: Andrew Baumann <Andrew.Baumann@microsoft.com>
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From: Richard Henderson <richard.henderson@linaro.org>
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In armv8, this register implements more than a single bit, with
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The guarded bit comes from the stage1 walk.
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fine-grained enables for read access to event counters, cycles
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counters, and write access to the software increment. This change
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implements those checks using custom access functions for the relevant
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registers.
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Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
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Fixes: Coverity CID 1507929
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Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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[PMM: move a couple of access functions to be only compiled
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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ifndef CONFIG_USER_ONLY to avoid compiler warnings]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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---
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target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
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target/arm/ptw.c | 1 +
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1 file changed, 71 insertions(+), 8 deletions(-)
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/helper.c
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--- a/target/arm/ptw.c
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+++ b/target/arm/helper.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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*/
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int el = arm_current_el(env);
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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- if (el == 0 && !env->cp15.c9_pmuserenr) {
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+ ret.guarded = s1.guarded;
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+ if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
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return CP_ACCESS_TRAP;
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if (s1.attrs == 0xf0) {
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}
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tagged = true;
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if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
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@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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+static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* ER: event counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
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+ && isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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+static CPAccessResult pmreg_access_swinc(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* SW: software increment write trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
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+ && !isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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#ifndef CONFIG_USER_ONLY
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+static CPAccessResult pmreg_access_selr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* ER: event counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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+static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* CR: cycle counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
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+ && isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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static inline bool arm_ccnt_enabled(CPUARMState *env)
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{
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/* This does not support checking PMCCFILTR_EL0 register */
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@@ -XXX,XX +XXX,XX @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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- env->cp15.c9_pmuserenr = value & 1;
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+ if (arm_feature(env, ARM_FEATURE_V8)) {
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+ env->cp15.c9_pmuserenr = value & 0xf;
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+ } else {
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+ env->cp15.c9_pmuserenr = value & 1;
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+ }
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}
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static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.raw_writefn = raw_write },
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/* Unimplemented so WI. */
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{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
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- .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
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+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
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#ifndef CONFIG_USER_ONLY
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{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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.access = PL0_RW, .type = ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
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- .accessfn = pmreg_access, .writefn = pmselr_write,
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+ .accessfn = pmreg_access_selr, .writefn = pmselr_write,
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.raw_writefn = raw_write},
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{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
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- .access = PL0_RW, .accessfn = pmreg_access,
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+ .access = PL0_RW, .accessfn = pmreg_access_selr,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
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.writefn = pmselr_write, .raw_writefn = raw_write, },
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{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write32,
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- .accessfn = pmreg_access },
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+ .accessfn = pmreg_access_ccntr },
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{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
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- .access = PL0_RW, .accessfn = pmreg_access,
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+ .access = PL0_RW, .accessfn = pmreg_access_ccntr,
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.type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write, },
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#endif
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@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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/* Unimplemented, RAZ/WI. */
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{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
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- .accessfn = pmreg_access },
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+ .accessfn = pmreg_access_xevcntr },
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{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
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.access = PL0_R | PL1_RW, .accessfn = access_tpm,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
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--
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--
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2.7.4
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2.34.1
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diff view generated by jsdifflib

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