[Qemu-devel] [PULL 0/2] target-arm queue
[PULL 0/1] target-arm queue
1
Couple of minor patches to sneak in before rc0. The PSCI return
1
The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
2
values fix is the most important one.
3
2
4
-- PMM
3
Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
5
4
6
The following changes since commit 94b5d57d2f5a3c849cecd65e424bb6f50b998df9:
5
are available in the Git repository at:
7
6
8
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging (2017-03-14 10:13:19 +0000)
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
9
8
10
are available in the git repository at:
9
for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
11
10
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170314
11
target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
13
14
for you to fetch changes up to d5affb0d8677e1a8a8fe03fa25005b669e7cdc02:
15
16
target/arm/arm-powerctl: Fix psci info return values (2017-03-14 11:28:54 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* arm-powerctl: Fix psci info return values
15
* fix part of the "TCG-disabled builds are broken" issue
21
* implement armv8 PMUSERENR (user-mode enable bits)
22
16
23
----------------------------------------------------------------
17
----------------------------------------------------------------
24
Andrew Baumann (1):
18
Philippe Mathieu-Daudé (1):
25
target/arm: implement armv8 PMUSERENR (user-mode enable bits)
19
target/arm/gdbstub: Only advertise M-profile features if TCG available
26
20
27
Andrew Jones (1):
21
target/arm/gdbstub.c | 5 +++--
28
target/arm/arm-powerctl: Fix psci info return values
22
1 file changed, 3 insertions(+), 2 deletions(-)
29
23
30
target/arm/cpu.h | 4 +--
31
target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
32
2 files changed, 73 insertions(+), 10 deletions(-)
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/2] target/arm: implement armv8 PMUSERENR (user-mode enable bits)
Deleted patch
1
From: Andrew Baumann <Andrew.Baumann@microsoft.com>
2
1
3
In armv8, this register implements more than a single bit, with
4
fine-grained enables for read access to event counters, cycles
5
counters, and write access to the software increment. This change
6
implements those checks using custom access functions for the relevant
7
registers.
8
9
Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
10
Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
[PMM: move a couple of access functions to be only compiled
13
ifndef CONFIG_USER_ONLY to avoid compiler warnings]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
17
1 file changed, 71 insertions(+), 8 deletions(-)
18
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
22
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
24
*/
25
int el = arm_current_el(env);
26
27
- if (el == 0 && !env->cp15.c9_pmuserenr) {
28
+ if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
29
return CP_ACCESS_TRAP;
30
}
31
if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
33
return CP_ACCESS_OK;
34
}
35
36
+static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
37
+ const ARMCPRegInfo *ri,
38
+ bool isread)
39
+{
40
+ /* ER: event counter read trap control */
41
+ if (arm_feature(env, ARM_FEATURE_V8)
42
+ && arm_current_el(env) == 0
43
+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
44
+ && isread) {
45
+ return CP_ACCESS_OK;
46
+ }
47
+
48
+ return pmreg_access(env, ri, isread);
49
+}
50
+
51
+static CPAccessResult pmreg_access_swinc(CPUARMState *env,
52
+ const ARMCPRegInfo *ri,
53
+ bool isread)
54
+{
55
+ /* SW: software increment write trap control */
56
+ if (arm_feature(env, ARM_FEATURE_V8)
57
+ && arm_current_el(env) == 0
58
+ && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
59
+ && !isread) {
60
+ return CP_ACCESS_OK;
61
+ }
62
+
63
+ return pmreg_access(env, ri, isread);
64
+}
65
+
66
#ifndef CONFIG_USER_ONLY
67
68
+static CPAccessResult pmreg_access_selr(CPUARMState *env,
69
+ const ARMCPRegInfo *ri,
70
+ bool isread)
71
+{
72
+ /* ER: event counter read trap control */
73
+ if (arm_feature(env, ARM_FEATURE_V8)
74
+ && arm_current_el(env) == 0
75
+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
76
+ return CP_ACCESS_OK;
77
+ }
78
+
79
+ return pmreg_access(env, ri, isread);
80
+}
81
+
82
+static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
83
+ const ARMCPRegInfo *ri,
84
+ bool isread)
85
+{
86
+ /* CR: cycle counter read trap control */
87
+ if (arm_feature(env, ARM_FEATURE_V8)
88
+ && arm_current_el(env) == 0
89
+ && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
90
+ && isread) {
91
+ return CP_ACCESS_OK;
92
+ }
93
+
94
+ return pmreg_access(env, ri, isread);
95
+}
96
+
97
static inline bool arm_ccnt_enabled(CPUARMState *env)
98
{
99
/* This does not support checking PMCCFILTR_EL0 register */
100
@@ -XXX,XX +XXX,XX @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
101
static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
102
uint64_t value)
103
{
104
- env->cp15.c9_pmuserenr = value & 1;
105
+ if (arm_feature(env, ARM_FEATURE_V8)) {
106
+ env->cp15.c9_pmuserenr = value & 0xf;
107
+ } else {
108
+ env->cp15.c9_pmuserenr = value & 1;
109
+ }
110
}
111
112
static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
113
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
114
.raw_writefn = raw_write },
115
/* Unimplemented so WI. */
116
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
117
- .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
118
+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
119
#ifndef CONFIG_USER_ONLY
120
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
121
.access = PL0_RW, .type = ARM_CP_ALIAS,
122
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
123
- .accessfn = pmreg_access, .writefn = pmselr_write,
124
+ .accessfn = pmreg_access_selr, .writefn = pmselr_write,
125
.raw_writefn = raw_write},
126
{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
127
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
128
- .access = PL0_RW, .accessfn = pmreg_access,
129
+ .access = PL0_RW, .accessfn = pmreg_access_selr,
130
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
131
.writefn = pmselr_write, .raw_writefn = raw_write, },
132
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
133
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
134
.readfn = pmccntr_read, .writefn = pmccntr_write32,
135
- .accessfn = pmreg_access },
136
+ .accessfn = pmreg_access_ccntr },
137
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
138
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
139
- .access = PL0_RW, .accessfn = pmreg_access,
140
+ .access = PL0_RW, .accessfn = pmreg_access_ccntr,
141
.type = ARM_CP_IO,
142
.readfn = pmccntr_read, .writefn = pmccntr_write, },
143
#endif
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
145
/* Unimplemented, RAZ/WI. */
146
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
147
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
148
- .accessfn = pmreg_access },
149
+ .accessfn = pmreg_access_xevcntr },
150
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
151
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
152
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
153
--
154
2.7.4
155
156
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/2] target/arm/arm-powerctl: Fix psci info return values
[PULL 1/1] target/arm/gdbstub: Only advertise M-profile features if TCG available
1
From: Andrew Jones <drjones@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
The power state spec section 5.1.5 AFFINITY_INFO defines the
3
Cortex-M profile is only emulable from TCG accelerator. Restrict
4
affinity info return values as
4
the GDBstub features to its availability in order to avoid a link
5
error when TCG is not enabled:
5
6
6
0 ON
7
Undefined symbols for architecture arm64:
7
1 OFF
8
"_arm_v7m_get_sp_ptr", referenced from:
8
2 ON_PENDING
9
_m_sysreg_get in target_arm_gdbstub.c.o
10
"_arm_v7m_mrs_control", referenced from:
11
_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
12
ld: symbol(s) not found for architecture arm64
13
clang: error: linker command failed with exit code 1 (use -v to see invocation)
9
14
10
I grepped QEMU for power_state to ensure that no assumptions
15
Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
11
of OFF=0 were being made.
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Andrew Jones <drjones@redhat.com>
18
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20170303123232.4967-1-drjones@redhat.com
19
Message-id: 20230322142902.69511-3-philmd@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
[PMM: add #include since I cherry-picked this patch from the series]
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
22
---
18
target/arm/cpu.h | 4 ++--
23
target/arm/gdbstub.c | 5 +++--
19
1 file changed, 2 insertions(+), 2 deletions(-)
24
1 file changed, 3 insertions(+), 2 deletions(-)
20
25
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
26
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
22
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
28
--- a/target/arm/gdbstub.c
24
+++ b/target/arm/cpu.h
29
+++ b/target/arm/gdbstub.c
25
@@ -XXX,XX +XXX,XX @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
30
@@ -XXX,XX +XXX,XX @@
26
/* These values map onto the return values for
31
#include "cpu.h"
27
* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
32
#include "exec/gdbstub.h"
28
typedef enum ARMPSCIState {
33
#include "gdbstub/helpers.h"
29
- PSCI_OFF = 0,
34
+#include "sysemu/tcg.h"
30
- PSCI_ON = 1,
35
#include "internals.h"
31
+ PSCI_ON = 0,
36
#include "cpregs.h"
32
+ PSCI_OFF = 1,
37
33
PSCI_ON_PENDING = 2
38
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
34
} ARMPSCIState;
39
2, "arm-vfp-sysregs.xml", 0);
35
40
}
41
}
42
- if (cpu_isar_feature(aa32_mve, cpu)) {
43
+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
44
gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
45
1, "arm-m-profile-mve.xml", 0);
46
}
47
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
48
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
49
"system-registers.xml", 0);
50
51
- if (arm_feature(env, ARM_FEATURE_M)) {
52
+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
53
gdb_register_coprocessor(cs,
54
arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
55
arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
36
--
56
--
37
2.7.4
57
2.34.1
38
58
39
59
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.